HV7351 [MICROCHIP]
8-Channel, ±70V, 3A Programmable High-Voltage;
| 型号： | HV7351 |
| 厂家： | 
MICROCHIP |
| 描述： | 8-Channel, ±70V, 3A Programmable High-Voltage |
| 文件： | 总26页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV7351
8-Channel, ±70V, 3A Programmable High-Voltage
Ultrasound-Transmit Beamformer
Features
General Description
• Eight Channels with Return-to-Zero (RTZ)
• Up to ±70V Output Voltage
The HV7351 device is an 8-channel programmable
high-voltage ultrasound-transmit beamformer. Each
channel is capable of swinging up to ±70V with an
active discharge back to 0V. The outputs can source
and sink up to 3.0A to achieve fast output rise and fall
times. The active discharge is also capable of sourcing
and sinking 3.0A for a fast return to ground. The topol-
ogy of the HV7351 will significantly reduce the number
of I/O logic control lines needed.
• ±3.0A Output Current
• Stores up to Four Different Patterns
• Independent Programmable Delays
• 80-lead Single 11 x 11 mm VQFN Package
Applications
Each pulser has four associated 64-bit shift registers
for storing predetermined transmit patterns and a 10-bit
delay counter for controlling the transmit time. One of
four arbitrary patterns can be transmitted with adjust-
able delay, depending on the data loaded into these
shift registers and the delay counter. The delay counter
can be clocked up to 200 MHz, allowing incremental
delays down to 5 ns.
• Medical Ultrasound Imaging
• NDT, Non-Destructive Testing
• Arbitrary Pattern Generator
• High-Speed PIN Diode Driver
Typical Application Circuit
Array
Probe
tDELAY1
tDELAY2
tDELAY3
Tx1
E1
E2
E3
HV7351
8-channel
U1
Tx2
Tx3
HV7351
8-channel
U2
TRIG
tDELAY127
Tx127
Tx128
HV7351
8-channel
U16
E127
E128
tDELAY128
TRIG
2015 Microchip Technology Inc.
DS20005412A-page 1
HV7351
Package Types (Top View)
HV7351
11 x 11 VQFN*
1
60 VNN
AVDD
VNF
59
DIN2
CS2
2
3
4
5
58 DGND
SIZE
INV
57
56
VPP
VPF
CW
DOUT2
EN
6
55 PGND
54
7
PVSS
8
53 PGND
9
PVDD
52
SCK
81
VSUB
DVDD
10
DGND
51
DGND
TRIG
TCK
TCK
VLL
11
50 DVDD
PVDD
49
12
13
14
15
PGND
48
PVSS
47
PGND
46
VPF
45
CS1
DOUT1
A0
16
17
18
19
20
44 VPP
DGND
VNF
43
42
A1
41 VNN
DIN1
* Includes Exposed Thermal Pad (EP); see Table 2-1.
DS20005412A-page 2
2015 Microchip Technology Inc.
HV7351
Block Diagram
VLL
AVDD
DVDD
EN
VPP
VPP
SIZE
CS1
SCK
N-Ch. Registers
P-Ch. Registers
16/32-bit Register
Pattern 1
Linear
16/32-bit Register
Pattern 1
VPF
Regulator
VPF
DIN1
DOUT1
VRN
16/32-bit Register
Pattern 2
16/32-bit Register
Pattern 2
VRN
16/32-bit Register
Pattern 3
16/32-bit Register
Pattern 3
A0
A1
VRP
VRP
16/32-bit Register
Pattern 4
16/32-bit Register
Pattern 4
Linear
VNF
Regulator
VNF
VNN
VNN
DIN2
DOUT2
8 10-bit Registers
for Delay Counters
6-bit for
Divide by N
CS2
VPP
CW
INV
CW
fCW
VPF
VNF
TX1
Divide
by 2
EN
10-bit Delay
Counter
EN
TRIG
6-bit Counter
Divide by N
N = 1 to 64
Control
Logic
INV
VNN
16/32 bit
Serial
EN/LD
CW
PIN
Shift Reg.
CLK
PGND
INV
PVSS
PVDD
16/32 bit
Serial
EN/LD
CW
NIN
Shift Reg.
CLK
PGND
PVDD
RTZ GATE Driver
Supply Voltages
PVSS
VPP
CW
fCW
Divide
by 2
EN
10-bit Delay
Counter
EN
VPF
VNF
TX8
VNN
6-bit Counter
Divide by N
N = 1 to 64
Control
Logic
INV
16/32 bit
Serial
EN/LD
CW
PIN
Shift Reg.
CLK
-
TCK
TCK
PGND
INV
+
V
LL to VDD
16/32 bit
Serial
EN/LD
CW
PVSS
PVDD
NIN
Translator
Shift Reg.
CLK
DGND
AGND
VSUB
PGND
2015 Microchip Technology Inc.
DS20005412A-page 3
HV7351
NOTES:
DS20005412A-page 4
2015 Microchip Technology Inc.
HV7351
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Positive logic supply (VLL)............................................................................................................................ -0.5V to 5.5V
Positive logic supply voltage (DVDD)............................................................................................................ -0.5V to 5.5V
Positive gate drive supply voltage (PVDD) ................................................................................................... -0.5V to 5.5V
Positive analog supply voltage (AVDD)......................................................................................................... -0.5V to 5.5V
Negative gate drive supply voltage (PVSS) ................................................................................................ +0.5V to -5.5V
High-voltage positive supply voltage (VPP) ................................................................................................. -0.5V to +80V
High-voltage negative supply voltage (VNN) ............................................................................................... +0.5V to -80V
Differential high voltage supply (VPP - VNN)............................................................................................................+160V
Positive floating supply voltage (VPF) .................................................................................................. VPP – 6.0V to VPP
Negative floating supply voltage (VNF).................................................................................................VNN to VNN + 6.0V
Positive supply for VNF regulator (VRP)............................................................................................................. 0V to 15V
Negative supply for VPF regulator (VRN).......................................................................................................... 0V to -15V
Operating temperature ...........................................................................................................................-40°C to +125°C
Storage temperature ...............................................................................................................................-65°C to +150°C
ESD Rating All Pins ..............................................................................................................................................0.75 kV
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods
may affect device reliability.
TABLE 1-1:
OPERATING SUPPLY VOLTAGES
Electrical Specifications: Unless otherwise specified: TA = +25°C. Boldface specifications apply over the TA range
of -20 to +85°C.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Note 1
Positive High Voltage Supply
Negative High Voltage Supply
Logic Interface Voltage
VPP
VNN
VLL
3.0
-70
—
—
70
-3.0
3.6
V
V
V
V
2.85
4.75
3.30
5.00
Low-Voltage Positive Analog
Supply Voltage
AVDD
5.25
Low-Voltage Positive Digital
Supply Voltage
DVDD
PVDD
PVSS
VRP
4.75
4.75
-5.25
4.75
-12
5.00
5.00
-5.00
—
5.25
5.25
-4.75
12
V
V
V
V
V
Low-Voltage Positive Gate Drive
Supply Voltage
Low-Voltage Negative Gate
Drive Supply Voltage
Low-Voltage Positive Supply
for VNF Regulator
Low-Voltage Negative Supply
for VPF Regulator
VRN
—
-4.75
Reference Voltage Logic Trip
Point for TCK Pin
TCK
0.4VLL
0.5VLL
—
0.6VLL
V
TCK/TCK Input Current
ITCK TCK
/I
—
±10
µA
ITCK = 0 to VLL,
TA = +25°C
(Note 1)
Note 1: Specification is obtained by characterization and is not 100% tested.
2015 Microchip Technology Inc.
DS20005412A-page 5
HV7351
TABLE 1-2:
REGULATOR OUTPUTS
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Positive Floating Gate
Drive Voltage
VPF
VPP - 5.25 VPP - 5.00 VPP - 4.00
V
4x1 µF ceramic capacitors
across VPF and VPP
Negative Floating Gate
Drive Voltage
VNF
VNN + 4.00 VNN + 5.00 VNN + 5.25
V
4x1 µF ceramic capacitors
across VNF and VNN
ELECTRICAL CHARACTERISTICS
Electrical Specifications: unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V,
PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
EN = Low,
V
LL Quiescent Current
IVLLQ
—
384
500
µA
all inputs are static
AVDD Quiescent Current
DVDD Quiescent Current
PVDD Quiescent Current
VRP Quiescent Current
IAVDDQ
IDVDDQ
IPVDDQ
IVRPQ
—
—
12
12
30
30
100
6
µA
µA
EN = Low,
all inputs are static
—
70
—
0.3
-0.01
-45
EN = Low,
all inputs are static
VRN Quiescent Current
IVRNQ
—
6
PVSS Quiescent Current
IPVSSQ
-85
—
µA
µA
EN = Low,
all inputs are static
VPP Quiescent Current
VNN Quiescent Current
IVPPQ
IVNNQ
IVLLEN
—
—
—
2.6
-1.6
390
6
6
EN = Low,
all inputs are static
VLL Enabled
Quiescent Current
500
µA
µA
EN = High,
all inputs are static
AVDD Enabled
Quiescent Current
IAVDDEN
IDVDDEN
IPVDDEN
IVRPEN
IVRNEN
IPVSSEN
IVPPEN
—
—
600
22
800
55
EN = High,
all inputs are static
DVDD Enabled
Quiescent Current
PVDD Enabled
Quiescent Current
—
44
100
650
—
µA
µA
EN = High,
all inputs are static
VRP Enabled
—
450
-350
-44
EN = High,
all inputs are static
Quiescent Current
VRN Enabled
Quiescent Current
-650
-100
—
PVSS Enabled
Quiescent Current
—
µA
µA
EN = High,
all inputs are static
VPP Enabled
370
-420
620
—
EN = High,
all inputs are static
Quiescent Current
VNN Enabled
IVNNEN
-620
Quiescent Current
VLL current at 80 MHz Clock
DVDD current at CW = 5 MHz
IVLLCW
IDVDDCW
IVPPCW
IVNNCW
—
—
—
—
500
25
—
—
—
—
µA
mA
mA
mA
VPP = +5.0V,
VNN = -5.0V,
EN = High,
CW = High,
80 MHz on TCK,
0.5VLL on TCK,
all 8 channels active at
5.0 MHz, no load
(Note 1)
VPP current at CW = 5 MHz
141
98
VNN current at CW = 5 MHz
Note 1: Specification is obtained by characterization and is not 100% tested.
DS20005412A-page 6
2015 Microchip Technology Inc.
HV7351
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V,
PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Transmit Clock
Frequency
fTCK
0
—
200
MHz
Serial Clock Frequency
fSCK
0
0
2
—
—
—
80
70
—
MHz No daisy chain
Daisy chained (Note 2)
Note 1
Set-up Time Data
into SCK
tSU-DIN
tH-DIN
ns
ns
Hold Time SCK
to Data In
2
2
—
—
—
—
Note 1
Note 2
Set-up Time CS1 Low
to SCK
tSU-CS1
ns
Set-up Time CS2 Low
to SCK
tSU-CS2
2
2
—
—
—
—
ns
ns
Note 2
Note 2
Set-up Time from TRIG
Fall to TCK Rise Edge
tSU-TRIG
TRIG Pulse Width
tW-TRIG
tLHDO
2 x TCK
—
9
—
12
10
12
10
—
—
Cycle Note 2
SCK to Data Out Low
to High Delay Time
3
ns
For DOUT1 (Note 1)
3
9
For DOUT2 (Note 1)
For DOUT1 (Note 1)
For DOUT2 (Note 1)
Note 2
SCK to Data Out High
to Low Delay Time
tHLDO
3
9
ns
3
tW-TRIG + 40
—
9
A1A0 Pulse Width
tWA1A0
—
20
ns
ns
Set-up Time A1A0 to
TRIG Rising Edge
tSUA1A0
Note 1
Hold Time A1A0 to
TRIG Falling Edge
tHA1A0
tEN-ON
—
—
20
1
—
—
ns
Device Enable Time
ms
1.0 µF capacitor on every
VPF and VNF pin (Note 1)
Device Disable Time
tEN-OFF
tr1
—
—
—
9
100
13
ns
ns
Note 1
Output Rise Time
from 0V to +HV
Load = 330 pF||2.5 k
Output Fall Time
from 0V to -HV
tf1
tr2
tf2
tr3
tf3
—
—
—
—
—
9
9
13
13
13
23
23
ns
ns
ns
ns
ns
Damping Output Rise
Time from -HV to 0V
Damping Output Fall
Time from +HV to 0V
9
Output Rise Time from
-HV to +HV
17
17
Output Fall Time from
+HV to -HV
CW Output Rise Time
CW Output Fall Time
trcw
tfcw
—
—
9
9
16
16
ns
ns
VPP = +5.0V,
VNN = -5.0V
Load = 330 pF||2.5 k
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Specification is for design guidance only.
2015 Microchip Technology Inc.
DS20005412A-page 7
HV7351
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V,
PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
No Load
Output Propagation
Delay Rise Time 1
tdr1
11
14
18
ns
Output Propagation
Delay Fall Time 1
tdf1
tdr2
11
12
11
12
11
10
14
15
15
15
15
13
18
19
18
19
18
17
ns
ns
ns
ns
ns
ns
Output Propagation
Delay Rise Time 2
Output Propagation
Delay Fall Time 2
tdf2
Output Propagation
Delay Rise Time 3
tdr3
Output Propagation
Delay Fall Time 3
tdf3
CW Output
tdcwlh
VPP = +5.0V,
VNN = -5.0V
No Load
Propagation Delay
Time from Low to High
CW Output
Propagation Delay
Time from High to Low
tdcwhl
10
—
—
14
17
—
—
ns
ns
ps
Delay Time Matching
tdcwhl
±0.7
P to N,
channel-to-channel
matching
Delay Jitter On Rise
or Fall
tJCW
LAT
13
VPP = +5.0V, VNN = -5.0V,
Load = 50Note 2
Latency
3.5
TCK Note 2
Output P-Channel MOSFET to VPP, CW = 0
Output
IOUT
2.2
3.2
—
A
Saturation Current
Output ON-Resistance
Output Capacitance
RON
—
—
4.2
62
—
—
IOUT = 100 mA
COSS
pF
VPP - VOUT = 25V,
f = 1.0 MHz (Note 2)
Output N-Channel MOSFET to VNN, CW = 0
Output
IOUT
2.2
3.2
—
A
Saturation Current
Output ON-Resistance
Output Capacitance
RON
—
—
2.4
50
—
—
IOUT = -100 mA
COSS
pF
VNN - VOUT = -25V,
f = 1.0 MHz (Note 2)
Output P-Channel MOSFET to VPP, CW = 1
Output
IOUT
1.2
1.5
—
A
Saturation Current
Output ON-Resistance
Output Capacitance
RON
—
—
8
—
—
IOUT = 100 mA
COSS
62
pF
VPP - VOUT = 25V,
f = 1.0 MHz (Note 2)
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Specification is for design guidance only.
DS20005412A-page 8
2015 Microchip Technology Inc.
HV7351
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V,
PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Output N-Channel MOSFET to VNN, CW = 1
Output
IOUT
1.2
1.5
—
A
Saturation Current
Output ON-Resistance
Output Capacitance
RON
—
—
6.6
50
—
—
IOUT = -100 mA
COSS
pF
VNN - VOUT = -25V,
f = 1.0 MHz (Note 2)
Damping P-Channel MOSFET to PGND
Output
IOUT
2.2
3.2
—
A
Saturation Current
Output ON-Resistance
Output capacitance
RON
—
—
4
—
—
IOUT = 100 mA
COSS
62
pF
VPP - VOUT = 25V,
f = 1.0 MHz (Note 2)
Damping N-Channel MOSFET to PGND
Output
IOUT
2.2
3.2
—
A
Saturation Current
Output ON-Resistance
Output Capacitance
RON
—
—
2.3
50
—
—
IOUT = -100 mA
COSS
pF
VNN - VOUT = -25V,
f = 1.0 MHz (Note 2)
Logic Inputs
Clock Input Current
ITCK
—
±1.0
—
—
µA
V
Voltage 0 to VLL
Clock Input
VIH_TCK
VTCK + 0.15
VLL
TCK = 0.5VLL (Note 2)
High Voltage
Clock Input
Low Voltage
VIL_TCK
VIH
0
—
—
—
—
—
—
—
—
VTCK - 0.15
V
V
Logic Input
High Voltage
0.8VLL
VLL
0.2VLL
1
For all logic inputs except
clock inputs
Logic Input
Low Voltage
VIL
0
V
Input Logic
High Current
IIH
—
µA
µA
V
Input Logic
Low Current
IIL
-1
—
Output Logic
Low Voltage
VOL
VOH
CIN
0
VLL - 0.7
—
0.7
IOUT = 0 to -10 mA
IOUT = 0 to 10 mA
Note 2
Output Logic
High Voltage
VLL
5.0
V
Input Logic
pF
Capacitance
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Specification is for design guidance only.
2015 Microchip Technology Inc.
DS20005412A-page 9
HV7351
TEMPERATURE SPECIFICATIONS
Electrical Specifications: unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V,
PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Operating Ambient Temperature Range
Storage Temperature Range
TA
TA
TJ
-40
-65
-40
—
—
—
+125
+150
+150
°C
°C
°C
Maximum Junction Temperature
Package Thermal Resistances
Thermal Resistance, 80L-11x11 VQFN
JA
—
14
—
°C/W
TABLE 1-3:
LOGIC TRUTH TABLE
Inputs
Outputs
Mode
Comments
EN
CW
INV
NIN
PIN
N-Ch. P-Ch. RTZ
Non-CW mode. Outputs
not inverted. Outputs are
controlled by data in the
shift registers
X
X
OFF
OFF
ON
Return-to-Zero (RTZ) is
activated when NIN and
PIN are both low. Output is
pulled to ground through a
series diode.
1
0
0
0
X
X
X
OFF
ON
ON
OFF
OFF
OFF Not inverted. Logic 1 in the
P-Channel register turns
on the output P-Channel
MOSFET.
1
1
1
0
0
0
0
0
X
0
1
1
1
0
1
OFF Not inverted. Logic 1 in the
N-Channel register turns
on the output N-Channel
MOSFET.
OFF
OFF Avoids cross overcurrent.
A logic 1 in both P- and N-
Channel registers will put
the output in a High Z state.
Non-CW mode. Outputs
are inverted. Outputs are
controlled by data in the
shift registers
X
X
ON
OFF
ON
OFF Transmit pattern is inverted
OFF
1
1
0
0
1
1
0
1
1
0
OFF
CW mode.
Output follows f
X
All 1
X
X
X
X
X
X
OFF
OFF
OFF If 10-bit counter reach all 1,
then the channel will be
turned OFF.
1
1
CW
Not
all 1
OFF/
ON
ON/
OFF
OFF The channel's output fol-
1
lows the f
signal. The
CW
shift registers for PIN and
NIN remain static to save
power.
Device Disabled
X
X
X
X
X
OFF
OFF
OFF High Z state
0
Legend: X = Don’t care.
DS20005412A-page 10
2015 Microchip Technology Inc.
HV7351
1.1
Timing Diagrams
TCK = 1.65V (0.5VLL
)
3.5 TCK cycles
3.3V
TCK
0V
3.3V
Internal CLK
(for N = 2)
0V
tSU-TRIG
3.3V
TRIG
0V
tWTRIG
tdr1
tdf2
+70V
90%
90%
tWTRIG needs to be at least
2 rising edges of TCK
Delay time set by
TX1 10-bit counter
tdf1
tdr2
10%
tr1
10%
tf2
0V
TX1
10%
10%
90%
tf1
90%
tr2
-70V
+70V
Delay time set by
TX2 10-bit counter
0V
TX2
Example with TX2 delay having
two TCK cycles more than TX1
-70V
FIGURE 1-1:
Timing Diagram of 3-Level, 1-Cycle Bipolar RTZ TX Pulse.
TCK = 1.65V (0.5VLL
)
3.5 TCK cycles
3.3V
TCK
0V
3.3V
Internal CLK
(for N = 2)
0V
tSU-TRIG
3.3V
TRIG
0V
tWTRIG
tdf3
tdr3
+70V
90%
90%
10%
tWTRIG needs to be at least
2 rising edges of TCK
Delay time set by
TX1 10-bit counter
0V
TX1
10%
-70V
tf3
tr3
+70V
0V
TX2
Delay time set by
TX2 10-bit counter
Example with TX2 delay having
one TCK cycle more than TX1
-70V
FIGURE 1-2:
Timing Diagram of 2-Level 2-Cycle Bipolar, non-RTZ TX Pulses with Damping.
2015 Microchip Technology Inc.
DS20005412A-page 11
HV7351
NOTES:
DS20005412A-page 12
2015 Microchip Technology Inc.
HV7351
2.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin
PIN FUNCTION TABLE
Symbol
Description
1
2
AVDD
DIN2
Positive analog supply voltage (+5.0V)
Serial data in for delay counters and frequency divider
Activates DIN2. Input logic high = off, input logic low = on.
3
4
5
6
CS2
SIZE
INV
Sets pattern width to either 16-bits or 32-bits. Logic low = 16-bits, logic high = 32-bits.
Inverts the TX output waveform. See Table 1-3 for details.
CW
Activates CW mode. Logic low = non-CW mode, logic high = CW mode.
See Table 1-3 for details.
7
DOUT2
EN
Data out for delay counters and frequency divider
Enables and disables device. Logic low = off, logic high = on.
Serial clock input for serial shift registers
Positive digital supply voltage (+5.0V)
Digital ground
8
9
10, 50
SCK
DVDD
DGND
TRIG
11, 43, 51, 58
12
Toggles all TX outputs to transmit. Needs to be high for two rising edges of TCK.
Delay counters will start on the rising edge of the TCK pin right after the falling edge of
the TRIG signal. See Section 1.1 “Timing Diagrams” for details.
13
14
TCK
TCK
The TCK and TCK pins can be driven by LVDS or SSTL types of output in a
differential manner. The TCK pin can be driven by LVCMOS single-ended output,
while setting the TCK to GND (or DC value of 0.4V to 0.6V). The logic trip point is on
the TCK rising edge and on the TCK falling edge, crossing in the differential manner.
In the single-ended case, the trip point is on the TCK rising edge.
15
VLL
Logic interface supply voltage (3.3V)
16
CS1
DOUT1
A0
Activates DIN1. Input logic high = off, input logic low = on
Data out for P-Channel and N-Channel pattern registers
Decoded to select 1 of 4 patterns to be loaded
17
18
19
A1
20
21
DIN1
VRN
Serial data in for P-Channel and N-Channel pattern registers
Negative supply for VPF regulator (-5.0V)
22, 49, 52, 79
PVDD
PGND
Positive gate drive supply voltage for RTZ output transistors (+5.0V)
Power ground path for RTZ output transistors
23, 24, 46, 48,
53, 55, 77, 78
25, 47, 54, 76
26, 45, 56, 75
PVSS
VPF
Negative gate drive supply voltage for RTZ output transistors (-5.0V)
Linear regulator output gate drive voltage for the P-Channel output transistors. A low
voltage 1.0 µF ceramic capacitor needs to be connected across every VPF and VPP
pins. There are four capacitors required in total.
27
NC
No connection
28, 42, 59, 73
VNF
Linear regulator output gate drive voltage for the N-Channel output transistors. A low
voltage 1.0 µF ceramic capacitor needs to be connected across every VNF to VNN
pins. There are four capacitors required in total.
29, 34, 35, 40,
41, 60, 61, 66,
67, 72
VNN
Negative high voltage supply (-3.0V to -70V)
30
TX1
VPP
Transmit pulser outputs for channel 1
31, 32, 37, 38,
44, 57, 63, 64,
69, 70
Positive high voltage supply (+3.0V to +70V)
2015 Microchip Technology Inc.
DS20005412A-page 13
HV7351
TABLE 2-1:
Pin
PIN FUNCTION TABLE (CONTINUED)
Symbol
Description
Transmit pulser outputs for channel 2
33
36
39
62
65
68
71
74
80
81
TX2
TX3
TX4
TX5
TX6
TX7
TX8
NC
Transmit pulser outputs for channel 3
Transmit pulser outputs for channel 4
Transmit pulser outputs for channel 5
Transmit pulser outputs for channel 6
Transmit pulser outputs for channel 7
Transmit pulser outputs for channel 8
No connection
VRP
VSUB
Positive supply for VNF regulator (+5.0V)
Exposed center pad must be externally connected to the ground (GND, 0V) on PCB.
(DGND).
DS20005412A-page 14
2015 Microchip Technology Inc.
HV7351
3.0
3.1
DEVICE DESCRIPTION
Loading Data into the Four 16/32
bit Pattern Registers
A detailed circuit diagram of the pattern registers is
shown in Figure 3-1. There are four programmable pat-
terns that can be stored. One of four patterns can be
selected via the two input logic decoder pins, A1 and
A0. Data can be loaded on the selected pattern. Each
pattern can be either 16- or 32-bits wide. The SIZE pin
determines whether they are 16- or 32-bits wide.
SIZE = H will set the pattern to be 32-bits wide while
SIZE = L will set it to 16-bits wide. DIN1 is the input
data for the register. When CS1 is high, data will not be
shifted in. Data is shifted in only when CS1 is low.
SIZE
SIZE
A1 A0 CS1
A1 A0 CS1
A1 A0 CS1
A1 A0 CS1
16-/32-bits
Shift Register
P-ch. Pattern 1
16-/32-bits
Shift Register
N-ch. Pattern 1
EN
DIN
A1 A0 CS1
SCK
SIZE
EN
16-/32-bits
Shift Register
P-ch. Pattern 2
16-/32-bits
Shift Register
N-ch. Pattern 2
CS1
A1
DIN
A1 A0 CS1
A1 A0 CS1
2 to 4
Decoder
SCK
DOUT1
Size
EN
A0
16-/32-bits
Shift Register
N-ch. Pattern 3
16-/32-bits
Shift Register
P-ch. Pattern 3
DIN
SCK
Size
EN
16/32 bits
Shift Register
P-ch. Pattern 4
16/32 bits
Shift Register
N-ch. Pattern 4
SCK
DIN
A1 A0 CS1
SCK
DIN1
FIGURE 3-1:
Pattern Register Circuit Diagram.
With SIZE = H, the circuit is effectively a 64-bit serial
shift register. The data first enters into the P-Channel
register and continues to be shifted though to the
N-Channel register. Data is clocked in during the rising
edge of the clock. There is no activity during the falling
edge of the clock. The DIN1 data enters into the S64 of
P-Channel register and exits the S1 of N-Channel
register from DOUT1. The SPI writing operation of the
waveform pattern registers are LSB first.
Data is shifted in during the rising edge of the clock. S1
is the first bit shifted in, entering the P-Channel register.
After 64 clock cycles, S1 will be located in the N-Chan-
nel register, as shown in Figure 3-2. It will also be
clocked out to DOUT1.
DIN1
32 bits for
P-ch Pattern 1
32 bits for
N-ch Pattern 1
DOUT1
SCK
32 bits for P-ch Pattern 1
32 bits for N-ch Pattern 1
EXAMPLE 3-1:
S64
S63
S34
S33
S32
S31
S2
S1
For:
SIZE
(SIZE
A1
=
=
=
=
High, 32-bits wide
Low, 16-bits wide)
FIGURE 3-2:
Waveform Pattern Register.
A0
= Low, Pattern 1 selected
CS1
Low, data can be shifted in
64-bit Serial Shift Register:
32 bits for the P-Channel
and
32 bits for the N-Channel
2015 Microchip Technology Inc.
DS20005412A-page 15
HV7351
A 2-to-4 decoder is provided to select which of the four
patterns is to be used for all of the outputs. Logic inputs
A1 and A0 determine which patterns are selected, fol-
lowing Table 3-1. Once A1 and A0 are set, a rising
edge on the trigger logic input pin will automatically
load the selected pattern to all of the outputs.
3.2
Loading Data into the Delay
Counters and the Divide-by-N
Counter
Each output channel (TX) has its own programmable
10-bit delay counter. For 8 channels, 80 bits are
needed. A 6-bit divide-by-N counter is also provided to
program the desired TX frequency. To program all the
individual delay counters and the divide-by-N counter,
an 86-bit serial shift register is provided. It uses the
same clock input that the pattern registers uses. DIN2
is the input data for this register. When CS2 is high,
data will not be shifted in. Data is shifted in only when
CS2 is low.
TABLE 3-1:
DECODER TRUTH TABLE
Logic Decoder Input
Pattern Selected
A1
A2
0
0
1
1
0
1
0
1
1
2
3
4
As shown in Figure 3-3, the data first enters into the
10-bit register for the TX8 delay counter and continues
to be shifted through to the 6-bit register for the
divide-by-N counter. Data is clocked in during the rising
edge of the clock. There is no activity during the falling
edge of the clock. The MSB bit in the 6-bit divide-by-N
register is clocked out into DOUT2 for cascading multi-
ple devices, if desired.
86-bit Serial Shift Register: 80 bits for the delay counters and 6 bits for the divide by N
6 bits
divide by N
DIN2
SCK
10 bits TX8 10 bits TX7 10 bits TX6 10 bits TX5 10 bits TX4 10 bits TX3 10 bits TX2 10 bits TX4
DOUT2
10 bits TX8 Delay Counter
10 bits TX7 Delay Counter
S70 S69 S68
6 bits divide by N
S86
S84 S83 S82 S81
S76 S75 S74
S6 S5 S4
S85
S80 S79 S78 S77
S73 S72 S71
S67
S3 S2 S1
MSB
LSB
MSB LSB
MSB
LSB
FIGURE 3-3:
Delay and Divide-by-N Registers.
3.3 10-Bit Delay Counter
The TCK and TCK pins are the input clock for the 10-bit
delay counter. The maximum capable clock frequency
is up to 200 MHz. The counter counts upward.
TABLE 3-2:
MSB
DELAY COUNTER
LSB
Delay Time
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1023 TCK cycles
1022 TCK cycles
1021 TCK cycles
1020 TCK cycles
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
3 TCK cycles
2 TCK cycles
1 TCK cycle
No trigger
DS20005412A-page 16
2015 Microchip Technology Inc.
HV7351
3.4
6-Bit Divide-by-N Counter
The TCK and TCK pins are the input clock for the 6-bit
divide-by-N counter. It generates the clock frequency
for the 16-/32-bit serial shift register for the output P-
and N-Channel patterns. Each clock cycle will set the
TX output to be either at VPP, VNN, ground or high-
impedance, depending on what was preprogrammed in
their corresponding registers.
TABLE 3-3:
MSB
6-BIT DIVIDE-BY-N COUNTER REGISTER
Output Shift Register Clock
LSB
Frequency
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
fTCK ÷ 64
fTCK ÷ 63
f
TCK ÷ 62
fTCK ÷ 61
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
fTCK ÷ 4
fTCK ÷ 3
fTCK ÷ 2
fTCK ÷ 1
2015 Microchip Technology Inc.
DS20005412A-page 17
HV7351
NOTES:
DS20005412A-page 18
2015 Microchip Technology Inc.
HV7351
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
80-Lead VQFN (11x11x1.0 mm)
Example
HV7351K6
1508256
Legend: XX...X Product Code or Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
2015 Microchip Technology Inc.
DS20005412A-page 19
HV7351
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
DS20005412A-page 20
2015 Microchip Technology Inc.
HV7351
APPENDIX A: REVISION HISTORY
Revision A (June 2015)
• Original Release of this Document.
2015 Microchip Technology Inc.
DS20005412A-page 21
HV7351
NOTES:
DS20005412A-page 22
2015 Microchip Technology Inc.
HV7351
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
XX
-X
Examples:
a) HV7351K6-G: Programmable High-Voltage
Package
Environmental
Ultrasound-Transmit Beamformer,
80LD 11x11 mm VQFN package
Device:
HV7351: Programmable High-Voltage, Ultrasound-Transmit
Beamformer
Package:
K6 =
Very Thin Plastic Quad Flat Pack, No Lead Package
– 11.00x11.00x1.0 mm Body, 0.50 mm Pitch,
80-Lead (VQFN)
Environmental:
G
=
Lead (Pb)-free/ROHS-compliant package
2015 Microchip Technology Inc.
DS20005412A-page 23
HV7351
NOTES:
DS20005412A-page 24
2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-402-6
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2015 Microchip Technology Inc.
DS20005412A-page 25
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01/27/15
DS20005412A-page 26
2015 Microchip Technology Inc.
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