KSZ8001SIS-TR_技术文档

KSZ8001L/S

1.8V, 3.3V 10/100BASE-T/TX/FX Physical Layer Transceiver

• Fully compliant to IEEE 802.3u standard

Features

• Supports auto-negotiation and manual selection

for 10/100Mbps speed and full / half-duplex mode

• Single chip 100BASE-TX/100BASE-FX/

10BASE-T physical layer solution

• Configurable through MII serial management port

or via external control pins

• 1.8V CMOS design, power consumption 250 mW

• Robust (130m+) operation over standard cables

• Programmable LED outputs for link, activity, full/

half duplex, collision and speed

• Supports Media Independent Interface (MII),

Reduced MII (RMII), and Serial MII (SMII)

• LinkMD^®feature to determine cable length and

diagnose faulty cables with +/- 2 m accuracy

• On-chip built-in analog front end filtering for both

100BASE-TX and 10BASE-T

• Supports back-to-back, 100BASE-FX to

100BASE-TX for media converter applications

• Supports HP MDI/MDI-X auto crossover

• Supports power down mode and power saving

mode

• Single 3.3V power supply with built-in 1.8V regu-

lator (‘L’ parts)

• MDC/MDIO to 12.5 MHz for rapid configuration

• Packages: 48-Pin LQFP, 48-Pin SSOP

Functional Diagram

4B/5B ENCODER

SCRAMBLER

PARALLEL/SERIAL

NRZ/NRZI

MLT3 ENCODER

TXD3

TXD2

TXD1

TXD0

TXER

TXC

10/100

PULSE

SHAPER

TX+

TX-

TRANSMITTER

PARALLEL/SERIAL

MANCHESTER ENCODER

TXEN

CRS

COL

MII/RMII/SMII

REGISTERS

AND

CONTROLLER

INTERFACE

ADAPTIVE EQ

RX+

RX-

BASELINE WANDER

CORRECTION

MLT3 DECODER

NRZI/NRZ

4B/5B DECODER

DESCRAMBLER

SERIAL/PARALLEL

CLOCK

RECOVERY

MDIO

MDC

RXD3

RXD2

RXD1

RXD0

RXER

RXDV

RXC

AUTO

NEGOTIATION

10BASE-T

RECEIVER

MANCHESTER DECODER

SERIAL/PARALLEL

POWER DOWN/

POWER SAVING

LINK

COL

FDX

SPD

LED

DRIVER

XI

PLL

XO

PWRDWN

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DS00003062A-page 1

KSZ8001L/S

TO OUR VALUED CUSTOMERS

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-

rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the

revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are

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DS00003062A-page 2

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KSZ8001L/S

Table of Contents

1.0 General Description ........................................................................................................................................................................ 4

2.0 Pin Description and Configuration .................................................................................................................................................. 5

3.0 Functional Overview ..................................................................................................................................................................... 12

4.0 Register Map ................................................................................................................................................................................. 27

5.0 Operational Characteristics ........................................................................................................................................................... 34

6.0 Timing Diagrams ........................................................................................................................................................................... 36

7.0 Package Information ..................................................................................................................................................................... 45

Appendix A: Data Sheet Revision History ........................................................................................................................................... 47

The Microchip Web Site ...................................................................................................................................................................... 48

Customer Change Notification Service ............................................................................................................................................... 48

Customer Support ............................................................................................................................................................................... 48

Product Identification System ............................................................................................................................................................. 49

 2009-2019 Microchip Technology Inc.

DS00003062A-page 3

KSZ8001L/S

1.0

GENERAL DESCRIPTION

The KSZ8001 is a 10BASE-T/100BASE-TX/100BASE-FX Physical Layer Transceiver, operating the core at 1.8 volts to

meet low voltage and low power requirements. The solution provides MII/RMII/SMII interfaces to transmit and receive

data. A unique mixed-signal design extends signaling distance while reducing power consumption.

HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover and

straight-through cables.

Featuring LinkMD^®cable diagnostics, which allows detection of common cabling plant problems such as open and short

circuits, the KSZ8001 represents a level of features and performance and is an ideal choice of physical layer transceiver

for 100BASE-TX/10BASE-T/100BASE-FX applications.

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KSZ8001L/S

2.0

2.1

PIN DESCRIPTION AND CONFIGURATION

Pin Diagram

FIGURE 2-1:

KSZ8001S - 48-PIN SSOP

Top View

SSOP 48

RST#

1

2

48

47

MDIO

MDC

VDDPLL

3

XI 46

RXD3/PHYAD1

RXD2/PHYAD2

4

XO 45

5

44

43

42

41

40

39

38

37

RXD1/PHYAD3

RXD0/PHYAD4

VDDIO

GND

NC

6

7

NC

8

GND

TX+

9

RXDV/PCS_LPBK

RXC

TX-

10

11

12

GND

RXER/ISO

VDDRCV

REXT

GND

KSZ8001S

GND

13

14

15

16

17

18

19

20

21

22

23

24

36

35

34

33

32

31

30

29

28

27

26

VDDC

TXER

GND

TXC/REF_CLK

FXSD/FXEN

TXEN

TXD0

RX+

RX-

TXD1

TXD2

TXD3

VDDRX

PD#

LED3/NWAYEN

LED2/DUPLEX

LED1/SPD100

LED0/TEST

COL/RMII

CRS/RMII_BTB

GND

VDDIO

INT#/PHYAD0

25

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KSZ8001L/S

FIGURE 2-2:

KSZ8001L - 48-PIN LQFP

1

2

36

GND

MDIO

Top View

LQFP 48

MDC

GND 35

RXD3/PHYAD1

3

34

FXSD/FXEN

4

33

RXD2/PHYAD2

RXD1/PHYAD3

RXD0/PHYAD4

RX+

5

RX- 32

VDDRX

6

31

30

KSZ8001L

7

VDDIO

GND

PD#

8

LED3/NWAYEN 29

9

28

RXDV/PCS_LPBK

RXC

LED2/DUPLEX

10

11

12

27

26

25

LED1/SPD100

RXER/ISO

GND

LED0/TEST

INT#/PHYAD0

2.2

Pin Description

Type

(Note 1)

Pin Number

Pin Name

Pin Function

MII Management (MIIM) Interface: Data I/O

1

2

3

MDIO

I/O

This pin requires an external 4.7K pull-up resistor.

MDC

I

MII Management (MIIM) Interface: Clock Input

This pin is synchronous to the MDIO data line.

MII Mode: Receive Data Output[3]²/

RXD3/

Ipd/O

PHYAD1

Configuration Mode: The pull-up/pull-down value is latched as PHY-

ADDR[1] during reset. See Section 2.3, "Strapping Options" for details.

4

5

RXD2/

PHYAD2

Ipd/O

MII Mode: MII Receive Data Output[2]²/

Configuration Mode: The pull-up/pull-down value is latched as PHY-

ADDR[2] during reset. See Strapping Options for details.

RXD1/

RXD[1]/

PHYAD3

MII Mode: Receive Data Output[1]²/

RMII Mode: Receive Data Output[1]³/

Configuration Mode: The pull-up/pull-down value is latched as PHY-

ADDR[3] during reset. See Strapping Options for details.

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KSZ8001L/S

Type

(Note 1)

Pin Number

Pin Name

Pin Function

6

RXD0/

RXD[0]/

RX

Ipd/O

MII Mode: Receive Data Output[0]²/

RMII Mode: Receive Data Output[0]³/

SMII Mode: Receive Data and Control⁴/

PHYAD4

Configuration Mode: The pull-up/pull-down value is latched as PHY-

ADDR[4] during reset. See Strapping Options for details.

7

8

9

VDDIO

GND

Pwr

Gnd

3.3V digital VDD

Ground

RXDV/

CRSDV/

PCS_LPBK

Ipd/O

MII Mode: Receive Data Valid Output /

RMII Mode: Carrier Sense/Receive Data Valid /

Configuration Mode: The pull-up/pull-down value is latched as pcs_lpbk

during reset. See Strapping Options for details.

10

11

RXC/

SMII_SE-

LECT

Ipd/O

MII Receive Clock Output

Operating at:

25 MHz = 100 Mbps

2.5 MHz = 10 Mbps

Configuration Mode: The pull-up/pull-down value is latched as SMII

during reset. See Strapping Options for details.

RXER/

RX_ER/

ISO

MII Mode: Receive Error Output /

RMII Mode: Receive Error /

Configuration Mode: The pull-up/pull-down value is latched as ISOLATE

during reset. See Strapping Options for details.

12

13

GND

Gnd

Pwr

Ground

VDDC

1.8V digital core VDD

VDD output

VDD input

:

KSZ8001L / KSZ8001SL

KSZ8001S

(See Section 3.11, "Circuit Design Reference for Power Supply" for

details)

14

15

TXER

Ipd

I/O

MII Transmit Error Input

TXC/ REF-

CLK/

CLOCK

MII Mode: MII Transmit Clock Output /

RMII Mode: 50 MHz Reference Clock Input /

SMII Mode: 125 MHz Synchronization Clock Input

16

17

TXEN

Ipd

MII Transmit Enable Input

TXD0/

TXD[0]/

TX

MII Mode: Transmit Data Input[0] /

RMII Mode: Transmit Data Input[0] /

SMII Mode: Transmit Data and Control

18

TXD1/

TXD[1]/

SYNC

Ipd

MII Mode: Transmit Data Input[1] /

RMII Mode: Transmit Data Input[1] /

SMII Mode: SYNC

19

20

21

TXD2

TXD3

Ipd

MII Transmit Data Input[2]

MII Transmit Data Input[3]

COL /

RMII_SE-

LECT

Ipd/O

MII Collision Detect Output

Configuration Mode: The pull-up/pull-down value is latched as RMII

select during reset. See Strapping Options for details.

22

CRS/

Ipd/O

MII Carrier Sense Output

RMII_BTB

Configuration Mode: The pull-up/pull-down value is latched as RMII

Loop-back during reset when RMII mode is selected. See Strapping

Options” for details.

23

24

GND

Gnd

Pwr

Ground

VDDIO

3.3V digital VDD

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DS00003062A-page 7

KSZ8001L/S

Type

(Note 1)

Pin Number

Pin Name

Pin Function

25

INT#/ PHY-

AD0

Ipu/O

Management Interface (MII) Interrupt Out.

Configuration Mode: Latched as PHYAD[0] during power up / reset. See

Strapping Options for details.

26

LED0/

TEST

Ipu/O

Programmable LED Output 0

Configuration Mode: The external pull down enable test mode and only

used for the factory test. Active Low. The LED0 pin is also programma-

ble via register 1eh.

LED mode = 00

Link/Act

No Link

Link

Pin State

LED Definition

H

L

-

Off

On

Activity

Toggle

LED mode = 01

Link

Pin State

LED Definition

No Link

Link

H

L

Off

On

LED mode = 10

10Mbps Link

No Link

Link

Pin State

LED Definition

H

L

Off

On

27

LED1 /

SPD100/

noFEF

Ipu/O

Programmable LED Output 1

Configuration Mode: Latched as SPEED (Register 0, bit 13) during

power up / reset. See Strapping Options for details. Active Low. The

LED1 pin is also programmable via register 1eh.

LED mode = 00

Speed

Pin State

LED Definition

10BT

H

L

Off

On

100BT

LED mode = 01

Speed

Pin State

LED Definition

10BT

H

L

Off

On

100BT

LED mode = 10

100Mbps Link

No Link

Pin State

LED Definition

H

L

Off

On

Link

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KSZ8001L/S

Type

(Note 1)

Pin Number

Pin Name

Pin Function

Programmable LED Output 2

28

LED2/

Ipu/O

DUPLEX

Configuration Mode: Latched as DUPLEX (register 0h, bit 8) during

power up / reset. See Strapping Options for details. Active Low. The

LED2 pin is also programmable via register 1eh.

LED mode = 00

Duplex

Pin State

LED Definition

Half

H

L

Off

On

Full

LED mode = 01

Full Duplex/Col

Half

Pin State

LED Definition

H

L

-

Off

Full

On

Collision

LED mode = 10

Duplex

Toggle

Pin State

LED Definition

Half

H

L

Off

On

Full

29

LED3/

Ipu/O

Programmable LED Output 3

NWAYEN

Configuration Mode: Latched as ANEG_EN (register 0h, bit 12) during

power up / reset. See Strapping Options for details. Active Low. The

LED3 pin is also programmable via register 1eh.

LED mode = 00

Collision

Pin State

LED Definition

No Collision

Collision

H

L

Off

On

LED mode = 01

Activity

Pin State

-

LED Definition

Toggle

Activity

LED mode = 10

Activity

Pin State

-

LED Definition

Toggle

Activity

30

31

PD#

Ipu

Chip power down input (active low)

1 (high) = Normal operation

0 (low) = Power down

VDDRX

Pwr

1.8V analog VDD

(See Circuit Design Reference for Power Supply for details)

Physical receive or transmit ‘-’ differential signal

Physical receive or transmit ‘+’ differential signal

32

33

34

RX-

I/O

RX+

FXSD/

FXEN

Ipd/O

Fiber Mode Enable / Signal Detect in Fiber Mode

If FXEN=0, FX mode is disable. The default is “0”.

(See Section 3.7, "100BASE-FX Mode" for details)

35

36

37

38

GND

Gnd

I

Ground

REXT

Connect a 6.65K external resistor from this pin to ground

VDDRCV

Pwr

3.3V analog VDD

(See Circuit Design Reference for Power Supply for details)

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KSZ8001L/S

Type

(Note 1)

Pin Number

Pin Name

Pin Function

39

40

41

42

43

44

45

46

GND

TX-

TX+

NC

Gnd

I/O

Ground

Physical transmit or receive ‘-’ differential signal

I/O

Physical transmit or receive ‘+’ differential signal

No Connect

Ground

NC

GND

XO

Gnd

O

I

25MHz crystal/oscillator clock connections

Pins (XI, XO) connect to a crystal. If an oscillator is used, XI connects to

a 3.3V tolerant oscillator and XO is a no connect.

Clock is +/- 50ppm for both crystal and oscillator.

XI

47

48

VDDPLL

RST#

Pwr

Ipu

1.8V analog PLL VDD

(See Circuit Design Reference for Power Supply for details)

Chip Reset

Active low, minimum of 50 us pulse is required

Note 1:

Pwr = power supply;

Ipu/O = input w/ internal pull up during

reset, output pin otherwise;

Ipd/O = input w/ internal pull down during

reset, output pin otherwise;

PD = strap pull down;

Gnd = ground;

I = input;

O = output;

I/O = bi-directional

Ipu = input w/ internal pull up;

Ipd = input w/ internal pull down;

PU = strap pull up;

2: MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted,

RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is

de-asserted.

3: RMII Rx Mode: The RXD[1..0] bits are synchronous with REF_CLK. For each clock period in

which CRS_DV is asserted, two bits of recovered data are sent from the PHY.

4: SMII Rx Mode: Receive data and control information are sent in 10 bit segments. In 100MBit

mode, each segment represents a new byte of data. In 10MBit mode, each segment is

repeated ten times; therefore, every ten segments represents a new byte of data. The MAC

can sample any one of every 10 segments in 10MBit mode.

5: MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD

[3..0] presents valid data from the MAC through the MII. TXD [3..0] has no effect when TXEN

is de-asserted.

6: RMII Tx Mode: The TXD[1..0] bits are synchronous with REF_CLK. For each clock period in

which TX_EN is asserted, two bits of recovered data are recovered by the PHY.

7: SMII Tx Mode: Transmit data and control information are received in 10 bit segments. In

100MBit mode, each segment represents a new byte of data. In 10MBit mode, each segment

is repeated ten times; therefore, every ten segments represents a new byte of data. The PHY

can sample any one of every 10 segments in 10MBit mode.

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KSZ8001L/S

2.3

Strapping Options

Pin Number

Pin Name

Type

Description

6, 5, 4,

3

PHYAD[4:1] /

RXD[0:3]

Ipd/O

PHY Address latched at power-up / reset.

The default PHY address is 00001.

25

9

PHYAD0 /

INT#

Ipu/O

Ipd/O

PCS_LPBK /

RXDV

Enables PCS_LPBK mode at power-up / reset.

PD (default) = Disable, PU = Enable

10

11

21

22

27

SMII_SELECT

/ RXC

Ipd/O

Ipu/O

Enables SMII mode at power-up / reset.

PD (default) = Disable, PU = Enable

ISO / RXER

Enables ISOLATE mode at power-up /reset.

PD (default) = Disable, PU = Enable

RMII_SELECT

/ COL

Enables RMII mode at power-up / reset.

PD (default) = Disable, PU = Enable

RMII_BTB/

CRS

Enable RMII_BTB mode at power-up / reset.

PD (default) = Disable, PU = Enable

SPD100 /

No FEF /

LED1

Latched into Register 0h bit 13 during power-up / reset.

PD = 10Mb/s, PU (default) = 100Mb/s.

If SPD100 is asserted during power-up / reset, this pin also

latched as the Speed Support in register 4h. (If FXEN is

pulled up, the latched value 0 means no Far _End _Fault.)

28

29

30

DUPLEX/

LED2

Ipu/O

Ipu

Latched into Register 0h bit 8 during power-up / reset.

PD = Half Duplex, PU (default) = Full duplex.

If Duplex is pulled up during reset, this pin also latched as

the Duplex support in register 4h.

NWAYEN/

LED3

Nway (auto-=Negotiation) Enable

Latched into Register 0h bit 12 during power-up / reset. PD

= Disable Auto-Negotiation, PU (default) = Enable Auto-

Negotiation

PD#

Power Down Enable

PU (default) = Normal operation, PD = Power down mode

Note:

Strap-in is latched during power up or reset. In some systems, the MAC RXD pins may drive high at all

times causing the PHY strap-in to be latched high during power up or system reset. In this case, it is rec-

ommended to use a strong pull down to GND via 1kohm resistor on RXDV, RXC, and RXER pins. Other-

wise, the PHY may stay in Isolate or loop back modes.

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DS00003062A-page 11

KSZ8001L/S

3.0

FUNCTIONAL OVERVIEW

3.1

Functional Description

3.1.1

100BASE-TX TRANSMIT

The 100BASE-TX transmit function performs parallel-to-serial conversion, NRZ to NRZI conversion, MLT-3 encoding

and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the 25 MHz, 4-bit nibbles into

a 125 MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data

is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by

an external 1% 6.65 K resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4 ns and complies with the

ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BASE-T output

driver is also incorporated into the 100BASE-TX driver.

3.1.2

100BASE-TX RECEIVE

The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and

clock recovery, NRZI to NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the equaliza-

tion filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and

phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize perfor-

mance. In this design, the variable equalizer will make an initial estimation based upon comparisons of incoming signal

strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and

can self adjust against environmental changes such as temperature variations.

The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used

to compensate for the effects of base line wander and to improve the dynamic range. The differential data conversion

circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then

used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles.

A synchronized 25 MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is

valid for the receiver at the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25

Mz reference clock and both TXC and RXC clocks continue to run.

3.1.3

PLL CLOCK SYNTHESIZER

The KSZ8001 generates 125 Mz, 25 Mz and 20 Mz clocks for system timing. An internal crystal oscillator circuit

provides the reference clock for the synthesizer.

3.1.4

SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)

The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.

3.1.5

10BASE-T TRANSMIT

When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KSZ8001 will continue to

encode and transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last

transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one.

The output driver is incorporated into the 100BASE- driver to allow transmission with the same magnetic. They are inter-

nally wave-shaped and pre-emphasized into outputs with a typical 2.5 V amplitude. The harmonic contents are at least

27 dB below the fundamental when driven by an all-ones Manchester-encoded signal.

3.1.6

10BASE-T RECEIVE

On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit

and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and

NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths in order to prevent

noises at the RX+ or RX- input from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks

onto the incoming signal and the KSZ8001 decodes a data frame. This activates the carrier sense (CRS) ad RXDV sig-

nals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in between

data reception.

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KSZ8001L/S

3.1.7

SQE AND JABBER FUNCTION (10BASE-T ONLY)

In 10BASE-T operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required

as a test of the 10BASE-T transmit/receive path and is called SQE test. The 10BASE-T transmitter will be disabled and

COL will go high if TXEN is High for more than 20 ms (Jabbering). If TXEN then goes low for more than 250 ms, the

10BASE-T transmitter will be re-enabled and COL will go Low.

3.1.8

AUTO-NEGOTIATION

The KSZ8001 performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It will auto-

matically choose its mode of operation by advertising its abilities and comparing them with those received from its link

partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in either

full- or half-duplex mode. Auto-negotiation is disabled in FX mode.

During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under

the conditions of power-on, link-loss or re-start. At the same time, the KSZ8001 will monitor incoming data to determine

its mode of operation. Parallel detection circuit will be enabled as soon as either 10BASE-T NLP (Normal Link Pulse)

or 100BASE-TX idle is detected. The operation mode is configured based on the following priority:

• Priority 1: 100BASE-TX, full-duplex

• Priority 2: 100BASE-TX, half-duplex

• Priority 3: 10BASE-T, full-duplex

• Priority 4: 10BASE-T, half-duplex

When the KSZ8001 receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge

bit), it will store these code words in Register 5 and wait for the next 3 identical code words. Once the KSZ8001 detects

the second code words, it then configures itself according to the above-mentioned priority. In addition, the KSZ8001 also

checks for 100BASE-TX idle or 10BASE-T NLP symbols. If either is detected, the KSZ8001 automatically configures to

match the detected operating speed.

3.2

MII Management Interface

The KSZ8001 supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output

(MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8001. The MDIO

interface consists of the following:

• A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT)

• A specific protocol that runs across the above-mentioned physical connection and it also allows one controller to

communicate with multiple KSZ8001 devices. Each KSZ8001 is assigned an MII address between 0 and 31 by the

PHYAD inputs.

• An internal addressable set of fourteen 16-bit MDIO registers. Register [0:6] are required and their functions are

specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.

The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status

change on the KSZ8001 based upon 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register

bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.

3.2.1

MII DATA INTERFACE

The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access

Controller (MAC) to the KSZ8001, and for receiving data from the line. Normal data transmission is implemented in 4B

Nibble Mode (4-bit wide nibbles).

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KSZ8001L/S

3.2.1.1

Transmit Clock (TXC): The transmit clock is normally generated by the KSZ8001 from an

external 25MHz reference source at the X1 input. The transmit data and control signals must

always be synchronized to the TXC by the MAC. The KSZ8001 normally samples these

signals on the rising edge of the TXC.

3.2.1.2

Receive Clock (RXC): For 100BASE-TX links, the receive clock is continuously recovered

from the line. If the link goes down, and auto-negotiation is disabled, the receive clock then

operates off the master input clock (X1 or TXC). For 10BASE-T links, the receive clock is

recovered from the line while carrier is active, and operates from the master input clock when

the line is idle. The KSZ8001 synchronizes the receive data and control signals on the falling

edge of RXC in order to stabilize the signals at the rising edge of the clock with 10ns setup and

hold times.

3.2.1.3

3.2.1.4

Transmit Enable: The MAC must assert TXEN at the same time as the first nibble of the

preamble, and de-assert TXEN after the last bit of the packet.

Receive Data Valid: The KSZ8001 asserts RXDV when it receives a valid packet. Line

operating speed and MII mode will determine timing changes in the following way:

For 100BASE-TX link with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last nibble

of the data packet.

For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “5D” and re-

mains asserted until the end of the packet.

3.2.1.5

3.2.1.6

Error Signals: Whenever the KSZ8001 receives an error symbol from the network, it asserts

RXER and drives “1110” (4B) on the RXD pins. When the MAC asserts TXER, the KSZ8001

will drive “H” symbols (a Transmit Error define in the IEEE 802.3 4B/5B code group) out on the

line to force signaling errors.

Carrier Sense (CRS): For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes

assertion of Carrier Sense (CRS). An end-of-stream delimiter, or /T/R symbol pair causes de-

assertion of CRS. The PMA layer will also de-assert CRS if IDLE symbols are received without

/T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-asserted. For

10T links, CRS assertion is based on reception of valid preamble, and de-assertion on

reception of an end-of-frame (EOF) marker.

3.2.1.7

Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at

the same time, then the KSZ8001 asserts its collision signal, which is asynchronous to any

clock.

3.3

RMII (Reduced MII) Data Interface

RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ether-

net PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].

This interface has the following characteristics:

• It is capable of supporting 10Mb/s and 100Mb/s data rates

• A single clock reference is sourced from the MAC to PHY (or from an external source)

• It provides independent 2 bit wide (di-bit) transmit and receive data paths

• It uses TTL signal levels, compatible with common digital CMOS ASIC processes

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KSZ8001L/S

TABLE 3-1:

RMII SIGNAL DEFINITION

Direction

Signal Name

(with respect to (with respect to

Use

the PHY)

the MAC)

REF_CLK

Input

Input or Output

Synchronous clock reference for receive, transmit and con-

trol interface

CRS_DV

RXD[1:0]

TX_EN

Output

Input

Carrier Sense/Receive Data Valid

Receive Data

Input

Output

Transit Enable

TXD[1:0]

RX_ER

Input

Transit Data

Output

Input

Receive Error

(Not Required)

Note:

Unused MII signals, TXD[3:2], TXER need to be tied to GND when RMII is used.

3.3.1

REFERENCE CLOCK (REF_CLK)

REF_CLK is a continuous 50 MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0],

and RX_ER. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide

REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock

distribution device. Each PHY device shall have an input corresponding to this clock but may use a single clock input

for multiple PHYs implemented on a single IC.

3.3.2

CARRIER SENSE/RECEIVE DATA VALID (CRS_DV)

CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is,

in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are

detected carrier is said to be detected.

Loss of carrier shall result in the de-assertion of CRS_DV synchronous to REF_CLK. So long as carrier criteria are being

met, CRS_DV shall remain asserted continuously from the first recovered di-bit of the frame through the final recovered

di-bit and shall be negated prior to the first REF_CLK that follows the final di-bit.

The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asyn-

chronous relative to REF_CLK, the data on RXD[1:0] shall be "00" until proper receive signal decoding takes place (see

definition of RXD[1:0] behavior).

3.3.3

RECEIVE DATA [1:0] (RXD[1:0])

RXD[1:0] shall transition synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0]

transfers two bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions)

a pre-determined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] shall be "00" to indicate idle

when CRS_DV is de-asserted. Values of RXD[1:0] other than "00" when CRS_DV is de-asserted are reserved for out-

of-band signaling (to be defined). Values other than "00" on RXD[1:0] while CRS_DV is de-asserted shall be ignored by

the MAC/repeater. Upon assertion of CRS_DV, the PHY shall ensure that RXD[1:0]=00 until proper receive decoding

takes place.

3.3.4

TRANSMIT ENABLE (TX_EN)

Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for trans-mission. TX_EN

shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be

transmitted are presented to the RMII. TX_EN shall be negated prior to the first REF_CLK following the final di-bit of a

frame. TX_EN shall transition synchronously with respect to REF_CLK.

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KSZ8001L/S

3.3.5

TRANSMIT DATA [1:0] (TXD[1:0])

Transmit Data TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0]

are accepted for transmission by the PHY. TXD[1:0] shall be "00" to indicate idle when TX_EN is de-asserted. Values

of TXD[1:0] other than "00" when TX_EN is de-asserted are reserved for out-of-band signaling (to be defined). Values

other than "00" on TXD[1:0] while TX_EN is disserted shall be ignored by the PHY.

3.3.6

COLLISION DETECTION

Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC can reli-

ably regenerate the COL signal of the MII by Ending TX_EN and CRS_DV.

During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers

as a self-test. The Signal Quality Error (SQE) function will not be supported by the reduced MII due to the lack of the

COL signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was

functioning. Since the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.

3.3.7

RX_ER

The PHY shall provide RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure

24-11 - Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error

(e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC

sublayer) was detected somewhere in the frame presently being transferred from the PHY. RX_ER shall transition syn-

chronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER shall have no effect on the MAC.

3.3.8

RMII AC CHARACTERISTICS

RMII Transmit Timing

3.3.8.1

20ns

REF_CLK

t

1

t2

TXD[1:0]

TXEN

Parameter

Min

Typ

Max

Unit

REF_CLK Frequency

50

MHz

ns

TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge

TXD[1:0], TX_EN, Data hold from REF_CLK rising edge

4

2

ns

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KSZ8001L/S

3.3.8.2

RMII Receive Timing

20ns

REF_CLK

RXD[1:0]

RXDV

RXER

tod

Parameter

Min

Typ

Max

Unit

REF_CLK Frequency

50

MHz

ns

RXD[1:0], CRS_DV, RX_ER Output delay from

REF_CLK rising edge

2.8

10

3.4

SMII Signal Definition

SMII is composed of two signals per port, a global synchronization signal, and a global 125MHz reference clock. All

signals are synchronous to the clock. All SMII I/F uses a common 125MHz reference clock and SYNC signals that are

synchronous to the reference clock. There are two signals in SMII from MAC-to-PHY for each port (TXD and TxSYNC),

and one signal per port from PHY-to-MAC (RXD).

The Serial Media Independent Interface (SMII) is designed to satisfy the following requirements:

• Convey complete MII information between a 10/100 PHY and MAC with two pins per port.

• Allow a multi-port MAC/PHY communication with one system clock.

• Operate in both half and full duplex.

• Per packet switching between 10Mbit and 100Mbit data rates.

• Allow direct MAC-to-MAC communication.

3.4.1

SMII SIGNALS

Signal Name

From

To

Use

RX

PHY

MAC

PHY

Receive Data and Control

Transmit Data and Control

Synchronization

TX

MAC

SYNC

Clock

MAC

System

MAC&PHY

Synchronization

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KSZ8001L/S

3.4.2

RECEIVE PATH

Receive data and control information are signaled in ten bit segments. In 100Mbit mode, each segment represents a

new byte of data. In 10Mbit mode, each segment is repeated ten times; therefore, every ten segments represent a new

byte of data. The MAC can simply any one of every 10 segment ion 10Mbit mode.

Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks.

FIGURE 3-1:

Receive Sequence Diagram

RX_CLK

RX_SYNC

RX

CRS

RX_DV

RXD0

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

RXD7

RX contains all of the information found on the receive path of the standard MII.

Bits Purpose

CRS

Carrier Sense – identical to MII, except that it is not an asynchronous signal

Receive Data Valid – identical to MII

RX_DV

RXD7-0

Encoded Data, see the RXD0-7 Encoding table

3.4.2.1

RX – Bit Description

RXD7-0 are used to convey packet data, RX_ER, and PHY status. The MAC can infer the meaning of RXD on a seg-

ment-by-basis by encoding the two control bits.

CRS

RX_DV

RXD0

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

RXD7

X

0

RX_ER

from pre- 0=10Mbit

vious

frame

Speed

Duplex

0=Half

1=Full

Link

0=Down

1=Up

Jabber

0=OK

1=Error

Upper

Nibble

0=invalid Detected

1=valid

False

Carrier

1

1=100Mbit

X

1

One Data Byte (Two MII Data Nibble)

3.4.2.2

TXD7 – 0 Encoding

Inter-frame status bit RXD5 conveys the validity of the upper nibble of the byte of the previous frame. Inter-frame status

bit RXD0 indicates whether or not the PHY detected an error somewhere on the previous frame. Both of these bits

should be valid in the segment immediately following a frame, and should stay valid until the first data segment of the

next frame begins.

When asserted, inter-frame status bit RXD6 indicates that the PHY has detected a false carrier event.

In order to send receive data to the MAC synchronous to the reference clock, the PHY must pass the data through an

elasticity FIFO to handle any difference between the reference clock rate and the clock at the packet source. The Ether-

net specification calls for packet data to be referenced to a clock with a frequency tolerance of 100ppm (0.01%); how-

ever, it is not uncommon to encounter Ethernet stations with clocks that have frequency errors up to 0.1%. Therefore,

the elasticity FIFO should be at least 27 bits * long, filling to the halfway point before beginning valid data transfer via

RX. RX_ER should be asserted if, during the reception of a frame, this FIFO overflows or underflows.

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KSZ8001L/S

Only RXD and RX_DV should be passed through the elasticity FIFO. CRS should not be passed through the elasticity

FIFO. Instead, CRS should be asserted for the time the ‘wire’ is busy receiving a frame.

3.4.3

TRANSMIT PATH

Transmit data and control information are signaled in ten bit segments, just like the receive path. In 100Mbit mode, each

segment represents anew byte of data. In 10Mbit mode each segment is repeated ten times; therefore, every ten seg-

ments represents a new byte of data. The PHY can sample any one of every 10 segments in 10Mbit mode.

Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks.

FIGURE 3-2:

Transmit Sequence Diagram

TX_CLK

TX_SYNC

TX

TX_ER

TX_EN

TXD0

TXD1

TXD2

TXD3

TXD4

TXD5

TXD6

TXD7

Bits

Purpose

TX_EN

TX_ER

TXD7-0

Transmit Enable – identical to MII

Transmit Error – identical to MII

Encoded Data – see TXD7-0 Encoding Table

3.4.3.1

TX- Bit Description

As far as the PHY is concerned, TXD7-0 are used to convey only packet data. To allow for a direct MAC-to-MAC con-

nection, the MAC uses TXD7-0 to signal ‘status’ in between frames.

TX_ER

TX_EN

TXD0

TXD1

TXD2

TXD3

TXD4

TXD7-5

x

0

Use to force

an error in a

direct MAC to

MAC connec-

tion

1

0

1

100MBit

Full Duplex

Link Up

No Jabber

x

1

One Data Byte (Two MII Data Nibbles)

TXD7 – 0 Encoding

3.4.4

COLLISION DETECTION

Collisions occur when CRS and TX_EN are simultaneously asserted. For this to work, the PHY must ensure that CRS

is not affected by its transmit path.

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KSZ8001L/S

3.4.5

DC SPECIFICATION

Parameter

Symbol

Vih

Min

Max

Units

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

2.0

Volts

uA

Vil

Iih

Iil

0.8

10

-10

uA

3.4.6

TIMING SPECIFICATION

Parameter

Min

Max

Units

Input Setup

Input Hold

1.5

1

ns

Output Delay

1.5

5

3.5

HP Auto Crossover (Auto MDI/MDI-X)

Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The

assignment of pin-outs for a 10/100 BASE-T crossover function cable is shown below.

This feature can eliminate the confusion in real applications by allowing both straight cable and crossover cables. This

feature is controlled by register 1f:13, see “Register 1fh” section for details.

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KSZ8001L/S

Straight Through Cable

10/100 Base‐T

Media Dependent Interface

10/100 Base‐T

Media Dependent Interface

1

Transmit Pair

Receive Pair

2

3

4

3

4

Receive Pair

Transmit Pair

5

6

7

8

6

7

8

Modular Connector

(RJ45)

Modular Connector

(RJ45)

HUB

NIC

(Repeater or Switch)

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DS00003062A-page 21

KSZ8001L/S

Straight Through Cable

10/100 Base‐T

Media Dependent Interface

10/100 Base‐T

Media Dependent Interface

1

Transmit Pair

Receive Pair

2

3

4

Receive Pair

Transmit Pair

5

6

7

8

6

7

8

Modular Connector

(RJ45)

Modular Connector

(RJ45)

HUB

NIC

(Repeater or Switch)

3.5.1

AUTO MDI/MDI-X CROSS-OVER TRANSFORMER CONNECTION

KSZ8001 features HP Auto MDI/MDI-X crossover and requires symmetric transformers that support Auto MDI/MDI-X.

See “Section 6.9, "Selection of Isolation Transformer"” for a list of transformers that support Auto MDI/MDI-X.

3.6

Power Management

The KSZ8001 offers the following modes for power management:

• Power Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# Low. In the

power down state, the KS8061 disables all internal functions and drives output pins to logic zero, except for the

MII serial management interface.

• Power Saving Mode: writing to register 1fh.10 can disable this mode. The KSZ8001 will then turn off everything

except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the KSZ8001 will

shutdown most of the internal circuits to save power if there is no link. Power Saving mode will be in this most

effective state when Auto-Negotiation Mode is enabled.

3.7

100BASE-FX Mode

100BASE-FX mode is activated when FXSD/FXEN is higher than 0.6V (This pin has a default pull down). Under this

mode, the auto-negotiation and auto-MDIX features are disabled.

In fiber operation FXSD pin should connect to the SD (signal detect) output of the fiber module. The internal threshold

of FXSD is around ⅔ Vdd +/- 50 mV (2.2V +/- 0.05V at 3.3V). Above this level, it is considered Fiber signal detected,

and the operation is summarized in the following table:

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KSZ8001L/S

FXSD/FXEN

Condition

Less than 0.6V

100TX mode

Less than 2.15V,

FX mode

but greater than 0.6V

Greater than 2.25V

No signal detected

FEF generated

FX mode

Signal detected

To ensure proper operation, the swing of fiber module SD should cover the threshold variation. Aresistive voltage divider

is recommended to adjust the SD voltage range.

FEF (Far End Fault), repetition of a special pattern, which consists of 84-ones and 1-zero, is generated under “FX mode

with no signal detected”. The purpose of FEF is to notify the sender of a faulty link. When receiving a FEF, the LINK will

go down to indicate a fault, even with fiber signal detected. The transmitter is not affected by receiving a FEF and still

sends out its normal transmit pattern from MAC. FEF can be disabled by strapping pin27 low, please refer to “Strapping

Options” section.

3.8

Media Converter Operation

The KSZ8001 is capable of performing media conversion with 2 parts in a back-to-back RMII mode as indicated in the

diagram. Both parts are in RMII mode and with RMII_BTB asserted (pin21 & 22 strapped high). One part is operating

at TX mode and the other in FX mode. Both parts can share a common 50MHz oscillator.

Under this operation, auto-Negotiation on the TX side will prohibit 10BASE-T link up. Additional options can be imple-

mented under this operation. Disable the transmitter and set it at tri-state by controlling the high TXD2 pin. In order to

do this, RXD2 and TXD2 pins need to be connected via an inverter. When TXD2 pin is high in both the copper and fiber

operation, it disables transmit. Meanwhile, the RXD2 pin on the copper side serves as the energy detect and can indi-

cate if a line signal is detected. TXD3 should be tied low and RXD3 let float. Please contact your local Microchip FAE

for a Media Converter reference design.

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DS00003062A-page 23

KSZ8001L/S

Vcc

21 22

Rx +/-

RxD

KSZ8001

TxD

Tx +/-

TxC/

Ref_CLK

OSC

50 MHz

TxC/

Ref_CLK

FTx

FRx

TxD

KSZ8001

(Fiber Mode)

RxD

34

21 22

Vcc

To the SD pin of the

Fiber Module

3.9

LinkMD^®Cable Diagnostics

The KSZ8001 utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such

as open circuits, short circuits and impedance mismatches. LinkMD^®works by sending a pulse of known amplitude and

duration down the MDI and MDIX pairs and analyzing the shape of the reflected signal. Timing the duration gives an

indication of the distance to the cabling fault with maximum distance of 200 m and accuracy of +/- 2 m. Cable diagnostics

are only valid for copper connections and do not support fiber optic operation.

LinkMD is used by accessing register 1dh, the LinkMD Control/Status register in conjunction with register 1fh, the

100BASE-TX PHY Controller register. To use LinkMD, HP Auto-MDIX is disabled by writing a ‘1’ to 1f:13 to enable man-

ual control over which pair is used to transmit the LinkMD pulse. The self-clearing Cable diagnostic test enable bit, 1d.15

is set to ‘1’ to start the test on this pair. When 1d.15 returns to ‘0’, the test is complete. The test result is returned in

1d.14:13 and the distance is returned in 1d.8:0. The cable diagnostic test results are as follows:

• 00 = Valid test, normal condition

• 01 = Valid test, open circuit in cable

• 10 = Valid test, short circuit in cable

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KSZ8001L/S

• 11 = Invalid test, LinkMD failed

The ‘11’ case, Invalid test, occurs when it is not possible for the KSZ8001 to shut down the link partner. In this case, the

test is not run, since it would not be possible for the KSZ8001 to determine if the detected signal is a reflection of the

signal generated or a signal from another source.

Cable length can be determined by multiplying the contents of 1d.8:0 by 0.39. This constant may be calibrated for dif-

ferent cabling conditions, including cables with a velocity of propagation that varies significantly from the norm.

3.10 Reference Clock Connection Options

KSZ8001 is capable of performing three different kinds of clock speed options for connecting the external reference

clock depends upon the different interface of using MII/RMII/SMII. The figures below illustrate the recommended con-

nection for using the different interface options. See Section 6.10, "Selection of Reference Crystal" for specifications.

FIGURE 3-3:

25MHz Oscillator Reference Clock Connection Diagram

XI

25MHz Osc

+/-50ppm

XO

NC

FIGURE 3-4:

25MHz Crystal Reference Clock Connection Diagram

27pF

XI

27pF

XO

25MHz Xtal

+/-50ppm

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KSZ8001L/S

FIGURE 3-5:

50/125 MHz Oscillator Reference Clock Connection for RMII/SMII

Mode Diagram

VCC

XI

10K

XO

NC

50/125MHz Osc

+/-50ppm

REF_CLK

3.11 Circuit Design Reference for Power Supply

The following diagram shows the power connections for the single 3.3V supply KSZ8001L and KSZ8001SL devices.

Ferrite

Bead

Ferrite

Bead

Ferrite

Bead

3.3A

1uF

1.8PLL

1.8A

1.8V

0.1uF

1uF

0.1uF

13

47

31

38

VDDRCV

V_IN

VDDIO

7

V_OUT

1.8V

LDO

Regulator

3.3V

24

KSZ8001L

KSZ8001SL

GND

8

12 23

36 39 44

35

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KSZ8001L/S

4.0

REGISTER MAP

Register No.

Description

0h

1h

Basic Control Register

Basic Status Register

PHY Identifier I

2h

3h

PHY Identifier II

4h

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page Register

Link Partner Next Page Ability

Reserved

5h

6h

7h

8h

9h-14h

15h

16h – 1ah

1bh

1ch

1dh

1eh

1fh

RXER Counter Register

Reserved

Interrupt Control/Status Register

Reserved

LinkMD^®Control/Status Register

PHY Control Register

100BASE-TX PHY Control Register

Address

Name

Description

Mode

Default

Register 0h – Basic Control

0.15

0.14

0.13

Reset

1 = software reset. Bit is self-clearing

RW/

SC

0

Loop-back

1 = loop-back mode

0 = normal operation

RW

0

Speed Select 1 = 100Mb/s

RW

Set by SPD100

(LSB)

0 = 10Mb/s

Ignored if Auto-Negotiation is enabled

(0.12 = 1)

0.12

Auto-Negotia- 1 = enable auto-negotiation process (over- RW

Set by NWAYEN

tion Enable

ride 0.13 and 0.8)

0 = disable auto-negotiation process

0.11

0.10

Power Down 1 = power down mode

0 = normal operation

RW

0

Isolate

1 = electrical isolation of PHY from MII and RW

TX+/TX-

Set by ISO

0 = normal operation

0.9

Restart Auto- 1 = restart auto-negotiation process

Negotiation 0 = normal operation. Bit is self-clearing

RW/

SC

0

0.8

Duplex Mode 1 = full duplex

0 = half duplex

RW

RO

Set by DUPLEX

0.7

Collision Test 1 = enable COL test

0 = disable COL test

0

0.6:1

Reserved

 2009-2019 Microchip Technology Inc.

DS00003062A-page 27

KSZ8001L/S

Address

0.0

Name

Disable

Transmitter

Description

0 = enable transmitter

1 = disable transmitter

Mode

RW

Default

0

Register 1h – Basic Status

1.15

1.14

1.13

1.12

1.11

100BASE-T4 1 = T4 capable

RO

0

1

0 = not T4 capable

100BASE-TX 1 = capable of 100BASE-X full duplex

Full Duplex

0 = not capable of 100BASE-X full duplex

100BASE-TX 1 = capable of 100BASE-X half duplex

Half Duplex

0 = not capable of 100BASE-X half duplex

10BASE-T

Full Duplex

1 = 10Mbps with full duplex

0 = no 10Mbps with full duplex capability

10BASE-T

Half Duplex

1 = 10Mbps with half duplex

0 = no 10Mbps with half duplex capability

1.10:7

1.6

Reserved

RO

0

1

No Preamble 1 = preamble suppression

0 = normal preamble

1.5

Auto-Negotia- 1 = auto-negotiation process completed

tion Complete 0 = auto-negotiation process not com-

pleted

RO

0

1.4

1.3

1.2

1.1

1.0

Remote Fault 1 = remote fault

0 = no remote fault

RO/

LH

0

1

0

1

Auto-Negotia- 1 = capable to perform auto-negotiation

RO

tion Ability

0 = unable to perform auto-negotiation

Link Status

1 = link is up

RO/

LL

0 = link is down

Jabber Detect 1 = jabber detected

0 = jabber not detected. Default is Low

RO/

LH

Extended

Capability

1 = supports extended capabilities regis-

ters

RO

Register 2h – PHY Identifier 1

2.15:0

PHY ID Num- Assigned to the 3^rdthrough 18^thbits of the RO

0022h

ber

Organizationally Unique Identifier (OUI).

Kendin Communication’s OUI is 0010A1

(hex)

Register 3h – PHY Identifier 2

3.15:10

PHY ID Num- Assigned to the 19^ththrough 24^thbits of

RO

000101

ber

the Organizationally Unique Identifier

(OUI). Kendin Communication’s OUI is

0010A1 (hex)

3.9:4

3.3:0

Model Num-

ber

Six bit manufacturer’s model number

RO

100001

1010

Revision

Number

Four bit manufacturer’s model number

Register 4h – Auto-Negotiation Advertisement

4.15

RW

0

0 = no next page capability.

4.14

4.13

Reserved

RO

0

Remote Fault 1 = remote fault supported

0 = no remote fault

RW

DS00003062A-page 28

 2009-2019 Microchip Technology Inc.

KSZ8001L/S

Address

Name

Description

Mode

RO

Default

4.12 : 11

4.10

Reserved

Pause

0

1 = pause function supported

0 = no pause function

RW

RO

RW

0

4.9

100BASE-T4 1 = T4 capable

0 = no T4 capability

0

4.8

4.7

100BASE-TX 1 = TX with full duplex

Full Duplex

Set by SPD100 & DUPLEX

Set by SPD100

0 = no TX full duplex capability

100BASE-TX 1 = TX capable

0 = no TX capability

4.6

4.5

10BASE-T

Full Duplex

1 = 10Mbps with full duplex

0 = no 10Mbps full duplex capability

Set by

DUPLEX

10BASE-T

1 = 10Mbps capable

0 = no 10Mbps capability

1

4.4:0

Selector Field [00001] = IEEE 802.3

00001

Register 5h – Auto-Negotiation Link Partner Ability

5.15

5.14

5.13

0 = no next page capability

RO

0

Acknowledge 1 = link code word received from partner

0 = link code word not yet received

Remote Fault 1 = remote fault detected

0 = no remote fault

5.12

Reserved

RO

0

5.11:10

Pause

5.10 5.11

0

No PAUSE

1

Asymmetric PAUSE (link partner)

0

Symmetric PAUSE

1

Symmetric & Asymmetric PAUSE (local

device)

5.9

100 BASE-T4 1 = T4 capable

0 = no T4 capability

RO

0

5.8

5.7

100BASE-TX 1 = TX with full duplex

0

Full Duplex

0 = no TX full duplex capability

100BASE-TX 1 = TX capable

0 = no TX capability

0

5.6

5.5

10BASE-T

Full Duplex

1 = 10Mbps with full duplex

0 = no 10Mbps full duplex capability

0

10BASE-T

1 = 10Mbps capable

0

0 = no 10Mbps capability

5.4:0

Selector Field [00001] = IEEE 802.3

00001

Register 6h – Auto-Negotiation Expansion

6.15:5

6.4

Reserved

RO

0

Parallel

Detection

Fault

1 = fault detected by parallel detection

RO/

0 = no fault detected by parallel detection. LH

 2009-2019 Microchip Technology Inc.

DS00003062A-page 29

KSZ8001L/S

Address

6.3

Name

Description

Mode

RO

Default

Link Partner

1 = link partner has next page capability

0 = link partner does not have next page

capability

0

1

6.2

1 = local device has next page capability

0 = local device does not have next page

capability

RO

6.1

6.0

Page

Received

1 = new page received

0 = new page not yet received

RO/

LH

0

Link Partner

1 = link partner has auto-negotiation capa- RO

Auto-Negotia- bility

tion Able 0 = link partner does not have auto-negoti-

ation capability

Register 7h – Auto-Negotiation Next Page

7.15

1 = additional next page(s) will follow

0 = last page

RW

0

7.14

7.13

RO

0

1

Message

Page

1 = message page

0 = unformatted page

RW

7.12

7.11

Acknowl-

edge2

1 = will comply with message

0 = cannot comply with message

RW

RO

0

Toggle

1 = previous value of the transmitted link

code word equaled logic One

0 = logic Zero

7.10:0

Message

Field

11-bit wide field to encode 2048 messages RW

001

Register 8h – Link Partner Next Page Ability

8.15

8.14

8.13

8.12

8.11

0 = last page

RO

0

Acknowledge 1 = successful receipt of link word

0 = no successful receipt of link word

Message

Page

1 = Message Page

0 = Unformatted Page

Acknowl-

edge2

1 = able to act on the information

0 = not able to act on the information

Toggle

1 = previous value of transmitted Link

Code Word equal to logic zero

0 = previous value of transmitted Link

Code Word equal to logic one

8.10:0

Message

Field

RO

RW

0

Register 15h – RXER Counter

15.15:0

RXER

Counter

RX Error counter for the RX_ER in each

package

0000

0

Register 1bh – Interrupt Control/Status Register

1b.15

Jabber Inter- 1=Enable Jabber Interrupt

rupt Enable 0=Disable Jabber Interrupt

DS00003062A-page 30

 2009-2019 Microchip Technology Inc.

KSZ8001L/S

Address

1b.14

Name

Description

Mode

RW

Default

Receive Error 1=Enable Receive Error Interrupt

0

Interrupt

Enable

0=Disable Receive Error Interrupt

1b.13

1b.12

1b.11

Page

1=Enable Page Received Interrupt

0=Disable Page Received Interrupt

RW

0

Received

Interrupt

Enable

Parallel

1= Enable Parallel Detect Fault Interrupt

0= Disable Parallel Detect Fault Interrupt

Detect Fault

Interrupt

Enable

Link Partner

1= Enable Link Partner Acknowledge Inter- RW

Acknowledge rupt

Interrupt

Enable

0= Disable Link Partner Acknowledge

Interrupt

1b.10

1b.9

Link Down

Interrupt

Enable

1= Enable Link Down Interrupt

0= Disable Link Down Interrupt

RW

0

Remote Fault 1= Enable Remote Fault Interrupt

Interrupt

Enable

0= Disable Remote Fault Interrupt

1b.8

1b.7

1b.6

1b.5

1b.4

Link Up Inter- 1= Enable Link Up Interrupt

rupt Enable 0= Disable Link Up Interrupt

Jabber Inter- 1= Jabber Interrupt Occurred

0

RO/

SC

rupt

0= Jabber Interrupt Does Not Occurred

ReceiveError 1= Receive Error Occurred

Interrupt

RO/

SC

0= Receive Error Does Not Occurred

Page Receive 1= Page Receive Occurred

Interrupt

RO/

SC

0= Page Receive Does Not Occurred

Parallel

Detect Fault

Interrupt

1= Parallel Detect Fault Occurred

0= Parallel Detect Fault Does Not

Occurred

RO/

SC

1b.3

Link Partner

1= Link Partner Acknowledge Occurred

RO/

SC

0

Acknowledge 0= Link Partner Acknowledge Does Not

Interrupt

Occurred

1b.2

1b.1

1b.0

Link Down

Interrupt

1= Link Down Occurred

0= Link Down Does Not Occurred

RO/

SC

0

Remote Fault 1= Remote Fault Occurred

Interrupt

RO/

SC

0= Remote Fault Does Not Occurred

Link Up Inter- 1= Link Up Interrupt Occurred

rupt

RO/

SC

0= Link Up Interrupt Does Not Occurred

Register 1dh – LinkMD^®Control/Status Register

1d.15

Cable diag-

nostic test

enable

0 = Indicates cable diagnostic test has

completed and the status information is

valid for read.

RW/

SC

0

1 = the cable diagnostic test is activated.

This bit is self-clearing.

 2009-2019 Microchip Technology Inc.

DS00003062A-page 31

KSZ8001L/S

Address

Name

Description

[00] = normal condition

[01] = open condition has been detected in

cable

Mode

RO

Default

1d.14:13

Cable diag-

nostic test

result

0

[10] = short condition has been detected in

cable

[11] = cable diagnostic test failed

1d.12:9

1d.8:0

Reserved

Cable fault

counter

Distance to fault, approximately

0.39m*cabfaultcnt value

RO

0

Register 1eh – PHY Control

1e:15:14

LED mode

[00] =

RW

LED3 <- collision

LED2 <- full duplex

LED1 <- speed

LED0 <- link/activity

[01] =

LED3 <- activity

LED2 <- full duplex/collision

LED1 <- speed

LED0 <- link

[10] =

LED3 <- activity

LED2 <- full duplex

LED1 <- 100Mbps link

LED0 <- 10Mbps link

[11] = reserved

1e.13

1e.12

1e.11

Polarity

0 = Polarity is not reversed

1 = Polarity is reversed

RO

Far end fault

detect

0 = Far end fault detected

1 = Far end fault not detected

MDIX/MDI

state

0 = MDIX

1 = MDI

1e:10:8

1e:7

Reserved

Remote loop- 0: normal mode

RW

0

back

1: remote (analog) loop back is enable

1e:6:0

Reserved

Register 1fh – 100BASE-TX PHY Controller

1f:15

1f:14

HP_MDIX

0: Microchip Auto MDI/MDI-X mode

1: HP Auto MDI/MDI-X mode

RW

1

0

MDI/MDI-X

Select

When Auto MDI/MDI-X is disabled,

0 = Transmit on TX+/- (pins 41,40)

Receive on RX+/- (pins 33,32)

1 = Transmit on RX+/- (pins 33,32)

Receive on TX+/- (pins 41,40)

DS00003062A-page 32

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KSZ8001L/S

Address

1f:13

Name

Pairswap dis- 1 = disable MDI/MDIX

able 0 = enable MDI/MDIX

Description

Mode

RW

Default

0

1f.12

1f.11

Energy detect 1 = presence of signal on RX+/- analog

wire pair

RO

0

0 = no signal detected on RX+/-

Force link

1 = force link pass

RW

0 = normal link operation

This bit bypasses the control logic and

allow transmitter to send pattern even if

there is no link.

1f.10

1f.9

1f.8

1f.7

Power Saving 1 = enable power saving

0 = disable

RW

RO

1

0

1

0

Interrupt Level 1 = interrupt pin active high

0 = active low

Enable Jabber 1 = enable jabber counter

0 = disable

Auto-Negotia- 1 = auto-negotiation complete

tion Complete 0 = not complete

This bit has the same definition as register

1.5.

1f.6

Enable Pause 1 = flow control capable

(Flow-Control 0 = no flow control

Result)

RO

0

1f.5

PHY Isolate

1 = PHY in isolate mode

0 = not isolated

RO

0

1f.4:2

Operation

[000] = still in auto-negotiation

Mode Indica- [001] = 10BASE-T half duplex

tion

[010] = 100BASE-TX half duplex

[011] = default

[101] = 10BASE-T full duplex

[110] = 100BASE-TX full duplex

[111] = PHY/MII isolate

1f.1

1f.0

Enable SQE

test

1 = enable SQE test

0 = disable

RW

0

Disable Data 1 = disable scrambler

Scrambling 0 = enable

 2009-2019 Microchip Technology Inc.

DS00003062A-page 33

KSZ8001L/S

5.0

5.1

OPERATIONAL CHARACTERISTICS

Absolute Maximum Rating (Note 1)

Storage Temperature (T_S) ...................................................................................................................... -55C to +150C

Supply Referenced to GND.......................................................................................................................... -0.5V to +4.0

All pins ......................................................................................................................................................... -0.5V to +4.0

**Please read the Notes at the end of the Electrical Characteristics.

5.2

Operating Range (Note 2)

Supply Voltage

(V_DDPLL, V_DDRX, V_DDC).....................................................................................................................................1.8V 5%

(V_DDRCV,V_DDIO) ................................................................................................................................................3.3V 5%

Ambient Temperature Commercial (T_AC) .....................................................................................................0C to +70C

Ambient Temperature Industrial (T_AI)........................................................................................................-40C to +85C

5.3

Package Thermal Resistance (_JA) (Note 3)

Thermal Resistance

_JA

_JC

Airflow Velocity (m/s)

KSZ8001L / KSZ8001LI

KSZ8001SL / KSZ8001SLI

KSZ8001S

0

1

2

0

83.56

75.19

42.43

77.08

68.20

36.19

72.36

66.43

34.24

35.90

42.65

6.75

5.4

Electrical Characteristics (Note 4)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Total Supply Current (Note 5)

KSZ8001L:

• Current consumption is for the single 3.3V supply KSZ8001L device only, and includes the 1.8V supply voltages

(VDDRX, VDDPLL) that are provided by the KSZ8001L via power output pin 13 (VDDC).

• Transformer consumes an additional 45mA @ 3.3V for 100BASE-TX and 70mA @ 3.3V for 10BASE-T.

I_DD1

I_DD2

I_DD3

I_DD4

I_DD5

100BASE-TX

Chip only, no transformer

52

32

35

5

mA

10BASE-T

Chip only, no transformer

Power Saving Mode

SW Power Down Mode

Power down pin (PD#)

Ethernet cable disconnected

Register (software) power down

Chip (hardware) power down

3

TTL Inputs

V_IH

V_IL

I_IN

Input High Voltage

2.0

2.4

V

Input Low Voltage

Input Current

0.8

10

V

VIN = GND – V_DD

I_OH= -4mA

-10

A

TTL Outputs

V_OH

V_OL

I I_OZ

Output High Voltage

V

Output Low Voltage

0.4

10

V

I

Output Tri-State Leakage

A

DS00003062A-page 34

 2009-2019 Microchip Technology Inc.

KSZ8001L/S

Symbol

Parameter

Condition

Min

Typ

Max

Unit

100BASE-TX Transmit (measured differentially after 1:1 transformer)

V_O

Peak Differential Output 50 from each output to V_DD

Voltage

0.95

1.05

V

V_IMB

t_r,t_t

Output Voltage Imbal-

ance

50 from each output to V_DD

2

%

Rise/Fall Time

3

0

5

ns

%

V

Rise/Fall Time Imbalance

Duty Cycle Distortion

Overshoot

0.5

0.25

5

V_SET

Reference Voltage of

ISET

0.75

Propagation Delay

Jitter

45

60

Ns

0.7

1.4

ns_(pk-pk)

10BASE-T Transmit (measured differentially after 1:1 transformer)

V_P

Peak Differential Output 50 from each output to V_DD

Voltage

2.2

2.8

V

V_IMB

t_r,t_t

Output Voltage Imbal-

ance

50 from each output to V_DD

3.5

ns

Rise/Fall Time

25

Clock Outputs

X1, X2

Crystal Oscillator

25

MHz

RXC₁₀₀Receive Clock, 100TX

25

MHz

RXC₁₀

Receive Clock, 10T

Receive Clock Jitter

2.5

3.0

25

MHz

ns_(pk-pk)

MHz

TXC₁₀₀Transmit Clock, 100TX

TXC₁₀

Transmit Clock, 10T

Transmit Clock Jitter

2.5

1.8

MHz

ns_(pk-pk)

Note 1: Exceeding the absolute rating(s) may cause permanent damage to the device. Operating at maximum con-

ditions for extended periods may affect device reliability.

2: This device is not guaranteed to operate beyond its specified operating rating. Unused inputs must always

be tied to an appropriate logic voltage level (Ground to V_DD).

3: No HS (heat spreader) in package.

4: Specification for packaged product only.

5: 100% data transmission in full-duplex mode and minimum IPG with 130-meter cable.

 2009-2019 Microchip Technology Inc.

DS00003062A-page 35

KSZ8001L/S

6.0

6.1

TIMING DIAGRAMS

10BaseT MII Transmit Timing

TXC

t_HD2

t_SU2

TXEN

t_HD1

TXD[3:0]

CRS

t_SU1

t_CRS1

t_CRS2

Valid

Data

TXP/TXM

t_LAT

SQE Timing

TXC

TXEN

COL

t_SQE

t_SQEP

min.

typ.

max.

t_SU1

t_SU2

TXD[3:0] Setup to TXC High

TXEN Setup to TXC High

TXD[3:0] Hold after TXC High

TXEN Hold after TXC High

TXEN High to CRS asserted latency

TXEN Low to CRS de-asserted latency

TXEN High to TXP/TXM output (TX latency)

COL (SQE) Delay after TXEN de-asserted

COL (SQE) Pulse Duration

10ns

0ns

t_HD1

t_HD2

t_CRS1

t_CRS2

t_LAT

t_SQE

t_SQEP

0ns

4BT

8BT

4BT

2.5us

1.0us

DS00003062A-page 36

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KSZ8001L/S

6.2

100BaseTX MII Transmit Timing

TXC

t_HD2

t_SU2

TXEN

t_HD1

t_SU1

TXD[3:0],

TXER

Data

In

t_CRS2

t_CRS1

t_LAT

CRS

Symbol

Out

TX+/TX-

min.

typ.

max.

t_SU1

t_SU2

TXD[3:0] Setup to TXC High

TX_ER Setup to TXC High

TXD[3:0] Hold after TXC High

TXER Hold after TXC High

TXEN Hold after TXC High

TXEN High to CRS asserted latency

TXEN Low to CRS de-asserted latency

10ns

0ns

t_HD1

t_HD2

t_HD3

t_CRS1

t_CRS2

t_LAT

4BT

7BT

TXEN High to TX+/TX- output (TX latency)

 2009-2019 Microchip Technology Inc.

DS00003062A-page 37

KSZ8001L/S

6.3

100BaseTX MII Receive Timing

Start of

Stream

End of

Stream

RX+/RX-

CRS

t_CRS1

t_CRS2

RXDV

t_RLAT

t_HD

RXD[3:0]

RXER

t_SU

t_WH

RXC

t_WL

t_P

min.

typ.

max.

3BT

t_P

RXC period

40ns

20ns

2BT

t_WL

t_WH

t_SU

RXC pulse width

RXD[3:0], RXER, RXDV setup to rising edge of RXC

RXD[3:0], RXER, RXDV hold from rising edge of RXC

CRS to RXD latency, 4B or 5B aligned

t_HD

t_RLAT

t_CRS1

t_CRS2

1BT

"Start of Stream " to CRS asserted

"End of Stream" to CRS de-asserted

140ns

170ns

DS00003062A-page 38

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KSZ8001L/S

6.4

Auto Negotiation / Fast Link Pulse Timing

FLP

Burst

TX+/TX-

t_FLPW

t_BTB

Clock

Pulse

Data

Pulse

Clock

Pulse

Data

Pulse

TX+/TX-

t_PW

t_CTD

t_CTC

min.

8ms

typ.

max.

t_BTB

t_FLPW

t_PW

t_CTD

t_CTC

FLP burst to FLP burst

FLP burst width

Clock/Data pulse width

Clock pulse to data pulse

Clock pulse to clock pulse

16ms 24ms

2ms

100ns

69us

136us

33

Number of Clock/Data pulses per burst

17

 2009-2019 Microchip Technology Inc.

DS00003062A-page 39

KSZ8001L/S

6.5

Serial Management Interface Timing

t_P

MDC

t_MD1

t_MD2

MDIO

(Into Chip)

Valid

Data

Valid

Data

t_MD3

MDIO

(Out of Chip)

Valid

Data

min.

typ.

max.

t_P

MDC period

400 ns

t_MD1

t_MD2

t_MD3

MDIO Setup to MDC (MDIO as input)

MDIO Hold after MDC (MDIO as input)

MDC to MDIO Valid (MDIO as output)

10ns

222ns

DS00003062A-page 40

 2009-2019 Microchip Technology Inc.

KSZ8001L/S

6.6

Reset Timing

FIGURE 6-1:

RESET TIMING DIAGRAM

Supply

Voltage

tsr

RST_N

Strap‐In Value

TABLE 6-1:

Parameter

RESET TIMING PARAMETERS

Description

Min

Max

Units

us

t_sr

Stable supply voltages to reset high

50

 2009-2019 Microchip Technology Inc.

DS00003062A-page 41

KSZ8001L/S

6.7

Reset Circuit Diagram

Microchip recommends the following discrete reset circuit when powering up the KSZ8001 device.

FIGURE 6-2:

RECOMMENDED RESET CIRCUIT

VCC

D1: 1N4148

D1

R 10K

KSZ8001

RST#

C 10uF

For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), the following reset

circuit is recommended.

FIGURE 6-3:

RECOMMENDED CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET

VCC

R 10K

D1

KSZ8001

CPU/FPGA

RST#

RST_OUT_n

D2

C 10uF

D1, D2: 1N4148

DS00003062A-page 42

 2009-2019 Microchip Technology Inc.

KSZ8001L/S

At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Microchip device. The reset out from

CPU/FPGA provides warm reset after power up. It is also recommend to power up VDD core voltage earlier than VDDIO

voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.

6.8

Reference Circuit for Strapping Option Configuration

The following figure shows the reference circuits for external pull-up and pull-down on the LED strapping pins.

3.3 V



Pull Up



LED pin

KSZ8001

3.3 V

Pull Down

KSZ8001





LED pin

Reference circuits for unmanaged programming through LED ports

 2009-2019 Microchip Technology Inc.

DS00003062A-page 43

KSZ8001L/S

6.9

Selection of Isolation Transformer

A1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke

is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics.

TABLE 6-2:

TRANSFORMER SELECTION CRITERIA

Parameter Value

Test Condition

Turns Ratio

1 CT : 1 CT

350 uH

Open-Circuit Inductance (min.)

Leakage Inductance (max.)

Inter-Winding Capacitance (max.)

D.C. Resistance (max.)

Insertion Loss (max.)

100 mV, 100 kHz, 8 mA

1 MHz (min.)

0.4 uH

12 pF

0.9 Ohms

1.0 dB

0-65 MHz

HIPOT (min.)

1500 Vrms

TABLE 6-3:

MAGNETIC VENDOR SELECTION LISTS

Single Port

Magnetic Manufacturer

Part Number

H1102

AUTO MDIX

Number of Port

Pulse

Yes

1

Bel Fuse

YCL

S558-5999-U7

SI-46001

SI-50170

PT163020

HB726

Transpower

Delta

LF8505

LanKom

LF-H41S

6.10 Selection of Reference Crystal

An oscillator or crystal with the following typical characteristics is recommended.

Characteristics Value

Units

Frequency

25.00000

 50

20

MHz

ppm

pF

Frequency Tolerance (max)

Load Capacitance (max)

Series Resistance

40

W

DS00003062A-page 44

 2009-2019 Microchip Technology Inc.

KSZ8001L/S

7.0

PACKAGE INFORMATION

FIGURE 7-1:

48-PIN LQFP PACKAGE OUTLINE AND RECOMMENDED LAND PATTERN

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

 2009-2019 Microchip Technology Inc.

DS00003062A-page 45

KSZ8001L/S

FIGURE 7-2:

48-PIN SSOP PACKAGE OUTLINE AND RECOMMENDED LAND PATTERN

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

DS00003062A-page 46

 2009-2019 Microchip Technology Inc.

KSZ8001L/S

APPENDIX A: DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

Section/Figure/Entry

Revision

Correction

DS00003062A (06-26-19)

Rev. 1.04 (25 June 2009)

Rev. 1.03 (7 March 2006)

Replaces previous Micrel version Rev. 1.04, June 2009.

Updated ordering information.

• Removed 48 Pin QFN (targeted) package option

• Renamed KS8001 to KSZ8001 throughout data sheet

• Added mechanical info for SSOP package

• Updated package thermal resistance

Rev. 1.02 (30 Jan 2006)

• Updated part ordering information

• Corrected recommended reset circuits to match corresponding description

• Added Micrel disclaimer to last page

• Corrected crystal/oscillator PPM in Reference Clock Connection Diagrams

• Added current consumption for KSZ8001L

• Correct RXC clock pulse width timing in 100BASE-TX MII Receive Timing Dia-

gram

• Added description for Auto MDI/MDI-X mode in register 1f.15

• Updated description for MDI/MDI-X select in register 1f.14

• Corrected Auto-Negotiation Complete bit, register 1f.7, to read only

• Added “Circuit Design Reference for Power Supply” section

• Updated Pin Description for the following pins: MDIO, VDDIO, VDDC, RX+, RX-

, TX+, TX-, XI, XO

Rev. 1.01 (16 May 2005)

• Changed REXT value to 6.65 K

• Removed preliminary status

• Added KSZ8001S to ordering information

• Added lead-free part numbers

Rev. 1.00 (31 Mar 2005)

Rev. 0.82 (25 Jan 2005)

• LinkMD distance coefficient changed to 0.39

• Interrupt register status bits set to RO/SC

• Recommended reset circuit added

• RMII timing added

Rev. 0.81 (17 Sep 2004)

Rev. 0.8 (9 Aug 2004)

• Updated series resistance for crystal specification to 40 

• Updated pin 38 (VDDRCV) definition to 3.3V

• Corrected pin configuration diagrams to reflect NC on pins 42 and 43

• Updated crystal tolerance to +/- 50 ppm

PRELIMINARY (25 Mar 2004) Preliminary data

 2009-2019 Microchip Technology Inc.

DS00003062A-page 47

KSZ8001L/S

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make

files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-

tains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s

guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion

groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-

nars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive

e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or

development tool of interest.

To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-

cation” and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales

offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-

ment.

Technical support is available through the web site at: http://www.microchip.com/support

DS00003062A-page 48

 2009-2019 Microchip Technology Inc.

KSZ8001L/S

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

[X]

XXX

[X]⁽¹⁾

Examples:

-

a)

KSZ8001L

Temperature

Range

Package

Tape and Reel

Option

Commercial Temperature, Integrated LDO

48-pin LQFP RoHS Compliant Pkg, Tray

KSZ8001L-TR

b)

Commercial Temperature, Integrated LDO

48-pin LQFP RoHS Compliant Pkg, Tape &

Reel

(2)

Device:

KSZ8001L , KSZ8001S

c)

d)

KSZ8001LI

Temperature:

Package:

Blank

I

=

0C to +70C (Commercial)

-40C to +85C (Industrial)

Industrial Temperature, Integrated LDO

48-pin LQFP RoHS Compliant Pkg, Tray

KSZ8001LI-TR

Industrial Temperature, Integrated LDO

48-pin LQFP RoHS Compliant Pkg, Tape &

Reel

S

=

48-pin SSOP

(2)

48-pin LQFP also offered

e)

f)

KSZ8001SL

Commercial Temperature, no Integrated LDO

48-pin SSOP RoHS Compliant Pkg, Tape &

Reel

Tape and Reel Option:

Blank = Standard packaging (tray)

TR

(1)

KSZ8001SL-TR

= Tape and Reel

Commercial Temperature, no Integrated LDO

48-pin SSOP RoHS Compliant Pkg, Tape &

Reel

Note 1: Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes

and is not printed on the device package.

Check with your Microchip Sales Office

for package availability with the Tape and

Reel option.

2: L = built-in 1.8V regulator

 2009-2019 Microchip Technology Inc.

DS00003062A-page 49

KSZ8001L/S

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be

superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO

REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-

chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold

harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or

otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,

CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,

MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,

PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and

other countries.

APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero,

motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux,

TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the

U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,

CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,

ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,

Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,

PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,

SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in

other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other

countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 9781522444473

For information regarding Microchip’s Quality Management Systems,

please visit www.microchip.com/quality.

DS00003062A-page 50

 2009-2019 Microchip Technology Inc.

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Australia - Sydney

Tel: 61-2-9868-6733

India - Bangalore

Tel: 91-80-3090-4444

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

China - Beijing

Tel: 86-10-8569-7000

India - New Delhi

Tel: 91-11-4160-8631

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

China - Chengdu

Tel: 86-28-8665-5511

India - Pune

Tel: 91-20-4121-0141

Finland - Espoo

Tel: 358-9-4520-820

China - Chongqing

Tel: 86-23-8980-9588

Japan - Osaka

Tel: 81-6-6152-7160

Web Address:

www.microchip.com

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

China - Dongguan

Tel: 86-769-8702-9880

Japan - Tokyo

Tel: 81-3-6880- 3770

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Guangzhou

Tel: 86-20-8755-8029

Korea - Daegu

Tel: 82-53-744-4301

Germany - Garching

Tel: 49-8931-9700

China - Hangzhou

Tel: 86-571-8792-8115

Korea - Seoul

Tel: 82-2-554-7200

Germany - Haan

Tel: 49-2129-3766400

Austin, TX

Tel: 512-257-3370

China - Hong Kong SAR

Tel: 852-2943-5100

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Germany - Heilbronn

Tel: 49-7131-72400

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

China - Nanjing

Tel: 86-25-8473-2460

Malaysia - Penang

Tel: 60-4-227-8870

Germany - Karlsruhe

Tel: 49-721-625370

China - Qingdao

Philippines - Manila

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shanghai

Tel: 86-21-3326-8000

Singapore

Tel: 65-6334-8870

Germany - Rosenheim

Tel: 49-8031-354-560

China - Shenyang

Tel: 86-24-2334-2829

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

China - Shenzhen

Tel: 86-755-8864-2200

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7288-4388

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

DS00003062A-page 51

 2009-2019 Microchip Technology Inc.

05/14/19


型号：	KSZ8001SIS-TR
厂家：	MICROCHIP
描述：	1.8V, 3.3V 10/100BASE-T/TX/FX Physical Layer Transceiver 局域网（LAN）标准
文件：	总51页 (文件大小：542K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KSZ8001SIS-TR [MICROCHIP]

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