KSZ8895MLUB-EVAL [MICROCHIP]
Integrated 5-Port 10/100 Managed Switch;
| 型号： | KSZ8895MLUB-EVAL |
| 厂家： | 
MICROCHIP |
| 描述： | Integrated 5-Port 10/100 Managed Switch 局域网（LAN）标准 |
| 文件： | 总120页 (文件大小：1657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KSZ8895MLUB
Integrated 5-Port 10/100 Managed Switch
Revision 2.1
General Description
The KSZ8895MLUB is a highly-integrated Layer 2-
managed 5-port switch with an optimized design and
plentiful features, qualified to meet AEC-Q100 standard
for automotive applications. It is designed for cost-
sensitive 10/100Mbps 5-port switch systems with on-chip
termination, lowest power consumption and internal core
power controller. These features will save more system
cost. It has 1.4Gbps high-performance memory
bandwidth, shared memory based switch fabric with full
non-blocking configuration. It also provides an extensive
feature set such as power management, programmable
rate limit and priority ratio, tag/port-based VLAN, packets
The KSZ8895MLUB consists of 10/100 PHYs with
patented and enhanced mixed-signal technology, media
access control (MAC) units, a high-speed non-blocking
switch fabric, a dedicated address lookup engine, and an
on-chip frame buffer memory. The KSZ8895MLUB
contains five MACs and four integrated PHYs. All PHYs
support 10/100Base-T/TX.
All registers of MACs and PHYs units can be managed
by the SPI interface or the SMI interface. MIIM registers
of the PHYs can be accessed through the MDC/MDIO
interface. EEPROM can set all control registers for the
unmanaged mode.
filtering,
quality-of-service
(QoS)
four-queue
The KSZ8895MLUB provides multiple CPU control/data
interfaces to effectively address both current and
emerging fast Ethernet applications.
prioritization, management interface, and MIB counters.
Port 5 is a MAC 5 MII interface with PHY mode as
default at switch side. The SW5-MII interface can be
connected to a processor with a MAC MII interface.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Revision 2.1
April 1, 2014
Micrel, Inc.
KSZ8895MLUB
Features
Advanced Switch Features
Integrated 5-Port 10/100 Ethernet Switch
•
IEEE 802.1q VLAN support for up to 128 VLAN groups
(full-range 4096 of VLAN IDs).
•
New generation switch with five MACs and five PHYs fully
compliant with IEEE 802.3u standard.
•
•
•
Static MAC table supports up to 32 entries.
VLAN ID tag/untag options, per port basis.
•
Non-blocking switch fabric assures fast packet delivery by
utilizing a 1K MAC address lookup table and a store-and-
forward architecture.
IEEE 802.1p/q tag insertion or removal on a per port
basis based on ingress port (egress).
•
•
On-chip 64Kbyte memory for frame buffering (not shared with
1K unicast address table).
•
Programmable rate limiting at the ingress and egress on
a per port basis.
Full duplex IEEE 802.3x flow control (PAUSE) with force mode
option.
•
•
Jitter-free per packet based rate-limiting support.
•
•
•
Half-duplex back pressure flow control.
Broadcast storm protection with percentage control
(global and per port basis).
HP Auto MDI/MDI-X and IEEE Auto crossover support.
Port 5 MAC5 SW5-MII interface supports PHY mode and MAC
mode.
•
•
IEEE 802.1d rapid spanning tree protocol RSTP
support.
•
•
•
7-wire serial network interface (SNI) support for legacy MAC.
Per port LED Indicators for link, activity, and 10/100 speed.
Tail tag mode (1byte added before FCS) support at Port
5 to inform the processor which ingress port receives
the packet.
Register port status support for link, activity, full/half duplex
and 10/100 speed.
•
1.4Gbps high-performance memory bandwidth and
shared memory-based switch fabric with fully non-
blocking configuration.
• Micrel LinkMD® cable diagnostic capabilities for
determining cable opens, shorts, and length.
On-chip terminations and internal biasing technology for cost
down and lowest power consumption.
•
•
•
MII with MAC 5 on Port 5, SW5-MII for MAC 5 MII
interface.
•
Enable/Disable option for huge frame size up to 2000
bytes per frame.
Switch Monitoring Features
•
•
•
•
Port mirroring/monitoring/sniffing: ingress and/or egress traffic
to any port or MII.
IGMP v1/v2 snooping (Ipv4) support for multicast packet
filtering.
MIB counters for fully-compliant statistics gathering 34 MIB
counters per port.
•
•
IPv4/IPv6 QoS support.
Support unknown unicast/multicast address and
unknown VID packet filtering.
Loop-back support for MAC, PHY, and remote diagnostic of
failure.
•
Self-address filtering.
Interrupt for the link change on any ports.
Comprehensive Configuration Register Access
Low Power Dissipation
•
•
•
•
Serial management interface (MDC/MDIO) to all PHYs
registers and SMI interface (MDC/MDIO) to all registers.
High-speed SPI (up to 25MHz) and I2C master Interface
to all internal registers.
•
•
•
Full-chip hardware power-down.
Full-chip software power-down/per port software power down.
Energy-detect mode support < 100mW full-chip power
consumption when all ports have no activity.
I/0 pins strapping and EEPROM to program selective
registers in unmanaged switch mode.
•
Very-low, full-chip power consumption (<0.5W), without extra
power consumption on transformers.
Control registers configurable on the fly (port-priority,
802.1p/d/q, AN…).
•
•
Dynamic clock-tree shutdown feature.
Voltages: Single 3.3V supply with 3.3V VDDIO and Internal
1.2V LDO controller enabled or external 1.2V LDO solution:
QoS/CoS Packet Prioritization Support
•
•
•
•
Per port, 802.1p and DiffServ-based.
−
−
−
Analog VDDAT 3.3V only
VDDIO support 3.3V, 2.5V and 1.8V
Low 1.2V core power
1/2/4-queue QoS prioritization selection.
Programmable weighted fair queuing for ratio control.
Re-mapping of 802.1p priority field per port basis.
•
•
Industrial Temperature Range: –40oC to +85oC.
Available in 128-pin LQFP, lead-free package.
Applications
•
•
•
•
•
In-vehicle diagnostics (OBD)
High-speed software download
Gateway switch
Head unit
Rear seat entertainment
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KSZ8895MLUB
Ordering Information
Part Number
Temperature Range
−40°C to +85°C
Package
Lead Finish/Grade
Pb-Free/Automotive
KSZ8895MLUB
128-Pin LQFP
(Automotive Grade)
KSZ8895MLUB-EVAL Board
Evaluation Board for KSZ8895MLUB
Revision History
Revision
Date
Summary of Changes
1.0
03/16/11
Initial
Update some descriptions, updates for descriptions of SMI mode and IGMP mode, update register
default values, pins type and some parameters.
1.1
09/27/11
Revision 1.1 datasheet reflects the revision A4 silicon (0.13um CMOS technology).
Updates timing data for MII PHY mode.
Update descriptions for VLAN table and I2C master mode.
Update the descriptions for the pins 125 and 126.
Update the equation in the broadcast storm protection section.
Update the operation rating to +/-5% and TTL min/max I/O voltage in different VDDIO. Change I/O
from TTL to CMOS.
Update SPI description from 127 to 255 for all registers.
Update the table of tail tag rules.
2.0
02/21/14
Update description for Register 1 bits [7:4].
Update table 8 from bit [57:55] to bit [58:56].
Update the port register control 2 bit [6] description bits [20:16] change to bits [11:7].
Add evaluation Board in the ordering information table.
Revision 2.0 datasheet reflects the revision B2 silicon (0.11um CMOS technology).
From B2 silicon, add LinkMD feature and ESD to be improved to 5KV.
The part number is changed from KSZ8895MLU to KSZ8895MLUB. Remove port 5 in the pin
configuration and pin description. Update notes description for pin 125 and pin 126 in the pins
descriptions. Update operating rating and electrical characteristics, correct typos.
2.1
03/31/14
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Contents
List of Figures......................................................................................................................................................................13
List of Tables.......................................................................................................................................................................14
Pin Configuration................................................................................................................................................................15
Pin Description....................................................................................................................................................................16
Pin for Strap-In Options......................................................................................................................................................22
Introduction .........................................................................................................................................................................25
Physical Layer Transceiver................................................................................................................................................25
100BASE-TX Transmit .....................................................................................................................................................25
10BASE-T Transmit..........................................................................................................................................................25
10BASE-T Receive...........................................................................................................................................................26
MDI/MDI-X Auto Crossover ..............................................................................................................................................26
Auto-Negotiation ...............................................................................................................................................................27
LinkMD® Cable Diagnostics..............................................................................................................................................29
On-Chip Termination Resistors ........................................................................................................................................30
Internal 1.2V LDO Controller ............................................................................................................................................30
Power Management ............................................................................................................................................................31
Normal Operation Mode ...................................................................................................................................................31
Energy Detect Mode .........................................................................................................................................................31
Soft Power-Down Mode....................................................................................................................................................32
Power-Saving Mode..........................................................................................................................................................32
Port-Based Power-Down Mode ........................................................................................................................................32
Switch Core.......................................................................................................................................................................32
Address Look-Up ..............................................................................................................................................................32
Learning............................................................................................................................................................................32
Migration ...........................................................................................................................................................................32
Aging.................................................................................................................................................................................32
Forwarding........................................................................................................................................................................33
Switching Engine ..............................................................................................................................................................33
Media Access Controller (MAC) Operation ......................................................................................................................33
MII Interface Operation .....................................................................................................................................................36
Port 5 MAC 5 SW5-MII Interface ......................................................................................................................................36
SNI Interface Operation ....................................................................................................................................................37
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Advanced Functionality......................................................................................................................................................39
QoS Priority Support.........................................................................................................................................................39
Port-Based Priority............................................................................................................................................................39
802.1p-Based Priority .......................................................................................................................................................39
Spanning Tree Support.....................................................................................................................................................40
Rapid Spanning Tree Support ..........................................................................................................................................41
Tail Tagging Mode ............................................................................................................................................................41
IGMP Support ...................................................................................................................................................................42
Port Mirroring Support ......................................................................................................................................................43
VLAN Support...................................................................................................................................................................43
Rate Limiting Support .......................................................................................................................................................44
Ingress Rate Limit.............................................................................................................................................................44
Egress Rate Limit..............................................................................................................................................................44
Transmit Queue Ratio Programming................................................................................................................................45
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ........................45
Configuration Interfaces.....................................................................................................................................................46
I2C Master Serial Bus Configuration.................................................................................................................................46
SPI Slave Serial Bus Configuration ..................................................................................................................................46
MII Management Interface (MIIM) ....................................................................................................................................49
Serial Management Interface (SMI)..................................................................................................................................49
Register Description ...........................................................................................................................................................51
Global Registers..................................................................................................................................................................53
Register 0 (0×00): Chip ID0..............................................................................................................................................53
Register 1 (0×01): Chip ID1 / Start Switch........................................................................................................................53
Register 2 (0×02): Global Control 0..................................................................................................................................53
Register 2 (0×02): Global Control 0..................................................................................................................................54
Register 3 (0×03): Global Control 1..................................................................................................................................54
Register 3 (0×03): Global Control 1..................................................................................................................................55
Register 4 (0×04): Global Control 2..................................................................................................................................56
Register 4 (0×04): Global Control 2..................................................................................................................................57
Register 5 (0×05): Global Control 3..................................................................................................................................57
Register 6 (0×06): Global Control 4..................................................................................................................................58
Register 7 (0×07): Global Control 5..................................................................................................................................59
Register 8 (0×08): Global Control 6..................................................................................................................................59
Register 9 (0×09): Global Control 7..................................................................................................................................59
Register 10 (0×0A): Global Control 8................................................................................................................................59
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KSZ8895MLUB
Register 11 (0×0B): Global Control 9................................................................................................................................59
Register 11 (0×0B): Global Control 9................................................................................................................................60
Register 12 (0×0C): Global Control 10 .............................................................................................................................61
Register 13 (0×0D): Global Control 11 .............................................................................................................................61
Register 14 (0×0E): Power-Down Management Control 1 ...............................................................................................62
Register 14 (0×0E): Power-Down Management Control 1 ...............................................................................................62
Register 15 (0×0F): Power-Down Management Control 2 ...............................................................................................62
Port Registers......................................................................................................................................................................63
Register 16 (0×10): Port 1 Control 0.................................................................................................................................63
Register 32 (0×20): Port 2 Control 0.................................................................................................................................63
Register 48 (0×30): Port 3 Control 0.................................................................................................................................63
Register 64 (0×40): Port 4 Control 0.................................................................................................................................63
Register 80 (0×50): Port 5 Control 0.................................................................................................................................63
Register 16 (0×10): Port 1 Control 0.................................................................................................................................64
Register 32 (0×20): Port 2 Control 0.................................................................................................................................64
Register 48 (0×30): Port 3 Control 0.................................................................................................................................64
Register 64 (0×40): Port 4 Control 0.................................................................................................................................64
Register 80 (0×50): Port 5 Control 0.................................................................................................................................64
Register 17 (0×11): Port 1 Control 1.................................................................................................................................64
Register 33 (0×21): Port 2 Control 1.................................................................................................................................64
Register 49 (0×31): Port 3 Control 1.................................................................................................................................64
Register 65 (0×41): Port 4 Control 1.................................................................................................................................64
Register 81 (0×51): Port 4 Control 1.................................................................................................................................64
Register 18 (0×12): Port 1 Control 2.................................................................................................................................65
Register 34 (0×22): Port 2 Control 2.................................................................................................................................65
Register 50 (0×32): Port 3 Control 2.................................................................................................................................65
Register 66 (0×42): Port 4 Control 2.................................................................................................................................65
Register 82 (0×52): Port 5 Control 2.................................................................................................................................65
Register 18 (0×12): Port 1 Control 2.................................................................................................................................66
Register 34 (0×22): Port 2 Control 2.................................................................................................................................66
Register 50 (0×32): Port 3 Control 2.................................................................................................................................66
Register 66 (0×42): Port 4 Control 2.................................................................................................................................66
Register 82 (0×52): Port 5 Control 2.................................................................................................................................66
Register 19 (0×13): Port 1 Control 3.................................................................................................................................67
Register 35 (0×23): Port 2 Control 3.................................................................................................................................67
Register 51 (0×33): Port 3 Control 3.................................................................................................................................67
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KSZ8895MLUB
Register 67 (0×43): Port 4 Control 3.................................................................................................................................67
Register 83 (0×53): Port 5 Control 3.................................................................................................................................67
Register 20 (0×14): Port 1 Control 4.................................................................................................................................67
Register 36 (0×24): Port 2 Control 4.................................................................................................................................67
Register 52 (0×34): Port 3 Control 4.................................................................................................................................67
Register 68 (0×44): Port 4 Control 4.................................................................................................................................67
Register 84 (0×54): Port 5 Control 4.................................................................................................................................67
Register 87 (0×57): Reserved Control Register ...............................................................................................................67
Register 25 (0×19): Port 1 Status 0 ..................................................................................................................................68
Register 41 (0×29): Port 2 Status 0 ..................................................................................................................................68
Register 57 (0×39): Port 3 Status 0 ..................................................................................................................................68
Register 73 (0×49): Port 4 Status 0 ..................................................................................................................................68
Register 89 (0×59): Reserved...........................................................................................................................................68
Register 26 (0×1A): Port 1 PHY Special Control/Status...................................................................................................68
Register 42 (0×2A): Port 2 PHY Special Control/Status...................................................................................................68
Register 58 (0×3A): Port 3 PHY Special Control/Status...................................................................................................68
Register 74 (0×4A): Port 4 PHY Special Control/Status...................................................................................................68
Register 90 (0×5A): Reserved ..........................................................................................................................................68
Register 27 (0×1B): Port 1 LinkMD Result .......................................................................................................................69
Register 43 (0×2B): Port 2 LinkMD Result .......................................................................................................................69
Register 59 (0×3B): Port 3 LinkMD Result .......................................................................................................................69
Register 75 (0×4B): Port 4 LinkMD Result .......................................................................................................................69
Register 91 (0×5B): Reserved ..........................................................................................................................................69
Register 28 (0×1C): Port 1 Control 5 ................................................................................................................................69
Register 44 (0×2C): Port 2 Control 5 ................................................................................................................................69
Register 60 (0×3C): Port 3 Control 5 ................................................................................................................................69
Register 76 (0×4C): Port 4 Control 5 ................................................................................................................................69
Register 92 (0×5C): Reserved..........................................................................................................................................69
Register 28 (0×1C): Port 1 Control 5 ................................................................................................................................70
Register 44 (0×2C): Port 2 Control 5 ................................................................................................................................70
Register 60 (0×3C): Port 3 Control 5 ................................................................................................................................70
Register 76 (0×4C): Port 4 Control 5 ................................................................................................................................70
Register 92 (0×5C): Reserved..........................................................................................................................................70
Register 29 (0×1D): Port 1 Control 6 ................................................................................................................................70
Register 45 (0×2D): Port 2 Control 6 ................................................................................................................................70
Register 61 (0×3D): Port 3 Control 6 ................................................................................................................................70
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KSZ8895MLUB
Register 77 (0×4D): Port 4 Control 6 ................................................................................................................................70
Register 93 (0×5D): Reserved..........................................................................................................................................70
Register 29 (0×1D): Port 1 Control 6 ................................................................................................................................71
Register 45 (0×2D): Port 2 Control 6 ................................................................................................................................71
Register 61 (0×3D): Port 3 Control 6 ................................................................................................................................71
Register 77 (0×4D): Port 4 Control 6 ................................................................................................................................71
Register 93 (0×5D): Reserved..........................................................................................................................................71
Register 30 (0×1E): Port 1 Status 1..................................................................................................................................71
Register 46 (0×2E): Port 2 Status 1..................................................................................................................................71
Register 62 (0×3E): Port 3 Status 1..................................................................................................................................71
Register 78 (0×4E): Port 4 Status 1..................................................................................................................................71
Register 94 (0×5E): Reserved ..........................................................................................................................................71
Register 31 (0×1F): Port 1 Control 7 and Status 2 ...........................................................................................................72
Register 47 (0×2F): Port 2 Control 7 and Status 2 ...........................................................................................................72
Register 63 (0×3F): Port 3 Control 7 and Status 2 ...........................................................................................................72
Register 79 (0×4F): Port 4 Control 7 and Status 2 ...........................................................................................................72
Register 95 (0×5F): Reserved ..........................................................................................................................................72
Advanced Control Registers..............................................................................................................................................73
Register 104 (0×68): MAC Address Register 0 ................................................................................................................73
Register 105 (0×69): MAC Address Register 1 ................................................................................................................73
Register 106 (0×6A): MAC Address Register 2................................................................................................................73
Register 107 (0×6B): MAC Address Register 3................................................................................................................73
Register 108 (0×6C): MAC Address Register 4................................................................................................................73
Register 109 (0×6D): MAC Address Register 5................................................................................................................73
Register 110 (0×6E): Indirect Access Control 0 ...............................................................................................................74
Register 111 (0×6F): Indirect Access Control 1................................................................................................................74
Register 112 (0×70): Indirect Data Register 8..................................................................................................................74
Register 113 (0×71): Indirect Data Register 7..................................................................................................................74
Register 114 (0×72): Indirect Data Register 6..................................................................................................................74
Register 115 (0×73): Indirect Data Register 5..................................................................................................................74
Register 116 (0×74): Indirect Data Register 4..................................................................................................................74
Register 117 (0×75): Indirect Data Register 3..................................................................................................................75
Register 118 (0×76): Indirect Data Register 2..................................................................................................................75
Register 119 (0×77): Indirect Data Register 1..................................................................................................................75
Register 120 (0×78): Indirect Data Register 0..................................................................................................................75
Register 124 (0x7C): Interrupt Status Register ................................................................................................................75
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KSZ8895MLUB
Register 125 (0x7D): Interrupt Mask Register..................................................................................................................76
Register 128 (0x80): Global Control 12 ............................................................................................................................76
Register 129 (0x81): Global Control 13 ............................................................................................................................76
Register 130 (0x82): Global Control 14 ............................................................................................................................77
Register 131 (0x83): Global Control 15 ............................................................................................................................77
Register 132 (0x84): Global Control 16 ............................................................................................................................78
Register 133(0x85): Global Control 17 .............................................................................................................................78
Register 134 (0x86): Global Control 18 ............................................................................................................................79
Register 135 (0x87): Global Control 19 ............................................................................................................................79
Register 144 (0x90): TOS Priority Control Register 0 ......................................................................................................80
Register 145 (0x91): TOS Priority Control Register 1 ......................................................................................................80
Register 146 (0x92): TOS Priority Control Register 2 ......................................................................................................80
Register 147 (0x93): TOS Priority Control Register 3 ......................................................................................................80
Register 148 (0x94): TOS Priority Control Register 4 ......................................................................................................81
Register 149 (0x95): TOS Priority Control Register 5 ......................................................................................................81
Register 150 (0x96): TOS Priority Control Register 6 ......................................................................................................81
Register 151 (0x97): TOS Priority Control Register 7 ......................................................................................................81
Register 152 (0x98): TOS Priority Control Register 8 ......................................................................................................81
Register 153 (0x99): TOS Priority Control Register 9 ......................................................................................................82
Register 154 (0x9A): TOS Priority Control Register 10....................................................................................................82
Register 155 (0x9B): TOS Priority Control Register 11....................................................................................................82
Register 156 (0x9C): TOS Priority Control Register 12....................................................................................................82
Register 157 (0x9D): TOS Priority Control Register 13....................................................................................................82
Register 158 (0x9E): TOS Priority Control Register 14....................................................................................................83
Register 159 (0x9F): TOS Priority Control Register 15 ....................................................................................................83
Register 176 (0xB0): Port 1 Control 8...............................................................................................................................83
Register 192 (0xC0): Port 2 Control 8 ..............................................................................................................................83
Register 208 (0xD0): Port 3 Control 8 ..............................................................................................................................83
Register 224 (0xE0): Port 4 Control 8...............................................................................................................................83
Register 240 (0xF0): Port 5 Control 8...............................................................................................................................83
Register 176 (0xB0): Port 1 Control 8...............................................................................................................................84
Register 192 (0xC0): Port 2 Control 8 ..............................................................................................................................84
Register 208 (0xD0): Port 3 Control 8 ..............................................................................................................................84
Register 224 (0xE0): Port 4 Control 8...............................................................................................................................84
Register 240 (0xF0): Port 5 Control 8...............................................................................................................................84
Register 177 (0xB1): Port 1 Control 9...............................................................................................................................84
Register 193 (0xC1): Port 2 Control 9 ..............................................................................................................................84
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Register 209 (0xD1): Port 3 Control 9 ..............................................................................................................................84
Register 225 (0xE1): Port 4 Control 9...............................................................................................................................84
Register 241 (0xF1): Port 5 Control 9...............................................................................................................................84
Register 178 (0xB2): Port 1 Control 10 ............................................................................................................................85
Register 194 (0xC2): Port 2 Control 10 ............................................................................................................................85
Register 210 (0xD2): Port 3 Control 10 ............................................................................................................................85
Register 226 (0xE2): Port 4 Control 10 ............................................................................................................................85
Register 242 (0xF2): Port 5 Control 10.............................................................................................................................85
Register 179 (0xB3): Port 1 Control 11 ............................................................................................................................85
Register 195 (0xC3): Port 2 Control 11 ............................................................................................................................85
Register 211 (0xD3): Port 3 Control 11 ............................................................................................................................85
Register 227 (0xE3): Port 4 Control 11 ............................................................................................................................85
Register 243 (0xF3): Port 5 Control 11.............................................................................................................................85
Register 180 (0xB4): Port 1 Control 12 ............................................................................................................................85
Register 196 (0xC4): Port 2 Control 12 ............................................................................................................................85
Register 212 (0xD4): Port 3 Control 12 ............................................................................................................................85
Register 228 (0xE4): Port 4 Control 12 ............................................................................................................................85
Register 244 (0xF4): Port 5 Control 12.............................................................................................................................85
Register 181 (0xB5): Port 1 Control 13 ............................................................................................................................86
Register 197 (0xC5): Port 2 Control 13 ............................................................................................................................86
Register 213 (0xD5): Port 3 Control 13 ............................................................................................................................86
Register 229 (0xE5): Port 4 Control 13 ............................................................................................................................86
Register 245 (0xF5): Port 5 Control 13.............................................................................................................................86
Register 182 (0xB6): Port 1 Rate Limit Control ................................................................................................................86
Register 198 (0xC6): Port 2 Rate Limit Control................................................................................................................86
Register 214 (0xD6): Port 3 Rate Limit Control................................................................................................................86
Register 230 (0xE6): Port 4 Rate Limit Control ................................................................................................................86
Register 246 (0xF6): Port 5 Rate Limit Control ................................................................................................................86
Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1..........................................................................................87
Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1..........................................................................................87
Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1..........................................................................................87
Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1..........................................................................................87
Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1..........................................................................................87
Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2..........................................................................................87
Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2..........................................................................................87
Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2..........................................................................................87
Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2..........................................................................................87
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Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2..........................................................................................87
Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3..........................................................................................87
Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3..........................................................................................87
Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3..........................................................................................87
Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3..........................................................................................87
Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3..........................................................................................87
Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4 .........................................................................................88
Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4 .........................................................................................88
Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4 .........................................................................................88
Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4 .........................................................................................88
Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4..........................................................................................88
Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1 ..........................................................................................88
Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1 ..........................................................................................88
Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1 ..........................................................................................88
Register 235 (0xEB): Port 4 Queue 0 Egress Limit Control 1 ..........................................................................................88
Register 251 (0xFB): Port 5 Queue 0 Egress Limit Control 1...........................................................................................88
Register 188 (0xBC): Port 1 Queue 1 Egress Limit Control 2 ..........................................................................................88
Register 204 (0xCC): Port 2 Queue 1 Egress Limit Control 2..........................................................................................88
Register 220 (0xDC): Port 3 Queue 1 Egress Limit Control 2..........................................................................................88
Register 236 (0xEC): Port 4 Queue 1 Egress Limit Control 2 ..........................................................................................88
Register 252 (0xFC): Port 5 Queue 1 Egress Limit Control 2 ..........................................................................................88
Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3 ..........................................................................................89
Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3..........................................................................................89
Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3..........................................................................................89
Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3 ..........................................................................................89
Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3 ..........................................................................................89
Register 190 (0xBE): Port 1 Queue 3 Egress Limit Control 4 ..........................................................................................89
Register 206 (0xCE): Port 2 Queue 3 Egress Limit Control 4 ..........................................................................................89
Register 222 (0xDE): Port 3 Queue 3 Egress Limit Control 4 ..........................................................................................89
Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4 ..........................................................................................89
Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4...........................................................................................89
Register 191(0xBF): Testing Register ..............................................................................................................................91
Register 207(0xCF): Reserved Control Register.............................................................................................................91
Register 223(0xDF): Test Register 2................................................................................................................................91
Register 239(0xEF): Test Register 3 ................................................................................................................................91
Register 255(0xFF): Testing Register4.............................................................................................................................91
April 1, 2014
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KSZ8895MLUB
Static MAC Address Table .................................................................................................................................................92
VLAN Table ..........................................................................................................................................................................94
Dynamic MAC Address Table ............................................................................................................................................96
Management Information Base (MIB) Counters...............................................................................................................98
Port 1 MIB Counter Indirect Memory Offsets....................................................................................................................98
Format of “Per port” MIB Counter.....................................................................................................................................99
MIIM Registers...................................................................................................................................................................102
Register 0h: MII Control..................................................................................................................................................102
Register 1h: MII Status ...................................................................................................................................................103
Register 2h: PHYID HIGH ..............................................................................................................................................103
Register 3h: PHYID LOW ...............................................................................................................................................103
Register 4h: Advertisement Ability..................................................................................................................................104
Register 5h: Link Partner Ability .....................................................................................................................................104
Register 1dh: LinkMD Control/Status ............................................................................................................................105
Register 1fh: PHY Special Control/Status ......................................................................................................................105
Absolute Maximum Ratings.............................................................................................................................................107
Operating Ratings.............................................................................................................................................................107
Electrical Characteristics .................................................................................................................................................107
Timing Diagrams ...............................................................................................................................................................109
EEPROM Timing.............................................................................................................................................................109
SNI Timing ......................................................................................................................................................................110
SPI Timing ......................................................................................................................................................................113
Auto-Negotiation Timing .................................................................................................................................................115
Reset Timing...................................................................................................................................................................116
Reset Circuit Diagram.....................................................................................................................................................117
Isolation Transformer Selection ......................................................................................................................................118
Reference Crystal Selection.............................................................................................................................................118
Package Information.........................................................................................................................................................119
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Revision 2.1
Micrel, Inc.
KSZ8895MLUB
List of Figures
Figure 1. Typical Straight Cable Connection ........................................................................................................................26
Figure 2. Typical Crossover Cable Connection ....................................................................................................................27
Figure 3. Auto-Negotiation ....................................................................................................................................................28
Figure 4. Destination Address Lookup Flow Chart (Stage 1) ...............................................................................................34
Figure 5. Destination Address Resolution Flow Chart (Stage 2) ..........................................................................................35
Figure 6. 802.1p Priority Field Format ..................................................................................................................................39
Figure 7. Tail Tag Frame Format..........................................................................................................................................41
Figure 8. KSZ8895MLUB EEPROM Configuration Timing Diagram ....................................................................................46
Figure 9. SPI Write Data Cycle .............................................................................................................................................47
Figure 10. SPI Read Data Cycle...........................................................................................................................................47
Figure 11. SPI Multiple Write ................................................................................................................................................48
Figure 12. SPI Multiple Read ................................................................................................................................................48
Figure 13. EEPROM Interface Input Receive Timing Diagram...........................................................................................109
Figure 14. EEPROM Interface Output Transmit Timing Diagram.......................................................................................109
Figure 15. SNI Input Timing ................................................................................................................................................110
Figure 16. SNI Output Timing .............................................................................................................................................110
Figure 17. MAC Mode MII Timing – Data Received from MII.............................................................................................111
Figure 18. MAC Mode MII Timing – Data Transmitted from MII.........................................................................................111
Figure 19. PHY Mode MII Timing – Data Received from MII..............................................................................................112
Figure 20. PHY Mode MII Timing – Data Transmitted from MII..........................................................................................112
Figure 21. SPI Input Timing ................................................................................................................................................113
Figure 22. SPI Output Timing..............................................................................................................................................114
Figure 23. Auto-Negotiation Timing ....................................................................................................................................115
Figure 24. Reset Timing......................................................................................................................................................116
Figure 25. Recommended Reset Circuit.............................................................................................................................117
Figure 26. Recommended Circuit for Interfacing with CPU/FPGA Reset...........................................................................117
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Micrel, Inc.
KSZ8895MLUB
List of Tables
Table 1. MDI/MDI-X Pin Definitions ......................................................................................................................................26
Table 2. Internal Function Block Status ................................................................................................................................31
Table 3. Switch MAC 5 MII Signals.......................................................................................................................................37
Table 4. SNI Signals .............................................................................................................................................................38
Table 5. Tail Tag Rules.........................................................................................................................................................42
Table 6. FID+DA Look-Up in the VLAN Mode ......................................................................................................................43
Table 7. FID+SA Look-Up in the VLAN Mode ......................................................................................................................44
Table 8. SPI Connections .....................................................................................................................................................47
Table 9. MII Management Interface Frame Format..............................................................................................................49
Table 10. Serial Management Interface (SMI) Frame Format..............................................................................................49
Table 11. Data Rate Selection in 100BT...............................................................................................................................90
Table 12. Data Rate Selection in 10BT.................................................................................................................................90
Table 13. Format of Static MAC Table for Read (32 Entries)...............................................................................................92
Table 14. Format of Static MAC Table for Writes (32 Entries) .............................................................................................93
Table 15. Format of Static VLAN Table (Support Max 4096 VLAN ID Entries and 128 Active VLANs)...............................94
Table 16. VLAN ID and Indirect Registers............................................................................................................................95
Table 17. Format of Dynamic MAC Address Table (1K Entries) ..........................................................................................96
Table 18. All Port Dropped Packet MIB Counters.................................................................................................................99
Table 19. Format of All Dropped Packet MIB Counters......................................................................................................100
Table 20. EEPROM Timing Parameters.............................................................................................................................109
Table 21. SNI Timing Parameters.......................................................................................................................................110
Table 22. MAC Mode MII Timing Parameters.....................................................................................................................111
Table 23. PHY Mode MII Timing Parameters .....................................................................................................................112
Table 24. SPI Input Timing Parameters..............................................................................................................................113
Table 25. SPI Output Timing Parameters...........................................................................................................................114
Table 26. Auto-Negotiation Timing Parameters..................................................................................................................115
Table 27. Reset Timing Parameters ...................................................................................................................................116
Table 28. Transformer Selection Criteria............................................................................................................................118
Table 29. Qualified Magnetic Vendors................................................................................................................................118
Table 30. Typical Reference Crystal Characteristics..........................................................................................................118
April 1, 2014
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Revision 2.1
Micrel, Inc.
KSZ8895MLUB
Pin Configuration
97
98
99
100
LED3-1
LED3-0
GNDD
VDDIO
LED2-2
LED2-1
LED2-0
LED1-2
LED1-1
LED1-0
MDC
MDIO
PMRXD1
PMRXD2
PMRXD3
PMRXDV
PMRXC
VDDIO
GNDD
PMTXC
PMTXER
PMTXD0
PMTXD1
PMTXD2
PMTXD3
PMTXEN
VDDC
GNDD
INTR_N
PWRDN_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDAT
NC
NC
GNDA
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
SPIQ
KSZ8895MLUB
SPIC/SCL
SPID/SDA
SPIS_N
PS1
PS0
RST_N
GNDD
VDDC
TESTEN
SCANEN
NC
(Top View)
X1
X2
NC
NC
LDO_O
IN_PWR_SEL
GNDA
TEST2
34
33
128-Pin LQFP
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Revision 2.1
Micrel, Inc.
KSZ8895MLUB
Pin Description
Pin Number
Pin Name
Type(1)
Port
Pin Function(2)
Disable auto MDI/MDI-X.
PD (default) = normal operation.
PU = disable auto MDI/MDI-X on all ports.
1
MDI-XDIS
Ipd
1 − 5
2
3
GNDA
VDDAR
RXP1
GND
Analog ground.
P
1.2V analog VDD.
4
I
1
1
Physical receive signal + (differential).
Physical receive signal – (differential).
Analog ground.
5
RXM1
GNDA
TXP1
I
6
GND
7
O
1
1
Physical transmit signal + (differential).
Physical transmit signal – (differential).
8
TXM1
VDDAT
RXP2
O
9
P
3.3V analog VDD.
10
11
12
13
14
15
16
I
I
2
2
Physical receive signal + (differential).
Physical receive signal – (differential).
Analog ground.
RXM2
GNDA
TXP2
GND
O
2
2
Physical transmit signal + (differential).
Physical transmit signal – (differential).
TXM2
VDDAR
GNDA
O
P
1.2V analog VDD
.
GND
Analog ground.
Set physical transmit output current. Pull-down with a
12.4kΩ1% resistor.
17
ISET
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
VDDAT
RXP3
RXM3
GNDA
TXP3
TXM3
VDDAT
RXP4
RXM4
GNDA
TXP4
TXM4
GNDA
VDDAR
NC
P
I
3.3V analog VDD.
3
3
Physical receive signal + (differential).
Physical receive signal - (differential).
Analog ground.
I
GND
O
3
3
Physical transmit signal + (differential).
Physical transmit signal – (differential).
O
P
3.3V analog VDD.
I
4
4
Physical receive signal + (differential).
Physical receive signal - (differential).
Analog ground.
I
GND
O
4
4
Physical transmit signal + (differential).
Physical transmit signal – (differential).
Analog ground.
O
GND
P
1.2V analog VDD
.
NC
NC
GND
NC
NC
P
No connect.
NC
No connect.
GNDA
NC
Analog ground.
No connect.
NC
No connect.
VDDAT
3.3V analog VDD
.
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Revision 2.1
Micrel, Inc.
KSZ8895MLUB
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
NC
NC
NC
NC
NC
NC
NC
NC
NC
Ipu
Port
Pin Function(2)
No connect.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
NC
NC
No connect.
NC
No connect.
NC
No connect.
NC
No connect.
NC
No connect.
NC
No connect.
NC
No connect.
NC
No connect.
PWRDN_N
INTR_N
GNDD
VDDC
PMTXEN
PMTXD3
PMTXD2
PMTXD1
PMTXD0
PMTXER
PMTXC
GNDD
VDDIO
PMRXC
PMRXDV
Full-chip power down. Active low.
Interrupt. This pin is Open-Drain output pin.
Digital ground.
Opu
GND
P
1.2V digital core VDD
.
Ipd
5
5
5
5
5
5
5
Reserved for MLUB. No connect.
Reserved for MLUB. No connect.
Reserved for MLUB. No connect.
Reserved for MLUB. No connect.
Reserved for MLUB. No connect.
Reserved for MLUB. No connect.
Reserved for MLUB. No connect.
Digital ground.
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
GND
P
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
Reserved for MLUB. No connect.
Reserved for MLUB. No connect.
I/O
5
5
Ipd/O
Reserved for MLUB.
Strap option:
62
63
64
65
66
PMRXD3
PMRXD2
PMRXD1
PMRXD0
PMRXER
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
5
5
5
5
5
PD (default) = enable flow control.
PU = disable flow control.
Reserved for MLUB.
Strap option:
PD (default) = disable back pressure.
PU = enable back pressure.
Reserved for MLUB.
Strap option:
PD (default) = drop excessive collision packets.
PU = does not drop excessive collision packets.
Reserved for MLUB.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex mode.
PU = enable for performance enhancement.
Reserved for MLUB.
Strap option:
PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
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Revision 2.1
Micrel, Inc.
KSZ8895MLUB
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
Port
Pin Function(2)
Reserved for MLUB.
Strap option for port 4 only.
67
PCRS
Ipd/O
5
PD (default) = force half-duplex if auto-negotiation is disabled or fails.
PU = force full-duplex if auto negotiation is disabled or fails. Refer to Register
76.
Reserved for MLUB.
Strap option for port 4 only.
PD (default) = no force flow control, normal operation.
PU = force flow control. Refer to Register 66.
68
PCOL
Ipd/O
5
69
70
71
72
73
74
SMTXEN
SMTXD3
SMTXD2
SMTXD1
SMTXD0
SMTXER
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Port 5 Switch MII transmit enable.
Port 5 Switch MII transmit bit 3.
Port 5 Switch MII transmit bit 2.
Port 5 Switch MII transmit bit 1.
Port 5 Switch MII transmit bit 0.
Port 5 Switch MII transmit error.
Port 5 Switch MII transmit clock:
Input: SW5-MII MAC mode.
Output: SW5-MII PHY modes.
75
SMTXC
I/O
76
77
GNDD
VDDIO
GND
P
Digital ground.
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
Port 5 Switch MII receive clock:
Input: SW5-MII MAC mode.
Output: SW5-MII PHY mode.
78
79
SMRXC
I/O
SMRXDV
Ipd/O
Switch MII receive data valid.
Port 5 Switch MII receive bit 3.
Strap option:
80
81
SMRXD3
SMRXD2
Ipd/O
Ipd/O
PD (default) = Disable Switch SW5-MII full-duplex flow control
PU = Enable Switch SW5-MII full-duplex flow control.
Port 5 Switch MII receive bit 2.
Strap option:
PD (default) = Switch SW5-MII in full-duplex mode;
PU = Switch SW5-MII in half-duplex mode.
Port 5 Switch MII receive bit 1.
Strap option:
82
SMRXD1
Ipd/O
PD (default) =Port 5 Switch SW5-MII in 100Mbps mode; SW5-TMII in
200Mbps mode.
PU = Switch SW5-MII in 10Mbps mode.
Port 5 Switch MII receive bit 0.
Strap option: LED mode
PD (default) = mode 0; PU = mode 1. See “Register 11.”
Mode 0, link at
100/Full LEDx[2,1,0]=0,0,0
10/Full LEDx[2,1,0]=0,0,1
Mode 1, link at
100/Full LEDx[2,1,0]=0,1,0
10/Full LEDx[2,1,0]=1,0,0
100/Half LEDx[2,1,0]=0,1,0
10/Half LEDx[2,1,0]=0,1,1
83
SMRXD0
Ipd/O
Ipd/O
100/Half LEDx[2,1,0]=0,1,1
10/Half LEDx[2,1,0]=1,0,1
Mode 0
Mode 1
LEDX_2
LEDX_1
LEDX_0
Port 5 Switch MII collision detect:
Input: SW5-MII MAC modes.
Output: SW5-MII PHY modes.
Lnk/Act
Fulld/Col
Speed
100Lnk/Act
10Lnk/Act
Full duplex
84
SCOL
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Revision 2.1
Micrel, Inc.
KSZ8895MLUB
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
Port
Pin Function(2)
Port 5 Switch MII modes carrier sense:
Input: SW5-MII MAC modes.
85
SCRS
Ipd/O
Output: SW5-MII PHY modes.
Pin 91,86,87 are dual MII configuration pins for the Port5 MAC5 MII. SW5-MII
supports both MAC mode and PHY modes.
86
SCONF1
Ipd
Pin#: (91, 86, 87)
Port5 Switch MAC5 SW5- MII
000
001
010
011
100
101
110
111
Disable, Otri
PHY Mode MII
MAC Mode MII
PHY Mode SNI
Disable (Default)
PHY Mode MII
MAC Mode MII
PHY Mode SNI
87
88
89
SCONF0
GNDD
Ipd
GND
P
Dual MII configuration pin. See pin 86 descriptions.
Digital ground.
VDDC
1.2V digital core VDD
.
Reserved for MLUB
Strap option: aging setup. See “Aging” section.
PU (default) = Aging enable
PD = Aging disable.
Reserved for MLUB
Strap option:
PU (default): enable PHY[5] MII I/F.
PD: tristate and disable all PHY[5] MII output. (Design should pull this pin
down as default for MLUB.
Reserved for MLUB
Strap option for port 4 only.
90
91
92
LED5-2
LED5-1
LED5-0
Ipu/O
Ipu/O
Ipu/O
5
5
5
PU (default) = Enable auto-negotiation.
PD = Disable auto-negotiation. Strap to register76 bit[7].
93
94
LED4-2
LED4-1
Ipu/O
Ipu/O
4
4
LED indicator 2.
LED indicator 1.
LED indicator 0.
Strap option:
95
LED4-0
Ipu/O
4
PU (default) = Normal mode.
PD = Energy Detection mode (EDPD mode).
Strap to register 14 bits[4:3]
96
97
LED3-2
LED3-1
Ipu/O
Ipu/O
3
3
LED indicator 2.
LED indicator 1.
LED indicator 0.
Strap option:
98
LED3-0
Ipu/O
3
PU (default) = Select I/O drive strength (8mA);
PD = Select I/O drive strength (12mA).
Strap to register132 bit[7-6].
99
GNDD
VDDIO
LED2-2
GND
P
Digital ground.
100
101
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
LED indicator 2.
Ipu/O
2
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Revision 2.1
Micrel, Inc.
KSZ8895MLUB
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
Port
Pin Function(2)
LED indicator 1.
Strap option: for port 3 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negotiation. Strap to register60 bit[7].
102
LED2-1
Ipu/O
2
103
104
LED2-0
LED1-2
Ipu/O
Ipu/O
2
1
LED indicator 0.
LED indicator 2.
LED indicator 1.
Strap option: for port 3 only.
105
LED1-1
Ipu/O
1
PU (default) = no force flow control, normal operation.
PD = force flow control. Strap to register60 bit[4].
LED indicator 0.
Strap option for port 3 only.
106
LED1-0
Ipu/O
1
PU (default) = force half-duplex if auto-negotiation is disabled or fails.
PD = force full-duplex if auto negotiation is disabled or fails.
Strap to register60 bit[5].
107
108
109
110
MDC
MDIO
Ipu
All
All
All
All
Switch MII management data clock. Or SMI interface clock.
Switch MII management data I/O. Or SMI interface data I/O.
Features internal pull down to define pin state when not driven.
Need an external pull-up when driven.
Ipu/O
Ipu/O
Ipu/O
SPIQ
SPI serial data output in SPI slave mode.
SPI slave mode: clock input
SPIC/SCL
(1) Input clock up to 25MHz in SPI slave mode,
(2) output clock at 61kHz in I2C master mode. See “Pin 113.”
SPI slave mode: serial data input.
111
112
SSPID/SDA
SPIS_N
Ipu/O
Ipu
All
All
(1) Serial data input in SPI slave mode;
(2) Serial data input/output in I2C master mode. See “Pin 113.”
SPI slave mode: chip select (active low).
(1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the
KSZ8895MLUB is deselected and SPIQ is held in high impedance state, a
high-to-low transition to initiate the SPI data transfer.
(2) not used in I2C master mode.
Serial bus configuration pin.
For this case, if the EEPROM is not present, the KSZ8895MLUB will start
itself with the PS[1.0] = 00 default register values.
Pin Configuration
PS[1.0]=00
Serial Bus Configuration
I2C Master Mode for EEPROM
SMI Interface Mode
113
PS1
Ipd
PS[1.0]=01
PS[1.0]=10
SPI Slave Mode for CPU Interface
Factory Test Mode (BIST)
PS[1.0]=11
114
115
116
117
118
119
120
PS0
RST_N
GNDD
VDDC
TESTEN
SCANEN
NC
Ipd
Ipu
GND
P
Serial bus configuration pin. See “Pin 113.”
Reset the KSZ8895MLUB device. Active low.
Digital ground.
1.2V digital core VDD
.
Ipd
Ipd
NC
NC for normal operation. Factory test pin.
NC for normal operation. Factory test pin.
No connect.
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Revision 2.1
Micrel, Inc.
KSZ8895MLUB
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
Port
Pin Function(2)
25MHz crystal clock connection/or 3.3V Oscillator input. Crystal/Oscillator
should be ±50ppm tolerance.
121
X1
I
122
123
124
X2
NC
NC
O
25MHz crystal clock connection.
No connect.
NC
NC
No connect.
LDO_O pin connect to Gate pin of MOSFET if using the internal 1.2V LDO
controller.
LDO_O pin will be floating if using an external 1.2V LDO.
Note: When pin126 voltage is greater than the internal 1.2V LDO controller
enable threshold (1V), the Internal 1.2V LDO controller is enabled and
creates a 1.2V output when using an external MOSFET.
When pin126 is pull-down, the internal 1.2V LDO controller is disabled and
pin 125 tri-stated.
125
LDO_O
P
Pull-up or a Resistor divider: Enable internal 1.2V LDO controller.
Pull-down: Disable internal 1.2V LDO controller.
Note: A 4K pull-up and a 2K pull-down resistors divider network is
recommended if using the internal 1.2V LDO controller and an external
MOSFET for 1.2V power.
126
IN_PWR_SEL
I
A 100Ω (approximately) resistor between the source and drain pins on the
MOSFET is highly recommended as well.
You can also use an external 1.2V LDO for 1.2V power supply.
127
128
GNDA
TEST2
GND
NC
Analog ground.
NC for normal operation. Factory test pin.
Notes:
1.
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
GND = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
NC = No connect.
2.
PU = Strap pin pull-up.
PD = Strap pull-down.
OTRI = Output tristated.
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Revision 2.1
Micrel, Inc.
KSZ8895MLUB
Pin for Strap-In Options
The KSZ8895MLUB can function as a managed switch or unmanaged switch. If no EEPROM or micro-controller exists,
the KSZ8895MLUB will operate from its default setting. The strap-in option pins can be configures by external pull-
up/down resistors and take the effect after power-down reset or warm reset, the functions are described in the following
tables.
Pin Number
Pin Name
PU/PD(1) Description(2)
Disable auto MDI/MDI-X.
1
MDI-XDIS
Ipd
PD = (default) = normal operation
PU = disable auto MDI/MDI-X on all ports.
Strap option:
62
63
64
65
66
67
68
80
81
82
PMRXD3
PMRXD2
PMRXD1
PMRXD0
PMRXER
PCRS
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
PD (default) = enable flow control;
PU = disable flow control.
Strap option:
PD (default) = disable back pressure;
PU = enable back pressure.
Strap option:
PD (default) = drop excessive collision packets;
PU = does not drop excessive collision packets.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex mode;
PU = enable for performance enhancement.
Strap option:
PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
Strap option for port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or fails.
PU = force full-duplex if auto-negotiation is disabled or fails. Refer to register 76.
Strap option for port 4 only.
PCOL
PD (default) = no force flow control.
PU = force flow control. Refer to register 66.
Switch MII receive bit 3. Strap option:
PD (default) = disable switch SW5-MII full-duplex flow control;
PU = enable switch SW5-MII full-duplex flow control.
Switch MII receive bit 2. Strap option:
PD (default) = switch SW5-MII in full-duplex mode;
PU = switch SW5-MII in half-duplex mode.
Switch MII receive bit 1. Strap option:
PD (default) = switch SW5-MII in 100Mbps mode and SW5-TMII in 200Mbps
PU = switch MII in 10Mbps mode.
SMRXD3
SMRXD2
SMRXD1
Switch MII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU = mode 1.
See “Register 11.”
Mode 0
Lnk/Act
Fulld/Col
Speed
Mode 1
100Lnk/Act
10Lnk/Act
Fulld
83
SMRXD0
Ipd/O
LEDX_2
LEDX_1
LEDX_0
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Pin for Strap-In Options (Continued)
Pin Number
Pin Name
PU/PD(1) Description(2)
Pins 91, 86, 87 are dual MII configuration pins for the Port5 MAC5 MII. SW5-MII supports
both MAC mode and PHY modes.
86
SCONF1
Ipd
Pin#: (91, 86, 87)
Port5 Switch MAC5 SW5- MII
Disable, Otri
000
001
010
011
100
101
110
111
PHY Mode MII
MAC Mode MII
PHY Mode SNI
Disable
PHY Mode MII
MAC Mode MII
PHY Mode SNI
87
90
SCONF0
LED5-2
Ipd
Dual MII configuration pin. See pin 86 descriptions.
Strap option: Aging setup. See “Aging” section
PU (default) = aging enable;
Ipu/O
PD = aging disable.
Strap option:
91
92
LED5-1
LED5-0
Ipu/O
Ipu/O
PU (default): enable PHY[5] MII I/F.
PD: tristate all PHY[5] MII output. See “Pin 86 SCONF1.”
Strap option for port 4 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negotiation. Strap to register76 bit[7]
LED indicator 0.
Strap option:
95
98
LED4-0
LED3-0
Ipu/O
Ipu/O
PU (default) = Normal mode.
PD = Energy Detection mode (EDPD mode).
Strap to register 14 bits[4:3]
LED3 indicator 0.
Strap option:
PU (default) = Select I/O current drive strength (8mA);
PD = Select I/O current drive strength (12mA).
Strap to register132 bit[7:6].
LED2 indicator 1.
Strap option for port 3 only.
102
105
LED2-1
LED1-1
Ipu/O
Ipu/O
PU (default) = Enable auto-negotiation.
PD = Disable auto-negotiation.
Strap to register60 bit[7]
LED1 indicator 1.
Strap option for port 3 only.
PU (default) = no force flow control, normal operation.
PD = force flow control. Strap to register50 bit[4]
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Pin for Strap-In Options (Continued)
Pin Number
Pin Name
PU/PD(1) Description(2)
LED1 indicator 0.
Strap option for port 3 only.
106
LED1-0
Ipu/O
PU (default) = force half-duplex if auto-negotiation is disabled or fails.
PD = force full-duplex if auto negotiation is disabled or fails.
Strap to register60 bit[5].
Serial bus configuration pin. For this case, if the EEPROM is not present, the
KSZ8895MLUB will start itself with the PS[1:0] =00 default register values.
Pin Configuration
PS[1:0]=00
Serial Bus Configuration
I2C Master Mode for EEPROM
SMI Interface Mode
113
114
PS1
PS0
Ipd
Ipd
PS[1:0]=01
PS[1:0]=10
SPI Slave Mode for CPU Interface
Factory Test Mode (BIST)
PS[1:0]=11
Serial bus configuration pin. See “Pin 113.”
Notes:
1.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
PU = Strap pin pull-up.
2.
PD = Strap pull-down.
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Introduction
The KSZ8895MLUB contains four 10/100 physical layer transceivers and five media access control (MAC) units with an
integrated Layer 2 managed switch. The device runs in two modes. The first mode is as a 4-port integrated switch. The
second is as a 4-port switch with the fifth MAC. In this mode, access to the fifth MAC is provided through a media
independent interface (MII).
The KSZ8895MLUB has the flexibility to reside in a managed or unmanaged design. In a managed design, a host
processor has complete control of the KSZ8895MLUB via the SPI bus, or via the MDC/MDIO interface with SMI mode. An
unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time.
On the media side, the KSZ8895MLUB supports IEEE 802.3 10BASE-T, 100BASE-TX on all ports with Auto MDI/MDIX.
The KSZ8895MLUB can be used as fully-managed 4-port standalone switch or hook up to microprocessor by its SW-MII
interface for an application solution.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the
design more efficient and allows for lower power consumption and smaller chip die size.
There are a number of major enhancements from the KS8995MA to the KSZ8895MLUB. These include: more host
interface options, four queues prioritization, tag as well as port based VLAN, rapid spanning tree support, IGMP snooping
support, port mirroring support and more flexible rate limiting and filtering functionality.
Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII
data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding
followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3
current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1 transformer ratio. It has a typical
rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing
jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving
side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since
the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its
characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This
is an ongoing process and can self-adjust against environmental changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8895MLUB generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are
generated from an external 25MHz crystal or oscillator.
Scrambler/De-Scrambler (100BASE-TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-
bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the
transmitter.
10BASE-T Transmit
The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with typical 2.3V amplitude. The harmonic contents are
at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal.
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10BASE-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data.
A squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the
RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the
incoming signal and the KSZ8895MLUB decodes a data frame. The receiver clock is maintained active during idle periods
in between data reception.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8895MLUB supports HP Auto MDI/MDI-X
and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the
KSZ8895MLUB device. This feature is extremely useful when end users are unaware of cable types, and also, saves on
an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control
registers, or MIIM PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are highlighted in Table 1:
Table 1. MDI/MDI-X Pin Definitions
MDI
MDI-X
RJ-45 Pins
Signals
TD+
RJ-45 Pins
Signals
RD+
RD-
1
2
3
6
1
2
3
6
TD-
RD+
RD-
TD+
TD-
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 1 depicts a
typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
Figure 1. Typical Straight Cable Connection
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Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 2
shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 2. Typical Crossover Cable Connection
Auto-Negotiation
The KSZ8895MLUB conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation
allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners
advertise their capabilities to each other, and then compare their own capabilities with those they received from their link
partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of
operation.
The following list shows the speed and duplex operation mode from highest to lowest.
•
•
•
•
Highest:
High:
100Base-TX, full-duplex
100Base-TX, half-duplex
10Base-T, full-duplex
10Base-T, half-duplex
Low:
Lowest:
If auto-negotiation is not supported or the KSZ8895MLUB link partner is forced to bypass auto-negotiation, the
KSZ8895MLUB sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and
allows the KSZ8895MLUB to establish link by listening for a fixed signal protocol in the absence of auto-negotiation
advertisement protocol. The auto-negotiation link-up process is shown in Figure 3.
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Figure 3. Auto-Negotiation
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LinkMD® Cable Diagnostics
The LinkMD® feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems
such as open circuits, short circuits and impedance mismatches.
LinkMD® works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with
maximum distance of 200m and accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable digital
format.
Note: Cable diagnostics are only valid for copper connections and do not support fiber optic operation.
Access
LinkMD® is initiated by accessing the PHY special control/status Registers {26, 42, 58, 74, 90} and the LinkMD result
Registers {27, 43, 59, 75, 91} for ports 1, 2, 3, 4 and 5 respectively; and in conjunction with the Registers Port Control 12
and 13 for ports 1, 2, 3, 4 and 5 respectively to disable Auto-Negotiation and Auto MDI/MDIX.
Alternatively, the MIIM PHY Registers 0 and 1d can be used for LinkMD® access also.
Usage
The following is a sample procedure for using LinkMD® with Registers {26, 27, 28, 29} on port 1.
1. Disable Auto-Negotiation by writing a ‘1’ to Register 28 (0x1c), bit [7].
2. Disable auto MDI/MDI-X by writing a ‘1’ to Register 29 (0x1d), bit [2] to enable manual control over the differential pair
used to transmit the LinkMD® pulse.
3. A software sequence set up to the internal registers for LinkMD only, see an example below.
4. Start cable diagnostic test by writing a ‘1’ to Register 26 (0x1a), bit [4]. This enable bit is self-clearing.
5. Wait (poll) for Register 26 (0x1a), bit [4] to return a ‘0’, and indicating cable diagnostic test is completed.
6. Read cable diagnostic test results in Register 26 (0x1a), bits [6:5]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the KSZ8895 is unable to shut down the link partner. In this instance, the test
is not run, since it would be impossible for the KSZ8895 to determine if the detected signal is a reflection of the signal
generated or a signal from another source.
7. Get distance to fault by concatenating Register 26 (0x1a), bit [0] and Register 27 (0x1b), bits [7:0]; and multiplying the
result by a constant of 0.4. The distance to the cable fault can be determined by the following formula:
D (distance to cable fault) = 0.4 x { (Register 26, bit [0]),(Register 27, bits [7:0]) }
D (distance to cable fault) is expressed in meters.
Concatenated value of Registers 26 bit [0] and 27 bit [7:0] should be converted to decimal before decrease 26 and
multiplying by 0.4.
The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation
that varies significantly from the norm.
For port 2, 3, 4, 5 and for the MIIM PHY registers, LinkMD® usage is similar.
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A LinkMD example
The following is a sample procedure for using LinkMD® on port 1.
//Set Force 100/Full and Force MDIX mode
//W is WRITE the register. R is READ register
W 1c ff
W 1d 04
//Set Internal Registers Temporary Adjustment for LinkMD
W 47 b0
W 27 00
W 37 03 (03- port 1, 04-port2, 05-port3, 06-port4, 07-port5)
W 47 80 (bit7-port1, bit6-port2, bit5-port3, bit4-port4, bit3-port5)
W 27 00
W 37 00
//Enable LinkMD Testing with Fault Cable for port 1
W 1a 10
R 1a
R 1b
//Result analysis based on the values of the Register 0x1a and 0x1b for port 1:
//The Register 0x1a bits [6-5] are for the open or the short detection.
//The Register 0x1a bit [0] + the Register 0x1b bits [7-0] = Vct_Fault [8-0]
//The distance to fault is about 0.4 x {Vct_Fault [8-0] – 26}
Note:
After end the testing, set all registers above to their default value, the default values are ‘00’ for the Register (0x37) and
the Register (0x47)
On-Chip Termination Resistors
The KSZ8895MLUB reduces board cost and simplifies board layout by using on-chip termination resistors for all ports and
the RX/TX differential pairs without the external termination resistors. The solution of the on chip termination and internal
biasing will save about 50% power consumption compare with using external biasing and termination resistors, and the
transformer will not consume power any more.
Internal 1.2V LDO Controller
The KSZ8895MLUB reduces board cost and simplifies board layout by integrating an internal 1.2V LDO controller to drive
a low cost MOSFET to supply the 1.2V core power voltage for a single 3.3V power supply solution.
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Power Management
The KSZ8895MLUB supports a full-chip hardware power-down mode. When PWRDN Pin 47 (Pin PWRDN =0) is
activated low, the entire chip is powered down. If this pin is de-asserted, the chip will be internally reset.
The KSZ8895MLUB can also use multiple power level of 3.3V, 2.5V or 1.8V for VDDIO to support different I/O voltage.
The KSZ8895MLUB supports enhanced power management feature in low power state with energy detection to ensure
low-power dissipation during device idle periods. There are five operation modes under the power management function
which is controlled by the register 14 bit [4:3] and the port register control 13 bit 3 as shown below:
•
•
•
•
•
Register 14 bit [4:3] = 00 normal operation mode
Register 14 bit [4:3] = 01 energy detect mode
Register 14 bit [4:3] = 10 soft power down mode
Register 14 bit [4:3] = 11 power saving mode
Port register 29, 45, 61, 77, 93 Control 13 bit 3 =1 are for the port based power-down mode
Table 2 indicates all internal function blocks status under four different power management operation modes.
Table 2. Internal Function Block Status
Power Management Operation Modes
KSZ8895MLUB
Function Blocks
Normal Mode
Enabled
Power-Saving Mode
Energy Detect Mode
Disabled
Soft Power-Down Mode
Disabled
Internal PLL Clock
Tx/Rx PHY
MAC
Enabled
Rx unused block disabled
Enabled
Enabled
Energy detect at Rx
Disabled
Disabled
Enabled
Disabled
Host Interface
Enabled
Enabled
Disabled
Disabled
Normal Operation Mode
This is the default setting bit [4:3] =00 in register 14 after the chip power-up or hardware reset. When KSZ8895MLUB is in
this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is ready for CPU
read or write.
During the normal operation mode, the host CPU can set the bit [4:3] in register 14 to transit the current normal operation
mode to any one of the other three power management operation modes.
Energy Detect Mode
The energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8895MLUB is not connected to an active link partner. In this mode, the device will save more power based on the
regular less power consumption. If the cable is not plugged, the KSZ8895MLUB can automatically enter to a low power
state, otherwise known as the energy detect mode. In this mode, KSZ8895MLUB will keep transmitting 120ns width
pulses at 1 pulse/s rate. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the
KSZ8895MLUB can automatically power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8895MLUB reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver.
The energy detect mode is entered by setting bit [4:3] =01 in register 14. When the KSZ8895MLUB is in this mode, it will
monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit [7:0] Go-
Sleep time in register 15, KSZ8895MLUB will go into a low power state. When KSZ8895MLUB is in low power state, it will
keep monitoring the cable energy. Once the energy is detected from the cable, KSZ8895MLUB will enter normal power
state. When KSZ8895MLUB is at normal power state, it is able to transmit or receive packet from the cable.
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Soft Power-Down Mode
The soft power-down mode is entered by setting bit [4:3] =10 in register 14. When KSZ8895MLUB is in this mode, all PLL
clocks are disabled, also all of PHYs and the MACs are off. Any dummy host access will wake-up this device from current
soft power-down mode to normal operation mode and internal reset will be issued to make all internal registers go to the
default values.
Power-Saving Mode
The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit [4:3]
=11 in register 14. When KSZ8895MLUB is in this mode, all PLL clocks are enabled, MAC is on, all internal registers
value will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY
transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the
unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the
KSZ8895MLUB can automatically enabled the PHY power up to normal power state from power saving mode.
During this power-saving mode, the host CPU can set bit [4:3] in register 14 to transit the current power saving mode to
any one of the other three power management operation modes.
Port-Based Power-Down Mode
In addition, the KSZ8895MLUB features a per-port power down mode. To save power, a PHY port that is not in use can
be powered down via the port registers control 13 bit3, or MIIM PHY registers 0 bit11.
Switch Core
Address Look-Up
The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table
plus switching information. The KSZ8895MLUB is guaranteed to learn 1K addresses and distinguishes itself from a hash-
based look-up table, which depending on the operating environment and probabilities, may not guarantee the absolute
number of addresses it can learn.
Learning
The internal look-up engine updates its table with a new entry if the following conditions are met:
•
•
The received packet’s source address (SA) does not exist in the look-up table.
The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full,
the last entry of the table is deleted first to make room for the new entry.
Migration
The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly.
Migration happens when the following conditions are met:
•
•
The received packet’s SA is in the table but the associated source port information is different.
The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine will update the existing record in the table with the new source port information.
Aging
The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time
stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the
record from the table. The look-up engine constantly performs the aging process and will continuously remove aging
records. The aging period is 300 ±75 seconds. This feature can be enabled or disabled through Register 3 or by external
pull-up or pull-down resistors on LED[5][2].
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Forwarding
The KSZ8895MLUB will forward packets using an algorithm that is depicted in the following flowcharts. Figure 6 shows
stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for
the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by the spanning tree,
IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as shown in Figure
7. This is where the packet will be sent.
KSZ8895MLUB Will Not Forward the Following Packets:
•
•
•
Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors.
802.3x pause frames. The KSZ8895MLUB will intercept these packets and perform the appropriate actions.
“Local” packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches the
port where the packet was from, the packet is defined as “local.”
Switching Engine
The KSZ8895MLUB features a high-performance switching engine to move data to and from the MAC’s, packet buffers. It
operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KSZ8895MLUB
has a 64kB internal frame buffer. This resource is shared between all five ports. There are a total of 512 buffers available.
Each buffer is sized at 128B.
Media Access Controller (MAC) Operation
The KSZ8895MLUB strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter-Packet Gap (IPG)
If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current
packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN.
Backoff Algorithm
The KSZ8895MLUB implements the IEEE Standard 802.3 binary exponential backoff algorithm, and optional “aggressive
mode” backoff. After 16 collisions, the packet will be optionally dropped, depending on the chip configuration in Register 3.
See “Register 3.”
Late Collision
If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped.
Illegal Frames
The KSZ8895MLUB discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in
Register 4. For special applications, the KSZ8895MLUB can also be programmed to accept frames up to 1916 bytes in
Register 4. Since the KSZ8895MLUB supports VLAN tags, the maximum sizing is adjusted when these tags are present.
Flow Control
The KSZ8895MLUB supports standard 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8895MLUB receives a pause control frame, the KSZ8895MLUB will not transmit the next
normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the
current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being
flow controlled), only flow control packets from the KSZ8895MLUB will be transmitted.
On the transmit side, the KSZ8895MLUB has intelligent and efficient ways to determine when to invoke flow control. The
flow control is based on availability of the system resources, including available buffers, available transmit queues and
available receive queues.
The KSZ8895MLUB flow controls a port that has just received a packet if the destination port resource is busy. The
KSZ8895MLUB issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard
802.3x. Once the resource is freed up, the KSZ8895MLUB sends out the other flow control frame (XON) with zero pause
time to turn off the flow control (turn on transmission to the port). A hysteresis feature is also provided to prevent over-
activation and deactivation of the flow control mechanism.
The KSZ8895MLUB flow controls all ports if the receive queue becomes full.
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Figure 4. Destination Address Lookup Flow Chart (Stage 1)
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Figure 5. Destination Address Resolution Flow Chart (Stage 2)
The KSZ8895MLUB will not forward the following packets:
1. Error packets
These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors.
2. IEEE802.3x PAUSE frames
KSZ8895MLUB intercepts these packets and performs full duplex flow control accordingly.
3. "Local" packets
Based on destination address (DA) lookup, if the destination port from the lookup table matches the port from which the
packet originated, the packet is defined as "local."
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Half-Duplex Back Pressure
The KSZ8895MLUB also provides a half-duplex back pressure option (note: this is not in IEEE 802.3 standards). The
activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required,
the KSZ8895MLUB sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber
and excessive deference as defined in IEEE 802.3 standards, after a certain period of time, the KSZ8895MLUB
discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. This short silent time
(no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sense-
deferred state. If the port has packets to send during a back pressure situation, the carrier sense-type back pressure is
interrupted and those packets are transmitted instead. If there are no more packets to send, carrier sense-type back
pressure becomes active again until switch resources are free. If a collision occurs, the binary exponential backoff
algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining
carrier sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes,
the user must enable the following:
•
•
•
Aggressive backoff (Register 3, bit 0)
No excessive collision drop (Register 4, bit 3)
Back pressure (Register 4, bit 5)
These bits are not set as the default because this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8895MLUB has an intelligent option to protect the switch system from receiving too many broadcast packets.
Broadcast packets are normally forwarded to all ports except the source port and thus use too many switch resources
(bandwidth and available space in transmit queues). The KSZ8895MLUB has the option to include “multicast packets” for
storm control. The broadcast storm rate parameters are programmed globally and can be enabled or disabled on a per
port basis. The rate is based on a 50ms (0.05s) interval for 100BT and a 500ms (0.5s) interval for 10BT. At the beginning
of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the
interval. The rate definition is described in Registers 6 and 7. The default setting for Registers 6 and 7 is 0x4A (74
decimal). This is equal to a rate of 1%, calculated as follows:
148,80 frames/sec X 50ms (0.05s)/interval X 1% = 74 frames/interval (approx.) = 0x4A
MII Interface Operation
The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface
between physical layer and MAC layer devices. The KSZ8895MLUB provides such interfaces on port 5. The SW5-MII
interface is used to connect to the fifth MAC. The MII interface contains two distinct groups of signals, one for
transmission and the other for receiving.
Port 5 MAC 5 SW5-MII Interface
Table 3 shows two connection manners:
1.
2.
The first is an external MAC connects to SW5-MII PHY mode.
The second is an external PHY connects to SW5-MII MAC mode.
Please see the pins [91, 86, and 87] description for detail configuration for the MAC mode and PHY mode, SW5-MII works
with 25MHz and 2.5MHz clock for 100Base-TX and 10Base-T.
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Table 3. Switch MAC 5 MII Signals
KSZ8895MLUB PHY Mode Connections
KSZ8895MLUB MAC Mode Connections
Description
KSZ8895MLUB SW5-
External
MAC
KSZ8895MLUB SW5-MII
Signal
External
PHY
Type
MII
Signal
Type
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
SMTXEN
SMTXER
SMTXD[3]
SMTXD[2]
SMTXD[1]
SMTXD[0]
SMTXC
Input
Input
Transmit enable
Transmit error
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
SMRXDV
Not used
SMRXD[3]
SMRXD[2]
SMRXD[1]
SMRXD[0]
SMRXC
Output
Not used
Output
Output
Output
Output
Input
Input
Transmit data bit 3
Transmit data bit 2
Transmit data bit 1
Transmit data bit 0
Transmit clock
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
MCOL
SCOL
Collision detection
Carrier sense
MCOL
SCOL
Input
MCRS
SCRS
MCRS
SCRS
Input
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
SMRXDV
Not used
SMRXD[3]
SMRXD[2]
SMRXD[1]
SMRXD[0]
SMRXC
Receive data valid
Receive error
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
SMTXEN
SMTXER
SMTXD[3]
SMTXD[2]
SMTXD[1]
SMTXD[0]
SMTXC
Input
Input
Receive data bit 3
Receive data bit 2
Receive data bit 1
Receive data bit 0
Receive clock
Input
Input
Input
Input
Input
The switch MII interface operates in either MAC mode or PHY mode for KSZ8895MLUB. These interfaces are nibble-wide
data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on the transmit side indicate
when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey
when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicates a
collision has occurred during transmission.
Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is
not provided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming
from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not
appropriate for this configuration. For PHY mode operation, if the device interfacing with the KSZ8895MLUB has an
MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KSZ8895MLUB has an
MTXER pin, it should be tied low.
SNI Interface Operation
The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This
interface can be directly connected to these types of devices. The signals are divided into two groups, one for
transmission and the other for reception. The signals involved are described in Table 4.
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Table 4. SNI Signals
SNI Signal
Description
Transmit Enable
Serial Transmit Data
Transmit Clock
KSZ8895MLUB Signal
TXEN
TXD
TXC
COL
CRS
RXD
RXC
SMTXEN
SMTXD[0]
SMTXC
Collision Detection
Carrier Sense
SCOL
SMRXDV
SMRXD[0]
SMRXC
Serial Receive Data
Receive Clock
This interface is a bit-wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on
the transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is
valid.
For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
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Advanced Functionality
QoS Priority Support
The KSZ8895MLUB provides Quality-of-Service (QoS) for applications such as VoIP and video conferencing. The
KSZ8895MLUB offer 1/2/4 priority queues option per port by setting the port registers xxx control 9 bit1 and the port
registers xxx control 0 bit0, the 1/2/4 queues split as follows,
[Port registers xxx control 9 bit1, control 0 bit0]=00 single output queue as default.
[Port registers xxx control 9 bit1, control 0 bit0]=01 egress port can be split into two priority transmit queues.
[Port registers xxx control 9 bit1, control 0 bit0]=10 egress port can be split into four priority transmit queues.
The four priority transmit queues is a new feature in the KSZ8895MLUB. The queue 3 is the highest priority queue and
Queue 0 is the lowest priority queue. The port registers xxx control 7 bit1 and the port registers xxx control 0 bit0 are used
to enable split transmit queues for ports 1, 2, 3, 4 and 5, respectively. If a port's transmit queue is not split, high priority
and low priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or use programmable weighted fair queuing
for the four priority queues scale by the port registers control 10, 11, 12 and 13 (default value are 8, 4, 2, 1 by their
bit[6:0].
Register 130 bit[7:6] Prio_2Q[1:0] is used when the 2 Queue configuration is selected, these bits are used to map the 2-bit
result of IEEE 802.1p from the registers 128, 129 or TOS/DiffServ mapping from registers 144-159 (for 4 Queues) into two
queues mode with priority high or low.
Please see the descriptions of the register 130 bits [7:6] for detail.
Port-Based Priority
With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets received at
the priority 3 receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding
transmit queue is split. The Port Registers Control 0 Bits [4:3] is used to enable port-based priority for ports 1, 2, 3, 4 and
5, respectively.
802.1p-Based Priority
For 802.1p-based priority, the KSZ8895MLUB examines the ingress (incoming) packets to determine whether they are
tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value, as
specified by the registers 128 and 129, both register 128/129 can map 3-bit priority field of 0-7 value to 2-bit result of 0-3
priority levels. The “priority mapping” value is programmable.
The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Figure 6. 802.1p Priority Field Format
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802.1p-based priority is enabled by bit [5] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively.
The KSZ8895MLUB provides the option to insert or remove the priority tagged frame's header at each individual egress
port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field (TCI), is
also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit [2] of the port registers control 0 and the port register control 8 to select which source port
(ingress port) PVID can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respectively. At the egress port, untagged
packets are tagged with the ingress port’s default tag. The default tags are programmed in the port registers control 3 and
control 4 for ports 1, 2, 3, 4 and 5, respectively. The KSZ8895MLUB will not add tags to already tagged packets.
Tag Removal is enabled by bit [1] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. At the egress port,
tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8895MLUB will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8895MLUB to set the “User Priority Ceiling” at
any ingress port by the port register control 2 bit 7. If the ingress packet’s priority field has a higher priority value than the
default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 144 to 159) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are
fully decoded, the resultant of the 64 possibilities of DSCP decoded is compared with the corresponding bits in the DSCP
register to determine priority.
Spanning Tree Support
Port 5 is the designated port for spanning tree support.
The other ports (port 1 – port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive
enable,” and “learning disable” register settings in Registers 18, 34, 50, and 66 for ports 1, 2, 3, and 4, respectively. The
following description shows the port setting and software actions taken for each of the five spanning tree states.
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to the
processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard
those packets.
Note: Processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1"
Software action: the processor should not send any packets to the port(s) in this state. The processor should program the
“Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should also be set so
that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1.
"Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
disabled on the port in this state.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
enabled on the port in this state.
Forwarding state: Packets are forwarded and received normally. Learning is enabled.
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Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
enabled on the port in this state.
Rapid Spanning Tree Support
There are three operational states of the Discarding, Learning, and Forwarding assigned to each port for RSTP:
Discarding ports do not participate in the active topology and do not learn MAC addresses.
Discarding state: the state includs three states of the disable, blocking and listening of STP.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to the
processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard
those packets. When disable the port’s learning capability (learning disable=’1’), set the register 1 bit5 and bi4 will flush
rapidly with the port related entries in the dynamic MAC table and static MAC table.
Note: Processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state.
Ports in Learning states learn MAC addresses, but do not forward user traffic.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
enabled on the port in this state.
Ports in Forwarding states fully participate in both data forwarding and MAC learning.
Forwarding state: packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is
enabled on the port in this state.
RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP Configuration BPDUs with the exception
of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carrying additional information.
Tail Tagging Mode
The Tail Tag is only seen and used by the port 5 interface, which should be connected to a processor by SW5-MII
interface. The one byte tail tagging is used to indicate the source/destination port in port 5. Only bit [3-0] are used for the
destination in the tail tagging byte. Other bits are not used. The Tail Tag feature is enabled by setting register 12.
Figure 7. Tail Tag Frame Format
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Table 5. Tail Tag Rules
Ingress to Port 5 (Host −> KSZ8895MLUB)
Bit [3:0]
0,0,0,0
0,0,0,1
0,0,1,0
0,1,0,0
1,0,0,0
1,1,1,1
Bit [7:4]
0,0,0,0
0,0,0,1
0,0,1,0
0,0,1,1
x, 1,x,x
1, x,x,x
Destination
Reserved
Port 1 (direct forward to port1)
Port 2 (direct forward to port2)
Port 3 (direct forward to port3)
Port 4 (direct forward to port4)
Port 1, 2,3 and 4 (direct forward to port 1,2,3,4,)
Queue 0 is used at destination port
Queue 1 is used at destination port
Queue 2 is used at destination port
Queue 3 is used at destination port
Whatever send packets to specified port in bit[3:0]
Bit[6:0] will be ignored as normal (Address look up)
Egress from Port 5 (KSZ8895MLUB −> Host)
Bit [1:0]
0,0
Source
Port 1 (packets from port 1)
Port 2 (packets from port 2)
Port 3 (packets from port 3)
Port 4 (packets from port 4)
0,1
1,0
1,1
IGMP Support
There are two parts involved to support the Internet Group Management Protocol (IGMP) in Layer 2. The first part is IGMP
snooping, the second part is this IGMP packet to be sent back to the subscribed port. Describe them as follows.
IGMP Snooping
The KSZ8895MLUB traps IGMP packets and forwards them only to the processor (Port 5 SW5-MII/RMII). The IGMP
packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4
and protocol version number = 0x2. Set register 5 bit [6] to ‘1’ to enable IGMP snooping.
IGMP Send Back to the Subscribed Port
Once the host responds the received IGMP packet, the host should know the original IGMP ingress port and send back
the IGMP packet to this port only, otherwise this IGMP packet will be broadcasted to all port to downgrade the
performance.
Enable the tail tag mode, the host will know the IGMP packet received port from tail tag bits [1:0] and can send back the
response IGMP packet to this subscribed port by setting the bits [3:0] in the tail tag. Enable “Tail tag mode” by setting
Register 12 bit 1.
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Port Mirroring Support
KSZ8895MLUB supports “port mirror” comprehensively as:
•
“Receive Only” Mirror on a Port
All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “rx
sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on port 1, is destined to port 4 after the
internal look-up. The KSZ8895MLUB will forward the packet to both port 4 and port 5. KSZ8895MLUB can optionally
forward even “bad” received packets to port 5.
•
•
“Transmit Only” Mirror on a Port
All the packets transmitted on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “tx
sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on any of the ports, is destined to port 1
after the internal look-up. The KSZ8895MLUB will forward the packet to both ports 1 and 5.
“Receive and Transmit” Mirror on Two Ports
All the packets received on port A AND transmitted on port B will be mirrored on the sniffer port. To turn on the “AND”
feature, set Register 5 bit 0 to 1. For example, port 1 is programmed to be “rx sniff,” port 2 is programmed to be
“transmit sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on port 1, is destined to port 4
after the internal look-up. The KSZ8895MLUB will forward the packet to port 4 only, since it does not meet the “AND”
condition. A packet, received on port 1, is destined to port 2 after the internal look-up. The KSZ8895MLUB will forward
the packet to both port 2 and port 5.
Multiple ports can be selected to be “rx sniffed” or “tx sniffed.” And any port can be selected to be the “sniffer port.” All
these per port features can be selected through Register 17.
VLAN Support
KSZ8895MLUB supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. KSZ8895MLUB provides a
128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address look-up max 128
active VLANs. If a non-tagged or null-VID-tagged packet is received, the ingress port VID is used for look-up when 802.1q
is enabled by the global register 5 control 3 bit 7. In the VLAN mode, the look-up process starts from VLAN table look-up
to determine whether the VID is valid. If the VID is not valid, the packet will be dropped and its address will not be learned.
If the VID is valid, FID is retrieved for further look-up by the static MAC table or dynamic MAC table. FID+DA is used to
determine the destination port. The followed table describes the difference actions at different situations of DA and
FID+DA in the static MAC table and dynamic MAC table after the VLAN table finish a look-up action. FID+SA is used for
learning purposes. The followed table also describes how to learning in the dynamic MAC table when VLAN table has
done a look-up and the static MAC table without a valid entry.
Table 6. FID+DA Look-Up in the VLAN Mode
DA Found in
Static MAC
Table
DA+FID Found in
Dynamic MAC
Table
Use FID Flag?
FID Match?
Action
Broadcast to the membership ports defined in the
VLAN table bit [11:7].
Send to the destination port defined in the dynamic
MAC table bit [58:56].
Send to the destination port(s) defined in the static
MAC table bit [52:48].
Broadcast to the membership ports defined in the
VLAN table bit [11:7].
Send to the destination port defined in the dynamic
MAC table bit [58:56].
Send to the destination port(s) defined in the static
MAC table bit [52:48].
No
No
Don’t care
Don’t care
Don’t care
Don’t care
No
No
Yes
Don’t care
Yes
Yes
Yes
Yes
0
1
1
1
Don’t care
No
No
Yes
Yes
Don’t care
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Table 7. FID+SA Look-Up in the VLAN Mode
SA+FID Found in
Dynamic MAC Table
Action
No
The SA+FID will be learned into the dynamic table.
Time stamp will be updated.
Yes
Advanced VLAN features are also supported in KSZ8895MLUB, such as “VLAN ingress filtering” and “discard non PVID”
defined in bits [6:5] of the port Register Control 2. These features can be controlled on a port basis.
Rate Limiting Support
The KSZ8895MLUB provides a fine resolution hardware rate limiting. The rate step is 64Kbps when the rate limit is less
than 1Mbps rate for 100BT or 10BT. The rate step is 1Mbps when the rate limit is more than 1Mbps rate for 100BT or
10BT (refer to Data Rate Selection Table which follow the end of the Port Register Queue 0 − 3 Ingress/Egress Limit
Control section). The rate limit is independently on the “receive side” and on the “transmit side” on a per port basis. For
10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data receive rate for each
priority at each port can be limited by setting up Ingress Rate Control Registers. On the transmit side, the data transmit
rate for each priority queue at each port can be limited by setting up Egress Rate Control Registers. The size of each
frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte, in addition to the data field (from packet
DA to FCS).
Ingress Rate Limit
For ingress rate limiting, KSZ8895MLUB provides options to selectively choose frames from all types, multicast,
broadcast, and flooded unicast frames by bits [3 − 2] of the port rate limit control register. The KSZ8895MLUB counts the
data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the
specified rate limit or the flow control takes effect without packet dropped when the ingress rate limit flow control is
enabled by the port rate limit control register bit 4. The ingress rate limiting supports the port-based, 802.1p and DiffServ-
based priorities, the port-based priority is fixed priority 0 − 3 selection by bits [4 − 3] of the port register control 0. The
802.1p and DiffServ-based priority can be mapped to priority 0 − 3 by default of the register 128 and 129. In the ingress
rate limit, set register 135 global control 19 bit3 for queue-based rate limit to be enabled if use two queues or four queues
mode, all related ingress ports and egress port should be spitted to two queues or four queues mode by the port registers
control 9 and control 0. The four queues mode will use Q0-Q3 for priority 0-3 by bit [6-0] of the port register ingress limit
control 1 − 4. The two queues mode will use Q0-Q1 for priority 0-1by bit [6-0] of the port register ingress limit control 1 − 2.
The priority levels in the packets of the 802.1p and DiffServ can be programmed to priority 0-3 by the register 128 and 129
for a re-mapping.
Egress Rate Limit
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter
frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output
priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate limit control
registers.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress end, and may be therefore slightly less than the specified egress rate. The egress rate limiting supports the port-
based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0 − 3 selection by bits [4 − 3] of the port
register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0 − 3 by default of the register 128
and 129. In the egress rate limit, set register 135 global control 19 bit3 for queue-based rate limit to be enabled if use two
queues or four queues mode, all related ingress ports and egress port should be spitted to two queues or four queues
mode by the port registers control 9 and control 0. The four queues mode will use Q0-Q3 for priority 0 − 3 by bit [6 − 0] of
the port register egress limit control 1 − 4. The two queues mode will use Q0 − Q1 for priority 0 − 1by bit [6 − 0] of the port
register egress limit control 1 − 2.
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The priority levels in the packets of the 802.1p and DiffServ can be programmed to priority 0 − 3 by the register 128 and
129 for a re-mapping.
When egress rate limit just use one queue per port for the egress port rate limit, the priority packets will be based on the
data rate selection table with the rate limit exact number. If egress rate limit use more than one queue per port for the
egress port rate limit, the highest priority packets will be based on the data rate selection table for the rate limit exact
number, other lower priority packet rate will be limited based on 8:4:2:1 (default) priority ratio based on the highest priority
rate. The transmit queue priority ratio is programmable.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Transmit Queue Ratio Programming
In transmit queues 0 − 3 of the egress port, the default priority ratio is 8:4:2:1, the priority ratio can be programmed by the
port registers control 10, 11, 12 and 13. When the transmit rate exceed the ratio limit in the transmit queue, the transmit
rate will be limited by the transmit queue 0 − 3 ratio of the port register control 10, 11, 12 and 13. The highest priority
queue will be no limited, other lower priority queues will be limited based on the transmit queue ratio.
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast
Enable Self-address filtering, the unknown unicast packet filtering and forwarding by the Register 131 Global Control 15.
Enable Unknown multicast packet filtering and forwarding by the Register 132 Global Control 16.
Enable Unknown VID packet filtering and forwarding by the Register 133 Global Control 17.
Enable Unknown IP multicast packet filtering and forwarding by the Register 134 Global Control 18.
This function is very useful in preventing those kinds of packets that could degrade the quality of the port in applications
such as voice over Internet Protocol (VoIP) and the daisy chain connection to prevent packets into endless loop.
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Configuration Interfaces
I2C Master Serial Bus Configuration
If a 2-wire EEPROM exists, then the KSZ8895MLUB can perform more advanced features like broadcast storm protection
and rate control. The EEPROM should have the entire valid configuration data from Register 0 to Register 255 defined in
the “Memory Map,” except the chipID = 0 in the register1 and the status registers. After reset, the KSZ8895MLUB will start
to read all 255 registers sequentially from the EEPROM. The configuration access time (tprgm) is less than 30ms, as shown
in Figure 8.
Figure 8. KSZ8895MLUB EEPROM Configuration Timing Diagram
To configure the KSZ8895MLUB with a pre-configured EEPROM use the following steps:
1. At the board level, connect pin 110 on the KSZ8895MLUB to the SCL pin on the EEPROM. Connect pin 111 on the
KSZ8895MLUB to the SDA pin on the EEPROM.
2. A[2-0] address pins of EEPROM should be tied to ground for address A[2-0] = ‘000’ to be identified by the
KSZ8895MLUB.
3. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00.” This puts the KSZ8895MLUB serial bus
configuration into I2C master mode.
4. Be sure the board-level reset signal is connected to the KSZ8895MLUB reset signal on pin 115 (RST_N).
5. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note that the
first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all other data will
be ignored.
6. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the
KSZ8895MLUB. After the reset is de-asserted, the KSZ8895MLUB will begin reading configuration data from the
EEPROM. The configuration access time (tprgm) is less than 30ms.
Note: For proper operation, make sure that pin 47 (PWRDN_N) is not asserted during the reset operation.
SPI Slave Serial Bus Configuration
The KSZ8895MLUB can also act as a SPI slave device. Through the SPI, the entire feature set can be enabled, including
“VLAN,” “IGMP snooping,” “MIB counters,” etc. The external master device can access any register from Register 0 to
Register 255 randomly. The system should configure all the desired settings before enabling the switch in the
KSZ8895MLUB. To enable the switch, write a "1" to Register 1 bit 0.
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed
configuration time, the KSZ8895MLUB also supports multiple reads or writes. After a byte is written to or read from the
KSZ8895MLUB, the internal address counter automatically increments if the SPI Slave Select Signal (SPIS_N) continues
to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on
SPIQ. If SPIS_N is kept low after the first byte is written, bits on the Master Out Slave Input (SPID) line will be written to
the next address. Asserting SPIS_N high terminates a read or write operation. This means that the SPIS_N signal must
be asserted high and then low again before issuing another command and address. The address counter wraps back to
zero once it reaches the highest address. Therefore the entire register set can be written to or read from by issuing a
single command and address.
The default SPI clock speed is 12.5MHz. The KSZ8895MLUB is able to support a SPI bus up to 25MHz (set register 12
bit[5:4] = 0x10). A high performance SPI master is recommended to prevent internal counter overflow.
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To use the KSZ8895MLUB SPI:
1. At the board level, connect KSZ8895MLUB pins as follows:
Table 8. SPI Connections
KSZ8895MLUB
Pin Number
KSZ8895MLUB Signal
Name
Microprocessor Signal Description
112
110
111
109
SPIS_N
SPIC
SPI Slave Select
SPI Clock
SPID
Master Out Slave Input
Master In Slave Output
SPIQ
2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “10” to set the serial configuration to SPI slave mode.
3. Power up the board and assert a reset signal. After reset wait 100µs, the start switch bit in Register 1 will be set to ‘0’.
Configure the desired settings in the KSZ8895MLUB before setting the start register to ‘1.'
4. Write configuration to registers using a typical SPI write data cycle as shown in Figure 9 or SPI multiple write as
shown in Figure 11. Note that data input on SPID is registered on the rising edge of SPIC.
5. Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure 10 or a
multiple read as shown in Figure 12. Note that read data is registered out of SPIQ on the falling edge of SPIC.
6. After configuration is written and verified, write a ‘1’ to Register 1 bit 0 to begin KSZ8895MLUB switch operation.
SPIS_N
SPIC
SPID
SPIQ
D7
D6
D5
D4
D3
D2
D1
D0
X
0
0
0
0
0
0
1
0
A7 A6 A5 A4 A3 A2 A1
A0
WRITE COMMAND
WRITE ADDRESS
WRITE DATA
Figure 9. SPI Write Data Cycle
SPIS_N
SPIC
SPID
X
0
0
0
0
0
0
1
1
A7 A6 A5 A4 A3 A2 A1
A0
SPIQ
D7
D6
D5
D4
D3
D2
D1
D0
READ COMMAND
READ ADDRESS
READ DATA
Figure 10. SPI Read Data Cycle
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SPIS_N
SPIC
SPID
D7
D6
D5
D4
D3
D2
D1
D0
X
0
0
0
0
0
0
1
0
A7 A6 A5 A4 A3 A2 A1
A0
SPIQ
WRITE COMMAND
WRITE ADDRESS
Byte 1
SPIS_N
SPIC
SPID
D7
D6
D5
D4
D4
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SPIQ
Byte 2
Byte 3 ...
Figure 11. SPI Multiple Write
Byte N
SPIS_N
SPIC
SPID
X
0
0
0
0
0
0
1
1
A7 A6 A5 A4 A3 A2 A1
A0
X
X
X
X
X
X
X
X
SPIQ
D7
D6
D5
D4
D3
D2
D1
D0
READ COMMAND
READ ADDRESS
Byte 1
SPIS_N
SPIC
SPID
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SPIQ
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Byte 2
Byte 3 ...
Byte N
Figure 12. SPI Multiple Read
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MII Management Interface (MIIM)
The KSZ8895MLUB supports the standard IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8895MLUB. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY
settings. Further details on the MIIM interface are found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
•
•
A physical connection that incorporates the data line (pin 108 MDIO) and the clock line (pin 107 MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8895MLUB device.
•
Access to a set of eight 16-bit registers, consisting of 8 standard MIIM registers [0:5h], 1d and 1f MIIM registers
per port.
The MIIM Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 9 depicts the MII Management Interface frame format.
Table 9. MII Management Interface Frame Format
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
Start of
Frame
Read/Write
OP Code
Preamble
TA
Data Bits[15:0]
Idle
Read
Write
32 1’s
32 1’s
01
01
10
01
AAAAA
AAAAA
RRRRR
RRRRR
Z0
10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
Z
Z
The MIIM interface does not have access to all the configuration registers in the KSZ8895MLUB. It can only access the
standard MIIM registers. See “MIIM Registers”. The SPI interface and MDC/MDIO SMI mode, on the other hand, can be
used to access all registers with the entire KSZ8895MLUB feature set.
Serial Management Interface (SMI)
The SMI is the KSZ8895MLUB non-standard MIIM interface that provides access to all KSZ8895MLUB configuration
registers. This interface allows an external device with MDC/MDIO interface to completely monitor and control the states
of the KSZ8895MLUB.
The SMI interface consists of the following:
•
•
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external controller to
communicate with the KSZ8895MLUB device.
•
Access to all KSZ8895MLUB configuration registers. Register access includes the Global, Port and Advanced Control
Registers 0-255 (0x00 – 0xFF), and indirect access to the standard MIIM registers [0:5] and custom MIIM registers
[29, 31].
The SMI Interface can operate up to a maximum clock speed of 10MHz MDC clock.
The following table depicts the SMI frame format.
Table 10. Serial Management Interface (SMI) Frame Format
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
Start of
Frame
Read/Write
OP Code
Preamble
TA
Data Bits[15:0]
Idle
Read
Write
32 1’s
32 1’s
01
01
10
01
RR11R
RR11R
RRRRR
RRRRR
Z0
10
0000_0000_DDDD_DDDD
xxxx_xxxx_DDDD_DDDD
Z
Z
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SMI register Read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’. The
8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit [4:0]}. TA is
turn-around bits. TA bits [1:0] are ’Z0’ means the processor MDIO pin is changed to input Hi-Z from output mode and the
followed ‘0’ is the read response from device, as the switch configuration registers are 8-bit wide, only the lower 8 bits of
data bits [15:0] are used
SMI register Write access is selected when OP Code is set to “01” and bits [2:1] of the PHY address is set to ‘11’. The
8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit [4:0]}. TA
bits [1:0] are set to ’10’, as the switch configuration registers are 8-bit wide, only the lower 8 bits of data bits [15:0] are
used.
To access the KSZ8895MLUB registers 0-255 (0x00 - 0xFF), the following applies:
PHYAD [4, 3, 0] and REGAD [4:0] are concatenated to form the 8-bit address; that is, {PHYAD [4, 3, 0], REGAD [4:0]} =
bits [7:0] of the 8-bit address.
Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as zeroes. For write operation, data bits
[15:8] are not defined, and hence can be set to either zeroes or ones.
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
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Register Description
Offset
Description
Decimal
0 − 1
Hex
0x00-0x01
0x02-0x0D
0x0E-0x0F
0x10-0x14
0x15-0x17
0x18-0x1F
0x20-0x24
0x25-0x27
0x28-0x2F
0x30-0x34
0x35-0x37
0x38-0x3F
0x40-0x44
0x45-0x47
0x48-0x4F
0x50-0x54
0x55-0x57
0x58-0x5F
0x60-0x67
0x68-0x6D
0x6E-0x6F
0x70-0x78
0x79-0x7B
0x7C-0x7D
0x7E-0x7F
0x80-0x87
0x88
Chip ID Registers
Global Control Registers
2 − 13
Power Down Management Control Registers
Port 1 Control Registers
14 − 15
16 − 20
Port 1 Reserved (Factory Test Registers)
Port 1 Control/Status Registers
Port 2 Control Registers
21 − 23
24 − 31
32 − 36
Port 2 Reserved (Factory Test Registers)
Port 2 Control/Status Registers
Port 3 Control Registers
37 − 39
40 − 47
48 − 52
Port 3 Reserved (Factory Test Registers)
Port 3 Control/Status Registers
Port 4 Control Registers
53 − 55
56 − 63
64 − 68
Port 4 Reserved (Factory Test Registers)
Port 4 Control/Status Registers
Port 5 Control Registers
69 − 71
72 − 79
80 − 84
Port 5 Reserved (Factory Test Registers)
Port 5 Control/Status Registers
Reserved (Factory Testing Registers)
MAC Address Registers
85 − 87
88 − 95
96 − 103
104 − 109
110 − 111
112 − 120
121 − 123
124 − 125
126 − 127
128 − 135
136
Indirect Access Control Registers
Indirect Data Registers
Reserved (Factory Testing Registers)
Port Interrupt Registers
Reserved (Factory Testing Registers)
Global Control Registers
Switch Self Test Control Register
QM Global Control Registers
TOS Priority Control Registers
TOS Priority Control Registers
Reserved (Factory Testing Registers)
Port 1 Control Registers
0x89-0x8F
0x90-0x91
0x92-0x9F
0xA0-0xAF
0xB0-0xBE
137 − 143
144 − 145
146 − 159
160 − 175
176 − 190
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Register Description (Continued)
Offset
Description
Decimal
191
Hex
0xBF
Reserved (Factory Testing Register): Transmit Queue Remap Base Register
Port 2 Control Registers
0xC0-0xCE
0xCF
192 − 206
207
Reserved (Factory Testing Register)
Port 3 Control Registers
0xD0-0xDE
0xDF
208 − 222
223
Reserved (Factory Testing Register)
Port 4 Control Registers
0xE0-0xEE
0xEF
224 − 238
239
Reserved (Factory Testing Register)
Port 5 Control Registers
0xF0-0xFE
0xFF
240 − 254
255
Reserved (Factory Testing Register)
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Global Registers
Register 0 (0×00): Chip ID0
Address Name
Description
Mode
Default
Family ID
Chip family.
RO
7 − 0
0 × 95
Register 1 (0×01): Chip ID1 / Start Switch
Address Name
Description
Mode
RO
Default
0 × 4
Chip ID
7 − 4
3 − 1
Revision ID
Revision ID
RO
0 × 0
1, start the chip when external pins (PS1, PS0) =
(01) or (1,0)
Note: in (PS1, PS0) = (0,0) mode, the chip will
start automatically, after trying to read the external
EEPROM. If EEPROM does not exist, the chip will
use default values for all internal registers. If
EEPROM is present, the contents in the EEPROM
will be checked.
The switch will check:
Register 0 = 0 × 95
0
Start Switch
R/W
0
Register 1 [7:4] chip ID = 00
If this check is OK, the contents in the EEPROM
will override chip register default values.
Chip will not start when external pins (PS1, PS0)
= (1, 0) or (0, 1).
Note: (PS1, PS0) = (1, 1) for Factory test only.
0, stop the switch function of the chip.
Register 2 (0×02): Global Control 0
Address Name
Description
Mode
R/W
RO
Default
New back-off algorithm designed for UNH
7
6
New Back-off Enable
Reserved
1 = Enable
0 = Disable
0
0
Reserved.
Flush the entire dynamic MAC table for RSTP
1 = Trigger the flush dynamic MAC table
operation. This bit is self-clear.
0 = Normal operation
R/W
(SC)
5
Flush Dynamic MAC Table
0
Note: All the entries associated with a port that
has its learning capability being turned off
(Learning Disable) will be flushed. If you want to
flush the entire Table, all ports learning capability
must be turned off.
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Global Registers (Continued)
Register 2 (0×02): Global Control 0
Address Name
Description
Mode
Default
Flush the matched entries in static MAC table for
RSTP
1 = Trigger the flush static MAC table operation.
This bit is self-clear (SC)
0 = Normal operation
R/W
(SC)
4
Flush Static MAC Table
0
Note: The matched entry is defined as the entry
whose Forwarding Ports field contains a single
port and MAC address with unicast. This port, in
turn, has its learning capability being turned off
(Learning Disable). Per port, multiple entries can
be qualified as matched entries.
3
2
Reserved
Reserved
N/A, don’t change
N/A, don’t change
RO
RO
1
1
1, the switch will drop packets with 0x8808 in T/L
filed, or DA = 01-80-C2-00-00-01.
1
UNH Mode
R/W
0
0, the switch will drop packets qualified as “flow
control” packets.
1, link change from “link” to “no link” will cause
fast aging (<800µs) to age address table faster.
After an age cycle is complete, the age logic will
return to normal (300 ±75 seconds). Note: If any
port is unplugged, all addresses will be
automatically aged out.
0
Link Change Age
R/W
0
Register 3 (0×03): Global Control 1
Address
Name
Description
Mode
Default
1, switch all packets including bad ones. Used
solely for debugging purpose. Works in
conjunction with sniffer mode.
7
Pass All Frames
R/W
0
1 = Enable support 2K Byte packet
0 = Disable support 2K Byte packet
6
2K Byte Packet Support
R/W
0
0
Pin PMRXD3
strap option.
PD(0): Enable Tx
flow control
(default).
0, will enable transmit flow control based on AN
result.
IEEE 802.3x Transmit
Flow Control Disable
5
R/W
1, will not enable transmit flow control regardless
of AN result.
PU(1): Disable
Tx/Rx flow
control.
Note: SPFLC
has internal pull-
down.
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Global Registers (Continued)
Register 3 (0×03): Global Control 1
Address Name
Description
Mode
Default
0
Pin PMRXD3
strap option.
0, will enable receive flow control based on AN
result.
PD (0): Enable
Rx flow control
(default).
1, will not enable receive flow control regardless
of AN result.
IEEE 802.3x Receive
4
R/W
Flow Control Disable
Note: Bit 5 and bit 4 default values are controlled
by the same pin, but they can be programmed
independently.
PU(1): Disable
Tx/Rx flow
control.
Note: SPFLC
has internal pull-
down.
1, will check frame length field in the IEEE
packets.
3
Frame Length Field Check
R/W
0
1
If the actual length does not match, the packet will
be dropped (for L/T <1500).
Pin LED[5][2]
strap option.
PD(0): Aging
disable.
1, enable age function in the chip.
0, disable aging function.
2
1
Aging Enable
R/W
R/W
PU(1): Aging
enable (default).
Note: LED[5][2]
has internal pull
up.
Fast Age Enable
1 = Turn on fast age (800µs).
0
0
Pin PMRXD0
strap option.
PD(0): Disable
aggressive back
off (default).
1 = Enable more aggressive back-off algorithm in
half duplex mode to enhance performance. This is
not an IEEE standard.
0
Aggressive Back Off Enable
R/W
PU(1):
Aggressive back
off.
Note: SPPE has
internal pull
down.
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Global Registers (Continued)
Register 4 (0×04): Global Control 2
Address Name
Description
Mode
Default
This feature is used for port VLAN (described in
Register 17, Register 33...).
Unicast Port-VLAN Mismatch
Discard
7
1, all packets can not cross VLAN boundary.
R/W
1
0, unicast packets (excluding unknown/
multicast/broadcast) can cross VLAN boundary.
1, “Broadcast Storm Protection” does not include
multicast packets. Only DA=FFFFFFFFFFFF
packets will be regulated.
Multicast Storm Protection
Disable
6
R/W
R/W
1
1
0, “Broadcast Storm Protection” includes
DA = FFFFFFFFFFFF and DA[40] = 1 packets.
1, carrier sense based backpressure is selected.
0, collision based backpressure is selected.
5
4
Back Pressure Mode
1, fair mode is selected. In this mode, if a flow
control port and a non-flow control port talk to the
same destination port, packets from the non-flow
control port may be dropped. This is to prevent
the flow control port from being flow controlled for
an extended period of time.
Flow Control and Back
Pressure fair Mode
R/W
1
0
0, in this mode, if a flow control port and a non-
flow control port talk to the same destination port,
the flow control port will be flow controlled. This
may not be “fair” to the flow control port.
Pin PMRXD1
strap option.
1, the switch will not drop packets when 16 or
more collisions occur.
PD(0): (default )
Drop excessive
collision packets.
PU(1): Don’t
3
No Excessive Collision Drop
R/W
0, the switch will drop packets when 16 or more
collisions occur.
drop excessive
collision packets.
Note: SPDECP
has internal pull
down.
1, will accept packet sizes up to 1916 bytes
(inclusive). This bit setting will override setting
from bit 1 of the same register.
2
Huge Packet Support
R/W
0
0, the maximum packet size will be determined by
bit 1 of this register.
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Global Registers (Continued)
Register 4 (0×04): Global Control 2
Address Name
Description
Mode
R/W
RO
Default
0
Pin PMRXER
strap option.
1, will accept packet sizes up to 1536 bytes
(inclusive).
PD(0): (default)
Legal Maximum Packet
0, 1522 bytes for tagged packets (not including
packets with STPID from CPU to ports 1-4), 1518
bytes for untagged packets. Any packets larger
than the specified value will be dropped.
1518/1522 byte
packets.
1
Size Check Disable
PU(1): 1536 byte
packets.
Note: SPPSZ
has internal pull-
down.
0
Reserved
N/A
0
Register 5 (0×05): Global Control 3
Address Name
Description
Mode
Default
1, 802.1q VLAN mode is turned on. VLAN table
needs to set up before the operation.
7
6
802.1q VLAN Enable
R/W
0
0, 802.1q VLAN is disabled.
1, IGMP snoop enabled. All the IGMP packets will
be forwarded to Switch MII port.
IGMP Snoop Enable on
Switch SW5-MII Interface
R/W
R/W
0
0
0, IGMP snoop disabled.
1, direct mode on port 5. This is a special mode
for the Switch MII interface. Using preamble
before MRXDV to direct switch to forward
packets, bypassing internal look-up.
Enable Direct Mode on
5
Switch SW5-MII Interface
0, normal operation.
1, packets forwarded to Switch MII interface will
be pre-tagged with the source port number
(preamble before MRXDV).
Enable Pre-Tag on
4
R/W
RO
0
Switch SW5-MII Interface
0, normal operation.
N/A
Reserved
00
3 − 2
1, the last 5 digits in the VID field are used as a
mask to determine which port(s) the packet
should be forwarded to.
0, no tag masks.
1
0
Enable “Tag” Mask
R/W
R/W
0
0
Note: Turn off the 802.1q VLAN mode (reg0x5, bit
7 = 0) for this bit to work.
1, will do Rx AND Tx sniff (both source port and
destination port need to match).
Sniff Mode Select
0, will do Rx OR Tx sniff (Either source port or
destination port needs to match).
This is the mode used to implement Rx only sniff.
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Global Registers (Continued)
Register 6 (0×06): Global Control 4
Address Name
Description
Mode
Default
1, enable half-duplex back pressure on switch MII
interface.
Switch SW5-MII Back Pressure
Enable
7
R/W
0
0, disable back pressure on switch MII interface.
Pin SMRXD2
strap option.
PD(0): (default)
Full-duplex
mode.
1, enable MII interface half-duplex mode.
0, enable MII interface full-duplex mode.
Switch SW5-MII Half-Duplex
Mode
6
R/W
PU(1): Half-
duplex mode.
Note: SMRXD2
has internal pull-
down.
Pin SMRXD3
strap option.
PD(0): (default)
Disable flow
control.
1, enable full-duplex flow control on switch MII
interface.
Switch SW5-MII Flow Control
Enable
5
R/W
0, disable full-duplex flow control on switch MII
interface.
PU(1): enable
flow control.
Note: SMRXD3
has internal pull-
down.
Pin SMRXD1
strap option.
PD(0): (default)
Enable
1, the switch SW5-MII is in 10Mbps mode.
0, the switch SW5-MII is in 100Mbps mode.
100Mbps.
4
Switch SW5-MII Speed
Null VID Replacement
R/W
PU(1): Enable
10Mbps.
Note: SMRXD1
has internal pull-
down.
1, will replace null VID with port VID (12 bits).
0, no replacement for null VID.
3
R/W
R/W
0
This along with the next register determines how
many
Broadcast Storm
000
2 − 0
“64 byte blocks” of packet data allowed on an
input port in a preset period. The period is 50ms
for 100BT or 500ms for 10BT. The default is 1%.
Protection Rate Bit [10:8]
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Global Registers (Continued)
Register 7 (0×07): Global Control 5
Address Name
Description
Mode
Default
This along with the previous register determines
how many “64 byte blocks” of packet data are
allowed on an input port in a preset period. The
period is 50ms for
Broadcast Storm
7 − 0
R/W
0x4A(1)
Protection Rate Bit [7:0]
100BT or 500ms for 10BT. The default is 1%.
Note:
1. 148,800 frames/sec × 1% = 74 frames/interval (approx.) = 0 × 4A.
Register 8 (0×08): Global Control 6
Address Name
Description
Mode
Default
Factory Testing
Reserved
R/W
7 − 0
0 × 24
Register 9 (0×09): Global Control 7
Address Name
Description
Mode
Default
Factory Testing
Reserved
R/W
7 − 0
0 × 28
Register 10 (0×0A): Global Control 8
Address
Name
Description
Mode
Default
Factory Testing
Reserved
R/W
7 − 0
0 × 00
Register 11 (0×0B): Global Control 9
Address
Name
Description
Mode
Default
7
6
5
4
Reversed
Reserved
Reserved
Reserved
N/A, don’t change
N/A, don’t change
N/A, don’t change
N/A, don’t change
RO
RO
RO
RO
0
0
0
0
1 = disable PHY power-save mode.
0 = enable PHY power-save mode.
3
2
PHY Power Save
Reserved
R/W
RO
0
0
N/A, don’t change
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Global Registers (Continued)
Register 11 (0×0B): Global Control 9
Address
Name
Description
Mode
Default
0 = led mode 0.
1 = led mode 1.
Mode 0, link at
100/Full LEDx[2,1,0]=0,0,0
LEDx[2,1,0]=0,1,0
100/Half
10/Half
Pin SMRXD0 -
strap option. Pull-
down(0):
10/Full LEDx[2,1,0]=0,0,1
LEDx[2,1,0]=0,1,1
Mode 1, link at
Enabled led
100/Full LEDx[2,1,0]=0,1,0
LEDx[2,1,0]=0,1,1
100/Half
10/Half
mode 0. Pull-
up(1): Enabled
led mode 1.
Note: SMRXD0
has internal pull-
down 0.
1
LED Mode
R/W
10/Full LEDx[2,1,0]=1,0,0
LEDx[2,1,0]=1,0,1
(0=LED on, 1=LED off)
Mode 0
Mode 1
LEDX_2
LEDX_1
LEDX_0
Lnk/Act
Fulld/Col
Speed
100Lnk/Act
10Lnk/Act
Fulld
Select the SPI/SMI clock edge for sampling
SPI/SMI read data
SPI/SMI Read Sampling Clock
Edge Select
0
1 = trigger by rising edge of SPI/SMI clock (for
high speed SPI about 25MHz and SMI about
10MHz)
R/W
0
0 = trigger by falling edge of SPI/SMI clock
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Global Registers (Continued)
Register 12 (0×0C): Global Control 10
Address
Name
Description
Mode
RO
Default
7
6
Reserved
Reserved
N/A, don’t change
N/A, don’t change
0
1
RO
Select the internal clock speed for SPI, MDI
interface:
00 = 41.67MHz (SPI up to 6.25MHz, MDC up to
6MHz)
01 = 83.33MHz Default (SPI SCL up to 12.5MHz,
MDC up to 12MHz)
CPU interface clock select
R/W
01
5 − 4
10 = 125MHz (for high-speed SPI about 25MHz)
11 = Reserved
3
2
Reserved
Reserved
N/A
RO
RO
00
1
N/A, don’t change
Tail Tag feature is applied for Port 5 only.
1 = Insert 1 Byte of data right before FCS
0 = Do not insert
1
0
Tail Tag Enable
R/W
R/W
0
0
1 = Switch will not filter 802.1x “flow control”
packets
Pass Flow Control Packet
0 = Switch will filter 802.1x “flow control” packets
Register 13 (0×0D): Global Control 11
Address
Name
Description
Mode
Default
Factory Testing
N/A, don’t change
RO
00000000
7 − 0
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Global Registers (Continued)
Register 14 (0×0E): Power-Down Management Control 1
Address
Name
Description
Mode
RO
Default
7
6
Reserved
Reserved
N/A, don’t change
N/A, don’t change
0
0
RO
Pll power down:
1 = Disable
0 = Enable
5
PLL Power Down
R/W
0
Note: It takes the effect in the Energy Detect
mode (EDPD mode).
00
Pin LED[4][0]
strap option.
Power management mode:
00 = Normal mode (D0)
PD(0): Select
Energy detection
mode
Power Management Mode
01 = Energy Detection mode (D2)
10 = soft Power Down mode (D3)
11 = Power Saving mode (D1)
R/W
4 − 3
PU(1): (default)
Normal mode
Note: LED[4][0]
has internal pull-
up.
Register 14 (0×0E): Power-Down Management Control 1
Address
2 − 1
0
Name
Description
Mode
R/W
RO
Default
Reserved
Reserved
N/A, don’t change
N/A, don’t change
00
0
Register 15 (0×0F): Power-Down Management Control 2
Address
Name
Description
Mode
Default
When the Energy Detect mode is on, this value is
used to control the minimum period that the no
energy event has to be detected consecutively
before the device enters the low power state. The
unit is 20 ms. The default of go_sleep time is 1.6
seconds (80Dec x 20ms).
7 - 0
Go_sleep_time[7:0]
R/W
01010000
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Port Registers
The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are
the same for all ports, but the address for each port is different, as indicated:
Register 16 (0×10): Port 1 Control 0
Register 32 (0×20): Port 2 Control 0
Register 48 (0×30): Port 3 Control 0
Register 64 (0×40): Port 4 Control 0
Register 80 (0×50): Port 5 Control 0
Address
Name
Description
Mode
Default
1, enable broadcast storm protection for ingress
packets on the port.
0, disable broadcast storm protection.
Broadcast Storm Protection
Enable
7
R/W
0
1, enable DiffServ priority classification for ingress
packets on port.
0, disable DiffServ function.
DiffServ Priority Classification
Enable
6
5
R/W
R/W
0
0
1, enable 802.1p priority classification for ingress
packets on port.
0, disable 802.1p.
802.1p Priority Classification
Enable
= 00, ingress packets on port will be classified as
priority 0 queue if “Diffserv” or “802.1p” classification
is not enabled or fails to classify.
= 01, ingress packets on port will be classified as
priority 1 queue if “Diffserv” or “802.1p” classification
is not enabled or fails to classify.
= 10, ingress packets on port will be classified as
priority 2 queue if “Diffserv” or “802.1p” classification
is not enabled or fails to classify.
Port-Based Priority
Classification Enable
R/W
00
4 − 3
= 11, ingress packets on port will be classified as
priority 3 queue if “Diffserv” or “802.1p” classification
is not enabled or fails to classify.
Note: “DiffServ”, “802.1p” and port priority can be
enabled at the same time. The OR’d result of
802.1p and DSCP overwrites the port priority.
1, when packets are output on the port, the switch
will add 802.1q tags to packets without 802.1q tags
when received. The switch will not add tags to
packets already tagged. The tag inserted is the
ingress port’s “port VID.”
2
1
Tag Insertion
Tag Removal
R/W
R/W
0
0
0, disable tag insertion.
1, when packets are output on the port, the switch
will remove 802.1q tags from packets with 802.1q
tags when received. The switch will not modify
packets received without tags.
0, disable tag removal.
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Port Registers (Continued)
Register 16 (0×10): Port 1 Control 0
Register 32 (0×20): Port 2 Control 0
Register 48 (0×30): Port 3 Control 0
Register 64 (0×40): Port 4 Control 0
Register 80 (0×50): Port 5 Control 0
Address
Name
Description
Mode
Default
This bit0 in the register16/32/48/64/80 should be
combination with Register177/193/209/225/241 bit 1
for port 1-5 will select the split of 1/2/4 queues:
For port 1, [Register177 bit 1, Register16 bit 0] =
[11], Reserved
[10], the port output queue is split into four priority
queues or if map 802.1p to priority 0-3 mode.
0
Two Queues Split Enable
R/W
0
[01], the port output queue is split into two priority
queues or if map 802.1p to priority 0-3 mode.
[00], single output queue on the port. There is no
priority differentiation even though packets are
classified into high or low priority.
Register 17 (0×11): Port 1 Control 1
Register 33 (0×21): Port 2 Control 1
Register 49 (0×31): Port 3 Control 1
Register 65 (0×41): Port 4 Control 1
Register 81 (0×51): Port 4 Control 1
Address Name
Description
Mode Default
1, port is designated as sniffer port and will transmit packets that are
monitored.
0, port is a normal port.
1, all the packets received on the port will be marked as “monitored
packets” and forwarded to the designated “sniffer port.”
0, no receive monitoring.
1, all the packets transmitted on the port will be marked as “monitored
packets” and forwarded to the designated “sniffer port.”
0, no transmit monitoring.
7
6
5
Sniffer Port
R/W
R/W
R/W
0
0
0
Receive Sniff
Transmit Sniff
Define the port’s Port VLAN membership. Bit 4 stands for port 5, bit 3
for port 4...bit 0 for port 1. The port can only communicate within the
membership. A ‘1’ includes a port in the membership; a ‘0’ excludes a
port from membership.
Port VLAN Membership
R/W
0x1f
4 − 0
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Port Registers (Continued)
Register 18 (0×12): Port 1 Control 2
Register 34 (0×22): Port 2 Control 2
Register 50 (0×32): Port 3 Control 2
Register 66 (0×42): Port 4 Control 2
Register 82 (0×52): Port 5 Control 2
Address Name
Description
Mode
Default
1, If packet ‘s “user priority field” is greater than the “user
priority field” in the port default tag register, replace the
packet’s “user priority field” with the “user priority field” in
the port default tag register control 3.
7
User Priority Ceiling
R/W
0
0, no replace packet’s priority filed with port default tag
priority filed of the port register control 3 bit [7:5].
1, the switch will discard packets whose VID port
membership in VLAN table bits [11:7] does not include
the ingress port.
0, no ingress VLAN filtering.
1, the switch will discard packets whose VID does not
match ingress port default VID.
6
5
Ingress VLAN Filtering.
R/W
R/W
0
0
Discard Non-PVID
packets
0, no packets will be discarded.
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Port Registers (Continued)
Register 18 (0×12): Port 1 Control 2
Register 34 (0×22): Port 2 Control 2
Register 50 (0×32): Port 3 Control 2
Register 66 (0×42): Port 4 Control 2
Register 82 (0×52): Port 5 Control 2
Address Name
Description
Mode
Default
0
Strap-in option
LED1_1/PCOL For
port 3/port 4
LED1_1 default
Pull up (1): Not
force flow control;
1, will always enable Rx and Tx flow control on the port,
regardless of AN result.
0, the flow control is enabled based on AN result
(Default)
PCOL default Pull-
down (0): Not force
flow control.
4
Force Flow Control
R/W
LED1_1 Pull down
(0): Force flow
control; PCOL Pull-
up (1): Force flow
control.
Note: This bit is reserved for port 5, SW5-MII use the
register 6 bit5 for the flow control.
Note: LED1_1 has
internal pull-up;
PCOL have internal
pull-down.
0
Pin PMRXD2 strap
option.
1, enable port half-duplex back pressure.
0, disable port half-duplex back pressure.
Pull-down (0):
disable back
pressure.
3
Back Pressure Enable
R/W
Note: This bit is reserved for port 5, SW5-MII use the
register 6 bit7 for the back pressure.
Pull-up(1): enable
back pressure.
Note: PMRXD2
has internal pull-
down.
1, enable packet transmission on the port.
0, disable packet transmission on the port.
2
1
0
Transmit Enable
Receive Enable
Learning Disable
R/W
R/W
R/W
1
1
0
1, enable packet reception on the port.
0, disable packet reception on the port.
1, disable switch address learning capability.
0, enable switch address learning.
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Port Registers (Continued)
Register 19 (0×13): Port 1 Control 3
Register 35 (0×23): Port 2 Control 3
Register 51 (0×33): Port 3 Control 3
Register 67 (0×43): Port 4 Control 3
Register 83 (0×53): Port 5 Control 3
Address Name
Description
Mode
Default
Port’s default tag, containing:
7 − 5: user priority bits
4: CFI bit
Default Tag [15:8]
R/W
0
7 − 0
3 − 0 : VID[11:8]
Register 20 (0×14): Port 1 Control 4
Register 36 (0×24): Port 2 Control 4
Register 52 (0×34): Port 3 Control 4
Register 68 (0×44): Port 4 Control 4
Register 84 (0×54): Port 5 Control 4
Address Name
Description
Mode
Default
Default port 1’s tag, containing:
7 − 0: VID[7:0]
Default Tag [7:0]
R/W
1
7 − 0
Note:
Registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) Associated with the ingress untagged packets, and used for
egress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up.
Register 87 (0×57): Reserved Control Register
Address Name
Description
Mode
Default
Reserved
N/A, don’t change
RO
7 − 0
0 × 00
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Port Registers (Continued)
Register 25 (0×19): Port 1 Status 0
Register 41 (0×29): Port 2 Status 0
Register 57 (0×39): Port 3 Status 0
Register 73 (0×49): Port 4 Status 0
Register 89 (0×59): Reserved
Address Name
Description
Mode
R/W
RO
Default
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
7
6
5
Hp_mdix
1
0
0
Factory Testing
Polrvs
Reserved
1 = Polarity is reversed
RO
0 = Polarity is not reversed
1 = Transmit flow control feature is active
0 = Transmit flow control feature is inactive
1 = Receive flow control feature is active
0 = Receive flow control feature is inactive
1 = Link speed is 100Mbps
Transmit Flow Control
Enable
4
3
2
RO
RO
RO
0
0
0
Receive Flow Control
Enable
Operation Speed
0 = Link speed is 10Mbps
1 = Link duplex is full
1
0
Operation Duplex
Reserved
RO
RO
0
0
0 = Link duplex is half
N/A
Register 26 (0×1A): Port 1 PHY Special Control/Status
Register 42 (0×2A): Port 2 PHY Special Control/Status
Register 58 (0×3A): Port 3 PHY Special Control/Status
Register 74 (0×4A): Port 4 PHY Special Control/Status
Register 90 (0×5A): Reserved
Address Name
Description
Mode
Default
7
Vct 10M Short
1 = less than 10 meter short detected
RO
0
00 = Normal condition
01 = Open condition detected in cable
10 = Short condition detected in cable
11 = Cable diagnostic test has failed
1 = Enable cable diagnostic test. After VCT test has
completed, this bit will be self-cleared.
0 = Indicate cable diagnostic test (if enabled) has
completed and the status information is valid for read.
1 = Force link pass
6 - 5
Vct_result
RO
00
0
R/W
(SC)
4
Vct_enable
3
2
Force_lnk
Pwrsave
R/W
R/W
0
0
0 = Normal Operation
1 = Enable power saving
0 = Disable power saving
1 = Perform Remote loopback, loopback on port 1 as
follows: Port 1 (reg. 26, bit 1 = ‘1’)
Start : RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Setting reg. 42, 58, 74, 90, bit 1 = ‘1’ will perform
remote loopback on port 2, 3, 4, 5.
0 = Normal Operation.
1
Remote Loopback
Vct_fault_count [8]
R/W
RO
0
0
Bits[8] of VCT fault count.
0
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Port Registers (Continued)
Register 27 (0×1B): Port 1 LinkMD Result
Register 43 (0×2B): Port 2 LinkMD Result
Register 59 (0×3B): Port 3 LinkMD Result
Register 75 (0×4B): Port 4 LinkMD Result
Register 91 (0×5B): Reserved
Address Name
Description
Mode
Default
Vct_fault_count [7:0]
Bits[7:0] of VCT fault count
7-0
Distance to the fault.
RO
0
It’s approximately 0.4m*Vct_fault_count [8:0]
Register 28 (0×1C): Port 1 Control 5
Register 44 (0×2C): Port 2 Control 5
Register 60 (0×3C): Port 3 Control 5
Register 76 (0×4C): Port 4 Control 5
Register 92 (0×5C): Reserved
Address Name
Description
Mode
Default
0
For port 3/port 4 only.
1, disable auto-negotiation, speed and duplex are
decided by bit 6 and 5 of the same register.
0, auto-negotiation is on.
INVERT of pins
LED[2][1]/LED[5][0]
strap option.
Disable Auto-
Negotiation
7
R/W
PD(0): Disable Auto-
Negotiation.
Note: The register bit value is the INVERT of the
strap value at the pin.
PU(1): Enable Auto-
Negotiation.
Note:LED[2][1]/LED[5][0]
have internal pull up.
1, forced 100BT if AN is disabled (bit 7).
0, forced 10BT if AN is disabled (bit 7).
6
Forced Speed
R/W
1
0
For port 3/port 4 only.
Pins LED1_0/PCRS
strap option.
1. For force half-duplex:
1, forced full-duplex if (1) AN is disabled or (2) AN
is enabled but failed.
0, forced half-duplex if (1) AN is disabled or (2) AN
is enabled but failed (Default).
LED1_0 pin Pull-up(1)
(default)
5
Forced Duplex
R/W
PCRS pin Pull-down (0)
(default). 2. For force
full-duplex: LED1_0 pin
Pull-down(0).
PCRS Pull-up (1):
Note: LED1_0 has
internal pull-up; PCRS
have internal pull down.
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Port Registers (Continued)
Register 28 (0×1C): Port 1 Control 5
Register 44 (0×2C): Port 2 Control 5
Register 60 (0×3C): Port 3 Control 5
Register 76 (0×4C): Port 4 Control 5
Register 92 (0×5C): Reserved
Address Name
Description
Mode
Default
1, advertise flow control capability.
0, suppress flow control capability from transmission to
link partner.
Advertised Flow Control
Capability
4
3
2
1
0
R/W
1
1, advertise 100BT full-duplex capability.
0, suppress 100BT full-duplex capability from
transmission to link partner.
Advertised 100BT Full-
Duplex Capability
R/W
R/W
R/W
R/W
1
1
1
1
1, advertise 100BT half-duplex capability.
0, suppress 100BT half-duplex capability from
transmission to link partner.
Advertised 100BT Half-
Duplex Capability
1, advertise 10BT full-duplex capability.
0, suppress 10BT full-duplex capability from
transmission to link partner.
Advertised 10BT Full-
Duplex Capability
1, advertise 10BT half-duplex capability.
0, suppress 10BT half-duplex capability from
transmission to link partner.
Advertised 10BT Half-
Duplex Capability
Register 29 (0×1D): Port 1 Control 6
Register 45 (0×2D): Port 2 Control 6
Register 61 (0×3D): Port 3 Control 6
Register 77 (0×4D): Port 4 Control 6
Register 93 (0×5D): Reserved
Address Name
Description
Mode
Default
1, turn off all port’s LEDs (LEDx_2, LEDx_1, LEDx_0,
where “x” is the port number). These pins will be
driven high if this bit is set to one.
7
LED Off
R/W
0
0, normal operation.
1, disable port’s transmitter.
0, normal operation.
6
5
Txids
R/W
0
0
1, restart auto-negotiation.
0, normal operation.
R/W
(SC)
Restart AN
4
3
FX reserved
Power Down
N/A
RO
0
0
1, power down.
0, normal operation.
R/W
1, disable auto MDI/MDI-X function.
0, enable auto MDI/MDI-X function.
2
1
Disable Auto MDI/MDI-X
Forced MDI
R/W
R/W
0
0
1, if auto MDI/MDI-X is disabled, force PHY into MDI
mode.
0, MDI-X mode.
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Port Registers (Continued)
Register 29 (0×1D): Port 1 Control 6
Register 45 (0×2D): Port 2 Control 6
Register 61 (0×3D): Port 3 Control 6
Register 77 (0×4D): Port 4 Control 6
Register 93 (0×5D): Reserved
Address Name
Description
Mode
Default
1 = Perform MAC loopback, loop back path as follows:
E.g. set port 1 MAC Loopback (reg. 29, bit 0 = ‘1’), use
port 2 as monitor port. The packets will transfer
Start: Port 2 receiving (also can start to receive
packets from port 3, 4, 5).
Loop-back: Port 1’s MAC.
0
MAC Loopback
R/W
0
End: Port 2 transmitting (also can end at port 3, 4,
5 respectively).
Setting reg. 45, 61, 77, 93, bit 0 = ‘1’ will perform MAC
loopback on port 2, 3, 4, 5 respectively.
0 = Normal Operation.
Register 30 (0×1E): Port 1 Status 1
Register 46 (0×2E): Port 2 Status 1
Register 62 (0×3E): Port 3 Status 1
Register 78 (0×4E): Port 4 Status 1
Register 94 (0×5E): Reserved
Address Name
Description
Mode
Default
1, MDI.
0, MDI-X.
7
6
5
4
3
2
MDIX Status
AN Done
RO
0
1, AN done.
0, AN not done.
RO
RO
RO
RO
RO
0
0
0
0
0
1, link good.
0, link not good.
Link Good
Partner Flow Control
Capability
1, link partner flow control capable.
0, link partner not flow control capable.
Partner 100BT Full-
Duplex Capability
1, link partner 100BT full-duplex capable.
0, link partner not 100BT full-duplex capable.
Partner 100BT Half-
Duplex Capability
1, link partner 100BT half-duplex capable.
0, link partner not 100BT half-duplex capable.
1, link partner 10BT full-duplex capable.
0, link partner not 10BT full-duplex capable.
1, link partner 10BT half-duplex capable.
0, link partner not 10BT half-duplex capable.
Partner 10BT Full-Duplex
Capability
1
0
RO
RO
0
0
Partner 10BT Half-Duplex
Capability
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Port Registers (Continued)
Register 31 (0×1F): Port 1 Control 7 and Status 2
Register 47 (0×2F): Port 2 Control 7 and Status 2
Register 63 (0×3F): Port 3 Control 7 and Status 2
Register 79 (0×4F): Port 4 Control 7 and Status 2
Register 95 (0×5F): Reserved
Address Name
Description
Mode
Default
1 = Perform PHY loopback, loop back path as follows:
E.g. set port 1 PHY Loopback (reg. 31, bit 7 = ‘1’)
Use the port 2 as monitor port. The packets will transfer
Start: Port 2 receiving (also can start from port 3, 4,
5).
7
PHY Loopback
R/W
0
Loopback: PMD/PMA of port 1’s PHY
End: Port 2 transmitting (also can end at port 3, 4,
5 respectively).
Setting reg. 47, 63, 79, 95, bit 7 = ‘1’ will perform PHY
loopback on port 2, 3, 4, 5 respectively.
0 = Normal Operation.
6
5
Reserved
RO
0
0
1, electrical isolation of PHY from MII and TX+/TX-.
0, normal operation.
PHY Isolate
R/W
R/W
(SC)
1, PHY soft reset. This bit is self-clear.
0, normal operation.
4
3
Soft Reset
Force Link
0
0
1, force link in the PHY.
R/W
RO
0, normal operation
Indicate the current state of port operation mode:
[000] = Reserved
[001] = Still in auto-negotiation
[010] = 10BASE-T half duplex
[011] = 100BASE-TX/FX half duplex
[100] = Reserved
Port Operation Mode
Indication
001
2 − 0
[101] = 10BASE-T full duplex
[110] = 100BASE-TX/FX full duplex
[111] = Reserved
Note:
Port Control 12 and 13, 14 and Port Status 1, 2 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition.
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Advanced Control Registers
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in
MAC pause control frames.
Register 104 (0×68): MAC Address Register 0
Address Name
Description
Mode
Default
MACA[47:40]
R/W
0x00
7 − 0
Register 105 (0×69): MAC Address Register 1
Address Name Description
MACA[39:32]
Mode
Default
R/W
0x10
7 − 0
Register 106 (0×6A): MAC Address Register 2
Address Name Description
MACA[31:24]
Mode
Default
R/W
0xA1
7 − 0
Register 107 (0×6B): MAC Address Register 3
Address Name Description
MACA[23:16]
Mode
Default
R/W
0xff
7 − 0
Register 108 (0×6C): MAC Address Register 4
Address Name Description
MACA[15:8]
Mode
Default
R/W
0xff
7 − 0
Register 109 (0×6D): MAC Address Register 5
Address Name Description
Mode
Default
MACA[7:0]
R/W
0xff
7 − 0
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Advanced Control Registers (Continued)
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or
the MIB counters.
Register 110 (0×6E): Indirect Access Control 0
Address Name
Description
Mode
Default
Reserved
Reserved.
R/W
000
7 − 5
1, read cycle.
4
Read High Write Low
R/W
0
0, write cycle.
00 = Static MAC address table selected.
01 = VLAN table selected.
10 = Dynamic address table selected.
11 = MIB counter selected.
Table Select
R/W
R/W
0
3 − 2
1 − 0
Indirect Address High
00
Bit 9 − 8 of indirect address.
Register 111 (0×6F): Indirect Access Control 1
Address Name
Description
Mode
Default
Indirect Address Low
R/W
00000000
7 − 0
Note:
Bit 7 − 0 of indirect address.
Write to Register 111 will actually trigger a command. Read or write access will be decided by bit 4 of Register 110.
Register 112 (0×70): Indirect Data Register 8
Address Name
Description
Mode
Default
Indirect Data
R/W
00000
68 − 64
Bit 68 − 64 of indirect data.
Register 113 (0×71): Indirect Data Register 7
Address Name
Description
Mode
Default
Indirect Data
R/W
00000000
63 − 56
Bit 63 − 56 of indirect data.
Register 114 (0×72): Indirect Data Register 6
Address Name
Description
Mode
Default
Indirect Data
R/W
00000000
55 − 48
Bit 55 − 48 of indirect data.
Register 115 (0×73): Indirect Data Register 5
Address Name
Description
Mode
Default
Indirect Data
R/W
00000000
47 − 40
Bit 47 − 40 of indirect data.
Register 116 (0×74): Indirect Data Register 4
Address Name
Description
Mode
Default
Indirect Data
R/W
00000000
39 − 32
Bit 39 − 32 of indirect data.
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Advanced Control Registers (Continued)
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or
the MIB counters.
Register 117 (0×75): Indirect Data Register 3
Address Name
Description
Mode
Default
Indirect Data
R/W
00000000
31 − 24
Bit of 31 − 24 of indirect data
Register 118 (0×76): Indirect Data Register 2
Address Name
Description
Mode
Default
Indirect Data
R/W
00000000
23 − 16
Bit 23 − 16 of indirect data.
Register 119 (0×77): Indirect Data Register 1
Address Name
Description
Mode
Default
Indirect Data
R/W
00000000
15 − 8
Bit 15 − 8 of indirect data.
Register 120 (0×78): Indirect Data Register 0
Address Name
Description
Mode
Default
Indirect Data
R/W
00000000
7 − 0
Bit 7 − 0 of indirect data.
Register 124 (0x7C): Interrupt Status Register
Address Name Description
Mode
RO
Default
000
Reserved
Reserved
Reserved
7 − 5
4
Reserved
RO
0
1, Port 4 interrupt request
0, normal
3
2
1
0
Port 4 Interrupt Status
RO
RO
RO
RO
0
0
0
0
Note: This bit is set by port 4 link change. Write a “1”
to clear this bit
1, Port 3 interrupt request
0, normal
Port 3 Interrupt Status
Port 2 Interrupt Status
Port 1 Interrupt Status
Note: This bit is set by port 3 link change. Write a “1”
to clear this bit
1, Port 2 interrupt request
0, normal
Note: This bit is set by port 2 link change. Write a “1”
to clear this bit
1, Port 1 interrupt request
0, normal
Note: This bit is set by port 1 link change. Write a “1”
to clear this bit
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Advanced Control Registers (Continued)
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or
the MIB counters.
Register 125 (0x7D): Interrupt Mask Register
Address Name
Description
Reserved.
Reserved
Mode
RO
Default
000
Reserved
7 − 5
4
Reserved
RO
0
1, Port 4 interrupt mask
0, normal
3
2
1
0
Port 4 Interrupt Mask
R/W
R/W
R/W
R/W
0
0
0
0
1, Port 3 interrupt mask
0, normal
Port 3 Interrupt Mask
Port 2 Interrupt Mask
Port 1 Interrupt Mask
1, Port 2 interrupt mask
0, normal
1, Port 1 interrupt mask
0, normal
The registers 128, 129 can be used to map from 802.1p priority field 0-7 to switch’s four priority queues 0-3, 0x3 is highest
priority queues as priority 3, 0x0 is lowest priority queues as priority 0.
Register 128 (0x80): Global Control 12
Address Name
Description
Mode
Default
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x3
7 - 6
5 - 4
3 - 2
1 - 0
Tag_0x3
R/W
0x1
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x2
Tag_0x2
Tag_0x1
Tag_0x0
R/W
R/W
R/W
0x1
0x0
0x0
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x1
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x0
Register 129 (0x81): Global Control 13
Address Name
Description
Mode
Default
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x7
7 - 6
5 - 4
3 - 2
1 - 0
Tag_0x7
Tag_0x6
Tag_0x5
Tag_0x4
R/W
0x3
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x6
R/W
R/W
R/W
0x3
0x2
0x2
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x5
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x4
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Advanced Control Registers (Continued)
Register 130 (0x82): Global Control 14
Address Name
Description
Mode
Default
When the 2 Queue configuration is selected, these
Pri_2Q[1:0] bits are used to map the 2-bit result of
IEEE 802.1p from register 128/129 or TOS/DiffServ
from register 144- 159 mapping (for 4 Queues) into
two queues low/high priorities.
2-bit result of IEEE 802.1p or TOS/DiffServ
00 (0) = map to Low priority queue
Pri_2Q[1:0]
01 (1) = Prio_2Q[0] map to Low/High priority queue
10 (2) = Prio_2Q[1] map to Low/High priority queue
11 (3) = map to High priority queue
(Note that program
Prio_2Q[1:0] = 01 is not
supported and should be
avoided)
R/W
10
7 − 6
Pri_2Q[1:0] =
00: Result 0, 1, 2 are low priority. 3 is high priority.
10: Result 0, 1 are low priority. 2, 3 are high priority
(default).
11: Result 0 is low priority. 1, 2, 3 are high priority.
N/A, don’t change
5
4
Reserved
Reserved
Reserved
Reserved
Reserved
RO
RO
RO
RO
RO
0
0
N/A, don’t change
N/A, don’t change
01
0
3 − 2
1
N/A, don’t change
0
N/A, don’t change
0.
Register 131 (0x83): Global Control 15
Address Name
Description
N/A
Mode
RO
Default
7
6
Reserved
Reserved
1
0
N/A
RO
1 = enable supporting unknown unicast packet
forward
Unknown unicast packet
forward
5
R/W
0
0 = disable
00000 = filter unknown unicast packet
00001 = forward unknown unicast packet to port 1
00011 = forward unknown unicast packet to port 1,
port 2
Unknown unicast packet
forward port map
R/W
00000
4 − 0
…
11111 = broadcast unknown unicast packet to all
ports
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Advanced Control Registers (Continued)
Register 132 (0x84): Global Control 16
Address Name
Description
Mode
Default
Output drive strength select[1:0] =
00 = 4mA drive strength
Pin LED[3][0]
strap option. Pull-
down (0): Select
12mA drive
01 = 8mA drive strength (default)
10 = 12mA drive strength
Chip I/O output drive strength
select[1:0]
11 = 16mA drive strength
strength. Pull-up
(1): Select 8mA
drive strength.
Note: LED[3][0]
has internal pull-
up.
R/W
7 − 6
Note:
bit[1] value is the INVERT of the strap value at the
pin.
bit[0] value is the SAME of the strap value at the pin
1 = enable supporting unknown multicast packet
forward
Unknown multicast packet
forward (not including IP
multicast packet)
5
R/W
R/W
0
0 = disable
00000 = filter unknown multicast packet
00001 = forward unknown multicast packet to port 1
00011 = forward unknown multicast packet to port 1,
port 2
Unknown multicast packet
forward port map
00000
4 − 0
…
11111 = broadcast unknown multicast packet to all
ports
Register 133(0x85): Global Control 17
Address Name
Description
Mode
Default
7 - 6
5
Reserved
RO
00
1 = enable supporting unknown VID packet forward
0 = disable
Unknown VID packet forward
R/W
0
00000 = filter unknown VID packet
00001 = forward unknown VID packet to port 1
Unknown VID packet forward 00011 = forward unknown VID packet to port 1, port
4 - 0
R/W
00000
port map
2
…
11111 = broadcast unknown VID packet to all ports
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Advanced Control Registers (Continued)
Register 134 (0x86): Global Control 18
Address Name
Description
Mode
Default
7
Reserved
N/A
RO
0
1 = Enable filtering of self-address unicast and
multicast packet
0 = Do not filter self-address packet
6
Self-Address Filter Enable
R/W
R/W
R/W
0
0
Note: The self-address filtering will filter packets on
the egress port, self MAC address is assigned in the
register 104 − 109.
1 = enable supporting unknown IP multicast packet
forward
Unknown IP multicast packet
forward
5
0 = disable
00000 = filter unknown IP multicast packet
00001 = forward unknown IP multicast packet to port 1
00011 = forward unknown IP multicast packet to port
1, port 2
Unknown IP multicast packet
forward port map
00000
4 − 0
…
11111 = broadcast unknown IP multicast packet to all
ports
Register 135 (0x87): Global Control 19
Address Name
Description
Mode
RO
Default
7
6
Reserved
Reserved
N/A, don’t change
N/A, don’t change
0
0
RO
The unit period for calculating Ingress Rate Limit
00 = 16 ms
Ingress Rate Limit Period
R/W
R/W
01
0
5 − 4
01 = 64 ms
1x = 256 ms
Enable Queue-based Egress Rate Limit
0 = port-base Egress Rate Limit (default)
1 = queue-based Egress Rate Limit
Queue-based Egress Rate
Limit Enabled
3
1 = enable source port PVID tag insertion or non-
insertion option on the egress port for each source port
PVID based on the ports registers control 8.
Insertion Source Port PVID
Tag Selection Enable
2
R/W
RO
0
0 = disable, all packets from any ingress port will be
inserted PVID based on port register control 0 bit 2.
Reserved
N/A, don’t change
00
1 − 0
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Advanced Control Registers (Continued)
Register 144 (0x90): TOS Priority Control Register 0
The IPv4/IPv6 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine
priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular
code that results is mapped to the value in the corresponding bit in the DSCP register.
Address Name
Description
Mode
Default
IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x0C
DSCP[7:6]
R/W
00
7 − 6
5 − 4
3 − 2
1 − 0
IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x08
DSCP[5:4]
DSCP[3:2]
DSCP[1:0]
R/W
R/W
R/W
00
00
00
IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x04
IPv4 and IPv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x00
Register 145 (0x91): TOS Priority Control Register 1
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0x1C
IPv4 and IPv6 mapping _ for value 0x18
IPv4 and IPv6 mapping _ for value 0x14
IPv4 and IPv6 mapping _ for value 0x10
DSCP[15:14]
7 −6
5 −4
3 −2
1 −0
DSCP[13:12]
DSCP[11:10]
DSCP[9:8]
00
00
00
Register 146 (0x92): TOS Priority Control Register 2
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0x2C
IPv4 and IPv6 mapping _ for value 0x28
IPv4 and IPv6 mapping _ for value 0x24
IPv4 and IPv6 mapping _ for value 0x20
DSCP[23:22]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[21:20]
DSCP[19:18]
DSCP[17:16]
00
00
00
Register 147 (0x93): TOS Priority Control Register 3
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0x3C
IPv4 and IPv6 mapping _ for value 0x38
IPv4 and IPv6 mapping _ for value 0x34
IPv4 and IPv6 mapping _ for value 0x30
DSCP[31:30]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[29:28]
DSCP[27:26]
DSCP[25:24]
00
00
00
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Advanced Control Registers (Continued)
Register 148 (0x94): TOS Priority Control Register 4
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0x4C
IPv4 and IPv6 mapping _ for value 0x48
IPv4 and IPv6 mapping _ for value 0x44
IPv4 and IPv6 mapping _ for value 0x40
DSCP[39:38]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[37:36]
DSCP[35:34]
DSCP[33:32]
00
00
00
Register 149 (0x95): TOS Priority Control Register 5
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0x5C
IPv4 and IPv6 mapping _ for value 0x58
IPv4 and IPv6 mapping _ for value 0x54
IPv4 and IPv6 mapping _ for value 0x50
DSCP[47:46]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[45:44]
DSCP[43:42]
DSCP[41:40]
00
00
00
Register 150 (0x96): TOS Priority Control Register 6
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0x6C
IPv4 and IPv6 mapping _ for value 0x68
IPv4 and IPv6 mapping _ for value 0x64
IPv4 and IPv6 mapping _ for value 0x60
DSCP[55:54]
7 −6
5 −4
3 −2
1 −0
DSCP[53:52]
DSCP[51:50]
DSCP[49:48]
00
00
00
Register 151 (0x97): TOS Priority Control Register 7
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0x7C
IPv4 and IPv6 mapping _ for value 0x78
IPv4 and IPv6 mapping _ for value 0x74
IPv4 and IPv6 mapping _ for value 0x70
DSCP[63:62]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[61:60]
DSCP[59:58]
DSCP[57:56]
00
00
00
Register 152 (0x98): TOS Priority Control Register 8
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0x8C
IPv4 and IPv6 mapping _ for value 0x88
IPv4 and IPv6 mapping _ for value 0x84
IPv4 and IPv6 mapping _ for value 0x80
DSCP[71:70]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[69:68]
DSCP[67:66]
DSCP[65:64]
00
00
00
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Advanced Control Registers (Continued)
Register 153 (0x99): TOS Priority Control Register 9
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0x9C
IPv4 and IPv6 mapping _ for value 0x98
IPv4 and IPv6 mapping _ for value 0x94
IPv4 and IPv6 mapping _ for value 0x90
DSCP[79:78]
7 − 6
5 −4
DSCP[77:76]
DSCP[75:74]
DSCP[73:72]
00
00
3 − 2
1 − 0
00
Register 154 (0x9A): TOS Priority Control Register 10
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0xAC
IPv4 and IPv6 mapping _ for value 0xA8
IPv4 and IPv6 mapping _ for value 0xA4
IPv4 and IPv6 mapping _ for value 0xA0
DSCP[87:86]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[85:84]
DSCP[83:82]
DSCP[81:80]
00
00
00
Register 155 (0x9B): TOS Priority Control Register 11
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0xBC
IPv4 and IPv6 mapping _ for value 0xB8
IPv4 and IPv6 mapping _ for value 0xB4
IPv4 and IPv6 mapping _ for value 0xB0
DSCP[95:94]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[93:92]
DSCP[91:90]
DSCP[89:88]
00
00
00
Register 156 (0x9C): TOS Priority Control Register 12
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0xCC
IPv4 and IPv6 mapping _ for value 0xC8
IPv4 and IPv6 mapping _ for value 0xC4
IPv4 and IPv6 mapping _ for value 0xC0
DSCP[103:102]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[101:100]
DSCP[99:98]
DSCP[97:96]
00
00
00
Register 157 (0x9D): TOS Priority Control Register 13
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0xDC
IPv4 and IPv6 mapping _ for value 0xD8
IPv4 and IPv6 mapping _ for value 0xD4
IPv4 and IPv6 mapping _ for value 0xD0
DSCP[111:110]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[109:108]
DSCP[107:106]
DSCP[105:104]
00
00
00
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Advanced Control Registers (Continued)
Register 158 (0x9E): TOS Priority Control Register 14
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0xEC
IPv4 and IPv6 mapping _ for value 0xE8
IPv4 and IPv6 mapping _ for value 0xE4
IPv4 and IPv6 mapping _ for value 0xE0
DSCP[119:118]
7 − 6
5 −4
DSCP[117:116]
DSCP[115:114]
DSCP[113:112]
00
00
3 − 2
1 − 0
00
Register 159 (0x9F): TOS Priority Control Register 15
Address Name
Description
Mode
R/W
R/W
R/W
R/W
Default
00
IPv4 and IPv6 mapping _ for value 0xFC
IPv4 and IPv6 mapping _ for value 0xF8
IPv4 and IPv6 mapping _ for value 0xF4
IPv4 and IPv6 mapping _ for value 0xF0
DSCP[127:126]
7 − 6
5 − 4
3 − 2
1 − 0
DSCP[125:124]
DSCP[123:122]
DSCP[121:120]
00
00
00
Register 176 (0xB0): Port 1 Control 8
Register 192 (0xC0): Port 2 Control 8
Register 208 (0xD0): Port 3 Control 8
Register 224 (0xE0): Port 4 Control 8
Register 240 (0xF0): Port 5 Control 8
Address Name
Description
Mode
Default
Reserved
RO
0000
7 − 4
Register 176: insert source port 1 PVID for untagged
frame at egress port 5
Insert Source Port PVID for
Untagged Packet Destination
to Highest Egress Port
Register 192: insert source port 2 PVID for untagged
frame at egress port 5
Register 208: insert source port 3 PVID for untagged
frame at egress port 5
3
R/W
0
Register 224: insert source port 4 PVID for untagged
frame at egress port 5
Note: Enabled by the register
135 bit 2
Register 240: insert source port 5 PVID for untagged
frame at egress port 4
Register 176: insert source port 1 PVID for untagged
frame at egress port 4
Insert Source Port PVID for
Untagged Packet Destination
to Second Highest Egress Port
Register 192: insert source port 2 PVID for untagged
frame at egress port 4
Register 208: insert source port 3 PVID for untagged
frame at egress port 4
2
R/W
0
Register 224: insert source port 4 PVID for untagged
frame at egress port 3
Note: Enabled by the register
135 bit 2
Register 240: insert source port 5 PVID for untagged
frame at egress port 3
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Advanced Control Registers (Continued)
Register 176 (0xB0): Port 1 Control 8
Register 192 (0xC0): Port 2 Control 8
Register 208 (0xD0): Port 3 Control 8
Register 224 (0xE0): Port 4 Control 8
Register 240 (0xF0): Port 5 Control 8
Address Name
Description
Mode
Default
Register 176: insert source port 1 PVID for untagged
frame at egress port 3
Insert Source Port PVID for
Untagged Packet Destination
to Second Lowest Egress Port
Register 192: insert source port 2 PVID for untagged
frame at egress port 3
Register 208: insert source port 3 PVID for untagged
frame at egress port 2
1
R/W
0
Register 224: insert source port 4 PVID for untagged
frame at egress port 2
Note: Enabled by the register
135 bit 2
Register 240: insert source port 5 PVID for untagged
frame at egress port 2
Register 176: insert source port 1 PVID for untagged
frame at egress port 2
Insert Source Port PVID for
Untagged Packet Destination
to Lowest Egress Port
Register 192: insert source port 2 PVID for untagged
frame at egress port 1
Register 208: insert source port 3 PVID for untagged
frame at egress port 1
0
R/W
0
Register 224: insert source port 4 PVID for untagged
frame at egress port 1
Note: Enabled by the register
135 bit 2
Register 240: insert source port 5 PVID for untagged
frame at egress port 1
Register 177 (0xB1): Port 1 Control 9
Register 193 (0xC1): Port 2 Control 9
Register 209 (0xD1): Port 3 Control 9
Register 225 (0xE1): Port 4 Control 9
Register 241 (0xF1): Port 5 Control 9
Address Name
Description
Mode
Default
Reserved
RO
0000000
7 − 2
This bit in combination with Register16/32/48/64/80 bit
0 will select the split of 1/2/4 queues:
{Register177 bit 1, Register16 bit 0}=
11, reserved.
10, the port output queue is split into four priority
queues or if map 802.1p to priority 0-3 mode.
1
4 Queue Split Enable
R/W
R/W
0
01, the port output queue is split into two priority
queues or if map 802.1p to priority 0-3 mode.
00, single output queue on the port. There is no priority
differentiation even though packets are classified into
high and low priority
0 = disable tag drop
1 = enable tag drop
0
Enable Dropping Tag
0
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Advanced Control Registers (Continued)
Register 178 (0xB2): Port 1 Control 10
Register 194 (0xC2): Port 2 Control 10
Register 210 (0xD2): Port 3 Control 10
Register 226 (0xE2): Port 4 Control 10
Register 242 (0xF2): Port 5 Control 10
Address Name
Description
Mode
Default
0, strict priority, will transmit all the packets from this
priority queue 3 before transmit lower priority queue.
Enable Port Transmit Queue 3
Ratio
7
R/W
1
1, bit[6:0] reflect the packet number allow to transmit
from this priority queue 3 within a certain time
Port Transmit Queue 3
Ratio[6:0]
Packet number for Transmit Queue 3 for highest
priority packets in four queues mode
6 - 0
R/W
0001000
Register 179 (0xB3): Port 1 Control 11
Register 195 (0xC3): Port 2 Control 11
Register 211 (0xD3): Port 3 Control 11
Register 227 (0xE3): Port 4 Control 11
Register 243 (0xF3): Port 5 Control 11
Address Name
Description
Mode
Default
0, strict priority, will transmit all the packets from this
priority queue 2 before transmit lower priority queue.
Enable Port Transmit Queue 2
Ratio
7
R/W
1
1, bit[6:0] reflect the packet number allow to transmit
from this priority queue 1 within a certain time
Packet number for Transmit Queue 2 for high/low
priority packets in high/low priority packets in four
queues mode
Port Transmit Queue 2
Ratio[6:0]
R/W
0000100
6 − 0
Register 180 (0xB4): Port 1 Control 12
Register 196 (0xC4): Port 2 Control 12
Register 212 (0xD4): Port 3 Control 12
Register 228 (0xE4): Port 4 Control 12
Register 244 (0xF4): Port 5 Control 12
Address Name
Description
Mode
Default
0, strict priority, will transmit all the packets from this
priority queue 1 before transmit lower priority queue.
Enable Port Transmit Queue 1
Rate
7
R/W
1
1, bit[6:0] reflect the packet number allow to transmit
from this priority queue 1 within a certain time
Packet number for Transmit Queue 1 for low/high
priority packets in four queues mode and high priority
packets in two queues mode
Port Transmit Queue 1
Ratio[6:0]
R/W
0000010
6 − 0
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Advanced Control Registers (Continued)
Register 181 (0xB5): Port 1 Control 13
Register 197 (0xC5): Port 2 Control 13
Register 213 (0xD5): Port 3 Control 13
Register 229 (0xE5): Port 4 Control 13
Register 245 (0xF5): Port 5 Control 13
Address Name
Description
Mode
Default
0, strict priority, will transmit all the packets from this
priority queue 0 before transmit lower priority queue.
Enable Port Transmit Queue 0
Rate
7
R/W
1
1, bit[6:0] reflect the packet number allow to transmit
from this priority queue 0 within a certain time
packet number for Transmit Queue 0 for lowest priority
packets in four queues mode and low priority packets
in two queues mode
Port Transmit Queue 0
Ratio[6:0]
R/W
0000001
6 − 0
Register 182 (0xB6): Port 1 Rate Limit Control
Register 198 (0xC6): Port 2 Rate Limit Control
Register 214 (0xD6): Port 3 Rate Limit Control
Register 230 (0xE6): Port 4 Rate Limit Control
Register 246 (0xF6): Port 5 Rate Limit Control
Address Name
Description
Mode
Default
Reserved
RO
000
7 − 5
1 = Flow Control is asserted if the port’s receive rate is
exceeded
Ingress Rate Limit Flow
Control Enable
4
R/W
0
0 = Flow Control is not asserted if the port’s receive
rate is exceeded
Ingress Limit Mode
These bits determine what kinds of frames are limited
and counted against ingress rate limiting.
= 00, limit and count all frames
Limit Mode
R/W
00
3 − 2
= 01, limit and count Broadcast, Multicast, and flooded
unicast frames
= 10, limit and count Broadcast and Multicast frames
only
= 11, limit and count Broadcast frames only
Count IFG bytes
= 1, each frame’s minimum inter frame gap
1
0
Count IFG
Count Pre
R/W
R/W
0
0
(IFG) bytes (12 per frame) are included in Ingress and
Egress rate limiting calculations.
= 0, IFG bytes are not counted.
Count Preamble bytes
= 1, each frame’s preamble bytes (8 per frame) are
included in Ingress and Egress rate limiting
calculations.
= 0, preamble bytes are not counted.
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Advanced Control Registers (Continued)
Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1
Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1
Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1
Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1
Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1
Address Name
Description
Mode
Default
7
Reserved
RO
0
Ingress data rate limit for priority 0 frames
Port-Based Priority 0 Ingress
Limit
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
R/W
0000000
6 − 0
Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2
Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2
Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2
Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2
Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2
Address Name
Description
Mode
Default
7
Reserved
RO
0
Ingress data rate limit for priority 1 frames
Port-Based Priority 1 Ingress
Limit
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
R/W
0000000
6 − 0
Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3
Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3
Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3
Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3
Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3
Address Name
Description
Mode
Default
7
Reserved
RO
0
Ingress data rate limit for priority 2 frames
Port-Based Priority 2 Ingress
Limit
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
R/W
0000000
6 − 0
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Advanced Control Registers (Continued)
Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4
Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4
Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4
Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4
Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4
Address Name
Description
Mode
Default
7
Reserved
RO
0
Ingress data rate limit for priority 3 frames
Port-Based Priority 3 Ingress
Limit
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
R/W
0000000
6 − 0
Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1
Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1
Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1
Register 235 (0xEB): Port 4 Queue 0 Egress Limit Control 1
Register 251 (0xFB): Port 5 Queue 0 Egress Limit Control 1
Address Name
Description
Mode
Default
7
Reserved
RO
0
Egress data rate limit for priority 0 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
Port Queue 0 Egress Limit
R/W
0000000
6 − 0
In four queues mode, it is lowest priority.
In two queues mode, it is low priority.
Register 188 (0xBC): Port 1 Queue 1 Egress Limit Control 2
Register 204 (0xCC): Port 2 Queue 1 Egress Limit Control 2
Register 220 (0xDC): Port 3 Queue 1 Egress Limit Control 2
Register 236 (0xEC): Port 4 Queue 1 Egress Limit Control 2
Register 252 (0xFC): Port 5 Queue 1 Egress Limit Control 2
Address Name
Description
Mode
Default
7
Reserved
RO
0
Egress data rate limit for priority 1 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
Port Queue 1 Egress Limit
R/W
0000000
6 − 0
In four queues mode, it is low/high priority.
In two queues mode, it is high priority.
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Advanced Control Registers (Continued)
Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3
Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3
Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3
Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3
Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3
Address Name
Description
Mode
Default
7
Reserved
RO
0
Egress data rate limit for priority 2 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
Port Queue 2 Egress Limit
R/W
0000000
6 − 0
In four queues mode, it is high/low priority.
Register 190 (0xBE): Port 1 Queue 3 Egress Limit Control 4
Register 206 (0xCE): Port 2 Queue 3 Egress Limit Control 4
Register 222 (0xDE): Port 3 Queue 3 Egress Limit Control 4
Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4
Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4
Address Name
Description
Mode
Default
7
Reserved
RO
0
Egress data rate limit for priority 3 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
Port Queue 3 Egress Limit
R/W
0000000
6 − 0
In four queues mode, it is highest priority.
Note:
1. In the port priority 0-3 ingress rate limit mode, need to set all related ingress/egress ports to two queues or four queues mode.
2. In the port queue 0-3 egress rate limit mode, the highest priority get exact rate limit based on the rate select table, other priorities packets rate are
based on the ratio of the port register control 10/11/12/13 when use more than one egress queue per port.
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Data Rate Selection Table in 100BT
Table 11. Data Rate Selection in 100BT
Rate for 100BT Mode
Priority/Queue 0-3 Ingress/egress
1Mbps <= rate <= 99Mbps
Rate = 100 Mbps
Limit Control Register bit[6:0] = decimal rate(decimal integer 1-99)
0 or 100 (decimal), ‘0’ is default value
Decimal
Less than 1Mbps (see as below)
64 Kbps
128 Kbps
192 Kbps
256 Kbps
320 Kbps
384 Kbps
448 Kbps
512 Kbps
576 Kbps
640 Kbps
704 Kbps
768 Kbps
832 Kbps
896 Kbps
960 Kbps
7’d101
7’d102
7’d103
7’d104
7’d105
7’d106
7’d107
7’d108
7’d109
7’d110
7’d111
7’d112
7’d113
7’d114
7’d115
Data Rate Selection Table in 10BT
Table 12. Data Rate Selection in 10BT
Rate for 10BT mode
Priority/Queue 0-3 Ingress/egress
Limit Control Register bit[6:0]= decimal rate(decimal integer 1-9)
1Mbps <= rate <= 9Mbps
Rate = 10 Mbps
0 or 10 (decimal), ‘0’ is default value
Decimal
Less than 1Mbps (see as below)
64 Kbps
128 Kbps
192 Kbps
256 Kbps
320 Kbps
384 Kbps
448 Kbps
512 Kbps
576 Kbps
640 Kbps
704 Kbps
768 Kbps
832 Kbps
896 Kbps
960 Kbps
7’d101
7’d102
7’d103
7’d104
7’d105
7’d106
7’d107
7’d108
7’d109
7’d110
7’d111
7’d112
7’d113
7’d114
7’d115
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Advanced Control Registers (Continued)
Register 191(0xBF): Testing Register
Address Name
Description
Mode
Default
Reserved
N/A
RO
0x80
7 − 0
Register 207(0xCF): Reserved Control Register
Address Name
Description
Mode
Default
Reserved
N/A, don’t change
RO
0x15
7 − 0
Register 223(0xDF): Test Register 2
Address Name
Description
Mode
Default
Reserved
R/W
00000000
7 − 0
Register 239(0xEF): Test Register 3
Address Name
Description
Mode
RO
Default
7
6
Reserved
Reserved
Reserved
Reserved
N/A, don’t change
N/A, don’t change
N/A, don’t change
N/A, don’t change
0
0
RO
5
RO
1
RO
0x12
4 − 0
Register 255(0xFF): Testing Register4
Address Name
Description
Mode
Default
Reserved
N/A, don’t change
RO
0x00
7 − 0
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Static MAC Address Table
KSZ8895MLUB has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched
to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging,
migration, and learning purposes. The static DA look-up result will have precedence over the dynamic DA look-up result. If
there are DA matches in both tables, the result from the static table will be used. The static table can only be accessed
and controlled by an external SPI master (usually a processor). The entries in the static table will not be aged out by
KSZ8895MLUB. An external device does all addition, modification and deletion. Register bit assignments are different for
static MAC table reads and static MAC table write, as shown in Table 13 and Table 14.
Table 13. Format of Static MAC Table for Read (32 Entries)
Address Name
Description
Mode
Default
Filter VLAN ID, representing one of the 128 active
VLANs
FID
RO
0000000
63 − 57
1, use (FID+MAC) to look-up in static table.
0, use MAC only to look-up in static table.
56
55
Use FID
RO
RO
0
Reserved
Reserved.
N/A
1, override spanning tree “transmit enable = 0” or
“receive enable = 0* setting. This bit is used for
spanning tree implementation.
54
53
Override
Valid
RO
RO
0
0
0, no override.
1, this entry is valid, the look-up result will be used.
0, this entry is not valid.
The 5 bits control the forward ports, example:
00001, forward to port 1
00010, forward to port 2
Forwarding Ports
MAC Address
…..
RO
RO
00000
0x0
52 − 48
10000, forward to port 5
00110, forward to port 2 and port 3
11111, broadcasting (excluding the ingress port)
48-bit MAC address.
47 − 0
Examples:
1. Static Address Table Read (read the 2nd entry)
Write to Register 110 with 0x10 (read static table selected)
Write to Register 111 with 0x1 (trigger the read operation)
Then
Read Register 113 (63 − 56)
Read Register 114 (55 − 48)
Read Register 115 (47 − 40)
Read Register 116 (39 − 32)
Read Register 117 (31− 24)
Read Register 118 (23 − 16)
Read Register 119 (15− 8)
Read Register 120 (7 − 0)
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Table 14. Format of Static MAC Table for Writes (32 Entries)
Address Name
Description
Mode
Default
Filter VLAN ID, representing one of the 128 active
VLANs.
FID
W
0000000
62 − 56
1, use (FID+MAC) to look-up in static table.
0, use MAC only to look-up in static table.
55
Use FID
W
W
W
0
0
0
1, override spanning tree “transmit enable = 0” or
“receive enable = 0” setting. This bit is used for
spanning tree implementation.
54
53
Override
Valid
0, no override.
1, this entry is valid, the look-up result will be used.
0, this entry is not valid.
The 5 bits control the forward ports, example:
00001, forward to port 1
00010, forward to port 2
Forwarding Ports
MAC Address
.....
W
W
00000
0x0
52 − 48
10000, forward to port 5
00110, forward to port 2 and port 3
11111, broadcasting (excluding the ingress port)
48-bit MAC address.
47 − 0
Examples:
1. Static Address Table Write (write the 8th entry)
Write to Register 110 with 0x10 (read static table selected)
Write Register 113 (62 − 56)
Write Register 114 (55 − 48)
Write Register 115 (47 − 40)
Write Register 116 (39 − 32)
Write Register 117 (31 − 24)
Write Register 118 (23 − 16)
Write Register 119 (15 − 8)
Write Register 120 (7 − 0)
Write to Register 110 with 0x00 (write static table selected)
Write to Register 111 with 0x7 (trigger the write operation)
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VLAN Table
The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this table is used
to retrieve VLAN information that is associated with the ingress packet. There are three fields for FID (filter ID), Valid, and
VLAN membership in the VLAN table. The three fields must be initialized before the table is used. There is no VID field
because 4096 VIDs are used as a dedicated memory address index into a 1024x52-bit memory space. Each entry has
four VLANs. Each VLAN has 13 bits. Four VLANs need 52 bits. There are a total of 1024 entries to support a total of 4096
VLAN IDs by using dedicated memory address and data bits. Refer to Tables below for details. FID has 7-bits to support
128 active VLANs.
Table 15. Format of Static VLAN Table (Support Max 4096 VLAN ID Entries and 128 Active VLANs)
Initial Value
Address
Name
Description
Mode
suggestion
1, the entry is valid.
0, entry is invalid.
12
Valid
R/W
0
Specify which ports are members of the VLAN.
If a DA look-up fails (no match in both static and
dynamic tables), the packet associated with this VLAN
will be forwarded to ports specified in this field.
Membership
FID
R/W
R/W
11111
11 − 7
6 − 0
E.g., 11001 means port 5, port 4 and port 1.
Filter ID. KSZ8895MLUB supports 128 active VLANs
represented by these seven bit fields. FID is the
mapped ID. If 802.1q VLAN is enabled, the look-up in
MAC table will be based on FID+DA and FID+SA.
0
If 802.1q VLAN mode is enabled, KSZ8895MLUB assigns a VID to every ingress packet when the packet is untagged or
tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with
non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up based on VID number
with its dedicated memory address and data bits. If the entry is not valid in the VLAN table, the packet is dropped and no
address learning occurs. If the entry is valid, the FID is retrieved. The FID+DA and FID+SA lookups in MAC tables are
performed. The FID+DA look-up determines the forwarding ports. If FID+DA fails for look-up in the MAC table, the packet
is broadcast to all the members or specified members (excluding the ingress port) based on the VLAN table. If FID+SA
fails, the FID+SA is learned. To communicate between different active VLANs, set the same FID; otherwise set a different
FID.
The VLAN table configuration is organized as 1024 VLAN sets, each VLAN set consists of four VLAN entries, to support
up to 4096 VLAN entries. Each VLAN set has 52 bits and should be read or written at the same time specified by the
indirect address.
The VLAN entries in the VLAN set is mapped to indirect data registers as follow:
Entry0[12:0] maps to the VLAN set bits[12 − 0] {register119[4:0], register120[7:0]}
Entry1[12:0] maps to the VLAN set bits[25 − 13]{register117[1:0], register118[7:0], register119[7:5]}
Entry2[12:0] maps to the VLAN set bits[38 − 26]{register116[6:0], register117[7:2]}
Entry3[12:0] maps to the VLAN set bits[51 − 39]{register114[3:0], register115[7:0], register116[7]}
In order to read one VLAN entry, the VLAN set is read first and the specific VLAN entry information can be extracted. To
update any VLAN entry, the VLAN set is read first then only the desired VLAN entry is updated and the whole VLAN set is
written back. Due to FID in VLAN table is 7-bit, so the VLAN table supports unique 128 flow VLAN groups. Each VLAN set
address is 10 bits long (Maximum is 1024) in the indirect address register 110 and 111, the bit [9 − 8] of VLAN set
address is at bit [1 − 0] of register 110, and the bit [7 − 0] of VLAN set address is at bit [7-0] of register 111. Each Write
and Read can access to four consecutive VLAN entries.
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Examples:
1. VLAN Table Read (read the VID=2 entry)
Write the indirect control and address registers first
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x0 (trigger the read operation for VID=0, 1, 2, 3 entries)
Then read the indirect data registers bits [38-26] for VID=2 entry
Read Register 116 (0x74), (register 116 [6:0] are bits 12 − 6 of VLAN VID=2 entry)
Read Register 117 (0x75), (register 117 [7:2] are bits 5 − 0 of VLAN VID=2 entry)
2. VLAN Table Write (write the VID=10 entry)
Read the VLAN set that contains VID=8, 9, 10, 11.
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the read operation and VID=8, 9, 10, 11 indirect address)
Read the VLAN set first by the indirect data registers 114, 115, 116, 117, 118, 119, 120.
3. Modify the indirect data registers bits [38 − 26] by the register 116 bit [6-0] and register 117 bit [7 − 2] as follows:
Write to Register 116 (0x74), (register116 [6:0] are bits 12 − 6 of VLAN VID=10 entry)
Write to Register 117 (0x75), (register117 [7:2] are bits 5 − 0 of VLAN VID=10 entry)
4. Then write the indirect control and address registers
Write to Register 110 (0x6E) with 0x04 (write VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the write operation and VID=8, 9, 10, 11 indirect address)
Table 16 shows the relationship of the indirect address/data registers and VLAN ID.
Table 16. VLAN ID and Indirect Registers
Indirect Address
High/Low Bit[9-0]
Indirect Data
Registers Bits for
Each VLAN Entry
VID
VID bit[12-2] in VLAN Tag
VID bit[1-0] in VLAN Tag
Numbers
for VLAN Sets
0
0
0
0
1
2
3
0
1
2
3
0
1
2
3
:
Bits[12 − 0]
Bits[25 − 13]
Bits[38 − 26]
Bits[51 − 39]
Bits[12 − 0]
Bits[25 − 13]
Bits[38 − 26]
Bits[51 − 39]
Bits[12 − 0]
Bits[25 − 13]
Bits[38 − 26]
Bits[51 − 39]
:
0
1
0
0
2
0
0
3
0
1
4
1
1
5
1
1
6
1
1
7
1
2
8
9
2
2
2
2
10
2
2
:
11
2
:
:
:
:
:
:
:
:
:
:
:
:
1023
1023
1023
1023
4092
4093
4094
4095
1023
1023
1023
1023
0
1
2
3
Bits[12 − 0]
Bits[25 − 13]
Bits[38 − 26]
Bits[51 − 39]
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Dynamic MAC Address Table
Table 17 is read only. The contents are maintained by the KSZ8895MLUB only.
Table 17. Format of Dynamic MAC Address Table (1K Entries)
Address Name
Description
Mode
Default
1, there is no valid entry in the table.
0, there are valid entries in the table.
Indicates how many valid entries in the table.
0x3ff means 1K entries
71
MAC Empty
RO
1
No of Valid Entries
Time Stamp
0x1 and bit 71 = 0: means 2 entries
0x0 and bit 71 = 0: means 1 entry
0x0 and bit 71 = 1: means 0 entry
RO
RO
0
70 − 61
60 − 59
2-bit counters for internal aging
The source port where FID+MAC is learned.
000 Port 1
001 Port 2
Source Port
RO
0x0
58 − 56
010 Port 3
011 Port 4
100 Port 5
1, The entry is not ready, retry until this bit is set to 0.
0, The entry is ready.
55
Data Ready
RO
FID
Filter ID.
RO
RO
0x0
0x0
54 − 48
47 − 0
MAC Address
48-bit MAC address.
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Dynamic MAC Address Table Read/Write Examples:
1. Dynamic MAC Address Table Read (read the 1st entry), and retrieve the MAC table size:
Write to Register 110 with 0x18 (read dynamic table selected)
Write to Register 111 with 0x0 (trigger the read operation) and then
Read Register 112 (71 − 64)
Read Register 113 (63 − 56); // the above two registers show # of entries
Read Register 114 (55 − 48) // if bit 55 is 1, restart (reread) from this register
Read Register 115 (47 − 40)
Read Register 116 (39 − 32)
Read Register 117 (31 − 24)
Read Register 118 (23 − 16)
Read Register 119 (15 − 8)
Read Register 120 (7 − 0)
2. Dynamic MAC Address Table Read (read the 257th entry), without retrieving # of entries information:
Write to Register 110 with 0x19 (read dynamic table selected)
Write to Register 111 with 0x1 (trigger the read operation) and then
Read Register 112 (71 − 64)
Read Register 113 (63 − 56)
Read Register 114 (55 − 48) // if bit 55 is 1, restart (reread) from this register
Read Register 115 (47 − 40)
Read Register 116 (39 − 32)
Read Register 117 (31 − 24)
Read Register 118 (23 − 16)
Read Register 119 (15 − 8)
Read Register 120 (7 − 0)
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Management Information Base (MIB) Counters
The Management Information Base (MIB) counters are provided on per port basis. These counters are read using indirect
memory access as noted in the following tables:
Port 1 MIB Counter Indirect Memory Offsets
Offset Counter Name
Description
0x0
0x1
0x2
0x3
0x4
RxLoPriorityByte
RxHiPriorityByte
RxUndersizePkt
RxFragments
Rx lo-priority (default) octet count including bad packets.
Rx hi-priority octet count including bad packets.
Rx undersize packets w/good CRC.
Rx fragment packets w/bad CRC, symbol errors or alignment errors.
Rx oversize packets w/good CRC (max: 1536 or 1522 bytes).
RxOversize
Rx packets longer than 1522B w/either CRC errors, alignment errors, or symbol errors (depends
on max packet size setting) or Rx packets longer than 1916B only.
0x5
0x6
0x7
RxJabbers
RxSymbolError
RxCRCerror
Rx packets w/ invalid data symbol and legal preamble, packet size.
Rx packets within (64,1522) bytes w/an integral number of bytes and a bad CRC (upper limit
depends on max packet size setting).
Rx packets within (64,1522) bytes w/a non-integral number of bytes and a bad CRC (upper limit
depends on max packet size setting).
0x8
0x9
0xA
0xB
0xC
RxAlignmentError
RxControl8808Pkts
RxPausePkts
The number of MAC control frames received by a port with 88-08h in EtherType field.
The number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (88-
08h), DA, control opcode (00 − 01), data length (64B min), and a valid CRC.
RxBroadcast
Rx good broadcast packets (not including errored broadcast packets or valid multicast packets).
Rx good multicast packets (not including MAC control frames, errored multicast packets or valid
broadcast packets).
RxMulticast
0xD
0xE
RxUnicast
Rx good unicast packets.
Rx64Octets
Total Rx packets (bad packets included) that were 64 octets in length.
Total Rx packets (bad packets included) that are between 65 and 127 octets in length.
Total Rx packets (bad packets included) that are between 128 and 255 octets in length.
Total Rx packets (bad packets included) that are between 256 and 511 octets in length.
Total Rx packets (bad packets included) that are between 512 and 1023 octets in length.
0xF
Rx65to127Octets
Rx128to255Octets
Rx256to511Octets
Rx512to1023Octets
0x10
0x11
0x12
Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper
limit depends on max packet size setting).
0x13
Rx1024to1522Octets
0x14
0x15
0x16
0x17
0x18
TxLoPriorityByte
TxHiPriorityByte
TxLateCollision
TxPausePkts
Tx lo-priority good octet count, including PAUSE packets.
Tx hi-priority good octet count, including PAUSE packets.
The number of times a collision is detected later than 512 bit-times into the Tx of a packet.
The number of PAUSE frames transmitted by a port.
TxBroadcastPkts
Tx good broadcast packets (not including errored broadcast or valid multicast packets).
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Port 1 MIB Counter Indirect Memory Offsets (Continued)
Offset
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Counter Name
TxMulticastPkts
TxUnicastPkts
Description
Tx good multicast packets (not including errored multicast packets or valid broadcast packets).
Tx good unicast packets.
TxDeferred
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium.
Tx total collision, half-duplex only.
TxTotalCollision
TxExcessiveCollision
TxSingleCollision
TxMultipleCollision
A count of frames for which Tx fails due to excessive collisions.
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision.
Successfully Tx frames on a port for which Tx is inhibited by more than one collision.
Format of “Per port” MIB Counter
For Port 2, the Base is 0x20, Same Offset Definition (0x20-0x3f)
For Port 3, the Base is 0x40, Same Offset Definition (0x40-0x5f)
For Port 4, the Base is 0x60, Same Offset Definition (0x60-0x7f)
For Port 5, the Base is 0x80, Same Offset Definition (0x80-0x9f)
Address Name
Description
Mode
Default
Format of Per Port MIB Counters (16 entries)
1, Counter overflow.
31
Overflow
RO
0
0, No Counter overflow.
1, Counter value is valid.
0, Counter value is not valid.
30
Count Valid
RO
RO
0
0
Counter Values
Counter value.
29 − 0
Table 18. All Port Dropped Packet MIB Counters
Offset
0x100
0x101
0x102
0x103
0x104
0x105
0x106
0x107
0x108
0x109
Counter Name
Description
Port1 Tx Drop Packets
Port2 Tx Drop Packets
Port3 Tx Drop Packets
Port4 Tx Drop Packets
Port5 Tx Drop Packets
Port1 Rx Drop Packets
Port2 Rx Drop Packets
Port3 Rx Drop Packets
Port4 Rx Drop Packets
Port5 Rx Drop Packets
Tx packets dropped due to lack of resources.
Tx packets dropped due to lack of resources.
Tx packets dropped due to lack of resources.
Tx packets dropped due to lack of resources.
Tx packets dropped due to lack of resources.
Rx packets dropped due to lack of resources.
Rx packets dropped due to lack of resources.
Rx packets dropped due to lack of resources.
Rx packets dropped due to lack of resources.
Rx packets dropped due to lack of resources.
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Table 19. Format of All Dropped Packet MIB Counters
Address Name
Description
Mode
N/A
Default
N/A
Reserved
Counter Values
Reserved.
30 − 16
15 − 0
Counter value.
RO
0
Note that all port dropped packet MIB counters do not indicate overflow or validity; therefore the application must keep
track of overflow and valid conditions.
The KSZ8895MLUB provides total 34 MIB counter per port. These counter are used to monitor the port detail activity for
network management and maintenance. These MIB counters are read using indirect memory access as as noted in the
following examples:
Programming Examples:
1. MIB counter read (read port 1 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counters selected)
Write to Register 111 with 0xe (trigger the read operation)
Then
Read Register 117 (counter value 31 − 24)
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23 − 16)
Read Register 119 (counter value 15 − 8)
Read Register 120 (counter value 7 − 0)
2. MIB counter read (read port 2 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counter selected)
Write to Register 111 with 0x2e (trigger the read operation)
Then
Read Register 117 (counter value 31 − 24)
//If bit 31 = 1, there was a counter overflow
//If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23 − 16)
Read Register 119 (counter value 15 − 8)
Read Register 120 (counter value 7 − 0)
3. MIB counter read (read port 1 tx drop packets)
Write to Register 110 with 0x1d
Write to Register 111 with 0x00
Then
Read Register 119 (counter value 15 − 8)
Read Register 120 (counter value 7 − 0)
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Note that to read out all the counters, the best performance over the SPI bus is (160+3) × 8 × 80 = 104us, where there are
160 registers, 3 overhead, 8 clocks per access, at 12.5MHz. In the heaviest condition, the byte counter will overflow in 2
minutes. It is recommended that the software read all the counters at least every 30 seconds. The per port MIB counters
are designed as “read clear.” A per port MIB counter will be cleared after it is accessed. All port dropped packet MIB
counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on
these counters.
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MIIM Registers
All the registers defined in this section can be also accessed via the SPI interface. Note that different mapping
mechanisms are used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for port 2,
“0x3” for port 3 and “0x4” for port 4. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh).
Register 0h: MII Control
Address
Name
Description
Mode
Default
1, PHY soft reset.
R/W
(SC)
15
Soft Reset
0
0, Normal operation.
1 = Perform MAC loopback, loop back path as follows:
Assume the loop-back is at port 1 MAC, port 2 is the
monitor port.
Port 1 MAC Loopback (port 1 reg. 0, bit 14 = ‘1’)
Start: RXP2/RXM2 (port 2). Can also start from
port 3, 4, 5
14
Loop Back
R/W
0
Loopback: MAC/PHY interface of port 1’s MAC
End: TXP2/TXM2 (port 2). Can also end at port 3,
4, 5 respectively
Setting address ox3,4,5 reg. 0, bit 14 = ‘1’ will
perform MAC loopback on port 3, 4, 5 respectively.
0 = Normal Operation.
1, 100Mbps.
13
12
11
10
9
Force 100
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
0
0
0, 10Mbps.
1, Auto-negotiation enabled.
0, Auto-negotiation disabled.
1, Power down.
AN Enable
Power Down
PHY Isolate
Restart AN
0, Normal operation.
1, Electrical PHY isolation of PHY from Tx+/Tx-.
0, Normal operation.
1, Restart Auto-negotiation.
0, Normal operation.
1, Full duplex.
8
Force Full Duplex
0, Half duplex.
7
6
Collision Test
Reserved
Not supported.
RO
RO
0
0
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
1, Force MDI.
5
4
3
2
1
0
Hp_mdix
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
Force MDI
0, Normal operation.
1, Disable auto MDI/MDI-X.
0, Normal operation.
Disable Auto MDI/MDI-X
Disable far End fault
Disable Transmit
Disable LED
1, Disable far end fault detection.
0, Normal operation.
1, Disable transmit.
0, Normal operation.
1, Disable LED.
0, Normal operation.
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MIIM Registers (Continued)
Register 1h: MII Status
Address
Name
Description
Mode
Default
15
T4 Capable
0, Not 100 BASET4 capable.
RO
0
1, 100BASE-TX full-duplex capable.
0, Not capable of 100BASE-TX full-duplex.
1, 100BASE-TX half-duplex capable.
0, Not 100BASE-TX half-duplex capable.
1, 10BASE-T full-duplex capable.
14
13
12
11
100 Full Capable
100 Half Capable
10 Full Capable
10 Half Capable
RO
RO
RO
RO
1
1
1
1
0, Not 10BASE-T full-duplex capable.
1, 10BASE-T half-duplex capable.
0, 10BASE-T half-duplex capable.
Reserved
RO
RO
0
0
10 − 7
6
Preamble Suppressed
Not supported.
1, Auto-negotiation complete.
0, Auto-negotiation not completed.
1, far end fault detected.
0, No far end fault detected.
1, Auto-negotiation capable.
0, Not auto-negotiation capable.
1, Link is up.
5
4
3
2
AN Complete
far End fault
AN Capable
Link Status
RO
RO
RO
RO
0
0
1
0
0, Link is down.
1
0
Jabber Test
Not supported.
RO
RO
0
0
Extended Capable
0, Not extended register capable.
Register 2h: PHYID HIGH
Address
Name
Description
Mode
Default
Phyid High
High order PHYID bits.
RO
0x0022
15 − 0
Register 3h: PHYID LOW
Address
Name
Description
Mode
Default
Phyid Low
Low order PHYID bits.
RO
0x1450
15 − 0
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MIIM Registers (Continued)
Register 4h: Advertisement Ability
Address
Name
Description
Mode
RO
Default
15
Next Page
Reserved
Remote fault
Reserved
Not supported.
0
0
0
0
14
RO
13
Not supported.
RO
RO
12 − 11
1, Advertise pause ability.
10
9
Pause
R/W
R/W
R/W
1
0
1
0, Do not advertise pause ability.
Reserved
Adv 100 Full
1, Advertise 100 full-duplex ability.
0, Do not advertise 100 full-duplex ability.
1, Advertise 100 half-duplex ability.
0, Do not advertise 100 half-duplex ability.
1, Advertise 10 full-duplex ability.
8
7
6
Adv 100 Half
Adv 10 Full
R/W
R/W
1
1
0, Do not advertise 10 full-duplex ability.
1, Advertise 10 half-duplex ability.
5
Adv 10 Half
R/W
RO
1
0, Do not advertise 10 half-duplex ability.
Selector Field
802.3
00001
4 − 0
Register 5h: Link Partner Ability
Address
Name
Description
Mode
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
15
Next Page
LP ACK
Not supported.
Not supported.
Not supported.
0
14
0
13
Remote fault
Reserved
Pause
0
0
12 − 11
10
9
Link partner pause capability.
0
Reserved
Adv 100 Full
Adv 100 Half
Adv 10 Full
Adv 10 Half
Reserved
0
8
Link partner 100 full capability.
Link partner 100 half capability.
Link partner 10 full capability.
Link partner 10 half capability.
0
7
0
6
0
0
5
4-0
00001
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MIIM Registers (Continued)
Register 1dh: LinkMD Control/Status
Address
Name
Description
Mode
Default
1 = Enable cable diagnostic. AfterVCT test has
completed, this bit will be self-cleared.
0 = Indicate cable diagnostic test (if enabled) has
completed and the status information is valid for read.
00 = Normal condition
R/W
(SC)
15
Vct_enable
0
01 = Open condition detected in cable
10 = Short condition detected in cable
11 = Cable diagnostic test has failed
14-13
Vct_result
RO
00
12
Vct 10M Short
Reserved
1 = Less than 10 meter short
RO
RO
0
0
11-9
Distance to the fault.
It’s approximately 0.4m*vct_fault_count [8:0]
8-0
Vct_fault_count
RO
000000000
Register 1fh: PHY Special Control/Status
Address
Name
Description
Mode
Default
Reserved
RO
0000000000
15 − 11
Indicate the current state of port operation mode:
[000] = reserved
[001] = still in auto-negotiation
[010] = 10BASE-T half duplex
[011] = 100BASE-TX half duplex
[100] = reserved
Port Operation Mode
Indication
RO
000
10 − 8
[101] = 10BASE-T full duplex
[110] = 100BASE-TX full duplex
[111] = PHY/MII isolate
N/A, don’t change
Reserved
Polrvs
R/W
RO
xx
0
7 − 6
1 = Polarity is reversed
0 = Polarity is not reversed
1 = MDI
5
4
3
2
MDI-X status
Force_lnk
Pwrsave
RO
0
0 = MDI-X
1 = Force link pass
0 = Normal operation
1 = Enable power save
0 = Disable power save
R/W
R/W
0
0
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Register 1fh: PHY Special Control/Status (Continued)
1 = Perform Remote loopback, loop back path as
follows:
Port 1 (PHY ID address 0x1 reg. 1f, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
1
0
Remote Loopback
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
R/W
RO
0
0
Setting PHY ID address 0x2,3,4,5 reg. 1fh, bit 1 = ‘1’
will perform remote loopback on port 2, 3, 4, 5.
0 = Normal Operation.
Reserved
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Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage
Supply Voltage
(VDDAR, VDDAP, VDDC).........................–0.5V to +2.4V
(VDDAT, VDDIO) ...................................–0.5V to +4.0V
Input Voltage ..........................................–0.5V to +4.0V
Output Voltage .......................................–0.5V to +4.0V
Lead Temperature (soldering, 10 sec.)............... 260°C
Storage Temperature (TS).................. –55°C to +150°C
HBM ESD Rating ....................................................5KV
(VDDAR, VDDAP, VDDC)........................+1.14V to +1.26V
(VDDAT) ...............................……..+3.135V to +3.465V
(VDDIO @ 3.3V)................................. +3.135V to +3.465V
(VDDIO @ 2.5V)................................. +2.375V to +2.625V
(VDDIO @ 1.8V)................................. +1.710V to +1.890V
Ambient Temperature (TA)
Industrial/Automotive ...............................–40°C to +85°C
Package Thermal Resistance(3)
LQFP (θJA) No Air Flow .............................48.22°C/W
LQFP (θJC) No Air Flow..............................13.95°C/W
Electrical Characteristics(4, 5)
VIN = 1.2V/3.3V (typ.); TA = 25°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
100BASE-TX Operation—All Ports 100% Utilization
IDX
100BASE-TX (Transmitter) 3.3V Analog
100BASE-TX 1.2V Analog
VDDAT
VDDAR
VDDC
86
22
mA
mA
mA
mA
mA
IDda
IDDc
IDDIO
IDDIO
100BASE-TX 1.2V Digital
42
100BASE-TX (Digital IO) Standalone Switch
3.3V Digital IO Port 5 SW5-MII MAC/PHY
VDDIO
VDDIO
2
22/38
10BASE-T Operation —All Ports 100% Utilization
IDX
10BASE-T (Transmitter) 3.3V Analog
10BASE-T 1.2V Analog
VDDAT
VDDAR
VDDC
107
8.6
44
mA
mA
mA
mA
mA
IDda
IDDc
IDDIO
IDDIO
10BASE-T 1.2V Digital
10BASE-TX (Digital IO) Standalone Switch
3.3V Digital IO Port 5 SW5-MII MAC/PHY
VDDIO
VDDIO
2
5/18
Auto-Negotiation Mode
IDX 10BASE-T (Transmitter) 3.3V Analog
IDda
VDDAT
VDDAR
VDDC
55
22
46
1.5
mA
mA
mA
mA
10BASE-T 1.2V Analog
IEDM
10BASE-T 1.2V Digital
IDDIO
Notes:
10BASE-T (Digital IO) Standalone Switch
VDDIO
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (ground
or VDD).
3. No heat spreader in package. The thermal junction to ambient (θJA) and the thermal junction to case (θJC) are under air velocity 0m/s.
4. Specification for packaged product only. There is no an additional transformer consumption due to use on chip termination technology with internal
biasing for 10Bese-T and 100Base-TX.
5. Measurements were taken with operating ratings.
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Electrical Characteristics(4, 5) (Continued)
VIN = 1.2V/3.3V (typ.); TA = 25°C
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Power Management Mode (Standalone)
IPSM1
IPSM2
ISPDM1
ISPDM2
IEDM1
IEDM2
Power-Saving Mode 3.3V
VDDAT + VDDIO
VDDAR + VDDC
VDDAT + VDDIO
VDDAR + VDDC
VDDAT + VDDIO
VDDAR + VDDC
35
55
2
mA
mA
mA
mA
mA
mA
Power-Saving Mode 1.2V
Soft Power-Down Mode 3.3V
Soft Power-Down Mode 1.2V
Energy-Detect Mode + PLL OFF 3.3V
Energy-Detect Mode + PLL OFF 1.2V
1.8
5.5
1.5
CMOS Inputs
2.0/1.8
/1.3
V
VIH
Input High Voltage (VDDIO=3.3/2.5/1.8V)
0.8/0.7
/0.5
V
VIL
IIN
Input Low Voltage (VDDIO=3.3/2.5/1.8V)
Input Current (Excluding Pull-Up/Pull-Down)
–10
10
µA
VIN = GND ~ VDDIO
IOH = –8mA
CMOS Outputs
2.4/2.0
/1.5
VOH
Output High Voltage (VDDIO=3.3/2.5/1.8V)
V
0.4/0.4
/0.3
VOL
IOZ
Output Low Voltage (VDDIO=3.3/2.5/1.8V)
Output Tri-State Leakage
IOL = 8mA
V
VIN = GND ~ VDDIO
10
µA
100BASE-TX Transmit (measured differentially after 1:1 transformer)
100Ω termination on the
differential output
VO
Peak Differential Output Voltage
Output Voltage Imbalance
0.95
1.05
2
V
100Ω termination on the
differential output
VIMB
%
Rise/fall Time
3
0
5
0.5
±0.5
5
ns
ns
ns
%
tr tt
Rise/fall Time Imbalance
Duty Cycle Distortion
Overshoot
Output Jitters
Peak-to-peak
0
0.75
400
1.4
ns
10BASE-T Receive
VSQ Squelch Threshold
5MHz square wave
300
585
mV
10BASE-T Transmit (measured differentially after 1:1 transformer) VDDAT = 3.3V
100Ω termination on the
differential output
VP
Peak Differential Output Voltage
2.2
2.5
2.8
V
Output Jitters
Peak-to-peak
1.4
28
3.5
30
ns
ns
Rise/fall Times
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Timing Diagrams
EEPROM Timing
Figure 13. EEPROM Interface Input Receive Timing Diagram
Figure 14. EEPROM Interface Output Transmit Timing Diagram
Table 20. EEPROM Timing Parameters
Symbol
tCYC1
tS1
Parameter
Clock Cycle
Set-Up Time
Hold Time
Min.
Typ.
Max.
Units
ns
16384
20
20
ns
tH1
ns
tOV1
Output Valid
4096
4112
4128
ns
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Timing Diagrams (Continued)
SNI Timing
Figure 15. SNI Input Timing
Figure 16. SNI Output Timing
Table 21. SNI Timing Parameters
Symbol
tCYC2
tS2
Parameter
Clock Cycle
Set-Up Time
Hold Time
Min.
Typ.
Max.
Units
ns
100
10
0
ns
tH2
ns
tO2
Output Valid
0
3
6
ns
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Timing Diagrams (Continued)
MII Timing
Figure 17. MAC Mode MII Timing – Data Received from MII
Figure 18. MAC Mode MII Timing – Data Transmitted from MII
Table 22. MAC Mode MII Timing Parameters
10Base-T/100Base-TX
Symbol
Parameter
Min.
Typ.
Max.
Units
ns
tCYC3
tS3
Clock Cycle
Set-Up Time
Hold Time
400/40
10
5
ns
tH3
ns
tOV3
Output Valid
3
9
25
ns
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Timing Diagrams (Continued)
MII Timing (Continued)
Figure 19. PHY Mode MII Timing – Data Received from MII
Figure 20. PHY Mode MII Timing – Data Transmitted from MII
Table 23. PHY Mode MII Timing Parameters
10BaseT/100BaseT
Symbol
Parameter
Min.
Typ.
Max.
Units
ns
tCYC4
tS4
Clock Cycle
Set-Up Time
Hold Time
400/40
10
0
ns
tH4
ns
tOV4
Output Valid
16
20
25
ns
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Timing Diagrams (Continued)
SPI Timing
Figure 21. SPI Input Timing
Table 24. SPI Input Timing Parameters
Symbol
Parameter
Min.
Typ.
Max.
Units
MHz
ns
fC
Clock Frequency
25
tCHSL
tSLCH
tCHSH
tSHCH
tSHSL
tDVCH
tCHDX
tCLCH
tCHCL
tDLDH
tDHDL
SPIS_N Inactive Hold Time
SPIS_N Active Set-Up Time
SPIS_N Active Hold Time
SPIS_N Inactive Set-Up Time
SPIS_N Deselect Time
Data Input Set-Up Time
Data Input Hold Time
Clock Rise Time
10
10
10
10
20
5
ns
ns
ns
ns
ns
5
ns
1
1
1
1
µs
Clock fall Time
µs
Data Input Rise Time
Data Input fall Time
µs
µs
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Timing Diagrams (Continued)
SPI Timing (Continued)
Figure 22. SPI Output Timing
Table 25. SPI Output Timing Parameters
Symbol
Parameter
Min.
Typ.
Max.
25
Units
MHz
ns
fC
Clock Frequency
SPIQ Hold Time
Clock Low to SPIQ Valid
Clock High Time
Clock Low Time
SPIQ Rise Time
SPIQ Fall Time
tCLQX
tCLQV
tCH
0
0
15
ns
18
18
ns
tCL
ns
tQLQH
tQHQL
tSHQZ
50
50
15
ns
ns
SPIQ Disable Time
ns
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Timing Diagrams (Continued)
Auto-Negotiation Timing
Figure 23. Auto-Negotiation Timing
Table 26. Auto-Negotiation Timing Parameters
Symbols
Parameters
Min.
Typ.
16
Max.
Units
ms
ms
ns
tBTB
FLP Burst to FLP Burst
FLP Burst Width
8
24
tFLPW
tPW
tCTD
tCTC
2
Clock/Data Pulse Width
Clock Pulse to Data Pulse
Clock Pulse to Clock Pulse
Number of Clock/Data Pulse per Burst
100
64
55.5
111
17
69.5
139
33
µs
128
µs
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Timing Diagrams (Continued)
Reset Timing
Figure 24. Reset Timing
Table 27. Reset Timing Parameters
Symbol Parameter
Min.
Typ.
Max.
Units
tSR
tCS
tCH
tRC
tvr
Stable Supply Voltages to Reset High
Configuration Set-Up Time
Configuration Hold Time
Reset to Strap-In Pin Output
3.3V rise time
10
50
ms
ns
ns
ns
µs
50
50
100
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Reset Circuit Diagram
Micrel recommends the following discrete reset circuit as shown in Figure 25 when powering up the KS8895MLUBB
device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we
recommend the reset circuit as shown in Figure 26.
Figure 25. Recommended Reset Circuit
Figure 26. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out
RST_OUT_n from CPU/FPGA provides the warm reset after power-up.
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Isolation Transformer Selection
One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-
mode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/TX
at chip side. Table 28 gives recommended transformer characteristics.
Table 28. Transformer Selection Criteria
Characteristics Name
Value
Test Condition
Turns Ratio
1 CT : 1 CT
350µH
Open-Circuit Inductance (min.)
Insertion Loss (max.)
HIPOT (min.)
100mV, 100kHz, 8mA
0.1MHz to 100MHz
1.1dB
1500Vrms
Note:
1. The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can
be compensated by increasing the line drive current by means of reducing the ISET resistor value.
2. The center taps of RX and TX should be isolated for the low power consumption.
Table 29 provide transformer vendors provide compatible magnetic parts for Micrel’s device.
Table 29. Qualified Magnetic Vendors
Vendors and Parts
Auto MDIX
# of Ports
Vendors and Parts
Auto MDIX
# of Ports
Pulse
H1664NL
H1164NL
TLA-6T718A
LF-H41S
Yes
Yes
Yes
Yes
Yes
4
4
1
1
1
Pulse
H1102
S558-5999-U7
PT163020
HB726
Yes
Yes
Yes
Yes
Yes
1
1
1
1
1
Pulse
TDK
Bel Fuse
YCL
LanKom
Datatronic
Transpower
Delta
NT79075
LF8505
Reference Crystal Selection
Table 30. Typical Reference Crystal Characteristics
Characteristics
Value
Units
MHz
ppm
pF
Frequency
25.00000
< = ±50
18 − 27
40
Frequency Tolerance (max.)
Load Capacitance (max.)
Series Resistance
Ω
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Package Information
128-Pin LQFP Package
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2011 Micrel, Incorporated.
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