LAN8671 [MICROCHIP]
10BASE-T1S Ethernet PHY Transceiver Product Brief;
| 型号： | LAN8671 |
| 厂家： | 
MICROCHIP |
| 描述： | 10BASE-T1S Ethernet PHY Transceiver Product Brief |
| 文件： | 总30页 (文件大小：575K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LAN8670/1/2
10BASE-T1S Ethernet PHY Transceiver Product Brief
Description
The LAN8670/1/2 is a high-performance 10BASE-T1S
•
•
Physical Layer Collision Avoidance (PLCA)
single-pair Ethernet PHY transceiver for 10ꢀMbit/s half-
duplex networking over a single pair of conductors.
Utilizing standard Ethernet technology in sensor/
actuator networks reduces application costs by
eliminating gateways necessary with legacy networking
technologies. The ability to connect multiple PHYs onto a
common mixing segment further saves implementation
costs by reducing cabling and switch ports. The
LAN8670/1/2 is designed for use in high-reliability cost
sensitive industrial, backplane, and building automation
sensor/actuator applications.
– Allows for high bandwidth utilization by
avoiding collisions on the physical layer
– Burst mode for transmission of multiple
packets for high packet rate latency-sensitive
applications
Enhanced electromagnetic compatibility /
electromagnetic interference (EMC/EMI)
performance
– Low RF emissions
– Robust against injected currents and network
cable shorts to ground or battery
– Simple low cost analog front-end
Highlights
•
•
Single 3.3V supply with integrated 1.8V regulator
•
•
High-performance 10BASE-T1S Ethernet PHY
Designed according to IEEE Std 802.3cg-2019™
– 10ꢀMbit/s over single balanced pair
Small footprint VQFN packaging with wettable
flanks
– LAN8670 32-pin (5ꢀxꢀ5ꢀmm)
– LAN8671 24-pin (4ꢀxꢀ4ꢀmm)
– Half-duplex point-to-point link segments up to
at least 15m
– LAN8672 36-pin (6ꢀxꢀ6ꢀmm)
– Half-duplex multidrop mixing segments up to at
least 25m with up to at least 8 PHYs
•
•
-40°C to +125°C extended temperature range
Microchip Functional Safety Ready
•
•
Media Independent Interface (MII) and Reduced
Media Independent Interface (RMII)
– 2.5ꢀMHz MII clock mode
– 50ꢀMHz RMII clock mode
Target Applications
•
Sensor/actuator networks operating at high
bandwidth
– Serial Management Interface (SMI) for rapid
register access
•
Microphone networks delivering audio streams for
beamforming, hands-free microphones, etc.
– Comprehensive status interrupt support
•
•
•
Backplane communication
Carrier Sense Multiple Access / Collision Detection
(CSMA/CD) media access control
Industrial control cabinets and machine control
Building automation
DS60001536E-page 1
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
To Our Valued Customers
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•
•
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DS60001536E-page 2
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Table of Contents
Description..................................................................................................................................................... 1
To Our Valued Customers.............................................................................................................................. 2
1. Preface....................................................................................................................................................4
1.1. Buffer Types................................................................................................................................. 4
2. Introduction............................................................................................................................................. 5
2.1. General Description......................................................................................................................5
3. Pin Description and Configuration...........................................................................................................7
3.1. LAN8670 Pin Assignments...........................................................................................................7
3.2. LAN8671 Pin Assignments...........................................................................................................9
3.3. LAN8672 Pin Assignments.........................................................................................................10
3.4. Pin Descriptions......................................................................................................................... 12
3.5. Configuration Straps...................................................................................................................14
4. Packaging Information.......................................................................................................................... 16
4.1. 32-VQFN (LAN8670 Only)......................................................................................................... 16
4.2. 24-VQFN (LAN8671 Only)......................................................................................................... 19
4.3. 36-VQFN (LAN8672 Only)......................................................................................................... 22
5. Package Marking Information............................................................................................................... 25
The Microchip Website.................................................................................................................................27
Product Change Notification Service............................................................................................................27
Customer Support........................................................................................................................................ 27
Microchip Devices Code Protection Feature................................................................................................27
Legal Notice................................................................................................................................................. 28
Trademarks.................................................................................................................................................. 28
Quality Management System....................................................................................................................... 29
Worldwide Sales and Service.......................................................................................................................30
DS60001536E-page 3
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Preface
1.
Preface
1.1
Buffer Types
Table 1-1.ꢀLAN8670/1/2 Buffer Type Descriptions
Buffer
Description
AI
Analog input
AO
AIO
ICLK
OCLK
P
Analog output
Analog bi-directional
Oscillator input
Crystal oscillator output
Power
PD
55ꢀkΩ (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always
enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive
signals external to the device. When connected to a load that must be pulled low, an external resistor must be
added.
PU
55ꢀkΩ (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-ups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals
external to the device. When connected to a load that must be pulled high, an external resistor must be added.
VIS-VDDP
VO-VDDP
VOH-VDDP
VOD-VDDP
3.3V Schmitt-triggered input (VDDP power domain)
3.3V output (VDDP power domain)
3.3V high-speed output (VDDP power domain)
3.3V open-drain output (VDDP power domain)
Note:ꢀ Digital signals are not 5V tolerant unless specified.
DS60001536E-page 4
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Introduction
2.
Introduction
2.1
General Description
The Microchip LAN8670/1/2 is a compact, low power, and cost-effective single-port 10BASE-T1S Ethernet physical
layer transceiver designed according to the IEEE Std 802.3cg-2019 specification. The device provides 10 Mbit/s
half-duplex transmit and receive capability over single-balanced pair medium such as Unshielded Twisted Pair (UTP)
cable. The LAN8670/1/2 is designed for use in applications requiring extended temperature range (-40°C to +125°C).
The device is also compliant to industrial EMC and EMI requirements. The single power supply and simple analog
front end simplifies its integration into small form factor applications.
The LAN8670/1/2 allows for the creation of both multidrop and point-to-point network topologies. Point-to-point link
segments of up to at least 15m in length are supported. The multidrop mode supports up to at least 8 PHYs
connected to a common mixing segment of up to at least 25m in length. The ability to connect multiple PHYs to a
common mixing segment reduces weight and implementation costs by reducing cabling and switch ports.
The LAN8670/1/2 supports communication with an Ethernet MAC via standard MII/RMII interfaces. An integrated
serial management interface (SMI) provides rapid register access and configuration at up to 4ꢀMHz.
Access to the physical medium is managed by CSMA/CD and optionally supplemented by Physical Layer Collision
Avoidance (PLCA).
The LAN8670/1/2 is designed to be used in functional safety related applications.
The Microchip LAN8670/1/2 family includes the following devices:
•
•
•
LAN8670
LAN8671
LAN8672
Device specific features that do not pertain to the entire LAN8670/1/2 family are called out independently throughout
this document. Table 2-1 below provides a summary of the feature differences between family members.
Table 2-1.ꢀLAN8670/1/2 Family Feature Matrix
o
o
Part Number
LAN8670
Package
32-VQFN
24-VQFN
36-VQFN
MII Support
RMII Support
PLCA Support
-40 to +125 C
X
X
X
X
X
X
X
X
X
LAN8671
LAN8672
X
A system-level block diagram and internal block diagram of the LAN8670/1/2 are shown in the following figures.
DS60001536E-page 5
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Introduction
Figure 2-1.ꢀLAN8670/1/2 System-Level Block Diagram
External MCU
TRXN
TRXP
MDI-
10 Mbps
MII/RMII
Ethernet
LAN8670/1/2
MDI+
MAC
Crystal or
Clock
Oscillator
Figure 2-2.ꢀLAN8670/1/2 Internal Block Diagram
VDDP
(3.3V)
MII/RMII
Mux
1.8V
LDO
RMII Logic
(10 mA)
MII
VDDA
(3.3V)
PLCA
VDDA POR
1.8 V POR
TRXP
TRXN
PCS
PMA
RESET_N
RESET Generator
XTI/REFCLKIN
XTO
CSRs
Control FSM
SMI
Misc Analog
MDIO MDC
IRQ_N
VDDA
RBIAS
(3.3V)
DS60001536E-page 6
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Pin Description and Configuration
3.
Pin Description and Configuration
The pin assignments and descriptions for the LAN8670/1/2 are detailed in the following sections. Pin buffer type
definitions are detailed in the Buffer Types section.
Related Links
1.1 Buffer Types
3.1
LAN8670 Pin Assignments
Figure 3-1.ꢀ LAN8670 32-VQFN Pin Assignments
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DNC
COL
RXD3 / MODE1
RXD2 / MODE0
IRQ_N
TXD3
TXD2
TXD1
TXD0
TXEN
VDDP
Microchip
RXER / PHYAD0
RXDV / CRSDV / PHYAD1
RXD1 / PHYAD3
VDDP
LAN8670
(Top View 32-VQFN)
Thermal slug connects to VSS
RXCLK
Note: Exposed pad (VSS) on bottom of package must be connected to ground.
Note:ꢀ Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor.
DS60001536E-page 7
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Pin Description and Configuration
Table 3-1.ꢀLAN8670 32-VQFN Pin Assignments
Pin Num
Pin Name
Pin Num
Pin Name
1
DNC
17
RXCLK
2
3
4
5
6
7
8
9
COL
TXD3
TXD2
TXD1
TXD0
TXEN
VDDP
DNC
18
19
20
21
22
23
24
25
VDDP
RXD1/PHYAD3
RXDV/CRSDV/PHYAD1
RXER/PHYAD0
IRQ_N
RXD2/MODE0
RXD3/MODE1
VDDA
10
11
12
13
14
15
16
RESET_N
TXER
26
27
28
29
30
31
32
RBIAS
XTI/REFCLKIN
XTO
TXCLK
MDC
VDDA
MDIO
TRXP
CRS/PHYAD4
RXD0/PHYAD2
TRXN
VSS
Note:ꢀ Exposed Pad (VSS) must be connected to ground.
DS60001536E-page 8
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Pin Description and Configuration
3.2
LAN8671 Pin Assignments
Figure 3-2.ꢀLAN8671 24-VQFN Pin Assignments
1
18
VSS
VDDA
2
17
DNC
DNC
3
16
TXD1
TXD0
TXEN
VDDP
Microchip
IRQ_N
LAN8671
4
5
6
15
RXER / PHYAD0
(Top View 24-VQFN)
14
CRSDV / PHYAD1
Thermal slug connects to VSS
13
VDDP
Note: Exposed pad (VSS) on bottom of package must be connected to ground.
Note:ꢀ Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor.
Table 3-2.ꢀLAN8671 24-VQFN Pin Assignments
Pin Num
Pin Name
Pin Num
Pin Name
1
VSS
13
VDDP
2
DNC
14
CRSDV/PHYAD1
3
4
5
TXD1
TXD0
TXEN
15
16
17
RXER/PHYAD0
IRQ_N
DNC
6
7
VDDP
DNC
18
19
VDDA
RBIAS
8
RESET_N
MDC
20
21
22
23
24
REFCLKIN
DNC
9
10
11
12
MDIO
VDDA
TRXP
RXD0/PHYAD2
RXD1/PHYAD3
TRXN
Note:ꢀ Exposed Pad (VSS) must be connected to ground.
DS60001536E-page 9
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Pin Description and Configuration
3.3
LAN8672 Pin Assignments
Figure 3-3.ꢀLAN8672 36-VQFN Pin Assignments
1
27
DNC
DNC
2
26
COL
RXD3 / MODE1
3
25
TXCLK
RXD2 / MODE0
4
24
TXD3
IRQ_N
Microchip
5
6
7
8
9
23
TXD2
TXD1
TXD0
TXEN
VDDP
RXER / PHYAD0
LAN8672
(Top View 36-VQFN)
22
RXDV / PHYAD1
21
RXD1 / PHYAD3
20
VDDP
Thermal slug connects to VSS
19
RXCLK
Note: Exposed pad (VSS) on bottomofpackage must be connected to ground.
Note:ꢀ Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor.
DS60001536E-page 10
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Pin Description and Configuration
Table 3-3.ꢀLAN8672 36-VQFN Pin Assignments
Pin Num
Pin Name
Pin Num
Pin Name
1
DNC
19
RXCLK
2
3
4
5
6
7
8
9
COL
TXCLK
TXD3
TXD2
TXD1
TXD0
TXEN
VDDP
20
21
22
23
24
25
26
27
VDDP
RXD1/PHYAD3
RXDV/PHYAD1
RXER/PHYAD0
IRQ_N
RXD2/MODE0
RXD3/MODE1
DNC
10
11
DNC
28
29
NC
RESET_N
VDDA
12
13
TXER
VSS
30
31
RBIAS
XTI
14
DNC
32
XTO
15
16
17
18
MDC
33
34
35
36
VDDA
TRXP
TRXN
VSS
MDIO
CRS/PHYAD4
RXD0/PHYAD2
Note:ꢀ Exposed Pad (VSS) must be connected to ground.
DS60001536E-page 11
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Pin Description and Configuration
3.4
Pin Descriptions
This section contains descriptions of the various LAN8670/1/2 pins. The “_N” symbol in the signal name indicates
that the active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates
that the reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the
high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture
of “active low” and “active high” signals. The term assert, or assertion, indicates that a signal is active, independent
of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is
inactive.
Pin buffer type definitions are detailed in the Buffer Types section.
Table 3-4.ꢀMII/RMII Signals
Name
Symbol
Buffer Type
Description
Transmit Data 0
TXD0
VIS-VDDP
Transmit data bus bit 0 (all modes)
Transmit Data 1
TXD1
TXD2
VIS-VDDP
VIS-VDDP
Transmit data bus bit 1 (all modes)
Transmit data bus bit 2 (MII mode)
Transmit Data 2
(MII Mode)
In RMII mode, this signal is not used and is internally pulled-
down to VSS.
Transmit Data 3
(MII Mode)
TXD3
TXER
VIS-VDDP
VIS-VDDP
Transmit data bus bit 3 (MII mode)
In RMII mode, this signal is not used and is internally pulled-
down to VSS.
Transmit Error
(MII Mode)
This signal is asserted to indicate that an error was detected
somewhere in the packet presently being transferred to the
transceiver.
This pin is unused in RMII mode and should be connected to
VSS.
Transmit Enable
TXEN
VIS-VDDP
VO-VDDP
Indicates that valid transmission data is present on TXD[3:0]. In
RMII mode, only TXD[1:0] provide valid data.
Note:ꢀ A pull-down resistor is recommended to prevent
incidental transmission if the MAC does not actively pull-down
or drive this pin low at all times during its reset and initialization.
Transmit Clock
(MII Mode)
TXCLK
2.5ꢀMHz clock used to latch data from the MAC into the
transceiver.
In RMII mode, this pin is unused and is driven low. It should be
left unconnected.
Receive Data 0
Receive Data 1
RXD0
RXD1
RXD2
VOH-VDDP
VOH-VDDP
VO-VDDP
Receive data bus bit 0 (all modes)
Receive data bus bit 1 (all modes)
Receive Data 2
(MII Mode)
Receive data bus bit 2 (MII mode)
In RMII mode, this pin is unused and is driven low.
Receive Data 3
(MII Mode)
RXD3
RXER
VO-VDDP
Receive data bus bit 3 (MII mode)
In RMII mode, this pin is unused and is driven low.
Receive Error
VOH-VDDP
This signal is asserted to indicate that an error was detected
somewhere in the packet presently being transferred from the
transceiver.
This signal is optional in RMII mode.
DS60001536E-page 12
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Pin Description and Configuration
...........continued
Name
Symbol
Buffer Type
Description
Receive Data Valid
(MII Mode)
RXDV
VOH-VDDP
Indicates that recovered and decoded data is available on the
RXD[3:0] pins.
This signal is not used in RMII mode.
Receive Clock
(MII Mode)
RXCLK
CRSDV
VO-VDDP
In MII mode, this pin is the 2.5ꢀMHz receive clock output.
In RMII mode, this pin is unused and is driven low. It should be
left unconnected.
Carrier Sense / Receive Data
Valid (RMII Mode)
VOH-VDDP
This signal is asserted to indicate the receive medium is non-
idle in RMII mode.
This signal is not used in MII mode.
Collision Detect
(MII Mode)
COL
CRS
VO-VDDP
VO-VDDP
Collision Detect.
In RMII mode, this pin is unused and is driven low.
Carrier Sense
(MII Mode)
Carrier Sense.
In RMII mode, this pin is unused and is driven low.
Table 3-5.ꢀEthernet Transceiver Pins
Name
Symbol
Buffer Type
AIO
Description
Ethernet TX/RX Positive Terminal
Ethernet TX/RX Negative Terminal
TRXP
TRXN
Positive terminal for transmit/receive signal.
Negative terminal for transmit/receive signal.
AIO
Table 3-6.ꢀSerial Management Interface (SMI) Pins
Name
Symbol
Buffer Type
Description
SMI Data Input/Output
MDIO
VIS-VDDP /
VO-VDDP
Serial Management Interface data input/output.
SMI Clock
MDC
VIS-VDDP
Serial Management Interface clock.
Table 3-7.ꢀMiscellaneous Pins
Name
Symbol
XTI
Buffer Type
ICLK
Description
External 25ꢀMHz Crystal Input
External Clock Input
External 25ꢀMHz crystal input.
REFCLKIN
ICLK
Single-ended clock oscillator input. A frequency of 25ꢀMHz shall
be used in all modes except RMII, which requires 50ꢀMHz.
Note:ꢀ When using a single-ended clock oscillator, XTO must
be left unconnected with <10ꢀpF stray capacitance.
External 25ꢀMHz Crystal Output
XTO
OCLK
External 25ꢀMHz crystal output.
Note:ꢀ When using a single-ended clock oscillator on XTI/
REFCLKIN, this pin must be left unconnected with <10ꢀpF stray
capacitance.
Interrupt
IRQ_N
VOD-VDDP
Device interrupt. Active low and open drain.
Note:ꢀ When used, this pin requires a 10ꢀkΩ (typical) pull-up to
VDDP.
Note:ꢀ This pin is to be unconnected when unused.
System Reset
RESET_N
VIS-VDDP
System reset. This pin is active low.
If unused, this pin must be pulled-up to VDDP.
DS60001536E-page 13
Product Brief
© 2021 Microchip Technology Inc.
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LAN8670/1/2
Pin Description and Configuration
...........continued
Name
Symbol
Buffer Type
Description
Bias Resistor
RBIAS
AIO
External bias resistor connection pin. This pin requires
connection of a 12.4ꢀkΩ resistor to ground.
Note:ꢀ The resistor must be within ±ꢀ1% tolerance across the
entire expected operating temperature range.
Do Not Connect
No Connect
DNC
NC
-
-
Pin is internally connected. The pin must be left floating
externally.
Pin is not connected internally. The pin should be left floating
externally.
Table 3-8.ꢀConfiguration Straps
Name
Symbol
Buffer Type
Description
Operating Mode Configuration
Straps 1-0
MODE[1:0]
VIS-VDDP
These configuration straps are used to select the device’s
default mode of operation. See Section 3.5, Configuration
Straps for additional information.
PHY Address Configuration
Straps 4-0
PHYAD[4:0]
VIS-VDDP
These configuration straps are used to select the device’s
default PHY SMI address. See Section 3.5, Configuration
Straps for additional information.
Table 3-9.ꢀPower Pins
Name
Symbol
Buffer Type
Description
+3.3V Switched I/O Power Supply
Input
VDDP
P
+3.3V switched I/O power supply input.
+3.3V Switched Analog Power
Supply Input
VDDA
VSS
P
P
+3.3V switched analog power supply input.
Ground
Common ground.
This exposed pad must be connected to the ground plane with
a via array.
3.5
Configuration Straps
Configuration straps allow various features of the device to be automatically configured to user defined values.
Configuration straps are identified by an underlined symbol name in the pin assignment lists and are latched on
Power-On Reset (POR) and pin reset (RESET_N). Configuration straps do not have internal resistors to prevent the
signal from floating when unconnected.
Important:ꢀ External pull-up or pull-down resistors must be sized appropriately (10ꢀkΩ, typical) to ensure
that the configuration straps reach the required voltage level prior to latching at reset.
3.5.1
Device Mode (MODE[1:0])
The MODE[1:0] configuration straps control various device modes. When the RESET_N pin is negated, the
associated register bit values are loaded according to the MODE[1:0] configuration straps and the device is
configured. When a soft reset occurs via the Soft Reset bit of the Basic Control Register, the configuration of the
device is controlled by the register bit values and the MODE[1:0] configuration straps have no affect.
The device’s mode may be configured using the hardware configuration straps as summarized in Table 3-10 below.
Note:ꢀ As the LAN8672 only supports operation in MII mode, the MODE[1:0] configuration straps must be set to 01b.
DS60001536E-page 14
Product Brief
© 2021 Microchip Technology Inc.
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LAN8670/1/2
Pin Description and Configuration
Table 3-10.ꢀMODE[1:0] Configuration Straps
MODE[1:0] Definition
00b
01b
10b
11b
Reserved
PHY is placed in MII mode with 25ꢀMHz crystal
PHY is placed in RMII mode with 50ꢀMHz REFCLKIN
Reserved
3.5.2
PHY Address (PHYAD[4:0])
The PHYAD[4:0] configuration straps are driven high or low to give each PHY a unique SMI address. This address is
latched into an internal register at the end of a hardware reset. In a multi-transceiver application (such as a switch),
the controller is able to manage each transceiver via the unique address. Each transceiver checks each management
data frame for a matching address in the relevant bits. When a match is recognized, the transceiver responds to that
particular frame.
The LAN8670/2 SMI address must be configured using the PHYAD[4:0] hardware configuration straps to any
value between 0x00 and 0x1F. The LAN8671 SMI address must be configured using the PHYAD[3:0] hardware
configuration straps to any value between 0x00 and 0x0F.
DS60001536E-page 15
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Packaging Information
4.
Packaging Information
4.1
32-VQFN (LAN8670 Only)
32-Lead Very Thin Plastic Quad Flat, No Lead Package (LMX) - 5x5x1.0 mm Body [VQFN]
With 3.4 mm Exposed Pad and Stepped Wettable Flanks
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
32
0.50 BSC
0.90
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
1.00
0.05
0.02
0.203 REF
5.00 BSC
3.40
5.00 BSC
3.40
0.25
0.40
-
0.35 REF
-
0.060
3.30
3.50
3.30
0.20
0.30
0.20
3.50
0.30
0.50
-
Terminal-to-Exposed Pad
Exposed Pad Corner Chamfer
Step Height
K
CH
A4
D3
0.10
0.035
0.19
0.085
Step Length
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-500 Rev B Sheet 1 of 2
DS60001536E-page 16
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (LMX) - 5x5x1.0 mm Body [VQFN]
With 3.4 mm Exposed Pad and Stepped Wettable Flanks
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
32X
0.08 C
0.10 C
D
A
B
NOTE 1
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
A1
TOP VIEW
0.10 C
0.10
C A B
(A3)
D2
A
SEATING
PLANE
C
0.10
C A B
SIDE VIEW
E2
e
2
A
A
2
1
A4
K
2X (CH)
D3
N
SECTION A-A
L
32X b
0.10
0.05
C A B
e
C
BOTTOM VIEW
Microchip Technology Drawing C04-500 Rev B Sheet 1 of 2
DS60001536E-page 17
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (LMX) - 5x5x1.0 mm Body [VQFN]
With 3.4 mm Exposed Pad and Stepped Wettable Flanks
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
32
1
2
Øv
EV
G2
C2 Y2
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
3.50
3.50
4.90
4.90
Contact Pad Spacing
Contact Pad Width (32)
Contact Pad Length (32)
Contact Pad to Center Pad (32)
Contact Pad to Contact Pad (X28)
Thermal Via Diameter
0.30
0.85
0.20
0.20
0.33
1.20
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2500 Rev B
DS60001536E-page 18
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Packaging Information
4.2
24-VQFN (LAN8671 Only)
24-Lead Very Thin Plastic Quad Flat, No Lead Package (U3B) - 4x4 mm Body [VQFN]
With 2.6mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZCY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24X
0.08 C
0.10 C
D
A
B
NOTE 1
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
A1
TOP VIEW
0.10 C
(A3)
0.10
C A B
A
C
D2
SEATING
PLANE
SIDE VIEW
0.10
C A B
DETAIL A
E2
A4
e
2
2
1
A
A
STEPPED
WETTABLE
FLANK
D3
SECTION A-A
K
N
L
24X b
0.10
0.05
C A B
e
C
BOTTOM VIEW
Microchip Technology Drawing C04-21483 Rev A Sheet 1 of 2
DS60001536E-page 19
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Packaging Information
24-Lead Very Thin Plastic Quad Flat, No Lead Package (U3B) - 4x4 mm Body [VQFN]
With 2.6mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZCY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units
MILLIMETERS
Dimension Limits
MIN
NOM
24
0.50 BSC
0.85
0.035
0.203 REF
4.00 BSC
2.60
4.00 BSC
2.60
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
0.90
0.05
2.50
2.70
2.50
0.20
0.35
0.20
-
2.70
0.30
0.45
-
0.085
0.19
0.25
0.40
-
-
Terminal-to-Exposed-Pad
Wettable Flank Step Length
Wettable Flank Step Height
K
D3
A4
0.10
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21483 Rev A Sheet 2 of 2
DS60001536E-page 20
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Packaging Information
24-Lead Very Thin Plastic Quad Flat, No Lead Package (U3B) - 4x4 mm Body [VQFN]
With 2.6mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZCY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
ØV
G2
C2
Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
2.70
2.70
4.00
4.00
Contact Pad Spacing
Contact Pad Width (X24)
Contact Pad Length (X24)
Contact Pad to Center Pad (X24)
Contact Pad to Contact Pad (20)
Thermal Via Diameter
0.30
0.85
0.23
0.20
0.30
1.00
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23483 Rev A Sheet 1 of 2
DS60001536E-page 21
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Packaging Information
4.3
36-VQFN (LAN8672 Only)
36-Lead Very Thin Plastic Quad Flat, No Lead Package (LNX) - 6x6x1.0 mm Body [VQFN]
With 4.4 mm Exposed Pad and Stepped Wettable Flanks
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
36X
0.08 C
0.10 C
D
A
B
NOTE 1
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
A1
TOP VIEW
0.10 C
(A3)
0.10
C A B
D2
A
SEATING
PLANE
C
SIDE VIEW
0.10
C A B
NOTE 1
E2
A4
2
1
A
A
D3
2X (CH)
SECTION A-A
N
L
36X b
0.10
0.05
C A B
e
C
BOTTOM VIEW
Microchip Technology Drawing C04-501 Rev B Sheet 1 of 2
DS60001536E-page 22
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Packaging Information
36-Lead Very Thin Plastic Quad Flat, No Lead Package (LNX) - 6x6x1.0 mm Body [VQFN]
With 4.4 mm Exposed Pad and Stepped Wettable Flanks
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
36
0.50 BSC
0.90
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
1.00
0.05
0.02
0.203 REF
6.00 BSC
4.40
6.00 BSC
4.40
0.25
0.40
-
0.35 REF
-
0.060
4.30
4.50
4.30
0.20
0.30
0.20
4.50
0.30
0.50
-
Terminal-to-Exposed-Pad
Exposed Pad Corner Chamfer
Step Height
K
CH
A4
D3
0.10
0.035
0.19
0.085
Step Length
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-501 Rev B Sheet 2 of 2
DS60001536E-page 23
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Packaging Information
36-Lead Very Thin Plastic Quad Flat, No Lead Package (LNX) - 6x6x1.0 mm Body [VQFN]
With 4.4 mm Exposed Pad and Stepped Wettable Flanks
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
36
1
ØV
2
G2
C2
EV
Y2
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Contact Pitch
E
0.50 BSC
Center Pad Width
Center Pad Length
X2
Y2
C1
C2
X1
Y1
G1
G2
V
4.50
4.50
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (Xnn)
Contact Pad Length (Xnn)
Contact Pad to Center Pad (Xnn)
Contact Pad to Contact Pad (Xnn)
Thermal Via Diameter
5.90
5.90
0.30
0.85
0.20
0.20
0.33
1.20
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2501 Rev B
DS60001536E-page 24
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Package Marking Information
5.
Package Marking Information
Figure 5-1.ꢀLAN8670 Top Mark
Legend:
LAN8670 Device Identifier
rr
Product Revision Code
yy
last two digits of Assembly Year
ww
nnn
cc
Assembly Work Week
Tracking Number
Country of Origin Abbreviation (optional)
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e
can be found on the outer packaging for this package.
e
3
*
)
3
LAN8670
rr
yywwnnn
cc
Figure 5-2.ꢀLAN8671 Top Mark
Legend:
8671
rr
Device Identifier (LAN8671)
Product Revision Code
y
last digit of Assembly Year
Assembly Work Week
Tracking Number
Country of Origin Abbreviation (optional)
Pb-free JEDEC designator for Matte Tin (Sn)
ww
nnn
cc
8671
rr
ywwnnn
cc
e
3
*
This package is Pb-free. The Pb-free JEDEC designator ( e
can be found on the outer packaging for this package.
)
3
DS60001536E-page 25
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Package Marking Information
Figure 5-3.ꢀLAN8672 Top Mark
Legend:
LAN8672 Device Identifier
rr
Product Revision Code
yy
last two digits of Assembly Year
ww
nnn
cc
Assembly Work Week
Tracking Number
Country of Origin Abbreviation (optional)
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e
can be found on the outer packaging for this package.
e
3
*
)
3
LAN8672
rr
yywwnnn
cc
DS60001536E-page 26
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
The Microchip Website
Microchip provides online support via our website at www.microchip.com/. This website is used to make files and
information easily available to customers. Some of the content available includes:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online
discussion groups, Microchip design partner program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of
seminars and events, listings of Microchip sales offices, distributors and factory representatives
Product Change Notification Service
Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will
receive email notification whenever there are changes, updates, revisions or errata related to a specified product
family or development tool of interest.
To register, go to www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Embedded Solutions Engineer (ESE)
Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: www.microchip.com/support
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner and under normal
conditions.
•
There are dishonest and possibly illegal methods being used in attempts to breach the code protection features
of the Microchip devices. We believe that these methods require using the Microchip products in a manner
outside the operating specifications contained in Microchip’s Data Sheets. Attempts to breach these code
protection features, most likely, cannot be accomplished without violating Microchip’s intellectual property rights.
•
•
Microchip is willing to work with any customer who is concerned about the integrity of its code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code
protection does not mean that we are guaranteeing the product is “unbreakable.” Code protection is constantly
evolving. We at Microchip are committed to continuously improving the code protection features of our products.
Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act.
If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue
for relief under that Act.
DS60001536E-page 27
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Legal Notice
Information contained in this publication is provided for the sole purpose of designing with and using Microchip
products. Information regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications.
THIS INFORMATION IS PROVIDED BY MICROCHIP “AS IS”. MICROCHIP MAKES NO REPRESENTATIONS
OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR
CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE
WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR
THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk,
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Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo,
MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip
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Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed
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VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2021, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-8406-6
DS60001536E-page 28
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
LAN8670/1/2
Quality Management System
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
DS60001536E-page 29
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
Worldwide Sales and Service
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Corporate Office
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Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 86-27-5980-5300
China - Xian
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-72884388
Tel: 281-894-5983
Indianapolis
Tel: 86-29-8833-7252
China - Xiamen
Noblesville, IN
Tel: 86-592-2388138
China - Zhuhai
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
Tel: 44-118-921-5800
Fax: 44-118-921-5820
DS60001536E-page 30
Product Brief
© 2021 Microchip Technology Inc.
and its subsidiaries
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