LAN8720ACP-ABC_技术文档

LAN8720A/LAN8720AI

Small Footprint RMII 10/100 Ethernet

Transceiver with HP Auto-MDIX Support

Highlights

Key Benefits

• Single-Chip Ethernet Physical Layer Transceiver

(PHY)

• Comprehensive flexPWR^®Technology

• High-Performance 10/100 Ethernet Transceiver

- Compliant with IEEE802.3/802.3u (Fast

Ethernet)

- Flexible Power Management Architecture

- Compliant with ISO 802-3/IEEE 802.3

(10BASE-T)

- LVCMOS Variable I/O voltage range: +1.6V

to +3.6V

- Loop-back modes

- Integrated 1.2V regulator

• HP Auto-MDIX support

- Auto-negotiation

- Automatic polarity detection and correction

- Link status change wake-up detection

- Vendor specific register functions

• Miniature 24-pin QFN/SQFN lead-free RoHS

compliant packages (4 x 4mm).

- Supports the reduced pin count RMII inter-

face

Target Applications

• Power and I/Os

• Set-Top Boxes

- Various low power modes

- Integrated power-on reset circuit

- Two status LED outputs

• Networked Printers and Servers

• Test Instrumentation

• LAN on Motherboard

- Latch-Up Performance Exceeds 150mA per

EIA/JESD 78, Class II

• Embedded Telecom Applications

• Video Record/Playback Systems

• Cable Modems/Routers

• DSL Modems/Routers

• Digital Video Recorders

• IP and Video Phones

- May be used with a single 3.3V supply

• Additional Features

- Ability to use a low cost 25Mhz crystal for

reduced BOM

• Packaging

• Wireless Access Points

• Digital Televisions

- 24-pin QFN/SQFN (4x4 mm) Lead-Free

RoHS Compliant package with RMII

• Digital Media Adapters/Servers

• Gaming Consoles

• Environmental

- Extended commercial temperature range 

(0°C to +85°C)

• POE Applications (Refer to Application Note

17.18)

- Industrial temperature range version avail-

able (-40°C to +85°C)

 2016 Microchip Technology Inc.

DS00002165B-page 1

LAN8720A/LAN8720AI

TO OUR VALUED CUSTOMERS

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-

rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the

revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are

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DS00002165B-page 2

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

Table of Contents

1.0 Introduction ..................................................................................................................................................................................... 4

2.0 Pin Description and Configuration .................................................................................................................................................. 6

3.0 Functional Description .................................................................................................................................................................. 14

4.0 Register Descriptions .................................................................................................................................................................... 41

5.0 Operational Characteristics ........................................................................................................................................................... 52

6.0 Package Information ..................................................................................................................................................................... 66

7.0 Application Notes .......................................................................................................................................................................... 71

Appendix A: Data Sheet Revision History ........................................................................................................................................... 73

The Microchip Web Site ...................................................................................................................................................................... 74

Customer Change Notification Service ............................................................................................................................................... 74

Customer Support ............................................................................................................................................................................... 74

Product Identification System ............................................................................................................................................................. 75

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LAN8720A/LAN8720AI

1.0

1.1

INTRODUCTION

General Terms and Conventions

The following is list of the general terms used throughout this document:

BYTE

FIFO

8-bits

First In First Out buffer; often used for elasticity buffer

Media Access Controller

MAC

RMII™

N/A

Reduced Media Independent Interface^TM

Not Applicable

X

Indicates that a logic state is “don’t care” or undefined.

RESERVED

Refers to a reserved bit field or address. Unless otherwise

noted, reserved bits must always be zero for write opera-

tions. Unless otherwise noted, values are not guaranteed

when reading reserved bits. Unless otherwise noted, do

not read or write to reserved addresses.

SMI

Serial Management Interface

1.2

General Description

The LAN8720A/LAN8720Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver with variable I/O

voltage that is compliant with the IEEE 802.3-2005 standards.

The LAN8720A/LAN8720Ai supports communication with an Ethernet MAC via a standard RMII interface. It contains a

full-duplex 10-BASE-T/100BASE-TX transceiver and supports 10Mbps (10BASE-T) and 100Mbps (100BASE-TX) oper-

ation. The LAN8720A/LAN8720Ai implements auto-negotiation to automatically determine the best possible speed and

duplex mode of operation. HP Auto-MDIX support allows the use of direct connect or cross-over LAN cables.

The LAN8720A/LAN8720Ai supports both IEEE 802.3-2005 compliant and vendor-specific register functions. However,

no register access is required for operation. The initial configuration may be selected via the configuration pins as

described in Section 3.7, "Configuration Straps," on page 29. Register-selectable configuration options may be used to

further define the functionality of the transceiver.

Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6V. The device can be configured to operate

on a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The linear regulator may be optionally dis-

abled, allowing usage of a high efficiency external regulator for lower system power dissipation.

The LAN8720A/LAN8720Ai is available in both extended commercial and industrial temperature range versions. A typ-

ical system application is shown in Figure 1-1.

DS00002165B-page 4

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LAN8720A/LAN8720AI

FIGURE 1-1:

SYSTEM BLOCK DIAGRAM

10/100

Ethernet

MAC

LAN8720A/

LAN8720Ai

MDI

RMII

Transformer

RJ45

Mode

LED

Crystal or

Clock

Oscillator

FIGURE 1-2:

ARCHITECTURAL OVERVIEW

MODE[0:2]

Mode Control

HP Auto-MDIX

Auto-

Negotiation

100M TX

Logic

100M

Transmitter

TXP/TXN

RXP/RXN

nRST

Reset Control

RMIISEL

Transmitter

10M TX

Logic

10M

Transmitter

SMI

Management

Control

MDIX

Control

TXD[0:1]

TXEN

XTAL1/CLKIN

XTAL2

PLL

RXD[0:1]

RXER

100M RX

Logic

Analog-to-

Digital

DSP System:

Clock

Data Recovery

Equalizer

Interrupt

Generator

nINT

LED1

LED2

CRS_DV

MDC

100M PLL

LEDs

Receiver

10M RX

Logic

Squeltch

& Filters

MDIO

RBIAS

Central Bias

10M PLL

PHY Address

Latches

PHYAD0

LAN8720A/LAN8720Ai

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DS00002165B-page 5

LAN8720A/LAN8720AI

2.0

PIN DESCRIPTION AND CONFIGURATION

FIGURE 2-1:

24-QFN/SQFN PIN ASSIGNMENTS (TOP VIEW)

VDD1A 19

12 MDIO

LAN8720A/LAN8720Ai

TXN 20

TXP 21

11 CRS_DV/MODE2

10 RXER/PHYAD0

(TOP VIEW)

VSS

RXN 22

RXP 23

RBIAS 24

9

8

7

VDDIO

RXD0/MODE0

RXD1/MODE1

NOTE: Exposed pad (VSS) on bottom of package must be connected to ground

Note 2-1

Note 2-2

When a lower case “n” is used at the beginning of the signal name, it indicates that the signal is

active low. For example, nRST indicates that the reset signal is active low.

The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer

types is provided in Section 2.2.

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LAN8720A/LAN8720AI

TABLE 2-1:

RMII SIGNALS

Name

Buffer

Type

Num Pins

Symbol

Description

1

Transmit

Data 0

TXD0

VIS

The MAC transmits data to the transceiver using

this signal.

1

Transmit

Data 1

TXD1

TXEN

VIS

The MAC transmits data to the transceiver using

this signal.

Transmit

Enable

VIS

(PD)

Indicates that valid transmission data is present

on TXD[1:0].

Receive

Data 0

RXD0

VO8

Bit 0 of the 2 data bits that are sent by the trans-

ceiver on the receive path.

PHY Operat-

ing Mode 0

Configuration

Strap

MODE0

VIS

(PU)

Combined with MODE1 and MODE2, this config-

uration strap sets the default PHY mode.

See Note 2-3 for more information on configura-

tion straps.

Note: Refer to Section 3.7.2, "MODE[2:0]:

Mode Configuration," on page 30 for

additional details.

1

Receive

Data 1

RXD1

VO8

Bit 1 of the 2 data bits that are sent by the trans-

ceiver on the receive path.

PHY Operat-

ing Mode 1

Configuration

Strap

MODE1

VIS

(PU)

Combined with MODE0 and MODE2, this config-

uration strap sets the default PHY mode.

See Note 2-3 for more information on configura-

tion straps.

Note: Refer to Section 3.7.2, "MODE[2:0]:

Mode Configuration," on page 30 for

additional details.

1

Receive Error

RXER

VO8

This signal is asserted to indicate that an error

was detected somewhere in the frame presently

being transferred from the transceiver.

PHY Address

0

PHYAD0

VIS

(PD)

This configuration strap sets the transceiver’s SMI

address.

Configuration

Strap

See Note 2-3 for more information on configura-

tion straps.

Note: Refer to Section 3.7.1, "PHYAD[0]: PHY

Address Configuration," on page 26 for

additional information.

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LAN8720A/LAN8720AI

TABLE 2-1:

RMII SIGNALS (CONTINUED)

Buffer

Type

Num Pins

Name

Symbol

Description

1

CarrierSense

/ Receive

Data Valid

CRS_DV

VO8

This signal is asserted to indicate the receive

medium is non-idle. When a 10BASE-T packet is

received, CRS_DV is asserted, but RXD[1:0] is

held low until the SFD byte (10101011) is

received.

Note: Per the RMII standard, transmitted data is

not looped back onto the receive data

pins in 10BASE-T half-duplex mode.

PHY Operat-

ing Mode 2

Configuration

Strap

MODE2

VIS

(PU)

Combined with MODE0 and MODE1, this config-

uration strap sets the default PHY mode.

See Note 2-3 for more information on configura-

tion straps.

Note: Refer to Section 3.7.2, "MODE[2:0]:

Mode Configuration," on page 27 for

additional details.

Note 2-3

Configuration strap values are latched on power-on reset and system reset. Configuration straps are

identified by an underlined symbol name. Signals that function as configuration straps must be

augmented with an external resistor when connected to a load. Refer to Section 3.7, "Configuration

Straps," on page 29 for additional information.

TABLE 2-2:

NUM PINS

LED PINS

BUFFER

TYPE

NAME

SYMBOL

DESCRIPTION

LED 1

LED1

O12

Link activity LED Indication. This pin is driven

active when a valid link is detected and blinks

when activity is detected.

Note: Refer to Section 3.8.1, "LEDs," on

page 32 for additional LED information.

Regulator Off

Configuration

Strap

REGOFF

IS

(PD)

This configuration strap is used to disable the

internal 1.2V regulator. When the regulator is dis-

abled, external 1.2V must be supplied to VDDCR.

• When REGOFF is pulled high to VDD2A with

an external resistor, the internal regulator is

disabled.

1

• When REGOFF is floating or pulled low, the

internal regulator is enabled (default).

See Note 2-4 for more information on configura-

tion straps.

Note: Refer to Section 3.7.4, "REGOFF:

Internal +1.2V Regulator Configuration,"

on page 32 for additional details.

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LAN8720A/LAN8720AI

TABLE 2-2:

NUM PINS

LED PINS (CONTINUED)

BUFFER

TYPE

NAME

SYMBOL

DESCRIPTION

LED 2

LED2

O12

Link Speed LED Indication. This pin is driven

active when the operating speed is 100Mbps. It is

inactive when the operating speed is 10Mbps or

during line isolation.

Note: Refer to Section 3.8.1, "LEDs," on

page 32 for additional LED information.

nINT/

REFCLKO

Function

Select

nINTSEL

IS

(PU)

This configuration strap selects the mode of the

nINT/REFCLKO pin.

• When nINTSEL is floated or pulled to

VDD2A, nINT is selected for operation on the

nINT/REFCLKO pin (default).

Configuration

1

Strap

• When nINTSEL is pulled low to VSS, REF-

CLKO is selected for operation on the nINT/

REFCLKO pin.

See Note 2-4 for more information on configura-

tion straps.

Note: Refer to See Section 3.8.1.2, "nINTSEL

and LED2 Polarity Selection," on page 33

for additional information.

Note 2-4

Configuration strap values are latched on power-on reset and system reset. Configuration straps are

identified by an underlined symbol name. Signals that function as configuration straps must be

augmented with an external resistor when connected to a load. Refer to Section 3.7, "Configuration

Straps," on page 29 for additional information.

TABLE 2-3:

SERIAL MANAGEMENT INTERFACE (SMI) PINS

BUFFER

Num PINs

NAME

SYMBOL

DESCRIPTION

TYPE

1

SMI Data

MDIO

VIS/

Serial Management Interface data input/output

Input/Output

VOD8

1

SMI Clock

MDC

VIS

Serial Management Interface clock

TABLE 2-4:

ETHERNET PINS

BUFFER

TYPE

Num PINs

NAME

SYMBOL

DESCRIPTION

1

Ethernet TX/

RX Positive

Channel 1

TXP

TXN

AIO

Transmit/Receive Positive Channel 1

1

Ethernet TX/

RX Negative

Channel 1

AIO

Transmit/Receive Negative Channel 1

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DS00002165B-page 9

LAN8720A/LAN8720AI

TABLE 2-4:

ETHERNET PINS (CONTINUED)

BUFFER

TYPE

Num PINs

NAME

SYMBOL

DESCRIPTION

1

Ethernet TX/

RX Positive

Channel 2

RXP

AIO

Transmit/Receive Positive Channel 2

1

Ethernet TX/

RX Negative

Channel 2

RXN

AIO

Transmit/Receive Negative Channel 2

TABLE 2-5:

MISCELLANEOUS PINS

BUFFER

TYPE

Num PINs

NAME

SYMBOL

DESCRIPTION

1

External

Crystal

Input

XTAL1

ICLK

External crystal input

External

Clock Input

CLKIN

XTAL2

ICLK

Single-ended clock oscillator input.

Note: When using a single ended clock

oscillator, XTAL2 should be left

unconnected.

1

External

Crystal Out-

put

OCLK

External crystal output

1

External

Reset

nRST

nINT

VIS

(PU)

System reset. This signal is active low.

Interrupt Out-

put

VOD8

(PU)

Active low interrupt output. Place an external

resistor pull-up to VDDIO.

Note: Refer to Section 3.6, "Interrupt

Management," on page 24 for additional

details on device interrupts.

Note: Refer to Section 3.8.1.2, "nINTSEL and

LED2 Polarity Selection," on page 32 for

details on how the nINTSEL configuration

strap is used to determine the function of

this pin.

Reference

Clock Output

REFCLKO

VO8

This optional 50MHz clock output is derived from

the 25MHz crystal oscillator. REFCLKO is select-

able via the nINTSEL configuration strap.

Note: Refer Section 3.7.4.2, "REF_CLK Out

Mode," on page 29 for additional details.

Note: Refer to Section 3.8.1.2, "nINTSEL and

LED2 Polarity Selection," on page 32 for

details on how the nINTSEL configuration

strap is used to determine the function of

this pin.

DS00002165B-page 10

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LAN8720A/LAN8720AI

TABLE 2-6:

ANALOG REFERENCE PINS

BUFFER

TYPE

Num PINs

NAME

SYMBOL

DESCRIPTION

1

External 1%

Bias Resistor

Input

RBIAS

AI

This pin requires connection of a 12.1k ohm (1%)

resistor to ground.

Refer to the LAN8720A/LAN8720Ai reference

schematic for connection information.

Note: The nominal voltage is 1.2V and the

resistor will dissipate approximately 1mW

of power.

TABLE 2-7:

POWER PINS

NAME

BUFFER

TYPE

Num PINs

SYMBOL

DESCRIPTION

1

+1.6V to

+3.6V Vari-

able I/O

VDDIO

P

+1.6V to +3.6V variable I/O power

Refer to the LAN8720A/LAN8720Ai reference

schematic for connection information.

Power

1

+1.2V Digital

Core Power

Supply

VDDCR

P

Supplied by the on-chip regulator unless config-

ured for regulator off mode via the REGOFF con-

figuration strap.

Refer to the LAN8720A/LAN8720Ai reference

schematic for connection information.

Note: 1 uF and 470 pF decoupling capacitors in

parallel to ground should be used on this

pin.

1

+3.3V Chan-

nel 1 Analog

Port Power

VDD1A

VDD2A

P

+3.3V Analog Port Power to Channel 1

Refer to the LAN8720A/LAN8720Ai reference

schematic for connection information.

+3.3V Chan-

nel 2 Analog

Port Power

+3.3V Analog Port Power to Channel 2 and the

internal regulator.

Refer to the LAN8720A/LAN8720Ai reference

schematic for connection information.

1

Ground

VSS

P

Common ground. This exposed pad must be con-

nected to the ground plane with a via array.

2.1

Pin Assignments

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DS00002165B-page 11

LAN8720A/LAN8720AI

TABLE 2-8:

Pin NUM

24-QFN PACKAGE PIN ASSIGNMENTS

Pin Name

Pin NUM

Pin Name

1

2

VDD2A

LED2/nINTSEL

LED1/REGOFF

XTAL2

13

14

15

16

17

18

19

20

21

22

23

24

MDC

nINT/REFCLKO

nRST

3

4

TXEN

5

XTAL1/CLKIN

VDDCR

TXD0

6

TXD1

7

RXD1/MODE1

RXD0/MODE0

VDDIO

VDD1A

TXN

8

9

TXP

10

11

12

RXER/PHYAD0

CRS_DV/MODE2

MDIO

RXN

RXP

RBIAS

2.2

Buffer Types

TABLE 2-9:

BUFFER TYPES

BUFFER TYPE

DESCRIPTION

IS

O12

VIS

Schmitt-triggered input

Output with 12mA sink and 12mA source

Variable voltage Schmitt-triggered input

VO8

VOD8

PU

Variable voltage output with 8mA sink and 8mA source

Variable voltage open-drain output with 8mA sink

50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-

ups are always enabled.

Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on

internal resistors to drive signals external to the device. When connected to a load

that must be pulled high, an external resistor must be added.

PD

50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-

downs are always enabled.

Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely

on internal resistors to drive signals external to the device. When connected to a

load that must be pulled low, an external resistor must be added.

AI

Analog input

AIO

ICLK

Analog bi-directional

Crystal oscillator input pin

DS00002165B-page 12

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LAN8720A/LAN8720AI

TABLE 2-9:

BUFFER TYPES (CONTINUED)

BUFFER TYPE

DESCRIPTION

OCLK

P

Crystal oscillator output pin

Power pin

Note 2-5

The digital signals are not 5V tolerant. Refer to Section 5.1, "Absolute Maximum Ratings*," on

page 54 for additional buffer information.

Note 2-6

Sink and source capabilities are dependent on the VDDIO voltage. Refer to Section 5.1, "Absolute

Maximum Ratings*," on page 54 for additional information.

 2016 Microchip Technology Inc.

DS00002165B-page 13

LAN8720A/LAN8720AI

3.0

FUNCTIONAL DESCRIPTION

This chapter provides functional descriptions of the various device features. These features have been categorized into

the following sections:

• Transceiver

• Auto-negotiation

• HP Auto-MDIX Support

• MAC Interface

• Serial Management Interface (SMI)

• Interrupt Management

• Configuration Straps

• Miscellaneous Functions

• Application Diagrams

3.1

Transceiver

3.1.1

100BASE-TX TRANSMIT

The 100BASE-TX transmit data path is shown in Figure 3-1. Each major block is explained in the following subsections.

FIGURE 3-1:

100BASE-TX TRANSMIT DATA PATH

PLL

MAC

Ext Ref_CLK

4B/5B

Encoder

Scrambler

and PISO

25MHz

by 4 bits

25MHz by

5 bits

RMII 50Mhz by 2 bits

RMII

NRZI

Converter

MLT-3

Converter

Tx

Driver

125 Mbps Serial

NRZI

MLT-3

Magnetics

RJ45

CAT-5

3.1.1.1

100BASE-TX Transmit Data Across the RMII Interface

The MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data. The data is

latched by the transceiver’s RMII block on the rising edge of REF_CLK. The data is in the form of 2-bit wide 50MHz data.

3.1.1.2

4B/5B Encoding

The transmit data passes from the RMII block to the 4B/5B encoder. This block encodes the data from 4-bit nibbles to

5-bit symbols (known as “code-groups”) according to Table 3-1. Each 4-bit data-nibble is mapped to 16 of the 32 pos-

sible code-groups. The remaining 16 code-groups are either used for control information or are not valid.

The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The

remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /

I/, a transmit error code-group is /H/, etc.

DS00002165B-page 14

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

TABLE 3-1:

4B/5B CODE TABLE

SYM

CODE

GROUP

RECEIVER

TRANSMITTER

INTERPRETATION

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

11111

11000

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

I

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

DATA

—

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

DATA

—

IDLE

Sent after /T/R until TXEN

Sent for rising TXEN

J

First nibble of SSD, translated to “0101”

following IDLE, else RXER

10001

01101

K

T

Second nibble of SSD, translated to

“0101” following J, else RXER

Sent for rising TXEN

Sent for falling TXEN

First nibble of ESD, causes de-assertion

of CRS if followed by /R/, else assertion

of RXER

00111

R

Second nibble of ESD, causes deasser-

tion of CRS if following /T/, else assertion

of RXER

Sent for falling TXEN

00100

00110

11001

00000

00001

00010

00011

H

V

Transmit Error Symbol

Sent for rising TXER

INVALID

INVALID, RXER if during RXDV

INVALID

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DS00002165B-page 15

LAN8720A/LAN8720AI

TABLE 3-1:

4B/5B CODE TABLE (CONTINUED)

CODE

GROUP

RECEIVER

SYM

TRANSMITTER

INTERPRETATION

00101

01000

01100

10000

V

INVALID, RXER if during RXDV

INVALID

3.1.1.3

Scrambling

Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band

peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire

channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being

radiated by the physical wiring.

The seed for the scrambler is generated from the transceiver address, PHYAD, ensuring that in multiple-transceiver

applications, such as repeaters or switches, each transceiver will have its own scrambler sequence.

The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.

3.1.1.4

NRZI and MLT-3 Encoding

The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI

data stream. The NRZI is encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a

code bit “1” and the logic output remaining at the same level represents a code bit “0”.

3.1.1.5

100M Transmit Driver

The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on outputs TXP and

TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-T and 100BASE-TX signals pass

through the same transformer so that common “magnetics” can be used for both. The transmitter drives into the 100

impedance of the CAT-5 cable. Cable termination and impedance matching require external components.

3.1.1.6

100M Phase Lock Loop (PLL)

The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the

100BASE-TX transmitter.

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LAN8720A/LAN8720AI

3.1.2

100BASE-TX RECEIVE

The 100BASE-TX receive data path is shown in Figure 3-2. Each major block is explained in the following subsections.

FIGURE 3-2:

100BASE-TX RECEIVE DATA PATH

PLL

MAC

Ext Ref_CLK

25MHz

by 4 bits

25MHz by

5 bits

4B/5B

Descrambler

and SIPO

RMII 50Mhz by 2 bits

RMII

Decoder

125 Mbps Serial

DSP: Timing

recovery, Equalizer

and BLW Correction

NRZI

MLT-3

NRZI

Converter

MLT-3

Converter

MLT-3

A/D

Converter

Magnetics

RJ45

CAT-5

6 bit Data

3.1.2.1

100M Receive Input

The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADC

samples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quanitizer, it generates

6 digital bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels

such that the full dynamic range of the ADC can be used.

3.1.2.2

Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and ampli-

tude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer

can restore the signal for any good-quality CAT-5 cable between 1m and 150m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the iso-

lation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)

on the received signal will result. To prevent corruption of the received data, the transceiver corrects for BLW and can

receive the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP,

selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to

extract the serial data from the received signal.

3.1.2.3

NRZI and MLT-3 Decoding

The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an

NRZI data stream.

3.1.2.4

Descrambling

The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel

Out (SIPO) conversion of the data.

During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once

synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.

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Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbols

within a window of 4000 bytes (40us). This window ensures that a maximum packet size of 1514 bytes, allowed by the

IEEE 802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period,

receive operation is aborted and the descrambler re-starts the synchronization process.

3.1.2.5

Alignment

The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)

pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of

frame.

3.1.2.6

5B/4B Decoding

The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The translated data is pre-

sented on the RXD[1:0] signal lines. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC pre-

amble. Reception of the SSD causes the transceiver to assert the receive data valid signal, indicating that valid data is

available on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the End of

Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-assert

the carrier sense and receive data valid signals.

Note:

These symbols are not translated into data.

3.1.2.7

Receive Data Valid Signal

The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on the

RXD[1:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized and RXD

is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failure

or SIGDET becomes false.

RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface (MII

mode).

FIGURE 3-3:

RELATIONSHIP BETWEEN RECEIVED DATA AND SPECIFIC MII SIGNALS

J

K

5

D

Idle

data data data data

T

R

CLEAR-TEXT

RX_CLK

RX_DV

RXD

5

D

data data data data

3.1.2.8

Receiver Errors

During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0

through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER signal is asserted and arbitrary

data is driven onto the RXD[1:0] lines. Should an error be detected during the time that the /J/K/ delimiter is being

decoded (bad SSD error), RXER is asserted true and the value ‘1110’ is driven onto the RXD[1:0] lines. Note that the

Valid Data signal is not yet asserted when the bad SSD error occurs.

3.1.2.9

100M Receive Data Across the RMII Interface

The 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate of 50MHz.

The controller samples the data on the rising edge of XTAL1/CLKIN (REF_CLK). To ensure that the setup and hold

requirements are met, the nibbles are clocked out of the transceiver on the falling edge of XTAL1/CLKIN (REF_CLK).

3.1.3

10BASE-T TRANSMIT

Data to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit nibbles from the

MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchester-encoded

and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.

The 10M transmitter uses the following blocks:

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LAN8720A/LAN8720AI

• MII (digital)

• TX 10M (digital)

• 10M Transmitter (analog)

• 10M PLL (analog)

3.1.3.1

10M Transmit Data Across the RMII Interface

The MAC controller drives the transmit data onto the TXD bus. TXD[1:0] shall transition synchronously with respect to

REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the device. TXD[1:0] shall be “00” to

indicate idle when TXEN is deasserted. Values of TXD[1:0] other than “00” when TXEN is deasserted are reserved for

out-of-band signaling (to be defined). Values other than “00” on TXD[1:0] while TXEN is deasserted shall be ignored by

the device.TXD[1:0] shall provide valid data for each REF_CLK period while TXEN is asserted.

In order to comply with legacy 10BASE-T MAC/Controllers, in half-duplex mode the transceiver loops back the trans-

mitted data, on the receive path. This does not confuse the MAC/Controller since the COL signal is not asserted during

this time. The transceiver also supports the SQE (Heartbeat) signal.

3.1.3.2

Manchester Encoding

The 4-bit wide data is sent to the 10M TX block. The nibbles are converted to a 10Mbps serial NRZI data stream. The

10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester

encode the NRZ data stream. When no data is being transmitted (TXEN is low), the 10M TX block outputs Normal Link

Pulses (NLPs) to maintain communications with the remote link partner.

3.1.3.3

10M Transmit Drivers

The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out

as a differential signal across the TXP and TXN outputs.

3.1.4

10BASE-T RECEIVE

The 10BASE-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics. It recovers the

receive clock from the signal and uses this clock to recover the NRZI data stream. This 10M serial data is converted to

4-bit data nibbles which are passed to the controller via MII at a rate of 2.5MHz.

This 10M receiver uses the following blocks:

• Filter and SQUELCH (analog)

• 10M PLL (analog)

• RX 10M (digital)

• MII (digital)

3.1.4.1

10M Receive Input and Squelch

The Manchester signal from the cable is fed into the transceiver (on inputs RXP and RXN) via 1:1 ratio magnetics. It is

first filtered to reduce any out-of-band noise. It then passes through a SQUELCH circuit. The SQUELCH is a set of

amplitude and timing comparators that normally reject differential voltage levels below 300mV and detect and recognize

differential voltages above 585mV.

3.1.4.2

Manchester Decoding

The output of the SQUELCH goes to the 10M RX block where it is validated as Manchester encoded data. The polarity

of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice

versa), the condition is identified and corrected. The reversed condition is indicated by the XPOL bit of the Special Con-

trol/Status Indications Register. The 10M PLL is locked onto the received Manchester signal, from which the 20MHz

cock is generated. Using this clock, the Manchester encoded data is extracted and converted to a 10MHz NRZI data

stream. It is then converted from serial to 4-bit wide parallel data.

The 10M RX block also detects valid 10Base-T IDLE signals - Normal Link Pulses (NLPs) - to maintain the link.

3.1.4.3

10M Receive Data Across the RMII Interface

The 2-bit data nibbles are sent to the RMII block. These data nibbles are valid on the rising edge of the RMII REF_CLK.

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LAN8720A/LAN8720AI

3.1.4.4

Jabber Detection

Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length,

usually due to a fault condition, which results in holding the TXEN input for a long period. Special logic is used to detect

the jabber state and abort the transmission to the line within 45ms. Once TXEN is deasserted, the logic resets the jabber

condition.

As shown in Section 4.2.2, "Basic Status Register," on page 45, the Jabber Detect bit indicates that a jabber condition

was detected.

3.2

Auto-negotiation

The purpose of the auto-negotiation function is to automatically configure the transceiver to the optimum link parameters

based on the capabilities of its link partner. Auto-negotiation is a mechanism for exchanging configuration information

between two link-partners and automatically selecting the highest performance mode of operation supported by both

sides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification.

Once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the

Serial Management Interface (SMI). The results of the negotiation process are reflected in the Speed Indication bits of

the PHY Special Control/Status Register, as well as in the Auto Negotiation Link Partner Ability Register. The auto-nego-

tiation protocol is a purely physical layer activity and proceeds independently of the MAC controller.

The advertised capabilities of the transceiver are stored in the Auto Negotiation Advertisement Register. The default

advertised by the transceiver is determined by user-defined on-chip signal options.

The following blocks are activated during an Auto-negotiation session:

• Auto-negotiation (digital)

• 100M ADC (analog)

• 100M PLL (analog)

• 100M equalizer/BLW/clock recovery (DSP)

• 10M SQUELCH (analog)

• 10M PLL (analog)

• 10M Transmitter (analog)

When enabled, auto-negotiation is started by the occurrence of one of the following events:

• Hardware reset

• Software reset

• Power-down reset

• Link status down

• Setting the Restart Auto-Negotiate bit of the Basic Control Register

On detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of Fast Link Pulses

(FLP), which are bursts of link pulses from the 10M transmitter. They are shaped as Normal Link Pulses and can pass

uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered

pulses, which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent,

contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.

The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28.

In summary, the transceiver advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). It

advertises its technology ability according to the bits set in the Auto Negotiation Advertisement Register.

There are 4 possible matches of the technology abilities. In the order of priority these are:

• 100M Full Duplex (Highest Priority)

• 100M Half Duplex

• 10M Full Duplex

• 10M Half Duplex (Lowest Priority)

If the full capabilities of the transceiver are advertised (100M, Full Duplex), and if the link partner is capable of 10M and

100M, then auto-negotiation selects 100M as the highest performance mode. If the link partner is capable of half and

full duplex modes, then auto-negotiation selects full duplex as the highest performance operation.

DS00002165B-page 20

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LAN8720A/LAN8720AI

Once a capability match has been determined, the link code words are repeated with the acknowledge bit set. Any dif-

ference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation

will also re-start if not all of the required FLP bursts are received.

The capabilities advertised during auto-negotiation by the transceiver are initially determined by the logic levels latched

on the MODE[2:0] configuration straps after reset completes. These configuration straps can also be used to disable

auto-negotiation on power-up. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 30 for additional infor-

mation.

Writing the bits 8 through 5 of the Auto Negotiation Advertisement Register allows software control of the capabilities

advertised by the transceiver. Writing the Auto Negotiation Advertisement Register does not automatically re-start auto-

negotiation. The Restart Auto-Negotiate bit of the Basic Control Register must be set before the new abilities will be

advertised. Auto-negotiation can also be disabled via software by clearing the Auto-Negotiation Enable bit of the Basic

Control Register.

Note:

The device does not support “Next Page” capability.

3.2.1

PARALLEL DETECTION

If the LAN8720A/LAN8720Ai is connected to a device lacking the ability to auto-negotiate (for example, no FLPs are

detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses.

In this case the link is presumed to be half duplex per the IEEE standard. This ability is known as “Parallel Detection.”

This feature ensures interoperability with legacy link partners. If a link is formed via parallel detection, then the Link Part-

ner Auto-Negotiation Able bit of the Auto Negotiation Expansion Register is cleared to indicate that the Link Partner is

not capable of auto-negotiation. The controller has access to this information via the management interface. If a fault

occurs during parallel detection, the Parallel Detection Fault bit of Link Partner Auto-Negotiation Able is set.

Auto Negotiation Link Partner Ability Register is used to store the link partner ability information, which is coded in the

received FLPs. If the link partner is not auto-negotiation capable, then the Auto Negotiation Link Partner Ability Register

is updated after completion of parallel detection to reflect the speed capability of the link partner.

3.2.2

RESTARTING AUTO-NEGOTIATION

Auto-negotiation can be restarted at any time by setting the Restart Auto-Negotiate bit of the Basic Control Register.

Auto-negotiation will also restart if the link is broken at any time. A broken link is caused by signal loss. This may occur

because of a cable break, or because of an interruption in the signal transmitted by the link partner. Auto-negotiation

resumes in an attempt to determine the new link configuration.

If the management entity re-starts auto-negotiation by setting the Restart Auto-Negotiate bit of the Basic Control Reg-

ister, the LAN8720A/LAN8720Ai will respond by stopping all transmission/receiving operations. Once the break_link_-

timer is completed in the Auto-negotiation state-machine (approximately 1200ms), auto-negotiation will re-start. In this

case, the link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negoti-

ation.

3.2.3

DISABLING AUTO-NEGOTIATION

Auto-negotiation can be disabled by setting the Auto-Negotiation Enable bit of the Basic Control Register to zero. The

device will then force its speed of operation to reflect the information in the Basic Control Register (Speed Select bit and

Duplex Mode bit). These bits should be ignored when auto-negotiation is enabled.

3.2.4

HALF VS. FULL DUPLEX

Half duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle net-

work traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. If

data is received while the transceiver is transmitting, a collision results.

In full duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode, CRS responds

only to receive activity. The CSMA/CD protocol does not apply and collision detection is disabled.

3.3

HP Auto-MDIX Support

HP Auto-MDIX facilitates the use of CAT-3 (10BASE-T) or CAT-5 (100BASE-T) media UTP interconnect cable without

consideration of interface wiring scheme. If a user plugs in either a direct connect LAN cable, or a cross-over patch

cable, as shown in Figure 3-4, the device’s Auto-MDIX transceiver is capable of configuring the TXP/TXN and RXP/RXN

pins for correct transceiver operation.

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LAN8720A/LAN8720AI

The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX and TX line pairs

are interchangeable, special PCB design considerations are needed to accommodate the symmetrical magnetics and

termination of an Auto-MDIX design.

The Auto-MDIX function can be disabled via the AMDIXCTRL bit in the Special Control/Status Indications Register.

FIGURE 3-4:

DIRECT CABLE CONNECTION VS. CROSS-OVER CABLE CONNECTION

RJ-45 8-pin straight-through

for 10BASE-T/100BASE-TX

signaling

RJ-45 8-pin cross-over for

10BASE-T/100BASE-TX

signaling

TXP

TXN

TXP

TXN

TXP

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

TXN

2

3

4

5

6

7

8

RXP

Not Used

RXN

Not Used

RXN

Not Used

RXN

Not Used

RXN

Not Used

Direct Connect Cable

Cross-Over Cable

3.4

MAC Interface

3.4.1

RMII

The device supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet

transceivers and switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices

incorporating many MACs or transceiver interfaces such as switches, the number of pins can add significant cost as the

port counts increase. RMII reduces this pin count while retaining a management interface (MDIO/MDC) that is identical

to MII.

The RMII interface has the following characteristics:

• It is capable of supporting 10Mbps and 100Mbps data rates

• A single clock reference is used for both transmit and receive

• It provides independent 2-bit (di-bit) wide transmit and receive data paths

• It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes

The RMII includes the following interface signals (1 optional):

• transmit data - TXD[1:0]

• transmit strobe - TXEN

• receive data - RXD[1:0]

• receive error - RXER (Optional)

• carrier sense - CRS_DV

• Reference Clock - (RMII references usually define this signal as REF_CLK)

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LAN8720A/LAN8720AI

3.4.1.1

CRS_DV - Carrier Sense/Receive Data Valid

The CRS_DV is asserted by the device when the receive medium is non-idle. CRS_DV is asserted asynchronously on

detection of carrier due to the criteria relevant to the operating mode. In 10BASE-T mode when squelch is passed, or

in 100BASE-X mode when 2 non-contiguous zeros in 10 bits are detected, the carrier is said to be detected.

Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which presents the first

di-bit of a nibble onto RXD[1:0] (for example, CRS_DV is deasserted only on nibble boundaries). If the device has addi-

tional bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the device shall assert

CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of

REF_CLK which present the first di-bit of a nibble. The result is, starting on nibble boundaries, CRS_DV toggles at 25

MHz in 100Mbps mode and 2.5 MHz in 10Mbps mode when CRS ends before RXDV (for example, the FIFO still has

bits to transfer when the carrier event ends). Therefore, the MAC can accurately recover RXDV and CRS.

During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data on RXD[1:0] is

considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to

REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal decoding takes place.

3.4.1.2

Reference Clock (REF_CLK)

The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0]

and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path.

However, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device uses

elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK.

3.5

Serial Management Interface (SMI)

The Serial Management Interface is used to control the device and obtain its status. This interface supports registers 0

through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers 16 to 31 allowed by the

specification. Non-supported registers (such as 7 to 15) will be read as hexadecimal “FFFF”. Device registers are

detailed in Section 4.0, "Register Descriptions," on page 43.

At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock provided by the

station management controller (SMC). MDIO is a bi-directional data SMI input/output signal that receives serial data

(commands) from the controller SMC and sends serial data (status) to the SMC. The minimum time between edges of

the MDC is 160 ns. There is no maximum time between edges. The minimum cycle time (time between two consecutive

rising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easily

driven by the I/O port of a microcontroller.

The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing of the data is shown

in Figure 3-5 and Figure 3-6. The timing relationships of the MDIO signals are further described in Section 5.5.6, "SMI

Timing," on page 64.

FIGURE 3-5:

MDIO TIMING AND FRAME STRUCTURE - READ CYCLE

Read Cycle

MDC

...

D1

D15 D14

D0

32 1's

Preamble

0

1

0

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

MDIO

Start of

Frame

OP

Code

Turn

Around

PHY Address

Data To Phy

Register Address

Data

Data From Phy

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LAN8720A/LAN8720AI

FIGURE 3-6:

MDIO TIMING AND FRAME STRUCTURE - WRITE CYCLE

Write Cycle

MDC

...

D15 D14

D1

D0

32 1's

Preamble

0

1

0

1

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

MDIO

Start of

Frame

OP

Code

Turn

Around

PHY Address

Register Address

Data

Data To Phy

3.6

Interrupt Management

The device management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. This

interrupt capability generates an active low asynchronous interrupt signal on the nINT output whenever certain events

are detected as setup by the Interrupt Mask Register.

The device’s interrupt system provides two modes, a Primary Interrupt mode and an Alternative interrupt mode. Both

systems will assert the nINT pin low when the corresponding mask bit is set. These modes differ only in how they de-

assert the nINT interrupt output. These modes are detailed in the following subsections.

Note:

The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative

interrupt mode requires setup after a power-up or hard reset.

3.6.1

PRIMARY INTERRUPT SYSTEM

The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status Register is “0”). The

Primary interrupt system is always selected after power-up or hard reset. In this mode, to set an interrupt, set the cor-

responding mask bit in the Interrupt Mask Register (see Table 3-3). Then when the event to assert nINT is true, the nINT

output will be asserted. When the corresponding event to deassert nINT is true, then the nINT will be de-asserted.

TABLE 3-2:

Mask

INTERRUPT MANAGEMENT TABLE

Event to Assert

nINT

Event to

De-Assert nINT

Interrupt Source Flag

Interrupt Source

30.7

30.6

29.7

ENERGYON

17.1

ENERGYON

Rising 17.1

(Note 3-3)

Falling 17.1 or

Reading register 29

29.6

Auto-Negotiation

complete

1.5

Auto-Negotiate

Complete

Rising 1.5

Falling 1.5 or

Reading register 29

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TABLE 3-2:

INTERRUPT MANAGEMENT TABLE

30.5

29.5

Remote Fault

Detected

1.4

Remote Fault

Rising 1.4

Falling 1.4, or

Reading register 1 or

Reading register 29

30.4

30.3

30.2

29.4

29.3

29.2

Link Down

1.2

5.14

6.4

Link Status

Falling 1.2

Rising 5.14

Rising 6.4

Reading register 1 or

Reading register 29

Auto-Negotiation

LP Acknowledge

Acknowledge

Falling 5.14 or

Read register 29

Parallel Detection

Fault

Parallel Detec-

tion Fault

Falling 6.4 or

Reading register 6, or

Reading register 29

or

Re-Auto Negotiate or

Link down

30.1

29.1

Auto-Negotiation

Page Received

6.1

Page Received

Rising 6.1

Falling of 6.1 or

Reading register 6, or

Reading register 29

Re-Auto Negotiate, or

Link Down.

Note 3-1

Note:

If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will

assert for 256 ms, approximately one second after ENERGYON goes low when the Cable is

unplugged. To prevent an unexpected assertion of nINT, the ENERGYON interrupt mask should

always be cleared as part of the ENERGYON interrupt service routine.

The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the signal acqui-

sition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a ‘1’ at power-up. If no

signal is present, then both ENERGYON and INT7 will clear within a few milliseconds.

3.6.2

ALTERNATE INTERRUPT SYSTEM

The Alternate interrupt system is enabled by setting the ALTINT bit of the Mode Control/Status Register to “1”. In this

mode, to set an interrupt, set the corresponding bit of the in the Mask Register 30, (see Table 3-4). To Clear an interrupt,

either clear the corresponding bit in the Interrupt Mask Register to deassert the nINT output, or clear the interrupt

source, and write a ‘1’ to the corresponding Interrupt Source Flag. Writing a ‘1’ to the Interrupt Source Flag will cause

the state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If

the Condition to deassert is true, then the Interrupt Source Flag is cleared and nINT is also deasserted. If the Condition

to deassert is false, then the Interrupt Source Flag remains set, and the nINT remains asserted.

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DS00002165B-page 25

LAN8720A/LAN8720AI

For example, setting the INT7 bit in the Interrupt Mask Register will enable the ENERGYON interrupt. After a cable is

plugged in, the ENERGYON bit in the Mode Control/Status Register goes active and nINT will be asserted low. To de-

assert the nINT interrupt output, either clear the ENERGYON bit in the Mode Control/Status Register by removing the

cable and then writing a ‘1’ to the INT7 bit in the Interrupt Mask Register, OR clear the INT7 mask (bit 7 of the Interrupt

Mask Register).

TABLE 3-3:

Mask

ALTERNATIVE INTERRUPT SYSTEM MANAGEMENT TABLE

Bit to

Clear

nINT

Event to

Condition to

Interrupt Source Flag

Interrupt Source

Assert nINT

De-Assert

30.7

30.6

29.7 ENERGYON

17.1 ENERGYON

Rising 17.1

Rising 1.5

17.1 low

1.5 low

29.7

29.6

29.6 Auto-Negotiation

complete

1.5

1.4

1.2

Auto-Negotiate

Complete

30.5

29.5 Remote Fault

Detected

Remote Fault

Rising 1.4

1.4 low

29.5

30.4

30.3

29.4 Link Down

Link Status

Falling 1.2

Rising 5.14

1.2 high

5.14 low

29.4

29.3

29.3 Auto-Negotiation

LP Acknowledge

5.14 Acknowledge

30.2

30.1

29.2 Parallel Detec-

tion Fault

6.4

6.1

Parallel Detec-

tion Fault

Rising 6.4

Rising 6.1

6.4 low

6.1 low

29.2

29.1

29.1 Auto-Negotiation

Page Received

Note:

The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the signal acqui-

sition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a ‘1’ at power-up. If no

signal is present, then both ENERGYON and INT7 will clear within a few milliseconds.

3.7

Configuration Straps

Configuration straps allow various features of the device to be automatically configured to user defined values. Config-

uration straps are latched upon Power-On Reset (POR) and pin reset (nRST). Configuration straps include internal

resistors in order to prevent the signal from floating when unconnected. If a particular configuration strap is connected

to a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that it

reaches the required voltage level prior to latching. The internal resistor can also be overridden by the addition of an

external resistor.

Note 3-2

The system designer must guarantee that configuration strap pins meet the timing requirements

specified in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page 59. If

configuration strap pins are not at the correct voltage level prior to being latched, the device may

capture incorrect strap values.

Note 3-3

When externally pulling configuration straps high, the strap should be tied to VDDIO, except for

REGOFF and nINTSEL which should be tied to VDD2A.

3.7.1

PHYAD[0]: PHY ADDRESS CONFIGURATION

The PHYAD0 bit is driven high or low to give each PHY a unique address. This address is latched into an internal register

at the end of a hardware reset (default = 0b). In a multi-PHY application (such as a repeater), the controller is able to

manage each PHY via the unique address. Each PHY checks each management data frame for a matching address in

the relevant bits. When a match is recognized, the PHY responds to that particular frame. The PHY address is also used

to seed the scrambler. In a multi-PHY application, this ensures that the scramblers are out of synchronization and dis-

perses the electromagnetic radiation across the frequency spectrum.

DS00002165B-page 26

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LAN8720A/LAN8720AI

The device’s SMI address may be configured using hardware configuration to either the value 0 or 1. The user can con-

figure the PHY address using Software Configuration if an address greater than 1 is required. The PHY address can be

written (after SMI communication at some address is established) using the PHYAD bits of the Special Modes Register.

The PHYAD0 hardware configuration strap is multiplexed with the RXER pin.

3.7.2

MODE[2:0]: MODE CONFIGURATION

The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the nRST pin is deas-

serted, the register bit values are loaded according to the MODE[2:0] configuration straps. The 10/100 digital block is

then configured by the register bit values. When a soft reset occurs via the Soft Reset bit of the Basic Control Register,

the configuration of the 10/100 digital block is controlled by the register bit values and the MODE[2:0] configuration

straps have no affect.

The device’s mode may be configured using the hardware configuration straps as summarized in Table 3-6. The user

may configure the transceiver mode by writing the SMI registers.

TABLE 3-4:

MODE[2:0] BUS

Default Register Bit Values

MODE[2:0]

Mode Definitions

Register 0

Register 4

[8,7,6,5]

[13,12,10,8]

000

001

010

10Base-T Half Duplex. Auto-negotiation disabled.

10Base-T Full Duplex. Auto-negotiation disabled.

0000

0001

1000

N/A

100Base-TX Half Duplex. Auto-negotiation dis-

abled.

CRS is active during Transmit & Receive.

011

100

100Base-TX Full Duplex. Auto-negotiation disabled.

CRS is active during Receive.

1001

1100

N/A

100Base-TX Half Duplex is advertised. Auto-negoti-

ation enabled.

0100

CRS is active during Transmit & Receive.

101

110

Repeater mode. Auto-negotiation enabled.

100Base-TX Half Duplex is advertised.

CRS is active during Receive.

1100

N/A

0100

N/A

Power Down mode. In this mode the transceiver will

wake-up in Power-Down mode. The transceiver

cannot be used when the MODE[2:0] bits are set to

this mode. To exit this mode, the MODE bits in Reg-

ister 18.7:5(see Section 4.2.9, "Special Modes Reg-

ister," on page 50) must be configured to some

other value and a soft reset must be issued.

111

All capable. Auto-negotiation enabled.

X10X

1111

The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in Table 3-5.

TABLE 3-5:

MODE Bit

PIN NAMES FOR MODE BITS

Pin Name

MODE[0]

MODE[1]

RXD0/MODE0

RXD1/MODE1

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DS00002165B-page 27

LAN8720A/LAN8720AI

TABLE 3-5:

PIN NAMES FOR MODE BITS

MODE Bit

Pin Name

MODE[2]

CRS_DV/MODE2

3.7.3

REGOFF: INTERNAL +1.2V REGULATOR CONFIGURATION

The incorporation of flexPWR technology provides the ability to disable the internal +1.2V regulator. When the regulator

is disabled, an external +1.2V must be supplied to the VDDCR pin. Disabling the internal +1.2V regulator makes it pos-

sible to reduce total system power, since an external switching regulator with greater efficiency (versus the internal linear

regulator) can be used to provide +1.2V to the transceiver circuitry.

Note:

Because the REGOFF configuration strap shares functionality with the LED1 pin, proper consideration must

also be given to the LED polarity. Refer to Section 3.8.1.1, "REGOFF and LED1 Polarity Selection," on

page 33 for additional information on the relation between REGOFF and the LED1 polarity.

3.7.3.1

Disabling the Internal +1.2V Regulator

To disable the +1.2V internal regulator, a pull-up strapping resistor should be connected from the REGOFF configuration

strap to VDD2A. At power-on, after both VDDIO and VDD2A are within specification, the transceiver will sample

REGOFF to determine whether the internal regulator should turn on. If the pin is sampled at a voltage greater than V_IH,

then the internal regulator is disabled and the system must supply +1.2V to the VDDCR pin. The VDDIO voltage must

be at least 80% of the operating voltage level (1.44V when operating at 1.8V, 2.0V when operating at 2.5V, 2.64V when

operating at 3.3V) before voltage is applied to VDDCR. As described in Section 3.7.4.2, when REGOFF is left floating

or connected to VSS, the internal regulator is enabled and the system is not required to supply +1.2V to the VDDCR pin.

3.7.3.2

Enabling the Internal +1.2V Regulator

The +1.2V for VDDCR is supplied by the on-chip regulator unless the transceiver is configured for the regulator off mode

using the REGOFF configuration strap as described in Section 3.7.4.1. By default, the internal +1.2V regulator is

enabled when REGOFF is floating (due to the internal pull-down resistor). During power-on, if REGOFF is sampled

below V_IL, then the internal +1.2V regulator will turn on and operate with power from the VDD2A pin.

3.7.4

NINTSEL: NINT/REFCLKO CONFIGURATION

The nINTSEL configuration strap is used to select between one of two available modes: REF_CLK In Mode (nINT) and

REF_CLK Out Mode. The configured mode determines the function of the nINT/REFCLKO pin. The nINTSEL configu-

ration strap is latched at POR and on the rising edge of the nRST. By default, nINTSEL is configured for nINT mode via

the internal pull-up resistor.

TABLE 3-6:

NINTSEL CONFIGURATION

Strap Value

Mode

REF_CLK description

nINTSEL = 0

nINTSEL = 1

REF_CLK Out Mode

REF_CLK In Mode

nINT/REFCLKO is the source of REF_CLK.

nINT/REFCLKO is an active low interrupt output. 

The REF_CLK is sourced externally and must be driven

on the XTAL1/CLKIN pin.

The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0]

and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path.

However, on the receive data path, the receiver recovers the clock from the incoming data stream. The device uses

elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK.

In REF_CLK In Mode, the 50MHz REF_CLK is driven on the XTAL1/CLKIN pin. This is the traditional system configu-

ration when using RMII, and is described in Section 3.7.4.1. When configured for REF_CLK Out Mode, the device gen-

erates the 50MHz RMII REF_CLK and the nINT interrupt is not available. REF_CLK Out Mode allows a low-cost 25MHz

crystal to be used as the reference for REF_CLK. This configuration may result in reduced system cost and is described

in Section 3.7.4.2.

DS00002165B-page 28

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

Note:

Because the nINTSEL configuration strap shares functionality with the LED2 pin, proper consideration must

also be given to the LED polarity. Refer to Section 3.8.1.2, "nINTSEL and LED2 Polarity Selection," on

page 33 for additional information on the relation between nINTSEL and the LED2 polarity.

3.7.4.1

REF_CLK In Mode

In REF_CLK In Mode, the 50MHz REF_CLK is driven on the XTAL1/CLKIN pin. A 50MHz source for REF_CLK must

be available external to the device when using this mode. The clock is driven to both the MAC and PHY as shown in

Figure 3-7.

FIGURE 3-7:

EXTERNAL 50MHZ CLOCK SOURCES THE REF_CLK

LAN8720A/LAN8720Ai

10/100 PHY

24-QFN

RMII

MAC

RMII

MDIO

MDC

nINT

Accepts external

50MHz clock

Mag

RJ45

TXD[1:0]

TXP

TXN

2

TXEN

RXP

RXN

RXD[1:0]

CRS_DV

RXER

REF_CLK

All RMII signals are

synchronous to the supplied

clock

XTAL1/CLKIN

XTAL2

LED[2:1]

nRST

2

Interface

50MHz

Reference

Clock

3.7.4.2

REF_CLK Out Mode

To reduce BOM cost, the device includes a feature to generate the RMII REF_CLK signal from a low-cost, 25MHz fun-

damental crystal. This type of crystal is inexpensive in comparison to 3^rdovertone crystals that would normally be

required for 50MHz. The MAC must be capable of operating with an external clock to take advantage of this feature as

shown in Figure 3-8.

In order to optimize package size and cost, the REFCLKO pin is multiplexed with the nINT pin. In REF_CLK Out mode,

the nINT functionality is disabled to accommodate usage of REFCLKO as a 50MHz clock to the MAC.

Note:

The REF_CLK Out Mode is not part of the RMII Specification. Timing in this mode is not compliant with the

RMII specification. To ensure proper system operation, a timing analysis of the MAC and LAN8720 must be

performed.

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DS00002165B-page 29

LAN8720A/LAN8720AI

FIGURE 3-8:

SOURCING REF_CLK FROM A 25MHZ CRYSTAL

Note: nINT not available in

this configuration

LAN8720A/LAN8720Ai

10/100 PHY

MAC

RMII

MDIO

MDC

Capable of

accepting 50MHz

clock

24-QFN

TXD[1:0]

RMII

2

TXEN

Mag

RJ45

RXD[1:0]

TXP

TXN

CRS_DV

RXER

RXP

RXN

REF_CLK

REFCLKO

XTAL1/CLKIN

XTAL2

LED[2:1]

nRST

25MHz

2

Interface

In some system architectures, a 25MHz clock source is available. The device can be used to generate the REF_CLK

to the MAC as shown in FIGURE 3-9:. It is important to note that in this specific example, only a 25MHz clock can be

used (clock cannot be 50MHz). Similar to the 25MHz crystal mode, the nINT function is disabled.

DS00002165B-page 30

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

FIGURE 3-9:

SOURCING REF_CLK FROM EXTERNAL 25MHZ SOURCE

Note: nINT is not available in

this configuration

LAN8720A/LAN8720Ai

10/100 PHY

24-QFN

MAC

RMII

MDIO

MDC

Capable of

accepting 50MHz

clock

TXD[1:0]

Mag

RJ45

2

TXP

TXN

TXEN

RXD[1:0]

RXP

RXN

CRS_DV

RXER

REF_CLK

REFCLKO

LED[2:1]

25MHz

Clock

XTAL1/CLKIN

XTAL2

2

nRST

Interface

3.8

Miscellaneous Functions

3.8.1

LEDS

Two LED signals are provided as a convenient means to determine the transceiver's mode of operation. All LED signals

are either active high or active low as described in Section 3.8.1.2, "nINTSEL and LED2 Polarity Selection" and Section

3.8.1.1, "REGOFF and LED1 Polarity Selection," on page 33.

The LED1 output is driven active whenever the device detects a valid link, and blinks when CRS is active (high) indicat-

ing activity.

The LED2 output is driven active when the operating speed is 100Mbps. This LED will go inactive when the operating

speed is 10Mbps or during line isolation.

Note:

When pulling the LED1 and LED2 pins high, they must be tied to VDD2A, NOT VDDIO.

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DS00002165B-page 31

LAN8720A/LAN8720AI

3.8.1.1

REGOFF and LED1 Polarity Selection

The REGOFF configuration strap is shared with the LED1 pin. The LED1 output will automatically change polarity based

on the presence of an external pull-up resistor. If the LED1 pin is pulled high to VDD2A by an external pull-up resistor

to select a logical high for REGOFF, then the LED1 output will be active low. If the LED1 pin is pulled low by the internal

pull-down resistor to select a logical low for REGOFF, the LED1 output will then be an active high output. Figure 3-7

details the LED1 polarity for each REGOFF configuration.

FIGURE 3-10:

LED1/REGOFF POLARITY CONFIGURATION

REGOFF = 1 (Regulator OFF)

LED output = Active Low

REGOFF = 0 (Regulator ON)

LED output = Active High

VDD2A

LED1/REGOFF

10K

~270 ohms

LED1/REGOFF

Note:

Refer to Section 3.7.4, "REGOFF: Internal +1.2V Regulator Configuration," on page 32 for additional infor-

mation on the REGOFF configuration strap.

3.8.1.2

nINTSEL and LED2 Polarity Selection

The nINTSEL configuration strap is shared with the LED2 pin. The LED2 output will automatically change polarity based

on the presence of an external pull-down resistor. If the LED2 pin is pulled high to VDD2A to select a logical high for

nINTSEL, then the LED2 output will be active low. If the LED2 pin is pulled low by an external pull-down resistor to select

a logical low for nINTSEL, the LED2 output will then be an active high output. Figure 3-8 details the LED2 polarity for

each nINTSEL configuration.

FIGURE 3-11:

LED2/NINTSEL POLARITY CONFIGURATION

nINTSEL = 1

LED output = Active Low

nINTSEL = 0

LED output = Active High

VDD2A

LED2/nINTSEL

10K

~270 ohms

LED2/nINTSEL

Note:

Refer to Section 3.7.5, "nINTSEL: nINT/TXER/TXD4 Configuration," on page 32 for additional information

on the nINTSEL configuration strap.

DS00002165B-page 32

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

3.8.2

VARIABLE VOLTAGE I/O

The device’s digital I/O pins are variable voltage, allowing them to take advantage of low power savings from shrinking

technologies. These pins can operate from a low I/O voltage of +1.62V up to +3.6V. The applied I/O voltage must main-

tain its value with a tolerance of ± 10%. Varying the voltage up or down after the transceiver has completed power-on

reset can cause errors in the transceiver operation. Refer to Section 5.0, "Operational Characteristics," on page 54 for

additional information.

Note:

Input signals must not be driven high before power is applied to the device.

3.8.3

POWER-DOWN MODES

There are two device power-down modes: General Power-Down Mode and Energy Detect Power-Down Mode. These

modes are described in the following subsections.

3.8.3.1

General Power-Down

This power-down mode is controlled via the Power Down bit of the Basic Control Register. In this mode, the entire trans-

ceiver (except the management interface) is powered-down and remains in this mode as long as the Power Down bit is

“1”. When the Power Down bit is cleared, the transceiver powers up and is automatically reset.

3.8.3.2

Energy Detect Power-Down

This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status Register. In this mode,

when no energy is present on the line the transceiver is powered down (except for the management interface, the

SQUELCH circuit, and the ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energy

from 100BASE-TX, 10BASE-T, or Auto-negotiation signals.

In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the transceiver is powered-down

and nothing is transmitted. When energy is received via link pulses or packets, the ENERGYON bit goes high and the

transceiver powers-up. The device automatically resets into the state prior to power-down and asserts the nINT interrupt

if the ENERGYON interrupt is enabled in the Interrupt Mask Register. The first and possibly the second packet to acti-

vate ENERGYON may be lost.

When the EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is disabled.

3.8.4

ISOLATE MODE

The device data paths may be electrically isolated from the RMII interface by setting the Isolate bit of the Basic Control

Register to “1”. In isolation mode, the transceiver does not respond to the TXD, TXEN and TXER inputs, but does

respond to management transactions.

Isolation provides a means for multiple transceivers to be connected to the same RMII interface without contention. By

default, the transceiver is not isolated (on power-up (Isolate=0).

3.8.5

RESETS

The device provides two forms of reset: Hardware and Software. The device registers are reset by both Hardware and

Software resets. Select register bits, indicated as “NASR” in the register definitions, are not cleared by a Software reset.

The registers are not reset by the power-down modes described in Section 3.8.3.

Note:

For the first 16us after coming out of reset, the RMII interface will run at 2.5 MHz. After this time, it will switch

to 25 MHz if auto-negotiation is enabled.

3.8.5.1

Hardware Reset

A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum

time detailed in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page 59 to ensure a proper trans-

ceiver reset. During a Hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal.

Note:

A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.5.3, "Power-On nRST

& Configuration Strap Timing," on page 59 for additional information.

3.8.5.2

Software Reset

A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All registers bits, except

those indicated as “NASR” in the register definitions, are cleared by a Software reset. The Soft Reset bit is self-clearing.

Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset process will be completed within 0.5s from the setting

of this bit.

 2016 Microchip Technology Inc.

DS00002165B-page 33

LAN8720A/LAN8720AI

3.8.6

CARRIER SENSE

The carrier sense (CRS) is output on the CRS_DV pin. CRS is a signal defined by the MII specification in the IEEE

802.3u standard. The device asserts CRS based only on receive activity whenever the transceiver is either in repeater

mode or full-duplex mode. Otherwise the transceiver asserts CRS based on either transmit or receive activity.

The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It activates carrier

sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier sense terminates if a span of 10 con-

secutive ones is detected before a /J/K/ Start-of Stream Delimiter pair. If an SSD pair is detected, carrier sense is

asserted until either /T/R/ End–of-Stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after

the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE

followed by some non-IDLE symbol.

3.8.7

LINK INTEGRITY TEST

The device performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram.

The link status is multiplexed with the 10Mbps link status to form the Link Status bit in the Basic Status Register and to

drive the LINK LED (LED1).

The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the ANSI X3.263 TP-

PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID signal. When DATA_VALID is

asserted, the control logic moves into a Link-Ready state and waits for an enable from the auto-negotiation block. When

received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should auto-negoti-

ation be disabled, the link integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.

To allow the line to stabilize, the link integrity logic will wait a minimum of 330 sec from the time DATA_VALID is

asserted until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will

immediately negate the Link signal and enter the Link-Down state.

When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T receiver logic.

3.8.8

LOOPBACK OPERATION

The device may be configured for near-end loopback and far loopback. These loopback modes are detailed in the fol-

lowing subsections.

3.8.8.1

Near-end Loopback

Near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indi-

cated by the blue arrows in Figure 3-9. The near-end loopback mode is enabled by setting the Loopback bit of the Basic

Control Register to “1”. A large percentage of the digital circuitry is operational in near-end loopback mode because data

is routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The transmitters are powered

down regardless of the state of TXEN.

FIGURE 3-12:

NEAR-END LOOPBACK BLOCK DIAGRAM

TXD

TX

RX

10/100

Ethernet

MAC

X

CAT-5

XFMR

RXD

X

Digital

Analog

SMSC

Ethernet Transceiver

DS00002165B-page 34

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

3.8.8.2

Far Loopback

Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in Figure 3-11. The far

loopback mode is enabled by setting the FARLOOPBACK bit of the Mode Control/Status Register to “1”. In this mode,

data that is received from the link partner on the MDI is looped back out to the link partner. The digital interface signals

on the local MAC interface are isolated.

FIGURE 3-13:

FAR LOOPBACK BLOCK DIAGRAM

Far-end system

TXD

TX

RX

10/100

Ethernet

MAC

X

Link

Partner

CAT-5

XFMR

^RXDX

Digital

Analog

SMSC

Ethernet Transceiver

3.8.8.3

Connector Loopback

The device maintains reliable transmission over very short cables, and can be tested in a connector loopback as shown

in Figure 3-11. An RJ45 loopback cable can be used to route the transmit signals an the output of the transformer back

to the receiver inputs, and this loopback will work at both 10 and 100.

FIGURE 3-14:

CONNECTOR LOOPBACK BLOCK DIAGRAM

1

2

3

4

5

6

7

8

TXD

RXD

TX

RX

10/100

Ethernet

MAC

XFMR

Digital

Analog

RJ45 Loopback Cable.

Created by connecting pin 1 to pin 3

and connecting pin 2 to pin 6.

SMSC

Ethernet Transceiver

3.9

Application Diagrams

This section provides typical application diagrams for the following:

• Simplified System Level Application Diagram

• Power Supply Diagram (1.2V Supplied by Internal Regulator)

• Power Supply Diagram (1.2V Supplied by External Source)

• Twisted-Pair Interface Diagram (Single Power Supply)

• Twisted-Pair Interface Diagram (Dual Power Supplies)

 2016 Microchip Technology Inc.

DS00002165B-page 35

LAN8720A/LAN8720AI

3.9.1

SIMPLIFIED SYSTEM LEVEL APPLICATION DIAGRAM

FIGURE 3-15:

SIMPLIFIED SYSTEM LEVEL APPLICATION DIAGRAM

LAN8720A/LAN8720Ai

10/100 PHY

24-QFN

RMII

MDIO

MDC

nINT

Mag

RJ45

TXP

TXN

TXD[1:0]

2

RXP

RXN

TXEN

RXD[1:0]

RXER

XTAL1/CLKIN

XTAL2

LED[2:1]

25MHz

2

nRST

Interface

DS00002165B-page 36

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

3.9.2

POWER SUPPLY DIAGRAM (1.2V SUPPLIED BY INTERNAL REGULATOR)

FIGURE 3-16:

POWER SUPPLY DIAGRAM (1.2V SUPPLIED BY INTERNAL REGULATOR)

LAN8720A/LAN8720Ai

Power

Supply

3.3V

24-QFN

Ch.2 3.3V

Core Logic

Circuitry

VDDCR

VDDIO

Internal

Regulator

VDD2A

OUT

IN

1 uF

470 pF

C_BYPASS

VDDDIO

Supply

1.8 - 3.3V

VDD1A

RBIAS

Ch.1 3.3V

Circuitry

C_BYPASS

C_F

C_BYPASS

LED1/

REGOFF

12.1k

VSS

~270 Ohm

 2016 Microchip Technology Inc.

DS00002165B-page 37

LAN8720A/LAN8720AI

3.9.3

POWER SUPPLY DIAGRAM (1.2V SUPPLIED BY EXTERNAL SOURCE)

FIGURE 3-17:

POWER SUPPLY DIAGRAM (1.2V SUPPLIED BY EXTERNAL SOURCE)

LAN8720A/LAN8720Ai

Power

Supply

3.3V

24-QFN

Ch.2 3.3V

Core Logic

Circuitry

VDDCR

Supply

1.2V

Internal

Regulator

(Disabled)

VDDCR

VDDIO

VDD2A

OUT

IN

1 uF

470 pF

C_BYPASS

VDDDIO

Supply

1.8 - 3.3V

VDD1A

RBIAS

Ch.1 3.3V

Circuitry

C_BYPASS

C_F

C_BYPASS

LED1/

REGOFF

12.1k

VSS

~270 Ohm

10k

DS00002165B-page 38

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

3.9.4

TWISTED-PAIR INTERFACE DIAGRAM (SINGLE POWER SUPPLY)

FIGURE 3-18:

TWISTED-PAIR INTERFACE DIAGRAM (SINGLE POWER SUPPLY)

Ferrite

bead

LAN8720A/LAN8720Ai

24-QFN

Power

Supply

3.3V

49.9 Ohm Resistors

VDD2A

VDD1A

TXP

C_BYPASS

Magnetics

RJ45

1

2

3

4

5

6

7

8

75

TXN

RXP

RXN

1000 pF

3 kV

C_BYPASS

 2016 Microchip Technology Inc.

DS00002165B-page 39

LAN8720A/LAN8720AI

3.9.5

TWISTED-PAIR INTERFACE DIAGRAM (DUAL POWER SUPPLIES)

FIGURE 3-19:

TWISTED-PAIR INTERFACE DIAGRAM (DUAL POWER SUPPLIES)

LAN8720A/LAN8720Ai

Power

Supply

3.3V

Power

Supply

2.5V - 3.3V

49.9 Ohm Resistors

24-QFN

VDD2A

VDD1A

TXP

C_BYPASS

Magnetics

RJ45

1

2

3

4

5

6

7

8

75

TXN

RXP

RXN

1000 pF

3 kV

C_BYPASS

DS00002165B-page 40

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

4.0

REGISTER DESCRIPTIONS

This chapter describes the various control and status registers (CSRs). All registers follow the IEEE 802.3 (clause

22.2.4) management register set. All functionality and bit definitions comply with these standards. The IEEE 802.3 spec-

ified register index (in decimal) is included with each register definition, allowing for addressing of these registers via

the Serial Management Interface (SMI) protocol.

4.1

Register Nomenclature

Table 4-1 describes the register bit attribute notation used throughout this document.

TABLE 4-1:

REGISTER BIT TYPES

Register Bit Type

Register Bit Description

Notation

R

W

Read: A register or bit with this attribute can be read.

Read: A register or bit with this attribute can be written.

Read only: Read only. Writes have no effect.

RO

WO

WC

WAC

RC

LL

Write only: If a register or bit is write-only, reads will return unspecified data.

Write One to Clear: writing a one clears the value. Writing a zero has no effect

Write Anything to Clear: writing anything clears the value.

Read to Clear: Contents is cleared after the read. Writes have no effect.

Latch Low: Clear on read of register.

LH

Latch High: Clear on read of register.

SC

Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no

effect. Contents can be read.

SS

Self-Setting: Contents are self-setting after being cleared. Writes of one have no

effect. Contents can be read.

RO/LH

Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After it

is read, the bit will either remain high if the high condition remains, or will go low if the

high condition has been removed. If the bit has not been read, the bit will remain high

regardless of a change to the high condition. This mode is used in some Ethernet PHY

registers.

NASR

Not Affected by Software Reset. The state of NASR bits do not change on assertion

of a software reset.

RESERVED

Reserved Field: Reserved fields must be written with zeros to ensure future compati-

bility. The value of reserved bits is not guaranteed on a read.

Many of these register bit notations can be combined. Some examples of this are shown below:

• R/W: Can be written. Will return current setting on a read.

• R/WAC: Will return current setting on a read. Writing anything clears the bit.

4.2

Control and Status Registers

Table 4-2 provides a list of supported registers. Register details, including bit definitions, are provided in the proceeding

subsections.

 2016 Microchip Technology Inc.

DS00002165B-page 41

LAN8720A/LAN8720AI

TABLE 4-2:

SMI REGISTER MAP

Register Index

Register Name

Basic Control Register

Group

(Decimal)

0

1

Basic

Basic Status Register

Basic

2

PHY Identifier 1

Extended

3

PHY Identifier 2

Extended

4

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Mode Control/Status Register

Special Modes

Extended

5

Extended

6

Extended

17

18

26

27

29

30

31

Vendor-specific

Symbol Error Counter Register

Control / Status Indication Register

Interrupt Source Register

Interrupt Mask Register

PHY Special Control/Status Register

4.2.1

BASIC CONTROL REGISTER

Index (In Decimal):

0

Size:

16 bits

Bits

Description

Type

Default

15

Soft Reset

R/W

SC

0b

1 = software reset. Bit is self-clearing. When setting this bit do not set other

bits in this register. The configuration (as described in Section 3.7.2,

MODE[2:0]: Mode Configuration) is set from the register bit values, and not

from the mode pins.

14

13

Loopback

R/W

0b

0 = normal operation

1 = loopback mode

Speed Select

0 = 10Mbps

Note 4-1

1 = 100Mbps

Ignored if Auto-negotiation is enabled (0.12 = 1).

12

Auto-Negotiation Enable

0 = disable auto-negotiate process

R/W

Note 4-1

1 = enable auto-negotiate process (overrides 0.13 and 0.8)

DS00002165B-page 42

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

Bits

Description

Type

Default

11

Power Down

0 = normal operation

R/W

0b

1 = General power down mode

The Auto-Negotiation Enable must be cleared before setting the Power

Down.

10

9

Isolate

R/W

0b

0 = normal operation

1 = electrical isolation of PHY from the RMII

Restart Auto-Negotiate

0 = normal operation

1 = restart auto-negotiate process

Bit is self-clearing.

R/W

SC

8

Duplex Mode

0 = half duplex

R/W

Note 4-1

1 = full duplex

Ignored if Auto-Negotiation is enabled (0.12 = 1).

7:0

RESERVED

RO

—

Note 4-1

The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to

Section 3.7.2, MODE[2:0]: Mode Configuration for additional information.

4.2.2

BASIC STATUS REGISTER

Index (In Decimal):

1

Size:

16 bits

Bits

Description

Type

Default

15

100BASE-T4

RO

0b

0 = no T4 ability

1 = T4 able

14

13

12

11

10

100BASE-TX Full Duplex

0 = no TX full duplex ability

1 = TX with full duplex

RO

1b

0b

100BASE-TX Half Duplex

0 = no TX half duplex ability

1 = TX with half duplex

10BASE-T Full Duplex

0 = no 10Mbps with full duplex ability

1 = 10Mbps with full duplex

10BASE-T Half Duplex

0 = no 10Mbps with half duplex ability

1 = 10Mbps with half duplex

100BASE-T2 Full Duplex

0 = PHY not able to perform full duplex 100BASE-T2

1 = PHY able to perform full duplex 100BASE-T2

 2016 Microchip Technology Inc.

DS00002165B-page 43

LAN8720A/LAN8720AI

Bits

Description

Type

Default

9

100BASE-T2 Half Duplex

RO

0b

0 = PHY not able to perform half duplex 100BASE-T2

1 = PHY able to perform half duplex 100BASE-T2

8

Extended Status

RO

0b

0 = no extended status information in register 15

1 = extended status information in register 15

7:6

5

RESERVED

RO

—

Auto-Negotiate Complete

0b

0 = auto-negotiate process not completed

1 = auto-negotiate process completed

4

3

2

1

0

Remote Fault

1 = remote fault condition detected

0 = no remote fault

RO/LH

RO

0b

1b

0b

1b

Auto-Negotiate Ability

0 = unable to perform auto-negotiation function

1 = able to perform auto-negotiation function

Link Status

0 = link is down

1 = link is up

RO/LL

RO/LH

RO

Jabber Detect

0 = no jabber condition detected

1 = jabber condition detected

Extended Capabilities

0 = does not support extended capabilities registers

1 = supports extended capabilities registers

4.2.3

PHY IDENTIFIER 1 REGISTER

Index (In Decimal):

2

Size:

16 bits

Bits

Description

Type

Default

15:0

PHY ID Number

R/W

0007h

Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier

(OUI), respectively.

4.2.4

PHY IDENTIFIER 2 REGISTER

Index (In Decimal):

3

Size:

16 bits

DS00002165B-page 44

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

Bits

Description

Type

Default

15:10

PHY ID Number

R/W

110000b

Assigned to the 19th through 24th bits of the OUI.

9:4

3:0

Model Number

Six-bit manufacturer’s model number.

R/W

001111b

Note 4-2

Revision Number

Four-bit manufacturer’s revision number.

Note 4-2

The default value of this field will vary dependent on the silicon revision number.

AUTO NEGOTIATION ADVERTISEMENT REGISTER

4.2.5

Index (In Decimal):

4

Size:

16 bits

Bits

Description

Type

Default

15:14

13

RESERVED

RO

—

Remote Fault

R/W

0b

0 = no remote fault

1 = remote fault detected

12

RESERVED

RO

—

11:10

Pause Operation

00 = No PAUSE

R/W

00b

01 = Symmetric PAUSE

10 = Asymmetric PAUSE toward link partner

11 = Advertise support for both Symmetric PAUSE and Asymmetric PAUSE

toward local device

Note:

When both Symmetric PAUSE and Asymmetric PAUSE are set,

the device will only be configured to, at most, one of the two set-

tings upon auto-negotiation completion.

9

8

RESERVED

RO

—

100BASE-TX Full Duplex

0 = no TX full duplex ability

1 = TX with full duplex

R/W

Note 4-3

7

6

5

100BASE-TX

0 = no TX ability

1 = TX able

R/W

1b

10BASE-T Full Duplex

0 = no 10Mbps with full duplex ability

1 = 10Mbps with full duplex

Note 4-3

10BASE-T

0 = no 10Mbps ability

1 = 10Mbps able

 2016 Microchip Technology Inc.

DS00002165B-page 45

LAN8720A/LAN8720AI

Bits

Description

Type

Default

4:0

Selector Field

R/W

00001b

00001 = IEEE 802.3

Note 4-3

The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to

Section 3.7.2, MODE[2:0]: Mode Configuration for additional information.

4.2.6

AUTO NEGOTIATION LINK PARTNER ABILITY REGISTER

Index (In Decimal):

5

Size:

16 bits

Bits

Description

Type

Default

15

0b

0 = no next page ability

1 = next page capable

Note:

This device does not support next page ability.

14

13

Acknowledge

0 = link code word not yet received

1 = link code word received from partner

RO

0b

Remote Fault

0 = no remote fault

1 = remote fault detected

12:11

10

RESERVED

RO

—

Pause Operation

0b

0 = No PAUSE supported by partner station

1 = PAUSE supported by partner station

9

100BASE-T4

0 = no T4 ability

1 = T4 able

RO

0b

Note:

This device does not support T4 ability.

8

7

100BASE-TX Full Duplex

0 = no TX full duplex ability

1 = TX with full duplex

RO

0b

100BASE-TX

0 = no TX ability

1 = TX able

6

10BASE-T Full Duplex

0 = no 10Mbps with full duplex ability

1 = 10Mbps with full duplex

0b

5

10BASE-T

0 = no 10Mbps ability

1 = 10Mbps able

0b

4:0

Selector Field

00001b

00001 = IEEE 802.3

DS00002165B-page 46

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

4.2.7

AUTO NEGOTIATION EXPANSION REGISTER

Index (In Decimal):

6

Size:

16 bits

Bits

Description

Type

Default

15:5

4

RESERVED

Parallel Detection Fault

0 = no fault detected by parallel detection logic

1 = fault detected by parallel detection logic

RO

—

RO/LH

0b

3

2

1

0

Link Partner Next Page Able

0 = link partner does not have next page ability

1 = link partner has next page ability

RO

0b

Next Page Able

0 = local device does not have next page ability

1 = local device has next page ability

Page Received

0 = new page not yet received

1 = new page received

RO/LH

RO

Link Partner Auto-Negotiation Able

0 = link partner does not have auto-negotiation ability

1 = link partner has auto-negotiation ability

4.2.8

MODE CONTROL/STATUS REGISTER

Index (In Decimal): 17

Size:

16 bits

Bits

Description

Type

Default

15:14

13

RESERVED

EDPWRDOWN

Enable the Energy Detect Power-Down mode:

0 = Energy Detect Power-Down is disabled

1 = Energy Detect Power-Down is enabled

RO

—

R/W

0b

12:10

9

RESERVED

RO

—

FARLOOPBACK

R/W

0b

Enables far loopback mode (for example, all the received packets are sent

back simultaneously (in 100BASE-TX only)). This mode works even if the Iso-

late bit (0.10) is set.

0 = Far loopback mode is disabled

1 = Far loopback mode is enabled

Refer to Section 3.8.9.2, Far Loopback for additional information.

 2016 Microchip Technology Inc.

DS00002165B-page 47

LAN8720A/LAN8720AI

Bits

Description

Type

Default

8:7

6

RESERVED

RO

—

ALTINT

Alternate Interrupt Mode:

R/W

0b

0 = Primary interrupt system enabled (Default)

1 = Alternate interrupt system enabled

Refer to Section 3.6, Interrupt Management for additional information.

5:2

1

RESERVED

RO

—

ENERGYON

1b

Indicates whether energy is detected. This bit transitions to “0” if no valid

energy is detected within 256ms. It is reset to “1” by a hardware reset and is

unaffected by a software reset. Refer to Section 3.8.3.2, Energy Detect

Power-Down for additional information.

0

RESERVED

R/W

0b

4.2.9

SPECIAL MODES REGISTER

Index (In Decimal): 18

Size:

16 bits

Bits

Description

Type

Default

15

14

RESERVED

RO

—

RESERVED

R/W

1b

Write as 1, ignore on read.

NASR

13:8

7:5

RESERVED

MODE

RO

—

R/W

Note 4-5

Transceiver mode of operation. Refer to Section 3.7.2, MODE[2:0]: Mode

Configuration for additional details.

NASR

4:0

PHYAD

R/W

NASR

Note 4-6

PHY Address. The PHY Address is used for the SMI address and for initial-

ization of the Cipher (Scrambler) key. Refer to Section 3.7.1, PHYAD[2:0]:

PHY Address Configuration for additional details.

Note 4-4

Note 4-5

The default value of this field is determined by the MODE[2:0] configuration straps. Refer to

Section 3.7.2, MODE[2:0]: Mode Configuration for additional information.

The default value of this field is determined by the PHYAD[0] configuration strap. Refer to

Section 3.7.1, PHYAD[2:0]: PHY Address Configuration for additional information.

4.2.10

SYMBOL ERROR COUNTER REGISTER

Index (In Decimal): 26

Size:

16 bits

DS00002165B-page 48

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

Bits

Description

Type

Default

15:0

SYM_ERR_CNT

RO

0000h

The symbol error counter increments whenever an invalid code symbol is

received (including IDLE symbols) in 100BASE-TX mode. The counter is

incremented only once per packet, even when the received packet contains

more than one symbol error. This counter increments up to 65,536 (2¹⁶) and

rolls over to 0 after reaching the maximum value.

Note:

This register is cleared on reset, but is not cleared by reading the

register. This register does not increment in 10BASE-T mode.

4.2.11

SPECIAL CONTROL/STATUS INDICATIONS REGISTER

Index (In Decimal): 27

Size:

16 bits

Bits

Description

Type

Default

15

AMDIXCTRL

HP Auto-MDIX control:

0 = Enable Auto-MDIX

R/W

0b

1 = Disable Auto-MDIX (use 27.13 to control channel)

14

13

RESERVED

RO

—

CH_SELECT

R/W

0b

Manual channel select:

0 = MDI (TX transmits, RX receives)

1 = MDIX (TX receives, RX transmits)

12

11

RESERVED

RO

—

SQEOFF

R/W

0b

Disable the SQE test (Heartbeat):

0 = SQE test is enabled

1 = SQE test is disabled

NASR

10:5

4

RESERVED

RO

—

XPOL

0b

Polarity state of the 10BASE-T:

0 = Normal polarity

1 = Reversed polarity

3:0

RESERVED

RO

—

4.2.12

INTERRUPT SOURCE FLAG REGISTER

Index (In Decimal): 29

Size:

16 bits

 2016 Microchip Technology Inc.

DS00002165B-page 49

LAN8720A/LAN8720AI

Bits

Description

Type

Default

15:8

7

RESERVED

RO

—

INT7

RO/LH

0b

0 = not source of interrupt

1 = ENERGYON generated

6

5

4

3

2

1

0

INT6

RO/LH

RO

0b

0 = not source of interrupt

1 = Auto-Negotiation complete

INT5

0 = not source of interrupt

1 = Remote Fault Detected

INT4

0 = not source of interrupt

1 = Link Down (link status negated)

INT3

0 = not source of interrupt

1 = Auto-Negotiation LP Acknowledge

INT2

0 = not source of interrupt

1 = Parallel Detection Fault

INT1

0 = not source of interrupt

1 = Auto-Negotiation Page Received

RESERVED

4.2.13

INTERRUPT MASK REGISTER

Index (In Decimal): 30

Size:

16 bits

Bits

Description

Type

Default

15:8

7:1

RESERVED

RO

—

Mask Bits

R/W

0000000b

0 = interrupt source is masked

1 = interrupt source is enabled

Note:

Refer to Section 4.2.12, Interrupt Source Flag Register for details

on the corresponding interrupt definitions.

0

RESERVED

RO

—

DS00002165B-page 50

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

4.2.14

PHY SPECIAL CONTROL/STATUS REGISTER

Index (In Decimal): 31

Size:

16 bits

Bits

Description

Type

Default

15:13

12

RESERVED

RO

—

Autodone

0b

Auto-negotiation done indication:

0 = Auto-negotiation is not done or disabled (or not active)

1 = Auto-negotiation is done

11:5

4:2

RESERVED - Write as 0000010b, ignore on read.

R/W

RO

0000010b

XXX

Speed Indication

HCDSPEED value:

001 = 10BASE-T half-duplex

101 = 10BASE-T full-duplex

010 = 100BASE-TX half-duplex

110 = 100BASE-TX full-duplex

1:0

RESERVED

RO

—

 2016 Microchip Technology Inc.

DS00002165B-page 51

LAN8720A/LAN8720AI

5.0

5.1

OPERATIONAL CHARACTERISTICS

Absolute Maximum Ratings*

Supply Voltage (VDDIO, VDD1A, VDD2A) (Note 5-1) ...............................................................................-0.5V to +3.6V

Digital Core Supply Voltage (VDDCR) (Note 5-1) ......................................................................................-0.5V to +1.5V

Ethernet Magnetics Supply Voltage ...........................................................................................................-0.5V to +3.6V

Positive voltage on signal pins, with respect to ground (Note 5-2)..............................................................................+6V

Negative voltage on signal pins, with respect to ground (Note 5-3)......................................................................... -0.5V

Positive voltage on XTAL1/CLKIN, with respect to ground ......................................................................................+3.6V

Positive voltage on XTAL2, with respect to ground..................................................................................................+2.5V

Ambient Operating Temperature in Still Air (T_A)............................................................................................... Note 5-40

Storage Temperature............................................................................................................................. .-55^oC to +150^oC

Junction to Ambient (_JA)................................................................................................................................. .59.8^oC/W

Junction to Case (_JC)...................................................................................................................................... .12.6^oC/W

Lead Temperature Range ...........................................................................................Refer to JEDEC Spec. J-STD-020

HBM ESD Performance per JEDEC JESD22-A114............................................................................................Class 3A

IEC61000-4-2 Contact Discharge ESD Performance (Note 5-5) ............................................................................+/-8kV

IEC61000-4-2 Air-Gap Discharge ESD Performance (Note 5-5) ..........................................................................+/-15kV

Latch-up Performance per EIA/JESD 78.......................................................................................................... .+/-150mA

Note 5-1

When powering this device from laboratory or system power supplies, it is important that the absolute

maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage

spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the

AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp

circuit be used.

Note 5-2

Note 5-3

Note 5-4

Note 5-5

This rating does not apply to the following pins: XTAL1/CLKIN, XTAL2, RBIAS.

This rating does not apply to the following pins: RBIAS.

0^oC to +85^oC for extended commercial version, -40^oC to +85^oC for industrial version.

Performed by independent 3rd party test facility.

*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating

only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional

operation of the device at any condition exceeding those indicated in Section 5.2, "Operating Conditions**", Section 5.1,

"Absolute Maximum Ratings*", or any other applicable section of this specification is not implied. Note, device signals

are NOT 5 volt tolerant unless specified otherwise.

5.2

Operating Conditions**

Supply Voltage (VDDIO)..........................................................................................................................+1.62V to +3.6V

Analog Port Supply Voltage (VDD1A, VDD2A) .........................................................................................+3.0V to +3.6V

Digital Core Supply Voltage (VDDCR) ..................................................................................................+1.08V to +1.32V

Ethernet Magnetics Supply Voltage ........................................................................................................+2.25V to +3.6V

Ambient Operating Temperature in Still Air (T_A)................................................................................................. Note 5-4

**Proper operation of the device is guaranteed only within the ranges specified in this section. After the device has com-

pleted power-up, VDDIO and the magnetics power supply must maintain their voltage level with +/-10%. Varying the

voltage greater than +/-10% after the device has completed power-up can cause errors in device operation.

Note:

Do not drive input signals without power supplied to the device.

DS00002165B-page 52

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

5.3

Power Consumption

This section details the device power measurements taken over various operating conditions. Unless otherwise noted,

all measurements were taken with power supplies at nominal values (VDDIO, VDD1A, VDD2A = 3.3V, VDDCR = 1.2V).

See Section 3.8.3, Power-Down Modes for a description of the power down modes. For more information on the REF_-

CLK modes, see Section 3.7.4, nINTSEL: nINT/REFCLKO Configuration.

5.3.1

REF_CLK IN MODE

TABLE 5-1:

DEVICE ONLY CURRENT CONSUMPTION AND POWER DISSIPATION (REF_CLK IN

MODE)

VDDA3.3

Power

PinS(mA)

VDDCR

Power

pin(mA)

VDDIO

power

pin(mA)

Total

Current

(mA)

Total

Power

(mW)

Power Pin Group

Max

Typical

Min

28

26

23

21

19

18

0.6

0.5

0.3

49

45

41

159

148

100BASE-TX /w traffic

10BASE-T /w traffic

96

Note 5-8

Max

Typical

Min

9.7

8.9

8.3

13

12

0.6

0.5

0.3

24

22

20

77

70

42

Note 5-8

Max

Typical

Min

4.2

4.1

3.9

3.0

1.9

0.2

0

7.4

6.2

5.8

25

21

Energy Detect Power Down

General Power Down

16

Note 5-8

Max

Typical

Min

0.4

0.3

2.8

1.8

1.7

0.2

0

3.4

2.3

2

11.2

7.6

3.0

Note 5-8

Note 5-6

Note 5-7

The current at VDDCR is either supplied by the internal regulator from current entering at VDD2A,

or from an external 1.2V supply when the internal regulator is disabled.

Current measurements do not include power applied to the magnetics or the optional external LEDs.

The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in 10BASE-T

mode, independent of the 2.5V or 3.3V supply rail of the transformer.

Note 5-8

Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled.

 2016 Microchip Technology Inc.

DS00002165B-page 53

LAN8720A/LAN8720AI

5.3.2

REF_CLK OUT MODE

.

TABLE 5-2:

DEVICE ONLY CURRENT CONSUMPTION AND POWER DISSIPATION (REF_CLK

OUT MODE)

VDDA3.3

Power

Pins(mA)

VDDCR

Power

Pin(mA)

VDDIO

Power

Pin(mA)

Total

Current

(mA)

Total

Power

(mW)

Power Pin Group

Max

Typical

Min

28

26

22

20

19

15

6.3

5.8

2.9

54

50

39

179

164

100BASE-T /w traffic

93

Note 5-11

Max

Typical

Min

9.9

8.8

7.1

13

12

10

6.4

5.6

3.0

30

26

20

96

85

10BASE-T /w traffic

Energy Detect Power Down

General Power Down

41

Note 5-11

Max

Typical

Min

4.5

4.0

3.9

2.7

1.5

1.2

0.3

0.2

0

7.5

5.7

5.1

25

19

15

Note 5-11

Max

Typical

Min

0.4

2.5

1.3

1.0

0.2

0

3.1

1.9

1.4

10.2

6.3

2.5

Note 5-11

Note 5-9

The current at VDDCR is either supplied by the internal regulator from current entering at VDD2A,

or from an external 1.2V supply when the internal regulator is disabled.

Note 5-10

Current measurements do not include power applied to the magnetics or the optional external LEDs.

The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in 10BASE-T

mode, independent of the 2.5V or 3.3V supply rail of the transformer.

Note 5-11

Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled.

DS00002165B-page 54

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

5.4

DC Specifications

TABLE 5-2: details the non-variable I/O buffer characteristics. These buffer types do not support variable voltage oper-

ation. TABLE 5-3: details the variable voltage I/O buffer characteristics. Typical values are provided for 1.8V, 2.5V, and

3.3V VDDIO cases.

TABLE 5-3:

NON-VARIABLE I/O BUFFER CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Units

Notes

IS Type Input Buffer

Low Input Level

V_ILI

V_IHI

-0.3

V

High Input Level

3.6

1.39

1.79

459

Negative-Going Threshold

Positive-Going Threshold

Schmitt Trigger Hysteresis

V_ILT

V_IHT

V_HYS

1.01

1.39

336

1.19

1.59

399

V

Schmitt trigger

V

mV

(V_IHT- V_ILT

)

Input Leakage

(V_IN= VSS or VDDIO)

I_IH

-10

10

2

uA

pF

Note 5-9

Input Capacitance

O12 Type Buffers

C_IN

Low Output Level

High Output Level

V_OL

V_OH

0.4

V

I_OL= 12mA

VDD2A -

0.4

I

_OH= -12mA

Note 5-10

ICLK Type Buffer

(XTAL1 Input)

Low Input Level

High Input Level

V_ILI

V_IHI

-0.3

0.9

0.35

3.6

V

Note 5-12

Note 5-13

This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up

resistors add +/- 50uA per-pin (typical).

XTAL1/CLKIN can optionally be driven from a 25MHz single-ended clock oscillator.

 2016 Microchip Technology Inc.

DS00002165B-page 55

LAN8720A/LAN8720AI

TABLE 5-4:

VARIABLE I/O BUFFER CHARACTERISTICS

1.8V 2.5V 3.3V

Parameter

Symbol

Min

Max

Units

Notes

Typ

VIS Type Input Buffer

Low Input Level

V_ILI

V_IHI

-0.3

V

High Input Level

3.6

1.76

1.90

288

Neg-Going Threshold

Pos-Going Threshold

Schmitt Trigger Hyster-

V_ILT

V_IHT

V_HYS

0.64

0.81

102

0.83 1.15 1.41

0.99 1.29 1.65

V

Schmitt trigger

V

158

136

138

mV

esis (V_IHT- V_ILT

)

Input Leakage

(V_IN= VSS or VDDIO)

I_IH

-10

10

2

uA

pF

Note 5-11

Input Capacitance

VO8 Type Buffers

C_IN

Low Output Level

High Output Level

V_OL

V_OH

0.4

V

I

_OL= 8mA

VDDIO -

0.4

I_OH= -8mA

VOD8 Type Buffer

Low Output Level

V_OL

0.4

V

I_OL= 8mA

Note 5-14

This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up

resistors add +/- 50uA per-pin (typical).

TABLE 5-5:

100BASE-TX TRANSCEIVER CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Units

Notes

Peak Differential Output Voltage High

Peak Differential Output Voltage Low

Signal Amplitude Symmetry

Signal Rise and Fall Time

Rise and Fall Symmetry

Duty Cycle Distortion

V_PPH

V_PPL

V_SS

T_RF

950

-950

98

—

50

—

1050

-1050

102

5.0

mVpk

%

Note 5-12

Note 5-13

—

3.0

—

nS

T_RFS

D_CD

V_OS

—

0.5

nS

35

65

%

Overshoot and Undershoot

Jitter

—

5

%

—

1.4

nS

Note 5-14

Note 5-15

Note 5-16

Measured at line side of transformer, line replaced by 100 (+/- 1%) resistor.

Offset from 16nS pulse width at 50% of pulse peak.

DS00002165B-page 56

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

Note 5-17

Measured differentially.

TABLE 5-6:

10BASE-T TRANSCEIVER CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Units

Notes

Transmitter Peak Differential Output Voltage

Receiver Differential Squelch Threshold

V_OUT

V_DS

2.2

2.5

2.8

V

Note 5-15

—

300

420

585

mV

Note 5-18

Min/max voltages guaranteed as measured with 100 resistive load.

5.5

AC Specifications

This section details the various AC timing specifications of the device.

Note 5-19

The SMI timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for

additional timing information.

Note 5-20

The RMII timing adheres to the RMII Consortium RMII Specification R1.2.

5.5.1

EQUIVALENT TEST LOAD

Output timing specifications assume a 25pF equivalent test load, unless otherwise noted, as illustrated in Figure 5-1

below.

FIGURE 5-1:

OUTPUT EQUIVALENT TEST LOAD

OUTPUT

25 pF

 2016 Microchip Technology Inc.

DS00002165B-page 57

LAN8720A/LAN8720AI

5.5.2

POWER SEQUENCE TIMING

This diagram illustrates the device power sequencing requirements. The VDDIO, VDD1A, VDD2A and magnetics power

supplies can turn on in any order provided they all reach operational levels within the specified time period t_pon. Device

power supplies can turn off in any order provided they all reach 0 volts within the specified time period p_off.

FIGURE 5-2:

POWER SEQUENCE TIMING

t_pon

t_poff

VDDIO

Magnetics

Power

VDD1A,

VDD2A

TABLE 5-7:

POWER SEQUENCE TIMING VALUES

Description

Symbol

Min

Typ

Max

Units

t_pon

t_poff

Power supply turn on time

Power supply turn off time

—

50

mS

500

Note:

When the internal regulator is disabled, a power-up sequencing relationship exists between VDDCR and

the 3.3V power supply. For additional information refer to Section 3.7.4, REGOFF: Internal +1.2V Regula-

tor Configuration.

5.5.3

POWER-ON NRST & CONFIGURATION STRAP TIMING

This diagram illustrates the nRST reset and configuration strap timing requirements in relation to power-on. A hardware

reset (nRST assertion) is required following power-up. For proper operation, nRST must be asserted for no less than

t_rstia. The nRST pin can be asserted at any time, but must not be deasserted before t_purstdafter all external power sup-

plies have reached 80% of their nominal operating levels. In order for valid configuration strap values to be read at

power-up, the t_cssand t_cshtiming constraints must be followed. Refer to Section 3.8.5, Resets for additional information.

DS00002165B-page 58

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

FIGURE 5-3:

POWER-ON NRST & CONFIGURATION STRAP TIMING

All External

Power Supplies

80%

t_purstd

t_purstv

t_rstia

nRST

t_css

t_csh

Configuration Strap

Pins Input

t_otaa

t_odad

Configuration Strap

Pins Output Drive

TABLE 5-8:

symbol

POWER-ON NRST & CONFIGURATION STRAP TIMING VALUES

DESCRIPTION

min

typ

max

units

t_purstd

t_purstv

t_rstia

t_css

External power supplies at 80% to nRST deassertion

External power supplies at 80% to nRST valid

nRST input assertion time

25

0

—

50

mS

nS

S

nS

100

200

1

Configuration strap pins setup to nRST deassertion

Configuration strap pins hold after nRST deassertion

Output tri-state after nRST assertion

t_csh

t_otaa

t_odad

Output drive after nRST deassertion

2

800

(Note 5-

20)

Note 5-21

Note 5-22

nRST deassertion must be monotonic.

Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7,

Configuration Straps for details. Configuration straps must only be pulled high or low and must not

be driven as inputs.

Note 5-23

20 clock cycles for 25MHz, or 40 clock cycles for 50MHz.

 2016 Microchip Technology Inc.

DS00002165B-page 59

LAN8720A/LAN8720AI

5.5.4

RMII INTERFACE TIMING

5.5.4.1

RMII Timing (REF_CLK Out Mode)

The 50MHz REF_CLK OUT timing applies to the case when nINTSEL is pulled-low. In this mode, a 25MHz crystal or

clock oscillator must be input on the XTAL1/CLKIN and XTAL2 pins. For more information on REF_CLK Out Mode, see

Section 3.7.4.2, REF_CLK Out Mode.

FIGURE 5-4:

RMII TIMING (REF_CLK OUT MODE)

t_clkp

t_clkht_clkl

REFCLKO

t_oval

t_ohold

RXD[1:0],

RXER

t_ohold

t_oval

CRS_DV

t_sut_ihold

t_ihold

TXD[1:0]

TXEN

t_ihold

t_su

TABLE 5-9:

Symbol

RMII TIMING VALUES (REF_CLK OUT MODE)

Description Min

Max

Units

Notes

t_clkp

t_clkh

t_clkl

REFCLKO period

20

—

ns

—

REFCLKO high time

REFCLKO low time

t_clkp*0.4

—

t_clkp*0.6

5.0

—

t_oval

RXD[1:0], RXER, CRS_DV output valid from ris-

ing edge of REFCLKO

Note 5-24

t_ohold

RXD[1:0], RXER, CRS_DV output hold from ris-

ing edge of REFCLKO

1.4

7.0

2.0

—

ns

Note 5-24

t_su

TXD[1:0], TXEN setup time to rising edge of

REFCLKO

t_ihold

TXD[1:0], TXEN input hold time after rising edge

of REFCLKO

Note 5-24

Timing was designed for system load between 10 pf and 25 pf.

DS00002165B-page 60

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

5.5.4.2

RMII Timing (REF_CLK In Mode)

The 50MHz REF_CLK IN timing applies to the case when nINTSEL is floated or pulled-high. In this mode, a 50MHz

clock must be input on the CLKIN pin. For more information on REF_CLK In Mode, see Section 3.7.4.1, REF_CLK In

Mode.

FIGURE 5-5:

RMII TIMING (REF_CLK IN MODE)

t_clkp

t_clkht_clkl

CLKIN

(REF_CLK)

t_oval

t_ohold

RXD[1:0],

RXER

t_ohold

t_oval

CRS_DV

TXD[1:0]

TXEN

t_sut_ihold

t_ihold

t_su

TABLE 5-10: RMII TIMING VALUES (REF_CLK IN MODE)

Symbol

Description

Min

Max

Units

Notes

t_clkp

t_clkh

t_clkl

CLKIN period

20

—

ns

—

CLKIN high time

CLKIN low time

t_clkp*0.35

—

t_clkp*0.65

14.0

—

t_oval

RXD[1:0], RXER, CRS_DV output valid from ris-

ing edge of CLKIN

Note 5-25

t_ohold

RXD[1:0], RXER, CRS_DV output hold from ris-

ing edge of CLKIN

3.0

4.0

1.5

—

ns

Note 5-25

t_su

TXD[1:0], TXEN setup time to rising edge of

CLKIN

t_ihold

TXD[1:0], TXEN input hold time after rising edge

of CLKIN

Note 5-25

Timing was designed for system load between 10 pf and 25 pf.

 2016 Microchip Technology Inc.

DS00002165B-page 61

LAN8720A/LAN8720AI

5.5.4.3

RMII CLKIN Requirements

TABLE 5-11: RMII CLKIN (REF_CLK) TIMING VALUES

Parameter

Min

Typ

Max

Units

Notes

CLKIN frequency

50

—

± 50

60

MHz

ppm

%

—

CLKIN Frequency Drift

CLKIN Duty Cycle

CLKIN Jitter

—

40

150

psec

p-p – not RMS

5.5.5

SMI TIMING

This section specifies the SMI timing of the device. Please refer to Section 3.5, Serial Management Interface (SMI) for

additional details.

FIGURE 5-6:

SMI TIMING

t_clkp

t_clkht_clkl

MDC

t_val

t_ohold

MDIO

(Data-Out)

t_sut_ihold

MDIO

(Data-In)

TABLE 5-12: SMI TIMING VALUES

Symbol

Description

Min

Max

Units

Notes

t_clkp

t_clkh

t_clkl

t_val

MDC period

400

160 (80%)

—

ns

—

MDC high time

MDC low time

—

MDIO (read from PHY) output valid from rising

edge of MDC

300

t_ohold

MDIO (read from PHY) output hold from rising

edge of MDC

0

—

ns

—

t_su

MDIO (write to PHY) setup time to rising edge of

MDC

10

t_ihold

MDIO (write to PHY) input hold time after rising

edge of MDC

DS00002165B-page 62

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

5.6

Clock Circuit

The device can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (±50ppm) input. If

the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should

be driven with a nominal 0-3.3V clock signal.

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals

(XTAL1/XTAL2). Either a 300uW or 100uW 25MHz crystal may be utilized. The 300uW 25MHz crystal specifications are

detailed in Section 5.6.1, "300uW 25MHz Crystal Specification," on page 65. The 100uW 25MHz crystal specifications

are detailed in Section 5.6.2, "100uW 25MHz Crystal Specification," on page 66.

5.6.1

300UW 25MHZ CRYSTAL SPECIFICATION

When utilizing a 300uW 25MHz crystal, the following circuit design (Figure 5-8) and specifications (Table 5-12) are

required to ensure proper operation.

FIGURE 5-7:

300UW 25MHZ CRYSTAL CIRCUIT

LAN8720

XTAL2

Y1

XTAL1

C₁

C₂

TABLE 5-13: 300UW 25MHZ CRYSTAL SPECIFICATIONS

Parameter

Crystal Cut

Symbol

Min

Nom

AT, typ

Fundamental Mode

Parallel Resonant Mode

Max

Units

Notes

—

Crystal Oscillation Mode

Crystal Calibration Mode

Frequency

—

F_fund

F_tol

F_temp

F_age

—

25.000

—

±50

—

MHz

PPM

pF

—

Frequency Tolerance @ 25^oC

Frequency Stability Over Temp

Frequency Deviation Over Time

Total Allowable PPM Budget

Shunt Capacitance

—

Note 5-26

Note 5-27

Note 5-28

—

+/-3 to 5

—

±50

—

C_O

C_L

—

7 typ

20 typ

—

Load Capacitance

—

300

—

pF

—

Drive Level

P_W

R₁

—

uW

—

Equivalent Series Resistance

Operating Temperature Range

XTAL1/CLKIN Pin Capacitance

XTAL2 Pin Capacitance

—

30

Ohm

^oC

—

Note 5-35

—

+85

—

3 typ

pF

Note 5-30

—

pF

 2016 Microchip Technology Inc.

DS00002165B-page 63

LAN8720A/LAN8720AI

Note 5-26

The maximum allowable values for Frequency Tolerance and Frequency Stability are application

dependent. Since any particular application must meet the IEEE ±50 PPM Total PPM Budget, the

combination of these two values must be approximately ±45 PPM (allowing for aging).

Note 5-27

Note 5-28

Frequency Deviation Over Time is also referred to as Aging.

The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as 

±100 PPM.

Note 5-29

Note 5-30

0^oC for extended commercial version, -40^oC for industrial version.

This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included

in this value. The XTAL1/CLKIN pin, XTAL2 pin and PCB capacitance values are required to

accurately calculate the value of the two external load capacitors. The total load capacitance must

be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate

at 25.000 MHz.

5.6.2

100UW 25MHZ CRYSTAL SPECIFICATION

When utilizing a 100uW 25MHz crystal, the following circuit design (Figure 5-9) and specifications (Table 5-13) are

required to ensure proper operation.

FIGURE 5-8:

100UW 25MHZ CRYSTAL CIRCUIT

LAN8720

XTAL2

R_S

Y1

XTAL1

C₁

C₂

TABLE 5-14: 100UW 25MHZ CRYSTAL SPECIFICATIONS

Parameter

Crystal Cut

Symbol

Min

Nom

AT, typ

Fundamental Mode

Parallel Resonant Mode

Max

Units

Notes

—

Crystal Oscillation Mode

Crystal Calibration Mode

Frequency

—

F_fund

F_tol

—

25.000

—

±50

—

MHz

PPM

pF

—

Frequency Tolerance @ 25^oC

Frequency Stability Over Temp

Frequency Deviation Over Time

Total Allowable PPM Budget

Shunt Capacitance

—

8

Note 5-31

Note 5-32

Note 5-33

—

F_temp

F_age

—

±3 to 5

—

±50

5

C_O

—

Load Capacitance

C_L

—

12

pF

—

Drive Level

P_W

—

100

—

uW

Note 5-34

DS00002165B-page 64

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

TABLE 5-14: 100UW 25MHZ CRYSTAL SPECIFICATIONS (CONTINUED)

Parameter

Symbol

Min

Nom

Max

Units

Notes

Equivalent Series Resistance

XTAL2 Series Resistor

R₁

R_s

—

495

—

500

—

80

505

+85

—

Ohm

^oC

—

Operating Temperature Range

XTAL1/CLKIN Pin Capacitance

XTAL2 Pin Capacitance

Note 5-35

—

3 typ

pF

Note 5-36

—

pF

Note 5-31

The maximum allowable values for Frequency Tolerance and Frequency Stability are application

dependent. Since any particular application must meet the IEEE ±50 PPM Total PPM Budget, the

combination of these two values must be approximately ±45 PPM (allowing for aging).

Note 5-32

Note 5-33

Frequency Deviation Over Time is also referred to as Aging.

The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as 

±100 PPM.

Note 5-34

Note 5-35

Note 5-36

The crystal must support 100uW operation to utilize this circuit.

0^oC for extended commercial version, -40^oC for industrial version.

This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included

in this value. The XTAL1/CLKIN pin, XTAL2 pin and PCB capacitance values are required to

accurately calculate the value of the two external load capacitors. The total load capacitance must

be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate

at 25.000 MHz.

 2016 Microchip Technology Inc.

DS00002165B-page 65

LAN8720A/LAN8720AI

6.0

6.1

PACKAGE INFORMATION

24-QFN (Punch)

Min

Nominal

Max

Remarks

A

0.70

0

—

3.90

3.55

2.40

0.30

0.18

0.25

0.85

0.02

—

4.00

3.75

2.50

0.40

0.25

—

1.00

0.05

0.90

4.10

3.95

2.60

0.50

0.30

—

Overall Package Height

Standoff

Mold Cap Thickness

X/Y Body Size

X/Y Mold Cap Size

X/Y Exposed Pad Size

Terminal Length

A1

A2

D/E

D1/E1

D2/E2

L

b

k

e

Terminal Width

Terminal to Exposed Pad Clearance

Terminal Pitch

0.50 BSC

Note 1: All dimensions are in millimeters unless otherwise noted.

2: Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip.

3: The pin 1 identifier may vary, but is always located within the zone indicated.

DS00002165B-page 66

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

 2016 Microchip Technology Inc.

DS00002165B-page 67

LAN8720A/LAN8720AI

6.2

24-SQFN (Sawn)

DS00002165B-page 68

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

6.3

Tape & Reel Information

Note:

Standard reel size is 5,000 pieces per reel.

 2016 Microchip Technology Inc.

DS00002165B-page 69

LAN8720A/LAN8720AI

DS00002165B-page 70

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

7.0

7.1

APPLICATION NOTES

Application Diagram

The device requires few external components. The voltage on the magnetics center tap can range from 2.5 - 3.3V.

7.1.1 RMII DIAGRAM

FIGURE 7-1:

SIMPLIFIED APPLICATION DIAGRAM

LAN8720

10/100 PHY

24-QFN

RMII

MDIO

MDC

nINT

Mag

RJ45

TXP

TXN

TXD[1:0]

2

RXP

RXN

TXEN

RXD[1:0]

RXER

XTAL1/CLKIN

XTAL2

LED[2:1]

25MHz

2

nRST

Interface

7.1.2

POWER SUPPLY DIAGRAM

 2016 Microchip Technology Inc.

DS00002165B-page 71

LAN8720A/LAN8720AI

FIGURE 7-3:

HIGH-LEVEL SYSTEM DIAGRAM FOR POWER

Analog

Supply

3.3V

Power to

magnetics

interface.

LAN8720

24-QFN

19

6

VDDCR

VDDIO

VDD1A

1uF

C_BYPASS

VDDDIO

Supply

9

1

VDD2A

RBIAS

1.8 - 3.3V

C_BYPASS

C_F

C_BYPASS

R

C

24

15

nRST

12k

VSS

7.1.3

TWISTED-PAIR INTERFACE DIAGRAM

FIGURE 7-5:

COPPER INTERFACE DIAGRAM

49.9 Resistors

LAN8720

24-QFN

Analog

Supply

3.3V

Magnetic

Supply

2.5 - 3.3V

1

VDD2A

C_BYPASS

19

21

VDD1A

TXP

C_BYPASS

Magnetics

RJ45

1

2

3

4

5

6

7

8

75

20

23

TXN

RXP

22

RXN

1000 pF

3 kV

C_BYPASS

DS00002165B-page 72

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

APPENDIX A: DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

Section/Figure/Entry

Revision

Correction

Rev B. (07-15-16)

Rev. A (06-24-16)

Section 5.1, "Absolute Maxi- Update to Positive voltage on XTAL1/CLKIN, with

mum Ratings*," on page 54

respect to ground.

Table 5-2, “Non-Variable I/O

Buffer Characteristics,” on

page 56

Update to min/max values for the last row, ICLK

Type Buffer (XTAL1 Input) - High Input Level.

All

Document converted to Microchip look and feel.

Replaces SMSC Rev. 1.4 (08-23-12).

Section 5.2, "Operating Con- Increased VDDCR operational limits from “+1.14V

ditions**," on page 54

to +1.26V” to “+1.08V to +1.32V”

Section 5.6, "Clock Circuit,"

on page 65

Added new 100uW crystal specifications and circuit

diagram. The section is now split into two subsec-

tions, one for 300uW crystals and the other for

100uW crystals.

Section 6.0, "Package Infor-

mation," on page 68

Added new subsections to include SQFN package

information.

Section , "Product Identifica- Updated ordering codes with sawn SQFN package

tion System," on page 77

options.

Rev. 1.4

(08-23-12)

Section 4.2.2, Basic Status

Register

Updated definitions of bits 10:8.

Rev. 1.3

(04-20-11)

Table 5-9, “RMII Timing Val-

ues (REF_CLK Out Mode),”

on page 60

Updated t_ovalmaximum value from 10.0ns to 5.0ns.

Updated diagrams and tables to include RXER.

Rev. 1.2 (11-10-10)

Section 5.5.5, "RMII Inter-

face Timing," on page 63

 2016 Microchip Technology Inc.

DS00002165B-page 73

LAN8720A/LAN8720AI

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make

files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-

tains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s

guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion

groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-

nars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive

e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or

development tool of interest.

To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-

cation” and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales

offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-

ment.

Technical support is available through the web site at: http://microchip.com/support

DS00002165B-page 74

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

[X]⁽¹⁾

-

[XXX]

[X]

PART NO.

Examples:

a)

LAN8720Ai-CP-TR

Industrial temp., Tape & Reel, 24-QFN (Punch)

Device Temperature Tape & Reel

Range

Option

Package

b)

LAN8720A-CP-ABC

Ext. commercial temp., Tray, 24-SQFN (Sawn)

Device:

LAN8720A

Temperature

Range:

CP

i-CP

=

0C to +85C (Extended Commercial)

= -40C to +85C (Industrial)

Tape and Reel

Option:

Blank = Standard packaging (tray)

(1)

TR

= Tape and Reel

Package:

Blank = Punch Package (24-QFN)

ABC = Sawn Package (24-SQFN)

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This

identifier is used for ordering purposes and is

not printed on the device package. Check

with your Microchip Sales Office for package

availability with the Tape and Reel option.

 2016 Microchip Technology Inc.

DS00002165B-page 75

LAN8720A/LAN8720AI

NOTES:

DS00002165B-page 76

 2016 Microchip Technology Inc.

LAN8720A/LAN8720AI

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be

superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO

REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-

chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold

harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or

otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,

Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other

countries.

ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial

Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless

DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 978-1-5224-0780-5

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ

CERTIFIEDꢀBYꢀDNVꢀ

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

== ISO/TSꢀ16949ꢀ==ꢀ

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2016 Microchip Technology Inc.

DS00002165B-page 77

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

Germany - Dusseldorf

Tel: 49-2129-3766400

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Germany - Karlsruhe

Tel: 49-721-625370

India - Pune

Tel: 91-20-3019-1500

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Austin, TX

Tel: 512-257-3370

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Boston

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Dongguan

Tel: 86-769-8702-9880

Italy - Venice

Tel: 39-049-7625286

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Guangzhou

Tel: 86-20-8755-8029

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Korea - Seoul

Cleveland

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Poland - Warsaw

Tel: 48-22-3325737

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Sweden - Stockholm

Tel: 46-8-5090-4654

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Novi, MI

Tel: 248-848-4000

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Houston, TX

Tel: 281-894-5983

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Taiwan - Kaohsiung

Tel: 886-7-213-7828

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

06/23/16

DS00002165B-page 78

 2016 Microchip Technology Inc.


型号：	LAN8720ACP-ABC
厂家：	MICROCHIP
描述：	Ethernet Transceiver
文件：	总78页 (文件大小：1209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LAN8720ACP-ABC [MICROCHIP]

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LAN8720I

LAN8740

LAN8740A

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