MCP1825-2502E/AT [MICROCHIP]
500 mA, Low Voltage, Low Quiescent Current LDO Regulator; 500毫安，低电压，低静态电流LDO稳压器
| 型号： | MCP1825-2502E/AT |
| 厂家： | 
MICROCHIP |
| 描述： | 500 mA, Low Voltage, Low Quiescent Current LDO Regulator |
| 文件： | 总38页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP1825/MCP1825S
500 mA, Low Voltage, Low Quiescent Current LDO Regulator
Features
Description
• 500 mA Output Current Capability
The MCP1825/MCP1825S is a 500 mA Low Dropout
(LDO) linear regulator that provides high current and
low output voltages. The MCP1825 comes in a fixed or
adjustable output voltage version, with an output
voltage range of 0.8V to 5.0V. The 500 mA output
current capability, combined with the low output voltage
capability, make the MCP1825 a good choice for new
sub-1.8V output voltage LDO applications that have
high current demands. The MCP1825S is a 3-pin fixed
voltage version.
• Input Operating Voltage Range: 2.1V to 6.0V
• Adjustable Output Voltage Range: 0.8V to 5.0V
(MCP1825 only)
• Standard Fixed Output Voltages:
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V
• Other Fixed Output Voltage Options Available
Upon Request
• Low Dropout Voltage: 210 mV Typical at 500 mA
• Typical Output Voltage Tolerance: 0.5%
• Stable with 1.0 µF Ceramic Output Capacitor
• Fast response to Load Transients
The MCP1825/MCP1825S is stable using ceramic
output capacitors that inherently provide lower output
noise and reduce the size and cost of the entire
regulator solution. Only 1 µF of output capacitance is
needed to stabilize the LDO.
• Low Supply Current: 120 µA (typical)
• Low Shutdown Supply Current: 0.1 µA (typical)
(MCP1825 only)
Using CMOS construction, the quiescent current
consumed by the MCP1825/MCP1825S is typically
less than 120 µA over the entire input voltage range,
making it attractive for portable computing applications
that demand high output current. The MCP1825
versions have a Shutdown (SHDN) pin. When shut
down, the quiescent current is reduced to less than
0.1 µA.
• Fixed Delay on Power Good Output
(MCP1825 only)
• Short Circuit Current Limiting and
Overtemperature Protection
• TO-263-5 (DDPAK-5), TO-220-5, SOT-223-5
Package Options (MCP1825).
• TO-263-3 (DDPAK-3), TO-220-3, SOT-223-3
Package Options (MCP1825S).
On the MCP1825 fixed output versions, the scaled-
down output voltage is internally monitored and a
power good (PWRGD) output is provided when the
output is within 92% of regulation (typical). The
PWRGD delay is internally fixed at 110 µs (typical).
Applications
• High-Speed Driver Chipset Power
• Networking Backplane Cards
• Notebook Computers
The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
fault conditions.
• Network Interface Cards
• Palmtop Computers
• 2.5V to 1.XV Regulators
© 2008 Microchip Technology Inc.
DS22056B-page 1
MCP1825/MCP1825S
Package Types
MCP1825
MCP1825S
DDPAK-5
TO-220-5
Fixed/Adjustable
DDPAK-3
TO-220-3
1
2
3
1
2
3
1
2 3 4 5
1 2 3 4 5
SOT-223-5
SOT-223-3
6
4
2
1
3
1
2
4
3
5
Pin
Pin
Fixed
Adjustable
1
2
3
4
VIN
1
2
3
4
5
6
SHDN
VIN
SHDN
VIN
GND (TAB)
VOUT
GND (TAB)
VOUT
GND (TAB)
VOUT
GND (TAB)
PWRGD
GND (TAB)
ADJ
GND (TAB)
DS22056B-page 2
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
Typical Applications
MCP1825 Fixed Output Voltage
PWRGD
R1
100 kΩ
On
SHDN
VIN
Off
1
VOUT = 1.8V @ 500 mA
VOUT
VIN = 2.3V to 2.8V
GND
C1
C2
1 µF
4.7 µF
MCP1825 Adjustable Output Voltage
VADJ
R2
20 kΩ
R1
40 kΩ
On
SHDN
VIN
Off
1
VOUT = 1.2V @ 500 mA
VOUT
VIN = 2.1V to 2.8V
C1
4.7 µF
C2
1 µF
GND
© 2008 Microchip Technology Inc.
DS22056B-page 3
MCP1825/MCP1825S
Functional Block Diagram - Adjustable Output
PMOS
VIN
VOUT
Undervoltage
Lock Out
(UVLO)
ISNS
Cf
Rf
SHDN
ADJ/SENSE
+
–
Driver w/limit
and SHDN
EA
Overtemperature
Sensing
SHDN
VREF
V
IN
Reference
SHDN
Soft-Start
Comp
TDELAY
GND
92% of VREF
DS22056B-page 4
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
Functional Block Diagram - Fixed Output (3-Pin)
PMOS
VIN
VOUT
Undervoltage
Lock Out
Sense
(UVLO)
ISNS
Cf
Rf
SHDN
+
–
Driver w/limit
and SHDN
EA
Overtemperature
Sensing
SHDN
VREF
V
IN
Reference
SHDN
Soft-Start
Comp
TDELAY
GND
92% of VREF
© 2008 Microchip Technology Inc.
DS22056B-page 5
MCP1825/MCP1825S
Functional Block Diagram - Fixed Output (5-Pin)
PMOS
VIN
VOUT
Undervoltage
Lock Out
Sense
(UVLO)
ISNS
Cf
Rf
SHDN
+
–
Driver w/limit
and SHDN
EA
Overtemperature
Sensing
SHDN
VREF
V
IN
Reference
SHDN
Soft-Start
PWRGD
Comp
TDELAY
GND
92% of VREF
DS22056B-page 6
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
† Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VIN....................................................................................6.5V
Maximum Voltage on Any Pin .. (GND – 0.3V) to (VDD + 0.3)V
Maximum Power Dissipation......... Internally-Limited (Note 6)
Output Short Circuit Duration................................Continuous
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature, TJ ...........................+150°C
ESD protection on all pins (HBM/MM) ........... ≥ 4 kV; ≥ 300V
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
OUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
I
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Operating Voltage
Input Quiescent Current
VIN
Iq
2.1
6.0
V
Note 1
—
120
0.1
220
µA
IL = 0 mA, VOUT = 0.8V to
5.0V
Input Quiescent Current for
SHDN Mode
ISHDN
IOUT
—
500
—
3
—
µA
mA
%/V
%
SHDN = GND
Maximum Output Current
—
VIN = 2.1V to 6.0V
V
R = 0.8V to 5.0V, Note 1
Line Regulation
ΔVOUT
(VOUT x ΔVIN
/
±0.05
±0.5
1.2
±0.16
1.0
—
(Note 1) ≤ VIN ≤ 6V
)
Load Regulation
ΔVOUT/VOUT
-1.0
—
IOUT = 1 mA to 500 mA,
(Note 4)
Output Short Circuit Current
IOUT_SC
A
RLOAD < 0.1Ω, Peak Current
Adjust Pin Characteristics (Adjustable Output Only)
Adjust Pin Reference Voltage
VADJ
0.402
0.410
0.418
V
VIN = 2.1V to VIN = 6.0V,
I
OUT = 1 mA
Adjust Pin Leakage Current
IADJ
-10
—
±0.01
40
+10
—
nA
VIN = 6.0V, VADJ = 0V to 6V
Adjust Temperature Coefficient
TCVOUT
ppm/°C Note 3
Fixed-Output Characteristics (Fixed Output Only)
Voltage Regulation VOUT
VR - 2.5% VR ±0.5% VR + 2.5%
V
Note 2
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX)
.
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
© 2008 Microchip Technology Inc.
DS22056B-page 7
MCP1825/MCP1825S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
I
OUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters
Sym
Min
Typ
Max
350
Units
Conditions
Dropout Characteristics
Dropout Voltage
VDROPOUT
—
210
mV
Note 5, IOUT = 500 mA,
V
IN(MIN) = 2.1V
Power Good Characteristics
PWRGD Input Voltage Operat-
ing Range
VPWRGD_VIN
1.0
—
—
6.0
V
TA = +25°C
1.2
6.0
TA = -40°C to +125°C
For VIN < 2.1V, ISINK = 100 µA
PWRGD Threshold Voltage
VPWRGD_TH
%VOUT Falling Edge
VOUT < 2.5V Fixed,
OUT = Adj.
(Referenced to VOUT
)
89
92
95
V
90
1.0
—
92
2.0
0.2
94
3.0
0.4
VOUT >= 2.5V Fixed
PWRGD Threshold Hysteresis
PWRGD Output Voltage Low
VPWRGD_HYS
VPWRGD_L
%VOUT
V
IPWRGD SINK = 1.2 mA,
ADJ = 0V
PWRGD Leakage
PWRGD
_
—
—
1
—
—
nA
µs
VPWRGD = VIN = 6.0V
Rising Edge
LK
PWRGD Time Delay
TPG
110
RPULLUP = 10 kΩ
Detect Threshold to PWRGD
Active Time Delay
TVDET-PWRGD
—
200
—
µs
VOUT = VPWRGD_TH + 20 mV
to VPWRGD_TH - 20 mV
Shutdown Input
Logic High Input
VSHDN-HIGH
VSHDN-LOW
SHDNILK
45
—
—
—
—
15
%VIN
%VIN
µA
VIN = 2.1V to 6.0V
VIN = 2.1V to 6.0V
Logic Low Input
SHDN Input Leakage Current
-0.1
±0.001
+0.1
VIN = 6V, SHDN =VIN
SHDN = GND
,
AC Performance
Output Delay From SHDN
TOR
eN
—
—
100
2.0
—
—
µs
SHDN = GND to VIN
,
V
OUT = GND to 95% VR
Output Noise
µV/√Hz IOUT = 200 mA, f = 1 kHz,
OUT = 10 µF (X7R Ceramic),
OUT = 2.5V
C
V
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX)
.
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
DS22056B-page 8
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
OUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
I
Parameters
Sym
Min
Typ
Max
Units
Conditions
Power Supply Ripple Rejection
Ratio
PSRR
—
60
—
dB
f = 100 Hz, COUT = 4.7 µF,
I
OUT = 100 µA,
INAC = 100 mV pk-pk,
IN = 0 µF
V
C
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TSD
—
—
150
10
—
—
°C
°C
IOUT = 100 µA, VOUT = 1.8V,
IN = 2.8V
V
ΔTSD
IOUT = 100 µA, VOUT = 1.8V,
IN = 2.8V
V
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX)
.
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
© 2008 Microchip Technology Inc.
DS22056B-page 9
MCP1825/MCP1825S
TEMPERATURE SPECIFICATIONS
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
TJ
TJ
TA
-40
—
—
—
—
+125
+150
+150
°C
°C
°C
Steady State
Transient
-65
Thermal Package Resistances
Thermal Resistance, 3LD DDPAK
θJA
θJC
θJA
θJC
θJA
θJC
θJA
θJC
θJA
θJC
θJA
θJC
—
—
—
—
—
—
—
—
—
—
—
—
31.4
3.0
—
—
—
—
—
—
—
—
—
—
—
—
°C/W 4-Layer JC51 Standard
Board
Thermal Resistance, 3LD TO-220
Thermal Resistance, 3LD SOT-223
Thermal Resistance, 5LD DDPAK
Thermal Resistance, 5LD TO-220
Thermal Resistance, 5LD SOT-223
29.4
2.0
°C/W 4-Layer JC51 Standard
Board
62
°C/W EIA/JEDEC JESD51-751-7
4 Layer Board
15.0
31.2
3.0
°C/W 4-Layer JC51 Standard
Board
29.3
2.0
°C/W 4-Layer JC51 Standard
Board
62
°C/W EIA/JEDEC JESD51-751-7
4 Layer Board
15.0
DS22056B-page 10
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
140
130
120
110
100
90
VOUT = 1.2V adj
IN = 2.1V to 6.0V
VOUT = 1.2V Adj
OUT = 0 mA
IOUT = 1 mA
V
I
130°C
90°C
IOUT = 50 mA
25°C
0°C
IOUT=100 mA IOUT=500 mA
-45°C
IOUT=250 mA
2
3
4
Input Voltage (V)
5
6
-45
-20
5
30
55
80
105 130
Temperature (°C)
FIGURE 2-1:
Quiescent Current vs. Input
FIGURE 2-4:
Line Regulation vs.
Voltage (Adjustable Version).
Temperature (Adjustable Version).
0.20
200
190
180
170
IOUT = 1.0 mA to 500 mA
VOUT = 1.2V Adj
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
VOUT = 3.3V
VOUT = 1.8V
VIN=5.0V
160
150
VIN=3.3V
140
130
120
VOUT = 0.8V
VOUT = 5.0V
110
100
VIN=2.5V
0
100
200
300
400
500
600
-45
-20
5
30
55
80
105 130
Load Current (mA)
Temperature (°C)
FIGURE 2-2:
Ground Current vs. Load
FIGURE 2-5:
Load Regulation vs.
Current (Adjustable Version).
Temperature (Adjustable Version).
170
0.4110
VOUT = 1.2V Adj
OUT = 0 mA
VOUT = 1.8V
OUT = 1.0 mA
160
0.4105
0.4100
0.4095
0.4090
0.4085
0.4080
0.4075
0.4070
I
I
150
VIN = 6.0V
140
VIN=6.0V
130 VIN=5.0V
120
110
100
90
VIN = 4.0V
VIN=4.0V
VIN=3.0V
VIN = 2.3V
VIN=2.1V
-45
-20
5
30
55
80
105
130
-45
-20
5
30
55
80
105 130
Temperature (°C)
Temperature (°C)
FIGURE 2-3:
Quiescent Current vs.
FIGURE 2-6:
Adjust Pin Voltage vs.
Junction Temperature (Adjustable Version).
Temperature (Adjustable Version).
© 2008 Microchip Technology Inc.
DS22056B-page 11
MCP1825/MCP1825S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
0.30
0.25
0.20
0.15
0.10
0.05
0.00
160
150
140
130
120
110
100
90
VOUT = 0.8V
OUT = 0 mA
I
VOUT = 5.0V Adj
+130°C
+90°C
+25°C
VOUT = 2.5V Adj
0°C
-45°C
0
50 100 150 200 250 300 350 400 450 500
Load Current (mA)
2
3
4
5
6
Input Voltage (V)
FIGURE 2-7:
Dropout Voltage vs. Load
FIGURE 2-10:
Quiescent Current vs. Input
Current (Adjustable Version).
Voltage.
0.30
0.28
150
140
130
120
110
100
90
IOUT = 500 mA
VOUT = 2.5V
I
OUT = 0 mA
VOUT = 5.0V Adj
+130°C
+90°C
0.26
0.24
0.22
0.20
VOUT = 3.3V Adj
+25°C
+0°C
VOUT = 2.5V Adj
-45°C
-45
-20
5
30
55
80
105
130
3
3.5
4
4.5
5
5.5
6
Temperature (°C)
Input Voltage (V)
FIGURE 2-8:
Dropout Voltage vs.
FIGURE 2-11:
Quiescent Current vs. Input
Temperature (Adjustable Version).
Voltage.
170
250
200
VIN = 2.3V for VR=0.8V
VIN = 3.0V for VR=2.5V
VOUT = 2.5V Fixed
160
150
140
130
120
110
100
VIN = 6.0V
VOUT=2.5V
150
100
50
VIN = 5.0V
VOUT=0.8V
VIN = 3.0V
VIN = 4.0V
0
-45
-20
5
30
55
80
105 130
0
100
200
300
400
500
600
Temperature (°C)
Load Current (mA)
FIGURE 2-9:
Power Good (PWRGD)
FIGURE 2-12:
Ground Current vs. Load
Time Delay vs. Temperature.
Current.
DS22056B-page 12
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
0.045
0.040
0.035
0.030
0.025
0.020
0.015
140
135
130
125
120
115
110
105
100
95
IOUT = 0 mA
VR = 2.5V
VIN = 3.1V to 6.0V
IOUT = 1 mA
VOUT = 5V
IOUT = 50 mA
IOUT = 100 mA
VOUT = 2.5V
VOUT = 0.8V
IOUT = 250 mA
IOUT = 500 mA
-45
-20
5
30
55
80
105
130
130
130
-45
-20
5
30
55
80
105 130
Temperature (°C)
Temperature (°C)
FIGURE 2-13:
Temperature.
Quiescent Current vs.
FIGURE 2-16:
Temperature.
Line Regulation vs.
0.30
0.25
0.20
VR = 0.8V
0.25
0.15
VOUT = 0.8V
IOUT = 1 mA to 500 mA
VIN = 4.0V
VIN = 5.0V
VIN = 2.1V
VIN = 6.0V
0.05
-0.05
-0.15
-0.25
0.15
0.10
0.05
0.00
VIN = 5.0V
VIN = 4.0V
VIN = 2.3V
VIN = 6.0V
-45
-20
5
30
55
80
105
-45
-20
5
30
55
80
105
130
Temperature (°C)
Temperature (°C)
FIGURE 2-14:
I
vs. Temperature.
FIGURE 2-17:
Temperature (V
Load Regulation vs.
< 2.5V Fixed).
SHDN
OUT
0.09
0.00
-0.05
-0.10
-0.15
-0.20
IOUT = 1 mA to 500 mA
VOUT = 0.8V
IN = 2.1V to 6.0V
IOUT = 1 mA
0.08
0.07
0.06
0.05
0.04
0.03
0.02
V
VOUT = 2.5V
IOUT = 50 mA
IOUT = 250 mA
IOUT = 100 mA
VOUT = 5.0V
-0.25
-0.30
-0.35
IOUT = 500 mA
-45
-20
5
30
55
80
105
-45
-20
5
30
55
80
105
130
Temperature (°C)
Temperature (°C)
FIGURE 2-15:
Temperature.
Line Regulation vs.
FIGURE 2-18:
Temperature (V
Load Regulation vs.
≥ 2.5V Fixed).
OUT
© 2008 Microchip Technology Inc.
DS22056B-page 13
MCP1825/MCP1825S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
0.30
10
VR=2.5V, VIN=3.3V
VR=0.8V, VIN=2.3V
COUT=1 μF cer
CIN=10 μF cer
0.25
0.20
0.15
0.10
0.05
0.00
VOUT = 5.0V
1
0.1
IOUT=200 mA
VOUT = 2.5V
0.01
0
100
200
300
400
500
0.01
0.1
1
10
100
1000
Frequency (kHz)
Load Current (mA)
FIGURE 2-19:
Dropout Voltage vs. Load
FIGURE 2-22:
Output Noise Voltage
Current.
Density vs. Frequency.
0.30
0.28
0.26
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
IOUT = 500 mA
VOUT = 5.0V
0.24
0.22
0.20
0.18
VR=1.2V Adj
COUT=10 μF ceramic X7R
VIN=2.5V
-60.0
-70.0
-80.0
CIN=0 μF
I
OUT=10 mA
VOUT = 2.5V
-45
-20
5
30
55
80
105
130
0.01
0.1
1
10
100
1000
Frequency (kHz)
Temperature (°C)
FIGURE 2-20:
Dropout Voltage vs.
FIGURE 2-23:
Power Supply Ripple
Temperature.
Rejection (PSRR) vs. Frequency (Adj.).
0.0
-10.0
-20.0
-30.0
-40.0
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
VOUT = 2.5V
VR=2.5V (Fixed)
-50.0
C
OUT=22 μF ceramic X7R
-60.0
-70.0
-80.0
-90.0
VIN=3.3V
C
IN=0 μF
I
OUT=10 mA
0.00 1.00 2.00 3.00 4.00 5.00 6.00
Input Voltage (V)
0.01
0.1
1
10
100
1000
Frequency (kHz)
FIGURE 2-21:
Short Circuit Current vs.
FIGURE 2-24:
Power Supply Ripple
Input Voltage.
Rejection (PSRR) vs. Frequency.
DS22056B-page 14
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
FIGURE 2-25:
2.5V (Adj.) Startup from V .
FIGURE 2-28:
Dynamic Line Response.
IN
FIGURE 2-26:
2.5V (Adj.) Startup from
FIGURE 2-29:
Dynamic Load Response
Shutdown.
(1 mA to 500 mA).
FIGURE 2-27:
Power Good (PWRGD)
FIGURE 2-30:
Dynamic Load Response
Timing.
(10 mA to 500 mA).
© 2008 Microchip Technology Inc.
DS22056B-page 15
MCP1825/MCP1825S
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
3-Pin Fixed
Output
5-Pin Fixed
Output
Adjustable
Output
Name
Description
—
1
2
1
2
SHDN
VIN
Shutdown Control Input (active-low)
Input Voltage Supply
1
2
3
3
GND
VOUT
PWRGD
ADJ
Ground
3
4
4
Regulated Output Voltage
Power Good Output
—
—
—
5
—
5
Voltage Adjust/Sense Input
Exposed Pad of the Package (ground potential)
Exposed Pad Exposed Pad Exposed Pad
EP
3.1
Shutdown Control Input (SHDN)
3.5
Power Good Output (PWRGD)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is delayed by 110 µs (typical) from the
time the LDO output is within 92% + 3% (maximum
hysteresis) of the regulated output value on power-up.
This delay time is internally fixed.
3.2
Input Voltage Supply (VIN)
3.6
Output Voltage Adjust Input (ADJ)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the user the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
3.7
Exposed Pad (EP)
3.3
Ground (GND)
The DDPAK and TO-220 package have an exposed
tab on the package. A heat sink may may be mount to
the tab to aid in the removal of heat from the package
during operation. The exposed tab is at the ground
potential of the LDO.
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 120 µA), so a heavy trace is not required.
For applications that have switching or noisy inputs, tie
the GND pin to the return of the output capacitor.
Ground planes help lower inductance and voltage
spikes caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4
Regulated Output Voltage (VOUT)
The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1825/MCP1825S
is stable with ceramic, tantalum and aluminum-electro-
lytic capacitors. See Section 4.3 “Output Capacitor”
for output capacitor selection guidance.
DS22056B-page 16
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
EQUATION 4-2:
4.0
DEVICE OVERVIEW
VOUT – VADJ
⎛
⎝
⎞
⎠
The MCP1825/MCP1825S is a high output current,
Low Dropout (LDO) voltage regulator. The low dropout
voltage of 210 mV typical at 500 mA of current makes
it ideal for battery-powered applications. Unlike other
high output current LDOs, the MCP1825/MCP1825S
only draws a maximum of 220 µA of quiescent current.
The MCP1825 has a shutdown control input and a
power good output.
--------------------------------
R1 = R2
VADJ
Where:
VOUT
VADJ
=
=
LDO Output Voltage
ADJ Pin Voltage
(typically 0.41V)
4.2
Output Current and Current
Limiting
4.1
LDO Output Voltage
The 5-pin MCP1825 LDO is available with either a fixed
output voltage or an adjustable output voltage. The
output voltage range is 0.8V to 5.0V for both versions.
The 3-pin MCP1825S LDO is available as a fixed
voltage device.
The MCP1825/MCP1825S LDO is tested and ensured
to supply a minimum of 500 mA of output current. The
MCP1825/MCP1825S has no minimum output load, so
the output load current can go to 0 mA and the LDO will
continue to regulate the output voltage to within
tolerance.
4.1.1
ADJUST INPUT
The MCP1825/MCP1825S also incorporates an output
current limit. If the output voltage falls below 0.7V due
to an overload condition (usually represents a shorted
load condition), the output current is limited to 1.2A
(typical). If the overload condition is a soft overload, the
MCP1825/MCP1825S will supply higher load currents
of up to 1.5A. The MCP1825/MCP1825S should not be
operated in this condition continuously as it may result
in failure of the device. However, this does allow for
device usage in applications that have higher pulsed
load currents having an average output current value of
500 mA or less.
The adjustable version of the MCP1825 uses the ADJ
pin (pin 5) to get the output voltage feedback for output
voltage regulation. This allows the user to set the
output voltage of the device with two external resistors.
The nominal voltage for ADJ is 0.41V.
Figure 4-1 shows the adjustable version of the
MCP1825. Resistors R1 and R2 form the resistor
divider network necessary to set the output voltage.
With this configuration, the equation for setting VOUT is:
EQUATION 4-1:
Output overload conditions may also result in an over-
temperature shutdown of the device. If the junction
temperature rises above 150°C, the LDO will shut
down the output voltage. See Section 4.8 “Overtem-
perature Protection” for more information on
overtemperature shutdown.
R1 + R2
⎛
⎝
⎞
⎠
------------------
VOUT = VADJ
R2
Where:
VOUT
VADJ
=
=
LDO Output Voltage
ADJ Pin Voltage
(typically 0.41V)
4.3
Output Capacitor
The MCP1825/MCP1825S requires a minimum output
capacitance of 1 µF for output voltage stability.
Ceramic capacitors are recommended because of their
size, cost and environmental robustness qualities.
MCP1825-ADJ
V
OUT
On
R
1
C2
1 µF
1
3
2 4
5
Off
SHDN
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X7R
0805 capacitor has an ESR of 50 milli-ohms.
ADJ
V
IN
C
R
1
2
GND
4.7 µF
FIGURE 4-1:
Typical adjustable output
voltage application circuit.
The allowable resistance value range for resistor R2 is
from 10 kΩ to 200 kΩ. Solving the equation for R1
yields the following equation:
Larger LDO output capacitors can be used with the
MCP1825/MCP1825S
to
improve
dynamic
performance and power supply ripple rejection
performance. A maximum of 22 µF is recommended.
Aluminum-electrolytic capacitors are not recom-
mended for low temperature applications of < -25°C.
© 2008 Microchip Technology Inc.
DS22056B-page 17
MCP1825/MCP1825S
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA (VPWRGD < 0.4V maximum).
4.4
Input Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
VPWRGD_TH
VOUT
TPG
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO as is practical. Larger input capacitors will also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
VOH
TVDET_PWRG
PWRGD
VOL
FIGURE 4-2:
Power Good Timing.
4.5
Power Good Output (PWRGD)
VIN
TOR
70 µs
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see
Section 1.0 “Electrical Characteristics” for Minimum
and Maximum specifications) of its nominal regulation
value.
30 µs
SHDN
TPG
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
power good time delay is started (shown as TPG in the
Electrical Characteristics table). The power good time
delay is fixed at 110 µs (typical). After the time delay
period, the PWRGD output will go high, indicating that
the output voltage is stable and within regulation limits.
VOUT
PWRGD
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 170 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
FIGURE 4-3:
Shutdown.
Power Good Timing from
4.6
Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of VIN, with minimum
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
DS22056B-page 18
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 30 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typically 100 µs. See Figure 4-4 for a timing diagram of
the SHDN input.
4.7
Dropout Voltage and
Undervoltage Lockout
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
2% below the nominal value that was measured with a
VR
+ 0.5V differential applied. The MCP1825/
MCP1825S LDO has a very low dropout voltage
specification of 210 mV (typical) at 500 mA of output
current. See Section 1.0 “Electrical Characteristics”
for maximum dropout voltage specifications.
The MCP1825/MCP1825S LDO operates across an
input voltage range of 2.1V to 6.0V and incorporates
input Undervoltage Lockout (UVLO) circuitry that
keeps the LDO output voltage off until the input voltage
reaches a minimum of 2.00V (typical) on the rising
edge of the input voltage. As the input voltage falls, the
LDO output will remain on until the input voltage level
reaches 1.82V (typical).
TOR
400 ns (typ)
70 µs
30 µs
SHDN
Since the MCP1825/MCP1825S LDO undervoltage
lockout activates at 1.82V as the input voltage is falling,
the dropout voltage specification does not apply for
output voltages that are less than 1.8V.
VOUT
For high-current applications, voltage drops across the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
between the input voltage source and the LDO. For
applications with input voltages near 2.1V, these PCB
trace voltage drops can sometimes lower the input
FIGURE 4-4:
Diagram.
Shutdown Input Timing
voltage enough to trigger
undervoltage lockout.
a shutdown due to
4.8
Overtemperature Protection
The MCP1825/MCP1825S LDO has temperature-
sensing circuitry to prevent the junction temperature
from exceeding approximately 150°C. If the LDO
junction temperature does reach 150°C, the LDO
output will be turned off until the junction temperature
cools to approximately 140°C, at which point the LDO
output will automatically resume normal operation. If
the internal power dissipation continues to be
excessive, the device will again shut off. The junction
temperature of the die is a function of power
dissipation, ambient temperature and package thermal
resistance. See Section 5.0 “Application Circuits/
Issues” for more information on LDO power
dissipation and junction temperature.
© 2008 Microchip Technology Inc.
DS22056B-page 19
MCP1825/MCP1825S
In addition to the LDO pass element power dissipation,
there is power dissipation within the MCP1825/
MCP1825S as a result of quiescent or ground current.
The power dissipation as a result of the ground current
can be calculated using the following equation:
5.0
APPLICATION CIRCUITS/
ISSUES
5.1
Typical Application
The MCP1825/MCP1825S is used for applications that
require high LDO output current and a power good
output.
EQUATION 5-2:
PI(GND) = VIN(MAX) × IVIN
Where:
V
= 2.5V @ 500 mA
OUT
R
PI(GND
=
Power dissipation due to the
quiescent current of the LDO
MCP1825-2.5
On
1
C
1
3
2 4
5
2
VIN(MAX)
IVIN
=
=
Maximum input voltage
10 kΩ
Off
SHDN
10 µF
Current flowing in the VIN pin
with no LDO output current
(LDO quiescent current)
V
IN
3.3V
C
1
4.7 µF
PWRGD
GND
The total power dissipated within the MCP1825/
MCP1825S is the sum of the power dissipated in the
LDO pass device and the P(IGND) term. Because of the
CMOS construction, the typical IGND for the MCP1825/
MCP1825S is 120 µA. Operating at a maximum VIN of
3.465V results in a power dissipation of 0.12 milli-Watts
for a 2.5V output. For most applications, this is small
compared to the LDO pass device power dissipation
and can be neglected.
FIGURE 5-1:
Typical Application Circuit.
5.1.1 APPLICATION CONDITIONS
Package Type
Input Voltage Range
IN maximum
IN minimum
=
=
=
=
=
=
=
=
=
TO-220-5
3.3V ± 5%
3.465V
V
V
3.135V
The maximum continuous operating junction
temperature specified for the MCP1825/MCP1825S is
+125°C. To estimate the internal junction temperature
of the MCP1825/MCP1825S, the total internal power
dissipation is multiplied by the thermal resistance from
junction to ambient (RθJA) of the device. The thermal
resistance from junction to ambient for the TO-220-5
package is estimated at 29.3°C/W.
VDROPOUT (max)
VOUT (typical)
IOUT
0.350V
2.5V
500 mA maximum
0.483W
PDISS (typical)
Temperature Rise
14.2°C
5.2
Power Calculations
EQUATION 5-3:
TJ(MAX) = PTOTAL × RθJA + TAMAX
5.2.1
POWER DISSIPATION
The internal power dissipation within the MCP1825/
MCP1825S is a function of input voltage, output
voltage, output current and quiescent current.
Equation 5-1 can be used to calculate the internal
power dissipation for the LDO.
TJ(MAX) = Maximum continuous junction
temperature
PTOTAL = Total device power dissipation
RθJA = Thermal resistance from junction to
ambient
EQUATION 5-1:
TAMAX = Maximum ambient temperature
PLDO = (VIN(MAX)) – VOUT(MIN)) × IOUT(MAX))
Where:
PLDO
=
LDO Pass device internal
power dissipation
VIN(MAX)
=
=
Maximum input voltage
VOUT(MIN)
LDO minimum output voltage
DS22056B-page 20
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
The maximum power dissipation capability for a
package can be calculated given the junction-to-
ambient thermal resistance and the maximum ambient
temperature for the application. Equation 5-4 can be
used to determine the package maximum internal
power dissipation.
5.3
Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
is calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
EQUATION 5-4:
5.3.1
POWER DISSIPATION EXAMPLE
(TJ(MAX) – TA(MAX)
)
PD(MAX) = ---------------------------------------------------
RθJA
Package
Package Type = TO-220-5
PD(MAX) = Maximum device power dissipation
Input Voltage
TJ(MAX) = maximum continuous junction
temperature
V
IN = 3.3V ± 5%
LDO Output Voltage and Current
TA(MAX) = maximum ambient temperature
V
OUT = 2.5V
RθJA = Thermal resistance from junction-to-
I
OUT = 500 mA
ambient
Maximum Ambient Temperature
A(MAX) = 60°C
Internal Power Dissipation
T
EQUATION 5-5:
TJ(RISE) = PD(MAX) × RθJA
PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX)
PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
x 500 mA
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
PLDO = 0.514 Watts
PD(MAX) = Maximum device power dissipation
RθJA = Thermal resistance from junction-to-
5.3.1.1
Device Junction Temperature Rise
ambient
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction-to-ambient for the application. The
thermal resistance from junction-to-ambient (RθJA) is
derived from EIA/JEDEC standards for measuring
thermal resistance. The EIA/JEDEC specification is
JESD51. The standard describes the test method and
board specifications for measuring the thermal
resistance from junction to ambient. The actual thermal
EQUATION 5-6:
TJ = TJ(RISE) + TA
TJ = Junction temperature
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
TA = Ambient temperature
resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
TJ(RISE) = PTOTAL x RθJA
TJRISE = 0.514 W x 29.3° C/W
TJRISE = 15.06°C
© 2008 Microchip Technology Inc.
DS22056B-page 21
MCP1825/MCP1825S
5.3.1.2
Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
TJ = TJRISE + TA(MAX)
TJ = 15.06°C + 60.0°C
TJ = 75.06°C
5.3.1.3
Maximum Package Power
Dissipation at 60°C Ambient
Temperature
TO-220-5 (29.3°C/W RθJA):
P
D(MAX) = (125°C – 60°C) / 29.3°C/W
D(MAX) = 2.218W
P
DDPAK-5 (31.2°C/Watt RθJA):
P
D(MAX) = (125°C – 60°C)/ 31.2°C/W
D(MAX) = 2.083W
P
From this table, you can see the difference in maximum
allowable power dissipation between the TO-220-5
package and the DDPAK-5 package.
DS22056B-page 22
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
3-Lead DDPAK (MCP1825S)
Example:
XXXXXXXXX
XXXXXXXXX
YYWWNNN
MCP1825S
08EEB
0710256
e
3
1
2
3
1
2
3
3-Lead SOT-223 (MCP1825S)
Example:
XXXXXXX
XXXYYWW
1825S08
EDB0710
NNN
256
3-Lead TO-220 (MCP1825S)
Example:
MCP1825S
12EAB
0710256
XXXXXXXXX
XXXXXXXXX
YYWWNNN
e
3
1
2
3
1
2
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
DS22056B-page 23
MCP1825/MCP1825S
Package Marking Information (Continued)
5-Lead DDPAK (MCP1825)
Example:
MCP1825
XXXXXXXXX
XXXXXXXXX
YYWWNNN
e
3
12EET
0710256
1 2 3 4 5
1 2 3 4 5
5-Lead SOT-223 (MCP1825)
Example:
XXXXXXX
1825-08
XXXYYWW
EDC0710
NNN
256
5-Lead TO-220 (MCP1825)
Example:
MCP1825
XXXXXXXXX
XXXXXXXXX
YYWWNNN
e
3
08EAT^
0710256
1 2 3 4 5
1 2 3 4 5
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS22056B-page 24
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
3-Lead Plastic (EB) [DDPAK]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
L1
D
D1
H
1
N
b
e
BOTTOM VIEW
TOP VIEW
b1
CHAMFER
OPTIONAL
C2
A
φ
c
L
A1
Units
INCHES
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
3
.100 BSC
Overall Height
Standoff §
A
.160
.000
.380
.245
.330
.549
.270
.014
.045
.020
.045
.068
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
.190
.010
.420
–
A1
E
Overall Width
Exposed Pad Width
E1
D
Molded Package Length
Overall Length
.380
.625
–
H
Exposed Pad Length
Lead Thickness
Pad Thickness
Lower Lead Width
Upper Lead Width
Foot Length
D1
c
.029
.065
.039
.070
.110
.067
8°
C2
b
b1
L
Pad Length
L1
φ
Foot Angle
0°
Notes:
1. § Significant Characteristic.
2. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-011B
© 2008 Microchip Technology Inc.
DS22056B-page 25
MCP1825/MCP1825S
3-Lead Plastic Small Outline Transistor (DB) [SOT-223]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
b2
E1
E
3
2
1
e
e1
A2
c
A
φ
b
L
A1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Leads
Lead Pitch
N
e
3
2.30 BSC
4.60 BSC
–
Outside Lead Pitch
Overall Height
Standoff
e1
A
–
1.80
0.10
1.70
7.30
3.70
6.70
0.35
0.84
3.10
–
A1
A2
E
0.02
1.50
6.70
3.30
6.30
0.23
0.60
2.90
0.75
0°
–
Molded Package Height
Overall Width
1.60
7.00
3.50
6.50
0.30
0.76
3.00
–
Molded Package Width
Overall Length
Lead Thickness
Lead Width
E1
D
c
b
Tab Lead Width
Foot Length
b2
L
Lead Angle
φ
–
10°
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-032B
DS22056B-page 26
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢖꢗꢘꢆꢙꢍꢏꢒꢁꢚꢚꢀꢛ
ꢜꢔꢊꢃꢝ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ
ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ
© 2008 Microchip Technology Inc.
DS22056B-page 27
MCP1825/MCP1825S
3-Lead Plastic Transistor Outline (AB) [TO-220]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
CHAMFER
E
A
OPTIONAL
P
A1
φ
Q
H1
D
D1
L1
L
b2
2
N
1
b
c
e
A2
e1
Units
INCHES
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
3
.100 BSC
Overall Pin Pitch
Overall Height
Tab Thickness
Base to Lead
Overall Width
e1
A
.200 BSC
.140
.020
.080
.357
.100
.560
.330
.230
.139
.500
–
–
–
.190
.055
.115
.420
.120
.650
.355
.270
.156
.580
.250
.024
.040
.070
A1
A2
E
–
–
Mounting Hole Center
Overall Length
Q
–
D
–
Molded Package Length
Tab Length
D1
H1
φP
L
–
–
Mounting Hole Diameter
Lead Length
–
–
Lead Shoulder
L1
c
–
Lead Thickness
Lead Width
.012
.015
.045
–
b
.027
.057
Shoulder Width
b2
Notes:
1. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-034B
DS22056B-page 28
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
5-Lead Plastic (ET) [DDPAK]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
L1
D
D1
H
1
N
b
BOTTOM VIEW
e
TOP VIEW
CHAMFER
OPTIONAL
C2
A
φ
c
L
A1
Units
INCHES
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
5
.067 BSC
Overall Height
Standoff §
A
.160
.000
.380
.245
.330
.549
.270
.014
.045
.020
.068
–
–
–
–
–
–
–
–
–
–
–
–
–
–
.190
.010
.420
–
A1
E
Overall Width
Exposed Pad Width
E1
D
Molded Package Length
Overall Length
Exposed Pad Length
Lead Thickness
Pad Thickness
Lead Width
.380
.625
–
H
D1
c
.029
.065
.039
.110
.067
8°
C2
b
Foot Length
L
Pad Length
L1
φ
Foot Angle
0°
Notes:
1. § Significant Characteristic.
2. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-012B
© 2008 Microchip Technology Inc.
DS22056B-page 29
MCP1825/MCP1825S
ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢖ!ꢘꢆꢙꢍꢏꢒꢁꢚꢚꢀꢛ
ꢜꢔꢊꢃꢝ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ
ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ
D
b2
E
E1
3
4
2
N
1
e
e1
A2
c
A
φ
L
b
A1
.ꢋꢒꢄꢈ
ꢕ/00/ꢕ + 1ꢗ
ꢝꢒꢇꢆꢋꢈꢒꢁꢋꢃ0ꢒꢇꢒꢄꢈ
ꢕ/2
23ꢕ
(
ꢜꢛ#$ꢃ)ꢗ*
(ꢛ"6ꢃ)ꢗ*
M
"ꢛ"9
ꢜꢛ9"
$ꢛ""
;ꢛ("
9ꢛ("
"ꢛ#6
"ꢛ'($
;ꢛ""
M
ꢕ%4
2ꢊꢇ5ꢆꢂꢃꢁꢘꢃ0ꢆꢍꢐꢈ
0ꢆꢍꢐꢃꢖꢒꢄꢉꢅ
3ꢊꢄꢈꢒꢐꢆꢃ0ꢆꢍꢐꢃꢖꢒꢄꢉꢅ
3-ꢆꢂꢍꢔꢔꢃ7ꢆꢒꢏꢅꢄ
ꢗꢄꢍꢋꢐꢁꢘꢘ
ꢕꢁꢔꢐꢆꢐꢃꢖꢍꢉꢎꢍꢏꢆꢃ7ꢆꢒꢏꢅꢄ
3-ꢆꢂꢍꢔꢔꢃ:ꢒꢐꢄꢅ
ꢕꢁꢔꢐꢆꢐꢃꢖꢍꢉꢎꢍꢏꢆꢃ:ꢒꢐꢄꢅ
3-ꢆꢂꢍꢔꢔꢃ0ꢆꢋꢏꢄꢅ
0ꢆꢍꢐꢃ+ꢅꢒꢉꢎꢋꢆꢈꢈ
0ꢆꢍꢐꢃ:ꢒꢐꢄꢅ
2
ꢆ
ꢆꢜ
%
%ꢜ
%#
ꢜ
ꢝ
ꢉ
5
5#
0
ꢀ
M
ꢜꢛ6"
"ꢛꢜ"
ꢜꢛ9(
$ꢛ#9
;ꢛ((
9ꢛ((
"ꢛ;#
"ꢛ(ꢜ
;ꢛ"(
ꢜꢛꢜ'
6ꢞ
"ꢛ"#
ꢜꢛ((
9ꢛ69
;ꢛ'(
9ꢛ'(
"ꢛ#'
"ꢛ'ꢜ
#ꢛ<(
"ꢛ<ꢜ
"ꢞ
+ꢍ5ꢃ0ꢆꢍꢐꢃ:ꢒꢐꢄꢅ
ꢀꢁꢁꢄꢃ0ꢆꢋꢏꢄꢅ
0ꢆꢍꢐꢃ%ꢋꢏꢔꢆ
'ꢞ
ꢜꢔꢊꢃꢉꢝ
ꢜꢛ ꢝꢒꢇꢆꢋꢈꢒꢁꢋꢈꢃꢝꢃꢍꢋꢐꢃ ꢜꢃꢐꢁꢃꢋꢁꢄꢃꢒꢋꢉꢔꢊꢐꢆꢃꢇꢁꢔꢐꢃꢘꢔꢍꢈꢅꢃꢁꢂꢃꢌꢂꢁꢄꢂꢊꢈꢒꢁꢋꢈꢛꢃꢕꢁꢔꢐꢃꢘꢔꢍꢈꢅꢃꢁꢂꢃꢌꢂꢁꢄꢂꢊꢈꢒꢁꢋꢈꢃꢈꢅꢍꢔꢔꢃꢋꢁꢄꢃꢆ!ꢉꢆꢆꢐꢃ"ꢛꢜ#$ꢃꢇꢇꢃꢌꢆꢂꢃꢈꢒꢐꢆꢛ
#ꢛ ꢝꢒꢇꢆꢋꢈꢒꢁꢋꢒꢋꢏꢃꢍꢋꢐꢃꢄꢁꢔꢆꢂꢍꢋꢉꢒꢋꢏꢃꢌꢆꢂꢃ%ꢗꢕ ꢃ&ꢜ'ꢛ(ꢕꢛ
)ꢗ*ꢙ )ꢍꢈꢒꢉꢃꢝꢒꢇꢆꢋꢈꢒꢁꢋꢛꢃ+ꢅꢆꢁꢂꢆꢄꢒꢉꢍꢔꢔ,ꢃꢆ!ꢍꢉꢄꢃ-ꢍꢔꢊꢆꢃꢈꢅꢁꢑꢋꢃꢑꢒꢄꢅꢁꢊꢄꢃꢄꢁꢔꢆꢂꢍꢋꢉꢆꢈꢛ
ꢕꢒꢉꢂꢁꢉꢅꢒꢌ +ꢆꢉꢅꢋꢁꢔꢁꢏ, ꢝꢂꢍꢑꢒꢋꢏ *"'>ꢜ;$)
DS22056B-page 30
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢖ!ꢘꢆꢙꢍꢏꢒꢁꢚꢚꢀꢛ
ꢜꢔꢊꢃꢝ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ
ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ
© 2008 Microchip Technology Inc.
DS22056B-page 31
MCP1825/MCP1825S
5-Lead Plastic Transistor Outline (AT) [TO-220]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
A
E
φP
CHAMFER
OPTIONAL
A1
Q
H1
D
D1
L
N
1
2
3
e
c
b
e1
A2
Units
INCHES
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
5
.067 BSC
Overall Pin Pitch
Overall Height
Overall Width
Overall Length
e1
A
.268 BSC
.140
.380
.560
.330
.204
.020
.100
.139
.482
.080
.012
.015
–
–
.190
.420
.650
.355
.293
.055
.120
.156
.590
.115
.025
.040
E
D
–
Molded Package Length
Tab Length
D1
H1
A1
Q
–
–
Tab Thickness
–
Mounting Hole Center
Mounting Hole Diameter
Lead Length
–
φP
L
–
–
Base to Bottom of Lead
Lead Thickness
A2
c
–
–
Lead Width
b
.027
Notes:
1. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-036B
DS22056B-page 32
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
APPENDIX A: REVISION HISTORY
Revision B (February 2008)
The following is the list of modifications
1. Updated Figure 2-4, Figure 2-5, Figure 2-16,
Figure 2-29, and Figure 2-30.
2. Updated package outline drawings and landing
pattern drawings to Section 6.0 “Packaging
Information”.
3. Updated Appendix A: “Revision History”.
Revision A (August 2007)
• Original Release of this Document.
© 2008 Microchip Technology Inc.
DS22056B-page 33
MCP1825/MCP1825S
NOTES:
DS22056B-page 34
© 2008 Microchip Technology Inc.
MCP1825/MCP1825S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
XX
X
X
X/
XX
a)
b)
c)
d)
e)
f)
MCP1825-0802E/XX: 0.8V LDO Regulator
Output Feature Tolerance Temp. Package
Voltage
MCP1825-1202E/XX: 1.2V LDO Regulator
MCP1825-1802E/XX: 1.8V LDO Regulator
MCP1825-2502E/XX: 2.5V LDO Regulator
MCP1825-3002E/XX: 3.0V LDO Regulator
MCP1825-3302E/XX: 3.3V LDO Regulator
MCP1825-5002E/XX: 5.0V LDO Regulator
MCP1825-ADJE/XX: ADJ LDO Regulator
Code
Device:
MCP1825: 500 mA Low Dropout Regulator
MCP1825T: 500 mA Low Dropout Regulator
Tape and Reel
MCP1825S: 500 mA Low Dropout Regulator
MCP1825ST: 500 mA Low Dropout Regulator
Tape and Reel
g)
h)
a)
b)
c)
d)
e)
f)
MCP1825S-0802E/YY:0.8V LDO Regulator
MCP1825S-1202E/YY:1.2V LDO Regulator
MCP1825S-1802E/YY:1.8V LDO Regulator
MCP1825S-2502E/YY:2.5V LDO Regulator
MCP1825S-2502E/YY:3.0V LDO Regulator
MCP1825S-3302E/YY:3.3V LDO Regulator
MCP1825S-5002E/YY:5.0V LDO Regulator
Output Voltage *:
08
12
18
25
30
33
50
=
=
=
=
=
=
=
0.8V “Standard”
1.2V “Standard”
1.8V “Standard”
2.5V “Standard”
3.0V “Standard”
3.3V “Standard”
5.0V “Standard”
g)
ADJ = Adjustable Output Voltage ** (MCP1825 Only)
*Contact factory for other output voltage options
** When ADJ is used, the “extra feature code” and
“tolerance” columns do not apply. Refer to examples.
XX
YY
=
=
=
AT for 5LD TO-220 package
DC for 5LD SOT-223 package
ET for 5LD DDPAK package
Extra Feature Code:
Tolerance:
0
2
E
=
=
=
Fixed
2.5% (Standard)
-40°C to +125°C
=
=
=
AB for 3LD TO-220 package
DB for 3LD SOT-223 package
EB for 3LD DDPAK package
Temperature:
Package Type:
AB
AT
EB
ET
DB
DC
=
=
=
=
=
=
Plastic Transistor Outline, TO-220, 3-lead
Plastic Transistor Outline, TO-220, 5-lead
Plastic, DDPAK, 3-lead
Plastic, DDPAK, 5-lead
Plastic Small Transistor Outline, SOT-223, 3-lead
Plastic Small Transistor Outline, SOT-223, 5-lead
Note: ADJ (Adjustable) only available in 5-lead version.
© 2008 Microchip Technology Inc.
DS22056B-page 35
MCP1825/MCP1825S
NOTES:
DS22056B-page 36
© 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
DS22056B-page 37
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS22056B-page 38
© 2008 Microchip Technology Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明