MCP19110T-E/MQ_技术文档

MCP19110/11

Digitally-Enhanced Power Analog Controller

with Integrated Synchronous Driver

Synchronous Buck Features

Microcontroller Features

• Precision 8 MHz Internal Oscillator Block:

- Factory Calibrated

• Input Voltage: 4.5V to 32V

• Output Voltage: 0.5V to 3.6V

- Greater than 3.6V requires external divider

• Switching Frequency: 100 kHz to 1.6 MHz

• Quiescent Current: 5 mA Typical

• High-Drive:

• Interrupt Capable

- Firmware

- Interrupt-on-Change Pins

• Only 35 Instructions to Learn

• 4096 Words On-Chip Program Memory

• High Endurance Flash:

- +5V Gate Drive

- 1A/2A Source Current

- 1A/2A Sink Current

- 100,000 write Flash Endurance

- Flash Retention: >40 years

• Low-Drive:

• Watchdog Timer (WDT) with Independent

Oscillator for Reliable Operation

• Programmable Code Protection

- +5V Gate Drive

- 2A Source Current

- 4A Sink Current

• In-Circuit Debug (ICD) via Two Pins (MCP19111)

• Peak Current Mode Control

• Differential Remote Output Sense

• Multi-Phase Systems:

- Master or Slave

• In-Circuit Serial Programming™ (ICSP™) via Two

Pins

• 11 I/O Pins and One Input-Only Pin (MCP19110)

- Three Open-Drain Pins

- Frequency Synchronized

- Common Error Signal

• Multiple Output Systems:

- Master or Slave

• 14 I/O Pins and One Input-Only Pin (MCP19111)

- Three Open-Drain Pins

• Analog-to-Digital Converter (ADC):

- 10-bit Resolution

- Frequency Synchronized

- AEC-Q100 Qualified

- 12 Internal Channels

- Eight External Channels

• Configurable Parameters:

- Overcurrent Limit

• Timer0: 8-bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- Input Undervoltage Lockout

- Output Overvoltage

- 16-bit Timer/Counter with Prescaler

- Two Selectable Clock Sources

• Timer2: 8-Bit Timer/Counter with Prescaler

- 8-bit Period Register

- Output Undervoltage

- Internal Analog Compensation

- Soft Start Profile

•

I²C Communication:

- Synchronous Driver Dead Time

- Switching Frequency

• Thermal Shutdown

- 7-bit Address Masking

- Two Dedicated Address Registers

- SMBus/PMBus^TMCompatibility

 2013-2016 Microchip Technology Inc.

DS20002331D-page 1

MCP19110/11

Pin Diagram – 24-Pin QFN (MCP19110)

1

V_DD

GPA0

18

17

16

15

14

13

2

BOOT

GPA1

3

4

5

6

GPA2

GPA3

HDRV

PHASE

V_DR

MCP19110

GPA7

GPA6

EXP-25

LDRV

DS20002331D-page 2

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 1:

I/O

24-PIN SUMMARY

Basic

Additional

GPA0

GPA1

GPA2

1

2

3

Y

AN0

AN1

AN2

—

IOC

Y

—

Analog Debug Output ⁽¹⁾

Sync. Signal In/Out ^{(2, 3)}

—

T0CKI

IOC

INT

GPA3

GPA4

5

8

Y

N

AN3

—

IOC

Y

N

—

GPA5

GPA6

GPA7

GPB0

GPB1

GPB2

V_IN

7

6

N

Y

N

—

IOC⁽⁴⁾

IOC

—

Y⁽⁵⁾

N

MCLR

ICSPDAT

ICSPCLK

—

5

—

SCL

SDA

—

N

—

9

—

N

—

23

24

11

14

AN4

AN5

—

Y

—

Error Signal In/Out ⁽³⁾

—

Y

—

V_IN

Device Input Voltage

V_DR

—

V_DR

Gate Drive Supply Input

Voltage

V_DD

GND

P_GND

LDRV

18

10

12

13

N

—

V_DD

GND

—

Internal Regulator Output

Small Signal Ground

Large Signal Ground

—

Low-Side MOSFET

Connection

HDRV

16

N

—

High-Side MOSFET

Connection

PHASE

BOOT

+V_SEN

15

17

21

N

—

Switch Node

Floating Bootstrap Supply

Output Voltage

Differential Sense

-V_SEN

22

N

—

Output Voltage

Differential Sense

+I_SEN

-I_SEN

20

19

N

—

Current Sense Input

Note 1: The Analog Debug Output is selected when the ATSTCON<BNCHEN> bit is set.

2: Selected when device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits

in the BUFFCON register.

3: Selected when device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in

the BUFFCON register.

4: The IOC is disabled when MCLR is enabled.

5: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 3

MCP19110/11

Pin Diagram – 28-Pin QFN (MCP19111)

1

21

20

19

18

17

16

15

GPB6

V_DD

GPA0

2

GPA1

3

BOOT

GPA2

4

GPB4

HDRV

PHASE

V_DR

MCP19111

5

6

7

GPA3

GPA7

GPA6

EXP-29

LDRV

DS20002331D-page 4

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 2:

I/O

28-PIN SUMMARY

Basic

Additional

GPA0

GPA1

GPA2

1

2

3

Y

AN0

AN1

AN2

—

IOC

Y

—

Analog Debug Output ⁽¹⁾

Sync. Signal In/Out ^{(2, 3)}

—

T0CKI

IOC

INT

GPA3

GPA4

5

9

Y

N

AN3

—

IOC

Y

N

—

GPA5

GPA6

GPA7

GPB0

GPB1

GPB2

GPB4

8

7

N

Y

—

IOC⁽⁴⁾

IOC

Y⁽⁵⁾

N

MCLR

—

6

—

SCL

SDA

—

N

—

10

26

28

4

—

N

—

AN4

AN5

AN6

Y

—

Error Signal In/Out ⁽³⁾

—

Y

—

Y

ICSPDAT

ICDDAT

GPB5

27

Y

AN7

—

IOC

Y

ICSPCLK

ICDCLK

Alternate Sync

Signal In/Out ^{(2, 3)}

GPB6

GPB7

V_IN

21

11

13

16

N

—

IOC

—

Y

—

V_IN

V_DR

Device Input Voltage

V_DR

—

Gate Drive Supply Input

Voltage

V_DD

GND

P_GND

LDRV

20

12

14

15

N

—

V_DD

GND

—

Internal Regulator Output

Small Signal Ground

Large Signal Ground

—

Low-Side MOSFET

Connection

HDRV

18

N

—

High-Side MOSFET

Connection

PHASE

BOOT

+V_SEN

17

19

24

N

—

Switch Node

Floating Bootstrap Supply

Output Voltage

Differential Sense

-V_SEN

25

N

—

Output Voltage

Differential Sense

+I_SEN

-I_SEN

23

22

N

—

Current Sense Input

Note 1: The Analog Debug Output is selected when the ATSTCON<BNCHEN> bit is set.

2: Selected when device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits

in the BUFFCON register.

3: Selected when device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in

the BUFFCON register.

4: The IOC is disabled when MCLR is enabled.

5: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 5

MCP19110/11

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Pin Description ........................................................................................................................................................................... 12

3.0 Functional Description................................................................................................................................................................ 17

4.0 Electrical Characteristics............................................................................................................................................................ 23

5.0 Digital Electrical Characteristics ................................................................................................................................................. 29

6.0 Configuring the MCP19110/11.................................................................................................................................................... 37

7.0 Typical Performance Curves ...................................................................................................................................................... 53

8.0 System Bench Testing................................................................................................................................................................ 57

9.0 Device Calibration ...................................................................................................................................................................... 59

10.0 Relative Efficiency Measurement ............................................................................................................................................... 67

11.0 Memory Organization................................................................................................................................................................. 69

12.0 Device Configuration.................................................................................................................................................................. 81

13.0 Oscillator Modes......................................................................................................................................................................... 83

14.0 Resets ........................................................................................................................................................................................ 85

15.0 Interrupts .................................................................................................................................................................................... 93

16.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 101

17.0 Watchdog Timer (WDT)............................................................................................................................................................ 103

18.0 Flash Program Memory Control ............................................................................................................................................... 105

19.0 I/O Ports ....................................................................................................................................................................................111

20.0 Interrupt-On-Change ................................................................................................................................................................ 121

21.0 Internal Temperature Indicator Module..................................................................................................................................... 123

22.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 125

23.0 Timer0 Module.......................................................................................................................................................................... 135

24.0 Timer1 Module with Gate Control............................................................................................................................................. 137

25.0 Timer2 Module.......................................................................................................................................................................... 140

26.0 PWM Module............................................................................................................................................................................ 143

27.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 147

28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 191

29.0 Instruction Set Summary.......................................................................................................................................................... 193

30.0 Development Support............................................................................................................................................................... 203

31.0 Packaging Information.............................................................................................................................................................. 207

Appendix A: Revision History............................................................................................................................................................. 213

Index .................................................................................................................................................................................................. 215

The Microchip Web Site..................................................................................................................................................................... 221

Customer Change Notification Service .............................................................................................................................................. 221

Customer Support.............................................................................................................................................................................. 221

Product Identification System............................................................................................................................................................. 223

DS20002331D-page 6

 2013-2016 Microchip Technology Inc.

MCP19110/11

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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

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 2013-2016 Microchip Technology Inc.

DS20002331D-page 7

MCP19110/11

NOTES:

DS20002331D-page 8

 2013-2016 Microchip Technology Inc.

MCP19110/11

After initial device configuration using Microchip’s

MPLAB^®X Integrated Development Environment (IDE)

software, the PMBus or I²C can be used by a host to

communicate with, or modify, the operation of the

MCP19110/11.

1.0

DEVICE OVERVIEW

The MCP19110/11 is a highly integrated, mixed signal,

analog pulse-width modulation (PWM) current mode

controller with an integrated microcontroller core for

synchronous DC/DC step-down applications. Since the

MCP19110/11 uses traditional analog control circuitry

to regulate the output of the DC/DC converter, the

integration of the PIC^®microcontroller mid-range core

is used to provide complete customization of device

operating parameters, start-up and shut down profiles,

protection levels and fault handling procedures.

Two internal linear regulators generate two 5V rails.

One 5V rail is used to provide power for the internal

analog circuitry and is contained on-chip. The second

5V rail provides power to the PIC device and is present

on the V_DDpin. It is recommended that a 1 µF capacitor

be placed between V_DDand P_GND. The V_DDpin may

also be directly connected to the V_DRpin, or connected

through a low-pass RC filter. The V_DRpin provides

power to the internal synchronous driver.

The MCP19110/11 is designed to efficiently operate

from a single 4.5V to 32V supply. It features integrated

synchronous drivers, bootstrap device, internal linear

regulator and 4 kW nonvolatile memory all in a

space-saving 24-pin 4 mm x 4mm QFN package

(MCP19110) or 28-pin 5 mm x 5 mm QFN package

(MCP19111).

FIGURE 1-1:

TYPICAL APPLICATION CIRCUIT

V_IN

GPA6

GPB1

V_IN

GPA0

GPA2

GPB2

GPA3

GPB7

GPB6

GPA1

GPA4

GPA7

GPB0

HDRV

BOOT

PHASE

LDRV

V_DD

TRACK

PGOOD

CNTL

+V_OUT

-V_OUT

ADDR1

ADDR0

SYNC

V_DR

MCP19111

+I_SEN

SMBus Alert

SCL

-I_SEN

+V_SEN

-V_SEN

SDA

ICDDAT

GPB4

P_GND

GND

®

MPLAB X ICD

ICDCLK

MCLR

GPB5

GPA5

Programmer

 2013-2016 Microchip Technology Inc.

DS20002331D-page 9

MCP19110/11

FIGURE 1-3:

MICROCONTROLLER CORE BLOCK DIAGRAM

Configuration

13

8

PORTA

Data Bus

Program Counter

GPA0

GPA1

GPA2

GPA3

GPA4

GPA5

Flash

4K x 14

Program

Memory

RAM

256

bytes

8 Level Stack

(13-bit)

File

Registers

Program

Bus

14

GPA6

GPA7

RAM Addr

9

Addr MUX

Instruction reg

Indirect

Addr

7

Direct Addr

8

PORTB

GPB0

GPB1

GPB2

FSR reg

STATUS reg

8

GPB4 (MCP19111

)

3

MUX

GPB5 (MCP19111

)

Power-up

Timer

GPB6 (MCP19111

)

Instruction

Decode &

Control

GPB7 (MCP19111

ALU

Power-on

Reset

8

Timing

Generation

TESTCLKIN

SDA

SCL

W reg

Watchdog

Timer

MSSP

8 MHz Internal

Oscillator

V_IN

VSS

MCLR

PMDATL

Self read/

write flash

memory

Timer2

Timer0

Timer1

EEADDR

T0CKI

Analog Interface

Registers

PWM

 2013-2016 Microchip Technology Inc.

DS20002331D-page 11

MCP19110/11

2.0

PIN DESCRIPTION

The MCP19110/11 family of devices feature pins that

have multiple functions associated with each pin.

Table 2-1 provides a description of the different func-

tions. See Section 2.1 “Detailed Pin Functional

Description” for more detailed information.

TABLE 2-1:

MCP19110/11 PINOUT DESCRIPTION

Input Output

Name

Function

Description

Type

GPA0/AN0/ANALOG_TEST

GPA1/AN1/CLKPIN

GPA0

AN0

TTL

AN

—

CMOS General purpose I/O

—

A/D Channel 0 input.

Internal analog signal multiplexer output ⁽¹⁾

ANALOG_TEST

GPA1

TTL

AN

—

CMOS General purpose I/O

AN1

—

A/D Channel 1 input.

Switching frequency clock input or output ^{(2 ,3)}

CLKPIN

GPA2

GPA2/AN2/T0CKI/INT

TTL

AN

ST

CMOS General purpose I/O

AN2

—

A/D Channel 2 input

Timer0 clock input

External interrupt

T0CKI

INT

ST

GPA3/AN3

GPA3

TTL

AN

TTL

CMOS General purpose I/O

AN3

—

A/D Channel 3 input

General purpose I/O

GPA4

OD

GPA5/MCLR

GPA5

TTL

—

General purpose input only

MCLR

GPA6

ICSPDAT

GPA7

SCL

ST

Master Clear with internal pull-up

GPA6/ICSPDAT

CMOS General purpose I/O

CMOS Serial Programming Data I/O (MCP19110 Only)

GPA7/SCL/ICSPCLK

ST

I²C

ST

OD

—

General purpose open-drain I/O

I²C clock

ICSPCLK

GPB0

SDA

Serial Programming Clock (MCP19110 Only)

General purpose I/O

I²C data input/output

GPB0/SDA

TTL

I²C

TTL

AN

—

OD

GPB1/AN4/EAPIN

GPB1

AN4

CMOS General purpose I/O

—

A/D Channel 4 input

Error amplifier signal input/output ⁽³⁾

EAPIN

GPB2

AN5

GPB2/AN5

TTL

AN

TTL

AN

ST

CMOS General purpose I/O

A/D Channel 5 input

CMOS General purpose I/O

A/D Channel 6 input

CMOS Serial Programming Data I/O

—

GPB4/AN6/ICSPDAT

(MCP19111 Only)

GPB4

AN6

—

ICSPDAT

Legend:

AN = Analog input or output CMOS =CMOS compatible input or output

TTL = TTL compatible input ST

OD = Open Drain

=Schmitt Trigger input with CMOS levels I²C = Schmitt Trigger input with I²C

Note 1: Analog Test is selected when the ATSTCON<BNCHEN> bit is set.

2: Selected when device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits

in the BUFFCON register.

3: Selected when device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in

the BUFFCON register.

DS20002331D-page 12

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 2-1:

MCP19110/11 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

GPB5/AN7/ICSPCLK/

ALT_CLKPIN

(MCP19111 Only)

GPB5

AN7

TTL

AN

ST

—

CMOS General purpose I/O

—

A/D Channel 7 input

ISCPCLK

ALT_CLKPIN

Serial Programming Clock

Alternate switching frequency clock input

or output ^(2,3)

GPB6 (MCP19111 Only)

GPB6

GPB7

V_IN

TTL

—

CMOS General purpose I/O

GPB7 (MCP19111 Only)

V_IN

—

Device input supply voltage

V_DD

—

Internal +5V LDO output pin

Gate drive supply input voltage pin

Small signal quiet ground

V_DR

—

GND

P_GND

LDRV

GND

P_GND

LDRV

—

Large signal power ground

—

High-current drive signal connected to the gate

of the low-side MOSFET

HDRV

—

Floating high-current drive signal connected to

the gate of the high-side MOSFET

PHASE

BOOT

+V_SEN

PHASE

BOOT

+V_SEN

—

Synchronous buck switch node connection

Floating bootstrap supply

Positive input of the output voltage sense

differential amplifier

-V_SEN

—

Negative input of the output voltage sense

differential amplifier

+I_SEN

-I_SEN

EP

+I_SEN

-I_SEN

—

Current sense input

Exposed Thermal Pad

Legend:

AN = Analog input or output CMOS =CMOS compatible input or output

TTL = TTL compatible input ST

OD = Open Drain

=Schmitt Trigger input with CMOS levels I²C = Schmitt Trigger input with I²C

Note 1: Analog Test is selected when the ATSTCON<BNCHEN> bit is set.

2: Selected when device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits

in the BUFFCON register.

3: Selected when device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in

the BUFFCON register.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 13

MCP19110/11

AN3 is an input to the A/D. To configure this pin to be

read by the A/D on channel 3, bits TRISA3 and ANSA3

must be set.

2.1

Detailed Pin Functional

Description

2.1.1

GPA0 PIN

2.1.5

GPA4 PIN

GPA0 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPA. An

internal weak pull-up and interrupt-on-change are also

available.

GPA4 is a true open-drain general purpose pin whose

data direction is controlled in TRISGPA. There is no

internal connection between this pin and device V_DD

making this pin ideal to be used as an SMBus Alert pin.

This pin does not have a weak pull-up, but interrupt-on-

change is available.

,

AN0 is an input to the A/D. To configure this pin to be

read by the A/D on channel 0, bits TRISA0 and ANSA0

must be set.

2.1.6

GPA5 PIN

When the ATSTCON<BNCHEN> bit is set, this pin is

configured as the ANALOG_TEST function. It is a

buffered output of the internal analog signal

multiplexer. Signals present on this pin are controlled

by the BUFFCON register, see Register 8-2.

GPA5 is a general purpose TTL input-only pin. An inter-

nal weak pull-up and interrupt-on-change are also

available.

For programming purposes, this pin is to be connected

to the MCLR pin of the serial programmer. See

Section 28.0 “In-Circuit Serial Programming™

(ICSP™)” for more information.

2.1.2

GPA1 PIN

GPA1 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPA. An

internal weak pull-up and interrupt-on-change are also

available.

2.1.7

GPA6 PIN

GPA6 is a general purpose CMOS input/output pin

whose data direction is controlled in TRISGPA. An

interrupt-on-change is also available.

AN1 is an input to the A/D. To configure this pin to be

read by the A/D on channel 1, bits TRISA1 and ANSA1

must be set.

On the MCP19110, the ISCPDAT is the serial program-

ming data input function. This is used in conjunction

with ICSPCLK to serial program the device. This pin

function is only implemented on the MCP19110.

When the MCP19110/11 is configured as a multiple

output or multi-phase MASTER or SLAVE, this pin is

configured

synchronization input or output, CLKPIN. See

Section 3.10.6 “Multi-Phase System” and

to

be

the

switching

frequency

2.1.8

GPA7 PIN

Section 3.10.7 “Multiple Output System” for more

information.

GPA7 is a true open-drain general purpose pin whose

data direction is controlled in TRISGPA. There is no

internal connection between this pin and device V_DD

This pin does not have a weak pull-up, but interrupt-on-

change is available.

When the MCP19110/11 is configured for I²C

communication (see Section 27.2 “I²C Mode

Overview”), GPA7 functions as the I²C clock, SCL.

.

2.1.3

GPA2 PIN

GPA2 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPA. An

internal weak pull-up and interrupt-on-change are also

available.

AN2 is an input to the A/D. To configure this pin to be

read by the A/D on channel 2, bits TRISA2 and ANSA2

must be set.

On the MCP19110, the ISCPCLK is the serial

programming clock function. This is used in conjunction

with ICSPDAT to serial program the device. This pin

function is only implemented on the MCP19110.

When bit T0CS is set, the T0CKI function is enabled.

See Section 23.0 “Timer0 Module” for more

information.

2.1.9

GPB0 PIN

GPA2 can also be configured as an external interrupt

by setting of the INTE bit. See Section 15.2

“GPA2/INT Interrupt” for more information.

GPB0 is a true open-drain general purpose pin whose

data direction is controlled in TRISGPB. There is no

internal connection between this pin and device V_DD

This pin does not have weak pull-up, but

interrupt-on-change is available.

.

a

2.1.4

GPA3 PIN

When the MCP19110/11 is configured for I²C

communication (see Section 27.2 “I²C Mode

Overview”), GPB0 functions as the I²C clock, SDA.

GPA3 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPA. An

internal weak pull-up and interrupt-on-change are also

available.

DS20002331D-page 14

 2013-2016 Microchip Technology Inc.

MCP19110/11

This pin can also be configured as an alternate switch-

ing frequency synchronization input or output, ALT_-

CLKPIN, for use in multiple output or multi-phase

systems. See Section 19.1 “Alternate Pin Function”

for more information.

2.1.10

GPB1 PIN

GPB1 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPB. An

internal weak pull-up and interrupt-on-change are also

available.

AN4 is an input to the A/D. To configure this pin to be

read by the A/D on channel 4, bits TRISB1 and ANSB1

must be set.

2.1.14

GPB6 PIN

This pin and associated functions is only available on

the MCP19111 device.

When the MCP19110/11 is configured as a multiple

output or multi-phase MASTER or SLAVE, this pin is

configured to be the error amplifier signal input or out-

put. See Section 3.10.6 “Multi-Phase System” and

Section 3.10.7 “Multiple Output System”, for more

information.

GPB6 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPB. An

internal weak pull-up and interrupt-on-change are also

available.

2.1.15

GPB7 PIN

This pin and associated functions is only available on

the MCP19111 device.

2.1.11

GPB2 PIN

GPB2 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPB. An

internal weak pull-up and interrupt-on-change are also

available.

GPB7 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPB. An

internal weak pull-up and interrupt-on-change are also

available.

AN5 is an input to the A/D. To configure this pin to be

read by the A/D on channel 5, bits TRISB2 and ANSB2

must be set.

2.1.16

V

IN

Device input power connection pin. It is recommended

that capacitance be placed between this pin and the

GND pin of the device.

2.1.12

GPB4 PIN

This pin and its associated functions are only available

on the MCP19111 device.

2.1.17

V

DD

GPB4 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPB. An

internal weak pull-up and interrupt-on-change are also

available.

The output of the internal +5.0V regulator is connected

to this pin. It is recommended that a 1.0 µF bypass

capacitor be connected between this pin and the GND

pin of the device. The bypass capacitor should be

placed physically close to the device.

AN6 is an input to the A/D. To configure this pin to be

read by the A/D on channel 6, bits TRISB4 and ANSB4

must be set.

2.1.18

V

DR

The 5V supply for the low-side driver is connected to

this pin. The pin can be connected by an RC filter to the

V_DDpin.

On the MCP19111, the ISCPDAT is the serial program-

ming data input function. This is used in conjunction

with ICSPCLK to serial program the device. This pin

function is only implemented on the MCP19111.

2.1.19

GND PIN

2.1.13

GBP5 PIN

GND is the small signal ground connection pin. This pin

should be connected to the exposed pad, on the

bottom of the package.

This pin and its associated functions are only available

on the MCP19111 device.

GPB5 is a general purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPB. An

internal weak pull-up and interrupt-on-change are also

available.

2.1.20

P

GND

Connect all large signal level ground returns to P_GND

.

These large-signal level ground traces should have a

small loop area and minimal length to prevent coupling

of switching noise to sensitive traces.

AN7 is an input to the A/D. To configure this pin to be

read by the A/D on channel 7, bits TRISB5 and ANSB5

must be set.

2.1.21

LDRV PIN

On the MCP19111, the ISCPCLK is the serial

programming clock function. This is used in conjunction

with ICSPDAT to serial program the device. This pin

function is only implemented on the MCP19111.

The gate of the low-side or rectifying MOSFET is

connected to LDRV. The PCB tracing connecting LDRV

to the gate must be of minimal length and appropriate

width to handle the high peak drive currents and fast

voltage transitions.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 15

MCP19110/11

2.1.22

HDRV PIN

The gate of the high-side MOSFET is connected to

HDRV. This is a floating driver referenced to PHASE.

The PCB trace connecting HDRV to the gate must be

of minimal length and appropriate width to handle the

high-peak drive current and fast voltage transitions.

2.1.23

PHASE PIN

The PHASE pin provides the return path for the high-

side gate driver. The source of the high-side MOSFET,

drain of the low-side MOSFET and the inductor are

connected to this pin.

2.1.24

BOOT PIN

The BOOT pin is the floating bootstrap supply pin for

the high-side gate driver. A capacitor is connected

between this pin and the PHASE pin to provide the

necessary charge to turn on the high-side MOSFET.

2.1.25

+V

SEN

The non-inverting input of the unity gain amplifier used

for output voltage remote sensing is connected to the

+V_SENpin. This pin can be internally pulled-up to V_DD

by setting PE1<PUEN> bit.

2.1.26

-V

SEN

The inverting input of the unity gain amplifier used for

output voltage remote sensing is connected to the

-V_SENpin. This pin can be internally pull-down to GND

by setting PE1<PDEN> bit.

2.1.27

+I

SEN

The non-inverting input of the current sense amplifier is

connected to the +I_SENpin.

2.1.28

-I

SEN

The inverting input of the current sense amplifier is

connected to the -I_SENpin.

2.1.29

EXPOSED PAD (EP)

There is no internal connection to the Exposed Thermal

Pad. The EP should be connected to the GND pin and

to the GND PCB plane to aid in the removal of the heat.

DS20002331D-page 16

 2013-2016 Microchip Technology Inc.

MCP19110/11

3.2

Internal Synchronous Driver

3.0

3.1

FUNCTIONAL DESCRIPTION

Linear Regulators

The internal synchronous driver is capable of driving

two N-Channel MOSFETs in a synchronous rectified

buck converter topology. The gate of the floating

MOSFET is connected to the HDRV pin. The source of

this MOSFET is connected to the PHASE pin. The

HDRV pin source and sink current is configurable. By

setting the DRVSTR bit in the PE1 register, the high-

side is capable of sourcing and sinking a peak current

of 1A. By clearing this bit, the source and sink peak

current is 2A.

Two internal linear regulators generate two 5V rails.

One 5V rail is used to provide power for the internal

analog circuitry and is contained on-chip. The second

5V rail provides power to the internal PIC core and it is

present on the V_DDpin. It is recommended that a 1 µF

capacitor be placed between V_DDand P_GND

.

The V_DRpin provides power to the internal

synchronous MOSFET driver. V_DDcan be directly

connected to V_DRor connected through a low-pass RC

filter to provide noise filtering. A 1 µF ceramic bypass

Note 1: The PE1<DRVSTR> bit configures the

peak source/sink current of the HDRV

pin.

capacitor should be placed between V_DRand P_GND

.

When connecting V_DDto V_DR, the gate drive current

required to drive the external MOSFETs must be added

to the MCP19110/11 quiescent current, I_Q(max). This

total current must be less than the maximum current,

I_DD-OUT, available from V_DDthat is specified in

Section 4.2 “Electrical Characteristics”.

The MOSFET connected to the LDRV pin is not

floating. The low-side MOSFET gate is connected to

the LDRV pin and the source of this MOSFET is

connected to P_GND. The drive strength of the LDRV pin

is not configurable. This pin is capable of sourcing a

peak current of 2A. The peak sink current is 4A. This

helps keep the low-side MOSFET off when the

high-side MOSFET is turning on.

EQUATION 3-1:

TOTAL REGULATOR

CURRENT

I_{DD – OUT}> I_Q+ I_DRIVE+ I_EXT



Note 1: Refer to Figure 1-1 for a graphical

representation

connections.

of

the

MOSFET

Where:

- I

is the total current available from V

DD-OUT

DD

3.2.1

MOSFET DRIVER DEAD TIME

- I is the device quiescent current

Q

The MOSFET driver dead time is defined as the time

between one drive signal going low and the

complimentary drive signal going high. Refer to

Figure 6-2. The MCP19110/11 has the capability to

adjust both the high-side and low-side driver dead time

independently. The adjustment of the driver dead time

is controlled by the DEADCON register and is

adjustable in 4 ns increments.

- I

is the current required to drive the

DRIVE

external MOSFETs

- I is the amount of current used to power

additional external circuitry.

EXT

EQUATION 3-2:

GATE DRIVE CURRENT

I_DRIVE= Q_gHIGH+ Q_gLOW  F_SW

Note 1: The DEADCON register controls the

amount of dead time added to the HDRV

or LDRV signal. The dead time circuitry is

enabled by the LDLYBY and HDLYBY

bits in the PE1 register.

Where:

- I_DRIVEis the current required to drive the

external MOSFETs

- Q_gHIGHis the total gate charge of the

high-side MOSFET

3.2.2

MOSFET DRIVER CONTROL

- Q_gLOWis the total gate charge of the

low-side MOSFET

The MCP19110/11 has the ability to disable the entire

synchronous driver or just one side of the synchronous

drive signal. The bits that control the MOSFET driver

can be found in the Register 8-1.

- F_SWis the switching frequency

Alternatively, an external regulator can be used to

power the synchronous driver. An external 5V source

can be connected to V_DR. The amount of current

required from this external source can be found in

Equation 3-2. Care must be taken that the voltage

applied to V_DRdoes not exceed the maximum ratings

By

setting

ATSTCON<DRVDIS>,

the

entire

synchronous driver is disabled. The HDRV and LDRV

signals are set low and the PHASE pin is floating.

Clearing this bit allows normal operation.

Individual control of the HDRV or LDRV signal is

accomplished by setting or clearing the HIDIS or

LODIS bits in the ATSTCON register. When either

driver is disabled, the output signal is set low.

found

in

Section 4.1

“Absolute

Maximum

Ratings (†)”.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 17

MCP19110/11

3.3

Output Voltage

3.6

Slope Compensation

The output voltage is configured by the settings

contained in the OVCCON and OVFCON registers. No

external resistor divider is needed to set the output

voltage. Refer to Section 6.10 “Output Voltage

Configuration”.

In current mode control systems, slope compensation

needs to be added to the control path to help prevent

subharmonic oscillation when operating with greater

than 50% duty cycle. In the MCP19110/11, a negative

slope is added to the error amplifier output signal

before it is compared to the current sense signal. The

amount of slope added is controlled by the

SLPCRCON register, Register 6-7.

The MCP19110/11 contains a unity gain differential

amplifier used for remote sensing of the output voltage.

Connect the +V_SENand -V_SENpins directly at the load

for better load regulation. The +V_SENand -V_SENare the

positive and negative inputs, respectively, of the

differential amplifier.

Note 1: To enable the slope compensation

circuitry, the ABECON<SLCPBY> bit

must be cleared.

3.4

Switching Frequency

The amount of slope compensation added should be

equal to the inductor current down slope during the

high-side off time.

The switching frequency is configurable over the range

of 100 kHz to 1.6 MHz. The Timer2 module is used to

generate the HDRV/LDRV switching frequency. Refer

to Section 26.0 “PWM Module” for more information.

Example 3-1 shows how to configure the

MCP19110/11 for a switching frequency of 300 kHz.

3.7

Current Sense

The output current is differentially sensed by the

MCP19110/11. The sense element can be either a

resistor placed in series with the output, or the series

resistance of the inductor. If the inductor series resis-

tance is used, a filter is needed to remove the large AC

component of the voltage that appears across the

inductor and leave only the small AC voltage that

appears across the inductor resistance, as shown in

Figure 3-2. This small AC voltage is representative of

the output current.

EXAMPLE 3-1:

CONFIGURING F

SW

BANKSEL

CLRF

T2CON

TMR2

0x19

PR2

0x0A

PWMRL

0x00

PWMPHL

0x04

T2CON

;Turn off Timer2

;Initialize module

;Fsw=300 kHz

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

;Max duty cycle=40%

;No phase shift

;Turn on Timer2

FIGURE 3-2:

INDUCTOR CURRENT

SENSE FILTER

V_IN

3.5

Compensation

-I_SEN

+I_SEN

The MCP19110/11 is an analog peak current mode

controller with integrated adjustable compensation.

The CMPZCON register is used to adjust the

compensation zero frequency and gain. Figure 3-1

shows the internal compensation network with the

output differential amplifier.

C_S

R_L

R_S

HDRV

To Load

PHASE

LDRV

L

FIGURE 3-1:

SIMPLIFIED INTERNAL

COMPENSATION

The value of R_Sand C_Scan be found by using

Equation 3-3. When the current sense filter time

constant is set equal to the inductor time constant, the

voltage appearing across C_Sapproximates the current

flowing in the inductor, multiplied by the inductor

resistance.

+V_SEN

-V_SEN

V_REF

DS20002331D-page 18

 2013-2016 Microchip Technology Inc.

MCP19110/11

EQUATION 3-3:

CALCULATING FILTER

VALUES

3.7.1

PLACEMENT OF THE CURRENT

SENSE FILTER COMPONENTS

The amplitude of the current sense signal is typically

less than 100 mV peak-to-peak. Therefore, the small

signal current sense traces are very susceptible to

circuit noise. When designing the printed circuit board,

placement of R_Sand C_Sis very important. The +I_SEN

and -I_SENtraces should be routed parallel to each other

with minimum spacing. This Kelvin sense routing

technique helps minimize noise sensitivity. The filter

capacitor (C_S), should be placed as close to the

MCP19110/11 as possible. This will help filter any noise

that is injected onto the current sense lines. The trace

connecting C_Sto the inductor should occur directly at

the inductor and not at any other +V_SENtrace. The filter

resistor (R_S), should be placed close to the inductor.

See Figure 3-3 for component placement. Care should

also be taken to avoid routing the +I_SENand -I_SEN

traces near the high current switching nodes of the

HDRV, LDRV, PHASE, or BOOST traces. It is

recommended that a ground layer be placed between

these high current traces and the small signal current

sense traces.

L

----- = R_S C_S

R_L

Where:

- L is the inductance value of the output

inductor

- R_Lis the series resistance of the output

inductor

- R_Sis the current sense filter resistor

- C_Sis the current sense filter capacitor

Both AC gain and DC gain can be added to the current

sense signal. Refer to Section 6.3 “Current Sense

AC Gain” and Section 6.4 “Current Sense DC Gain”

for more information.

FIGURE 3-3:

CURRENT SENSE FILTER COMPONENT PLACEMENT

-I_SEN

+I_SEN

C_S

R_S

To

PHASE

To

Load

INDUCTOR

 2013-2016 Microchip Technology Inc.

DS20002331D-page 19

MCP19110/11

3.8.3

OUTPUT UNDERVOLTAGE

3.8

Protection Features

When the output undervoltage DAC is enabled by

setting the ABECON<UVDCEN> bit, the voltage

measured between the +V_SENand -V_SENpins is

monitored and compared to the UV threshold

controlled by the OUVCON register (Register 6-12).

When the output voltage is below the threshold, the

PIR2<UVIF> flag will be set. Once set, firmware can

determine how the MCP19110/11 responds to the fault

condition and it must clear the UVIF flag.

3.8.1

INPUT UNDERVOLTAGE LOCKOUT

The input Undervoltage Lockout (UVLO) threshold is

configurable by the VINLVL register, Register 6-1.

When the voltage at the V_INpin of the MCP19110/11 is

below the configurable threshold, the PIR2<VINIF>

flag will be set. This flag is cleared by hardware once

the V_INvoltage is greater than the configurable

threshold. By enabling the global interrupts or polling

the VINIF bit, the MCP19110/11 can be disabled when

the V_INvoltage is below the threshold.

By setting the PE1<UVTEE> bit, the HDRV and LDRV

signals will be asserted low when the UVIF flag is set.

The signals will remain low until the flag is cleared.

Note 1: The UVLO DAC must be enabled by

setting the VINLVL<UVLOEN> bit.

Note 1: The UV DAC must be enabled by setting

2: Interrupt flag bits are set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit

or the Global Enable bit (GIE) of the

INTCON register.

the ABECON<UVDCEN> bit.

2: Interrupt flag bits are set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit

or the Global Enable bit (GIE) of the

INTCON register.

Some techniques that can be used to disable the

switching of the MCP19110/11 while the VINIF flag is

set include setting the ATSTCON<DVRDIS> bit, setting

the reference voltage to 0V, setting the PE1<PUEN>

bit, or setting the ATSTCON<HIDIS> and

ATSTCON<LODIS> bits.

3: The output of the remote sense

comparator is compared to the UV

threshold. Therefore, the offset in this

comparator should be considered when

calculating the UV threshold.

3.8.4

OUTPUT OVERVOLTAGE

3.8.2

OUTPUT OVERCURRENT

When the output overvoltage DAC is enabled by setting

the ABECON<OVDCEN> bit, the voltage measured

between the +V_SENand -V_SENpins is monitored and

compared to the OV threshold controlled by the

OOVCON register (Register 6-13). When the output

voltage is above the threshold, the PIR2<OVIF> flag

will be set. Once set, firmware can determine how the

MCP19110/11 responds to the fault condition and it

must clear the OVIF flag.

The MCP19110/11 senses the voltage drop across the

high-side MOSFET to determine when an output

overcurrent (OC) exists. This voltage drop is

configurable by the OCCON register (Register 6-2),

and is measured when the high-side MOSFET is

conducting. To avoid false OC events, leading edge

blanking is applied to the measurements. The amount

of blanking is controlled by the OCLEB<1:0> bits in the

OCCON register. See Section 6.2 “Output

Overcurrent” for more information.

By setting the PE1<OVTEE> bit, the HDRV and LDRV

signals will be asserted low when the OVIF flag is set.

The signals will remain low until the flag is cleared.

When the input voltage is greater than 20V, or if the

R_DSONof the high-side MOSFET is such that the

programmed overcurrent threshold does not produce

acceptable peak overcurrent protection, an alternative

method must be used to determine an overcurrent

situation. An alternative technique can use the

configurable output undervoltage protection, and the

PE1<UVTEE> bit, to quickly terminate switching when

the output voltage drops because of an overcurrent

event.

Note 1: The OV DAC must be enabled by setting

the ABECON<UVDCEN> bit.

2: Interrupt flag bits are set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit

or the Global Enable bit (GIE) of the

INTCON register.

3: The output of the remote sense

comparator is compared to the OV

threshold. Therefore, the offset in this

comparator should be considered when

calculating the OV threshold.

Note 1: The OC DAC must be enabled by setting

the OCCON<OCEN> bit.

DS20002331D-page 20

 2013-2016 Microchip Technology Inc.

MCP19110/11

3.8.5

The

OVERTEMPERATURE

MCP19110/11 features

Note 1: The GUI can be found on the

a

hardware

MCP19110/11

product

page

on

overtemperature shutdown protection typically set at

+160°C. No firmware fault-handling procedure is

required to shutdown the MCP19110/11 for an

overtemperature condition. The ABECON<TMPSEN>

bit must be set to enable the over temperature circuitry.

www.microchip.com.

2: Microchip's MPLAB

X Integrated

Development Environment Software is

required to use the GUI.

The MCP19110/11 device features firmware debug

support. See Section 30.0 “Development Support”

for more information.

3.9

PIC Microcontroller Core

Integrated into the MCP19110/11 is the PIC

microcontroller mid-range core. This is a fully functional

microcontroller, allowing proprietary features to be

implemented. Setting the CONFIG<CP> bit enables

the code protection. The firmware is then protected

from external reads or writes. Various status and fault

bits are available to customize the fault handling

response.

3.10 Miscellaneous Features

3.10.1

DEVICE ADDRESSING

The communication address of the MCP19110/11 is

stored in the SSPADD register. This value can be

loaded when the device firmware is programmed or

configured by external components. By reading a volt-

age on a GPIO with the ADC, a device specific address

can be stored into the SSPADD register.

A minimal amount of firmware is required to properly

configure

the

MCP19110/11.

Section 6.0

“Configuring the MCP19110/11” contains detailed

information about each register that needs to be set for

the MCP19110/11 device to operate. To aid in the

development of the required firmware, a Graphical

User Interface (GUI) has been developed. This GUI

can be used to quickly configure the MCP19110/11 for

basic operation. Customized or proprietary features

can then be added to the GUI generated firmware.

The MCP19110/11 contains a second address register,

SSPADD2. This is a 7-bit address that can be used as

the SMBus alert address when PMBus communication

is used. See Section 27.0 “Master Synchronous

Serial Port (MSSP) Module” for more information.

3.10.2

DEVICE ENABLE

A GPIO pin can be configured to be a device enable

pin. By configuring the pin as an input, the PORT

register or the interrupt on change (IOC) can be used

to enable the device. Example 3-2 shows how to

configure a GPIO as an enable pin by testing the PORT

register.

EXAMPLE 3-2:

CONFIGURING GPA3 AS DEVICE ENABLE

BANKSEL

TRISGPA

BSF

BANKSEL

TRISGPA, 3

ANSELA

;Set GPA3 as input

BCF

ANSELA, 3

;Set GPA3 as digital input

:

;Insert additional user code here

:

WAIT_ENABLE:

BANKSEL

BTFSS

PORTGPA

PORTGPA, 3

;Test GPA3 to see if pulled high

;A high on GPA3 indicated device to be enabled

;Stay in loop waiting for device enable

GOTO

BANKSEL

WAIT_ENABLE

ATSTCON

BSF

:

ATSTCON, 0

;Enable the device by enabling drivers

;Insert additional code here

:

 2013-2016 Microchip Technology Inc.

DS20002331D-page 21

MCP19110/11

3.10.3

OUTPUT POWER GOOD

Note 1: The ALT_CLKPIN can also be used by

setting the APFCON<CLKSEL> bit. This

function is only available in the

MCP19111.

The output voltage measured between the +V_SENand

-V_SENpins can be monitored by the internal ADC. In

firmware, when this ADC reading matches a user-

defined power good value, a GPIO can be toggled to

indicate the system output voltage is within a specified

range. Delays, hysteresis and time-out values can all

be configured in firmware.

3.10.7

MULTIPLE OUTPUT SYSTEM

In a multiple output system, the switching frequency of

each converter should be synchronized to a master

clock to prevent beat frequencies from developing.

Phase shift is often added to the master clock to help

smooth the system input current. The MCP19110/11

has the ability to function as a multiple output master or

slave by setting the appropriate MLTPH<2:0> bits in

the BUFFCON register (Register 8-2).

3.10.4

OUTPUT VOLTAGE SOFT-START

During start-up, soft start of the output voltage is

accomplished in firmware. By using one of the internal

timers and incrementing the OVCCON or OVFCON

register on a timer overflow, very long soft start times

can be achieved.

When configured as a multiple output master, the

GPA1 pin is set as the CLKPIN output function. The

internal switching frequency clock is applied to this pin

and is to be connected to the GPA1 pin of the slave

units.

3.10.5

OUTPUT VOLTAGE TRACKING

The MCP19110/11 can be configured to track another

voltage signal at start-up or shutdown. The ADC is

configured to read a GPIO that has the desired tracking

voltage applied to it. The firmware then handles the

tracking of the internal output voltage reference to this

ADC reading.

When configured as a multiple output slave, the GPA1

pin is set as the CLKPIN input function. The switching

frequency clock of the master device is connected to

this pin. Phase shift can be applied by appropriately

setting the PWMPHL register of the slave device. Refer

to Section 26.1 “Standard Pulse-Width Modulation

(PWM) Mode”.

3.10.6

MULTI-PHASE SYSTEM

In a multi-phase system, the output of each converter

is connected together. There is one master device that

sets the system switching frequency and provides each

slave device with an error signal, in order to regulate

the output to the same value.

Note 1: The ALT_CLKPIN can also be used by

setting the APFCON<CLKSEL> bit. This

function is only available in the

MCP19111.

The MCP19110/11 can be configured as a multi-phase

master or slave by the setting of the MLTPH<2:0> bits

in the BUFFCON register (Register 8-2). When set as

a multi-phase master device, the internal switching fre-

quency clock is connected to GPA1 and the output of

the error amplifier is connected to GPB1. The GPIOs

need to be configured as outputs.

3.10.8

SYSTEM BENCH TESTING

The MCP19110/11 is a highly integrated controller. To

facilitate system prototyping, various internal signals

can be measured by configuring the MCP19110/11 in

bench test mode. To accomplish this, the

ATSTCON<BNCHEN> bit is set. This configures GPA0

as the ANALOG_TEST feature. The signals measured

on GPA0 are controlled by the ASEL<4:0> bits of the

BUFFCON register. See Section 8.0 “System Bench

Testing” for more information.

When set as a multi-phase slave device, the GPA1 pin

is configured as the CLKPIN function. The switching

frequency clock from the master device must be

connected to GPA1. The slave device will synchronize

its internal switching frequency clock to the master

clock. Phase shift can be applied by setting the

PWMPHL register of the slave device. The slave GPB1

pin is configured as the error signal input pin (EAPIN).

The master error amplifier output must be connected to

GPB1. Gain can be added to the master error amplifier

output signal by the SLVGNCON register setting

(Register 6-8). The slave device will use this master

error signal to regulate the output voltage. When set as

a slave device, GPA1 and GPB1 need to be configured

as inputs. Refer to Section 26.1 “Standard Pulse-

Width Modulation (PWM) Mode” for additional

information.

Note 1: The factory-set calibration words are

write-protected

even

when

the

MCP19110/11 is placed in a Bench Test

mode.

DS20002331D-page 22

 2013-2016 Microchip Technology Inc.

MCP19110/11

4.0

4.1

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS ^(†)

V_IN– V_GND.................................................................................................................................................. -0.3V to +32V

V_{BOOT -}V_PHASE.......................................................................................................................................... -0.3V to +6.5V

V_PHASE(continuous) ........................................................................................................................ GND – 0.3V to +38V

V_PHASE(transient < 100 ns)............................................................................................................. GND – 5.0V to +38V

V_DDinternally generated...................................................................................................................................+5V ±20%

V_HDRV, HDRV Pin..........................................................................................................+V_PHASE– 0.3V to V_BOOT+ 0.3V

V_LDRV, LDRV Pin............................................................................................................. +(V_GND– 0.3V) to (V_DD+ 0.3V)

Voltage on MCLR with respect to GND.................................................................................................... -0.3V to +13.5V

Maximum Voltage: any other pin..................................................................................... +(V_GND– 0.3V) to (V_DD+ 0.3V)

Maximum output current sunk by any single I/O pin ...............................................................................................25 mA

Maximum output current sourced by any single I/O pin..........................................................................................25 mA

Maximum current sunk by all GPIO ........................................................................................................................65 mA

Maximum current sourced by all GPIO ...................................................................................................................65 mA

ESD protection on all pins (HBM) ...........................................................................................................................1.0 kV

ESD protection on all pins (MM)100V

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at those or any other conditions above those indicated in

the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods

may affect device reliability.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 23

MCP19110/11

4.2

Electrical Characteristics

Electrical Specifications: Unless otherwise noted, V_IN= 12V, V_REF= 1.2V, F_SW= 300 kHz, T_A= +25°C.

Boldface specifications apply over the T_Arange of -40°C to +125°C.

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

Input

Input Voltage

V_IN

I_Q

4.5

—

3

—

5

32

10

2.2

32

V

Input Quiescent Current

Shutdown Current

mA Not switching

mA Note 4

I_SHDN

UVLO

1.8

—

Adjustable Input Under-

voltage Lockout Range

V

VINLVL is a LOG DAC

Input Undervoltage Lock-

out Hysteresis

UVLO_HYS

—

13

—

%

Hysteresis applied to

adjustable UVLO setpoint

Overcurrent

Overcurrent Minimum

Threshold

OC_MIN

OC_MAX

OC_MID

—

160

620

400

—

mV

Overcurrent Maximum

Threshold

Overcurrent Mid-Scale

Threshold

240

550

Overcurrent Step Size

OC_{STEP_SIZE}

LEB_min

10

15

20

mV

ns

Adjustable OC Leading

Edge Blanking Minimum

Set Point

—

114

—

Adjustable OC Leading

Edge Blanking Maximum

Set Point

LEB_max

—

780

—

ns

Current Sense

Current Sense Minimum

AC Gain

I_{AC_GAIN}

—

0

—

dB

mV

dB

Current Sense Maximum

AC Gain

22.8

11.5

1.5

Current Sense AC Gain

Mid-Set Point

I_{AC_GAIN}

8.5

—

14

Current Sense AC Gain

Step Size

I_{AC_GAIN_STEP}

I_{AC_OFFSET}

I_{DC_GAIN}

—

Current Sense AC Gain

Offset Voltage

-175

—

9

135

—

Current Sense Minimum

DC Gain

19.5

35.7

28.6

2.3

Current Sense Maximum

DC Gain

I_{DC_GAIN}

—

Current Sense DC Gain

Mid-Set Point

I_{DC_GAIN}

27

30.3

—

Current Sense DC Gain

Step Size

I_{DC_GAIN_STEP}

—

Note 1: Ensured by design. Not production tested.

2: _DD-OUTis the voltage present at the V_DDpin. V_DDis the internally generated bias voltage.

V

3: This is the total source current for all GPIO pins combined. Individually, each pin can source a maximum of

25 mA.

4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h, and

SLEEP command issued to PIC core, see SECTION 16.0.

DS20002331D-page 24

 2013-2016 Microchip Technology Inc.

MCP19110/11

4.2

Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V_IN= 12V, V_REF= 1.2V, F_SW= 300 kHz, T_A= +25°C.

Boldface specifications apply over the T_Arange of -40°C to +125°C.

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

Current Sense DC Gain

Offset Voltage

I_{DC_OFFSET}

1.4

1.56

1.7

V

Voltage for Zero Current

Voltage Reference

VZC

—

1.45

—

V

VZCCON = 0x80h

Adjustable V_OUTRange

V_{OUT_RANGE}

0.5

3.6

V_OUTrange with no external

voltage divider

V

_OUTCoarse Resolution

_OUTCoarse

V_{OUT_COARSE}

10.8

1.85

15.8

2.04

25.8

2.25

mV

V

OUT_COARSE_MID

Mid Set Point

V_OUTFine Resolution

V_{OUT_FINE}

—

0.8

1

mV

Output Overvoltage

Adjustable Overvoltage

Range

OV_RANGE

OV_MID

OV_R

0

—

2

4.5

2.3

—

V

Adjustable Overvoltage

Mid-Set Point

1.8

—

Adjustable Overvoltage

Resolution

15

mV

Output Undervoltage

Adjustable

Undervoltage Range

UV_RANGE

UV_MID

UV_R

0

—

2

4.5

2.3

—

Adjustable Undervoltage

Mid-Set Point

1.8

—

V

Adjustable Undervoltage

Resolution

15

mV

Remote Sense Differential Amplifier

Closed Loop Voltage

Gain

A_VOL

0.95

1

1.05

V/V

GND – 0.3

—

V

+ 1.0

Common Mode Range

V_CMR

—

V

Note 1

DD

Common Mode

Reject Ratio

CMRR

57

—

dB

Differential Amplifier

Offset

V_OS

—

40

mV See Section 9.5 “Calibration

Word 5” and Section 9.6

“Calibration Word 6”

Compensation

Minimum Zero Frequency

Maximum Zero Frequency

F_{ZERO_MIN}

F_{ZERO_MAX}

G_{EA_MIN}

—

350

35000

0

—

Hz

dB

Minimum Error Amplifier

Gain

Maximum Error Amplifier

Gain

G_{EA_MAX}

—

36.15

—

dB

Note 1: Ensured by design. Not production tested.

2: _DD-OUTis the voltage present at the V_DDpin. V_DDis the internally generated bias voltage.

V

3: This is the total source current for all GPIO pins combined. Individually, each pin can source a maximum of

25 mA.

4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h, and

SLEEP command issued to PIC core, see SECTION 16.0.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 25

MCP19110/11

4.2

Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V_IN= 12V, V_REF= 1.2V, F_SW= 300 kHz, T_A= +25°C.

Boldface specifications apply over the T_Arange of -40°C to +125°C.

Parameter

Oscillator

Symbol

Min.

Typ.

Max.

Units

Conditions

Internal Oscillator

Frequency

F_OSC

7.60

8.00

8.40

MHz

kHz

Switching Frequency

F_SW

N

—

F_OSC/N

—

Switching Frequency

Range Select

5

80

Maximum Duty Cycle

—

(N–1)/N

4

—

%/

100

Dead Time Adjustment

Dead Time Step Size

HDRV Output Driver

DT_STEP

ns

HDRV Source

Resistance

R_HDRV-SCR

—

1

2

1

2

2.6

3.5

2.6

3.5



Measured at 500 mA

Note 1, High Range

Measured at 500 mA

Note 1, Low Range

HDRV Sink Resistance

R_HDRV-SINK

Measured at 500 mA

Note 1, High Range

Measured at 500 mA

Note 1, Low Range

HDRV Source Current

HDRV Sink Current

I_HDRV-SCR

I_HDRV-SINK

—

2

1

—

30

A

Note 1, High Range

Note 1, Low Range

Note 1, High Range

Note 1, Low Range

2

1

HDRV Rise Time

HDRV Fall Time

15

ns Note 1, C_LOAD= 3.3 nF,

High Range

t_RH

t_FH

—

15

30

ns Note 1, C_LOAD= 3.3 nF,

High Range

LDRV Output Driver

LDRV

Source Resistance

R_LDRV-SCR

R_LDRV-SINK

—

1

2.5

1.0



Measured at 500 mA

Note 1

LDRV Sink Resistance

0.5

Measured at 500 mA

Note 1

LDRV Source Current

LDRV Sink Current

LDRV Rise Time

I_LDRV-SCR

I_LDRV-SINK

t_RL

—

2

4

—

30

15

A

Note 1

15

7

ns Note 1, C_LOAD= 3.3 nF

LDRV Fall Time

t_FL

Note 1: Ensured by design. Not production tested.

2: _DD-OUTis the voltage present at the V_DDpin. V_DDis the internally generated bias voltage.

V

3: This is the total source current for all GPIO pins combined. Individually, each pin can source a maximum of

25 mA.

4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h, and

SLEEP command issued to PIC core, see SECTION 16.0.

DS20002331D-page 26

 2013-2016 Microchip Technology Inc.

MCP19110/11

4.2

Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V_IN= 12V, V_REF= 1.2V, F_SW= 300 kHz, T_A= +25°C.

Boldface specifications apply over the T_Arange of -40°C to +125°C.

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

Linear Regulator

Bias Voltage, LDO Output

V_DD

4.6

—

5.0

5.4

—

V

V_IN= 6.0V to 32V, Note 2

Internal Circuitry

Bias Voltage

AV_DD

Maximum V_DDOutput

Current

I_DD

30

—

mA V_IN= 6.0V to 20V,

V_DD= 5.0V,

Note 2

Line Regulation

Load Regulation

V_DD

(V_DDx V_IN)

/

—

-1.75

—

0.05

-0.8

65

0.1

+0.5

—

%/V (V_DD+1.0V)  V_IN 20V

Note 2

V_DD/V_DD

%

I_DD= 1 mA to 30 mA

Note 2

Output Short

Circuit Current

I_{DD_SC}

mA V_IN= (V_DD+ 1.0V)

Note 2

Dropout Voltage

V_IN– V_DD

—

0.5

1

V

I_DD= 30 mA,

V_IN= V_DD+ 1.0V

Note 2

Power Supply

Rejection Ratio

PSRR_LDO

BG

—

60

—

dB f  1000 Hz, I_DD= 25 mA,

C_IN= 0 µF, C_DD= 1 µF

V

Band Gap Voltage

-2.5%

1.23

+2.5%

GPIO Pins

Maximum GPIO

Sink Current

I_{SINK_GPIO}

I_{SOURCE_GPIO}

I_{PULL-UP_GPIO}

V_OL

—

50

—

90

mA Note 3, Note 1

µA V_DD= 5V

Maximum GPIO

Source Current

GPIO Weak

Pull-up Current

250

—

400

0.6

GPIO Output Low

Voltage

V

I_OL= 7 mA, V_DD= 5V,

T_A= +90°C

GPIO Output

High Voltage

V_OH

V_DD– 0.7

—

I_OH= -2.5 mA, V_DD= 5V,

T_A= +90°C

GPIO Input

Leakage Current

GPIO_I_IL

±0.1

±1

µA Negative current is defined as

current sourced by the pin,

T_A= +90°C

GPIO Input Low Voltage

V_IL

GND

—

0.8

V

I/O Port with TTL buffer

V_DD= 5V, T_A= +90°C

0.2V_DD

V

I/O Port with Schmitt Trigger

buffer, V_DD= 5V, T_A= +90°C

GND

0.2V_DD

V

MCLR, T_A= +90°C

Note 1: Ensured by design. Not production tested.

2: _DD-OUTis the voltage present at the V_DDpin. V_DDis the internally generated bias voltage.

V

3: This is the total source current for all GPIO pins combined. Individually, each pin can source a maximum of

25 mA.

4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h, and

SLEEP command issued to PIC core, see SECTION 16.0.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 27

MCP19110/11

4.2

Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V_IN= 12V, V_REF= 1.2V, F_SW= 300 kHz, T_A= +25°C.

Boldface specifications apply over the T_Arange of -40°C to +125°C.

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

GPIO Input High Voltage

V_IH

2.0

—

V_DD

V

I/O Port with TTL buffer,

V_DD= 5V, T_A= +90°C

0.8V_DD

—

V_DD

V

I/O Port with Schmitt Trigger

buffer, V_DD= 5V, T_A= +90°C

MCLR, T_A= +90°C

Thermal Shutdown

T_SHD

—

160

20

—

°C

Thermal Shutdown

Hysteresis

T_{SHD_HYS}

Note 1: Ensured by design. Not production tested.

2: _DD-OUTis the voltage present at the V_DDpin. V_DDis the internally generated bias voltage.

V

3: This is the total source current for all GPIO pins combined. Individually, each pin can source a maximum of

25 mA.

4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h, and

SLEEP command issued to PIC core, see SECTION 16.0.

4.3

Thermal Specifications

Parameter

Symbol

Min.

Typ.

Max.

Units

Test Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Maximum Junction Temperature

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 24L-QFN 4x4

Thermal Resistance, 28L-QFN 5x5

T_A

T_J

T_A

-40

—

+125

+150

C

-65

_JA

—

42

—

C/W

35.3

DS20002331D-page 28

 2013-2016 Microchip Technology Inc.

MCP19110/11

5.0

5.1

DIGITAL ELECTRICAL CHARACTERISTICS

Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

3. TCC:ST

4. Ts

(I²C specifications only)

F

Frequency

TTime

Lowercase letters (pp) and their meanings:

pp

cc

ck

cs

di

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O port

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

Fall

P

R

V

Z

Period

H

High

Rise

I

Invalid (high-impedance)

Low

Valid

L

High-impedance

I²C only

AA

Output access

Bus free

High

Low

High

Low

BUF

TCC:ST (I²C specifications only)

CC

HD

Hold

SU

Setup

ST

DAT

STA

DATA input hold

START condition

STO

STOP condition

FIGURE 5-1:

LOAD CONDITIONS

Load Condition 1

V_DD/2

Load Condition 2

R_L

C_L

V_SS

R_L= 464

C_L= 50 pF for all GPIO pins

 2013-2016 Microchip Technology Inc.

DS20002331D-page 29

MCP19110/11

5.2

AC Characteristics: MCP19110/11 (Industrial, Extended)

FIGURE 5-2:

EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

OSC

1

2

TABLE 5-1:

EXTERNAL CLOCK TIMING REQUIREMENTS

Param No. Sym.

Characteristic

Min. Typ.^†

Max. Units

Conditions

F_OSC

Oscillator Frequency⁽¹⁾

Oscillator Period⁽¹⁾

Instruction Cycle Time⁽¹⁾

—

8

—

MHz

ns

1

2

*

T_OSC

T_CY

250

1000

ns

These parameters are characterized but not tested.

†

Data in “Typ” column is at V_IN= 12V (V_DD= 5V), +25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

Note 1: Instruction cycle period (T_CY) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code.

FIGURE 5-3:

CLKOUT AND I/O TIMING

Q1

Q4

Q2

Q3

OSC

22

23

19

18

I/O Pin

(input)

15

17

I/O Pin

(output)

new value

old value

20, 21

DS20002331D-page 30

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 5-2:

CLKOUT AND I/O TIMING REQUIREMENTS

Sym. Characteristic Min.

Param

No.

Typ.^†

Max.

Units Conditions

17

TosH2ioV OSC1 (Q1 cycle) to

Port out valid

—

50

—

150*

300

—

ns

18

19

TosH2ioI OSC1 (Q2 cycle) to Port input invalid

100

(I/O in hold time)

TioV2osH Port input valid to OSC1

0

—

ns

(I/O in setup time)

20

21

TioR

TioF

Tinp

Port output rise time

Port output fall time

—

10

40

ns

22

22A

INT pin high

or low time

25

40

—

ns

23

23A

Trbp

Port A change INT

high or low time

Tcy

—

ns

*

†

These parameters are characterized but not tested.

Data in “Typ” column is at V_IN= 12V (V_DD= 5V), +25C unless otherwise stated.

FIGURE 5-4:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

V_DD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

I/O Pins

 2013-2016 Microchip Technology Inc.

DS20002331D-page 31

MCP19110/11

TABLE 5-3:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP

TIMER REQUIREMENTS

Param

No.

Sym.

Characteristic

Min.

Typ.^†

Max. Units

Conditions

30

31

T_MCL

T_WDT

MCLR Pulse Width (low)

2

7

—

µs

V_DD= 5V, -40°C to +85°C

Watchdog Timer Time-out

Period (No Prescaler)

18

33

ms V_DD= 5V, -40°C to +85°C

32

T_OST

Oscillation Start-up Timer

Period

—

1024T_OSC

64

—

T_OSC= OSC1 period

33*

T_PWRT

Power-up Timer Period

28

132

ms V_DD= 5V, -40°C to +85°C

µs

(4 x T_WDT

)

34

T_IOZ

I/O high-impedance from MCLR

Low or Watchdog Timer Reset

—

2.0

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at V_IN= 12V (V_DD= 5V), +25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

FIGURE 5-5:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

41

40

42

TABLE 5-4:

TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No.

Sym.

Characteristic

T0CKI High Pulse Width

Min.

Typ.^†Max. Units

Conditions

40*

Tt0H

Tt0L

Tt0P

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5T_CY+ 20

—

ns

10

0.5T_CY+ 20

10

41*

42*

T0CKI Low Pulse Width

T0CKI Period

Greater of:

20 or TCY + 40

N

N = prescale value

(2, 4, ..., 256)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at V_IN= 12V (V_DD= 5V), +25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

DS20002331D-page 32

 2013-2016 Microchip Technology Inc.

MCP19110/11

FIGURE 5-6:

PWM TIMING

PWM (CLKPIN)

53

54

Note:

Refer to Figure 5-1 for load conditions.

TABLE 5-5:

Param

PWM REQUIREMENTS

Characteristic

Sym.

Min.

Typ.† Max. Units

Conditions

No.

53*

54*

TccR

TccF

PWM (CLKPIN) output rise time

PWM (CLKPIN) output fall time

—

10

25

ns

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at V_IN= 12V (V_DD= 5V), +25°C unless otherwise stated. Parameters are for design

guidance only and are not tested.

TABLE 5-6:

MCP19110/11 A/D CONVERTER (ADC) CHARACTERISTICS:

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +125°C

Param

Sym.

No.

Characteristic

Min.

Typ.^†

Max.

Units

Conditions

AD01

AD02

AD03

N_RResolution

E_ILIntegral Error

—

10

1

bit

LSb AV_DD= 5.0V

E_DLDifferential Error

LSb No missing codes to 10 bits

AV_DD= 5.0V

AD04

AD07

E_OFFOffset Error

—

+3.0

2

+5.0

5

LSb AV_DD= 5.0V

V

E_GNGain Error

V_REFReference Voltage⁽³⁾

AD06

AV_DD

—

AD06A

AD07

AD08

V_AINFull-Scale Range

GND

—

AV_DD

10

V

Z_AINRecommended Impedance

of Analog Voltage Source

k

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at V_IN= 12V (V_DD= 5V), +25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing

codes.

3: When ADC is off, it will not consume any current other than leakage current. The power-down current

specification includes any such leakage from the ADC module.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 33

MCP19110/11

TABLE 5-7:

MCP19110/11 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  T_A +125°C

Param

Sym.

No.

Characteristic

Min.

Typ.^†

Max. Units

Conditions

AD130* T_AD

A/D Clock Period

A/D Internal RC Oscillator

Period

AD131 T_CNVConversion Time

3.0

1.6

—

9.0

6.0

µs T_OSC-based, V_DD= 5.0V

µs At V_DD= 5.0V

4.0

—

11

—

T_ADSet GO/DONE bit to new data in

A/D Result register

(not including Acquisition

Time)⁽¹⁾

AD132* T_ACQAcquisition Time

AD133* T_AMPAmplifier Settling Time

AD134 T_GOQ4 to A/D Clock Start

11.5

—

5

µs

—

T_OSC/2

—

T_OSC

2 + T_CY

/

—

If the A/D clock source is selected

as RC, a time of T_CYis added

before the A/D clock starts. This

allows the SLEEPinstruction to be

executed.

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at V_IN= 12V (V_DD= 5V), +25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

Note 1: ADRESH and ADRESL registers may be read on the following T_CYcycle.

FIGURE 5-7: A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

134

1/2 T_CY

131

Q4

130

A/D CLK

9

8

7

6

3

2

1

0

A/D DATA

OLD_DATA

NEW_DATA

ADRES

ADIF

GO

DONE

SAMPLING STOPPED

132

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of T_CYis added before the A/D clock starts. This

allows the SLEEPinstruction to be executed.

DS20002331D-page 34

 2013-2016 Microchip Technology Inc.

MCP19110/11

FIGURE 5-8:

A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

134

131

Q4

130

A/D CLK

9

8

7

3

2

1

0

6

A/D DATA

NEW_DATA

DONE

OLD_DATA

ADRES

ADIF

GO

SAMPLING STOPPED

132

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of T_CYis added before the A/D clock starts. This

allows the SLEEPinstruction to be executed.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 35

MCP19110/11

NOTES:

DS20002331D-page 36

 2013-2016 Microchip Technology Inc.

MCP19110/11

The VINLVL<UVLOEN> bit must be set to enable the

input Undervoltage Lockout circuitry.

6.0

CONFIGURING THE

MCP19110/11

The MCP19110/11 is an analog controller with digital

peripheral. This means that device configuration is

handled through register settings instead of adding

external components. The following sections detail how

to set the analog control registers.

Note:

The VINIF interrupt flag bit is set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit or

the Global Enable bit, GIE, of the INTCON

register.

6.1

Input Undervoltage Lockout

The VINLVL register contains the digital value that sets

the input Undervoltage Lockout. When the input

voltage on the V_INpin to the MCP19110/11 is below this

programmed level, the INTCON<VINIF> flag will be

set. This bit is automatically cleared when the

MCP19110/11 V_INvoltage rises above this

programmed level.

REGISTER 6-1:

VINLVL: INPUT UNDERVOLTAGE LOCKOUT CONTROL REGISTER

R/W-0

UVLOEN

bit 7

U-0

—

R/W-x

UVLO5

UVLO4

UVLO3

UVLO2

UVLO1

UVLO0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

UVLOEN: Undervoltage Lockout DAC Control bit

1= Undervoltage Lockout DAC is enabled

0= Undervoltage Lockout DAC is disabled

bit 6

Unimplemented: Read as ‘0’

bit 5-0

UVLO<5:0>: Undervoltage Lockout Configuration bits

UVLO<5:0>= 26.5*ln(UVLO_{SET_POINT}/4)

 2013-2016 Microchip Technology Inc.

DS20002331D-page 37

MCP19110/11

6.2

Output Overcurrent

The MCP19110/11 features a cycle-by-cycle peak

current limit. By monitoring the OCIF interrupt flag,

custom overcurrent fault handling can be implemented.

To detect an output overcurrent, the MCP19110/11

senses the voltage drop across the high-side MOSFET

while it is conducting. Leading edge blanking is

incorporated to mask the overcurrent measurement for

a given amount of time. This helps prevent false

overcurrent readings. When the input voltage is greater

than 20V, or if the R_DSONof the high-side MOSFET is

such that the programmed overcurrent threshold does

not produce acceptable peak overcurrent protection,

an alternative method must be used to determine an

output overcurrent situation. An alternative technique

can use the configurable output undervoltage

protection and the PE1<UVTEE> bit to quickly

terminate switching when the output voltage drops

because of an overcurrent event.

When an output overcurrent is sensed, the OCIF flag is

set and the high-side drive signal is immediately

terminated. Without any custom overcurrent handling

implemented, the high-side drive signal will be asserted

high at the beginning of the next clock cycle. If the

overcurrent condition still exists, the high-drive signal

will again be terminated.

The OCIF interrupt flag must be cleared in software.

However, if a subsequent switching cycle without an

overcurrent condition has not occurred, hardware will

immediately set the OCIF interrupt flag.

Register OCCON contains the bits used to configure

both the output overcurrent limit and the amount of

leading edge blanking (see Register 6-2).

The OCCON<OCEN> bit must be set to enable the

input overcurrent circuitry.

Note:

The OCIF interrupt flag bit is set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit or

the Global Enable bit, GIE, of the INTCON

register.

DS20002331D-page 38

 2013-2016 Microchip Technology Inc.

MCP19110/11

REGISTER 6-2:

OCCON: OUTPUT OVERCURRENT CONTROL REGISTER

R/W-0

OCEN

bit 7

R/W-x

OOC4

R/W-x

OOC3

R/W-x

OOC2

R/W-x

OOC1

R/W-x

OOC0

OCLEB1

OCLEB0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

OCEN: Output Overcurrent DAC Control bit

1= Output Overcurrent DAC is enabled

0= Output Overcurrent DAC is disabled

bit 6-5

OCLEB<1:0>: Leading Edge Blanking

00= 114 ns blanking

01= 213 ns blanking

10= 400 ns blanking

11= 780 ns blanking

bit 4-0

OOC<4:0>: Output Overcurrent Configuration bits

00000= 160 mV drop

00001= 175 mV drop

00010= 190 mV drop

00011= 205 mV drop

00100= 220 mV drop

00101= 235 mV drop

00110= 250 mV drop

00111= 265 mV drop

01000= 280 mV drop

01001= 295 mV drop

01010= 310 mV drop

01011= 325 mV drop

01100= 340 mV drop

01101= 355 mV drop

01110= 370 mV drop

01111= 385 mV drop

10000= 400 mV drop

10001= 415 mV drop

10010= 430 mV drop

10011= 445 mV drop

10100= 460 mV drop

10101= 475 mV drop

10110= 490 mV drop

10111= 505 mV drop

11000= 520 mV drop

11001= 535 mV drop

11010= 550 mV drop

11011= 565 mV drop

11100= 580 mV drop

11101= 595 mV drop

11110= 610 mV drop

11111= 625 mV drop

 2013-2016 Microchip Technology Inc.

DS20002331D-page 39

MCP19110/11

6.3

Current Sense AC Gain

The current measured across the inductor is a square

wave that is averaged by the capacitor (C_S) connected

between +I_SENand -I_SEN. This very small voltage plus

the ripple can be amplified by the current sense AC

gain circuitry. The amount of gain is controlled by the

CSGSCON register.

REGISTER 6-3:

CSGSCON: CURRENT SENSE AC GAIN CONTROL REGISTER

U-0

—

R/W-x

Reserved

CSGS3

CSGS2

CSGS1

CSGS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

Unimplemented: Read as ‘0’

bit 6-4

bit 3-0

Reserved

CSGS<3:0>: Current Sense AC Gain Setting bits

0000= 0 dB

0001= 1.0 dB

0010= 2.5 dB

0011= 4.0 dB

0100= 5.5 dB

0101= 7.0 dB

0110= 8.5 dB

0111= 10.0 dB

1000= 11.5 dB

1001= 13.0 dB

1010= 14.5 dB

1011= 16.0 dB

1100= 17.5 dB

1101= 19.0 dB

1110= 20.5 dB

1111= 22.0 dB

DS20002331D-page 40

 2013-2016 Microchip Technology Inc.

MCP19110/11

6.4

Current Sense DC Gain

DC gain can be added to the sensed inductor current to

allow it to be read by the ADC. The amount of DC gain

added is controlled by the CSDGCON register.

Adding DC gain to the current sense signal used by the

control loop may also be needed in some multi-phase

systems to account for device and component

differences. The CSDGEN bit determines if the gained

current sense signal is added back to the AC current

signal (see Register 6-4). If the CSDGEN bit is cleared,

DC gain can still be added, but the gained signal is not

added back to the AC current signal.

REGISTER 6-4:

CSDGCON: CURRENT SENSE DC GAIN CONTROL REGISTER

R/W-0

CSDGEN

bit 7

U-0

—

U-0

—

U-0

—

R/W-x

Reserved

CSDG2

CSDG1

CSDG0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

CSDGEN: Current Sense DC Gain Enable bit

1= DC gain current sense signal used in control loop.

0= DC gain current sense signal only read by ADC.

bit 6-4

bit 3

Unimplemented: Read as ‘0’

Reserved

bit 2-0

CSDG<2:0>: Current Sense DC Gain Setting bits

000= 19.5 dB

001= 21.8 dB

010= 24.1 dB

011= 26.3 dB

100= 28.6 dB

101= 30.9 dB

110= 33.2 dB

111= 35.7 dB

 2013-2016 Microchip Technology Inc.

DS20002331D-page 41

MCP19110/11

6.5

Voltage for Zero Current

In multi-phase systems it may be necessary to provide

some offset to the sensed inductor current. The

VZCCON register can be used to provide a positive or

negative offset in the sensed current. Typically, the

VZCCON will be set to 0x80h, which corresponds to

the sensed inductor current centered around 1.45V.

However, by adjusting the VZCCON register, this

centered voltage can be shifted up or down by

approximately 3.28 mV per step.

REGISTER 6-5:

VZCCON: VOLTAGE FOR ZERO CURRENT CONTROL REGISTER

R/W-x

VZC7

R/W-x

VZC6

R/W-x

VZC5

R/W-x

VZC4

R/W-x

VZC3

R/W-x

VZC2

R/W-x

VZC1

R/W-x

VZC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

VZC<7:0>: Voltage for Zero Current Setting bits

00000000= -420.00 mV Offset

00000001= -416.72 mV Offset

•

10000000= 0 mV Offset

•

11111110= +413.12 mV Offset

11111111= +416.40 mV Offset

DS20002331D-page 42

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MCP19110/11

FIGURE 6-1:

SIMPLIFIED

COMPENSATION

6.6

Compensation Setting

The MCP19110/11 uses a peak current mode control

architecture. A control reference is used to regulate the

peak current of the converter directly. The inner current

loop essentially turns the inductor into a voltage-

controlled current source. This reduces the control-to-

output transfer function to a simple single-pole model of

a current source feeding a capacitor. The desired

response of the overall loop can be tuned by proper

placement of the compensation zero frequency and

gain. Figure 6-1 shows a simplified drawing of the

internal compensation. See Register 6-6 for the

adjustable zero frequency and gain settings.

+V_SEN

-V_SEN

V_REF

REGISTER 6-6:

CMPZCON: COMPENSATION SETTING CONTROL REGISTER

R/W-x

CMPZF3

bit 7

R/W-x

CMPZF2

CMPZF1

CMPZF0

CMPZG3

CMPZG2

CMPZG1

CMPZG0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

CMPZF<3:0>: Compensation Zero Frequency Setting bits

0000= 1500 Hz

0001= 1850 Hz

0010= 2300 Hz

0011= 2840 Hz

0100= 3460 Hz

0101= 4300 Hz

0110= 5300 Hz

0111= 6630 Hz

1000= 8380 Hz

1001= 9950 Hz

1010= 12200 Hz

1011= 14400 Hz

1100= 18700 Hz

1101= 23000 Hz

1110= 28400 Hz

1111= 35300 Hz

bit 3-0

CMPZG<3:0>: Compensation Gain Setting bits

0000= 36.15 dB

0001= 33.75 dB

0010= 30.68 dB

0011= 28.43 dB

0100= 26.10 dB

0101= 23.81 dB

0110= 21.44 dB

0111= 19.10 dB

1000= 16.78 dB

1001= 14.32 dB

1010= 12.04 dB

1011= 9.54 dB

1100= 7.23 dB

1101= 4.61 dB

1110= 2.28 dB

1111= 0.00 dB

 2013-2016 Microchip Technology Inc.

DS20002331D-page 43

MCP19110/11

The amount of negative slope added to the error ampli-

fier output is controlled by Register 6-7.

6.7

Slope Compensation

A negative voltage slope is added to the output of the

error amplifier. This is done to prevent subharmonic

instability when:

The slope compensation is enabled by setting the

SLCPBY bit in the ABECON register.

1. the operating duty cycle is greater than 50%

2. wide changes in the duty cycle occur.

REGISTER 6-7:

SLPCRCON: SLOPE COMPENSATION RAMP CONTROL REGISTER

R/W-x

SLPG3

bit 7

R/W-x

SLPG2

SLPG1

SLPG0

SLPS3

SLPS2

SLPS1

SLPS0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

SLPG<3:0>: Slope Compensation Amplitude Configuration bits

0000= 0.017 V_PK-PK, measured for 50% duty cycle waveform

0001= 0.022 V_PK-PK, measured for 50% duty cycle waveform

0010= 0.030 V_PK-PK, measured for 50% duty cycle waveform

0011= 0.040 V_PK-PK, measured for 50% duty cycle waveform

0100= 0.053 V_PK-PK, measured for 50% duty cycle waveform

0101= 0.070 V_PK-PK, measured for 50% duty cycle waveform

0110= 0.094 V_PK-PK, measured for 50% duty cycle waveform

0111= 0.125 V_PK-PK, measured for 50% duty cycle waveform

1000= 0.170 V_PK-PK, measured for 50% duty cycle waveform

1001= 0.220 V_PK-PK, measured for 50% duty cycle waveform

1010= 0.300 V_PK-PK, measured for 50% duty cycle waveform

1011= 0.400 V_PK-PK, measured for 50% duty cycle waveform

1100= 0.530 V_PK-PK, measured for 50% duty cycle waveform

1101= 0.700 V_PK-PK, measured for 50% duty cycle waveform

1110= 0.940 V_PK-PK, measured for 50% duty cycle waveform

1111= 1.250 V_PK-PK, measured for 50% duty cycle waveform

bit 3-0

6.7.1

SLPS<3:0>: Slope Compensation V/t Configuration bits

SLPS<3:0> CONFIGURATION

6.7.2

SLPG<3:0> CONFIGURATION

The SLPS<3:0> directly controls the V/t of the

added ramp. This byte should be set proportional to

the switching frequency according to the following

equation:

The SLPG<3:0> controls the amplitude of the added

ramp. The values listed above correspond to a 50%

duty cycle waveform and is true only if the SLPS<3:0>

bits are set according to the equation in Section 6.7.1

“SLPS<3:0> Configuration”. If less amplitude is

required, the SLPS<3:0> bits can be adjusted to a

lower switching frequency.

EQUATION 6-1:

F_SW









--------------------

n =

– 1

100 000

Where:

F_SW= Device switching frequency

n = Decimal equivalent of SLPS<3:0>

DS20002331D-page 44

 2013-2016 Microchip Technology Inc.

MCP19110/11

6.8

MASTER Error Signal Gain

Note:

The SLVGNCON register is configured in

the multi-phase SLAVE device.

When operating in a multi-phase system, the output of

the MASTER’s error amplifier is used by all SLAVE

devices as their control signal. It is important to balance

the current in all phases to maintain a uniform

temperature across all phases. Component tolerances

make this balancing difficult. Each SLAVE device has

the ability to gain or attenuate the MASTER error signal

depending upon the settings of Register 6-8.

REGISTER 6-8:

SLVGNCON: MASTER ERROR SIGNAL INPUT GAIN CONTROL REGISTER

U-0

—

U-0

—

U-0

—

R/W-x

SLVGN4

SLVGN3

SLVGN2

SLVGN1

SLVGN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

SLVGN<4:0>: MASTER Error Signal Gain bits

00000= -3.3 dB

00001= -3.1 dB

00010= -2.9 dB

00011= -2.7 dB

00100= -2.5 dB

00101= -2.3 dB

00110= -2.1 dB

00111= -1.9 dB

01000= -1.7 dB

01001= -1.4 dB

01010= -1.2 dB

01011= -1.0 dB

01100= -0.8 dB

01101= -0.6 dB

01110= -0.4 dB

01111= -0.2 dB

10000= 0.0 dB

10001= 0.2 dB

10010= 0.4dB

10011= 0.7 dB

10100= 0.9 dB

10101= 1.1 dB

10110= 1.3 dB

10111= 1.5 dB

11000= 1.7 dB

11001= 1.9 dB

11010= 2.1 dB

11011= 2.3 dB

11100= 2.6 dB

11101= 2.8 dB

11110= 3.0 dB

11111= 3.2 dB

 2013-2016 Microchip Technology Inc.

DS20002331D-page 45

MCP19110/11

FIGURE 6-2:

MOSFET DRIVER

DEAD TIME

6.9

MOSFET Driver Programmable

Dead Time

The turn-on delay of the high-side and low-side drive

signals can be configured independently to allow differ-

ent MOSFETs and circuit board layouts to be used to

construct an optimized system. See Figure 6-2.

HDRV

HDLY

Setting the HDLYBY and LDLYBY bits of the PE1

register enables the high-side and low-side delay,

respectively. The amount of delay added is controlled

in the DEADCON register. See Register 6-9 for more

information.

LDLY

LDRV

REGISTER 6-9:

DEADCON: DRIVER DEAD TIME CONTROL REGISTER

R/W-x

HDLY3

bit 7

R/W-x

LDLY3

R/W-x

LDLY2

R/W-x

LDLY1

R/W-x

LDLY0

HDLY2

HDLY1

HDLY0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

HDLY<3:0>: High-Side Dead Time Configuration bits

0000= 11 ns delay

0001= 15 ns delay

0010= 19 ns delay

0011= 23 ns delay

0100= 27 ns delay

0101= 31 ns delay

0110= 35 ns delay

0111= 39 ns delay

1000= 43 ns delay

1001= 47 ns delay

1010= 51 ns delay

1011= 55 ns delay

1100= 59 ns delay

1101= 63 ns delay

1110= 67 ns delay

1111= 71 ns delay

bit 3-0

LDLY<3:0>: Low-Side Dead Time Configuration bits

0000= 4 ns delay

0001= 8 ns delay

0010= 12 ns delay

0011= 16 ns delay

0100= 20 ns delay

0101= 24 ns delay

0110= 28 ns delay

0111= 32 ns delay

1000= 36 ns delay

1001= 40 ns delay

1010= 44 ns delay

1011= 48 ns delay

1100= 52 ns delay

1101= 56 ns delay

1110= 60 ns delay

1111= 64 ns delay

DS20002331D-page 46

 2013-2016 Microchip Technology Inc.

MCP19110/11

6.10 Output Voltage Configuration

Note:

The OVFCON<VOUTEN> bit must be set

to enable the output voltage setting

registers.

Two registers control the error amplifier reference

voltage. The reference is coarsely set in 15 mV steps

and then finely adjusted in 0.82 mV steps above the

coarse setting (see Registers 6-10 and 6-11). Higher

output voltages can be achieved by using a voltage

divider connected between the output and the +V_SEN

pin. Care must be taken to ensure maximum voltage

rating compliance on all pins.

The units for the OVC<7:0> and

OVF<4:0> equations are volts.

REGISTER 6-10: OVCCON: OUTPUT VOLTAGE SET POINT COARSE CONTROL REGISTER

R/W-0

OVC7

R/W-0

OVC6

R/W-0

OVC5

R/W-0

OVC4

R/W-0

OVC3

R/W-0

OVC2

R/W-0

OVC1

R/W-0

OVC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

OVC<7:0>: Output Voltage Set Point Coarse Configuration bits (Note)

OVC<7:0>= (V_OUT/0.0158)-1

REGISTER 6-11: OVFCON: OUTPUT VOLTAGE SET POINT FINE CONTROL REGISTER

R/W-0

U-0

—

U-0

—

R/W-0

OVF4

R/W-0

OVF3

R/W-0

OVF2

R/W-0

OVF1

R/W-0

OVF0

VOUTEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

VOUTEN: Output Voltage DAC Enable bit

1= Output Voltage DAC is enabled

0= Output Voltage DAC is disabled

Unimplemented: Read as ‘0’

bit 6-5

bit 4-0

OVF<4:0>: Output Voltage Set Point Fine Configuration bits (Note)

OVF<4:0>= (V_OUT– V_{OUT_COARSE})/0.0008

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DS20002331D-page 47

MCP19110/11

6.11 Output Undervoltage

Note:

The units for the OUV<7:0> equation are

volts.

The output voltage is monitored, and when it is below

the output undervoltage threshold, the UVIF flag is set.

This flag must be cleared in software. See

Section 15.3.1.4 “PIR2 Register” for more

information.

The output undervoltage threshold is controlled by the

OUVCON register, as shown in Register 6-12.

REGISTER 6-12: OUVCON: OUTPUT UNDERVOLTAGE DETECT LEVEL CONTROL REGISTER

R/W-x

OUV7

R/W-x

OUV6

R/W-x

OUV5

R/W-x

OUV4

R/W-x

OUV3

R/W-x

OUV2

R/W-x

OUV1

R/W-x

OUV0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

OUV<7:0>: Output Undervoltage Detect Level Configuration bits

OUV<7:0>= (V_{OUT_UV_Detect_Level})/0.015

6.12 Output Overvoltage

Note:

The units for the OOV<7:0> equation are

volts.

The output voltage is monitored, and when it is above

the output overvoltage threshold, the OVIF flag is set.

This flag must be cleared in software. See

Section 15.3.1.4 “PIR2 Register” for more

information.

The output overvoltage threshold is controlled by the

OOVCON register, as shown in Register 6-13.

REGISTER 6-13: OOVCON: OUTPUT OVERVOLTAGE DETECT LEVEL CONTROL REGISTER

R/W-x

OOV7

R/W-x

OOV6

R/W-x

OOV5

R/W-x

OOV4

R/W-x

OOV3

R/W-x

OOV2

R/W-x

OOV1

R/W-x

OOV0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

OOV<7:0>: Output Overvoltage Detect Level Configuration bits

OOV<7:0>= (V_{OUT_OV_Detect_Level})/0.015

DS20002331D-page 48

 2013-2016 Microchip Technology Inc.

MCP19110/11

6.13.4

OUTPUT VOLTAGE SENSE

PULL-UP/PULL-DOWN

6.13 Analog Peripheral Control

The MCP19110/11 has various analog peripherals.

These peripherals can be configured to allow custom-

izable operation. Refer to Register 6-14 more informa-

tion.

A high-impedance pull-up on the +V_SENpin can be

configured by setting the PE1<PUEN> bit. When set,

the +V_SENpin is internally pulled-up to V_DD

.

A high-impedance pull-down on the -V_SENcan be

configured by setting the PE1<PDEN> bit. When set,

the -V_SENpin is internally pulled-down to ground.

6.13.1

DIODE EMULATION MODE

The MCP19110/11 can operate in either diode

emulation or synchronous rectification mode. When

operating in diode emulation mode, the LDRV signal is

terminated when the voltage across the low-side

MOSFET is approximately 0V. This condition is true

when the inductor current reaches approximately 0A.

Both the HDRV and LDRV signals are low until the

beginning of the next switching cycle. At that time, the

HDRV signal is asserted high, turning on the high-side

MOSFET.

6.13.5

OUTPUT UNDERVOLTAGE

ACCELERATOR

The MCP19110/11 has additional control circuitry to

allow it to respond quickly to an output undervoltage

condition. The enabling of this circuitry is handled by

the PE1<UVTEE> bit. When this bit is set, the

MCP19110/11 will respond to an output undervoltage

condition by setting both the HDRV and LDRV signals

low and turning off both the high-side and low-side

MOSFETs.

When operating in Synchronous Rectification mode,

the LDRV signal is held high until the beginning of the

next switching cycle. At that time, the HDRV signal is

asserted high, turning on the high-side MOSFET.

6.13.6

OUTPUT OVERVOLTAGE

ACCELERATOR

The PE1<DECON> bit controls the operating mode of

the MCP19110/11.

The MCP19110/11 has additional control circuitry to

allow it to respond quickly to an output overvoltage

condition. The enabling of this circuitry is handled by

the PE1<OVTEE> bit. When this bit is set, the

MCP19110/11 will respond to an output overvoltage

condition by setting both the HDRV and LDRV signals

low and turning off both the high-side and low-side

MOSFETs.

6.13.2

HIGH-SIDE DRIVE STRENGTH

The peak source and sink current of the high-side

driver can be configured to either be 1A source/sink or

2A source/sink. The PE1<DVRSTR> bit determines

the high-side drive strength.

6.13.3

MOSFET DRIVER DEAD TIME

As described in Section 6.9 “MOSFET Driver

Programmable Dead Time”, the MOSFET drive dead

time can be adjusted. In order to enable dead time

settings, the proper bypass bits must be cleared.

PE1<HDLYBY> and PE1<LDLYBY> control the delay

circuits. Clearing the respective bits allows the dead

time programmed by the DEADCON register to be

added to the appropriate turn-on edge.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 49

MCP19110/11

REGISTER 6-14: PE1: ANALOG PERIPHERAL ENABLE 1 CONTROL REGISTER

R/W-0

PDEN

R/W-0

PUEN

R/W-0

DECON

DVRSTR

HDLYBY

LDLYBY

UVTEE

OVTEE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DECON: Diode Emulation Mode bit

1= Diode emulation mode enabled

0= Synchronous rectification mode enabled

DVRSTR: High-Side Drive Strength Configuration bit

1= High-side 1A source/sink drive strength

0= High-side 2A source/sink drive strength

HDLYBY: High-Side Dead Time Bypass bit

1= High-side dead time bypass is enabled

0= High-side dead time bypass is disabled

LDLYBY: Low-Side Dead Time Bypass bit

1= Low-side dead time bypass is enabled

0= Low-side dead time bypass is disabled

PDEN: -V_SENWeak Pull Down Enable bit

1= -V_SENweak pull down is enabled

0= -V_SENweak pull down is disabled

PUEN: +V_SENWeak Pull Up Enable bit

1= +V_SENweak pull up is enabled

0= +V_SENweak pull up is disabled

UVTEE: Output Undervoltage Accelerator Enable bit

1= Output undervoltage accelerator is enabled

0= Output undervoltage accelerator is disabled

OVTEE: Output Overvoltage Accelerator Enable bit

1= Output overvoltage accelerator is enabled

0= Output overvoltage accelerator is disabled

DS20002331D-page 50

 2013-2016 Microchip Technology Inc.

MCP19110/11

6.14.6

INTERNAL TEMPERATURE

MEASUREMENT CONTROL

6.14 Analog Blocks Enable Control

Various analog circuit blocks can be enabled or

disabled, as shown in Register 6-15. Additional enable

bits are located in the ATSTCON register.

The internal temperature of the silicon can be

measured with the ADC. To enable the internal

temperature

measurement

circuitry,

the

ABECON<TMPSEN> bit must be set.

6.14.1

OUTPUT OVERVOLTAGE ENABLE

The output overvoltage is enabled by setting the

ABECON<OVDCEN> bit. Clearing this bit will disable

the output overvoltage circuitry and cause the setting in

the OOVCON register to be ignored.

6.14.7

RELATIVE EFFICIENCY CIRCUITY

CONTROL

Section 10.0 “Relative Efficiency Measurement”

describes the procedure used to measure the relative

6.14.2

OUTPUT UNDERVOLTAGE ENABLE

efficiency

of

the

system.

Setting

the

ABECON<RECIREN> bit enables the relative

efficiency measurement circuitry.

The output undervoltage is enabled by setting the ABE-

CON<UVDCEN> bit. Clearing this bit will disable the

output undervoltage circuitry and cause the setting in

the OUVCON register to be ignored.

6.14.8

SIGNAL CHAIN CONTROL

Setting the ABECON<PATHEN> bit enables the

voltage control path. Under normal operation, this bit is

set.

6.14.3

RELATIVE EFFICIENCY

MEASUREMENT CONTROL

Section 10.0 “Relative Efficiency Measurement”

describes the procedure used to measure the relative

efficiency

of

the

system.

Setting

the

ABECON<MEASEN> bit initiates the relative

measurement.

6.14.4

SLOPE COMPENSATION CONTROL

The slope compensation described in Register 6-7 can

be bypassed by setting the ABECON<SLCPBY> bit.

Under normal operation, this bit will always be set.

6.14.5

CURRENT MEASUREMENT

CONTROL

The peak current measurement circuitry is controlled

by the ABECON<CRTMEN> bit. Setting this bit

enables the current measurement circuitry. Under

normal operation, this bit will be set.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 51

MCP19110/11

REGISTER 6-15: ABECON: ANALOG BLOCK ENABLE CONTROL REGISTER

R/W-0

OVDCEN

UVDCEN

MEASEN

SLCPBY

CRTMEN

TMPSEN

RECIREN

PATHEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

OVDCEN: Output overvoltage DAC control bit

1= Output overvoltage DAC is enabled

0= Output overvoltage DAC is disabled

UVDCEN: Output undervoltage DAC control bit

1= Output undervoltage DAC is enabled

0= Output undervoltage DAC is disabled

MEASEN: Relative efficiency measurement control bit

1= Initiate relative efficiency measurement

0= Relative efficiency measurement not in progress

SLCPBY: Slope compensation bypass control bit

1= Slope compensation is disabled

0= Slope compensation is enabled

CRTMEN: Current measurement circuitry control bit

1= Current measurement circuitry is enabled

0= Current measurement circuitry is disabled

TMPSEN: Internal temperature sensor and over temperature control bit

1= Internal temperature sensor and over temperature circuitry is enabled

0= Internal temperature sensor and over temperature circuitry is disabled

RECIREN: Relative efficiency circuitry control bit

1= Relative efficiency measurement circuitry is enabled

0= Relative efficiency measurement circuitry is disabled

PATHEN: Signal chain circuitry control bit

1= Signal chain circuitry is enabled

0= Signal chain circuitry is disabled

DS20002331D-page 52

 2013-2016 Microchip Technology Inc.

MCP19110/11

7.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

Note: Unless otherwise indicated, V_IN= 12V, F_SW= 300 kHz, T_A= +25°C.

1.0

0.8

0.6

0.4

0.2

5.6

5.4

5.2

5.0

4.8

4.6

4.4

4.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (ºC)

0

2

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32

CODE

FIGURE 7-1:

I vs. Temperature.

FIGURE 7-4:

OVFCON DAC INL vs.

Q

Code and Temperature (-40°C to +125°C).

0.2

0.0

0.0016

0.0014

0.0012

0.0010

0.0008

0.0006

0.0004

0.0002

0.0000

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

0

2

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32

CODE

64

128

192

256

CODE

FIGURE 7-2:

OVCCON DAC INL vs.

FIGURE 7-5:

OVFCON DAC DNL vs.

Code and Temperature (-40°C to +125°C).

0.030

0.025

0.020

0.015

0.010

0.005

5.09

I_DD= 1 mA

5.08

5.07

5.06

5.05

5.04

-40ºC

+125ºC

+25ºC

0

64

128

CODE

192

256

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Input Voltage, V_IN(V)

FIGURE 7-3:

OVCCON DAC DNL vs.

FIGURE 7-6:

V

vs. Input Voltage.

DD

Code and Temperature (-40°C to +125°C).

 2013-2016 Microchip Technology Inc.

DS20002331D-page 53

MCP19110/11

Note: Unless otherwise indicated, V_IN= 12V, F_SW= 300 kHz, T_A= +25°C.

5.07

5.06

5.05

5.04

5.03

5.02

5.01

5.00

4.99

3.35

3.34

3.33

3.32

3.31

3.30

3.29

3.28

3.27

3.26

3.25

OVCCON = 0xDCh

+125ºC

+25ºC

- 40ºC

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

Current (mA)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (ºC)

FIGURE 7-7:

V

vs. Output Current.

FIGURE 7-10:

V

vs. Temperature

REGREF

DD

(V

= 3.3V).

REGREF

80

70

60

50

40

0.63

0.62

0.61

0.60

0.59

0.58

0.57

OVCCON = 0x28h

-40ºC

+125ºC

30

20

10

+25ºC

4

0

2

6

8

10

12

14

16

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (ºC)

HDLY CODE

FIGURE 7-8:

V

vs. Temperature

FIGURE 7-11:

HDRV Dead Time vs.

REGREF

(V

= 0.6V).

HDLY Code.

REGREF

1.84

1.83

1.82

1.81

1.80

1.79

1.78

1.77

70

60

50

40

30

20

10

0

OVCCON = 0x78h

+25ºC

+125ºC

-40ºC

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (ºC)

0

2

4

6

8

10

12

14

16

LDLY CODE

FIGURE 7-9:

(V = 1.8V).

V

vs. Temperature

FIGURE 7-12:

LDLY Code.

LDRV Dead Time vs.

REGREF

DS20002331D-page 54

 2013-2016 Microchip Technology Inc.

MCP19110/11

Note: Unless otherwise indicated, V_IN= 12V, F_SW= 300 kHz, T_A= +25°C.

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

8.05

8.04

8.03

8.02

8.01

8.00

7.99

7.98

7.97

7.96

7.95

DRVSTR = 0

R_HDRV-SOURCE

R_HDRV-SINK

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (ºC)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (ºC)

FIGURE 7-13:

HDRV R

vs.

FIGURE 7-16:

Oscillator Frequency vs.

DSon

Temperature.

3.0

1.64

R_IND= 3.0 m

DRVSTR = 1

1.63

1.62

1.61

1.60

1.59

1.58

1.57

1.56

1.55

1.54

1.53

2.5

2.0

1.5

1.0

0.5

R_HDRV-SOURCE

R_HDRV-SINK

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (ºC)

0

5

10

15

20

25

30

Output Current (A)

FIGURE 7-14:

HDRV R

vs.

FIGURE 7-17:

CRNT Voltage vs. Output

DSon

Temperature.

Current.

24%

22%

20%

18%

16%

14%

12%

10%

8%

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

R_LDRV-SOURCE

6%

4%

R_LDRV-SINK

2%

0%

30

38

47

56

64

73

81

90 100

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (ºC)

CMRR (dB)

FIGURE 7-15:

LDRV R

vs.

FIGURE 7-18:

Remote Sense Amplifier

DSon

Temperature.

CMRR.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 55

MCP19110/11

NOTES:

DS20002331D-page 56

 2013-2016 Microchip Technology Inc.

MCP19110/11

8.1

Analog Bench Test Control

8.0

SYSTEM BENCH TESTING

To allow for easier system design and bench testing,

the MCP19110/11 family of devices feature a multi-

plexer used to output various internal analog signals.

These signals can be measured on the GPA0 pin

through a unity gain buffer. The configuration control of

the GPA0 pin is found in the ATSTCON register, as

shown in Register 8-1.

8.1.1

ATSTCON REGISTER

The ATSTCON register contains the bits used to dis-

able the MOSFET drivers and configure the GPA0 pin

as the unity gain buffer out, as shown in Register 8-1.

Note 1: The DRVDIS bit is reset to ‘1’ so the high-

side and low-side drivers are in a known

state after reset. This bit must be cleared

by software for normal operation.

Control of the signals present at the output of the unity

gain buffer is found in the BUFFCON register, as shown

in Register 8-2.

REGISTER 8-1:

ATSTCON: ANALOG BENCH TEST CONTROL REGISTER

R/W-1

Reserved

bit 7

U-0

—

U-0

—

U-0

R/W-0

HIDIS

R/W-0

LODIS

R/W-0

R/W-1

Reserved

BNCHEN

DRVDIS

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Reserved

bit 6-5

bit 4

Unimplemented: Read as ‘0’

Reserved

bit 3

HIDIS: High-side driver control bit

1= High-side driver is disabled

0= High-side driver is enabled

bit 2

bit 1

bit 0

LODIS: Low-side driver control bit

1= Low-side driver is disabled

0= Low-side driver is enabled

BNCHEN: GPA0 bench test configuration control bit

1= GPA0 is configured for analog bench test output

0= GPA0 is configured for normal operation

DRVDIS: MOSFET driver disable control bit

1= High-side and low-side drivers are set low, PHASE pin is floating

0= High-side and low-side drivers are set for normal operation

 2013-2016 Microchip Technology Inc.

DS20002331D-page 57

MCP19110/11

When measuring signals with the unity gain buffer, the

buffer offset must be added to the measured signal.

The factory measured buffer offset can be read from

memory location 2087h. Refer to Section 11.1.1

“Reading Program Memory as Data” for more infor-

mation.

8.2

Unity Gain Buffer

The unity gain buffer module is used during a multi-

phase application and while operating in Bench Test

mode.

When the ATSTCON<BNCHEN> bit is set, the device

is in Bench Test mode and the ASEL<4:0> bits of the

BUFFCON register determine which internal analog

signal can be measured on the GPA0 pin.

REGISTER 8-2:

BUFFCON: UNITY GAIN BUFFER CONTROL REGISTER

R/W-0

MLTPH2

bit 7

R/W-0

MLTPH1

MLTPH0

ASEL4

ASEL3

ASEL2

ASEL1

ASEL0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-0

MLTPH<2:0>: System configuration bits

000= Device set as stand-alone unit

001= Device set as multiple output MASTER

010= Device set as multiple output SLAVE

011= Device set as multi-phase MASTER

100= Device set as multi-phase SLAVE

ASEL<4:0>: Multiplexer output control bit

00000= Voltage proportional to current in the inductor

00001= Error amplifier output plus slope compensation, input to PWM comparator

00010= Input to slope compensation circuitry

00011= Band gap reference

00100= Output voltage reference

00101= Output voltage after internal differential amplifier

00110= Unimplemented

00111= Voltage proportional to the internal temperature

01000= Internal ground for current sense circuitry, see Section 6.5 “Voltage for Zero Current”

01001= Output overvoltage comparator reference

01010= Output undervoltage comparator reference

01011= Error amplifier output

01100= For a multi-phase SLAVE, error amplifier signal received from MASTER

01101= For multi-phase SLAVE, error signal received from MASTER with gain,

see Section 6.8 “MASTER Error Signal Gain”

01110= V_INdivided down by 13

01111= DC inductor valley current

10000= Unimplemented

•

11100= Unimplemented

11101= Overcurrent reference

11110= Unimplemented

11111= Unimplemented

DS20002331D-page 58

 2013-2016 Microchip Technology Inc.

MCP19110/11

9.1

Calibration Word 1

9.0

DEVICE CALIBRATION

The DOV<3:0> bits at memory location 2080h set the

offset calibration for the output voltage remote sense

differential amplifier. Firmware must read these values

and write them to the DOVCAL register for proper

calibration.

Read-only memory locations 2080h through 208Fh

contain factory calibration data. Refer to Section 18.0

“Flash Program Memory Control” for information on

how to read from these memory locations.

The FCAL<6:0> bits at memory location 2080h set the

internal oscillator calibration. Firmware must read

these values and write them to the OSCCAL register

for proper calibration.

REGISTER 9-1:

CALWD1: CALIBRATION WORD 1 REGISTER

U-0

—

U-0

—

R/P-1

DOV3

R/P-1

DOV2

R/P-1

DOV1

R/P-1

DOV0

bit 13

bit 8

U-0

—

R/P-1

FCAL6

FCAL5

FCAL4

FCAL3

FCAL2

FCAL1

FCAL0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13-12

bit 11-8

bit 7

Unimplemented: Read as ‘0’

DOV<3:0>: Output voltage remote sense differential amplifier offset calibration bits.

Unimplemented: Read as ‘0’

bit 6-0

FCAL<6:0>: Internal oscillator calibration bits.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 59

MCP19110/11

The BGR<3:0> bits at memory location 2082h calibrate

the internal band gap. Firmware must read these

values and write them to the BGRCAL register for

proper calibration.

9.2

Calibration Word 2

The VRO<3:0> bits at memory location 2082h calibrate

the offset of the buffer amplifier of the output voltage

regulation reference set point. This effectively changes

the band gap reference. Firmware must read these

values and write them to the VROCAL register for

proper calibration.

REGISTER 9-2:

CALWD2: CALIBRATION WORD 2 REGISTER

U-0

—

U-0

—

R/P-1

VRO3

R/P-1

VRO2

R/P-1

VRO1

R/P-1

VRO0

bit 13

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

BGR3

R/P-1

BGR2

R/P-1

BGR1

R/P-1

BGR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13-12

bit 11-8

bit 7-4

Unimplemented: Read as ‘0’

VRO<3:0>: Reference voltage offset calibration bits.

Unimplemented: Read as ‘0’

bit 3-0

BGR<3:0>: Internal band gap calibration bits.

DS20002331D-page 60

 2013-2016 Microchip Technology Inc.

MCP19110/11

9.3

Calibration Word 3

The TTA<3:0> bits at memory location 2083h calibrate

the overtemperature shutdown threshold point. Firm-

ware must read these values and write them to the

TTACAL register for proper calibration.

The ZRO<3:0> bits at memory location 2083h calibrate

the offset of the error amplifier. Firmware must read

these values and write them to the ZROCAL register for

proper calibration.

REGISTER 9-3:

CALWD3: CALIBRATION WORD 3 REGISTER

U-0

—

U-0

—

R/P-1

TTA3

R/P-1

TTA2

R/P-1

TTA1

R/P-1

TTA0

bit 13

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

ZRO3

R/P-1

ZRO2

R/P-1

ZRO1

R/P-1

ZRO0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13-12

bit 11-8

bit 7-4

Unimplemented: Read as ‘0’

TTA<3:0>: Overtemperature shutdown threshold calibration bits.

Unimplemented: Read as ‘0’

bit 3-0

ZRO<3:0>: Error amplifier offset voltage calibration bits.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 61

MCP19110/11

9.4

Calibration Word 4

The TANA<9:0> bits at memory location 2084h contain

the ADC reading from the internal temperature sensor

when the silicon temperature is at +30°C. The

temperature coefficient of the internal temperature

sensor is 16 mV/°C.

REGISTER 9-4:

CALWD4: CALIBRATION WORD 4 REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

TANA9

TANA8

bit 13

bit 8

R/P-1

TANA7

bit 7

R/P-1

TANA6

TANA5

TANA4

TANA3

TANA2

TANA1

TANA0

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13-10

bit 9-0

Unimplemented: Read as ‘0’

TANA<9:0>: ADC internal temperature sensor at +30°C calibration bits

TANA<9:0>= (Temperature x 13.3 mV/°C) +1.75

DS20002331D-page 62

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MCP19110/11

9.5

Calibration Word 5

The DIFC<7:0> bits at memory location 2085h contain

the offset voltage information for the output voltage

difference amplifier. The value is an 8-bit two’s

complement number that represents the number of the

OVCCON counts needed to adjust for the differential

amplifier offset. This value can be used to completely

remove the differential amplifier offset.

For example, the offset of the differential amplifier is

measured to be -64 mV. Since one OVCCON count

equals 16 mV, this represents four counts of the

OVCCON register. Therefore, the value stored at

location 2085h would be 0xFCh, where the setting of

the DIFC7 bit represents a negative number.

REGISTER 9-5:

CALWD5: CALIBRATION WORD 5 REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 13

bit 8

R/P-1

DIFC7

bit 7

R/P-1

DIFC6

DIFC5

DIFC4

DIFC3

DIFC2

DIFC1

DIFC0

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13-8

bit 7-0

Unimplemented: Read as ‘0’

DIFC<7:0>: OVCCON counts to adjust for differential amplifier offset calibration bits

 2013-2016 Microchip Technology Inc.

DS20002331D-page 63

MCP19110/11

9.6

Calibration Word 6

The DIFF<7:0> bits at memory location 2086h contain

the offset voltage information for the output voltage

difference amplifier. The value is an 8-bit two’s

complement number that represents the number of the

OVFCON counts needed to adjust for the differential

amplifier offset. This value can be used to completely

remove the differential amplifier offset.

For example, the offset of the differential amplifier is

measured to be +4.2 mV. Since one OVFCON count

equals 0.7 mV, this represents six counts of the

OVFCON register. Therefore the value stored at

location 2086h would be 0x06h, where clearing the

DIFF7 bit represents a positive number.

REGISTER 9-6:

CALWD6: CALIBRATION WORD 6 REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 13

bit 8

R/P-1

DIFF7

bit 7

R/P-1

DIFF6

R/P-1

DIFF5

R/P-1

DIFF4

R/P-1

DIFF3

R/P-1

DIFF2

R/P-1

DIFF1

R/P-1

DIFF0

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13-8

bit 7-0

Unimplemented: Read as ‘0’

DIFF<7:0>: OVFCON counts to adjust for differential amplifier offset calibration bits

DS20002331D-page 64

 2013-2016 Microchip Technology Inc.

MCP19110/11

9.7

Calibration Word 7

The BUFF<7:0> bits at memory location 2087h

represent the offset voltage of the unity gain buffer in

millivolts. This is an 8-bit two’s complement number.

The MSB is the sign bit. If the MSB is set to 1, the

resulting number is negative.

REGISTER 9-7:

CALWD7: CALIBRATION WORD 7 REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 13

bit 8

R/P-1

BUFF7

bit 7

R/P-1

BUFF6

BUFF5

BUFF4

BUFF3

BUFF2

BUFF1

BUFF0

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13-8

bit 7-0

Unimplemented: Read as ‘0’

BUFF<7:0>: Unity gain buffer offset voltage calibration bits

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DS20002331D-page 65

MCP19110/11

NOTES:

DS20002331D-page 66

 2013-2016 Microchip Technology Inc.

MCP19110/11

7. Whenthemeasurementiscomplete,usetheADC

toreadtheRELEFFchannel.Thisvaluebecomes

the Fractional variable in Equation 10-1. This

reading should be accomplished approximately

50ms after the RELESS<MSDONE> bit is set.

10.0 RELATIVE EFFICIENCY

MEASUREMENT

With a constant input voltage, output voltage and load

current, any change in the high-side MOSFET on-time

represents a change in the system efficiency. The

MCP19110/11 is capable of measuring the on-time of

the high-side MOSFET. Therefore, the relative

efficiency of the system can be measured and

optimized by changing the system parameters, such as

switching frequency, driver dead time or high-side drive

strength.

8. Read the value of the RE<6:0> bits in the

RELEFF register and store the reading as

Whole.

9. Clear the ABECON<MEASEN> bit.

10. The relative efficiency is then calculated by the

following equation:

EQUATION 10-1:

10.1 Relative Efficiency Measurement

Procedure

Fractional – Low

High – Low

PR2 + 1









--------------------------------------------------

Whole +

To measure the relative efficiency, the RELEFF regis-

ter, ABECON<MEASEN> and ABECON<RECIREN>

bits, and the ADC RELEFF input are used. The

following steps outlines the measurement process:

Duty Cycle = -------------------------------------------------------------------------------

Where:

Whole = Value obtained in Step 8 of the

measurement procedure

1. Set the ABECON<RECIREN> bit to enable the

measurement circuitry.

Fractional = Value obtained in Step 7 of the

measurement procedure

2. Clear the ABECON<MEASEN> bit.

3. With the ADC, read the RELEFF channel and

store this reading as the High.

High = Value obtained in Step 3 of the

measurement procedure

4. With the ADC, read the VZC channel and store

this reading as the Low.

Low = Value obtained in Step 4 of the

measurement procedure

5. Set the ABECON<MEASEN> bit to initiate a

measurement cycle.

6. Monitor the RELEFF<MSDONE> bit. When set,

it indicates the measurement is complete.

Note 1: The RELEFF<MSDONE> bit is set and

cleared automatically.

REGISTER 10-1: RELEFF: RELATIVE EFFICIENCY MEASUREMENT REGISTER

R/W-0

RE6

R/W-0

RE5

R/W-0

RE4

R/W-0

RE3

R/W-0

RE2

R/W-0

RE1

R/W-0

RE0

MSDONE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

MSDONE: Relative efficiency measurement done bit

1= Relative efficiency measurement is complete

0= Relative efficiency measurement is not complete

bit 6-0

RE<6:0>: Whole clock counts for relative efficiency measurement result

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DS20002331D-page 67

MCP19110/11

NOTES:

DS20002331D-page 68

 2013-2016 Microchip Technology Inc.

MCP19110/11

FIGURE 11-1:

PROGRAM MEMORY MAP

AND STACK FOR

MCP19110/11

11.0 MEMORY ORGANIZATION

There are two types of memory in the MCP19110/11:

• Program Memory

PC<12:0>

• Data Memory

CALL, RETURN

RETFIE, RETLW

- Special Function Registers (SFRs)

- General Purpose RAM

13

Stack Level 1

11.1 Program Memory Organization

The MCP19110/11 has a 13-bit program counter

capable of addressing an 8K x 14 program memory

space. Only the first 4K x 14 (0000h-0FFFh) is

physically implemented. Addressing a location above

this boundary will cause a wrap-around within the first

4K x 14 space. The Reset vector is at 0000h and the

interrupt vector is at 0004h (see Figure 11-1). The width

of the program memory bus (instruction word) is

14-bits. Since all instructions are a single word, the

MCP19110/11 has space for 4K of instructions.

Stack Level 8

Reset Vector

0000h

0004h

0005h

Interrupt Vector

On-Chip Program

Memory

0FFFh

1000h

Shadows 000-FFFh

1FFFh

2000h

2003h

User IDs⁽¹⁾

ICD Instruction⁽¹⁾

Manufacturing Codes⁽¹⁾

Device ID (hardcoded)⁽¹⁾

2004h

2005h

2006h

Config Word⁽¹⁾

Reserved

2007h

2008h

200Ah

200Bh

Reserved for

Manufacturing & Test⁽¹⁾

207Fh

2080h

Calibration Words⁽¹⁾

Unimplemented

208Fh

2090h

20FFh

2100h

Shadows 2000-20FFh

3FFFh

Note 1: Not code protected.

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DS20002331D-page 69

MCP19110/11

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

11.1.1

READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in

program memory. The first method is to use tables of

RETLW instructions. The second method is to set a

Files Select Register (FSR) to point to the program

memory.

11.1.1.1

RETLWInstruction

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u= unchanged).

The RETLWinstruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 11-1.

Therefore, it is recommended that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits, see the Section 29.0

“Instruction Set Summary”.

EXAMPLE 11-1:

constants

RETLW INSTRUCTION

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

;Index0 data

;Index1 data

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

;… THE CONSTANT IS IN W

11.2 Data Memory Organization

The data memory (see Table 11-1) is partitioned into

four banks, which contain the General Purpose

Registers (GPR) and the Special Function Registers

(SFR). The Special Function Registers are located in

the first 32 locations of each bank. Register locations

20h-7Fh in Bank 0, A0h-EFh in Bank 1 and 120h-16Fh

in Bank 2 are General Purpose Registers,

implemented as static RAM. All other RAM is

unimplemented and returns ‘0’ when read. The

RP<1:0> bits of the STATUS register are the bank

select bits.

RP1

0

RP0

0

-> Bank 0 is selected

-> Bank 1 is selected

-> Bank 2 is selected

-> Bank 3 is selected

0

1

0

1

To move values from one register to another register,

the value must pass throught the W register. This

means that for all register-to-register moves, two

instruction cycles are required.

The STATUS register, shown in Register 11-1,

contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (RAM)

DS20002331D-page 70

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MCP19110/11

REGISTER 11-1: STATUS: STATUS REGISTER

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC⁽¹⁾

R/W-x

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

IRP: Register Bank Select bit (used for Indirect addressing)

1= Bank 2 & 3 (100h – 1FFh)

0= Bank 0 & 1 (00h – FFh)

bit 6-5

RP<1:0>: Register Bank Select bits (used for Direct addressing)

00= Bank 0 (00h - 7Fh)

01= Bank 1 (80h - FFh)

10= Bank 2 (100h - 17Fh)

11= Bank 3 (180h - 1FFh)

bit 4

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

bit 3

bit 2

bit 1

bit 0

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Digit Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWFinstructions)

1= A carry-out from the 4^thlow-order bit of the result occurred

0= No carry-out from the 4^thlow-order bit of the result

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

11.2.1

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 11-1). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the microcontroller core are described

in this section. Those related to the operation of the

peripheral features are described in the associated

section for that peripheral feature.

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DS20002331D-page 71

MCP19110/11

11.3 DATA MEMORY

TABLE 11-1: MCP19110/11 DATA MEMORY MAP

File

Address

Indirect addr.⁽¹⁾

TMR0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

Indirect addr. ⁽¹⁾80h

Indirect addr.⁽¹⁾

TMR0

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

Indirect addr. ⁽¹⁾180h

OPTION_REG

PCL

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

OPTION_REG

PCL

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

PCL

STATUS

FSR

STATUS

FSR

STATUS

FSR

STATUS

FSR

PORTGPA

PORTGPB

PIR1

TRISGPA

TRISGPB

PIE1

WPUGPA

WPUGPB

PE1

IOCA

IOCB

ANSELA

ANSELB

PIR2

PIE2

BUFFCON

ABECON

PCLATH

INTCON

PCON

APFCON

PCLATH

INTCON

PCLATH

INTCON

TMR1L

TMR1H

T1CON

TMR2

PCLATH

INTCON

PORTICD⁽²⁾

TRISICD⁽²⁾

ICKBUG⁽²⁾

BIGBUG⁽²⁾

PMCON1

PMCON2

PMADRL

PMADRH

PMDATL

T2CON

PR2

VINLVL

SSPADD

SSPBUF

OCCON

SSPCON1

SSPCON2

SSPCON3

SSPMSK

SSPSTAT

SSPADD2

SSPMSK2

PWMPHL

PWMPHH

PWMRL

CSGSCON

CSDGCON

PMDATH

PWMRH

VZCCON

CMPZCON

OUVCON

OSCCAL

DOVCAL

TTACAL

BGRCAL

VROCAL

ZROCAL

OVCCON

OVFCON

OSCTUNE

ADRESL

ADRESH

ADCON0

ADCON1

OOVCON

DEADCON

SLPCRCON

SLVGNCON

RELEFF

ATSTCON

General

Purpose

Register

80 Bytes

General

Purpose

Register

General

Purpose

Register

80 bytes

EFh

F0h

16F

1EF

96 Bytes

Accesses

Bank 0

Accesses

Bank 0

170h

Accesses

Bank 0

1F0h

7Fh

FFh

17Fh

1FFh

Bank 0

Bank 1

Bank2

Bank3

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

2: Only accessible when DBGEN = 0 and ICKBUG<INBUG> = 1.

DS20002331D-page 72

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MCP19110/11

TABLE 11-2: MCP19110/11 SPECIAL REGISTERS SUMMARY BANK 0

Value on

Adr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR Reset

(1)

resets

Bank 0

00h INDF

01h TMR0

02h PCL

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module’s Register

xxxx xxxx xxxx xxxx

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

Program Counter's (PC) Least Significant byte

03h STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

04h FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

05h PORTGPA

GPA7

GPA6

GPA5

GPB5

BCLIF

OCIF

—

GPA4

GPB4

SSPIF

OVIF

—

GPA3

—

GPA2

GPB2

—

GPA1

GPB1

GPA0

GPB0

06h PORTGPB

07h PIR1

GPB7

—

GPB6

ADIF

—

xxx- xxxx uuu- uuuu

-000 --00 -000 --00

—

TMR2IF

VINIF

TMR1IF

08h PIR2

UVIF

—

DCERIF 0-00 --00 0-00 --00

09h PCON

---- -qq- ---- -uu-

—

OT

POR

—

0Ah PCLATH

0Bh INTCON

0Ch TMR1L

—

Write buffer for upper 5 bits of program counter

INTE IOCE T0IF INTF

---0 0000 ---0 0000

(3)

GIE

PEIE

T0IE

IOCF

0000 000x 0000 000u

xxxx xxxx uuuu uuuu

Holding register for the Least Significant byte of the 16-bit TMR1

Holding register for the Most Significant byte of the 16-bit TMR1

TMR1H

0Dh

xxxx xxxx

uuuu uuuu

T1CON

0Eh

—

T1CKPS1 T1CKPS0

—

TMR1CS

TMR1ON --00 --00

--uu --uu

uuuu uuuu

---- -000

1111 1111

—

0Fh TMR2

10h T2CON

11h PR2

Timer2 Module Register

0000 0000

—

TMR2ON T2CKPS1 T2CKPS0

---- -000

1111 1111

—

Timer2 Module Period Register

Unimplemented

12h

—

13h PWMPHL

14h PWMPHH

15h PWMRL

16h PWMRH

SLAVE Phase Shift Register

PWM Register Low Byte

PWM Register High Byte

Unimplemented

xxxx xxxx uuuu uuuu

17h

18h

—

Unimplemented

19h OVCCON

1Ah OVFCON

OVC7

OVC6

—

OVC5

—

OVC4

OVF4

OVC3

OVF3

OVC2

OVF2

OVC1

OVF1

OVC0

OVF0

0000 0000 0000 0000

VOUTON

0--0 0000 0--0 0000

---0 0000 ---0 0000

xxxx xxxx uuuu uuuu

1Bh OSCTUNE

—

TUN4

TUN3

TUN2

TUN1

TUN0

ADRESL

1Ch

Least significant 8 bits of the right-shifted result

Most significant 2 bits of right-shifted result

ADRESH

1Dh

---- --xx uuuu uuuu

1Eh ADCON0

1Fh ADCON1

CHS3

—

CHS4

CHS2

CHS1

—

CHS0

—

GO/DONE

—

ADON

—

-000 0000 -000 0000

-000 ---- -000 ----

ADCS2

ADCS1

ADCS0

Legend:

Note 1:

— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.

IRP & RP1 bits are reserved, always maintain these bits clear.

MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will set again if the

mismatch exists.

2:

3:

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DS20002331D-page 73

MCP19110/11

TABLE 11-3: MCP19110/11 SPECIAL REGISTERS SUMMARY BANK 1

Values on

all other

resets

Value on

POR Reset

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

Bank 1

80h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

81h

OPTION_REG

1111 1111 1111 1111

RAPU

INTEDG

T0CS

Program Counter's (PC) Least Significant byte

RP0 TO PD

Indirect data memory address pointer

T0SE

PSA

PS2

PS1

PS0

82h

83h

PCL

0000 0000 0000 0000

0001 1xxx 000q quuu

(2)

STATUS

IRP

RP1

Z

DC

C

84h

85h

86h

87h

88h

89h

FSR

xxxx xxxx uuuu uuuu

TRISGPA

TRISGPB

PIE1

TRISA7

TRISB7

—

TRISA6

TRISB6

ADIE

TRISA5

TRISB5

BCLIE

OCIE

TRISA4

TRISB4

SSPIE

OVIE

TRISA3

TRISA2

TRISB2

—

TRISA1

TRISB1

TMR2IE

VINIE

—

TRISA0 1111 1111 1111 1111

TRISB0 1111 1111 1111 1111

—

TMR1IE -000 --00 -000 --00

DCERIE 0-00 --00 0-00 --00

CLKSEL ---- ---0 ---- ---0

PIE2

UVIE

—

APFCON

—

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

PCLATH

INTCON

—

Write buffer for upper 5 bits of program counter

---0 0000 ---0 0000

0000 000x 0000 000u

(4)

GIE

PEIE

T0IE

INTE

IOCE

T0IF

INTF

IOCF

Unimplemented

—

VINLVL

UVLOEN

OCEN

—

OCLEB1

—

UVLO5

UVLO4

OOC4

UVLO3

OOC3

UVLO2

OOC2

UVLO1

OOC1

UVLO0

OOC0

0-xx xxxx 0-uu uuuu

0xxx xxxx 0uuu uuuu

--xx xxxx --uu uuuu

-xxx xxxx -uuu uuuu

xxxx xxxx uuuu uuuu

0--- xxxx 0--- uuuu

---- xxxx ---- uuuu

xxxx xxxx uuuu uuuu

---x xxxx ---u uuuu

0000 0000 0000 0000

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

OCCON

—

OCLEB0

Reserved Reserved Reserved Reserved Reserved Reserved

CSGS3 CSGS2 CSGS1 CSGS0

CSGSCON

—

Reserved Reserved Reserved

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

CSDGCON

—

CSDGEN

—

Reserved

Reserved Reserved Reserved Reserved

VZC3 VZC2 VZC1 VZC0

CSDG2

CSDG1

CSDG0

VZCCON

CMPZCON

OUVCON

OOVCON

DEADCON

VZC7

VZC6

VZC5

VZC4

CMPZF3 CMPZF2 CMPZF1 CMPZF0 CMPZG3 CMPZG2 CMPZG1 CMPZG0

OUV7

OOV7

HDLY3

SLPG3

—

OUV6

OOV6

HDLY2

SLPG2

—

OUV5

OOV5

HDLY1

SLPG1

—

OUV4

OOV4

HDLY0

SLPG0

SLVGN4

RE4

OUV3

OOV3

LDLY3

SLPS3

SLVGN3

RE3

OUV2

OOV2

LDLY2

SLPS2

SLVGN2

RE2

OUV1

OOV1

LDLY1

SLPS1

SLVGN1

RE1

OUV0

OOV0

LDLY0

SLPS0

SLVGN0

RE0

9Ch SLPCRCON

9Dh SLVGNCON

9Eh

9Fh

RELEFF

—

MSDONE

RE6

RE5

Unimplemented

—

Legend:

Note 1:

— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.

IRP & RP1 bits are reserved, always maintain these bits clear.

RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.

MCLR and WDT Reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will set again if the

mismatch exists.

2:

3:

4:

DS20002331D-page 74

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 11-4: MCP19110/11 SPECIAL REGISTERS SUMMARY BANK 2

Value on

Adr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR Reset

(1)

resets

Bank 2

100h INDF

101h TMR0

102h PCL

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module’s Register

xxxx xxxx xxxx xxxx

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

Program Counter's (PC) Least Significant byte

(2)

103h STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

104h FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

--1- 1111 --u- uuuu

105h WPUGPA

—

WPUA5

—

WPUA3

WPUA2

WPUA1

WPUA0

106h WPUGPB

107h PE1

WPUB7

DECON

WPUB6

DVRSTR

MLTPH1

1111 -11- uuuu -uu-

WPUB5

WPUB4

LDLYBY

—

WPUB2

PUEN

WPUB1

UVTEE

—

HDLYBY

PDEN

OVTEE

0000 1100 0000 1100

0000 0000 0000 0000

108h BUFFCON MLTPH2

MLTPH0

ASEL4

ASEL3

ASEL2

ASEL1

ASEL0

109h ABECON

OVDCEN UVDCEN MEASEN

SLCPBY

CRTMEN

TMPSEN RECIREN

PATHEN

0000 0000 0000 0000

---0 0000 ---0 0000

0000 000x 0000 000u

10Ah PCLATH

10Bh INTCON

—

Write buffer for upper 5 bits of program counter

(3)

GIE

PEIE

T0IE

INTE

IOCE

T0IF

INTF

IOCF

10Ch

10Dh

—

Unimplemented

—

10Eh

10Fh

—

Unimplemented

ADD<7:0>

—

110h SSPADD

111h SSPBUF

112h SSPCON1

113h SSPCON2

114h SSPCON3

115h SSPMSK

116h SSPSTAT

117h SSPADD2

118h SSPMSK2

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

1111 1111 1111 1111

Synchronous Serial Port Receive Buffer/Transmit Register

WCOL

GCEN

SSPOV

ACKSTAT

PCIE

SSPEN

ACKDT

SCIE

CKP

ACKEN

BOEN

SSPM>3:0>

RCEN

PEN

RSEN

AHEN

SEN

ACKTIM

SDAHT

SBCDE

DHEN

MSK<7:0>

SMP

CKE

D/A

P

S

R/W

UA

BF

—

ADD2<7:0>

MSK2<7:0>

0000 0000 0000 0000

1111 1111 1111 1111

119h

11Ah

11Bh

—

Unimplemented

—

11Ch

11Dh

11Eh

11Fh

—

Unimplemented

—

Legend:

Note 1:

— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.

IRP & RP1 bits are reserved, always maintain these bits clear.

MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will set again if the

mismatch exists.

2:

3:

 2013-2016 Microchip Technology Inc.

DS20002331D-page 75

MCP19110/11

TABLE 11-5: MCP19110/11 SPECIAL REGISTERS SUMMARY BANK 3

Values on

all other

resets

Value on

POR Reset

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

Bank 3

180h INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

181h OPTION_REG

1111 1111 1111 1111

RAPU

INTEDG

T0CS

Program Counter's (PC) Least Significant byte

RP0 TO PD

Indirect data memory address pointer

T0SE

PSA

PS2

PS1

PS0

182h PCL

0000 0000 0000 0000

0001 1xxx 000q quuu

(2)

183h STATUS

IRP

RP1

Z

DC

C

184h FSR

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0000 -000 0000 -000

---- 1111 ---- 1111

--11 -11- --11 -11-

185h IOCA

186h IOCB

187h ANSELA

188h ANSELB

IOCA7

IOCB7

—

IOCA6

IOCB6

—

IOCA5

IOCB5

—

IOCA4

IOCB4

—

IOCA3

—

IOCA2

IOCB2

ANSA2

ANSB2

IOCA1

IOCB1

ANSA1

ANSB1

IOCA0

IOCB0

ANSA0

—

ANSA3

—

ANSB5

ANSB4

189h

—

Unimplemented

Write buffer for upper 5 bits of program counter

INTE IOCE T0IF INTF IOCF

—

18Ah PCLATH

18Bh INTCON

18Ch PORTICD

—

---0 0000 ---0 0000

0000 000x 0000 000u

(4)

GIE

PEIE

T0IE

(5)

In-Circuit Debug Port Register

In-Circuit Debug TRIS Register

In-Circuit Debug Register

18Dh TRISICD

(5)

18Eh ICKBUG

18Fh BIGBUG

0--- ---- 0--- ----

---- ---- ---- ----

-0-- -000 -0-- -000

---- ---- ---- ----

0000 0000 0000 0000

---- 0000 ---- 0000

0000 0000 0000 0000

--00 0000 --00 0000

(5)

In-Circuit Debug Breakpoint Register

WREN

190h PMCON1

191h PMCON2

192h PMADRL

193h PMADRH

194h PMDATL

195h PMDATH

—

CALSEL

—

WR

RD

Program Memory Control Register 2 (not a physical register)

PMADRL7

PMADRL6

PMADRL5

PMADRL4

PMADRL3

PMADRL2

PMADRH2

PMDATL2

PMDATH2

PMADRL1

PMADRH1

PMDATL1

PMDATH1

PMADRL0

PMADRH0

PMDATL0

PMDATH0

—

PMADRH3

PMDATL3

PMDATH3

PMDATL7

PMDATL6

PMDATL5

PMDATH5

PMDATL4

PMDATH4

—

196h

197h

—

Unimplemented

—

198h OSCCAL

199h DOVCAL

19Ah TTACAL

19Bh BGRCAL

—

FCALT6

FCALT5

FCALT4

FCALT3

DOVT3

TTA3

FCALT2

DOVT2

TTA2

FCALT1

DOVT1

TTA1

FCALT0

DOVT0

TTA0

xxxx xxxx uuuu uuuu

—

Reserve Reserved Reserved Reserved

d

BGRT3

BGRT2

BGRT1

BGRT0

19Ch VROCAL

19Dh ZROCAL

—

VROT3

ZROT3

VROT2

ZROT2

VROT1

ZROT1

VROT0

ZROT0

xxxx xxxx uuuu uuuu

19Eh

—

Unimplemented

HIDIS

—

19Fh ATSTCON

—

LODIS

BNCHEN

DRVDIS

1--0 0001 1--0 0001

Legend:

Note 1:

— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.

IRP & RP1 bits are reserved, always maintain these bits clear.

RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.

MCLR and WDT Reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will set again if the

mismatch exists.

2:

3:

4:

5:

Only accessible when DBGEN = 0 and ICKBUG<INBUG> = 1.

DS20002331D-page 76

 2013-2016 Microchip Technology Inc.

MCP19110/11

11.3.0.1

OPTION Register

Note 1: To achieve a 1:1 prescaler assignment

for Timer0, assign the prescaler to the

WDT by setting PSA bit to ‘1’ of the

OPTION register. See Section 23.1.3

“Software Programmable Prescaler”

The OPTION register is a readable and writable

register, which contains various control bits to

configure:

• Timer0/WDT prescaler

• External GPA2/INT interrupt

• Timer0

• Weak pull-ups on PORTGPA and PORTGPB

REGISTER 11-2: OPTION_REG: OPTION REGISTER (Note 1)

R/W-1

RAPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RAPU: Port GPx Pull-up Enable bit

1= Port GPx pull-ups are disabled

0= Port GPx pull-ups are enabled

INTEDG: Interrupt Edge Select bit

0= Interrupt on rising edge of INT pin

1= Interrupt on falling edge of INT pin

T0CE: TMR0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock

T0SE: TMR0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

TMR0

Rate

Bit Value

WDT Rate

000

001

010

011

100

101

110

111

1: 2

1: 4

1: 1

1: 2

1: 8

1: 4

1: 16

1: 32

1: 64

1: 128

1: 256

1: 8

1: 16

1: 32

1: 64

1: 128

Note 1: Individual WPUx bit must also be enabled.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 77

MCP19110/11

11.4.3

COMPUTED FUNCTION CALLS

11.4 PCL and PCLATH

A computed function CALLallows programs to maintain

tables of functions and provides another way to

execute state machines or look-up tables. When

performing a table read using a computed function

CALL, care should be exercised if the table location

crosses a PCL memory boundary (each 256-byte

block).

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 11-2 shows the two

situations for loading the PC. The upper example in

Figure 11-2 shows how the PC is loaded on a write to PCL

(PCLATH<4:0>  PCH). The lower example in

Figure 11-2 shows how the PC is loaded during a CALLor

GOTOinstruction (PCLATH<4:3>  PCH).

If using the CALLinstruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<4:3> is loaded with PCLATH<4:3>.

11.4.4

STACK

FIGURE 11-2:

LOADING OF PC IN

DIFFERENT SITUATIONS

The MCP19110/11 has an 8-level x 13-bit wide hard-

ware stack (refer to Figure 11-1). The stack space is

not part of either program or data space and the Stack

Pointer is not readable or writable. The PC is PUSHed

onto the stack when a CALLinstruction is executed or

an interrupt causes a branch. The stack is POPed in

the event of a RETURN, RETLWor a RETFIEinstruction

execution. PCLATH is not affected by a PUSH or POP

operation.

PCH

PCL

12

8 7

0

Instruction with

Destination

PC

8

PCLATH<4:0>

5

ALU Result

PCLATH

PCL

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

PCH

12 11 10 8 7

0

GOTO, CALL

PC

PCLATH<4:3>

11

2

Opcode <10:0>

Note 1: There are no Status bits to indicate Stack

PCLATH

MODIFYING PCL

Overflow or Stack Underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interrupt address.

11.4.1

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

content of the program counter to be changed by

writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are written to the PCL register, all

13 bits of the program counter will change to the values

contained in the PCLATH register and those being

written to the PCL register.

11.5 Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register

actually accesses data pointed to by the File Select

Register (FSR). Reading INDF itself indirectly will

produce 00h. Writing to the INDF register directly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR and the IRP bit of the

STATUS register, as shown in Figure 11-3.

11.4.2

COMPUTED GOTO

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFFh to 0X00h in the middle

of the table, then PCLATH must be incremented for

each address rollover that occurs between the table

beginning and the table location within the table.

A simple program to clear RAM location 40h-7Fh using

indirect addressing is shown in Example 11-2.

For more information, refer to Application Note AN556

– “Implementing a Table Read” (DS00556).

DS20002331D-page 78

 2013-2016 Microchip Technology Inc.

MCP19110/11

EXAMPLE 11-2:

INDIRECT ADDRESSING

MOVLW

MOVWF

0x40

FSR

;initialize pointer

;to RAM

INCF

BTFSS

GOTO

INDF

FSR

FSR,7

;inc pointer

;all done?

;no clear next

;yes continue

CONTINUE

FIGURE 11-3:

DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

From Opcode

7

File Select Register

RP1 RP0

6

0

IRP

Bank Select

180h

Location Select

Bank Select

Location Select

00h

00

01

10

11

Data

Memory

7Fh

1FFh

Bank 0

Bank 1 Bank 2

Bank 3

For memory map detail, see Figure 11-2.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 79

MCP19110/11

NOTES:

DS20002331D-page 80

 2013-2016 Microchip Technology Inc.

MCP19110/11

12.0 DEVICE CONFIGURATION

Note:

The DBGEN bit in Configuration Word is

Device Configuration consists of Configuration Word,

and Code Protection.

managed

automatically

by

device

development tools, including debuggers

and programmers. For normal device

operation, this bit should be maintained as

a '1'.

12.1 Configuration Word

There are several Configuration Word bits that allow

different timers to be enabled and memory protection

options. These are implemented as Configuration

Word at 2007h.

REGISTER 12-1: CONFIG – CONFIGURATION WORD REGISTER

R/P-1

U-1

—

R/P-1

WRT1

R/P-1

U-1

—

U-1

—

DBGEN

WRT0

bit 13

bit 8

bit 0

U-1

—

R/P-1

CP

R/P-1

U-1

—

U-1

—

U-1

—

MCLRE

PWRTE

WDTE

bit 7

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13

DBGEN: ICD Debug bit

1= ICD debug mode disabled

0= ICD debug mode enabled

bit 12

Unimplemented: Read as ‘1’

bit 11-10

WRT<1:0>: Flash Program Memory Self Write Enable bit

11= Write protection off

10= 000h to 3FFh write protected, 400h to FFFh may be modified by PMCON1 control

01= 000h to 7FFh write protected, 800h to FFFh may be modified by PMCON1 control

00= 000h to FFFh write protected, entire program memory is write protected.

bit 9-7

bit 6

Unimplemented: Read as ‘1’

CP: Code Protection

1= Program memory code protection is disabled

0= Program memory code protection is enabled

bit 5

MCLRE: MCLR Pin Function Select

1= MCLR pin is MCLR function and weak internal pull-up is enabled

0= MCLR pin is alternate function, MCLR function is internally disabled

bit 4

PWRTE: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

bit 3

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

bit 2-0

Unimplemented: Read as ‘1’

 2013-2016 Microchip Technology Inc.

DS20002331D-page 81

MCP19110/11

12.2 Code Protection

12.3 Write Protection

Code protection allows the device to be protected from

unauthorized access. Internal access to the program

memory is unaffected by any code protection setting.

Write protection allows the device to be protected from

unintended self-writes. Applications, such as

bootloader software, can be protected while allowing

other regions of the program memory to be modified.

12.2.1

PROGRAM MEMORY PROTECTION

The WRT<1:0> bits in the Configuration Word define

the size of the program memory block that is protected.

The entire program memory space is protected from

external reads and writes by the CP bit in the

Configuration Word. When CP = 0, external reads and

writes of the program memory are inhibited and a read

will return all ‘0’s. The CPU can continue to read

program memory, regardless of the protection bit

settings. Writing the program memory is dependent

upon the write protection setting. See Section 12.3

“Write Protection” for more information.

12.4 ID Locations

Four memory locations (2000h – 2003h) are

designated as ID locations where the user can store

checksum or other code identification numbers. These

locations are not accessible during normal execution

but are readable and writable during Program/Verify

mode. Only the Least Significant seven bits of the ID

locations are reported when using MPLAB Integrated

Development Environment (IDE).

DS20002331D-page 82

 2013-2016 Microchip Technology Inc.

MCP19110/11

13.3 Frequency Tuning in User Mode

13.0 OSCILLATOR MODES

In addition to the factory calibration, the base

frequency can be tuned in the user's application. This

frequency tuning capability allows the user to deviate

from the factory-calibrated frequency. The user can

tune the frequency by writing to the OSCTUNE

register (see Register 13-1).

The MCP19110/11 has one oscillator configuration

which is an 8 MHz internal oscillator.

13.1 Internal Oscillator (INTOSC)

The Internal Oscillator module provides a system

clock source of 8 MHz. The frequency of the internal

oscillator can be trimmed with a calibration value in the

OSCTUNE register.

13.2 Oscillator Calibration

The 8 MHz internal oscillator is factory calibrated. The

factory calibration values reside in the read-only

Calibration Word 1 register. These values must be read

from the Calibration Word 1 register and stored in the

OSCCAL register. Refer to Section 18.0 “Flash

Program Memory Control” for the procedure on

reading from program memory.

Note 1: The FCAL<6:0> bits from the Calibration

Word 1 register must be written into the

OSCCAL register to calibrate the internal

oscillator.

REGISTER 13-1: OSCTUNE – OSCILLATOR TUNING REGISTER

U-0

—

U-0

—

U-0

—

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

TUN<4:0>: Frequency Tuning bits

01111= Maximum frequency

01110=

•

00001=

00000= Center frequency. Oscillator Module is running at the calibrated frequency.

11111=

•

10000= Minimum frequency

 2013-2016 Microchip Technology Inc.

DS20002331D-page 83

MCP19110/11

On power up, the device is held in reset by the

power-up time, if the power-up timer is enabled.

13.3.1

OSCILLATOR DELAY UPON

POWER-UP, WAKE-UP AND

BASE FREQUENCY CHANGE

Following a wake-up from Sleep mode or POR, an

internal delay of ~10 µs is invoked to allow the

memory bias to stabilize before program execution

can begin.

In applications where the OSCTUNE register is used to

shift the frequency of the internal oscillator, the

application should not expect the frequency of the

internal oscillator to stabilize immediately. In this case,

the frequency may shift gradually toward the new

value. The time for this frequency shift is less than eight

cycles of the base frequency.

TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCTUNE

—

TUN4

TUN3

TUN2

TUN1

TUN0

83

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources.

TABLE 13-2: SUMMARY OF CALIBRATION WORD ASSOCIATED WITH CLOCK SOURCES

Register

on Page

Name

Bits Bit -/7 Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

CALWD1

13:8

7:0

—

DOV3

DOV2

DOV1

DOV0

59

FCAL6

FCAL5

FCAL4

FCAL3

FCAL2

FCAL1

FCAL0

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources.

DS20002331D-page 84

 2013-2016 Microchip Technology Inc.

MCP19110/11

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

14.0 RESETS

The Reset logic is used to place the MCP19110/11 into

a known state. The source of the Reset can be

determined by using the device status bits.

• Power-on Reset

• MCLR Reset

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Overtemperature Reset (OT)

• MCLR Reset

• MCLR Reset during Sleep

• WDT Reset

WDT wake-up does not cause register resets in the

same manner as a WDT Reset, since wake-up is

viewed as the resumption of normal operation. TO and

PD bits are set or cleared differently in different Reset

situations, as indicated in Table 14-1. Software can use

these bits to determine the nature of the Reset. See

Table 14-2 for a full description of Reset states of all

registers.

• WDT Reset

To allow V_DDto stabilize, an optional power-up timer

can be enabled to extend the Reset time after a POR

event.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 14-1.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 5.0 “Digital

Electrical

Characteristics”

for

pulse-width

specifications.

FIGURE 14-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/V_PPpin

Sleep

WDT

Module

Time-out

Reset

V_DDRise

Detect

Power-on Reset

V_DD

S

R

PWRT

Chip_Reset

On-Chip

RC OSC

11-bit Ripple Counter

Q

Enable PWRT

Note 1: Refer to the Configuration Word register (Register 12-1).

TABLE 14-1: TIME-OUT IN VARIOUS

SITUATIONS

Power-up

Wake-up from

Sleep

PWRTE = 0

PWRTE = 1

T_PWRT

—

 2013-2016 Microchip Technology Inc.

DS20002331D-page 85

MCP19110/11

TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE

POR

TO

PD

Condition

0

u

1

0

1

u

0

Power-on Reset

WDT Reset

WDT Wake-up

u

1

u

0

MCLR Reset during normal operation

MCLR Reset during Sleep

Legend: u= unchanged, x= unknown

14.1 Power-on Reset (POR)

14.2 MCLR

The on-chip POR circuit holds the chip in Reset until

V_DDhas reached a high enough level for proper

operation. To take advantage of the POR, simply

connect the MCLR pin through a resistor to V_DD. This

will eliminate external RC components usually needed

to create Power-on Reset.

MCP19110/11 has a noise filter in the MCLR Reset

path. The filter will detect and ignore small pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

Voltages applied to the MCLR pin that exceed its

specification can result in both MCLR Resets and

excessive current beyond the device specification

during the ESD event. For this reason, Microchip

recommends that the MCLR pin no longer be tied

directly to V_DD. The use of an RC network, as shown in

Figure 14-2, is suggested.

Note:

The POR circuit does not produce an

internal Reset when V_DDdeclines. To

re-enable the POR, V_DDmust reach V_SS

for a minimum of 100 µs.

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure proper operation. If these conditions are not

met, the device must be held in Reset until the

operating conditions are met.

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word register. When

MCLRE = 0, the Reset signal to the chip is generated

internally. When the MCLRE = 1, the MCLR pin

becomes an external Reset input. In this mode, the

MCLR pin has a weak pull-up to V_DD

.

FIGURE 14-2:

RECOMMENDED MCLR

CIRCUIT

V_DD

R₁

1 k (or greater)

R2

MCLR

100 

(needed with

capacitor)

C₁

SW1

(optional)

0.1 µF

(optional, not critical)

DS20002331D-page 86

 2013-2016 Microchip Technology Inc.

MCP19110/11

14.3 Power-up Timer (PWRT)

14.5 Power-Up Timer

The Power-up Timer provides a fixed 64 ms (nominal)

time-out on power-up only, from POR Reset. The

Power-up Timer operates from an internal RC

oscillator. The chip is kept in Reset as long as PWRT is

active. The PWRT delay allows the V_DDto rise to an

acceptable level. A Configuration bit (PWRTE), can

disable (if set) or enable (if cleared or programmed) the

Power-up Timer.

The Power-up Timer optionally delays device execution

after a POR event. This timer is typically used to allow

V_DDto stabilize before allowing the device to start

running.

The Power-up Timer is controlled by the PWRTE bit of

Configuration Word.

14.6 Start-up Sequence

The Power-up Timer delay will vary from chip-to-chip

due to:

Upon the release of a POR, the following must occur

before the device will begin executing:

• V_DDvariation

• Power-up Timer runs to completion (if enabled)

• Oscillator start-up timer runs to completion

• MCLR must be released (if enabled)

• Temperature variation

• Process variation

Note:

Voltage spikes below V_SSat the MCLR

pin, inducing currents greater than 80 mA,

may cause latch-up. Thus, a series resis-

tor of 50-100 should be used when

applying a “low” level to the MCLR pin,

The total time-out will vary based on PWRTE bit status.

For example, with PWRTE bit erased (PWRT disabled),

there will be no time-out at all. Figures 14-3, 14-4

and 14-5 depict time-out sequences.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 14-4). This is useful for testing purposes or

to synchronize more than one MCP19110/11 device

operating in parallel.

rather than pulling this pin directly to V_SS

.

14.4 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDTinstruction within the time-out

period. The TO and PD bits in the STATUS register are

changed to indicate the WDT Reset. See Section 17.0

“Watchdog Timer (WDT)” for more information.

14.6.1

POWER CONTROL (PCON)

REGISTER

The Power Control register PCON (address 8Eh) has

two Status bits to indicate what type of Reset occurred

last.

FIGURE 14-3:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

V_DD

MCLR

Internal POR

T_PWRT

PWRT Time-out

OST Time-out

Internal Reset

T_IOSCST

 2013-2016 Microchip Technology Inc.

DS20002331D-page 87

MCP19110/11

FIGURE 14-4:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

V_DD

MCLR

Internal POR

T_PWRT

PWRT Time-out

OST Time-out

Internal Reset

T_IOSCST

FIGURE 14-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH V

)

DD

V_DD

MCLR

Internal POR

T_PWRT

PWRT Time-out

OST Time-out

Internal Reset

T_IOSCST

DS20002331D-page 88

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS

Wake-up from Sleep through

Interrupt

Wake-up from Sleep through

WDT Time-out

Power-on

Reset

MCLR Reset

WDT Reset

Register

Address

W

—

xxxx xxxx

uuuu uuuu

xxxx xxxx

uuuu uuuu

INDF

00h/80h/

100h/180h

TMR0

PCL

01h/101h

xxxx xxxx

0000 0000

uuuu uuuu

0000 0000

uuuu uuuu

PC + 1⁽³⁾

02h/82h/

102h/182h

STATUS

FSR

03h/83h/

103h/183h

0001 1xxx

xxxx xxxx

000q quuu⁽⁴⁾

uuuu uuuu

uuuq quuu⁽⁴⁾

uuuu uuuu

04h/84h/

104h/184h

PORTGPA

PORTGPB

PIR1

05h

06h

07h

08h

09h

xxxx xxxx

xxx- xxxx

-000 --00

0-00 --00

---- -qq-

---0 0000

uuuu uuuu

uuu- uuuu

-000 --00

0-00 --00

---- -uu-

---0 0000

uuuu uuuu

uuu- uuuu

-uuu --uu

u-uu --uu

---- -uu-

---u uuuu

PIR2

PCON

PCLATH

0Ah/8Ah/

10Ah/18Ah

INTCON

0Bh/8Bh/

0000 000x

0000 000u

uuuu uuuu⁽²⁾

10Bh/18Bh

TMR1L

0Ch

0Dh

0Eh

0Fh

10h

11h

13h

14h

15h

16h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

xxxx xxxx

--00 --00

0000 0000

---- -000

1111 1111

xxxx xxxx

0000 0000

0--0 0000

---0 0000

xxxx xxxx

---- --xx

-000 0000

-000 ----

1111 1111

uuuu uuuu

--uu --uu

uuuu uuuu

---- -000

1111 1111

uuuu uuuu

0000 0000

0--0 0000

---0 0000

uuuu uuuu

---- --uu

-000 0000

-000 ----

1111 1111

uuuu uuuu

--uu --uu

uuuu uuuu

---- -uuu

uuuu uuuu

u--u uuuu

---u uuuu

uuuu uuuu

---- ---uu

-uuu uuuu

-uuu ----

uuuu uuuu

TMR1H

T1CON

TMR2

T2CON

PR2

PWMPHL

PWMPHH

PWMRL

PWMRH

OVCCON

OVFCON

OSCTUNE

ADRESL⁽¹⁾

ADRESH⁽¹⁾

ADCON0⁽¹⁾

ADCON1⁽¹⁾

OPTION_REG 81h/181h

TRISGPA

TRISGPB

Legend:

85h

86h

u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If V_DDgoes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 14-5 for Reset value for specific condition.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 89

MCP19110/11

TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

Wake-up from Sleep through

Power-on

Reset

MCLR Reset

WDT Reset

Interrupt

Wake-up from Sleep through

WDT Time-out

Register

Address

PIE1

87h

88h

-000 --00

0-00 --00

---- ---0

0-xx xxxx

0xxx xxxx

-xxx xxxx

0--- xxxx

xxxx xxxx

---x xxxx

0000 0000

--1- 1111

1111 -11-

0000 1100

000- 0000

0000 0000

xxxx xxxx

0000 0000

1111 1111

-000 --00

0-00 --00

---- ---0

0-uu uuuu

0uuu uuuu

-uuu uuuu

0--- uuuu

uuuu uuuu

---u uuuu

0000 0000

--u- uuuu

uuuu -uu-

0000 1100

000- 0000

0000 0000

uuuu uuuu

0000 0000

-uuu --uu

u-uu --uu

---- ---u

u-uu uuuu

uuuu uuuu

-uuu uuuu

u--- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

--u- uuuu

uuuu -uu-

uuuu uuuu

uuu- uuuu

uuuu uuuu

PIE2

APFCON

VINLVL

89h

90h

OCCON

91h

CSGSCON

CSDGCON

VZCCON

CMPZCON

OUVCON

OOVCON

DEADCON

SLPCRCON

SLVGNCON

RELEFF

WPUGPA

WPUGPB

PE1

93h

95h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

105h

106h

107h

108h

109h

110h

111h

112h

113h

114h

115h

116h

117h

118h

185h

186h

187h

188h

190h

191h

192h

193h

194h

BUFFCON

ABECON

SSPADD

SSPBUF

SSPCON1

SSPCON2

SSPCON3

SSPMSK

SSPSTAT

SSPADD2

SSPMSK2

IOCA

1111 1111

0000 0000

1111 1111

0000 0000

0000 -000

---- 1111

--11 -11-

-0-- -000

---- ----

0000 0000

---- -000

0000 0000

1111 1111

0000 0000

0000 -000

---- 1111

--11 -11-

-0-- -000

---- ----

0000 0000

---- -000

0000 0000

uuuu uuuu

uuuu -uuu

---- uuuu

--uu -uu-

-u-- -uuu

---- ----

uuuu uuuu

---- -uuu

uuuu uuuu

IOCB

ANSELA

ANSELB

PMCON1

PMCON2

PMADRL

PMADRH

PMDATL

Legend:

u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If V_DDgoes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 14-5 for Reset value for specific condition.

DS20002331D-page 90

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

Wake-up from Sleep through

Interrupt

Wake-up from Sleep through

WDT Time-out

Power-on

Reset

MCLR Reset

WDT Reset

Register

Address

PMDATH

195h

198h

199h

19Ah

19Bh

19Ch

19Dh

19F

--00 0000

-xxx xxxx

---- xxxx

1--- 0001

--00 0000

-uuu uuuu

---- uuuu

1--- 0001

--uu uuuu

-uuu uuuu

---- uuuu

u--- uuuu

OSCCAL

DOVCAL

TTACAL

BGRCAL

VROCAL

ZROCAL

ATSTCON

Legend:

u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If V_DDgoes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 14-5 for Reset value for specific condition.

14.7 Determining the Cause of a Reset

TABLE 14-4: RESET STATUS BITS AND

THEIR SIGNIFICANCE

Upon any Reset, multiple bits in the STATUS and

PCON register are updated to indicate the cause of the

Reset. Table 14-4 and Table 14-5 show the Reset

conditions of these registers.

POR TO PD

Condition

0

u

1

0

1

u

1

u

0

u

Power-on Reset

WDT Reset

WDT Wake-up from Sleep

Interrupt Wake-up from Sleep

MCLR Reset during normal

operation

u

0

1

0

x

0

x

0

MCLR Reset during Sleep

Not allowed. TO is set on POR

Not allowed. PD is set on POR

TABLE 14-5: RESET CONDITION FOR SPECIAL REGISTERS (Note 2)

Program

Counter

STATUS

PCON

Register

Condition

Register

0001 1xxx

000u uuuu

Power-on Reset

0000h

---- -u0-

---- -uu-

MCLR Reset during normal operation

MCLR Reset during Sleep

WDT Reset

0000h

0001 0uuu

0000 uuuu

uuu0 0uuu

uuu1 0uuu

---- -uu-

WDT Wake-up from Sleep

Interrupt Wake-up from Sleep

PC + 1

PC + 1⁽¹⁾

Legend:

u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack

and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 91

MCP19110/11

14.8 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits

to differentiate between a:

• Power-on Reset (POR)

• Overtemperature (OT)

The PCON register bits are shown in Register 14-1.

REGISTER 14-1: PCON – POWER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

OT

R/W-0

POR

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-3

bit 2

Unimplemented: Read as '0'

OT: Overtemperature Reset Status bit

1= No Overtemperature Reset occurred

0= An Overtemperature Reset occurred (must be set in software after an Overtemperature occurs)

bit 1

bit 0

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

Unimplemented: Read as '0'

TABLE 0-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

PCON

—

OT

Z

POR

DC

—

C

92

71

STATUS

IPR

RP1

RP0

TO

PD

Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

DS20002331D-page 92

 2013-2016 Microchip Technology Inc.

MCP19110/11

15.1 Interrupt Latency

15.0 INTERRUPTS

For external interrupt events, such as the INT pin or

PORTGPx change interrupt, the interrupt latency will

be three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 15-2). The latency is the same for one or

two-cycle instructions.

The MCP19110/11 has multiple sources of interrupt:

• External Interrupt (INT pin)

• Interrupt-On-Change (IOC) Interrupts

• Timer0 Overflow Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• ADC Interrupt

15.2 GPA2/INT Interrupt

• System Overvoltage Error

• System Undervoltage Error

• System Overcurrent Error

• SSP

The external interrupt on the GPA2/INT pin is

edge-triggered; either on the rising edge, if the INTEDG

bit of the OPTION register is set, or the falling edge, if

the INTEDG bit is cleared. When a valid edge appears

on the GPA2/INT pin, the INTF bit of the INTCON

register is set. This interrupt can be disabled by

clearing the INTE control bit of the INTCON register.

The INTF bit must be cleared by software in the

Interrupt Service Routine before re-enabling this

interrupt. The GPA2/INT interrupt can wake-up the

processor from Sleep, if the INTE bit was set prior to

going into Sleep. See Section 16.0 “Power-Down

Mode (Sleep)” for details on Sleep, and Section 16.1

“Wake-up from Sleep” for timing of wake-up from

Sleep through GPA2/INT interrupt.

• BCL

• System Input Undervoltage Error

The Interrupt Control register (INTCON) and Peripheral

Interrupt Request Registers (PIRx) record individual

interrupt requests in flag bits. The INTCON register

also has individual and global interrupt enable bits.

The Global Interrupt Enable bit, GIE of the INTCON

register, enables (if set) all unmasked interrupts, or

disables (if cleared) all interrupts. Individual interrupts

can be disabled through their corresponding enable

bits in the INTCON register and PIEx registers. GIE is

cleared on Reset.

Note:

The ANSEL register must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs

will read ‘0’ and cannot generate an

interrupt.

When an interrupt is serviced, the following actions

occur automatically:

• The GIE is cleared to disable any further interrupt.

• The return address is pushed onto the stack.

• The PC is loaded with 0004h.

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR, to avoid repeated

interrupts. Because the GEI bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

The RETFIEinstruction exists the ISR by popping the

previous address from the stack, restoring the saved

context from the shadow registers and setting the GIE

bit.

For additional information on a specific Interrupt’s oper-

ation, refer to its Peripheral chapter.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 93

MCP19110/11

FIGURE 15-1:

INTERRUPT LOGIC

UVIF

UVIE

OVIF

OVIE

OCIF

OCIE

VINIF

VINIE

T0IF

T0IE

Wake-up (If in Sleep mode)

Interrupt to CPU

INTF

INTE

ADIF

ADIE

IOCF

IOCE

BCLIF

BCLIE

PEIF

PEIE

SSPIF

SSPIE

GIE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

FIGURE 15-2:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN

(3)

CLKOUT

(4)

INT pin

(1)

(5)

(2)

Interrupt Latency

INTF flag

(INTCON reg.)

GIE bit

(INTCON reg.)

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

PC + 1

Instruction

Fetched

Inst (PC + 1)

Inst (0004h)

Inst (PC)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 T . Synchronous latency = 3 T , where T = instruction cycle time.

CY

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 5.0 “Digital Electrical Characteristics”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

DS20002331D-page 94

 2013-2016 Microchip Technology Inc.

MCP19110/11

15.3 Interrupt Control Registers

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

15.3.1

INTCON REGISTER

The INTCON register is a readable and writable regis-

ter, that contains the various enable and flag bits for the

TMR0 register overflow, interrupt-on-change and exter-

nal INT pin interrupts.

REGISTER 15-1: INTCON – INTERRUPT CONTROL REGISTER

R/W-0

GIE

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

IOCE

R/W-0

T0IF

R/W-0

INTF

R/W-x

IOCF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

GIE: Global Interrupt Enable bit

1= Enables all unmasked interrupts

0= Disables all interrupts

PEIE: Peripheral Interrupt Enable bit

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

T0IE: TMR0 Overflow Interrupt Enable bit

1= Enables the TMR0 interrupt

0= Disables the TMR0 interrupt

INTE: INT External Interrupt Enable bit

1= Enables the INT external interrupt

0= Disables the INT external interrupt

IOCE: Interrupt-on-Change Enable bit⁽¹⁾

1 = Enables the interrupt-on-change

0 = Disables the interrupt-on-change

T0IF: TMR0 Overflow Interrupt Flag bit⁽²⁾

bit 2

bit 1

bit 0

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INTF: External Interrupt Flag bit

1= The external interrupt occurred (must be cleared in software)

0= The external interrupt did not occur

IOCF: Interrupt-on-Change Interrupt Flag bit

1= When at least one of the interrupt-on-change pins changed state

0= None of the interrupt-on-change pins have changed state

Note 1: IOC register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clear-

ing T0IF bit.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 95

MCP19110/11

15.3.1.1

PIE1 Register

The PIE1 register contains the Peripheral Interrupt

Enable bits, as shown in Register 15-2.

Note 1: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 15-2: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0

—

R/W-0

ADIE

R/W-0

BCLIE

R/W-0

SSPIE

U-0

—

U-0

—

R/W-0

TMR2IE

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

UNIMPLEMENTED: Read as '0'

ADIE: ADC Interrupt Enable bit

bit 6-0

1= Enables the ADC interrupt

0= Disables the ADC interrupt

bit 6-0

BCLIE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt

0 = Disables the MSSP Bus Collision Interrupt

SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrupt

bit 6-0

UNIMPLEMENTED: Read as 0

TMR2IE: Timer2 Interrupt Enable

1= Enables the Timer2 interrupt

0= Disables the Timer2 interrupt

bit 6-0

TMR1IE: Timer1 Interrupt Enable

1= Enables the Timer1 interrupt

0= Disables the Timer1 interrupt

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15.3.1.2

PIE2 Register

The PIE2 register contains the Peripheral Interrupt

Enable bits, as shown in Register 15-3.

Note 1: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 15-3: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2

U-0

—

R/W-0

OCIE

R/W-0

OVIE

U-0

—

U-0

—

R/W-0

VINIE

U-0

—

UVIE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

UVIE: Output Undervoltage Interrupt Enable bit

1= Enables the UV interrupt

0= Disables the UV interrupt

bit 6

bit 5

UNIMPLEMENTED: Read as '0'

OCIE: Output Overcurrent Interrupt Enable bit

1= Enables the OC interrupt

0= Disables the OC interrupt

bit 4

OVIE: Output Overvoltage Interrupt Enable bit

1= Enables the OV interrupt

0= Disables the OV interrupt

bit 3-2

bit 1

UNIMPLEMENTED: Read as '0'

VINIE: V_INUVLO Interrupt Enable

1= Enables the V_INUVLO interrupt

0= Disables the V_INUVLO interrupt

bit 0

UNIMPLEMENTED: Read as '0'

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15.3.1.3

PIR1 Register

The PIR1 register contains the Peripheral Interrupt

Flag bits, as shown in Register 15-4.

Note 1: Interrupt flag bits are set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit

or the Global Enable bit, GIE of the

INTCON register. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

REGISTER 15-4: PIR1 – PERIPHERAL INTERRUPT FLAG REGISTER 1

U-0

—

R/W-0

ADIF

R/W-0

BCLIF

R/W-0

SSPIF

U-0

—

U-0

—

R/W-0

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

UNIMPLEMENTED: Read as '0'

ADIF: ADC Interrupt Flag bit

1= ADC conversion complete

0= ADC conversion has not completed or has not been started

BCLIF: MSSP Bus Collision Interrupt Flag bit

1= Interrupt is pending

bit 5

bit 4

0= Interrupt is not pending

SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 3-2

bit 1

UNIMPLEMENTED: Read as '0'

TMR2IF: Timer2 to PR2 Match Interrupt Flag

1= Timer2 to PR2 match occurred (must be cleared in software)

0= Timer2 to PR2 match did not occur

TMR1IF: Timer1 Interrupt Flag

bit 0

1= Timer1 rolled over (must be cleared in software)

0= Timer1 has not rolled over

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15.3.1.4

PIR2 Register

The PIR2 register contains the Peripheral Interrupt

Flag bits, as shown in Register 15-5.

Note 1: Interrupt flag bits are set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit

or the Global Enable bit, GIE of the

INTCON register. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

REGISTER 15-5: PIR2 – PERIPHERAL INTERRUPT FLAG REGISTER 2

R/W-0

UVIF

U-0

—

R/W-0

OCIF

R/W-0

OVIF

U-0

—

U-0

—

R/W-0

VINIF

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

UVIF: Output Undervoltage Error Interrupt Flag bit

1= Output undervoltage error has occurred

0= Output undervoltage error has not occurred

bit 6

bit 5

UNIMPLEMENTED: Read as '0'

OCIF: Output Overcurrent Error Interrupt Flag bit

1= Output overcurrent error has occurred

0= Output overcurrent error has not occurred

bit 4

OVIF: Output Overvoltage Error Interrupt Flag bit

1= Output overvoltage error has occurred

0= Output overvoltage error has not occurred

bit 3-2

bit 1

UNIMPLEMENTED: Read as '0'

VINIF: V_INStatus bit

1= V_INis below acceptable level

0= V_INis at acceptable level

UNIMPLEMENTED: Read as '0'

bit 0

TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

RAPU

—

PEIE

INTEDG

ADIE

—

T0IE

T0CE

BCLIE

OCIE

BCLIF

OCIF

INTE

T0SE

SSPIE

OVIE

SSPIF

OVIF

IOCE

PSA

—

T0IF

PS2

—

INTF

PS1

IOCF

PS0

95

77

96

97

98

99

OPTION_REG

PIE1

TMR2IE TMR1IE

VINIE

TMR2IF TMR1IF

VINIF

PIE2

UVIE

—

PIR1

ADIF

—

PIR2

UVIF

—

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.

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15.4 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W and STATUS

registers). This must be implemented in software.

Temporary

holding

registers

W_TEMP

and

STATUS_TEMP should be placed in the last 16 bytes

of GPR (see Figure 11-2). These 16 locations are

common to all banks and do not require banking. This

makes context save and restore operations simpler.

The code shown in Example 15-1 can be used to:

• Store the W register

• Store the STATUS register

• Execute the ISR code

• Restore the Status (and Bank Select Bit register)

• Restore the W register

Note:

The MCP19110/11 device does not

require saving the PCLATH. However, if

computed GOTOs are used in both the ISR

and the main code, the PCLATH must be

saved and restored in the ISR.

EXAMPLE 15-1:

SAVING STATUS AND W REGISTERS IN RAM

MOVWF

SWAPF

W_TEMP

STATUS,W

;Copy W to TEMP register

;Swap status to be saved into W

;Swaps are used because they do not affect the status bits

;Save status to bank zero STATUS_TEMP register

MOVWF

:

STATUS_TEMP

:(ISR)

:

;Insert user code here

SWAPF

STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into STATUS register

;Swap W_TEMP

MOVWF

SWAPF

STATUS

W_TEMP,F

W_TEMP,W

;Swap W_TEMP into W

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16.1 Wake-up from Sleep

16.0 POWER-DOWN MODE (SLEEP)

The device can wake-up from Sleep through one of the

following events:

The Power-Down mode is entered by executing a

SLEEPinstruction.

1. External Reset input on MCLR pin, if enabled

2. POR Reset

Upon entering Sleep mode, the following conditions

exist:

3. Watchdog Timer, if enabled

4. Any external interrupt

1. WDT will be cleared but keeps running, if

enabled for operation during Sleep.

2. PD bit of the STATUS register is cleared.

3. TO bit of the STATUS register is set.

4. CPU clock is not disabled.

5. Interrupts by peripherals capable of running

during Sleep (see individual peripheral for more

information)

The first two events will cause a device Reset. The last

three events are considered a continuation of program

execution. To determine whether a device Reset or

Wake-up event occurred, refer to Section 14.7

“Determining the Cause of a Reset”.

5. Timer1 oscillator is unaffected, and peripherals

that operate from it may continue operation in

Sleep.

6. ADC is unaffected.

7. I/O ports maintain the status they had before

SLEEP was executed (driving high, low or

high-impedance).

The following peripheral interrupts can wake the device

from Sleep:

8. Resets other than WDT are not affected by

Sleep mode.

1. Timer1 interrupt. Timer1 must be operating as

an asynchronous counter

9. Analog circuitry is unaffected by execution of

2. A/D conversion

SLEEPinstruction.

3. Interrupt-on-change

4. External Interrupt from INT pin

Refer to individual chapters for more details on

peripheral operation during Sleep.

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEPinstruction, the device will then call the Interrupt

Service Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have an NOPafter the SLEEPinstruction.

To minimize current consumption, the following

conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using Timer1 oscillator

I/O pins that are high-impedance inputs should be

pulled to V_DDor GND externally to avoid switching

currents caused by floating inputs.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

The SLEEP instruction does not affect the analog

circuitry. The enable state of the analog circuitry does

not change with the execution of the SLEEPinstruction.

Examples of internal circuitry that might be sourcing

current include modules, such as the DAC. See

Section 22.0 “Analog-to-Digital Converter (ADC)

Module” for more information on this module.

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• If the interrupt occurs during or after the

execution of a SLEEPinstruction:

16.1.1

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

- SLEEPinstruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared

• If the interrupt occurs before the execution of a

SLEEPinstruction:

- SLEEPinstruction will execute as an NOP

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as an NOP.

- PD bit of the STATUS register will not be

cleared

FIGURE 16-1:

OSC

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

T_OST

(1)

Interrupt flag

Interrupt Latency

GIE bit

(INTCON reg.)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Dummy Cycle Dummy Cycle

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Executed

Note 1: GIE = 1assumed. In this case, after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution

will continue in-line.

TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

INTCON

IOCA

IOCB

PIE1

GIE

IOCA7

IOCB7

—

PEIE

IOCA6

IOCB6

ADIE

—

T0IE

IOCA5

IOCB5

BCLIE

OCIE

BCLIF

OCIF

INTE

IOCA4

IOCB4

SSPIE

OVIE

SSPIF

OVIF

IOCE

IOCA3

—

T0IF

IOCA2

IOCB2

—

INTF

IOCA1

IOCB1

IOCF

IOCA0

IOCB0

95

122

96

—

TMR2IE TMR1IE

VINIE

TMR2IF TMR1IF

PIE2

UVIE

—

97

PIR1

ADIF

—

98

PIR2

UVIF

IRP

—

VINIF

DC

—

C

99

STATUS

RP1

RP0

TO

PD

Z

71

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.

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17.2 WDT Period

17.0 WATCHDOG TIMER (WDT)

The WDT has a nominal time-out period of 18 ms (with

no prescaler). The time-out periods vary with

temperature, V_DDand process variations from part to

part (see Table 5-4). If longer time-out periods are

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT under software control by

writing to the OPTION register. Thus, time-out periods

up to 2.3 seconds can be realized.

The Watchdog Timer is a free-running timer. The WDT

is enabled by setting the WDTE bit of the Configuration

Word (default setting).

During normal operation, a WDT time-out generates a

device Reset. If the device is in Sleep mode, a WDT

time-out causes the device to wake-up and continue

with normal operation.

The WDT can be permanently disabled by clearing the

WDTE bit of the Configuration word. See Section 12.1

“Configuration Word” for more information.

The CLRWDT and SLEEP instructions clear the WDT

and the prescaler, if assigned to the WDT, and prevent

it from timing out and generating a device Reset.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time-out.

17.1 Watchdog Timer (WDT) Operation

During normal operation, a WDT time-out generates a

device RESET. If the device is in SLEEP mode, a WDT

time-out causes the device to wake-up and continue

with normal operation; this is known as a WDT wake-

up. The WDT can be permanently disabled by clearing

the WDTE configuration bit.

17.3 WDT Programming

Considerations

Under worst-case conditions (i.e., V_DD= Minimum,

Temperature = Maximum, Maximum WDT prescaler), it

may take several seconds before a WDT time-out

occurs.

The postscaler assignment is fully under software

control and can be changed during program execution.

FIGURE 17-1:

WATCHDOG TIMER WITH SHARED PRESCALER BLOCK DIAGRAM

F_OSC/4

Data Bus

0

1

8

1

Sync

TMR0

2 T_CY

T0CKI

0

1

Set Flag bit T0IF

on Overflow

PSA

T0CS

T0SE

8-bit

Prescaler

PSA

8

1

0

PS<2:0>

WDT

Time-out

Watchdog

Timer

PSA

WDTE

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG register.

2: WDTE bit is in the Configuration Word register.

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TABLE 17-1: WDT STATUS

Conditions

WDT

WDTE = 0

CLRWDTCommand

Exit Sleep

Cleared

TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Register on

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OPTION_REG

RAPU

INTEDG

T0CS

T0SE

PSA

PS<2:0>

77

Legend: Shaded cells are not used by the Watchdog Timer.

TABLE 17-3: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH WATCHDOG TIMER

Register

Name

Bits Bit -/7 Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

on Page

CONFIG

13:8

7:0

—

DBGEN

MCLRE

—

WRT1

WDTE

WRT0

—

81

CP

PWRTE

Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by Watchdog Timer.

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18.1 PMADRH and PMADRL Registers

18.0 FLASH PROGRAM MEMORY

CONTROL

The PMADRH and PMADRL registers can address up

to a maximum of 4K words of program memory.

The Flash program memory is readable and writable

during normal operation (full V_INrange). This memory

is not directly mapped in the register file space.

Instead, it is indirectly addressed through the Special

Function Registers (SFR) (see Registers 18-1 to 18-

5). There are six SFRs used to read and write this

memory:

When selecting a program address value, the Most

Significant Byte (MSB) of the address is written to the

PMADRH register and the Least Significant Byte

(LSB) is written to the PMADRL register.

18.2 PMCON1 and PMCON2 Registers

• PMCON1

• PMCON2

• PMDATL

• PMDATH

• PMADRL

• PMADRH

PMCON1 is the control register for the data program

memory accesses.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental premature

termination of a write operation.

When interfacing the program memory block, the

PMDATL and PMDATH registers form a two-byte

word, which holds the 14-bit data for read/write, and

the PMADRL and PMADRH registers form a two-byte

word, which holds the 13-bit address of the FLASH

location being accessed. These devices have 4K

words of program Flash with an address range from

0000h to 0FFFh.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear.

The CALSEL bit allows the user to read locations in

test memory in case there are calibration bits stored in

the calibration word locations that need to be

transferred to SFR trim registers. The CALSEL bit is

only for reads, and if a write operation is attempted

with CALSEL = 1, no write will occur.

The program memory allows single word read and a

four-word write. A four-word write automatically erases

the row of the location and writes the new data (erase

before write).

PMCON2 is not a physical register. Reading PMCON2

will read all '0's. The PMCON2 register is used

exclusively in the flash memory write sequence.

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range

of the device for byte or word operations.

When the device is code protected, the CPU may

continue to read and write the Flash program memory.

Depending on the settings of the Flash Program

Memory Enable (WRT<1:0>) bits, the device may or

may not be able to write certain blocks of the program

memory, however, reads of the program memory are

allowed.

When the Flash Program Memory Code Protection

(CP) bit is enabled, the program memory is code

protected, and the device programmer (ICSP) cannot

access data or program memory.

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18.3 Flash Program Memory

Control Registers

REGISTER 18-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-0

bit 0

PMDATL<7:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

PMDATL<7:0>: 8 Least Significant Data bits Read from Program Memory

REGISTER 18-2: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0

bit 7

R/W-0

bit 0

PMADRL<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

PMADRL<7:0>: 8 Least Significant Address bits for Program Memory Read/Write Operation

REGISTER 18-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0

—

U-0

—

R/W-0

bit 0

PMDATH<5:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

PMDATH<5:0>: 6 Most Significant Data bits Read from Program Memory

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REGISTER 18-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

bit 0

PMADRH<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

PMADRH<3:0>: Specifies the 4 Most Significant Address bits or High bits for Program Memory Reads.

REGISTER 18-5: PMCON1: PROGRAM MEMORY CONTROL REGISTER 1

U-1

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

WREN

R/S-0

WR

R/S-0

RD

CALSEL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

S = Bit can only be set

bit 7

bit 6

Unimplemented: Read as '1'

CALSEL: Program Memory Calibration Space Select bit

1= Select test memory area for reads only (for loading calibration trim registers)

0= Select user area for reads

bit 5-3

bit 2

Unimplemented: Read as '0'

WREN: Program Memory Write Enable bit

1= Allows write cycles

0= Inhibits write to the Flash Program Memory

bit 1

bit 0

WR: Write Control bit

1= Initiates a write cycle to program memory. (The bit is cleared by hardware when write is complete.

The WR bit can only be set (not cleared) in software.)

0= Write cycle to the Flash memory is complete

RD: Read Control bit

1= Initiates a program memory read. (The read takes one cycle. The RD is cleared in hardware; the

RD bit can only be set (not cleared) in software).

0= Does not initiate a Flash memory read

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18.3.1

READING THE FLASH PROGRAM

MEMORY

To read a program memory location, the user must

write two bytes of the address to the PMADRL and

PMADRH registers, and then set control bit RD

(PMCON1<0>). Once the read control bit is set, the

program memory Flash controller will use the second

instruction cycle after to read the data. This causes the

second instruction immediately following the “BSF

PMCON1,RD” instruction to be ignored. The data is

available, in the very next cycle, in the PMDATL and

PMDATH registers; it can be read as two bytes in the

following instructions. PMDATL and PMDATH regis-

ters will hold this value until another read or until it is

written to by the user (during a write operation).

EXAMPLE 18-1:

FLASH PROGRAM READ

BANKSELPM_ADR; Change STATUS bits RP1:0 to select bank with PMADR

MOVLWMS_PROG_PM_ADDR;

MOVWFPMADRH; MS Byte of Program Address to read

MOVLWLS_PROG_PM_ADDR;

MOVWFPMADRL; LS Byte of Program Address to read

BANKSELPMCON1; Bank to containing PMCON1

BSF PMCON1, RD; EE Read

NOP

; First instruction after BSF PMCON1,RD executes normally

; Any instructions here are ignored as program

; memory is read in second cycle after BSF PMCON1,RD

;

BANKSELPMDATL; Bank to containing PMADRL

MOVFPMDATL, W; W = LS Byte of Program PMDATL

MOVFPMDATH, W; W = MS Byte of Program PMDATL

FIGURE 18-1:

FLASH PROGRAM MEMORY READ CYCLE EXECUTION – NORMAL MODE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Flash ADDR

Flash DATA

PMADRH,PMADRL

PC

PC + 1

PPCC+33

PC + 4

PC + 5

INSTR (PC) INSTR (PC + 1)

PMDATH,PMDATL

INSTR (PC + 3) INSTR (PC + 4)

BSF PMCON1,RD

Executed here

INSTR (PC - 1)

Executed here

INSTR (PC + 1)

Executed here

NOP

Executed here

INSTR (PC + 3)

Executed here

INSTR (PC + 4)

Executed here

RD bit

PMDATH

PMDATL

Register

EERHLT

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The user must follow the same specific sequence to

initiate the write for each word in the program block,

writing each program word in sequence (000, 001,

010, 011). When the write is performed on the last

word (PMADRL<1:0> = 11), a block of sixteen words is

automatically erased and the content of the four-word

buffer registers are written into the program memory.

18.3.2

WRITING TO THE FLASH

PROGRAM MEMORY

A word of the Flash program memory may only be

written to if the word is in an unprotected segment of

memory, as defined in Section 12.1 “Configuration

Word” (bits WRT1:WRT0).

After the “BSF PMCON1,WR” instruction, the processor

requires two cycles to set up the erase/write operation.

The user must place two NOPinstructions after the WR

bit is set. Since data is being written to buffer registers,

the writing of the first three words of the block appears

to occur immediately. The processor will halt internal

operations for the typical 4 ms, only during the cycle in

which the erase takes place (i.e., the last word of the

sixteen-word block erase). This is not Sleep mode, as

the clocks and peripherals will continue to run. After

the four-word write cycle, the processor will resume

operation with the third instruction after the PMCON1

write instruction. The above sequence must be

repeated for the higher 12 words.

Note: The write protect bits are used to protect the

users’ program from modification by the

user’s code. They have no effect when

programming is performed by ICSP. The

code-protect bits, when programmed for

code protection, will prevent the program

memory from being written via the ICSP

interface.

Flash program memory must be written in four-word

blocks. See Figures 18-2 and 18-3 for more details. A

block consists of four words with sequential addresses,

with a lower boundary defined by an address, where

PMADRL<1:0> = 00. All block writes to program

memory are done as 16-word erase by four-word write

operations. The write operation is edge-aligned and

cannot occur across boundaries.

Note: An erase is only initiated for the write of four

words, just after

a row boundary; or

PMCON1<WR> set with PMADRL<3:0> =

xxxx0011.

To write program data, the WREN bit must be set and

the data must first be loaded into the buffer registers

(see Figure 18-2). This is accomplished by first writing

the destination address to PMADRL and PMADRH,

and then writing the data to PMDATL and PMDATH.

After the address and data have been set, then the

following sequence of events must be executed:

Refer to Figure 18-2 for a block diagram of the buffer

registers and the control signals for test mode.

18.3.3 PROTECTION AGAINST SPURIOUS

WRITE

1. Write 55h, then AAh, to PMCON2 (Flash

programming sequence).

There are conditions when the device should not write

to the program memory. To protect against spurious

writes, various mechanisms have been built in. On

power-up, WREN is cleared. Also, the Power-up Timer

(72 ms duration) prevents program memory writes.

2. Set the WR control bit of the PMCON1 register.

All four buffer register locations should be written to

with correct data. If less than four words are being writ-

ten to in the block of four words, then a read from the

program memory location(s) not being written to must

be performed. This takes the data from the program

memory location(s) not being written and loads it into

the PMDATL and PMDATH registers. Then the

sequence of events to transfer data to the buffer regis-

ters must be executed.

The write initiate sequence, and the WREN bit, help

prevent an accidental write during a power glitch or

software malfunction.

18.3.4 OPERATION DURING CODE PROTECT

When the device is code protected, the CPU is able to

read and write unscrambled data to the program

memory. The test mode access is disabled.

To transfer data from the buffer registers to the program

memory, the PMADRL and PMADRH must point to the

18.3.5 OPERATION DURING WRITE PROTECT

last

location

in

the

four-word

block

(PMADRL<1:0> = 11). Then the following sequence of

events must be executed:

When the program memory is write protected, the

CPU can read and execute from the program memory.

The portions of program memory that are write pro-

tected can not be modified by the CPU using the

PMCON registers. The write protection has no effect in

ICSP mode.

1. Write 55h, then AAh, to PMCON2 (Flash

programming sequence).

2. Set control bit WR of the PMCON1 register to

begin the write operation.

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DS20002331D-page 109

MCP19110/11

FIGURE 18-2:

BLOCK WRITES TO 4K FLASH PROGRAM MEMORY

If at new row

7

5

0

0 7

sixteen words of

Flash are erased,

then four buffers

are transferred to

Flash automatically

after this word is

written

PMDATH

6

PMDATL

8

First word of block

to be written

14

PMADRL<1:0> = 00

Buffer Register

PMADRL<1:0> = 01

PMADRL<1:0> = 10

PMADRL<1:0> = 11

Buffer Register

Program Memory

FIGURE 18-3:

FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Flash

PMADRH,PMADRL

PMDATH,PMDATL

PC + 1

PC + 2

PC + 3

PC + 4

ADDR

INSTR

(PC + 1)

ignored

read

INSTR

(PC)

Flash

DATA

INSTR (PC+3)

INSTR (PC+2)

(INSTR (PC + 2)

NOP

Executed here

Processor halted

EE Write Time

BSF PMCON1,WR

Executed here

INSTR (PC + 1)

Executed here

INSTR (PC + 3)

Executed here

NOP

Executed here

Flash

Memory

Location

WR bit

PMWHLT

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MCP19110/11

19.0 I/O PORTS

In general, when a peripheral is enabled, that pin may

not be used as a general purpose I/O pin.

Each port has two registers for its operation. These

registers are:

• TRISGPx registers (data direction register)

• PORTGPx registers (reads the levels on the pins

of the device)

Some ports may have one or more of the following

additional registers. These registers are:

• ANSELx (analog select)

• WPUx (weak pull-up)

Ports with analog functions also have an ANSELx

register, which can disable the digital input and save

power. A simplified model of a generic I/O port, without

the interfaces to other peripherals, is shown in

Figure 19-1.

FIGURE 19-1:

GENERIC I/O PORTGPX

OPERATION

TRISx

Read LATx

Q

D

Write LATx

Write PORTx

V_DD

CK

Data Register

Data Bus

I/O pin

Read PORTx

To peripherals

V_SS

ANSELx

EXAMPLE 19-1:

INITIALIZING PORTA

; This code example illustrates

; initializing the PORTGPA register. The

; other ports are initialized in the same

; manner.

BANKSELPORTGPA;

CLRF

PORTGPA;Init PORTA

BANKSELANSELA;

CLRF

ANSELA;digital I/O

BANKSELTRISGPA;

MOVLW

MOVWF

B'00011111';Set GPA<4:0> as

;inputs

TRISGPA;and set GPA<7:6> as

;outputs

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This bit has no effect on the values of any TRIS

register. PORT and TRIS overrides will be routed to the

correct pin. The unselected pin will be unaffected.

19.1 Alternate Pin Function

The Alternate Pin Function Control (APFCON) register

is used to steer specific peripheral input and output

functions between different pins. The APFCON register

is shown in Register 19-1. For the MCP19111 device,

the following function can be moved between different

pins:

• Frequency Synchronization Clock Input/Output

REGISTER 19-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CLKSEL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

bit 0

Unimplemented: Read as ‘0’

CLKSEL: Pin Selection bit

1= Multi-phase or multiple output clock function is on GPB5

0= Multi-phase or multiple output clock function is on GPA1

19.2.1

INTERRUPT-ON-CHANGE

19.2 PORTGPA and TRISGPA Registers

Each PORTGPA pin is individually configurable as an

interrupt-on-change pin. Control bits IOCA<7:0>

enable or disable the interrupt function for each pin.

The interrupt-on-change feature is disabled on a

Power-on Reset. Reference Section 20.0 “Interrupt-

On-Change” for more information.

PORTGPA is an 8-bit wide, bidirectional port consisting

of five CMOS I/O, two open-drain I/O, and one open-

drain input-only pin. The corresponding data direction

register is TRISGPA (Register 19-3). Setting

a

TRISGPA bit (= 1) will make the corresponding

PORTGPA pin an input (i.e., disable the output driver).

Clearing

a

TRISGPA bit (= 0) will make the

19.2.2

WEAK PULL-UPS

corresponding PORTGPA pin an output (i.e., enables

output driver). The exception is GPA5, which is input

only and its TRISGPA bit will always read as ‘1’.

Example 19-1 shows how to initialize an I/O port.

PORTGPA <3:0> and PORTGPA5 have an internal weak

pull-up. PORTGPA<7:6> are special ports for the SSP

module and do not have weak pull-ups. Individual control

bits can enable or disable the internal weak pull-ups (see

Register 19-4). The weak pull-up is automatically turned

off when the port pin is configured as an output, an

alternative function or on a Power-on Reset setting the

RAPU bit of the OPTION register. The weak pull-up on

GPA5 is enabled when configured as MCLR pin by setting

bit 5 of the Configuration word, and disabled when GPA5

is an I/O. There is no software control of the MCLR

pull-up.

Reading the PORTGPA register (Register 19-2) reads

the status of the pins, whereas writing to it will write to

the PORT latch. All write operations are read-modify-

write operations.

The TRISGPA register (Register 19-3) controls the

PORTGPA pin output drivers, even when they are

being used as analog inputs. The user must ensure the

bits in the TRISGPA register are maintained set when

using them as analog inputs. I/O pins configured as

analog input always read ‘0’. If the pin is configured for

a digital output (either port or alternate function), the

TRISGPA bit must be cleared in order for the pin to

drive the signal, and a read will reflect the state of the

pin.

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Analog input functions, such as ADC, are not shown in

the priority lists. These inputs are active when the I/O

pin is set for Analog mode using the ANSELA registers.

Digital output functions may control the pin when it is in

Analog mode with the priority shown in Table 19-1.

19.2.3

ANSELA REGISTER

The ANSELA register (Register 19-5) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allows

analog functions on the pin to operate correctly.

TABLE 19-1: PORTGPA OUTPUT PRIORITY

The state of the ANSELA bits has no effect on the

digital output functions. A pin with TRISGPA clear and

ANSELA set will still operate as a digital output, but the

Input mode will be analog. This can cause unexpected

Pin Name

Function Priority⁽¹⁾

GPA0

AN0

ANALOG_TEST

behavior

when

executing

read-modify-write

instructions on the affected port.

GPA1

GPA2

GPA1

AN1

CLKPIN

Note:

The ANSELA bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSELA bits

must be initialized to ‘0’ by user software.

GPA2

AN2

T0CKI

INT

GPA3

AN3

19.2.4

PORTGPA FUNCTIONS AND

OUTPUT PRIORITIES

GPA4

GPA5

GPA6

GPA4 (open-drain input/output)

GPA5 (open-drain data input only)

Each PORTGPA pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are shown in Table 19-1. For additional

information, refer to the appropriate section in this data

sheet.

GPA6

ICSPDAT (MCP19110 Only)

GPA7

GPA7 (open-drain output)

SCL

PORTGPA pins GPA7 and GPA4 are true open-drain

pins with no connection back to V_DD

.

ICSPCLK (MCP19110 Only)

Note 1: Priority listed from highest to lowest.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

REGISTER 19-2: PORTGPA: PORTGPA REGISTER

R/W-x

GPA7

R/W-x

GPA6

R-x

R/W-x

GPA3

R/W-x

GPA2

R/W-x

GPA1

R/W-x

GPA0

GPA5

GPA4

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

GPA7: General Purpose Open-Drain I/O pin.

GPA6: General Purpose I/O pin.

1= Port pin is > V_IH

0= Port pin is < V_IL

bit 5

GPA5/MCLR: General Purpose Open-Drain I/O pin.

GPA4: General Purpose Open-Drain I/O pin.

bit 4

bit 3-0

GPA<3:0>: General Purpose I/O pin.

1= Port pin is > V_IH

0= Port pin is < V_IL

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REGISTER 19-3: TRISGPA: PORTGPA TRI-STATE REGISTER

R/W-1

R-1

R/W-1

TRISA7

TRISA6

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

TRISA<7:6>: PORTGPA Tri-State Control bit

1= PORTGPA pin configured as an input (tri-stated)

0= PORTGPA pin configured as an output

bit 5

TRISA5: GPA5 Port Tri-State Control bit

This bit is always ‘1’ as GPA5 is an input only

bit 4-0

TRISA<4:0>: PORTGPA Tri-State Control bit

1= PORTGPA pin configured as an input (tri-stated)

0= PORTGPA pin configured as an output

REGISTER 19-4: WPUGPA: WEAK PULL-UP PORTGPA REGISTER

U-0

—

U-0

—

R/W-1

U-0

—

R/W-1

WPUA5

WPUA3

WPUA2

WPUA1

WPUA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5

Unimplemented: Read as ‘0’

WPUA5: Weak Pull-up Register bit

1= Pull-up enabled.

0= Pull-up disabled.

bit 4

Unimplemented: Read as ‘0’

bit 3-0

WPUA<3:0>: Weak Pull-up Register bit

1= Pull-up enabled.

0= Pull-up disabled.

Note 1: The weak pull-up device is enabled only when the global RAPU bit is enabled, the pin is in input mode

(TRISGPA = 1), and the individual WPUA bit is enabled (WPUA = 1), and the pin is not configured as an

analog input.

2: GPA5 weak pull-up is also enabled when the pin is configured as MCLR in Configuration word.

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REGISTER 19-5: ANSELA: ANALOG SELECT PORTGPA REGISTER

U-0

—

U-0

—

U-0

—

R/W-1

—

R/W-1

ANSA3

ANSA2

ANSA1

ANSA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

ANSA<3:0>: Analog Select PORTGPA Register bit

1= Analog input. Pin is assigned as analog input.⁽¹⁾

0= Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and

interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTGPA

Register

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

ANSELA

—

ANSA3

—

ANSA2

—

ANSA1

—

ANSA0

115

112

APFCON

CLKSEL

OPTION_REG

PORTGPA

TRISGPA

RAPU INTEDG

GPA7 GPA6

TRISA7 TRISA6

T0CS

GPA5

T0SE

GPA4

PSA

PS2

PS1

PS0

77

GPA3

GPA2

GPA1

GPA0

113

114

TRISA5 TRISA4 TRISA3

WPUA5 WPUA3

TRISA2 TRISA1 TRISA0

WPUA2 WPUA1 WPUA0

WPUGPA

—

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTGPA.

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Input mode will be analog. This can cause unexpected

behavior when executing read-modify-write instructions

on the affected port.

19.3 PORTGPB and TRISGPB

Registers

PORTGPB is an 8-bit wide, bidirectional port consisting

of seven general purpose I/O ports. The corresponding

data direction register is TRISGPB (Register 19-7).

Setting a TRISGPB bit (= 1) will make the corresponding

PORTGPB pin an input (i.e., disable the output driver).

Note:

The ANSELB bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSELB bits

must be initialized to ‘0’ by the user’s

software.

Clearing

a

TRISGPB bit (= 0) will make the

corresponding PORTGPB pin an output (i.e., enable the

output driver). Example 19-1 shows how to initialize an

I/O port.

19.3.4

PORTGPB FUNCTIONS AND

OUTPUT PRIORITIES

Some pins for PORTGPB are multiplexed with an

alternate function for the peripheral, or a clock function.

In general, when a peripheral or clock function is

enabled, that pin may not be used as a general purpose

I/O pin.

Each PORTGPB pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are shown in Table 19-3. For additional

information, refer to the appropriate section in this data

sheet.

Reading the PORTGPB register (Register 19-6) reads

the status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations.

PORTGPB pin GPB0 is a true open-drain pin with no

connection back to V_DD

.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

The TRISGPB register (Register 19-7) controls the

PORTGPB pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISGPB register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’. If the pin is configured for a digital

output (either port or alternate function), the TRISGPB bit

must be cleared in order for the pin to drive the signal and

a read will reflect the state of the pin.

Analog input functions, such as ADC, and some digital

input functions are not included in the list below. These

inputs are active when the I/O pin is set for Analog

mode using the ANSELB registers. Digital output

functions may control the pin when it is in Analog mode,

with the priority shown in Table 19-3.

TABLE 19-3: PORTGPB OUTPUT PRIORITY

Function Priority⁽¹⁾

19.3.1

INTERRUPT-ON-CHANGE

Pin Name

Each PORTGPB pin is individually configurable as an

interrupt-on-change pin. Control bits IOCB<7:4> and

IOCB<2:0> enable or disable the interrupt function for

each pin. The interrupt-on-change feature is disabled

GPB0

GPB0 (open-drain input/output)

SDA

GPB1

AN4

EAPIN

on

a Power-on Reset. Reference Section 20.0

“Interrupt-On-Change” for more information.

GPB2

GPB4

GPB2

AN5

19.3.2

WEAK PULL-UPS

Each of the PORTGPB pins has an individually

configurable internal weak pull-up. Control bits

WPUB<7:4> and WPUB<2:1> enable or disable each

pull-up (see Register 19-8). Each weak pull-up is

automatically turned off when the port pin is configured

as an output. All pull-ups are disabled on a Power-on

Reset by the RAPU bit of the OPTION register.

GPB4

AN6

ICSPDAT/ICDDAT (MCP19111 Only)

GPB5

AN7

ICSPCLK/ICDCLK (MCP19111 Only)

ALT_CLKPIN (MCP19111 Only)

GPB6

GPB7

GPB6

GPB7

19.3.3

ANSELB REGISTER

The ANSELB register (Register 19-9) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allows

analog functions on the pin to operate correctly.

Note 1: Priority listed from highest to lowest.

The state of the ANSELB bits has no effect on the digital

output functions. A pin with TRISGPB clear and

ANSELB set will still operate as a digital output, but the

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REGISTER 19-6: PORTGPB: PORTGPB REGISTER

R/W-x

GPB7⁽¹⁾

R/W-x

GPB6⁽¹⁾

R/W-x

GPB5⁽¹⁾

R/W-x

GPB4⁽¹⁾

U-x

—

R/W-x

GPB2

R/W-x

GPB1

R/W-x

GPB0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

GPB<7:4>: General Purpose I/O Pin bit

1= Port pin is > V_IH

0= Port pin is < V_IL

bit 3

Unimplemented: Read as ‘0’

bit 2-0

GPB<2:0>: General Purpose I/O Pin bit

1= Port pin is > V_IH

0= Port pin is < V_IL

Note 1: Not implemented on MCP19110.

REGISTER 19-7: TRISGPB: PORTGPB TRI-STATE REGISTER

R/W-1

TRISB7⁽¹⁾

R/W-1

TRISB6⁽¹⁾

R/W-1

TRISB5⁽¹⁾

R/W-1

TRISB4⁽¹⁾

U-1

—

R/W-1

TRISB2

TRISB1

TRISB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-4

TRISB<7:4>: PORTGPB Tri-State Control bit

1= PORTGPB pin configured as an input (tri-stated)

0= PORTGPB pin configured as an output

bit 3

Unimplemented: Read as ‘1’

bit 2-0

TRISB<2:0>: PORTGPB Tri-State Control bit

1= PORTGPB pin configured as an input (tri-stated)

0= PORTGPB pin configured as an output

Note 1: Not implemented on MCP19110.

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REGISTER 19-8: WPUGPB: WEAK PULL-UP PORTGPB REGISTER

R/W-1

WPUB7⁽²⁾

R/W-1

WPUB6⁽²⁾

R/W-1

WPUB5⁽²⁾

R/W-1

WPUB4⁽²⁾

U-0

—

R/W-1

U-0

—

WPUB2

WPUB1

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-4

WPUB<7:4>: Weak Pull-up Register bit

1= Pull-up enabled

0= Pull-up disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-1

WPUB<2:1>: Weak Pull-up Register bit

1= Pull-up enabled

0= Pull-up disabled

bit 0

Unimplemented: Read as ‘0’

Note 1: The weak pull-up device is enabled only when the global RAPU bit is enabled, the pin is in Input mode

(TRISGPA = 1), the individual WPUB bit is enabled (WPUB = 1), and the pin is not configured as an

analog input.

2: Not implemented on MCP19110.

REGISTER 19-9: ANSELB: ANALOG SELECT PORTGPB REGISTER

U-0

—

U-0

—

R/W-1

ANSB5⁽²⁾

R/W-1

ANSB4⁽²⁾

U-0

—

R/W-1

U-0

—

ANSB2

ANSB1

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

ANSB<5:4>: Analog Select PORTGPB Register bit

1= Analog input. Pin is assigned as analog input⁽¹⁾

.

0= Digital I/O. Pin is assigned to port or special function.

bit 3

Unimplemented: Read as ‘0’

bit 2-1

ANSB<2:1>: Analog Select PORTGPB Register bit

1= Analog input. Pin is assigned as analog input⁽¹⁾

.

0= Digital I/O. Pin is assigned to port or special function.

bit 0

Unimplemented: Read as ‘0’

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and

interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

2: Not implemented on MCP19110.

DS20002331D-page 118

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 19-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTGPB

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

APFCON

—

ANSB5

—

ANSB4

—

ANSB2

—

ANSB1

—

118

112

CLKSEL

OPTION_REG RAPU

INTEDG

GPB6

T0CS

GPB5

T0SE

GPB4

PSA

—

PS2

PS1

PS0

77

PORTGPB

TRISGPB

WPUGPB

GPB7

GPB2

GPB1

GPB0

117

118

TRISB7 TRISB6 TRISB5 TRISB4

WPUB7 WPUB6 WPUB5 WPUB4

—

TRISB2 TRISB1 TRISB0

WPUB2 WPUB1

—

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTGPB.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 119

MCP19110/11

NOTES:

DS20002331D-page 120

 2013-2016 Microchip Technology Inc.

MCP19110/11

20.3 Clearing Interrupt Flags

20.0 INTERRUPT-ON-CHANGE

The user, in the Interrupt Service Routine, clears the

interrupt by:

Each PORTGPA and PORTGPB pin is individually

configurable as an interrupt-on-change pin. Control bits

IOCA and IOCB enable or disable the interrupt function

for each pin. Refer to Register 20-1 and Register 20-2.

The interrupt-on-change is disabled on a Power-on

Reset.

a) Any read of PORTGPA or PORTGPB AND

Clear flag bit IOCF. This will end the mismatch

condition;

OR

The interrupt-on-change on GPA5 is disabled when

configured as MCLR pin in the Configuration Word.

b) Any write of PORTGPA or PORTGPB AND

Clear flag bit IOCF will end the mismatch

condition;

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTGPA or PORTGPB. The mismatched outputs of

the last read of all the PORTGPA and PORTGPB pins

are OR’ed together to set the Interrupt-on-Change

Interrupt Flag bit (IOCF) in the INTCON register

(Register 15-1).

A mismatch condition will continue to set flag bit IOCF.

Reading PORTGPA or PORTGPB will end the

mismatch condition and allow flag bit IOCF to be

cleared. The latch holding the last read value is not

affected by a MCLR Reset. After this Reset, the IOCF

flag will continue to be set if a mismatch is present.

20.1 Enabling the Module

Note:

If a change on the I/O pin should occur

when any PORTGPA or PORTGPB

operation is being executed, then the

IOCF interrupt flag may not get set.

To allow individual port pins to generate an interrupt, the

IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will

still occur, but an interrupt will not be generated.

20.4 Operation in Sleep

20.2 Individual Pin Configuration

The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCE bit is set.

To enable a pin to detect an interrupt-on-change, the

associated IOCAx or IOCBx bit of the IOCA or IOCB

register is set.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 121

MCP19110/11

20.5 Interrupt-On-Change Registers

REGISTER 20-1: IOCA: INTERRUPT-ON-CHANGE PORTGPA REGISTER

R/W-0

IOCA7

R/W-0

IOCA6

R/W-0

IOCA5

R/W-0

IOCA4

R/W-0

IOCA3

R/W-0

IOCA2

R/W-0

IOCA1

R/W-0

IOCA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

IOCA<7:6>: Interrupt-on-Change PORTGPA Register bits

1= Interrupt-on-change enabled on the pin

0= Interrupt-on-change disabled on the pin

bit 5

IOCA<5>: Interrupt-on-Change PORTGPA Register bits⁽¹⁾

1= Interrupt-on-change enabled on the pin

0= Interrupt-on-change disabled on the pin

bit 4-0

IOCA<4:0>: Interrupt-on-Change PORTGPA Register bits

1= Interrupt-on-change enabled on the pin

0= Interrupt-on-change disabled on the pin

Note 1: The Interrupt-on-change on GPA5 is disabled if GPA5 is configured as MCLR.

REGISTER 20-2: IOCB: INTERRUPT-ON-CHANGE PORTGPB REGISTER

R/W-0

IOCB7⁽¹⁾

R/W-0

IOCB6⁽¹⁾

R/W-0

IOCB5⁽¹⁾

R/W-0

IOCB4⁽¹⁾

U-0

—

R/W-0

IOCB2

R/W-0

IOCB1

R/W-0

IOCB0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

IOCB<7:4>: Interrupt-on-Change PORTGPB Register bits

1= Interrupt-on-change enabled on the pin

0= Interrupt-on-change disabled on the pin

bit 3

Unimplemented: Read as ‘0’

bit 2-0

IOCB<2:0>: Interrupt-on-Change PORTGPB Register bits

1= Interrupt-on-change enabled on the pin

0= Interrupt-on-change disabled on the pin

Note 1: Not implemented on MCP19111.

TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

ANSELB

INTCON

IOCA

—

ANSA3

—

ANSA2

ANSB2

T0IF

ANSA1

ANSB1

INTF

ANSA0

—

115

118

96

—

ANSB5

T0IE

ANSB4

INTE

GIE

PEIE

IOCA6

IOCB6

TRISA6

IOCE

IOCA3

—

IOCF

IOCA7

IOCB7

TRISA7

IOCA5

IOCB5

TRISA5

IOCA4

IOCB4

TRISA4

IOCA2

IOCB2

TRISA2

IOCA1

IOCB1

TRISA1

IOCA0

IOCB0

TRISA0

122

114

117

IOCB

TRISGPA

TRISA3

TRISGPB

TRISB7

TRISB6

TRISB5

TRISB4

—

TRISB2

TRISB1

TRISB0

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by interrupt-on-change.

DS20002331D-page 122

 2013-2016 Microchip Technology Inc.

MCP19110/11

21.2 Temperature Output

21.0 INTERNAL TEMPERATURE

INDICATOR MODULE

The output of the circuit is measured using the internal

analog-to-digital converter. Channel 10 is reserved for

the temperature circuit output. Refer to Section 22.0

“Analog-to-Digital Converter (ADC) Module” for

detailed information.

The MCP19110/11 is equipped with a temperature

circuit designed to measure the operating temperature

of the silicon die. The circuit's range of the operating

temperature falls between -40°C and +125°C. The

output is a voltage that is proportional to the device

temperature. The output of the temperature indicator is

internally connected to the device ADC.

The temperature of the silicon die can be calculated by

the ADC measurement by using Equation 21-1.

EQUATION 21-1: SILICON DIE

TEMPERATURE

21.1 Circuit Operation

The TMPSEN bit in the ABECON register,

Register 6-15, is set to enable the internal temperature

ADC READING – 1.75

----------------------------------------------------------

TEMP_DIE=

13.3mV/C

measurement

circuit.

The

MCP19110/11

overtemperature shutdown feature is also controlled by

this bit.

FIGURE 21-1:

TEMPERATURE CIRCUIT

DIAGRAM

V

DD

TMPSEN

V

OUT

ADC

MUX

ADC

n

CHS bits

(ADCON0 register)

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MCP19110/11

NOTES:

DS20002331D-page 124

 2013-2016 Microchip Technology Inc.

MCP19110/11

The internal band gap supplies the voltage reference to

the ADC.

22.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

approximation and stores the right justified conversion

result into the ADC result registers (ADRESH:ADRESL

register pair). Figure 22-1 shows the block diagram of

the ADC.

FIGURE 22-1:

ADC BLOCK DIAGRAM

00000

V_{IN_ANA}

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

V_REF

OV_REF

UV_REF

V_BGR

V_REF

V_OUT

CRT

VZC

DEMAND

RELEFF

TEMP_ANA

ANA_IN

DCI

ADC

GO/DONE

10

10000

10001

10010

10011

10100

10101

10110

10111

ADON

GPA0

GPA1

ADRESH ADRESL

V_SS

GPA2

GPA3

GPB1

GPB2

GPB4⁽³⁾

GPB5⁽³⁾

CHS4:CHS0

Note 1: When ADON = 0, all multiplexer inputs are disconnected.

2: See ADCON0 register (Register 22-1) for detailed analog channel selection per device.

3: Not implemented on MCP19110.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 125

MCP19110/11

22.1.3

ADC CONVERSION CLOCK

22.1 ADC Configuration

The source of the conversion clock is software

selectable via the ADCS bits of the ADCON1 register.

There are five possible clock options:

When configuring and using the ADC, the following

functions must be considered:

• Port configuration

• Channel selection

• ADC conversion clock source

• Interrupt control

• F_OSC/8

• F_OSC/16

• F_OSC/32

• F_OSC/64

• Result formatting

• F_RC(clock derived from internal oscillator with a

divisor of 16)

22.1.1

PORT CONFIGURATION

The time to complete one bit conversion is defined as

T_AD. One full 10-bit conversion requires 11 T_ADperiods

as shown in Figure 22-2.

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to

Section 19.0 “I/O Ports” for more information.

For

a correct conversion, the appropriate T_AD

specification must be met. Refer to the A/D conversion

requirements in Section 5.0 “Digital Electrical

Characteristics” for more information. Table 22-1

gives examples of appropriate ADC clock selections.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

Note:

Unless using the F_RC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

22.1.2

CHANNEL SELECTION

There are up to 19 channel selections available on the

MCP19110 and 21 channel selections available on the

MCP19111:

• AN<6:0> pins

TABLE 22-1: ADC CLOCK PERIOD (T ) VS.

AD

DEVICE OPERATING

FREQUENCIES

• VIN_ANA: 1/13 of the input voltage (V_IN)

• VREGREF: V_OUTreference voltage

• OV_REF: reference for OV comparator

• UV_REF: reference for UV comparator

• VBGR: band gap reference

Device

ADC Clock Period (T_AD

)

Frequency

(F_OSC

)

• VOUT: output voltage

ADC

Clock Source

ADCS<2:0>

8 MHz

• CRT: voltage proportional to the AC inductor

current

F_OSC/8

001

101

010

110

x11

1.0 µs⁽²⁾

2.0 µs

• VZC: an internal ground, Voltage for Zero Current

• DEMAND: input to slope compensation circuitry

• RELEFF: relative efficient measurement channel

F_OSC/16

F

_OSC/32

_OSC/64

F_RC

4.0 µs

8.0 µs⁽³⁾

2.0 – 6.0 µs^(1,4)

• TMP_ANA: voltage proportional to silicon die tem-

perature

• ANA_IN: for a multi-phase slave, error amplifier

signal received from master

Legend: Shaded cells are outside of recommended

range.

• DCI: DC inductor valley current

Note 1: The F_RCsource has a typical T_ADtime of

4 µs for V_DD> 3.0V.

The CHS<4:0> bits of the ADCON0 register determine

which channel is connected to the sample and hold

circuit.

2: These values violate the minimum

required T_ADtime.

3: For faster conversion times, the selection

When changing channels, a delay is required before

starting the next conversion. Refer to Section 22.2

“ADC Operation” for more information.

of another clock source is recommended.

4: The F_RCclock source is only

recommended if the conversion will be

preformed during Sleep.

DS20002331D-page 126

 2013-2016 Microchip Technology Inc.

MCP19110/11

FIGURE 22-2:

ANALOG-TO-DIGITAL CONVERSION T CYCLES

AD

T_CY- T

T_AD8 T_AD9 T_AD10 T_AD11

7

_ADT_AD1 T_AD2 T_AD3 T_AD4 T_AD

5

T_AD6 T_AD

b4

b1

b0

b9

Conversion starts

b8

b7

b6

b5

b3

b2

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO/DONE bit

On the following cycle:

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

This interrupt can be generated while the device is

operating, or while in Sleep. If the device is in Sleep,

22.1.4

INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC Interrupt Flag is the ADIF bit in

the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be

cleared in software.

the interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the GIE and PEIE bits of the INTCON

register must be disabled. If the GIE and PEIE bits of

the INTCON register are enabled, execution will switch

to the Interrupt Service Routine.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

22.1.5

RESULT FORMATTING

2: The ADC operates during Sleep-only

The 10-bit A/D conversion result is supplied in right

justified format only.

when the F_RCoscillator is selected.

Figure 22-3 shows the output format.

FIGURE 22-3:

10-BIT A/D RESULT FORMAT

(ADFM = 1)

MSB

LSB

bit 7

bit 0

bit 7

bit 0

Read as ‘0’

10-bit A/D Result

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DS20002331D-page 127

MCP19110/11

22.2.5

A/D CONVERSION PROCEDURE

22.2 ADC Operation

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

22.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the

GO/DONE bit of the ADCON0 register to a ‘1’ will start

the Analog-to-Digital conversion.

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

register)

• Configure pin as analog (Refer to the ANSEL

register)

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

2. Configure the ADC module:

• Select ADC conversion clock

• Select ADC input channel

• Turn on ADC module

Refer

to

Section 22.2.5

“A/D

Conversion Procedure”.

22.2.2

COMPLETION OF A CONVERSION

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Enable ADC interrupt

• Set the ADIF Interrupt Flag bit

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

• Update the ADRESH:ADRESL registers with new

conversion result

.

5. Start conversion by setting the GO/DONE bit.

22.2.3

TERMINATING A CONVERSION

6. Wait for ADC conversion to complete by one of

the following:

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRESH:ADRESL registers will not be updated with

the partially complete Analog-to-Digital conversion

sample. Instead, the ADRESH:ADRESL register pair

will retain the value of the previous conversion.

Additionally, a two T_ADdelay is required before another

acquisition can be initiated. Following the delay, an

input acquisition is automatically started on the

selected channel.

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

2: Refer to Section 22.4 “A/D Acquisition

Requirements”.

EXAMPLE 22-1:

;This code block configures the ADC

A/D CONVERSION

22.2.4

ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the F_RC

option. When the F_RCclock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

;for polling, Frc clock and AN0 input.

;

;Conversion start & polling for completion ;

are included.

;

BANKSEL

MOVLW

MOVWF

BANKSEL

BSF

BANKSEL

BSF

BANKSEL

MOVLW

MOVWF

CALL

BSF

BTFSC

GOTO

BANKSEL

MOVF

MOVWF

BANKSEL

MOVF

ADCON1

B’01110000’

ADCON1

TRISGPA

TRISGPA,0

ANSELA

ANSELA,0

ADCON0

B’01000001’

ADCON0

SampleTime

ADCON0,1

$-1

;

;Frc clock

;

;Set GPA0 to input

;

;Set GPA0 to analog

;

;Select channel AN0

;Turn ADC On

;Acquisiton delay

;Start conversion

;Is conversion done?

;No, test again

;

;Read upper 2 bits

;store in GPR space

;

When the ADC clock source is something other than

F_RC, a SLEEP instruction causes the present

conversion to be aborted and the ADC module is

turned off, although the ADON bit remains set.

ADRESH

ADRESH,W

RESULTHI

ADRESL

ADRESL,W

RESULTLO

;Read lower 8 bits

;Store in GPR space

MOVWF

DS20002331D-page 128

 2013-2016 Microchip Technology Inc.

MCP19110/11

22.3 ADC Register Definitions

The following registers are used to control the

operation of the ADC:

REGISTER 22-1: ADCON0: A/D CONTROL REGISTER 0

U-0

—

R/W-0

CHS4

R/W-0

CHS3

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

ADON

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

CHS<4:0>: Analog Channel Select bits

bit 6-2

00000= VIN_ANA (analog voltage proportional to 1/13 of V_IN)

00001= VREGREF (reference voltage for V_REGoutput)

00010= OV_REF (reference for overvoltage comparator)

00011= UV_REF (reference for undervoltage comparator)

00100= VBGR (band gap reference)

00101= INT_VREG (internal version of the V_REGload voltage)

00110= CRT (voltage proportional to the current in the inductor)

00111= VZC (an internal ground, Voltage for Zero Current)

01000= DEMAND (input to current loop, output of demand mux)

01001= RELEFF (analog voltage proportional to duty cycle)

01010= TMP_ANA (analog voltage proportional to temperature)

01011= ANA_IN (demanded current from the remote master)

01100= DCI (dc inductor valley current)

01101= Unimplemented

01110= Unimplemented

01111= Unimplemented

10000= GPA0 (i.e. ADDR1)

10001= GPA1 (i.e. ADDR0)

10010= GPA2 (i.e. Temperature Sensor Input)

10011= GPA3 (i.e. Tracking Voltage)

10100= GPB1

10101= GPB2

10110= GPB4⁽¹⁾

10111= GPB5⁽¹⁾

11000= Unimplemented

11001= Unimplemented

11011= Unimplemented

11100= Unimplemented

11101= Unimplemented

11110= Unimplemented

11111= Unimplemented

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

Note 1: Not implemented on MCP19110.

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DS20002331D-page 129

MCP19110/11

REGISTER 22-2: ADCON1: A/D CONTROL REGISTER 1

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000= Reserved

001= F_OSC/8

010= F_OSC/32

x11= F_RC(clock derived from internal oscillator with a divisor of 16)

100= Reserved

101= F_OSC/16

110= F_OSC/64

bit 3-0

Unimplemented: Read as ‘0’

REGISTER 22-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-x

ADRES9

ADRES8

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1-0

Unimplemented: Read as ‘0’

ADRES<9:8>: Most Significant A/D Results

REGISTER 22-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL)

R-x

ADRES7

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

ADRES1

ADRES0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-0

ADRES<7:0>: Least Significant A/D results

DS20002331D-page 130

 2013-2016 Microchip Technology Inc.

MCP19110/11

The maximum recommended impedance for

analog sources is 10 k. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 22-1 may be used. This equation

assumes that 1/2 LSb error is used (1,024 steps for the

ADC). The 1/2 LSb error is the maximum error allowed

for the ADC to meet its specified resolution.

22.4 A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (C_HOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 22-4. The source

impedance (R_S) and the internal sampling switch (R_SS

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (R_SS

)

impedance varies over the device voltage (V_DD), refer

to Figure 22-4.

EQUATION 22-1: ACQUISITION TIME EXAMPLE

Assumptions:

Temperature = +50°C and external impedance of 10 k 5.0V V

DD

T

= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

ACQ

= T

+ T + T

AMP

C

COFF

= 2 µs + T + Temperature - 25°C0.05 µs/°C

C

The value for T can be approximated with the following equations:

C













1

-----------------------------

;[1] V_CHOLDcharged to within 1/2 lsb

V

1 –

= V

APPLIED

CHOLD

n + 1

2

 – 1

–T

C













----------

RC

1 – e

= V

;[2] V_CHOLDcharge response to V_APPLIED

;combining [1] and [2]

CHOLD

–T

C













----------













RC

1

-----------------------------

1 –

APPLIED

n + 1

2

 – 1

Note: Where n = number of bits of the ADC.

Solving for T :

C

T

= –C

R + R + R  ln(1/2047)

HOLD IC SS

C

S

= –10 pF1 k + 7 k + 10 k ln(0.0004885)

= 1.37µs

Therefore:

T

= 2 µs + 1.37µs + 50°C- 25°C0.05µs/°C

ACQ

= 4.67 µs

Note 1: The charge holding capacitor (C_HOLD) is not discharged after each conversion.

2: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 131

MCP19110/11

FIGURE 22-4:

ANALOG INPUT MODEL

V_DD

V_T0.6V

Analog

Input

Sampling

Switch

R_IC 1k

SS

R

SS

S

(1)

C_PIN

5 pF

I_LEAKAGE

VA

C_HOLD= 10 pF

_SS/V_REF

V

0.6V

T

V

-

6V

Legend:

5V

R_SS

C_HOLD= Sample/Hold Capacitance

C_PIN= Input Capacitance

V_DD4V

3V

2V

I_LEAKAGE= Leakage current at the pin due to various junctions

R_IC= Interconnect Resistance

5 6 7 8 91011

Sampling Switch

(k)

R_SS= Resistance of Sampling Switch

SS = Sampling Switch

V_T= Threshold Voltage

Note 1: Refer to Section 5.0 “Digital Electrical Characteristics”.

FIGURE 22-5:

ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

03h

02h

01h

00h

Analog Input Voltage

1.5 LSB

0.5 LSB

Zero-Scale

Transition

V_REF

-

Full-Scale

Transition

V_REF+

DS20002331D-page 132

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON0

ADCON1

ADRESH

ADRESL

ANSELA

ANSELB

INTCON

PIE1

—

CHS4

ADCS2

—

CHS3

ADCS1

—

CHS2

ADCS0

—

CHS1

—

CHS0

—

GO/DONE ADON

129

130

115

118

95

—

ADRES9 ADRES8

ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0

—

ANSA3

—

ANSA2

ANSB2

T0IF

ANSA1

ANSB1

INTF

ANSA0

—

ANSB5

T0IE

ANSB4

INTE

GIE

PEIE

ADIE

ADIF

TRISA6

TRISB6

IOCE

—

IOCF

—

BCLIE

BCLIF

TRISA5

TRISB5

SSPIE

SSPIF

TRISA4

TRISB4

—

TMR2IE

TMR2IF

TRISA1

TRISB1

TMR1IE

TMR1IF

TRISA0

TRISB0

96

PIR1

—

98

TRISGPA

TRISGPB

TRISA7

TRISB7

TRISA3

—

TRISA2

TRISB2

114

117

Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 133

MCP19110/11

NOTES:

DS20002331D-page 134

 2013-2016 Microchip Technology Inc.

MCP19110/11

23.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (independent of Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

Figure 23-1 is a block diagram of the Timer0 module.

FIGURE 23-1:

BLOCK DIAGRAM OF THE TIMER0

F_OSC/4

Data Bus

0

1

8

T0CKI

1

0

Sync

2 T_CY

TMR0

Set Flag bit TMR0IF

on Overflow

TMR0SE

8-bit

Prescaler

TMR0CS

PSA

Overflow to Timer1

8

PS<2:0>

23.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

23.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignment is controlled by the PSA bit of the

OPTION_REG register. To assign the prescaler to

Timer0, the PSA bit must be cleared to ‘0’.

23.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-Bit Timer mode is

selected by clearing the T0CS bit of the OPTION_REG

register.

There are eight prescaler options for the Timer0

module ranging from 1:2 to 1:256. The prescale values

are selectable via the PS<2:0> bits of the

OPTION_REG register. In order to have a 1:1 prescaler

value for the Timer0 module, the prescaler must be

disabled by setting the PSA bit of the OPTION_REG

register.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register

can be adjusted, in order to account for

the two-instruction cycle delay when

TMR0 is written.

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing to

the TMR0 register will clear the prescaler.

23.1.2

8-BIT COUNTER MODE

In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin. The

incrementing edge is determined by the T0SE bit of the

OPTION_REG register.

8-Bit Counter mode using the T0CKI pin is selected by

setting the T0CS bit in the OPTION_REG register to ‘1’.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 135

MCP19110/11

23.1.4

SWITCHING PRESCALER

BETWEEN TIMER0 AND WDT

MODULES

23.1.5

TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The T0IF interrupt

flag bit of the INTCON register is set every time the

TMR0 register overflows, regardless of whether or not

the Timer0 interrupt is enabled. The T0IF bit can only

be cleared in software. The Timer0 interrupt enable is

the T0IE bit of the INTCON register.

As a result of having the prescaler assigned to either

Timer0 or the WDT, it is possible to generate an

unintended device Reset when switching prescaler

values. When changing the prescaler assignment from

Timer0 to the WDT module, the instruction sequence

shown in Example 23-1 must be executed.

Note:

The Timer0 interrupt cannot wake the

processor from Sleep, since the timer is

frozen during Sleep.

EXAMPLE 23-1:

CHANGING PRESCALER

(TIMER0  WDT)

BANKSEL TMR0

CLRWDT

;

23.1.6

USING TIMER0 WITH AN

EXTERNAL CLOCK

;Clear WDT

;Clear TMR0 and

;prescaler

;

CLRF

TMR0

When Timer0 is in Counter mode, the synchronization

of the T0CKI input and the Timer0 register is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks.

Therefore, the high and low periods of the external

clock source must meet the timing requirements as

BANKSEL OPTION_REG

BSF

CLRWDT

OPTION_REG,PSA ;Select WDT

;

MOVLW

ANDWF

IORLW

MOVWF

b’11111000’

;Mask prescaler

;bits

;Set WDT prescaler

;to 1:32

OPTION_REG,W

b’00000101’

OPTION_REG

shown

in

Section 5.0

“Digital

Electrical

Characteristics”.

23.1.7

OPERATION DURING SLEEP

When changing the prescaler assignment from the

WDT to the Timer0 module, the following instruction

sequence must be executed (see Example 23-2).

Timer0 cannot operate while the processor is in Sleep

mode. The contents of the TMR0 register will remain

unchanged while the processor is in Sleep mode.

EXAMPLE 23-2:

CHANGING PRESCALER

(WDT  TIMER0)

CLRWDT

;Clear WDT and

;prescaler

;

BANKSEL OPTION_REG

MOVLW

ANDWF

IORLW

MOVWF

b’11110000’ ;Mask TMR0 select and

OPTION_REG,W ;prescaler bits

b’00000011’ ;Set prescale to 1:16

OPTION_REG

;

TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register

on Page

Name

INTCON

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GIE

PEIE

T0IE

INTE

T0SE

IOCIE

PSA

T0IF

PS2

INTF

PS1

IOCIF

PS0

96

OPTION_REG

TMR0

RAPU

INTEDG

T0CS

77

Timer0 Module Register

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3

135*

114

TRISGPA

TRISA2 TRISA1 TRISA0

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.

Page provides register information.

*

DS20002331D-page 136

 2013-2016 Microchip Technology Inc.

MCP19110/11

24.0 TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer with the following

features:

• 16-bit timer register pair (TMR1H:TMR1L)

• Readable and Writable (both registers)

• Selectable internal clock source

• 2-bit prescaler

• Interrupt on overflow

Figure 24-1 is a block diagram of the Timer1 module.

FIGURE 24-1:

TIMER1 BLOCK DIAGRAM

TMR1ON

Set flag bit

TMR1IF on

Overflow

TMR1⁽¹⁾

TMR1L

TMR1H

F_OSC

1

0

Prescaler

1, 2, 4, 8

2

F_OSC/4

T1CKPS<1:0>

Note 1: TMR1 register increments on rising edge.

TMR1CS

24.2.1

INTERNAL CLOCK SOURCE

24.1 Timer1 Operation

The TMR1H:TMR1L register pair will increment on

multiples of F_OSCor F_OSC/4 as determined by the

Timer1 prescaler.

The Timer1 module is a 16-bit incrementing timer which

is accessed through the TMR1H:TMR1L register pair.

Writes to TMR1H or TMR1L directly update the

counter. The timer is incremented on every instruction

cycle.

As an example, when the F_OSCinternal clock source is

selected, the Timer1 register value will increment by four

counts every instruction clock cycle.

Timer1 is enabled by configuring the TMR1ON bit in the

T1CON register. Table 24-1 displays the Timer1 enable

selections.

TABLE 24-1: CLOCK SOURCE

SELECTIONS

TMR1CS

Clock Source

24.2 Clock Source Selection

1

0

8 MHz system Clock (F_OSC)

The TMR1CS bit of the T1CON register is used to select

the clock source for Timer1. Table 24-1 displays the

clock source selections.

2 MHz instruction clock (F_OSC/4)

 2013-2016 Microchip Technology Inc.

DS20002331D-page 137

MCP19110/11

24.3 Timer1 Prescaler

24.5 Timer1 in Sleep

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

Unlike other standard mid-range Timer1 modules, the

MCP19110/11 Timer1 module only clocks from an

internal system clock, and thus does not run during

Sleep mode, nor can it be used to wake the device from

this mode.

24.6 Timer1 Control Register

24.4 Timer1 Interrupt

The Timer1 Control register (T1CON), shown in

Register 24-1, is used to control Timer1 and select the

various features of the Timer1 module.

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

REGISTER 24-1: T1CON: TIMER1 CONTROL REGISTER

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

T1CKPS1

T1CKPS0

TMR1CS

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3-2

bit 1

Unimplemented: Read as ‘0’

TMR1CS: Timer1 Clock Source Control bit

1= 8 MHz system clock (F_OSC

)

0= 2 MHz instruction clock (F_OSC

TMR1ON: Timer1 On bit

1= Enables Timer1

)

bit 0

0= Stops Timer1, Clears Timer1 gate flip-flop

DS20002331D-page 138

 2013-2016 Microchip Technology Inc.

MCP19110/11

TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

BCLIE

BCLIF

INTE

SSPIE

SSPIF

IOCE

—

T0IF

—

INTF

IOCF

95

96

TMR2IE TMR1IE

TMR2IF TMR1IF

PIR1

—

98

TMR1H

TMR1L

T1CON

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

137*

138

—

T1CKPS1 T1CKPS0

—

TMR1CS TMR1ON

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

Page provides register information.

*

 2013-2016 Microchip Technology Inc.

DS20002331D-page 139

MCP19110/11

The match output of the Timer2/PR2 comparator is

used to set the TMR2IF interrupt flag bit in the PIR1

register.

25.0 TIMER2 MODULE

The Timer2 module is an 8-bit timer with the following

features:

The TMR2 and PR2 registers are both fully readable

and writable. On any Reset, the TMR2 register is set to

00h and the PR2 register is set to FFh.

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

Timer2 is turned on by setting the TMR2ON bit in the

T2CON register to a ‘1’. Timer2 is turned off by clearing

the TMR2ON bit to a ‘0’.

See Figure 25-1 for a block diagram of Timer2.

The Timer2 prescaler is controlled by the T2CKPS bits

in the T2CON register. The prescaler counter is cleared

when:

25.1 Timer2 Operation

The clock input to the Timer2 module is the system

clock (F_OSC). The clock is fed into the Timer2 prescaler,

which has prescale options of 1:1, 1:4 or 1:16. The

output of the prescaler is then used to increment the

TMR2 register.

• A write to TMR2 occurs

• A write to T2CON occurs

• Any device Reset occurs (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset)

The values of TMR2 and PR2 are constantly compared

to determine when they match. TMR2 will increment

from 00h until it matches the value in PR2. When a

match occurs, TMR2 is reset to 00h on the next

increment cycle.

Note:

TMR2 is not cleared when T2CON is

written.

FIGURE 25-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

TMR2

bit TMR2IF

Output

Reset

EQ

Prescaler

1:1, 1:4, 1:8, 1:16

TMR2

F_OSC

2

Comparator

PR2

T2CKPS<1:0>

DS20002331D-page 140

 2013-2016 Microchip Technology Inc.

MCP19110/11

25.2 Timer2 Control Register

REGISTER 25-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

TMR2ON

T2CKPS1

T2CKPS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-3

bit 2

Unimplemented: Read as ‘0’

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00=Prescaler is 1

01=Prescaler is 4

10=Prescaler is 8

11=Prescaler is 16

TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

BCLIE

BCLIF

INTE

SSPIE

SSPIF

IOCE

—

T0IF

—

INTF

IOCF

95

96

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

—

98

PR2

Timer2 Module Period Register

TMR2ON T2CKPS1 T2CKPS0

Holding Register for the 8-bit TMR2 Time Base

140*

141

140*

T2CON

TMR2

—

Legend: — = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

Page provides register information.

*

 2013-2016 Microchip Technology Inc.

DS20002331D-page 141

MCP19110/11

NOTES:

DS20002331D-page 142

 2013-2016 Microchip Technology Inc.

MCP19110/11

26.1.2

SWITCHING FREQUENCY

SYNCHRONIZATION MODE

26.0 PWM MODULE

The CCP module implemented on the MCP19110/11

is a modified version of the CCP module found in

The MCP19110/11 can be programmed to be a

switching frequency MASTER or SLAVE device. The

MASTER device functions as described in

Section 26.1.1

Synchronization) Mode” with the exception of the

standard

mid-range

microcontrollers.

In

the

MCP19110/11, the PWM module is used to generate

the system clock or system oscillator. This system

clock will control the MCP19110/11 switching

frequency, as well as set the maximum allowable duty

cycle. The PWM module does not continuously adjust

the duty cycle to control the output voltage. This is

accomplished by the analog control loop and

associated circuitry.

“Stand-Alone

(Non-Frequency

system clock also being applied to GPA1.

A SLAVE device will receive the MASTER system

clock on GPA1. This MASTER system clock will be

OR’ed with the output of the TIMER2 module. This

OR’ed signal will latch PWMRL into PWMRH and

PWMPHL into PWMPHH.

26.1 Standard Pulse-Width Modulation

(PWM) Mode

Figure 26-1 shows a simplified block diagram of the

CCP module in PWM mode.

The PWMPHL register allows for a phase shift to be

added to the SLAVE system clock.

The PWM module output signal is used to set the

operating switching frequency and maximum

allowable duty cycle of the MCP19110/11. The actual

duty cycle on the HDRV and LDRV is controlled by the

analog PWM control loop. However, this duty cycle

cannot be greater than the value in the PWMRL

register.

It is desired to have the MCP19110/11 SLAVE device’s

system clock start point shifted by a programmed

amount from the MASTER system clock. This SLAVE

phase shift is specified by writing to the PWMPHL reg-

ister. The SLAVE phase shift can be calculated by

using the following equation.

There are two modes of operation that concern the

system clock PWM signal. These modes are

stand-alone (non-frequency synchronization) and

frequency synchronization.

EQUATION 26-2:

SLAVE PHASE SHIFT=PWMPHL•TOSC•(T2 PRESCALE VALUE)

26.1.1

STAND-ALONE (NON-FREQUENCY

SYNCHRONIZATION) MODE

When the MCP19110/11 is running stand-alone, the

PWM signal functions as the system clock. It is

operating at the programmed switching frequency with

a programmed maximum duty cycle (D_CLOCK). The

programmed maximum duty cycle is not adjusted on a

cycle-by-cycle basis to control the MCP19110/11

system output. The required duty cycle (D_BUCK) to

control the output is adjusted by the MCP19110/11

analog control loop and associated circuitry. D_CLOCK

does, however, set the maximum allowable D_BUCK

.

EQUATION 26-1:

D_BUCK 1 – D_CLOCK

 2013-2016 Microchip Technology Inc.

DS20002331D-page 143

MCP19110/11

FIGURE 26-1:

SIMPLIFIED PWM BLOCK DIAGRAM

PWMRL

8

PWMPHL

8

PWMPHH

(SLAVE)

PWMRH

(SLAVE)

LATCH DATA

8

SYSTEM

CLOCK

OSC

Comparator

R

S

Q

8

RESET TIMER

TMR2

(Note 1)

8

Comparator

8

CLKPIN_IN

PR2

Note 1: TIMER 2 should be clocked by F_OSC(8 MHz).

A PWM output (Figure 26-2) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

26.1.3

PWM PERIOD

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the

following equation:

FIGURE 26-2:

PWM OUTPUT

EQUATION 26-3:

Period

PWM PERIOD=[(PR2)+1] x T_OSCx (T2 PRESCALE VALUE)

When TMR2 is equal to PR2, the following two events

occur on the next increment cycle:

Duty Cycle

TMR2 = PR2 + 1

• TMR2 is cleared

TMR2 = PWMRH

• The PWM duty cycle is latched from PWMRL into

PWMRH

TMR2 = PR2 + 1

DS20002331D-page 144

 2013-2016 Microchip Technology Inc.

MCP19110/11

26.1.4

PWM DUTY CYCLE (D

)

CLOCK

26.2 Operation During Sleep

The PWM duty cycle (D_CLOCK) is specified by writing

to the PWMRL register. Up to 8-bit resolution is

available. The following equation is used to calculate

the PWM duty cycle (D_CLOCK):

When the device is placed in Sleep, the allocated

timer will not increment and the state of the module will

not change. If the CLKPIN pin is driving a value, it will

continue to drive that value. When the device wakes

up, it will continue from this state.

EQUATION 26-4:

PWM DUTY CYCLE=PWMRL x T_OSCx (T2 PRESCALE VALUE)

The PWMRL bits can be written to at any time, but the

duty cycle value is not latched into PWMRH until after

a match between PR2 and TMR2 occurs.

TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH PWM MODULE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

APFCON

T2CON

—

CLKSEL

112

141

140*

143*

58

TMR2ON T2CKPS1 T2CKPS0

PR2

Timer2 Module Period Register

PWM Register Low Byte

SLAVE Phase Shift Byte

PWMRL

PWMPHL

BUFFCON

MLTPH2 MLTPH1 MLTPH0

ASEL4

ASEL3

ASEL2

ASEL1

ASEL0

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Capture mode.

Page provides register information.

*

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NOTES:

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The I²C interface supports the following modes and

features:

27.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

• Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited Multi-Master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

27.1 Master SSP (MSSP) Module

Overview

The Master Synchronous Serial Port (MSSP) module is

a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be Serial EEPROMs, shift registers,

display drivers, A/D converters, etc. The MSSP module

only operates in Inter-Integrated Circuit (I²C) mode.

• Clock stretching

• Bus collision detection

• General call address matching

• Dual Address masking

• Address Hold and Data Hold modes

• Selectable SDA hold times

Figure 27-1 is a block diagram of the I²C interface

module in Master mode. Figure 27-2 is a diagram of the

I²C interface module in Slave mode.

2

FIGURE 27-1:

MSSP BLOCK DIAGRAM (I C MASTER MODE)

Internal

data bus

[SSPM 3:0]

Read

Write

SSPBUF

SSPSR

Baud rate

generator

(SSPADD)

SDA

Shift

Clock

SDA in

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate (SSPCON2)

SCL

Start bit detect,

Stop bit detect,

SCL in

Bus Collision

Write collision detect,

Clock arbitration,

State counter for,

end of XMIT/RCV,

Address Match detect

Set/Reset: S, P, SSPSTAT, WCOL, SSPxOV

Reset SEN, PEN (SSPCON2)

Set SSPIF, BCLIF

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2

FIGURE 27-2:

MSSP BLOCK DIAGRAM (I C SLAVE MODE)

Internal

Data Bus

Read

Write

SSPBUF Reg

SSPSR Reg

SCL

Shift

Clock

SDA

MSb

LSb

SSPMSK Reg

Match Detect

SSPADD Reg

Addr Match

Set, Reset

S, P bits

(SSPSTAT Reg)

Start and

Stop bit Detect

The SSPCON1 register is used to define the I²C mode.

Four selection bits (SSPCON1<3:0>) allow one of the

following I²C modes to be selected:

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

• I²C Master mode, clock = OSC/4 (SSPADD +1)

• I²C firmware controlled Master mode (Slave idle)

2

27.2 I C MODE OVERVIEW

The Inter-Integrated Circuit Bus (I²C) is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment, where the master

devices initiate the communication. A Slave device is

controlled through addressing.

The MSSP module has eight registers for I²C

operation. They are the:

The SSPSTAT register gives the status of the data

transfer. This information includes detection of a

START or STOP bit, specifies if the data received byte

was data or address, if the next byte is completion of

the 10-bit address, and if this will be a read or write data

transfer.

• MSSP Status Register (SSPSTAT)

• MSSP Control Register1 (SSPCON1)

• MSSP Control Register2 (SSPCON2)

• MSSP Control Register3 (SSPCON3)

• Serial Receive/Transmit Buffer (SSPBUF)

The SSPBUF is the register in which transfer data is

written to or read from. The SSPSR register shifts the

data in or out of the device. In receive operation, the

SSPBUF and SSPSR create a double buffer receiver.

This allows reception of the next byte to begin before

reading the last byte of received data. When the

complete byte is received before the SSPBUF register

is read, a receiver overflow has occurred and the

SSPOV bit (SSPCON1<6>) is set and the byte in the

SSPSR is lost.

• MSSP Shift Register (SSPSR) - Not directly

accessible

• MSSP Address Register (SSPADD)

• MSSP Address Register2 (SSPADD2)

• MSSP Address Mask Register1 (SSPMSK)

• MSSP Address Mask Register2 (SSPMSK2)

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The I²C bus specifies two signal connections:

A Start bit is indicated by a high-to-low transition of the

SDA line while the SCL line is held high. Address and

data bytes are sent out, Most Significant bit (MSb) first.

The Read/Write bit is sent out as a logical one when the

master intends to read data from the slave, and is sent

out as a logical zero when it intends to write data to the

slave.

• Serial Clock (SCL)

• Serial Data (SDA)

Both the SCL and SDA connections are bidirectional

open-drain lines, each requiring pull-up resistors for the

supply voltage. Pulling the line to ground is considered

a logical zero; letting the line float is considered a

logical one.

Before selecting any I²C mode, the SCL and SDA pins

must be programmed to inputs by setting the

appropriate TRIS bits. Selecting I²C mode, by setting

the SSPEN bit, enables the SCL and SDA pins to be

used as clock and data lines in I²C mode.

The Acknowledge bit (ACK) is an active-low signal,

which holds the SDA line low to indicate to the

transmitter that the slave device has received the

transmitted data and is ready to receive more.

The transition of a data bit is always performed while

the SCL line is held low. Transitions that occur while the

SCL line is held high are used to indicate Start and Stop

bits.

Figure 27-3 shows a typical connection between two

devices configured as master and slave.

If the master intends to write to the slave, then it

repeatedly sends out a byte of data, with the slave

responding after each byte with an ACK bit. In this

example, the master device is in Master Transmit

mode, and the slave is in Slave Receive mode.

2

FIGURE 27-3:

I C MASTER/SLAVE

CONNECTION

V_DD

If the master intends to read from the slave, then it

repeatedly receives a byte of data from the slave, and

responds after each byte with an ACK bit. In this

example, the master device is in Master Receive mode,

and the slave is Slave Transmit mode.

SCL

V_DD

Master

Slave

On the last byte of data communicated, the master

device may end the transmission by sending a Stop bit.

If the master device is in Receive mode, it sends the

Stop bit in place of the last ACK bit. A Stop bit is

indicated by a low-to-high transition of the SDA line,

while the SCL line is held high.

SDA

The I²C bus can operate with one or more master

devices and one or more slave devices.

In some cases, the master may want to maintain

control of the bus and reinitiate another transmission. If

so, the master device may send another Start bit in

place of the Stop bit or last ACK bit when it is in receive

mode.

There are four potential modes of operation for a given

device:

• Master Transmit mode

(master is transmitting data to a slave)

• Master Receive mode

(master is receiving data from a slave)

The I²C bus specifies three message protocols:

• Single message where a master writes data to a

slave

• Slave Transmit mode

(slave is transmitting data to a master)

• Single message where a master reads data from

a slave

• Slave Receive mode

(slave is receiving data from the master)

• Combined message where a master initiates a

minimum of two writes, or two reads, or a

combination of writes and reads, to one or more

slaves

To begin communication, a master device starts out in

Master Transmit mode. The master device sends out a

Start bit followed by the address byte of the slave it

intends to communicate with. This is followed by a

single Read/Write bit, which determines whether the

master intends to transmit to or receive data from the

slave device.

When one device is transmitting a logical one, or letting

the line float, and a second device is transmitting a

logical zero, or holding the line low, the first device can

detect that the line is not a logical one. This detection,

when used on the SCL line, is called clock stretching.

Clock stretching gives slave devices a mechanism to

control the flow of data. When this detection is used on

the SDA line, it is called arbitration. Arbitration ensures

that there is only one master device communicating at

any single time.

If the requested slave exists on the bus, it will respond

with an Acknowledge bit, otherwise known as an ACK.

The master then continues in either Transmit mode or

Receive mode and the slave continues in the

complement, either in Receive mode or Transmit

mode, respectively.

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If two master devices are sending a message to two

different slave devices at the address stage, the master

sending the lower slave address always wins

arbitration. When two master devices send messages

to the same slave address, and addresses can

sometimes refer to multiple slaves, the arbitration

process must continue into the data stage.

27.2.1

CLOCK STRETCHING

When a slave device has not completed processing

data, it can delay the transfer of more data through the

process of Clock Stretching. An addressed slave

device may hold the SCL clock line low after receiving

or sending a bit, indicating that it is not yet ready to

continue. The master that is communicating with the

slave will attempt to raise the SCL line in order to

transfer the next bit, but will detect that the clock line

has not yet been released. Because the SCL

connection is open-drain, the slave has the ability to

hold that line low until it is ready to continue

communicating.

Arbitration usually occurs very rarely, but it is a

necessary process for proper multi-master support.

2

27.3 I C MODE OPERATION

All MSSP I²C communication is byte oriented and

shifted out MSb first. Six SFR registers and two

interrupt flags interface the module with the PIC

microcontroller and user software. Two pins, SDA and

SCL, are exercised by the module to communicate

with other external I²C devices.

Clock stretching allows receivers that cannot keep up

with a transmitter to control the flow of incoming data.

27.2.2

ARBITRATION

Each master device must monitor the bus for Start and

Stop bits. If the device detects that the bus is busy, it

cannot begin a new message until the bus returns to an

Idle state.

27.3.1 BYTE FORMAT

All communication in I²C is done in 9-bit segments. A

byte is sent from a Master to a Slave or vice-versa, fol-

lowed by an Acknowledge bit sent back. After the 8^th

falling edge of the SCL line, the device outputting data

on the SDA changes that pin to an input and reads in

an acknowledge value on the next clock pulse.

However, two master devices may try to initiate a

transmission on or about the same time. When this

occurs, the process of arbitration begins. Each

transmitter checks the level of the SDA data line and

compares it to the level that it expects to find. The first

transmitter to observe that the two levels don't match,

loses arbitration, and must stop transmitting on the

SDA line.

The clock signal, SCL, is provided by the master. Data

is valid to change while the SCL signal is low, and

sampled on the rising edge of the clock. Changes on

the SDA line while the SCL line is high define special

conditions on the bus, explained below.

For example, if one transmitter holds the SDA line to a

logical one (lets it float) and a second transmitter holds

it to a logical zero (pulls it low), the result is that the

SDA line will be low. The first transmitter then observes

that the level of the line is different than expected and

concludes that another transmitter is communicating.

27.3.2 DEFINITION OF I²C TERMINOLOGY

There is language and terminology in the description

of I²C communication that have definitions specific to

I²C. That word usage is defined below and may be

used in the rest of this document without explanation.

This table was adapted from the Philips I²C

specification.

The first transmitter to notice this difference is the one

that loses arbitration and must stop driving the SDA

line. If this transmitter is also a master device, it also

must stop driving the SCL line. It then can monitor the

lines for a Stop condition before trying to reissue its

transmission. In the meantime, the other device that

has not noticed any difference between the expected

and actual levels on the SDA line continues with its

original transmission. It can do so without any

complications, because so far, the transmission

appears exactly as expected with no other transmitter

disturbing the message.

27.3.3 SDA AND SCL PINS

On the MCP19110/11, the SCL and SDA pins are

always open-drain. These pins should be set by the

user to inputs by setting the appropriate TRIS bits.

Note: Data is tied to output zero when an I²C

mode is enabled.

Slave Transmit mode can also be arbitrated, when a

master addresses multiple slaves, but this is less

common.

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27.3.4 SDA HOLD TIME

The hold time of the SDA pin is selected by the SDAHT

bit of the SSPCON3 register. Hold time is the time SDA

is held valid after the falling edge of SCL. Setting the

SDAHT bit selects a longer 300 ns minimum hold time

and may help on buses with large capacitance.

2

TABLE 27-1: I C BUS TERMS

TERM

Description

The device which shifts data out onto the bus.

The device which shifts data in from the bus.

Transmitter

Receiver

Master

The device that initiates a transfer, generates clock signals and terminates a transfer.

The device addressed by the master.

Slave

Multi-Master

Arbitration

A bus with more than one device that can initiate data transfers.

Procedure to ensure that only one master at a time controls the bus. Winning arbitration

ensures that the message is not corrupted.

Synchronization

Idle

Procedure to synchronize the clocks of two or more devices on the bus.

No master is controlling the bus, and both SDA and SCL lines are high.

Any time one or more master devices are controlling the bus.

Active

Addressed Slave

Matching Address

Write Request

Read Request

Slave device that has received a matching address and is actively being clocked by a master.

Address byte that is clocked into a slave that matches the value stored in SSPADDx.

Slave receives a matching address with R/W bit clear, and is ready to clock in data.

Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of

the Slave. This data is the next and all following bytes until a Restart or Stop.

Clock Stretching

Bus Collision

When a device on the bus holds SCL low to stall communication.

Any time the SDA line is sampled low by the module while it is outputting and expected high

state.

27.3.5 START CONDITION

27.3.7 RESTART CONDITION

The I²C specification defines a Start condition as a

transition of SDA from a high to a low state, while SCL

line is high. A Start condition is always generated by

the master and signifies the transition of the bus from

an Idle to an Active state. Figure 27-4 shows the wave

forms for Start and Stop conditions.

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an

address. The master may want to address the same or

another slave.

A bus collision can occur on a Start condition if the

module samples the SDA line low before asserting it

low. This does not conform to the I²C Specification,

that states no bus collision can occur on a Start.

In 10-bit Addressing Slave mode, a Restart is required

for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, match-

ing both high and low address bytes, the master can

issue a Restart and the high address byte with the

R/W bit set. The slave logic will then hold the clock

and prepare to clock out data.

27.3.6 STOP CONDITION

A Stop condition is a transition of the SDA line from

low-to-high state while the SCL line is high.

After a full match with R/W clear in 10-bit mode, a prior

match flag is set and maintained. Until a Stop

condition, a high address with R/W clear or a high

address match fails.

Note: At least one SCL low time must appear

before a Stop is valid, therefore, if the SDA

line goes low then high again while the SCL

line stays high, only the Start condition is

detected.

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27.3.8 START/STOP CONDITION INTERRUPT

MASKING

The SCIE and PCIE bits of the SSPCON3 register can

enable the generation of an interrupt in Slave modes

that do not typically support this function. These bits

will have no effect on slave modes where interrupt on

Start and Stop detect are already enabled.

2

FIGURE 27-4:

I C START AND STOP CONDITIONS

SDA

SCL

S

P

Change of

Data Allowed

Start

Stop

Condition

2

FIGURE 27-5:

I C RESTART CONDITION

Sr

Change of

Data Allowed

Change of

Data Allowed

Restart

Condition

27.3.9 ACKNOWLEDGE SEQUENCE

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSPCON3 register are

clear.

The 9^thSCL pulse for any transferred byte in I²C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDA line low. The transmitter must release control

of the line during this time to shift in the response. The

Acknowledge (ACK) is an active-low signal, pulling the

SDA line low indicates to the transmitter that the

device has received the transmitted data and is ready

to receive more.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSPSTAT register

or the SSPOV bit of the SSPCON1 register are set

when a byte is received, an ACK will not be sent.

When the module is addressed, after the 8^thfalling

edge of SCL on the bus, the ACKTIM bit of the

SSPCON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

The result of an ACK is placed in the ACKSTAT bit of

the SSPCON2 register.

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSPCON2 regis-

ter is set/cleared to determine the response.

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2

27.4.2.2

I C Slave 10-bit Addressing Mode

27.4 I C SLAVE MODE OPERATION

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9

and A8 are the two MSb of the 10-bit address and

stored in bits 2 and 1 of the SSPADDx register.

The MSSP Slave mode operates in one of the four

modes selected in the SSPM bits of SSPCON1

register. The modes can be divided into 7-bit and

10-bit Addressing mode. 10-bit Addressing mode

operates the same as 7-bit, with some additional

overhead for handling the larger addresses.

After the acknowledge of the high byte, the UA bit is

set, and SCL is held low until the user updates

SSPADDx with the low address. The low address byte

is clocked in and all eight bits are compared to the low

address value in SSPADDx. Even if there is no

address match, SSPIF and UA are set, and SCL is

held low until SSPADDx is updated to receive a high

byte again. When SSPADDx is updated, the UA bit is

cleared. This ensures the module is ready to receive

the high address byte on the next communication.

Modes with Start and Stop bit interrupts operate the

same as the other modes. The exception is the SSPIF

bit getting set upon detection of a Start, Restart or Stop

condition.

27.4.1

SLAVE MODE ADDRESSES,

SSPADD

The SSPADD register (Register 27-7) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSPBUF register and an

interrupt is generated. If the value does not match, the

module goes idle and no indication is given to the

software that anything happened.

A high and low address match as a write request is

required at the start of all 10-bit addressing

communication. A transmission can be initiated by

issuing a Restart once the slave is addressed, and

clocking in the high address with the R/W bit set. The

slave hardware will then acknowledge the read

request and prepare to clock out data. This is only

valid for a slave after it has received a complete high

and low address byte match.

The SSPMSK register (Register 27-6) affects the

address matching process. See Section 27.4.10

“SSPMSKx Register” for more information.

27.4.3

SLAVE RECEPTION

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSPSTAT register is cleared.

The received address is loaded into the SSPBUF

register and acknowledged.

27.4.2

SECOND SLAVE MODE ADDRESS,

SSPADD2

The SSPADD2 register (Register 27-9) contains a

second Slave mode address. To enable the use of this

second Slave mode address, bit 0 must be set. The

first byte received after a Start or Restart condition is

compared against the value stored in this register. If

the byte matches, the value is loaded into the

SSPBUF register and an interrupt is generated. If the

value does not match, the module goes Idle and no

indication is given to the software that anything

happened.

When an overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF of the SSPSTAT

register is set, or bit SSPOV of the SSPCON1 register

is set. The BOEN bit of the SSPCON3 register modifies

this operation. For more information, see

Register 27-5.

An MSSP interrupt is generated for each transferred

data byte. Flag bit, SSPIF, must be cleared by software.

The SSPMSK2 register, Register 27-8, affects the

address matching process. See Section 27.4.10

“SSPMSKx Register” for more information.

When the SEN bit of the SSPCON2 register is set, SCL

will be held low (clock stretch) following each received

byte. The clock must be released by setting the CKP

bit of the SSPCON1 register, except sometimes in

10-bit mode.

2

27.4.2.1

I C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

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27.4.3.1

7-bit Addressing Reception

27.4.3.2

7-bit Reception with AHEN and

DHEN

This section describes a standard sequence of events

for the MSSP module configured as an I²C Slave in

7-bit Addressing mode, all decisions made by

hardware or software and their effect on reception.

Figure 27-6 and Figure 27-7 are used as a visual

reference for this description.

Slave device reception with AHEN and DHEN set

operates the same as without these options, with extra

interrupts and clock stretching added after the 8^th

falling edge of SCL. These additional interrupts allow

the slave software to decide whether it wants to ACK

the receive address or data byte, rather than the

hardware. This functionality adds support for PMBus

that was not present on previous versions of this

module.

This is a step-by-step process of what typically must

be done to accomplish I²C communication.

1. Start bit detected.

2. S bit of SSPSTAT is set; SSPIF is set if interrupt

on Start detect is enabled.

This list describes the steps that need to be taken by

slave software to use these options for I²C

communication. Figure 27-8 displays a module using

both address and data holding. Figure 27-9 includes

the operation with the SEN bit of the SSPCON2

register set.

3. Matching address with R/W bit clear is received.

4. The slave pulls SDA low sending an ACK to the

master, and sets SSPIF bit.

5. Software clears the SSPIF bit.

6. Software reads received address from SSPBUF

clearing the BF flag.

1. S bit of SSPSTAT is set; SSPIF is set if interrupt

on Start detect is enabled.

7. If SEN = 1, Slave software sets CKP bit to

2. Matching address with R/W bit clear is clocked

in. SSPIF is set and CKP cleared after the 8^th

falling edge of SCL.

release the SCL line.

8. The master clocks out a data byte.

9. Slave drives SDA low, sending an ACK to the

master, and sets SSPIF bit.

3. Slave clears the SSPIF.

4. Slave can look at the ACKTIM bit of the SSP-

CON3 register to determine if the SSPIF was

after or before the ACK.

10. Software clears SSPIF.

11. Software reads the received byte from SSPBUF

clearing BF.

5. Slave reads the address value from SSPBUF,

clearing the BF flag.

12. Steps 8–12 are repeated for all received bytes

from the Master.

6. Slave sets ACK value clocked out to the master

by setting ACKDT.

13. Master sends Stop condition, setting P bit of

SSPSTAT, and the bus goes Idle.

7. Slave releases the clock by setting CKP.

8. SSPxIF is set after an ACK, not after a NACK.

9. If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSPIF.

Note: SSPIF is still set after the 9th falling edge of

SCL even if there is no clock stretching and

BF has been cleared. Only if NACK is sent

to Master is SSPIF not set.

11. SSPIF set and CKP cleared after 8th falling

edge of SCL for a received data byte.

12. Slave looks at ACKTIM bit of SSPCON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSPBUF

clearing BF.

14. Steps 7–14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK = 1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSTSTAT register.

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27.4.4

SLAVE TRANSMISSION

27.4.4.2

7-bit Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register, and an ACK pulse is

sent by the slave on the ninth bit.

A master device can transmit a read request to a

slave, and then clock data out of the slave. The list

below outlines what software for a slave will need to

do to accomplish

a

standard transmission.

Figure 27-10 can be used as a reference to this list.

Following the ACK, slave hardware clears the CKP bit

and the SCL pin is held low (see Section 27.4.7

“Clock Stretching” for more detail). By stretching the

clock, the master will be unable to assert another clock

pulse until the slave is done preparing the transmit

data.

1. Master sends a Start condition on SDA and

SCL.

2. S bit of SSPSTAT is set; SSPIF is set if interrupt

on Start detect is enabled.

3. Matching address with R/W bit set is received by

the Slave setting SSPIF bit.

The transmit data must be loaded into the SSPBUF

register which also loads the SSPSR register. Then the

SCL pin should be released by setting the CKP bit of

the SSPCON1 register. The eight data bits are shifted

out on the falling edge of the SCL input. This ensures

that the SDA signal is valid during the SCL high time.

4. Slave hardware generates an ACK and sets

SSPIF.

5. SSPIF bit is cleared by user.

6. Software reads the received address from SSP-

BUF, clearing BF.

7. R/W is set so CKP was automatically cleared

after the ACK.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. This ACK

value is copied to the ACKSTAT bit of the SSPCON2

register. If ACKSTAT is set (not ACK), then the data

transfer is complete. In this case, when the not ACK is

latched by the slave, the slave goes Idle and waits for

another occurrence of the Start bit. If the SDA line was

low (ACK), the next transmit data must be loaded into

the SSPBUF register. Again, the SCL pin must be

released by setting bit CKP.

8. The slave software loads the transmit data into

SSPBUF.

9. CKP bit is set releasing SCL, allowing the

master to clock the data out of the slave.

10. SSPIF is set after the ACK response from the

master is loaded into the ACKSTAT register.

11. SSPIF bit is cleared.

12. The slave software checks the ACKSTAT bit to

see if the master wants to clock out more data.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared by software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

Note 1:If the master ACKs the clock will be

stretched.

2: ACKSTAT is the only bit updated on the

rising edge of SCL (9th) rather than the

falling.

27.4.4.1

Slave Mode Bus Collision

13. Steps 9-13 are repeated for each transmitted

byte.

A slave receives a Read request and begins shifting

data out on the SDA line. If a bus collision is detected

and the SBCDE bit of the SSPCON3 register is set, the

BCLIF bit of the PIR register is set. Once a bus collision

is detected, the slave goes Idle and waits to be

addressed again. User software can use the BCLIF bit

to handle a slave bus collision.

14. If the master sends a not ACK; the clock is not

held, but SSPIF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

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27.4.4.3

7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSPCON3 register

enables additional clock stretching and interrupt

generation after the 8^thfalling edge of a received

matching address. Once a matching address has

been clocked in, CKP is cleared and the SSPIF

interrupt is set.

Figure 27-11 displays a standard waveform of a 7-bit

Address Slave Transmission with AHEN enabled.

1. Bus starts Idle.

2. Master sends Start condition; the S bit of

SSPSTAT is set; SSPIF is set if interrupt on Start

detect is enabled.

3. Master sends matching address with R/W bit

set. After the 8^thfalling edge of the SCL line, the

CKP bit is cleared and SSPIF interrupt is

generated.

4. Slave software clears SSPIF.

5. Slave software reads ACKTIM bit of SSPCON3

register, and R/W and D/A of the SSPSTAT

register to determine the source of the interrupt.

6. Slave reads the address value from the

SSPBUF register clearing the BF bit.

7. Slave software decides from this information if it

wishes to ACK or not ACK and sets ACKDT bit

of the SSPCON2 register accordingly.

8. Slave sets the CKP bit releasing SCL.

9. Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit

and sets SSPIF after the ACK if the R/W bit is

set.

11. Slave software clears SSPIF.

12. Slave loads value to transmit to the master into

SSPBUF setting the BF bit.

Note: SSPBUF cannot be loaded until after the

ACK.

13. Slave sets CKP bit releasing the clock.

14. Master clocks out the data from the slave and

sends an ACK value on the 9^thSCL pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSPCON2 register.

16. Steps 10–15 are repeated for each byte

transmitted to the master from the slave.

17. If the master sends a not ACK, the slave

releases the bus, allowing the master to send a

Stop and end the communication.

Note: Master must send a not ACK on the last byte

to ensure that the slave releases the SCL

line to receive a Stop.

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27.4.5

SLAVE MODE 10-BIT ADDRESS

RECEPTION

27.4.6

10-BIT ADDRESSING WITH

ADDRESS OR DATA HOLD

This section describes a standard sequence of events

for the MSSP module configured as an I²C Slave in

10-bit Addressing mode.

Reception using 10-bit addressing with AHEN or DHEN

set is the same as with 7-bit modes. The only difference

is the need to update the SSPADDx register using the

UA bit. All functionality, specifically when the CKP bit is

cleared and SCL line is held low, are the same.

Figure 27-13 can be used as a reference of a slave in

10-bit addressing with AHEN set.

Figure 27-12 is used as a visual reference for this

description.

This is a step-by-step process of what must be done

by slave software to accomplish I²C communication.

Figure 27-14 shows a standard waveform for a slave

transmitter in 10-bit Addressing mode.

1. Bus starts Idle.

2. Master sends Start condition; S bit of SSPSTAT

is set; SSPIF is set, if interrupt on Start detect is

enabled.

3. Master sends matching high address with R/W

bit clear; UA bit of the SSPSTAT register is set.

4. Slave sends ACK and SSPIF is set.

5. Software clears the SSPIF bit.

6. Software reads received address from SSPBUF

clearing the BF flag.

7. Slave loads low address into SSPADDx,

releasing SCL.

8. Master sends matching low-address byte to the

Slave; UA bit is set.

Note:

Updates to the SSPADDx register are not

allowed until after the ACK sequence.

9. Slave sends ACK and SSPIF is set.

Note: If the low address does not match, SSPIF

and UA are still set so that the slave soft-

ware can set SSPADDx back to the high

address. BF is not set because there is no

match. CKP is unaffected.

10. Slave clears SSPIF.

11. Slave reads the received matching address

from SSPBUF clearing BF.

12. Slave loads high address into SSPADD.

13. Master clocks a data byte to the slave and

clocks out the slave’s ACK on the 9th SCL

pulse; SSPIF is set.

14. If SEN bit of SSPCON2 is set, CKP is cleared by

hardware and the clock is stretched.

15. Slave clears SSPIF.

16. Slave reads the received byte from SSPBUF

clearing BF.

17. If SEN is set, the slave sets CKP to release the

SCL.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

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27.4.7

CLOCK STRETCHING

27.4.7.2

10-bit Addressing Mode

Clock stretching occurs when a device on the bus holds

the SCL line low, effectively pausing communication.

The slave may stretch the clock to allow more time to

handle data or prepare a response for the master

device. A master device is not concerned with

stretching, as anytime it is active on the bus and not

transferring data, it is stretching. Any stretching done

by a slave is invisible to the master software and

handled by the hardware that generates SCL.

In 10-bit Addressing mode, when the UA bit is set, the

clock is always stretched. This is the only time the SCL

is stretched without CKP being cleared. SCL is

released immediately after a write to SSPADDx.

Note: Previous versions of the module did not

stretch the clock if the second address byte

did not match.

27.4.7.3

Byte NACKing

The CKP bit of the SSPCON1 register is used to control

stretching in software. Any time the CKP bit is cleared,

the module will wait for the SCL line to go low and then

hold it. Setting CKP will release SCL and allow more

communication.

When AHEN bit of SSPCON3 is set; CKP is cleared by

the hardware after the 8^thfalling edge of SCL for a

received matching address byte. When DHEN bit of

SSPCON3 is set; CKP is cleared after the 8^thfalling

edge of SCL for received data.

Stretching after the 8^thfalling edge of SCL allows the

slave to look at the received address or data and

decide if it wants to ACK the received data.

27.4.7.1

Normal Clock Stretching

Following an ACK, if the R/W bit of the SSPSTAT is

set, causing a read request, the slave hardware will

clear CKP. This allows the slave time to update

SSPBUF with data to transfer to the master. If the SEN

bit of SSPCON2 is set, the slave hardware will always

stretch the clock after the ACK sequence. Once the

slave is ready; CKP is set by software and

communication resumes.

27.4.8

CLOCK SYNCHRONIZATION AND

THE CKP BIT

Any time the CKP bit is cleared, the module will wait for

the SCL line to go low and then hold it. However,

clearing the CKP bit will not assert the SCL output low

until the SCL output is already sampled low. Therefore,

the CKP bit will not assert the SCL line until an external

I²C master device has already asserted the SCL line.

The SCL output will remain low until the CKP bit is set

and all other devices on the I²C bus have released

SCL. This ensures that a write to the CKP bit will not

violate the minimum high time requirement for SCL

(see Figure 27-15).

Note 1: The BF bit has no effect on if the clock will

be stretched or not. This is different than

previous versions of the module that

would not stretch the clock or clear CKP,

if SSPBUF was read before the 9^thfalling

edge of SCL.

2: Previous versions of the module did not

stretch the clock for a transmission if

SSPBUF was loaded before the 9^thfalling

edge of SCL. It is now always cleared for

read requests.

FIGURE 27-15:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX ‚ – 1

Master device

asserts clock

CKP

Master device

releases clock

WR

SSPCON1

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In 10-bit Address mode, the UA bit will not be set on the

reception of the general call address. The slave will

prepare to receive the second byte as data, just as it

would in the 7-bit mode.

27.4.9

GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I²C bus is such that

the first byte after the Start condition usually

determines which device will be the slave addressed by

the master device. The exception is the general call

address, which can address all devices. When this

address is used, all devices should, in theory, respond

with an acknowledge.

If the AHEN bit of the SSPCON3 register is set, just as

with any other address reception, the slave hardware

will stretch the clock after the 8^thfalling edge of SCL.

The slave must then set its ACKDT value and release

the clock with communication progressing as it would

normally.

The general call address is a reserved address in the

I²C protocol, defined as address 0x00. When the

GCEN bit of the SSPCON2 register is set, the slave

module will automatically ACK the reception of this

address, regardless of the value stored in SSPADDx.

After the slave clocks in an address of all zeros with the

R/W bit clear, an interrupt is generated and slave

software can read SSPBUF and respond. Figure 27-16

shows a general call reception sequence.

FIGURE 27-16:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address

after ACK, set interrupt

Receiving Data

ACK

R/W = 0

ACK

General Call Address

SDA

SCL

D7 D6 D5 D4 D3 D2 D1 D0

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

S

SSPIF

BF (SSPSTAT<0>)

Cleared by software

SSPBUF is read

GCEN (SSPCON2<7>)

’1’

27.4.10 SSPMSKX REGISTER

An SSP Mask (SSPMSKx) register (Register 27-6 and

Register 27-8) is available in I²C Slave mode as a

mask for the value held in the SSPSRx register during

an address comparison operation. A zero (‘0’) bit in the

SSPMSKx register has the effect of making the

corresponding bit of the received address a “don’t

care”.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSP operation until written with a mask value.

The SSP Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0>

only. The SSP mask has no effect during the

reception of the first (high) byte of the address.

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27.5 I²C Master Mode

27.5.1

I C MASTER MODE OPERATION

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I²C bus will

not be released.

Master mode is enabled by setting and clearing the

appropriate SSPM bits in the SSPCON1 register and

by setting the SSPEN bit. In Master mode, the SDA and

SCK pins must be configured as inputs. The MSSP

peripheral hardware will override the output driver TRIS

controls when necessary, to drive the pins low.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted eight bits at a time. After each byte is trans-

mitted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset or when the MSSP module is disabled.

Control of the I²C bus may be taken when the P bit is

set, or the bus is Idle.

In Firmware Controlled Master mode, user code

conducts all I²C bus operations based on Start and

Stop bit condition detection. Start and Stop condition

detection is the only active circuitry in this mode. All

other communication is done by the user software

directly manipulating the SDA and SCL lines.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received eight bits at a time.

After each byte is received, an Acknowledge bit is

transmitted. Start and Stop conditions indicate the

beginning and the end of transmission.

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP interrupt, if enabled):

• Start condition detected

• Stop condition detected

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

A Baud Rate Generator is used to set the clock

frequency output on SCL. See Section 27.6 “Baud

Rate Generator” for more detail.

Note 1: The MSSP module, when configured in

I²C Master mode, does not allow queuing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

initiate transmission before the Start

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a

write to the SSPBUF did not occur.

27.5.2

CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

releases the SCL pin (SCL allowed to float high). When

the SCL pin is allowed to float high, the Baud Rate

Generator (BRG) is suspended from counting until the

SCL pin is actually sampled high. When the SCL pin is

sampled high, the Baud Rate Generator is reloaded

with the contents of SSPADD<7:0> and begins

counting. This ensures that the SCL high time will

always be at least one BRG rollover count in the event

that the clock is held low by an external device

(Figure 27-17).

2: When in Master mode, Start/Stop

detection is masked and an interrupt is

generated when the SEN/PEN bit is

cleared and the generation is complete.

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FIGURE 27-17:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

DX DX ‚ – 1

SDA

SCL deasserted but slave holds

SCL low (clock arbitration)

SCL allowed to transition high

SCL

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count

BRG

Reload

of the SDA being driven low while SCL is high is the

Start condition and causes the S bit of the SSPSTAT

register to be set. Following this, the Baud Rate

Generator is reloaded with the contents of

SSPADD<7:0> and resumes its count. When the Baud

Rate Generator times out (T_BRG), the SEN bit of the

SSPCON2 register will be automatically cleared by

hardware; the Baud Rate Generator is suspended,

leaving the SDA line held low and the Start condition is

complete.

27.5.3

WCOL STATUS FLAG

If the user writes the SSPBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL is set and the contents of the buffer are

unchanged (the write does not occur). Any time the

WCOL bit is set, it indicates that an action on SSPBUF

was attempted while the module was not Idle.

Note:

Because queuing of events is not allowed,

writing to the lower five bits of SSPCON2

is disabled until the Start condition is

complete.

Note 1: If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start condition,

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLIF, is set, the Start condition is

aborted and the I²C module is reset into

its Idle state.

2

27.5.4

I C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN bit of the SSPCON2 register. If the

SDA and SCL pins are sampled high, the Baud Rate

Generator is reloaded with the contents of

SSPADD<7:0> and starts its count. If SCL and SDA

are both sampled high when the Baud Rate Generator

times out (T_BRG), the SDA pin is driven low. The action

2: The Philips I²C Specification states that a

bus collision cannot occur on a Start.

FIGURE 27-18:

FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

Write to SEN bit occurs here

At completion of Start bit,

hardware clears SEN bit

and sets SSPIF bit

SDA = 1,

SCL = 1

T_BRG

Write to SSPBUF occurs here

2^ndbit

1^stbit

T_BRG

SDA

SCL

S

T_BRG

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27.5.5

I C MASTER MODE REPEATED

START CONDITION TIMING

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

A Repeated Start condition occurs when the RSEN bit

of the SSPCON2 register is programmed high and the

Master state machine is no longer active. When the

RSEN bit is set, the SCL pin is asserted low. When the

SCL pin is sampled low, the Baud Rate Generator is

loaded and begins counting. The SDA pin is released

(brought high) for one Baud Rate Generator count

(T_BRG). When the Baud Rate Generator times out, if

SDA is sampled high, the SCL pin will be deasserted

(brought high). When SCL is sampled high, the Baud

Rate Generator is reloaded and begins counting. SDA

and SCL must be sampled high for one T_BRG. This

action is then followed by the assertion of the SDA pin

(SDA = 0) for one T_BRGwhile SCL is high. SCL is

asserted low. Following this, the RSEN bit of the SSP-

CON2 register will be automatically cleared and the

Baud Rate Generator will not be reloaded, leaving the

SDA pin held low. As soon as a Start condition is

detected on the SDA and SCL pins, the S bit of the

SSPSTAT register will be set. The SSPIF bit will not be

set until the Baud Rate Generator has timed out.

2: A bus collision during the Repeated Start

condition occurs if:

•SDA is sampled low when SCL goes

from low-to-high.

•SCL goes low before SDA is

asserted low. This may indicate

that another master is attempting to

transmit a data ‘1’.

FIGURE 27-19:

REPEAT START CONDITION WAVEFORM

S bit set by hardware

Write to SSPCON2

occurs here

SDA = 1,

At completion of Start bit,

hardware clears RSEN bit

and sets SSPIF

SDA = 1,

SCL = 1

SCL (no change)

T_BRG

1st bit

SDA

SCL

Write to SSPBUF occurs here

T_BRG

Sr

Repeated Start

T_BRG

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27.5.6

I C MASTER MODE

TRANSMISSION

27.5.6.2

WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the

buffer are unchanged (the write does not occur).

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the Buffer Full flag bit, BF, and will allow the Baud

Rate Generator to begin counting and start the next

transmission. Each bit of address/data will be shifted

out onto the SDA pin after the falling edge of SCL is

asserted. SCL is held low for one Baud Rate Generator

rollover count (T_BRG). Data should be valid before SCL

is released high. When the SCL pin is released high, it

is held that way for T_BRG. The data on the SDA pin must

remain stable for that duration and some hold time after

the next falling edge of SCL. After the 8^thbit is shifted

out (the falling edge of the 8^thclock), the BF flag is

cleared and the master releases the SDA. This allows

the slave device being addressed to respond with an

ACK bit during the 9^thbit time if an address match

occurred, or if data was received properly. The status of

ACK is written into the ACKSTAT bit on the rising edge

of the 9^thclock. If the master receives an Acknowledge,

the Acknowledge Status bit, ACKSTAT, is cleared. If

not, the bit is set. After the 9^thclock, the SSPIF bit is set

and the master clock (Baud Rate Generator) is

suspended until the next data byte is loaded into the

SSPBUF, leaving SCL low and SDA unchanged

(Figure 27-20).

WCOL must be cleared by software before the next

transmission.

27.5.6.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSPCON2

register is cleared when the slave has sent an

Acknowledge (ACK = 0) and is set when the slave

does not Acknowledge (ACK = 1). A slave sends an

Acknowledge when it has recognized its address

(including a general call), or when the slave has

properly received its data.

27.5.6.4

Typical transmit sequence

1. The user generates a Start condition by setting

the SEN bit of the SSPCON2 register.

2. SSPIF is set by hardware on completion of the

Start.

3. SSPIF is cleared by software.

4. The MSSP module will wait the required start

time before any other operation takes place.

5. The user loads the SSPBUF with the slave

address to transmit.

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the 8^thclock, the master will release

the SDA pin, allowing the slave to respond with an

Acknowledge. On the falling edge of the 9^thclock, the

master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT Status bit of the SSPCON2

register. Following the falling edge of the 9^thclock

transmission of the address, the SSPIF is set, the BF

flag is cleared and the Baud Rate Generator is turned

off until another write to the SSPBUF takes place,

holding SCL low and allowing SDA to float.

6. Address is shifted out the SDA pin until all eight

bits are transmitted. Transmission begins as

soon as SSPBUF is written to.

7. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPCON2 register.

8. The MSSP module generates an interrupt at the

end of the 9^thclock cycle by setting the SSPIF

bit.

9. The user loads the SSPBUF with eight bits of

data.

10. Data is shifted out the SDA pin until all eight bits

are transmitted.

11. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPCON2 register.

27.5.6.1

BF Status Flag

In Transmit mode, the BF bit of the SSPSTAT register

is set when the CPU writes to SSPBUF, and is cleared

when all eight bits are shifted out.

12. Steps 8–11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits of the SSP-

CON2 register. Interrupt is generated once the

Stop/Restart condition is complete.

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27.5.7

I C MASTER MODE RECEPTION

27.5.7.4

Typical Receive Sequence:

Master mode reception is enabled by programming the

Receive Enable bit, RCEN bit, of the SSPCON2

register.

1. The user generates a Start condition by setting

the SEN bit of the SSPCON2 register.

2. SSPIF is set by hardware on completion of the

Start.

Note:

The MSSP module must be in an Idle

state before the RCEN bit is set, or the

RCEN bit will be disregarded.

3. SSPIF is cleared by software.

4. The user writes SSPBUF with the slave address

to transmit and the R/W bit set.

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes (high-to-

low/low-to-high) and data is shifted into the SSPSR.

After the falling edge of the eighth clock, the receive

enable flag is automatically cleared, the contents of the

SSPSR are loaded into the SSPBUF, the BF flag bit is

set, the SSPIF flag bit is set and the Baud Rate Gener-

ator is suspended from counting, holding SCL low. The

MSSP is now in Idle state awaiting the next command.

When the buffer is read by the CPU, the BF flag bit is

automatically cleared. The user can then send an

Acknowledge bit at the end of reception by setting the

Acknowledge Sequence Enable, ACKEN bit, of the

SSPCON2 register.

5. Address is shifted out the SDA pin until all eight

bits are transmitted. Transmission begins as

soon as SSPBUF is written to.

6. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPCON2 register.

7. The MSSP module generates an interrupt at the

end of the 9^thclock cycle by setting the SSPIF

bit.

8. User sets the RCEN bit of the SSPCON2 register

and the Master clocks in a byte from the slave.

9. After the 8^thfalling edge of SCL, SSPIF and BF

are set.

10. Master clears SSPIF and reads the received

byte from SSPBUF, clears BF.

27.5.7.1

BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

11. Master sets ACK value sent to slave in ACKDT

bit of the SSPCON2 register and initiates the

ACK by setting the ACKEN bit.

12. Masters ACK is clocked out to the Slave and

SSPIF is set.

27.5.7.2

SSPOV Status Flag

In receive operation, the SSPOV bit is set when eight

bits are received into the SSPSR and the BF flag bit is

already set from a previous reception.

13. The user clears SSPIF.

14. Steps 8–13 are repeated for each received byte

from the slave.

27.5.7.3

WCOL Status Flag

15. Master sends a not ACK or Stop to end

communication.

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write does not occur).

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27.5.8

ACKNOWLEDGE SEQUENCE

TIMING

27.5.9

STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN bit of the SSPCON2 register. At the end of a

receive/transmit, the SCL line is held low after the

falling edge of the 9^thclock. When the PEN bit is set,

the master will assert the SDA line low. When the SDA

line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCL pin will be brought high

and one T_BRG(Baud Rate Generator rollover count)

later, the SDA pin will be deasserted. When the SDA

pin is sampled high while SCL is high, the P bit of the

SSPSTAT register is set. A T_BRGlater, the PEN bit is

cleared and the SSPIF bit is set (Figure 27-23).

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit, of the

SSPCON2 register. When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (T_BRG

)

and the SCL pin is deasserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the Baud

Rate Generator counts for T_BRG. The SCL pin is then

pulled low. Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP module then goes into Idle mode (Figure 27-22).

27.5.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write does

not occur).

27.5.8.1

WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write does

not occur).

FIGURE 27-22:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

ACKEN automatically cleared

write to SSPCON2

ACKEN = 1, ACKDT = 0

T_BRG

ACK

T_BRG

SDA

SCL

D0

8

9

SSPIF

Cleared in

SSPIF set at

software

Cleared in

software

the end of receive

SSPIF set at the end

of Acknowledge sequence

Note:

T_BRG= one Baud Rate Generator period.

FIGURE 27-23:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1for T_BRG, followed by SDA = 1for T_BRG

Write to SSPCON2,

set PEN

after SDA sampled high. P bit (SSPSTAT<4>) is set.

Falling edge of

9th clock

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

T_BRG

SCL

ACK

SDA

P

T_BRG

SCL brought high after T_BRG

SDA asserted low before rising edge of clock

to setup Stop condition

Note:

T_BRG= one Baud Rate Generator period.

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27.5.10 SLEEP OPERATION

27.5.13 MULTI-MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

While in Sleep mode, the I²C slave module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wakes the processor

from Sleep (if the MSSP interrupt is enabled).

Multi-Master mode support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the

master outputs a ‘1’ on SDA, by letting SDA float high

and another master asserts a ‘0’. When the SCL pin

floats high, data should be stable. If the expected data

on SDA is a ‘1’ and the data sampled on the SDA pin is

‘0’, then a bus collision has taken place. The master will

set the Bus Collision Interrupt Flag, BCLIF and reset

the I²C port to its Idle state (Figure 27-24).

27.5.11 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

27.5.12 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSPx module is disabled. Control of the I²C bus may

be taken when the P bit of the SSPSTAT register is set,

or the bus is Idle, with both the S and P bits clear. When

the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSPBUF can be written to. When the user services the

bus collision Interrupt Service Routine and if the I²C

bus is free, the user can resume communication by

asserting a Start condition.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed by

hardware with the result placed in the BCLIF bit.

If a Start, Repeated Start, Stop or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are deasserted and the respective control bits in

the SSPCON2 register are cleared. When the user

services the bus collision Interrupt Service Routine and

if the I²C bus is free, the user can resume

communication by asserting a Start condition.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be set.

• A Repeated Start Condition

• An Acknowledge Condition

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the deter-

mination of when the bus is free. Control of the I²C bus

can be taken when the P bit is set in the SSPSTAT

register, or the bus is Idle and the S and P bits are

cleared.

FIGURE 27-24:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,

data does not match what is driven

by the master.

SDA line pulled low

by another source

Data changes

while SCL = 0

Bus collision has occurred.

SDA released

by master

SDA

Set bus collision

interrupt (BCLIF)

SCL

BCLIF

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If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 27-27). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to zero; if the SCL pin is sampled as ‘0’

during this time, a bus collision does not occur. At the

end of the BRG count, the SCL pin is asserted low.

27.5.13.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 27-25).

b) SCL is sampled low before SDA is asserted low

(Figure 27-26).

During a Start condition, both the SDA and the SCL

pins are monitored.

Note:

The reason that bus collision is not a

factor during a Start condition is that no

two bus masters can assert a Start

condition at the exact same time.

Therefore, one master will always assert

SDA before the other. This condition does

not cause a bus collision because the two

masters must be allowed to arbitrate the

first address following the Start condition.

If the address is the same, arbitration

must be allowed to continue into the data

portion, Repeated Start or Stop

conditions.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted

• the BCLIF flag is set

•

the MSSP module is reset to its Idle state

(Figure 27-25).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded and counts down. If the

SCL pin is sampled low while SDA is high, a bus

collision occurs because it is assumed that another

master is attempting to drive a data ‘1’ during the Start

condition.

FIGURE 27-25:

BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF,

S bit and SSPIF set because

SDA = 0, SCL = 1.

SDA

SCL

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SEN cleared automatically because of bus collision.

SSP module reset into Idle state.

SEN

SDA sampled low before

Start condition. Set BCLIF.

S bit and SSPIF set because

SDA = 0, SCL = 1.

BCLIF

SSPIF and BCLIF are

cleared by software

S

SSPIF

SSPIF and BCLIF are

cleared by software

DS20002331D-page 178

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FIGURE 27-26:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

T_BRG

SDA

SCL

SEN

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

SCL = 0before SDA = 0,

bus collision occurs. Set BCLIF.

SCL = 0before BRG time-out,

bus collision occurs. Set BCLIF.

BCLIF

Interrupt cleared

by software

S

’0’

SSPIF

FIGURE 27-27:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1

Set S

Set SSPIF

Less than T_BRG

T_BRG

SDA

SCL

SDA pulled low by other master.

Reset BRG and assert SDAx.

S

SCLx pulled low after BRG

time-out

SEN

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

’0’

BCLIF

S

SSPIF

Interrupts cleared

by software

SDAx = 0, SCL = 1,

set SSPIF

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If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 27-28).

If SDA is sampled high, the BRG is reloaded and begins

counting. If SDA goes from high-to-low before the BRG

times out, no bus collision occurs because no two

masters can assert SDA at exactly the same time.

27.5.13.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

If SCL goes from high-to-low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated Start condition

(see Figure 27-29.)

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

When the user releases SDA and the pin is allowed to

float high, the BRG is loaded with SSPADD and counts

down to zero. The SCL pin is then deasserted and

when sampled high, the SDA pin is sampled.

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

FIGURE 27-28:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

RSEN

BCLIF

Cleared by software

’0’

S

’0’

SSPIF

FIGURE 27-29:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

T_BRG

SDA

SCL

SCL goes low before SDA,

set BCLIF. Release SDA and SCL.

BCLIF

RSEN

Interrupt cleared

by software

’0’

S

SSPIF

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The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSPADD and

counts down to 0. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 27-30). If the SCL pin is sampled

low before SDA is allowed to float high, a bus collision

occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 27-31).

27.5.13.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high.

FIGURE 27-30:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

T_BRG

low after T_BRG

,

set BCLIF

SDA

SDA asserted low

SCL

PEN

BCLIF

P

’0’

SSPIF

FIGURE 27-31:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

T_BRG

SDA

SCL goes low before SDA goes high,

set BCLIF

Assert SDA

SCL

PEN

BCLIF

P

’0’

SSPIF

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2

TABLE 27-1: SUMMARY OF REGISTERS ASSOCIATED WITH I C OPERATION

Reset

Values on

Page:

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

—

PEIE

ADIE

T0IE

BCLIE

BCLIF

TRISA5

TRISB5

ADD5

INTE

SSPIE

SSPIF

IOCE

—

T0IF

—

INTF

IOCF

95

96

TMR2IE TMR1IE

TMR2IF TMR1IF

PIR1

—

ADIF

—

98

TRISGPA

TRISGPB

SSPADD

SSPBUF

SSPCON1

SSPCON2

TRISA7

TRISB7

ADD7

TRISA6

TRISB6

ADD6

TRISA4 TRISA3 TRISA2

TRISB4 TRISB3 TRISB2

TRISA1

TRISB1

ADD1

TRISA0

TRISB0

ADD0

114

117

188

148*

185

186

187

188

184

189

ADD4

ADD3

ADD2

Synchronous Serial Port Receive Buffer/Transmit Register

WCOL

GCEN

SSPOV

SSPEN

CKP

ACKEN

BOEN

MSK4

P

SSPM3 SSPM2

RCEN PEN

SDAHT SBCDE

SSPM1

RSEN

AHEN

MSK1

UA

SSPM0

SEN

ACKSTAT ACKDT

SSPCON3 ACKTIM

PCIE

MSK6

CKE

SCIE

MSK5

D/A

DHEN

MSK0

BF

SSPMSK

SSPSTAT

SSPMSK2

SSPADD2

MSK7

SMP

MSK3

S

MSK2

R/W

MSK27

ADD27

MSK26

ADD26

MSK25

ADD25

MSK24

MSK23

MSK22

MSK21

MSK20

ADD24

ADD23

ADD22

ADD21

ADD20

Legend: —= unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I²C mode.

*

Page provides register information.

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An internal signal “Reload” in Figure 27-32 triggers the

value from SSPADD to be loaded into the BRG counter.

This occurs twice for each oscillation of the module

clock line. The logic dictating when the reload signal is

asserted depends on the mode the MSSP is being

operated in.

27.6 BAUD RATE GENERATOR

The MSSP module has a Baud Rate Generator

available for clock generation in I²C Master mode. The

Baud Rate Generator (BRG) reload value is placed in

the SSPADD register (Register 27-7). When a write

occurs to SSPBUF, the Baud Rate Generator will

automatically begin counting down.

Table 27-2 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

Once the given operation is complete, the internal clock

will automatically stop counting and the clock pin will

remain in its last state.

EQUATION 27-1:

F

OSC

----------------------------------------------

F

=

CLOCK

SSPADD + 14

FIGURE 27-32:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0>

SSPADD<7:0>

SSPM<3:0>

SCL

Reload

Control

Reload

BRG Down Counter

F_OSC/2

SSPCLK

Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPADD when used as a Baud Rate

Generator for I²C. This is an implementation

limitation.

TABLE 27-2: MSSP CLOCK RATE W/BRG

F_CLOCK

(2 Rollovers of BRG)

F_OSC

F_CY

BRG Value

8 MHz

2 MHz

04h

0Bh

13h

400 kHz⁽¹⁾

166 kHz

100 kHz

Note 1: The I²C interface does not conform to the 400 kHz I²C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

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REGISTER 27-2: SSPSTAT: SSP STATUS REGISTER

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

SMP: Data Input Sample bit

1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for high speed mode (400 kHz)

CKE: Clock Edge Select bit

1= Enable input logic so that thresholds are compliant with SMBus specification

0= Disable SMBus specific inputs

D/A: Data/Address bit

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

P: Stop bit

(This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0= Stop bit was not detected last

bit 3

bit 2

S: Start bit

(This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0= Start bit was not detected last

R/W: Read/Write bit information

This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit, or not ACK bit.

In I²C Slave mode:

1= Read

0= Write

In I²C Master mode:

1= Transmit is in progress

0= Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.

bit 1

bit 0

UA: Update Address bit (10-bit I²C mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

Receive:

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Transmit:

1= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full

0= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

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REGISTER 27-3: SSPCON1: SSP CONTROL REGISTER 1

R/C/HS-0

WCOL

R/C/HS-0

SSPOV

R/W-0

CKP

R/W-0

bit 0

SSPEN

SSPM<3:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

HS = Bit is set by hardware

C = User cleared

bit 7

WCOL: Write Collision Detect bit

Master mode:

1= A write to the SSPBUF register was attempted while the I²C conditions were not valid for a

transmission to be started

0= No collision

Slave mode:

1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)

0= No collision

bit 6

bit 5

bit 4

SSPOV: Receive Overflow Indicator bit ⁽¹⁾

1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t

care” in Transmit mode (must be cleared in software).

0= No overflow

SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output

1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins ⁽²⁾

0= Disables serial port and configures these pins as I/O port pins

CKP: Clock Polarity Select bit

In I²C Slave mode:

SCL release control

1= Enable clock

0= Holds clock low (clock stretch). (Used to ensure data setup time.)

In I²C Master mode:

Unused in this mode

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000= Reserved

0001= Reserved

0010= Reserved

0011= Reserved

0100= Reserved

0101= Reserved

0110= I²C Slave mode, 7-bit address

0111= I²C Slave mode, 10-bit address

1000= I²C Master mode, clock = F_OSC/(4 x (SSPADD+1))⁽³⁾

1001= Reserved

1010= Reserved

1011= I²C firmware controlled Master mode (Slave idle)

1100= Reserved

1101= Reserved

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPBUF register.

2: When enabled, the SDA and SCL pins must be configured as inputs.

3: SSPADD values of 0, 1 or 2 are not supported for I²C Mode.

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REGISTER 27-4: SSPCON2: SSP CONTROL REGISTER 2

R/W-0/0

GCEN

R-0/0

R/W-0/0

ACKDT

R/S/HS-0/0 R/S/HS-0/0

ACKEN RCEN

R/S/HS-0/0

PEN

R/S/HS-0/0 R/W/HS-0/0

RSEN SEN

bit 0

ACKSTAT

bit 7

Legend:

R = Readable bit

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

S = User set

H = Bit is set by hardware

-n/n = Value at POR/Value at all other resets

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (in I²C Slave mode only)

1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit

1= Acknowledge was not received

0= Acknowledge was received

ACKDT: Acknowledge Data bit

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1= Not Acknowledge

0= Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit (in I²C Master mode only)

In Master Receive mode:

1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence Idle

bit 3

bit 2

RCEN: Receive Enable bit (in I²C Master mode only)

1= Enables Receive mode for I²C

0= Receive Idle

PEN: Stop Condition Enable bit (in I²C Master mode only)

SCK Release Control:

1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0= Stop condition Idle

bit 1

bit 0

RSEN: Repeated Start Condition Enabled bit (in I²C Master mode only)

1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Repeated Start condition Idle

SEN: Start Condition Enabled bit (in I²C Master mode only)

In Master mode:

1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Start condition Idle

In Slave mode:

1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0= Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the Idle mode, this bit may not be

set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

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MCP19110/11

REGISTER 27-5: SSPCON3: SSP CONTROL REGISTER 3

R-0/0

R/W-0/0

PCIE

R/W-0/0

SCIE

R/W-0/0

BOEN

R/W-0/0

SDAHT

R/W-0/0

SBCDE

R/W-0/0

AHEN

R/W-0/0

DHEN

ACKTIM

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n/n = Value at POR/Value at ‘1’ = Bit is set

all other resets

bit 7

bit 6

bit 5

bit 4

ACKTIM: Acknowledge Time Status bit⁽²⁾

1= Indicates the I²C bus is in an Acknowledge sequence, set on the 8^thfalling edge of SCL clock

0= Not an Acknowledge sequence, cleared on the 9^thrising edge of SCL clock

PCIE: Stop Condition Interrupt Enable bit

1= Enable interrupt on detection of Stop condition

0= Stop detection interrupts are disabled⁽¹⁾

SCIE: Start Condition Interrupt Enable bit

1= Enable interrupt on detection of Start or Restart conditions

0= Start detection interrupts are disabled⁽¹⁾

BOEN: Buffer Overwrite Enable bit

In I²C Master mode:

This bit is ignored.

In I²C Slave mode:

1= SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state

of the SSPOV bit only if the BF bit = 0.

0= SSPBUF is only updated when SSPOV is clear

bit 3

bit 2

SDAHT: SDA Hold Time Selection bit

1= Minimum of 300 ns hold time on SDA after the falling edge of SCL

0= Minimum of 100 ns hold time on SDA after the falling edge of SCL

SBCDE: Slave Mode Bus Collision Detect Enable bit (I²C Slave mode only)

If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF

bit of the PIR2 register is set, and bus goes Idle

1= Enable slave bus collision interrupts

0= Slave bus collision interrupts are disabled

bit 1

bit 0

AHEN: Address Hold Enable bit (I²C Slave mode only)

1= Following the 8^thfalling edge of SCL for a matching received address byte; CKP bit of the SSP-

CON1 register will be cleared and the SCL will be held low.

0= Address holding is disabled

DHEN: Data Hold Enable bit (I²C Slave mode only)

1= Following the 8^thfalling edge of SCL for a received data byte; slave hardware clears the CKP bit

of the SSPCON1 register and SCL is held low.

0= Data holding is disabled

Note 1: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

2: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

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MCP19110/11

REGISTER 27-6: SSPMSK: SSP MASK REGISTER 1

R/W-1

MSK<7:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

bit 0

MSK<7:1>: Mask bits

1= The received address bit n is compared to SSPADD<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

MSK<0>: Mask bit for I²C Slave mode, 10-bit Address

I²C Slave mode, 10-bit address (SSPM<3:0> = 0111or 1111):

1= The received address bit 0 is compared to SSPADD<0> to detect I²C address match

0= The received address bit 0 is not used to detect I²C address match

I²C Slave mode, 7-bit address, the bit is ignored

REGISTER 27-7: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER 1

R/W-0

ADD<7:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Master mode:

bit 7-0

ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) x 4)/F_OSC

10-Bit Slave mode — Most Significant Address byte:

bit 7-3

Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit

pattern sent by master is fixed by I²C specification and must be equal to ‘11110’. However, those bits

are compared by hardware and are not affected by the value in this register.

bit 2-1

bit 0

ADD<2:1>: Two Most Significant bits of 10-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

10-Bit Slave mode — Least Significant Address byte:

bit 7-0

ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1

bit 0

ADD<7:1>: 7-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

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MCP19110/11

REGISTER 27-8: SSPMSK2: SSP MASK REGISTER 2

R/W-1

MSK2<7:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

bit 0

MSK2<7:1>: Mask bits

1= The received address bit n is compared to SSPADD2<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

MSK2<0>: Mask bit for I²C Slave mode, 10-bit Address

I²C Slave mode, 10-bit address (SSPM<3:0> = 0111or 1111):

1= The received address bit 0 is compared to SSPADD2<0> to detect I²C address match

0= The received address bit 0 is not used to detect I²C address match

I²C Slave mode, 7-bit address, the bit is ignored

REGISTER 27-9: SSPADD2: MSSP ADDRESS 2

R/W-0

ADD2<7:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Master mode:

bit 7-0

ADD2<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC

10-Bit Slave mode — Most Significant Address byte:

bit 7-3

Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit

pattern sent by master is fixed by I²C specification and must be equal to ‘11110’. However, those bits

are compared by hardware and are not affected by the value in this register.

bit 2-1

bit 0

ADD2<2:1>: Two Most Significant bits of 10-bit address

ADD2<0>: SSPADD2 Enable bit.

1= Enable address matching with SSPADD2

0= Disable address matching with SSPADD2

10-Bit Slave mode — Least Significant Address byte:

bit 7-0

ADD2<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1

bit 0

ADD2<7:1>: 7-bit address

ADD2<0>: SSPADD2 Enable bit.

1= Enable address matching with SSPADD2

0= Disable address matching with SSPADD2

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MCP19110/11

NOTES:

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MCP19110/11

28.1 Common Programming Interfaces

28.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

Connection to a target device is typically done through

an ICSP header. A commonly found connector on

development tools is the RJ-11 in the 6P6C (6 pin,

6 connector) configuration. See Figure 28-1.

ICSP programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process, allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP

programming:

FIGURE 28-1:

ICD RJ-11 STYLE

CONNECTOR INTERFACE

• ICSPCLK

• ICSPDAT

• MCLR

• V_DD

ICSPDAT

• V_SS

NC

2 4 6

V_DD

ICSPCLK

In Program/Verify mode, the Program Memory, User IDs

and the Configuration Words are programmed through

1 3

5

Target

PC Board

Bottom Side

MCLR

serial communications. The ICSPDAT pin is

a

V_SS

bidirectional I/O used for transferring the serial data and

the ICSPCLK pin is the clock input. The device is placed

into a Program/Verify mode by holding the ICSPDAT and

ICSPCLK pins low, while raising the MCLR pin from V_ILto

Pin Description

1

2

3

4

5

6

=

1 = MCLR

V_IHH

.

2 = V_DDTarget

3 = V_SS(ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

Another connector often found in use with the PICkit™

programmers is a standard 6-pin header with 0.1 inch

spacing. Refer to Figure 28-2.

FIGURE 28-2:

PICkit™ PROGRAMMER-STYLE CONNECTOR INTERFACE

Pin 1 Indicator

Pin Description*

1

2

3

4

5

6

=

1 = MCLR

2 = V_DDTarget

3 = V_SS(ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

1

2

3

4

5

6

*

The 6-pin header (0.100" spacing) accepts 0.025" square pins.

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MCP19110/11

For additional interface recommendations, refer to your

specific device programmer manual prior to PCB

design.

It is recommended that isolation devices be used to

separate the programming pins from other circuitry.

The type of isolation is highly dependent on the specific

application and may include devices, such as resistors,

diodes, or even jumpers. See Figure 28-3 for more

information.

FIGURE 28-3:

External

TYPICAL CONNECTION FOR ICSP PROGRAMMING

V_DD

Programming

Signals

Device to be

Programmed

V_DD

V_PP

V_SS

MCLR

V_SS

Data

ICSPDAT

ICSPCLK

Clock

*

Isolation devices (as required)

*

To Normal Connections

28.2 In-Circuit Debugger

In-circuit debugging requires access to the ICDCLK,

ICDDATA, and MCLR pins. These pins are only

available on the MCP19111 device.

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MCP19110/11

29.0 INSTRUCTION SET SUMMARY

TABLE 29-1: OPCODE FIELD

DESCRIPTIONS

The MCP19110/11 instruction set is highly orthogonal

and is comprised of three basic categories:

Field

Description

• Byte-oriented operations

• Bit-oriented operations

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

• Literal and control operations

Bit address within an 8-bit file register

Literal field, constant data or label

Each instruction is a 14-bit word divided into an

opcode, which specifies the instruction type, and one

or more operands, which further specify the operation

of the instruction. The formats for each of the

categories are presented in Figure 29-1, while the

various opcode fields are summarized in Table 29-1.

k

x

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

Table 29-2 lists the instructions recognized by the

MPASM^TMassembler.

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

PC Program Counter

TO Time-Out bit

C

Carry bit

DC Digit carry bit

Zero bit

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

Z

PD Power-Down bit

FIGURE 29-1:

GENERAL FORMAT FOR

INSTRUCTIONS

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

Byte-Oriented file register operations

13

8

7

6

0

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

One instruction cycle consists of four oscillator periods;

for an oscillator frequency of 4 MHz, this gives a normal

instruction execution time of 1 µs. All instructions are

executed within a single instruction cycle, unless a

conditional test is true, or the program counter is

changed as a result of an instruction. When this occurs,

the execution takes two instruction cycles, with the

second cycle executed as an NOP.

Bit-Oriented file register operations

13 10 9 7 6

b (BIT #)

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

Literal and control operations

29.1 Read-Modify-Write Operations

General

13

8

7

0

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (RMW)

operation. The register is read, the data is modified,

and the result is stored according to either the

instruction or the destination designator ‘d’. A read

operation is performed on a register even if the

instruction writes to that register.

OPCODE

k (literal)

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

For example, a CLRF PORTA instruction will read

PORTGPA, clear all the data bits, then write the result

back to PORTGPA. This example would have the

unintended consequence of clearing the condition that

set the IOCF flag.

k (literal)

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MCP19110/11

TABLE 29-2: MCP19110/11 INSTRUCTION SET

14-Bit Opcode

Status

Affecte Notes

d

Mnemonic,

Description

Operands

Cycles

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00 0111 dfff ffff C, DC, Z

1, 2

2

00 0101 dfff ffff

00 0001 lfff ffff

00 0001 0xxx xxxx

00 1001 dfff ffff

00 0011 dfff ffff

00 1011 dfff ffff

00 1010 dfff ffff

00 1111 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 lfff ffff

00 0000 0xx0 0000

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

DECFSZ

INCF

Z

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

Z

Move W to f

No Operation

–

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1, 2

00 0010 dfff ffff C, DC, Z

00 1110 dfff ffff

00 0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

1, 2

3

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

–

k

–

k

–

k

Add literal and W

AND literal with W

Call Subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C, DC, Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

Z

00 0000 0110 0100 TO, PD

10 1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

00 0000 0110 0011 TO, PD

11 110x kkkk kkkk C, DC, Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be

cleared if assigned to the Timer0 module.

3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles.

The second cycle is executed as an NOP.

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MCP19110/11

29.2 Instruction Descriptions

ADDLW

Add literal and W

BCF

Bit Clear f

Syntax:

[ label ] ADDLW

0  k  255

k

Syntax:

[ label ] BCF f,b

Operands:

Operation:

Status Affected:

Description:

Operands:

0  f  127

0  b  7

(W) + k  (W)

C, DC, Z

Operation:

0 (f<b>)

Status Affected:

Description:

None

The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the

W register.

Bit ‘b’ in register ‘f’ is cleared.

ADDWF

Add W and f

BSF

Bit Set f

Syntax:

[ label ] ADDWF f,d

Syntax:

[ label ] BSF f,b

Operands:

0  f  127

d 0,1

Operands:

0  f  127

0  b  7

Operation:

(W) + (f)  (destination)

Operation:

1 (f<b>)

Status Affected: C, DC, Z

Status Affected:

Description:

None

Description:

Add the contents of the W register

Bit ‘b’ in register ‘f’ is set.

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back

in register ‘f’.

BTFSC

Bit Test f, Skip if Clear

ANDLW

AND literal with W

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDLW

0  k  255

k

Operands:

0  f  127

0  b  7

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k)  (W)

Operation:

skip if (f<b>) = 0

Z

Status Affected: None

The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

register.

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is discarded, and an

NOPis executed instead, making

this a two-cycle instruction.

ANDWF

AND W with f

Syntax:

[ label ] ANDWF f,d

Operands:

0  f  127

d 0,1

Operation:

(W) .AND. (f)  (destination)

Status Affected:

Description:

Z

AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

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MCP19110/11

BTFSS

Bit Test f, Skip if Set

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] BTFSS f,b

Syntax:

[ label ] CLRWDT

Operands:

0  f  127

0  b < 7

Operands:

Operation:

None

00h  WDT

0 WDT prescaler,

1 TO

Operation:

skip if (f<b>) = 1

Status Affected: None

1 PD

Description

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

Status Affected: TO, PD

If bit ‘b’ is ‘1’, then the next

instruction is discarded and an

NOPis executed instead, making

this a two-cycle instruction.

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT.

Status bits TO and PD are set.

CALL

Call Subroutine

COMF

Complement f

Syntax:

[ label ] CALL k

0  k  2047

Syntax:

[ label ] COMF f,d

Operands:

Operation:

Operands:

0  f  127

d  [0,1]

(PC)+ 1 TOS,

k  PC<10:0>,

Operation:

(f)  (destination)

(PCLATH<4:3>)  PC<12:11>

Status Affected:

Description:

Z

Status Affected: None

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

register ‘f’.

Description:

Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two-cycle instruction.

CLRF

Clear f

DECF

Decrement f

Syntax:

[ label ] CLRF

0  f  127

f

Syntax:

[ label ] DECF f,d

Operands:

Operation:

Operands:

0  f  127

d  [0,1]

00h  (f)

1 Z

Operation:

(f) - 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h  (W)

1 Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z)

is set.

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MCP19110/11

DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) - 1  (destination);

skip if result = 0

Operation:

(f) + 1  (destination),

skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, then an NOPis

executed instead, making it a

two-cycle instruction.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, an NOPis executed

instead, making it a two-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO k

0  k  2047

Syntax:

[ label ] IORLW k

0  k  255

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k  PC<10:0>

PCLATH<4:3>  PC<12:11>

(W) .OR. k  (W)

Z

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

Description:

GOTOis an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTOis a

two-cycle instruction.

INCF

Increment f

IORWF

Inclusive OR W with f

Syntax:

[ label ] INCF f,d

Syntax:

[ label ] IORWF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) + 1  (destination)

Operation:

(W) .OR. (f)  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

 2013-2016 Microchip Technology Inc.

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MCP19110/11

MOVF

Move f

MOVWF

Move W to f

[ label ] MOVWF

0  f  127

(W)  (f)

Syntax:

Operands:

[ label ] MOVF f,d

Syntax:

f

0  f  127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

Operation:

(f)  (dest)

None

Status Affected:

Description:

Z

Move data from W register to

register ‘f’.

The contents of register ‘f’ is

moved to a destination dependent

upon the status of ‘d’. If d = 0,

destination is W register. If d = 1,

the destination is file register ‘f’

itself. d = 1is useful to test a file

register since Status flag Z is

affected.

Words:

1

Cycles:

Example:

MOVW

F

OPTION

Before Instruction

OPTION = 0xFF

Words:

1

W

=

0x4F

After Instruction

Cycles:

Example:

OPTION = 0x4F

W

MOVF

FSR, 0

=

0x4F

After Instruction

W

=

value in

FSR register

Z

=

1

NOP

No Operation

MOVLW

Syntax:

Move literal to W

Syntax:

[ label ] NOP

[ label ] MOVLW k

0  k  255

Operands:

Operation:

Status Affected:

Description:

Words:

None

Operands:

Operation:

No operation

k  (W)

None

Status Affected: None

No operation.

Description:

The eight-bit literal ‘k’ is loaded into

1

W register. The “don’t cares” will

assemble as ‘0’s.

Cycles:

1

NOP

Example:

Words:

1

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

DS20002331D-page 198

 2013-2016 Microchip Technology Inc.

MCP19110/11

RETFIE

Return from Interrupt

[ label ] RETFIE

None

RETLW

Return with literal in W

[ label ] RETLW k

0  k  255

Syntax:

Operands:

Operation:

Operands:

Operation:

TOS  PC,

1 GIE

k  (W);

TOS  PC

Status Affected:

Description:

None

Status Affected:

Description:

None

Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE (INT-

CON<7>). This is a two-cycle

instruction.

The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

Words:

1

2

Cycles:

Example:

Words:

1

CALL TABLE;W contains

Cycles:

Example:

2

;table offset

;value

RETFIE

GOTO DONE

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

After Interrupt

TABLE

PC = TOS

GIE=

1

RETLW k2

;

•

RETLW kn ;End of table

DONE

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

None

Operands:

Operation:

TOS  PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed and the top of the stack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

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RLF

Rotate Left f through Carry

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

0  f  127

d  [0,1]

Operands:

Operation:

00h  WDT,

0 WDT prescaler,

1 TO,

Operation:

See description below

C

Status Affected:

Description:

0 PD

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The processor is put into Sleep

mode with the oscillator stopped.

C

Register f

Words:

1

Cycles:

Example:

RLF

REG1,0

Before Instruction

REG1

0110

C

=

1110

0

After Instruction

REG1

0110

W

1100

C

1110

1100

1

RRF

Rotate Right f through Carry

SUBLW

Subtract W from literal

Syntax:

[ label ] RRF f,d

Syntax:

[ label ] SUBLW k

0 k 255

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

k - (W) W)

Operation:

See description below

C

Status Affected: C, DC, Z

Status Affected:

Description:

Description: The W register is subtracted (two’s

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

Result

Condition

C = 0

W  k

C

Register f

C = 1

W  k

DC = 0

DC = 1

W<3:0>  k<3:0>

W<3:0>  k<3:0>

DS20002331D-page 200

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SUBWF

Subtract W from f

XORWF

Exclusive OR W with f

Syntax:

[ label ] SUBWF f,d

Syntax:

[ label ] XORWF f,d

Operands:

0 f 127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) - (W) destination)

Operation:

(W) .XOR. (f) destination)

Status Affected: C, DC, Z

Status Affected:

Description:

Z

Description:

Subtract (two’s complement

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

method) W register from register ‘f’.

If ‘d’ is ‘0’, the result is stored in the

W register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

C = 0

W  f

C = 1

W  f

DC = 0

DC = 1

W<3:0>  f<3:0>

W<3:0>  f<3:0>

SWAPF

Swap Nibbles in f

Syntax:

[ label ] SWAPF f,d

Operands:

0  f  127

d  [0,1]

Operation:

(f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Status Affected: None

Description:

The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in the W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

XORLW

Exclusive OR literal with W

Syntax:

[ label ] XORLW k

0 k 255

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k W)

Z

The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

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DS20002331D-page 201

MCP19110/11

NOTES:

DS20002331D-page 202

 2013-2016 Microchip Technology Inc.

MCP19110/11

30.1 MPLAB X Integrated Development

Environment Software

30.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers (MCU) and dsPIC^®digital

signal controllers (DSC) are supported with a full range

of software and hardware development tools:

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

hardware development tool that runs on Windows^®,

Linux and Mac OS^®X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

• Integrated Development Environment

- MPLAB^®X IDE Software

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

With complete project management, visual call graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multiple projects with simultaneous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

• Simulators

- MPLAB X SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

Feature-Rich Editor:

- PICkit™ 3

• Color syntax highlighting

• Device Programmers

- MPLAB PM3 Device Programmer

• Smart code completion makes suggestions and

provides hints as you type

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Automatic code formatting based on user-defined

rules

• Third-party Development Tools

• Live parsing

User-Friendly, Customizable Interface:

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project-Based Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Simultaneous debugging sessions

File History and Bug Tracking:

• Local file history feature

• Built-in support for Bugzilla issue tracker

 2013-2016 Microchip Technology Inc.

DS20002331D-page 203

MCP19110/11

30.2 MPLAB XC Compilers

30.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16, and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

MPLAB XC Compilers include an assembler, linker and

utilities. The assembler generates relocatable object

files that can then be archived or linked with other

relocatable object files and archives to create an

executable file. MPLAB XC Compiler uses the

assembler to produce its object file. Notable features of

the assembler include:

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

30.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archived or linked with other relocatable object

files and archives to create an executable file. Notable

features of the assembler include:

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

30.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multipurpose

source files

• Directives that allow complete control over the

assembly process

DS20002331D-page 204

 2013-2016 Microchip Technology Inc.

MCP19110/11

30.6 MPLAB X SIM Software Simulator

30.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB X SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the MPLAB

IDE.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 interface and is connected to the target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

30.9 PICkit 3 In-Circuit Debugger/

Programmer

The MPLAB PICkit

3

allows debugging and

30.7 MPLAB REAL ICE In-Circuit

Emulator System

programming of PIC and dsPIC Flash microcontrollers

at a most affordable price point using the powerful

graphical user interface of the MPLAB IDE. The

MPLAB PICkit 3 is connected to the design engineer’s

PC using a full-speed USB interface and can be

connected to the target via a Microchip debug (RJ-11)

connector (compatible with MPLAB ICD 3 and MPLAB

REAL ICE). The connector uses two device I/O pins

and the Reset line to implement in-circuit debugging

and In-Circuit Serial Programming™ (ICSP™).

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

30.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a mod-

ular, detachable socket assembly to support various

package types. The ICSP cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices, and incorporates an MMC card for file

storage and data applications.

The emulator is field upgradeable through future firm-

ware downloads in MPLAB X IDE. MPLAB REAL ICE

offers significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cables.

 2013-2016 Microchip Technology Inc.

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MCP19110/11

30.11 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

30.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide applica-

tion firmware and source code for examination and

modification.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companies, such as Gimpel

and Trace Systems

• Protocol Analyzers from companies, such as

Saleae and Total Phase

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

• Demonstration Boards from companies, such as

MikroElektronika, Digilent^®and Olimex

• Embedded Ethernet Solutions from companies,

such as EZ Web Lynx, WIZnet and IPLogika^®

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has a line of evaluation kits and demonstra-

®

tion software for analog filter design, KEELOQ security

ICs, CAN, IrDA^®, PowerSmart battery management,

SEEVAL^®evaluation system, Sigma-Delta ADC, flow

rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS20002331D-page 206

 2013-2016 Microchip Technology Inc.

MCP19110/11

31.0 PACKAGING INFORMATION

31.1 Package Marking Information

24-Lead QFN (4x4x0.9 mm) (MCP19110 only)

Example

19110

E/MJ ^^

e

3

1320

256

28-Lead QFN (5x5x0.9 mm)(MCP19111 only)

Example

19111

PIN 1

e

3

E/MQ ^^

1246256

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

RoHS Compliant JEDEC designator for Matte Tin (Sn)

e

3

*

This package is RoHS Compliant. The RoHS Compliant

JEDEC designator ( ) can be found on the outer packaging

e

3

for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 207

MCP19110/11

24-Lead Plastic Quad Flat, No Lead Package (MJ) – 4x4x0.9 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002331D-page 208

 2013-2016 Microchip Technology Inc.

MCP19110/11

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2013-2016 Microchip Technology Inc.

DS20002331D-page 209

MCP19110/11

28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN or VQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

NOTE 1

1

2

(DATUM B)

(DATUM A)

2X

0.10 C

2X

TOP VIEW

0.10 C

A1

C

A

SEATING

PLANE

28X

A3

0.08 C

0.10

SIDE VIEW

C A B

0.10

D2

C A B

E2

28X K

2

1

NOTE 1

28X L

N

28X b

0.10

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing C04-140C Sheet 1 of 2

DS20002331D-page 210

 2013-2016 Microchip Technology Inc.

MCP19110/11

28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN or VQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Pins

Pitch

Overall Height

Standoff

Contact Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

N

28

0.50 BSC

0.90

e

A

A1

A3

E

E2

D

D2

b

L

0.80

0.00

1.00

0.05

0.02

0.20 REF

5.00 BSC

3.25

5.00 BSC

3.25

0.25

0.40

-

3.15

3.35

3.15

0.18

0.35

0.20

3.35

0.30

0.45

-

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-140C Sheet 2 of 2

 2013-2016 Microchip Technology Inc.

DS20002331D-page 211

MCP19110/11

28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern

With 0.55 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Microchip Technology Drawing C04-2140A

DS20002331D-page 212

 2013-2016 Microchip Technology Inc.

MCP19110/11

APPENDIX A: REVISION HISTORY

Revision D (July 2016)

The following is the list of modifications:

1. Updated Register 6-15.

2. Updated information in Section 3.8.5, Overtem-

perature and Section 21.1, Circuit Operation.

Revision C (March 2015)

The following is the list of modifications:

1. Updated Figure 1-2.

2. Updated

Register 6-10,

Register 6-11,

Register 6-12 and Register 6-13.

3. Updated Section 9.2 “Calibration Word 2”.

4. Updated Section 9.3 “Calibration Word 3”.

5. Updated Equation 10-1.

6. Updated information in the first sentence of

Section 11.4 “PCL and PCLATH”.

7. Removed Section 11.1.1.2 “Indirect Read with

Files Select Register (FSR)”.

8. Updated the first sentence in Section 12.0

“Device Configuration”.

9. Removed Section “12.5 Device ID and Revision

ID”.

10. Updated information in Section 18.3.2 “Writing

to the Flash Program Memory”.

11. Updated information in Section 22.1.2 “Chan-

nel Selection”.

12. Updated information for bit 6-2 in Register 22-1.

Revision B (June 2013)

The following is the list of modifications:

1. Added new device MCP19110 to the family and

the related information across the document.

2. Updated information in Features section.

3. Added pinout diagram and pin summary table

for the MCP19110 device.

4. Updated Figure 1-1.

5. Updated Section 2.0 “Pin Description”.

6. Updated Section 4.3 “Thermal

Specifications”.

7. Added new Section 28.2 “In-Circuit

Debugger”.

8. Updated Section 31.1 “Package Marking

Information”.

9. Updated Product Identification System.

10. Fixed minor typographical errors.

Revision A (January 2013)

• Original Release of this Document.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 213

MCP19110/11

NOTES:

DS20002331D-page 214

 2013-2016 Microchip Technology Inc.

MCP19110/11

INDEX

Watchdog Timer ....................................................... 103

A

A/D

C

Specifications...................................................... 3, 5, 33

C Compilers

MPLAB C18.............................................................. 204

Calibration Word

Associated Registers.................................................. 84

Capture/Compare/PWM ........................................... 143, 145

Clock Switching .................................................................. 84

Code Examples

A/D Conversion ........................................................ 128

Assigning Prescaler to Timer0.................................. 136

Assigning Prescaler to WDT..................................... 136

Initializing PORTA .................................................... 111

Saving Status and W Registers in RAM................... 100

Compensation .................................................................... 18

Compensation Setting ........................................................ 43

Computed Function Calls ................................................... 78

Computed GOTO................................................................ 78

Current

A/D Conversion................................................................. 127

Requirements.............................................................. 34

Timing ................................................................... 34, 35

Absolute Maximum Ratings ................................................ 23

AC Characteristics .............................................................. 30

ACKSTAT ......................................................................... 172

ACKSTAT Status Flag ...................................................... 172

ADC .................................................................................. 125

Acquisition Requirements ......................................... 131

Associated Registers ................................................ 133

Block Diagram........................................................... 125

Calculating Acquisition Time..................................... 131

Channel Selection..................................................... 126

Configuration............................................................. 126

Configuring Interrupt ................................................. 128

Conversion Clock...................................................... 126

Conversion Procedure .............................................. 128

Internal Sampling Switch (RSS) IMPEDANCE .............. 131

Interrupts................................................................... 127

Operation .................................................................. 128

Operation During Sleep ............................................ 128

Port Configuration..................................................... 126

Register Definitions................................................... 129

Source Impedance.................................................... 131

Special Event Trigger................................................ 128

ADCON0 Register............................................................. 129

ADCON1 Register............................................................. 130

ADRESH Register (ADFM = 0)......................................... 130

ADRESL Register (ADFM = 0).......................................... 130

Alternate Pin Function....................................................... 112

Analog Blocks Enable Control ............................................ 51

Analog Peripheral Control................................................... 49

Analog-to-Digital Converter. See ADC

Measurement Control................................................. 51

Current Sense ........................................................ 18, 40, 41

Customer Change Notification Service............................. 221

Customer Support............................................................. 221

D

Data Memory ...................................................................... 70

Data Memory Map.............................................................. 72

DC and AC Characteristics................................................. 53

Graphs and Tables..................................................... 53

DC Characteristics.............................................................. 30

Development Support....................................................... 203

Device

Configuration ........................................................ 37, 81

Code Protection.................................................. 82

Configuration Word............................................. 81

ID Locations ....................................................... 82

Write Protection.................................................. 82

Device Calibration............................................................... 59

Calibration Word 1...................................................... 59

Calibration Word 2...................................................... 60

Calibration Word 3...................................................... 61

Calibration Word 4...................................................... 62

Calibration Word 5...................................................... 63

Calibration Word 6...................................................... 64

Calibration Word 7...................................................... 65

Device Overview................................................................... 9

Digital Electrical Characteristics ......................................... 29

Diode Emulation Mode ....................................................... 49

ANSELA Register ............................................................. 115

ANSELB Register ............................................................. 118

APFCON Register............................................................. 112

Assembler

MPASM Assembler................................................... 204

B

Bench Testing

Analog Bench Test Control......................................... 57

System........................................................................ 57

BF ............................................................................. 172, 174

BF Status Flag .......................................................... 172, 174

Block Diagrams

ADC .......................................................................... 125

ADC Transfer Function ............................................. 132

Analog Input Model................................................... 132

Generic I/O Port........................................................ 111

Interrupt Logic............................................................. 94

MCLR Circuit............................................................... 86

MCP19110/11 Synchronous Buck Block Diagram...... 10

MSSP (I²C Master Mode) ......................................... 147

MSSP (I²C Slave Mode) ........................................... 148

On-Chip Reset Circuit................................................. 85

Simplified PWM......................................................... 144

Timer0....................................................................... 135

Timer1....................................................................... 137

Timer2....................................................................... 140

E

ECCP/CCP. See Enhanced Capture/Compare/PWM

Electrical Characteristics .............................................. 23, 24

Errata.................................................................................... 7

External Clock..................................................................... 30

F

Features

Miscellaneous............................................................. 21

Protection ................................................................... 20

Synchronous Buck........................................................ 1

Firmware Instructions ....................................................... 193

Flash Program Memory Control........................................ 105

Operation During Code Protect ................................ 109

 2013-2016 Microchip Technology Inc.

DS20002331D-page 215

MCP19110/11

Operation during write Protect ..................................109

Protecting..................................................................109

Reading.....................................................................108

Writing to...................................................................109

Flash Program Memory Control Registers........................106

DECF........................................................................ 196

DECFSZ ................................................................... 197

GOTO....................................................................... 197

INCF ......................................................................... 197

INCFSZ..................................................................... 197

IORLW...................................................................... 197

IORWF...................................................................... 197

MOVF ....................................................................... 198

MOVLW .................................................................... 198

MOVWF.................................................................... 198

NOP.......................................................................... 198

RETFIE..................................................................... 199

RETLW ..................................................................... 199

RETURN................................................................... 199

RLF........................................................................... 200

RRF .......................................................................... 200

SLEEP ...................................................................... 200

SUBLW..................................................................... 200

SUBWF..................................................................... 201

SWAPF..................................................................... 201

XORLW .................................................................... 201

XORWF .................................................................... 201

Summary Table ........................................................ 194

Internal Sampling Switch (RSS) IMPEDANCE ...................... 131

Internal Synchronous Driver ............................................... 17

Internal Temperature Indicator Module............................. 123

Circuit Operation....................................................... 123

Temperature Output ................................................. 123

Internal Temperature Measurement Control....................... 51

Internet Address ............................................................... 221

Interrupt-on-Change ......................................................... 121

Associated Registers................................................ 122

Clearing Interrupt Flags ............................................ 121

Enabling the Module................................................. 121

Operation in Sleep.................................................... 121

Pin Configuration...................................................... 121

Registers .................................................................. 122

Interrupts

H

High-Side Drive Strength ....................................................49

I

I/O

Ports..........................................................................111

I²C Mode (MSSPx)

Acknowledge Sequence ...........................................152

Acknowledge Sequence Timing................................176

Associated Registers ................................................182

Bus Collision

During a Repeated Start Condition...................180

During a Start Condition....................................178

During a Stop Condition....................................181

Effects of a Reset......................................................177

I²C Clock Rate w/BRG..............................................183

Master Mode.............................................................169

Clock Arbitration................................................169

Operation ..........................................................169

Reception..........................................................174

Start Condition Timing ..............................170, 171

Transmission.....................................................172

Multi-Master Communication, Bus Collision and Arbitra-

tion ....................................................................177

Multi-Master Mode ....................................................177

Operation ..................................................................150

Overview...................................................................148

Read/Write Bit Information (R/W Bit) ........................153

Slave Mode

10-bit Address Reception..................................163

Bus Collision .....................................................159

Clock Synchronization ......................................167

General Call Address Support ..........................168

Operation ..........................................................153

SSPMSKx Register...........................................168

Transmission.....................................................159

Sleep Operation........................................................177

Stop Condition Timing...............................................176

In-Circuit Serial Programming (ICSP) ...............................191

Common Programming Interfaces............................191

In-Circuit Debugger...................................................192

Indirect Addressing .............................................................78

Input ....................................................................................24

Type............................................................................12

Under Voltage Lockout .........................................20, 37

Instruction Format .............................................................193

Instruction Set ...................................................................193

ADDLW.....................................................................195

ADDWF.....................................................................195

ANDLW.....................................................................195

ANDWF.....................................................................195

BCF...........................................................................195

BSF...........................................................................195

BTFSC ......................................................................195

BTFSS ......................................................................196

CALL.........................................................................196

CLRF.........................................................................196

CLRW .......................................................................196

CLRWDT...................................................................196

COMF .......................................................................196

ADC.......................................................................... 128

Associated Registers.................................................. 99

Context Saving ......................................................... 100

Control Registers........................................................ 95

RA2/INT...................................................................... 93

TMR1........................................................................ 138

L

Linear Regulators ............................................................... 17

M

MASTER Error Signal Gain ................................................ 45

Master Synchronous Serial Port. See MSSPx

MCLR.................................................................................. 86

Internal........................................................................ 86

Memory Organization ......................................................... 69

Data............................................................................ 70

Program...................................................................... 69

Microchip Internet Web Site.............................................. 221

MOSFET................................... 15, 16, 17, 38, 46, 49, 57, 67

Driver Dead Time........................................................ 17

MOSFET Driver

Dead Time.................................................................. 49

Programmable Dead Time.......................................... 46

MPLAB ASM30 Assembler, Linker, Librarian................... 204

MPLAB Integrated Development Environment Software.. 203

MPLAB PM3 Device Programmer .................................... 205

MPLAB REAL ICE In-Circuit Emulator System ................ 205

DS20002331D-page 216

 2013-2016 Microchip Technology Inc.

MCP19110/11

MPLINK Object Linker/MPLIB Object Librarian ................ 204

MSSPx.............................................................................. 147

Arbitration.................................................................. 150

Baud Rate Generator................................................ 183

Clock Stretching........................................................ 150

I²C Bus Terms .......................................................... 151

I²C Master Mode....................................................... 169

I²C Mode................................................................... 148

I²C Mode Operation.................................................. 150

I²C Slave Mode Operation........................................ 153

Module Overview ...................................................... 147

Multi-Phase System............................................................ 22

Pin Descriptions and Diagrams ................................ 119

PORTGPA ................................................................ 112, 121

ANSELA Register..................................................... 113

Associated Registers................................................ 115

Functions and Output Priorities ................................ 113

Interrupt-on-Change ................................................. 112

Weak Pull-Ups.......................................................... 112

PORTGPA Register.......................................................... 112

PORTGPB ................................................................ 116, 121

ANSELB Register..................................................... 116

Associated Registers................................................ 119

Functions and Output Priorities ................................ 116

Interrupt-on-Change ................................................. 116

P1B/P1C/P1D.Capture/Compare/PWM ................... 116

Weak Pull-Ups.......................................................... 116

PORTGPB Register.................................................. 116, 117

Power-Down Mode (Sleep)............................................... 101

Associated Registers................................................ 102

Power-on Reset (POR)....................................................... 86

Power-up Timer (PWRT) .................................................... 87

Prescaler, Timer1

Select (T1CKPS1:T1CKPS0 Bits) .............................. 46

Product Identification System........................................... 223

Program Memory................................................................ 69

Map and Stack (MCP19111) ...................................... 69

Program Memory Protection............................................... 82

Programming, Device Instructions.................................... 193

Pulse-Width Modulation...................................................... 33

Associated Registers................................................ 145

Duty Cycle ................................................................ 145

Module...................................................................... 143

Operating during Sleep............................................. 145

Period ....................................................................... 144

Stand-alone Mode .................................................... 143

Standard Mode......................................................... 143

Switching Frequency Synchronization Mode............ 143

O

OPCODE Field Descriptions............................................. 193

Oscillator............................................................................. 83

Associated Registers .................................................. 84

Calibration................................................................... 83

Delay Upon Power-up................................................. 84

Frequency Tuning....................................................... 83

Internal Oscillator........................................................ 83

Oscillator Module ................................................................ 84

Output ................................................................................. 49

Multiple System........................................................... 22

Overcurrent..................................................... 20, 38, 39

Overvoltage..................................................... 20, 25, 48

Overvoltage Enable .................................................... 51

Power Good................................................................ 22

Type............................................................................ 12

Under Voltage................................................. 20, 25, 48

Under Voltage Accelerator.......................................... 49

Under Voltage Enable................................................. 51

Voltage........................................................................ 18

Soft-Start............................................................. 22

Tracking.............................................................. 22

Voltage Configuration ................................................. 47

Voltage Sense Pull-up/Pull-down................................ 49

Overcurrent......................................................................... 39

Overvoltage Accelerator ..................................................... 49

R

Reader Response............................................................. 222

Read-Modify-Write Operations ......................................... 193

Register

P

Packaging ......................................................................... 207

Marking ..................................................................... 207

Specifications............................................................ 208

PCL..................................................................................... 78

Modifying..................................................................... 78

PCLATH.............................................................................. 78

PCON Register ............................................................. 87, 92

Pin Diagram

OVFCON (Output Voltage Set Point Fine Control)..... 47

Registers

ABECON (Analog Block Enable Control) ................... 52

ADCON0 (ADC Control 0)........................................ 129

ADCON1 (ADC Control 1)........................................ 130

ADRESH (ADC Result High) with ADFM = 0) .......... 130

ADRESL (ADC Result Low) with ADFM = 0)............ 130

ANSELA (Analog Select GPA) ................................. 115

ANSELB (Analog Select GPB) ................................. 118

APFCON (Alternate Pin Function Control) ............... 112

ATSTCON (Analog Bench Test Control).................... 57

BUFFCON (Unity Gain Buffer Control)....................... 58

CALWD1 (Calibration Word 1) ................................... 59

CALWD2 (Calibration Word 2) ................................... 60

CALWD3 (Calibration Word 3) ................................... 61

CALWD4 (Calibration Word 4) ................................... 62

CALWD5 (Calibration Word 5) ................................... 63

CALWD6 (Calibration Word 6) ................................... 64

CALWD7 (Calibration Word 7) ................................... 65

CMPZCON (Compensation Setting Control).............. 43

CONFIG (Configuration Word) ................................... 81

CSDGCON (Voltage For Zero Current Control) ......... 41

CSGSCON (Current Sense AC Gain Control)............ 40

DEADCON (Driver Dead Time Control) ..................... 46

INTCON (Interrupt Control) ........................................ 95

24-Pin QFN................................................................... 2

28-Pin QFN................................................................... 4

Pinout Description

Summary................................................................... 3, 5

Pinout Description Table..................................................... 12

PIR1 Register...................................................................... 98

PIR2 Register...................................................................... 99

PMADRH Register............................................................ 105

PMADRL Register..................................................... 105, 106

PMCON1 Register .................................................... 105, 107

PMCON2 Register ............................................................ 105

PMDATH Register ............................................................ 106

PMDATL Register............................................................. 106

PMDRH Register .............................................................. 107

PORTB

Additional Pin Functions

Weak Pull-up .................................................... 117

 2013-2016 Microchip Technology Inc.

DS20002331D-page 217

MCP19110/11

IOCA (Interrupt-on-Change PORTGPA)...................122

IOCB (Interrupt-on-Change PORTGPB)...................122

LPCRCON (Slope Compensation Ramp Control).......44

OCCON (Output Overcurrent Control)........................39

OOVCON (Output Overvoltage Detect Level Control) 48

OPTION_REG (Option) ..............................................77

OSCTUNE (Oscillator Tuning)....................................83

OUVCON (Output Under Voltage Detect Level Control)

48

OVCCON (Output Voltage Set Point Coarse Control) 47

PCON (Power Control) .........................................87, 92

PE1(Analog Peripheral Enable 1 Control) ..................50

PIE1 (Peripheral Interrupt Enable)..............................96

PIR1 (Peripheral Interrupt Flag)..................................98

PIR2 (Peripheral Interrupt Flag)..................................99

PMADRL (Program Memory Address)......................106

PMCON1 (Program Memory Control).......................107

PMDATH (Program Memory Data)...........................106

PMDATL (Program Memory Data)............................106

PMDRH (Program Memory Address)........................107

PORTGPA ................................................................113

PORTGPB ................................................................117

RELEFF (Relative Efficiency Measurement) ..............67

Reset Values...............................................................89

SLVGNCON (MASTER Error Signal Input Gain Control)

45

Special Function Registers................................................. 71

Special Registers Summary

Bank 0 ........................................................................ 73

Bank 1 ........................................................................ 74

Bank 2 ........................................................................ 75

Bank 3 ........................................................................ 76

SSPxADD Register................................................... 188, 189

SSPxCON1 Register ........................................................ 185

SSPxCON2 Register ........................................................ 186

SSPxCON3 Register ........................................................ 187

SSPxMSK Register................................................... 188, 189

SSPxOV............................................................................ 174

SSPxOV Status Flag ........................................................ 174

SSPxSTAT Register ......................................................... 184

R/W Bit ..................................................................... 153

Stack................................................................................... 78

Start-up Sequence.............................................................. 87

STATUS Register ............................................................... 71

Switching Frequency .......................................................... 18

System Bench Testing.................................................. 22, 57

T

T1CON Register ............................................................... 138

T1CKPS1:T1CKPS0 Bits............................................ 46

Temperature Indicator Module.......................................... 123

Thermal Specifications ....................................................... 28

Timer Requirements

Special Registers Summary......................73, 74, 75, 76

SSPCON1(SSP Control)...........................................185

SSPSTAT (SSP Status)............................................184

SSPxADD (MSSPx Address and Baud Rate, I²C Mode)

188, 189

RESET, Watchdog Timer, Oscillator Start-up Timer and

Power-up ............................................................ 32

Timer0....................................................................... 135, 141

8-Bit Counter Mode................................................... 135

8-bit Timer Mode....................................................... 135

Associated Registers................................................ 136

External Clock........................................................... 136

Operation.................................................................. 135

Operation During Sleep ............................................ 136

T0CKI ....................................................................... 136

Timer0 Module.................................................................. 135

Timer1............................................................................... 137

Associated Registers................................................ 139

Associated registers ................................................. 139

Clock Source Selection............................................. 137

Control Register........................................................ 138

Interrupt .................................................................... 138

Operation.................................................................. 137

Operation During Sleep ............................................ 138

Prescaler .................................................................. 138

Sleep ........................................................................ 138

TMR1H Register....................................................... 137

TMR1L Register........................................................ 137

Timer1 Module.................................................................. 137

Timer2

SSPxCON1 (MSSPx Control 1)................................185

SSPxCON2 (SSPx Control 2)...................................186

SSPxCON3 (SSPx Control 3)...................................187

SSPxMSK (SSPx Mask) ...................................188, 189

SSPxSTAT (SSPx Status) ........................................184

STATUS......................................................................71

T1CON (Timer1 Control)...........................................138

TRISA (Tri-State PORTA).........................................114

TRISGPB (PORTGPB Tri-State) ..............................117

TXCON .....................................................................141

VINLVL (Input Under Voltage Lockout Control)..........37

VZCCON (Voltage for Zero Current Control) ..............42

WPUB (Weak Pull-up PORTB).................................114

WPUGPA

Weak Pull-up PORTGPA..................................114

WPUGPB (Weak Pull-up PORTGPB).......................118

Relative Efficiency Circuity Control .....................................51

Relative Efficiency Measurement........................................67

Procedure ...................................................................67

Relative Efficiency Measurement Control ...........................51

Reset...................................................................................85

Determining Causes ...................................................91

Resets.................................................................................85

Associated Registers ..................................................92

Revision History ................................................................213

Associated registers ................................................. 141

Control Register........................................................ 141

Operation.................................................................. 140

Timer2 Module.................................................................. 140

Timer2/4/6

S

Associated Registers................................................ 141

Timers

Signal Chain Control ...........................................................51

Sleep

Timer1

Wake-up from ...........................................................101

Wake-up Using Interrupts .........................................102

Slope Compensation.....................................................18, 44

Slope Compensation Control ..............................................51

Software Simulator (MPLAB SIM).....................................205

Special Event Trigger........................................................128

T1CON ............................................................. 138

Timer2/4/6

TXCON............................................................. 141

Timing Diagrams

Acknowledge Sequence........................................... 176

Baud Rate Generator with Clock Arbitration............. 170

DS20002331D-page 218

 2013-2016 Microchip Technology Inc.

MCP19110/11

BRG Reset Due to SDA Arbitration During Start Condi-

tion.................................................................... 179

Bus Collision During a Repeated Start Condition (Case

1)....................................................................... 180

Bus Collision During a Repeated Start Condition (Case

2)....................................................................... 180

Bus Collision During a Start Condition (SCL = 0) ..... 179

Bus Collision During a Stop Condition (Case 1) ....... 181

Bus Collision During a Stop Condition (Case 2) ....... 181

Bus Collision During Start Condition (SDA only) ...... 178

Bus Collision for Transmit and Acknowledge............ 177

Capture/Compare/PWM.............................................. 33

Clock Synchronization .............................................. 167

First Start Bit Timing ................................................. 170

I²C Master Mode (7 or 10-Bit Transmission) ............ 173

I²C Master Mode (7-Bit Reception)........................... 175

I²C Stop Condition Receive or Transmit Mode......... 176

INT Pin Interrupt.......................................................... 94

Power-up Timer .......................................................... 31

Repeat Start Condition.............................................. 171

Reset........................................................................... 31

Start-up Timer............................................................. 31

Time-out Sequence

Case 1 ................................................................ 87

Case 2 ................................................................ 88

Case 3 ................................................................ 88

Timer0......................................................................... 32

Timer1......................................................................... 32

Wake-up from Interrupt............................................. 102

Watchdog Timer.......................................................... 31

Timing Parameter Symbology............................................. 29

Timing Requirements

CLKOUT and I/O......................................................... 31

External Clock............................................................. 30

TRISA Register................................................................. 114

TRISGPA .......................................................................... 112

TRISGPA Register............................................................ 112

TRISGPB Register.................................................... 116, 117

TXCON (Timer2/4/6) Register .......................................... 141

Typical Application Circuit..................................................... 9

Typical Performance Curves............................................... 53

U

Under Voltage Lockout

Input............................................................................ 37

Unity Gain Buffer................................................................. 58

V

Voltage For Zero Current.................................................... 42

W

Watchdog Timer (WDT).............................................. 87, 103

Associated Registers ................................................ 104

Configuration Word w/ Watchdog Timer................... 104

Operation .................................................................. 103

Period........................................................................ 103

Programming Considerations ................................... 103

WCOL ....................................................... 170, 172, 174, 176

WCOL Status Flag.................................... 170, 172, 174, 176

WPUB Register................................................................. 114

WPUGPB Register............................................................ 118

WWW Address.................................................................. 221

WWW, On-Line Support ....................................................... 7

 2013-2016 Microchip Technology Inc.

DS20002331D-page 219

MCP19110/11

DS20002331D-page 220

 2013-2016 Microchip Technology Inc.

MCP19110/11

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our website at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on “Cus-

tomer Change Notification” and follow the registration

instructions.

 2013-2016 Microchip Technology Inc.

DS20002331D-page 221

MCP19110/11

NOTES:

DS20002331D-page 222

 2013-2016 Microchip Technology Inc.

MCP19110/11

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

[X]⁽¹⁾

Examples:

PART NO.

X

/XX

-

a)

MCP19110-E/MJ: Extended temperature,

24LD QFN 4x4 package

MCP19110T-E/MJ: Tape and Reel,

Extended temperature,

Device Tape and Reel

Option

Temperature

Range

Package

b)

24LD QFN 4x4 package

Device:

MCP19110: Digitally Enhanced Power Analog Controller with

Integrated Synchronous Driver

a)

b)

MCP19111-E/MQ: Extended temperature,

28LD QFN 5x5 package

MCP19111T-E/MQ: Tape and Reel,

Extended temperature,

MCP19111: Digitally Enhanced Power Analog Controller with

Integrated Synchronous Driver

28LD QFN 5x5 package

Tape and Reel

Option:

Blank = Standard packaging (tube)

T

= Tape and Reel

Note 1: Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes

and is not printed on the device package.

Check with your Microchip Sales Office

for package availability with the Tape and

Reel option.

Temperature

Range:

E

= -40C to +125C (Extended)

Package:

MJ = 24-lead Plastic Quad Flat, No Lead Package -

4x4x0.9 mm body (QFN)

MQ = 28-lead Plastic Quad Flat, No Lead Package -

5x5x0.9 mm body (QFN)

 2013-2016 Microchip Technology Inc.

DS20002331D-page 223

MCP19110/11

NOTICE TO CUSTOMERS

®

This product is subject to a license from Power-One , Inc. related to digital power technology

(DPT) patents owned by Power-One, Inc. This license does not extend to stand-alone power

supply products.

DS20002331D-page 224

 2013-2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate,

dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,

KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,

MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,

RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O

are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company,

ETHERSYNCH, Hyper Speed Control, HyperLight Load,

IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,

BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

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QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ

CERTIFIEDꢀBYꢀDNVꢀ

ISBN: 978-1-5224-0773-7

== ISO/TSꢀ16949ꢀ==ꢀ

 2013-2016 Microchip Technology Inc.

DS20002331D-page 225

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06/23/16

DS20002331D-page 226

 2013-2016 Microchip Technology Inc.


型号：	MCP19110T-E/MQ
厂家：	MICROCHIP
描述：	Digitally-Enhanced Power Analog Controller
文件：	总226页 (文件大小：3155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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