MCP2022-E-P [MICROCHIP]
DATACOM, INTERFACE CIRCUIT, PDIP14, 0.300 INCH, LEAD FREE, PLASTIC, DIP-8;
| 型号： | MCP2022-E-P |
| 厂家： | 
MICROCHIP |
| 描述： | DATACOM, INTERFACE CIRCUIT, PDIP14, 0.300 INCH, LEAD FREE, PLASTIC, DIP-8 光电二极管 |
| 文件： | 总58页 (文件大小：2029K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP2021/2/1P/2P
LIN Transceiver with Voltage Regulator
Features:
Description:
• The MCP2021/2/1P/2P are Compliant with LIN
Bus Specifications 1.3, 2.0, and 2.1 and are
Compliant to SAE J2602
The MCP2021/2/1P/2P provides a bidirectional, half-
duplex communication physical interface to automotive
and industrial LIN systems that meets the LIN bus
specification Revision 2.0. The devices incorporate a
voltage regulator with 5V at 50 mA or 3.3V at 50 mA
regulated power-supply outputs.
• Support Baud Rates up to 20 kBaudwith
LIN-compatible Output Driver
• 43V Load Dump Protected
The regulator is short-circuit protected, and is protected
by an internal thermal shutdown circuit. The device has
been specifically designed to operate in the automotive
operating environment and will survive all specified
transient conditions while meeting all of the stringent
quiescent current requirements.
• Very Low EMI Meets Stringent OEM Requirements
• Wide Supply Voltage, 6.0V - 18.0V Continuous:
- Maximum Input Voltage of 30V
• Extended Temperature Range: -40 to +125°C
• Interface to PIC® EUSART and Standard USARTs
• Local Interconnect Network (LIN) Bus Pin:
- Internal Pull-up Resistor and Diode
- Protected Against Ground Shorts
- Protected Against Loss of Ground
- High-Current Drive
The MCP2021/2/1P/2P family of devices includes the
following packages.
8-pin PDIP, DFN and SOIC packages:
• MCP2021-330, LIN-compatible driver, 8-pin, 3.3V
regulator, wake up on dominant level of LBUS
• Automatic Thermal Shutdown
• MCP2021-500, LIN-compatible driver, 8-pin, 5.0V
regulator, wake up on dominant level of LBUS
• On-Chip Voltage Regulator:
- Output Voltage of 5.0V with Tolerances of
±3% Overtemperature Range
• MCP2021P-330, LIN-compatible driver, 8-pin,
3.3V regulator, wake up at falling edge of LBUS
voltage
- Available with Alternate Output Voltage of
3.3V with Tolerances of ±3%
Overtemperature Range
• MCP2021P-500, LIN-compatible driver, 8-pin,
5.0V regulator, wake up at falling edge of LBUS
voltage
- Maximum Continuous Input Voltage of 30V
- Internal Thermal Overload Protection
- Internal Short Circuit Current Limit
14-pin PDIP, TSSOP and SOIC packages with RESET
output:
- External Components Limited to Filter
Capacitor Only and Load Capacitor
• MCP2022-330, LIN-compatible driver, 14-pin,
3.3V regulator, RESET output, wake up on domi-
nant level of LBUS
• Two Low-Power Modes:
• MCP2022-500, LIN-compatible driver, 14-pin,
5.0V regulator, RESET output, wake up on domi-
nant level of LBUS
- Receiver On, Transmitter Off, Voltage
Regulator On ( 85 µA)
- Receiver Monitoring Bus, Transmitter Off,
• MCP2022P-330, LIN-compatible driver, 14-pin,
3.3V regulator, RESET output, wake up at falling
edge of LBUS voltage
Voltage Regulator Off ( 16 µA)
• MCP2022P-500, LIN-compatible driver, 14-pin,
5.0V regulator, RESET output, wake up at falling
edge of LBUS voltage
2005-2013 Microchip Technology Inc.
DS22018G-page 1
MCP2021/2/1P/2P
Package Types
DFN-8, PDIP-8, SOIC-8
RXD
1
2
3
4
8
7
6
FAULT/TXE
VBB
CS/LWAKE
VREG
LBUS
VSS
TXD
5
PDIP-14, SOIC-14, TSSOP-14
1
2
3
14
13
12
FAULT/TXE
VBB
RXD
CS/LWAKE
VREG
TXD
LBUS
VSS
4
5
11
10
9
RESET
NC
NC
NC
NC
6
7
NC
8
MCP2021/2 Block Diagram
Thermal
Protection
Short Circuit
Protection
RESET
(MCP2022 ONLY)
Voltage
Regulator
VBB
Ratiometric
Reference
Internal Circuits
VREG
Wake-Up
Logic and
Power Control
–
RXD
+
~30 k
CS/LWAKE
TXD
LBUS
VSS
OC
FAULT/TXE
Short Circuit
Protection
Thermal
Protection
DS22018G-page 2
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
MCP2021P/2P Block Diagram
RESET
(MCP2022P ONLY)
Thermal
Protection
Short-Circuit
Protection
Voltage
Regulator
VBB
Ratiometric
Reference
Internal Circuits
VREG
Wake-Up
Logic and
Power Control
–
RXD
+
~30
k
CS/LWAKE
TXD
LBUS
VSS
OC
FAULT/TXE
Thermal
and
Short-Circuit
Protection
Short-Circuit
Protection
2005-2013 Microchip Technology Inc.
DS22018G-page 3
MCP2021/2/1P/2P
NOTES:
DS22018G-page 4
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
EQUATION 1-1:
1.0
DEVICE OVERVIEW
The MCP2021/2/1P/2P provides a physical interface
between a microcontroller and a LIN half-duplex bus. It
is intended for automotive and industrial applications
with serial bus speeds up to 20 Kbaud.
RTP <= (VBBmin - 5.5) / 250 mA.
5.5V = VUVLO + 1.0V,
250 mA is the peak current at Power-On when
VBB = 5.5V
The MCP2021/2/1P/2P provides
a
half-duplex,
1.2
Internal Protection
bidirectional communications interface between a
microcontroller and the serial network bus. This device
will translate the CMOS/TTL logic levels to LIN-level
logic, and vice versa.
1.2.1
ESD PROTECTION
For component-level ESD ratings, please refer to the
Section 2.1 “Absolute Maximum Ratings†”.
The LIN specification 2.0 requires that the
transceiver(s) of all nodes in the system be connected
via the LIN pin, referenced to ground, and with a
maximum external termination resistance load of 510
from LIN bus to battery supply. The 510corresponds
to one Master and sixteen Slave nodes.
1.2.2
GROUND LOSS PROTECTION
The LIN Bus specification states that the LIN pin must
transition to the recessive state when ground is
disconnected. Therefore, a loss of ground effectively
forces the LIN line to a hi-impedance level.
The MCP2021/2/1P/2P-500 provides a +5V, 50 mA,
regulated power output. The regulator uses an LDO
design, is short-circuit protected, and will turn the
regulator output off if it falls below 3.5V.
1.2.3
THERMAL PROTECTION
The thermal protection circuit monitors the die tem-
perature and is able to shut down the LIN transmitter
and voltage regulator if it detects a thermal overload.
The MCP2021/2/1P/2P also includes thermal-
shutdown protection.
There are three causes for a thermal overload. A
thermal shut down can be triggered by any one, or a
combination of, the following thermal overload
conditions:
The regulator is specifically designed to operate in the
automotive environment and will survive +43V load
dump transients, double-battery jumps, and reverse
battery connections when a reverse blocking diode is
used. The other members of the MCP2021/2/1P/2P-
330 family output +3.3V at 50 mA with a turn-off voltage
of 2.5V. (See Section 1.6 “Internal Voltage
Regulator”).
• Voltage regulator overload
• LIN bus output overload
• Increase in die temperature due to increase in
environmental temperature
MCP2021/2 wakes from Power-Down mode on a
dominant level on LBUS. MCP2021P/2P wakes at a
transition from recessive level to dominant level on
LBUS.
Driving the TXD and checking the RXD pin makes it
possible to determine whether there is a bus contention
(i.e., Rx = low, Tx = high) or a thermal overload condi-
tion (i.e., Rx = high, Tx = low).
1.1
Optional External Protection
1.1.1
REVERSE BATTERY PROTECTION
An external reverse-battery-blocking diode should be
used to provide polarity protection (see Figure 1-6).
1.1.2
TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 43V transient suppressor (TVS) diode,
between VBB and ground, with a 50 transient protec-
tion resistor (RTP) in series with the battery supply and
the VBB pin, protect the device from power transients
(see Figure 1-6) and ESD events. While this protection
is optional, it is considered good engineering practice.
The resistor value is chosen according to Equation 1-1.
2005-2013 Microchip Technology Inc.
DS22018G-page 5
MCP2021/2/1P/2P
LIN Bus
Overload
to VBB
Output
Overload
Voltage
Regulator
Shutdown
Transmitter
Shutdown
Operation
Mode
Temperature <SHUTDOWNTEMP
Temperature <SHUTDOWNTEMP
FIGURE 1-1:
Thermal Shutdown State Diagrams.
LIN bus activity will also change the device from
Power-Down mode to Ready mode. MCP2021/2
wakes up on the dominant level of the LIN bus, and
MCP2021P/2P on a falling edge that follows a domi-
nant level lasting 20 µs of time.
1.3 Modes of Operation
For an overview of all operational modes, please refer
to Table 1-1.
1.3.1
POWER-ON RESET MODE
The Power-Down mode can be reached through either
Operation mode or Transmitter-Off mode.
Upon application of VBB, the device enters Power-On
Reset mode (POR). During this mode, the part main-
tains the digital section in a Reset mode and waits until
the voltage on pin VBB rises above the “ON” threshold
(typically 5.75V) to enter to the Ready mode. If during
the operation, the voltage on pin VBB falls below the
“OFF” threshold (typically 4.25V), the part comes back
to the POR mode.
1.3.3
READY MODE
Upon entering Ready mode, the voltage regulator and
receiver-threshold-detect circuit are powered up. The
transmitter remains in an off state. The device is ready
to receive data as soon as the regulator is stabilized,
but not to transmit. If a microcontroller is being driven
by the voltage regulator output, it will go through a POR
and initialization sequence. The LIN pin is in the reces-
sive state for MCP2021/2 and in floating state for
MCP2021P/2P.
1.3.2
POWER-DOWN MODE
In Power-Down mode, the transmitter and the voltage
regulator are off. Only the receiver wake-up from the
LIN bus section, and the CS/LWAKE pin wake-up
circuits, are in operation. This is the lowest power
mode.
The device will stay in Ready mode until the output of
the voltage regulator has stabilized and the CS/LWAKE
pin is true (‘1’). After VREG is stable and CS/LWAKE is
high, MCP2021/2 will enter Operation mode; and
MCP2021P/2P will enter either Operation mode or
Transmitter-Off mode, depending on the level of the
FAULT/TXE pin (refer to Figure 1-3).
If pin CS/LWAKE goes to a high level during Power-
Down mode, the device immediately enters Ready
mode and enables the voltage regulator; and after the
output has stabilized (approximately 0.3 ms to 1.2 ms),
the device goes to Operation mode or Transmitter-Off
mode (see Figure 1-2 for MCP2021/2 and Figure 1-3
for MCP2021P/2P).
1.3.4
OPERATION MODE
In this mode, all internal modules are operational.
The device will go into the Power-Down mode on the
falling edge of CS/LWAKE.
Note:
The above time interval <1.2 ms assumes
12V VBB input and no thermal shutdown
event.
For the MCP2021P/2P devices, the pull-up resistor is
switched on only in this mode.
DS22018G-page 6
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
Because of this, if the LIN bus becomes perma-
nently shorted, it becomes impossible to place
the MCP202X in a low-power state.
1.3.5
TRANSMITTER-OFF MODE
Whenever the FAULT/TXE signal is low, or permanent
dominant on TXD/LBUS is detected, the LBUS
transmitter is off.
3. State Machine Options:
The MCP202XP device is able to enter
Transmitter Off mode from Ready mode without
transitioning through Operation mode. The
MCP202X device must enter Operation mode
from Ready mode. (see State Machine
Diagrams, Figure 1-2 and Figure 1-3 for
details). This capability allows the system
designer to monitor the bus in Ready mode to
determine if the system should transition to
normal operation and connect the internal pull-
up, or if Ready mode was reached due to an
invalid condition. In the case of an invalid
condition, the MCP202XP device can be placed
into Power-Down mode without connecting the
internal pull-up and waking other nodes on the
LIN Bus network.
The transmitter may be re-enabled whenever the
FAULT/TXE signal returns high, either by removing the
internal fault condition or when the CPU returns the
FAULT/TXE high. The transmitter will not be enabled if
the FAULT/TXE pin is brought high when the internal
fault is still present.
If TX-OFF mode is caused by TXD/LBUS permanent
dominant level, the transmitter can recover when the
permanent dominant status disappears.
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption of the bus during times of
uncertain operation.
1.3.6
WAKE-UP
The Wake-Up sub-module observes the LBUS in order
to detect bus activity. Bus activity is detected when the
voltage on the LBUS stays below a threshold of approx-
imately 0.4 VBB for a typical duration of at least 20 µs.
The MCP2021/2 device is level sensitive to LBUS. Dom-
inant level longer than 20 µs will cause the device to
leave the Power-Down mode. The MCP2021P/2P
device is falling-edge sensitive to LBUS. Only the LBUS
transition from recessive to dominant, followed by at
least 20 µs dominant level, can wake up the device.
Putting CS/LWAKE to high level also wakes up the
device. Refer to Figure 1-2 and Figure 1-3.
Note:
To enter Transmitter Off, the system must
set TXE ‘low’ before pulling CS high (see
Figure 1-5). Otherwise, if CS is pulled high
first, the MCP202XP will enter Operation
mode due to the internal pull-up on TXE.
To properly take advantage of the device differences,
the system designer is required to implement some
microcontroller code to the power-up routine. This code
will monitor the status of the LIN bus to determine how
to respond to the dominant signal. It will also determine
if the local LIN node needs to respond or can ‘Listen
Only’. If the local LIN node does not need to respond, it
can enter Transmitter Off mode, disconnecting the
30k pull-up, reducing module current while still
maintaining the ability to properly receive all valid LIN
messages.
1.3.7
DIFFERENCE DETAILS BETWEEN
MCP2021/2 AND MCP2021P/2P
The MCP202XP is a minor variation of the MCP202X
device that adds improved state machine control, as
well as the ability to disconnect the internal 30k pull-
up between LIN and VBB in all modes except normal
operation. These changes allow the system designer
to better handle fault conditions and reduce the overall
system current consumption. The differences between
the two device versions are as follows:
1. Switchable LIN-VBB Pull-Up Resistor:
On the MCP202XP device, the internal 30k
pull-up resistor is disconnected in all modes
except Operation mode. On the MCP202X
device, this pull-up resistor is always connected.
(See the MCP2021/2 Block Diagram and the
MCP2021P/2P Block Diagram for details.)
2. Power Down Wake-up on LIN Traffic:
The MCP202XP device requires a LIN falling
edge to generate a valid Wake condition, due to
bus traffic. The MCP202X device will generate a
Wake anytime LIN is at a valid dominant level.
2005-2013 Microchip Technology Inc.
DS22018G-page 7
MCP2021/2/1P/2P
Power-Down
TX: OFF
RX: OFF
VREG: OFF
CS/LWAKE=0
CS/LWAKE=0
Operation
TX: ON
RX: ON
CS/LWAKE=1
or dominant level on LBUS
VREG: ON
FAULT/TXE=0
Or Faults*
CS/LWAKE=1&
VREG_OK=1
FAULT/TXE=1
&No Faults*
Ready
TX: OFF
RX: ON
POR
TX: OFF
RX: OFF
Transmitter Off
TX: OFF
VREG: ON
VREG: OFF
RX: ON
VREG: ON
Start
bus contention
*Fault: thermal shutdown and TXD/LBUS
FIGURE 1-2:
MCP2021/2 Operational Modes State Diagrams.
Note:
While the device is in shutdown, TXD should not be actively driven high or it may power internal logic
through the ESD diodes and may damage the device.
Power-Down
TX: OFF
RX: OFF
VREG: OFF
CS/LWAKE=0
CS/LWAKE=0
Operation
TX: ON
RX: ON
CS/LWAKE=1
or Falling edge on LBUS
VREG: ON
FAULT/TXE=0
Or Faults*
CS/LWAKE=1&
VREG_OK=1&
FAULT/TXE=1
FAULT/TXE=1
&No Faults*
Ready
TX: OFF
RX: ON
POR
TX: OFF
RX: OFF
Transmitter Off
TX: OFF
VREG: ON
VREG: OFF
RX: ON
VREG: ON
CS=1&VREG_OK=1
&FAULT/TXE=0
Start
bus contention
*Fault: thermal shutdown and TXD/LBUS
FIGURE 1-3:
MCP2021P/2P Operational Modes State Diagrams.
DS22018G-page 8
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
CS_LWAKE
VREG
0
nFAULT_TXE
0
LBUS
State
Ready
Sleep
FIGURE 1-4:
MCP2021P/2P Wake-Up Due to Bus Disconnecting.
2005-2013 Microchip Technology Inc.
DS22018G-page 9
MCP2021/2/1P/2P
tCSactive> = 2S
CS/LWAKE
VREG
FAULT/TXE = 1
Forced internally
FAULT/TXE = 0
FAULT/TXE
Forced externally
LBUS disconnected;
e.g., Master pull-up &
internal resistor off;
LBUS floating.
LBUS
Transmitter-Off
Mode
Power-Down
Mode
STATE
Operation Mode
Forced Power-Down Mode after BUS-OFF
instruction or a longer LIN-Bus inactivity
( > = 4 sec according to LIN specification)
FIGURE 1-5:
Forced Power-Down Mode Sequence for MCP2021P/2P.
DS22018G-page 10
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
TABLE 1-1:
State
OVERVIEW OF OPERATIONAL MODES
Voltage
Transmitter Receiver
Regulator
Operation
Comments
POR
OFF
OFF
OFF
Read VBB; if VBB>5.75V, enter Ready
mode
Ready
OFF
ON
ON
MCP2021/2:
Bus-Off state
If CS/LWAKE is high level, then Operation
mode.
MCP2021P/2P:
If CS/LWAKE is high level and FAULT/TXE
is high level, then Operation mode.
If CS/LWAKE is high level and FAULT/TXE
is low level, then TXOFF mode.
Operation
ON
ON
ON
If CS/LWAKE is low level, then Power-
Down mode.
Normal
Operation
mode
If FAULT/TXE is low level or TXD/LBUS
permanent dominant is detected, then
Transmitter-Off mode.
Power-Down
OFF
OFF
Activity
Detect
OFF
ON
On LIN bus falling, go to Ready mode. On Low-Power
CS/LWAKE high level, go through Ready
mode; then, to either operation or
Transmitter-Off mode (refer to Figure 1-2
and Figure 1-3).
mode
Transmitter-Off
ON
If CS/LWAKE is low level, then Power-
Down mode.
If FAULT/TXE is high, then Operation
mode.
2005-2013 Microchip Technology Inc.
DS22018G-page 11
MCP2021/2/1P/2P
1.4
Pin Descriptions
TABLE 1-1:
PINOUT DESCRIPTIONS
Devices
Function
8-Pin
DFN,
PDIP,
SOIC
14-Pin
PDIP,
SOIC,
TSSOP
Pin
Name
Pin
Type
Normal Operation
VREG
VSS
3
5
3
11
13
4
O
P
Power Output
Ground
VBB
7
P
Battery Supply
TXD
4
I
Transmit Data Input (TTL)
Receive Data Output (CMOS)
LIN bus (Bidirectional)
RXD
1
1
O
LBUS
6
12
2
I/O
TTL
OD
OD
CS/LWAKE
FAULT/TXE
RESET
2
Chip Select (TTL)
8
14
5
Fault Detect Output, Transmitter Enable (OD)
RESET signal Output (OD)
—
Legend: O = Output, P = Power, I = Input, TTL = TTL input buffer, OD = Open-Drain output
The internal LIN receiver observes the activities on the
LIN bus, and generates output signal RXD that follows
the state of the LBUS. A 1st degree with 1 µS time con-
stant (160KhZ), low-pass input filter is placed to
maintain EMI immunity.
1.4.1
POWER OUTPUT (VREG)
Positive Supply Voltage Regulator Output pin.
1.4.2
GROUND (VSS)
BATTERY (VBB)
Ground pin.
1.4.3
1.4.7
CS/LWAKE
Battery Positive Supply Voltage pin. This pin is also the
input for the internal voltage regulator.
Chip Select Input pin. A internal pull-down resistor will
keep the CS/LWAKE pin low. This is done to ensure
that no disruptive data will be present on the bus while
the microcontroller is executing a POR and I/O initial-
ization sequence. The pin must see a high level to
activate the transmitter.
1.4.4
TRANSMIT DATA INPUT (TXD)
The Transmit Data Input pin has an internal pull-up to
VREG. The LIN pin is low (dominant) when TXD is low,
and high (recessive) when TXD is high.
If CS/LWAKE= ‘0’ when the VBB supply is turned on,
the device stays in Ready mode (Low-Power mode). In
Ready mode, both the receiver and the voltage
regulator are on and the LIN transmitter driver is off.
For extra bus security, TXD is internally forced to ‘1’
when VREG is less than 1.8V (typical).
If the thermal protection detects an overtemperature
condition while the signal TXD is low, the transmitter is
shut down. The recovery from the thermal shutdown is
equal to adequate cooling time.
If CS/LWAKE = ‘1’ when the VBB supply is turned on,
the device will proceed to either Operation or Transmit-
ter-Off mode (refer to Figure 1-2 and Figure 1-3) after
the VREG output has stabilized.
1.4.5
RECEIVE DATA OUTPUT (RXD)
This pin may also be used as a local wake-up input
(see Figure 1-6). In this implementation, the microcon-
troller will set the I/O pin that controls the CS/LWAKE
as an high-impedance input. The internal pull-down
resistor will keep the input low. An external switch, or
other source, can then wake up the transceiver and the
microcontroller.
The Receive Data Output pin is a standard CMOS
output and follows the state of the LIN pin.
1.4.6
LIN BUS
The bidirectional LIN bus Interface pin is the driver unit
for the LIN pin and is controlled by the signal TXD. LIN
has an open collector output with a current limitation.
To reduce EMI, the edges during the signal changes
are slope-controlled. To further reduce radiated emis-
sions, the LBUS pin has corner-rounding control for both
falling and rising edges.
Note:
CS/LWAKE should not be tied directly to
VREG as this could force the MCP202X
into Operation mode before the
microcontroller is initialized.
DS22018G-page 12
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
This pin has an internal pull-up resistor of
approximately 750 k. The internal pull-up resistor is
too weak. We recommend adding a 10 kOhm external
pull-up resistor to ensure a logic high level.
1.4.8
FAULT/TXE
Fault Detect Output and Transmitter Enable Input
bidirectional pin.
This pin is an open-drain output. Its state is defined as
shown in Table 1-2. The transmitter driver is disabled
whenever this pin is low (‘0’), either from an internal
fault condition or by external drive. This allows the
transmitter to be placed in an off state and still allow the
voltage regulator to operate. Refer to Table 1-1.
Note 1: The FAULT/TXE pin is true (0) whenever
the internal circuits have detected a short
or thermal excursion and have disabled
the LBUS output driver.
2: FAULT/TXE is true (0) when VREG not OK
The FAULT/TXE also signals a mismatch between the
TXD input and the LBUS level. This can be used to
detect a bus contention. Since the bus exhibits a
propagation delay, the sampling of the internal
compare is debounced to eliminate false faults.
and has disabled the LBUS output driver.
The FAULT/TXE pin sampled at a rate faster than every
10 µs.
TABLE 1-2:
FAULT/TXE TRUTH TABLE
FAULT/TXE
TXD
In
RXD
Out
LINBUS
I/O
Thermal
Override
Definition
External
Input
Driven
Output
L
H
VBB
OFF
H
L
FAULT, TXD driven low, LINBUS shorted to
VBB (Note 1)
H
L
H
x
H
L
L
x
VBB
GND
GND
VBB
OFF
OFF
OFF
ON
x
H
H
H
H
L
H
H
H
L
OK
OK
OK, data is being received from the LINBUS
FAULT, transceiver in thermal shutdown
x
x
VBB
x
NO FAULT, the CPU is commanding the
transceiver to turn off the transmitter driver
Legend: x = don’t care
Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault
reporting during bus propagation delays.
1.4.9
RESET
RESET is an open-drain output pin. This pin reflects an
internal signal that tracks the internal system voltage
has reached a valid, stable level.
As long as the internal voltage is valid, this pin will keep
high impedance. When the system voltage drops below
the minimum required, the voltage regulator will shut
down and immediately convert the RESET output to
short to GND. A pull-up resistor is needed to change
the output to high/low voltage. When connected to a
microcontroller input, this can provide a warning that
the voltage regulator is shutting down (see Figure 1-2).
Alternately, it can act as an external brown-out by
connecting the RESET output to MCLR (see Figure 1-
2). In addition to monitoring the internal voltage,
RESET is asserted immediately upon entering the
Power-Down mode.
2005-2013 Microchip Technology Inc.
DS22018G-page 13
MCP2021/2/1P/2P
1.5
Typical Applications
+12
+12
(5)
RTP
WAKE-UP
(5)
Master Node Only
+12
43V
CF
CG
220 k
VREG
TXD
VDD
VBB
TXD
1 k
(6)
LBUS
LIN Bus
RXD
I/O
RXD
(4)
27V
CS/LWAKE
FAULT/TXE
(3)
I/O
VSS
100 pF
Note 1: See Figure 2-3 for correct capacity and ESR for stable operation.
2: CF is the filter capacitor for the external voltage supply.
3: This diode is only needed if CS/LWAKE is connected to a 12V supply.
4: Transient suppressor diode. Vclamp L = 43V.
5: These components are required for additional load dump protection above 43V.
6: We recommend adding an external 10k pull-up resistor.
FIGURE 1-6:
Typical MCP2021/MCP2021P Application.
DS22018G-page 14
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
+12
+12
(5)
RTP
WAKE-UP
(5)
Master Node Only
+12
43V
CF
CG
220 k
VDD
TXD
VREG
TXD
VBB
1 k
LBUS
LIN Bus
RXD
I/O
RXD
(4)
27V
CS/LWAKE
FAULT/TXE
(3)
I/O
INT or MCLR
RESET
VSS
100 pF
(6)
VDD
Note 1: See Figure 2-3 for correct capacity and ESR for stable operation.
2: CF is the filter capacitor for the external voltage supply.
3: This diode is only needed if CS/LWAKE is connected to a 12V supply.
4: Transient suppressor diode. Vclamp L = 43V.
5: These components are required for additional load dump protection above 43V.
6: Required if CPU does not have internal pull-up.
FIGURE 1-7:
Typical MCP2022/MCP2022P Application.
40m
+ Return
LIN bus
1 k
VBB
LIN bus
MCP202X
LIN bus
MCP202X
LIN bus
MCP202X
LIN bus
MCP202X
Slave 1
µC
Slave 2
µC
Slave n <16
µC
Master
µC
FIGURE 1-8:
Typical LIN Network Configuration.
2005-2013 Microchip Technology Inc.
DS22018G-page 15
MCP2021/2/1P/2P
ing of the POR trip point. The MCP2021 will then
monitor VBB and turn on the regulator when VBB rises
above 5.75, again.
1.6
Internal Voltage Regulator
1.6.1
5.0V REGULATOR
When the input voltage (VBB) drops below the differen-
tial needed to provide stable regulation, the output
VREG) will track the input down to approximately
+4.25V. The regulator will turn off the output at this
point. This will allow PIC microcontrollers with internal
POR circuits to generate a clean arming of the POR trip
point. The regulator output will stay off until VBB is
The MCP2021 has a low-drop-out voltage, positive
regulator capable of supplying 5.00 VDC ±3% at up to
50 mA of load current, over the entire operating
temperature range of -40°C to +125°C. With a load
current of 50 mA, the minimum input to output voltage
differential required for the output to remain in
regulation is typically +0.5V (+1V maximum over the
full operating temperature range). Quiescent current is
less than 100 µA with a full 50 mA load current when
the input to output voltage differential is greater than
+3.00V.
above +5.75 VDC
.
In the start phase, the device must detect at least 5.75V
to initiate operation during power up. In the Power-
Down mode, the VBB monitor will be turned off.
The regulator requires an external output bypass
capacitor for stability. See Figure 2-3 for correct
capacity and ESR for stable operation.
Note:
The regulator has an overload current
limiting of approximately 100 mA. During a
short circuit, the VREG is monitored. If
VREG is lower than 3.5V, the VREG will turn
off. After a recovery time of about three
milliseconds, the VREG will be checked
again. If there is no short circuit (VREG
>3.5V), the VREG will be switched back on.
Designed for automotive applications, the regulator will
protect itself from double-battery jumps and up to +43V
load dump transients. The voltage regulator has both
short-circuit and thermal-shut-down protection built in.
Regarding the correlation between VBB, VREG and IDD,
please refer to Figure 1-10 — Figure 1-12. When the
input voltage (VBB) drops below the differential needed
to provide stable regulation, the output VREG will track
the input down to approximately 3.5V, at which point
the regulator will turn off. This will allow microcontrol-
lers with internal POR circuits to generate a clean arm-
The regulator has a thermal shutdown. If the thermal
protection circuit detects an overtemperature condition,
and the signals TXD and RXD are LOW, or TXD is HIGH,
the regulator will shut down. The recovery from the
thermal shutdown is equal to adequate cooling time.
Pass
Element
VBB
VREG
Sampling
Network
Fast
Transient
Loop
Buffer
VSS
VREF
FIGURE 1-9:
Voltage Regulator Block Diagram.
DS22018G-page 16
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
1.6.2
3.3V REGULATOR
A metal option provides for a alternate 3.30 VDC ±3%
at up to 50 mA of load current over the entire operating
temperature range of -40°C to +125°C. All
specifications given above for the 5.0V operation apply
except for any difference noted here.
The same input tracking of 4.25V applies the 3.3V
regulator.
Note:
The regulator has an overload current
limiting of approximately 100 mA. If VREG
is lower than 2.5V, the VREG will turn off.
VBB
V
8
6
4
2
0
t
VREG
V
5.0
3.5
3
0
t
(1)
(2)
(3)
Note 1: Start-up, VBB < 5.75V, regulator off.
2: VBB > 5.75V, regulator on.
3: VBB 5.5V, regulator tracks VBB.
4: VBB < 4.25V, regulator will turn off.
FIGURE 1-10:
Voltage Regulator Output on POR.
2005-2013 Microchip Technology Inc.
DS22018G-page 17
MCP2021/2/1P/2P
VBB
V
12
8
6
4
3.5
2
0
t
VREG
V
5
4
3.5
3
0
t
(1)
(2) (3) (4)
Note 1: Voltage regulator on.
2: VBB 5.5V, regulator tracks VBB until VBB < 4.25V.
3: VREG < 3.5V, regulator is off.
4: VBB > 5.75V, regulator on.
FIGURE 1-11:
Voltage Regulator Output on Power Dip.
DS22018G-page 18
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
IREG
mA
50
0
t
VREG
V
6
5.0
3.5
3
0
t
(1)
Note 1: IREG less than 50 mA, regulator on.
2: After IREG exceeds IREGmax, voltage regulator output will be reduced until VREG off is reached.
(2)
FIGURE 1-12:
Voltage Regulator Output on Overcurrent Situation.
1.7 ICSP™ Considerations
The following should be considered when the
MCP2021/2/1P/2P is connected to pins supporting
in-circuit programming:
• Power used for programming the microcontroller
can be supplied from the programmer or from the
MCP2021/2/1P/2P.
• The voltage on VREG should not exceed the
maximum output voltage of VREG.
2005-2013 Microchip Technology Inc.
DS22018G-page 19
MCP2021/2/1P/2P
NOTES:
DS22018G-page 20
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
2.0
2.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VIN DC Voltage on RXD and TXD........................................................................................................-0.3 to VREG+0.3V
VIN DC Voltage on FAULT and RESET.........................................................................................................-0.3 to +5.5V
VIN DC Voltage on CS/LWAKE.......................................................................................................................-0.3 to +43V
VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) .....................................-0.3 to +43V
VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-200V
VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V
VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-300V
VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V
VBB Battery Voltage, continuous....................................................................................................................-0.3 to +30V
VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V
VLBUS Bus Voltage, transient (Note 1)............................................................................................................-27 to +43V
ILBUS Bus Short Circuit Current Limit....................................................................................................................200 mA
ESD protection on LIN, VBB (IEC 61000-4-2, 330 Ohm, 150 pF) (Note 3).............................................. minimum ±9 kV
ESD protection on LIN, VBB (Charge Device Model) (Note 2)..............................................................................±1500V
ESD protection on LIN, VBB (Human Body Model, 1 kOhm, 100 pF) (Note 4)....................................................... ±8 kV
ESD protection on LIN, VBB (Machine Model) (Note 2)..........................................................................................±800V
ESD protection on all other pins (Human Body Model) (Note 2) ............................................................................> 4 kV
Maximum Junction Temperature............................................................................................................................. 150C
Storage Temperature ..................................................................................................................................-55 to +150C
Note 1: ISO 7637/1 load dump compliant (t < 500 ms).
2: According to JESD22-A114-B.
3: According to IBEE, without bus filter.
4: Limited by Test Equipment.
† NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2005-2013 Microchip Technology Inc.
DS22018G-page 21
MCP2021/2/1P/2P
2.2
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
DC Specifications
TA = -40°C to +125°C
CLOADREG = 10 µF
Parameter
Power
Sym
Min
Typ
Max
Units
Conditions
VBB Quiescent Operating
Current
IBBQ
115
210
µA
IOUT = 0 mA,
LBUS recessive
—
—
120
90
215
190
µA
µA
VOUT = 3.3V
VBB Transmitter-Off
Current
IBBTO
IBBPD
With VREG on, transmitter
off, receiver on, FAULT/TXE
= VIL, CS = VIH
—
—
95
16
210
26
µA
µA
VOUT = 3.3V
VBB Power-Down Current
With VREG powered-off,
receiver on and transmitter
off, FAULT/TXE = VIH,
TXD = VIH, CS = VIL)
—
—
VBB Current with VSS
Floating
IBBNOGND
VIH
-1
1
mA VBB = 12V, GND to VBB,
VLIN = 0-18V
Microcontroller Interface
High-Level Input Voltage
(TXD, FAULT/TXE)
2.0 or
(0.25VREG
+ 0.8)
VREG
+0.3
V
V
—
—
—
—
—
—
—
—
—
Low-Level Input Voltage
(TXD, FAULT/TXE)
VIL
IIH
-0.3
-2.5
-10
0.15 VREG
High-Level Input Current
(TXD, FAULT/TXE)
—
—
µA
µA
µA
V
Input voltage = 0.8*VREG
Input voltage = 0.2*VREG
Low-Level Input Current
(TXD, FAULT/TXE)
IIL
Pull-up Current on Input
(TXD)
IPUTXD
VIH
-3.0
0.7 VREG
-0.3
—
—
~800 k internal pull-up to
VREG @ VIH = 0.7*VREG
High-Level Input Voltage
(CS/LWAKE)
VBB
0.3VREG
7.0
Through a current-limiting
resistor
Low-Level Input Voltage
(CS/LWAKE)
VIL
V
High-Level Input Current
(CS/LWAKE)
IIH
µA
µA
µA
Input voltage = 0.8*VREG
Input voltage = 0.2*VREG
Low-Level Input Current
(CS/LWAKE)
IIL
—
3.0
Pull-down Current on
Input (CS/LWAKE)
IPDCS
—
6.0
~1.3M internal pull-down
to VSS @ VIH = 3.5V
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB).
2: For design guidance only, not tested.
3: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
DS22018G-page 22
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
2.2
DC Specifications (Continued)
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
DC Specifications
TA = -40°C to +125°C
CLOADREG = 10 µF
Parameter
Sym
Min
Typ
Max
Units
Conditions
Bus Interface
—
—
—
—
High-Level Input Voltage
Low-Level Input Voltage
Input Hysteresis
VIH(LBUS)
VIL(LBUS)
VHYS
0.6 VBB
18
V
V
V
Recessive state
-8
—
0.4 VBB
0.175 VBB
200
Dominant state
VIH(LBUS) - VIL(LBUS)
Low-Level Output
Current
IOL(LBUS)
40
mA Output voltage = 0.1 VBB,
VBB = 12V
—
—
—
—
—
Pull-up Current on Input
IPU(LBUS)
ISC
5
50
180
200
µA
~30 k internal pull-up
@ VIH (LBUS) = 0.7 VBB
Short Circuit Current
Limit
mA (Note 1)
High-Level Output
Voltage
VOH(LBUS)
0.8 VBB
—
VBB
V
V
VOH(LBUS) must be at least
0.8 VBB
Low-Level Output
Voltage
VOLLO
(LBUS)
0.2 VBB
—
Input Leakage Current (at IBUS_PAS_DOM
the receiver during
-1
mA Driver off,
VBUS = 0V,
dominant bus level)
VBAT = 12V
—
—
Leakage Current
(disconnected from
ground)
IBUS_NO_GND
IBUS
-1
+1
10
mA
µA
GNDDEVICE = VBAT,
0V < VBUS < 18V,
VBAT = 12V
Leakage Current
(disconnected from VBAT)
—
VBAT = GND,
0 < VBUS < 18V,
TA = -40°C to +85°C
(Note 3)
50
µA
V
TA = +85°C to +125°C
Receiver Center Voltage
Slave Termination
VBUS_CNT
Rslave
0.475 VBB
20
0.5
VBB
0.525 VBB
VBUS_CNT = (VIL (LBUS) +
VIH (LBUS))/2
30
47
k
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB).
2: For design guidance only, not tested.
3: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
2005-2013 Microchip Technology Inc.
DS22018G-page 23
MCP2021/2/1P/2P
2.2
DC Specification (Continued)
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
DC Specifications
TA = -40°C to +125°C
CLOADREG = 10 µF
Parameter
Sym
Min
Typ
Max
Units
Conditions
Voltage Regulator - 5.0V
Output Voltage
VOUT
4.85
—
5.00
10
5.15
50
V
0 mA < IOUT < 50 mA,
Load Regulation
VOUT2
mV 5 mA < IOUT < 50 mA
refer to Section 1.6
“Internal Voltage
Regulator”
Quiescent Current
IVRQ
—
—
—
—
25
50
µA
dB
IOUT = 0 mA, (Note 2)
Power Supply Ripple
Reject
PSRR
1 VPP @10-20 kHz
CLOAD = 10 µf,
ILOAD = 50 mA
Output Noise Voltage
eN
—
—
100
µVRMS 10 Hz – 40 MHz
CFILTER = 10 µf,
CBP = 0.1 µf, CLOAD 10 µf,
ILOAD = 50 mA
Shutdown Voltage
VSD
VBB
3.5
6.0
—
—
4.0
V
V
See Figure 1-8
Input Voltage to Maintain
Regulation
18.0
Input Voltage to Turn Off
Output
VOFF
VON
4.0
5.5
—
—
4.5
6.0
V
V
Input Voltage to Turn On
Output
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB).
2: For design guidance only, not tested.
3: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
60
12V DFN
50
18V DFN
12V SOIC
40
18V SOIC
30
20
10
0
Temperature (°C)
FIGURE 2-1:
MCP2021-500 Safe Operating Range.
DS22018G-page 24
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
2.2
DC Specification (Continued)
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
DC Specifications
TA = -40°C to +125°C
CLOADREG = 10 µF
Parameter
Sym
Min
Typ
Max
Units
Conditions
Voltage Regulator - 3.3V
Output Voltage
VOUT
3.20
—
3.30
10
3.40
50
V
0 mA < IOUT < 50 mA
Line Regulation
VOUT1
mV IOUT = 1 mA,
6.0V < VBB < 18V
Load Regulation
VOUT2
—
10
50
mV 5 mA < IOUT < 50 mA
Refer to Section 1.6
“Internal Voltage
Regulator”
Quiescent Current
IVRQ
—
—
—
—
25
50
µA
dB
IOUT = 0 mA, (Note 2)
Power Supply Ripple
Reject
PSRR
1 VPP @10-20 kHz
CLOAD = 10 µf,
ILOAD = 50 mA
Output Noise Voltage
eN
—
—
100
µVRMS 10 Hz – 40 MHz
/Hz CFILTER = 10 µf, CBP =
0.1 µf CLOAD = 10 µf,
ILOAD = 50 mA
Shutdown Voltage
VSD
VBB
2.5
6.0
—
—
2.7
V
V
See Figure 1-8
Input Voltage to Maintain
Regulation
18.0
Input Voltage to Turn Off
Output
VOFF
VON
4.0
5.5
—
—
4.5
6.0
V
V
Input Voltage to Turn On
Output
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB).
2: For design guidance only, not tested.
3: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
60
12V DFN
50
18V DFN
12V SOIC
40
18V SOIC
30
20
10
0
Temperature (°C)
FIGURE 2-2:
MCP2021-330 Safe Operating Range.
2005-2013 Microchip Technology Inc.
DS22018G-page 25
MCP2021/2/1P/2P
ESR Curves
10
Instable
Unstable
Stable only
1
0.1
with Tantalum or
Electrolytic cap.
Stable with
Tantalum,
Electrolytic and
Ceramic cap.
Unstable
Instable
0.01
0.001
Unstable
Instable
1000
0.1
1
100
10
Load Capacitor [uF]
FIGURE 2-3:
ESR Curves for Load Capacitor Selection.
DS22018G-page 26
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
2.3
AC Specification
VBB = 6.0V to 18.0V; TA = -40°C to +125°C
AC CHARACTERISTICS
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Bus Interface - Constant Slope Time Parameters
Slope rising and falling
edges
tSLOPE
tTRANSPD
tRECPD
3.5
—
—
—
—
22.5
4.0
µs
µs
µs
µs
7.3V <= VBB <= 18V
Propagation Delay of
Transmitter
—
tTRANSPD = max (tTRANSPDR or
tTRANSPDF)
Propagation Delay of
Receiver
—
6.0
tRECPD = max (tRECPDR or
tRECPDF)
Symmetry of Propagation
Delay of Receiver rising
edge w.r.t. falling edge
tRECSYM
-2.0
2.0
tRECSYM = max (tRECPDF -
tRECPDR)
Symmetry of Propagation
Delay of Transmitter rising
edge w.r.t. falling edge
tTRANSSYM
tFAULT
-2.0
—
2.0
µs
µs
tTRANSSYM = max (tTRANSPDF -
tTRANSPDR)
Time to sample of FAULT/
TXE for bus conflict reporting
—
—
—
32.5
—
tFAULT = max (tTRANSPD +
tSLOPE + tRECPD)
Duty Cycle 1 @20.0 kbit/sec
Duty Cycle 2 @20.0 kbit/sec
Duty Cycle 3 @10.4 kbit/sec
Duty Cycle 4 @10.4 kbit/sec
39.6
%tBIT CBUS;RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.744 x VBB,
THDOM(MAX) = 0.581 x VBB,
VBB =7.0V - 18V; tBIT = 50 µs.
D1 = tBUS_REC(MIN) / 2 x tBIT)
—
41.7
—
—
—
—
58.1
%tBIT CBUS;RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.284 x VBB,
THDOM(MAX) = 0.422 x VBB,
VBB =7.6V - 18V; tBIT = 50 µs.
D2 = tBUS_REC(MAX) / 2 x tBIT)
—
%tBIT CBUS;RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.778 x VBB,
THDOM(MAX) = 0.616 x VBB,
VBB =7.0V - 18V; tBIT = 96 µs.
D3 = tBUS_REC(MIN) / 2 x tBIT)
59.0
%tBIT CBUS;RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.251 x VBB,
THDOM(MAX) = 0.389 x VBB,
VBB =7.6V - 18V; tBIT = 96 µs.
D4 = tBUS_REC(MAX) / 2 x tBIT)
2005-2013 Microchip Technology Inc.
DS22018G-page 27
MCP2021/2/1P/2P
2.3
AC Specification (Continued)
VBB = 6.0V to 18.0V; TA = -40°C to +125°C
AC CHARACTERISTICS
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Voltage Regulator
Bus Activity Debounce Time
tBDB
5
10
20
µs
µs
Bus debounce time
Bus Activity to Voltage
Regulator Enabled
tBACTVE
100
250
500
After bus debounce time
Voltage Regulator Enabled
to Ready
tVEVR
tCSOR
(Note 1)
—
—
—
—
1200
500
µs
µs
Chip Select to Operation
Ready
(Note 1, 2)
Chip Select to Power-Down
Short-Circuit to Shut-Down
RESET Timing
tCSPD
—
—
—
80
µs
µs
tSHUTDOWN
20
100
VREG OK Detect to RESET
Inactive
tRPU
tRPD
—
—
—
—
10.0
10.0
µs
µs
VREG OK Detect to RESET
Active
Note 1: Time depends on external capacitance and load.
2: Design guidance only, not tested.
2.4
Thermal Specifications
THERMAL CHARACTERISTICS
Parameter
Symbol
Typ
Max
Units
Test Conditions
—
—
Recovery Temperature
RECOVERY
SHUTDOWN
tTHERM
+140
+150
1.5
C
C
ms
Shutdown Temperature
Short Circuit Recovery Time
Thermal Package Resistances
Thermal Resistance, 8L-DFN
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
5.0
JA
JA
JA
JA
JA
JA
35.7
89.3
149.5
70
—
—
—
—
—
—
C/W
C/W
C/W
C/W
C/W
C/W
95.3
100
Note 1: The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum
allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)JA. If this dissipation is
exceeded, the die temperature will rise above 150C and the MCP2021 will go into thermal shutdown.
DS22018G-page 28
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
2.5
Timing Diagrams and Specifications
TXD
50%
50%
LBUS
.95VLBUS
.50VBB
.0.4VBB
0.0V
TTRANSPDR
TTRANSPDF
TRECPDF
TRECPDR
50%
RXD
50%
Internal TXD/RXD
Match
Match
Match
Match
Match
Compare
FAULT Sampling
T
T
FAULT
FAULT
Hold
Value
Hold
Value
FAULT/TXE Output
Stable
Stable
Stable
FIGURE 2-4:
Bus Timing Diagram.
CS/LWAKE
T
CSOR
VREG
VOUT
TCSPD
FIGURE 2-5:
Regulator CS/LWAKE Timing Diagram.
2005-2013 Microchip Technology Inc.
DS22018G-page 29
MCP2021/2/1P/2P
TVEVR
LBUS
0.4VBB
TBDB + TBACTVE
VREG
VOUT
FIGURE 2-6:
Regulator BUS WAKE Timing Diagram.
6.0V
5.0V
VBB
5.0V
4.0V
3.5V
VREG
TRPD
TRPD
RESET
TRPU
TRPU
FIGURE 2-7:
RESET Timing Diagram.
DS22018G-page 30
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
CS/LWAKE
TCSOR
VREG
VOUT
TRPU
TCSPD
RESET
FIGURE 2-8:
CS/LWAKE to RESET Timing Diagram.
0.2
0.15
0.1
Vbb = 6V
Vbb = 7.3V
Vbb = 12V
Vbb = 14.4V
Vbb = 18V
0.05
0
-40C
25C
85C
125C
Temperature (°C)
FIGURE 2-9:
Typical IBBQ vs. Temperature.
2005-2013 Microchip Technology Inc.
DS22018G-page 31
MCP2021/2/1P/2P
0.18
0.16
0.14
0.12
0.1
Vbb = 6V
0.08
0.06
0.04
0.02
0
Vbb = 7.3V
Vbb = 12V
Vbb = 14.4V
Vbb = 18V
-40C
25C
85C
125C
Temperature (°C)
FIGURE 2-10:
Typical IBBTO vs Temperature.
0.025
0.02
0.015
0.01
0.005
0
Vbb = 6V
Vbb = 7.3V
Vbb = 12V
Vbb = 14.4V
Vbb = 18V
-40C
25C
85C
125C
Temperature (°C)
FIGURE 2-11:
Typical IBBPD vs. Temperature.
DS22018G-page 32
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
3.0
3.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (4x4x0.9 mm)
Example
202150
E/MD
1033
256
XXXXXX
XXXXXX
3
MCP2021
202150
MCP2021P
2021P5
YYWW
NNN
PIN 1
PIN 1
8-Lead DFN-S (6x5x0.9 mm)
Example
2021500
3
E/MF
MCP2021
2021500
1033
256
NNN
PIN 1
PIN 1
8-Lead PDIP (300 mil)
Example
2021500
XXXXXXXX
XXXXXNNN
3
MCP2021
2021500
E/P 256
1033
YYWW
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2005-2013 Microchip Technology Inc.
DS22018G-page 33
MCP2021/2/1P/2P
3.1 Package Marking Information (Continued)
8-Lead SOIC (3.90 mm)
Example
2021500E
SN 1033
MCP2021
MCP2021P
3
2021500E
2021P50E
256
NNN
14-Lead PDIP (300 mil)
Example
MCP2022-500
3
MCP2022
MCP2022P
E/P
MCP2022-500 MCP2022P-500
1033256
14-Lead SOIC (3.90 mm)
Example
MCP2022-500
3
MCP2022
E/SL
MCP2022-500
1033256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS22018G-page 34
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
3.1 Package Marking Information (Continued)
14-Lead TSSOP (4.4 mm)
Example
2022500E
1033
XXXXXXXX
MCP2022
MCP2022P
2022P50E
YYWW
NNN
2022500E
256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2005-2013 Microchip Technology Inc.
DS22018G-page 35
MCP2021/2/1P/2P
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
DS22018G-page 36
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
2005-2013 Microchip Technology Inc.
DS22018G-page 37
MCP2021/2/1P/2P
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22018G-page 38
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
e
D
L
b
N
N
K
E
E2
EXPOSED PAD
NOTE 1
NOTE 1
1
2
1
2
D2
BOTTOM VIEW
TOP VIEW
A
A3
A1
NOTE 2
Units
MILLIMETERS
Dimension Limits
MIN
NOM
8
1.27 BSC
0.85
MAX
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Length
Overall Width
N
e
A
A1
A3
D
0.80
0.00
1.00
0.05
0.01
0.20 REF
5.00 BSC
6.00 BSC
4.00
2.30
0.40
E
Exposed Pad Length
Exposed Pad Width
Contact Width
Contact Length
Contact-to-Exposed Pad
D2
E2
b
L
K
3.90
2.20
0.35
0.50
0.20
4.10
2.40
0.48
0.75
–
0.60
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-122B
2005-2013 Microchip Technology Inc.
DS22018G-page 39
MCP2021/2/1P/2P
ꢀꢁꢂꢃꢄ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢄꢃꢈꢂꢂꢆꢉꢄꢃꢊꢋꢈxꢋꢌꢆꢃqꢂꢋꢍꢉꢌꢎꢃꢊꢏꢆꢋꢆꢃꢆꢆꢃꢄꢅꢆꢃꢐꢍꢈꢂꢁꢈꢅꢍꢊꢃQꢋꢈxꢋꢌꢍꢉꢌꢃꢑꢊꢆꢈꢍsꢍꢈꢋꢄꢍꢁꢉꢃꢏꢁꢈꢋꢄꢆqꢃꢋꢄꢃ
ꢅꢄꢄꢊ)ꢒꢒꢓꢇꢍꢈꢂꢁꢈꢅꢍꢊꢓꢈꢁꢇꢒꢊꢋꢈxꢋꢌꢍꢉꢌ
DS22018G-page 40
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
A1
c
e
eB
b1
b
Units
INCHES
Dimension Limits
MIN
NOM
8
.100 BSC
–
.130
–
.310
.250
.365
.130
.010
.060
.018
–
MAX
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
N
e
A
A2
A1
E
E1
D
L
c
b1
b
eB
–
.210
.195
–
.115
.015
.290
.240
.348
.115
.008
.040
.014
–
.325
.280
.400
.150
.015
.070
.022
.430
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B
2005-2013 Microchip Technology Inc.
DS22018G-page 41
MCP2021/2/1P/2P
Note: For the moꢔt current package drawingꢔ, pleaꢔe ꢔee the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22018G-page 42
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
Note: For the moꢔt current package drawingꢔ, pleaꢔe ꢔee the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2005-2013 Microchip Technology Inc.
DS22018G-page 43
MCP2021/2/1P/2P
ꢅꢆꢇꢃꢈꢉꢊꢋꢌꢈꢍꢂꢎꢏꢊꢐꢑꢈꢌꢌꢊꢒꢓꢂꢌꢎꢔꢃꢊꢕꢐꢀꢖꢊꢗꢊꢀꢈꢘꢘꢁꢙꢚꢊꢛꢜꢝꢞꢊꢑꢑꢊꢟꢁꢉꢠꢊꢡꢐꢒꢢꢣꢤ
ꢀꢁꢂꢃꢄ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢄꢃꢈꢂꢂꢆꢉꢄꢃꢊꢋꢈxꢋꢌꢆꢃqꢂꢋꢍꢉꢌꢎꢃꢊꢏꢆꢋꢆꢃꢆꢆꢃꢄꢅꢆꢃꢐꢍꢈꢂꢁꢈꢅꢍꢊꢃQꢋꢈxꢋꢌꢍꢉꢌꢃꢑꢊꢆꢈꢍsꢍꢈꢋꢄꢍꢁꢉꢃꢏꢁꢈꢋꢄꢆqꢃꢋꢄꢃ
ꢅꢄꢄꢊ)ꢒꢒꢓꢇꢍꢈꢂꢁꢈꢅꢍꢊꢓꢈꢁꢇꢒꢊꢋꢈxꢋꢌꢍꢉꢌ
DS22018G-page 44
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
c
A1
b1
b
e
eB
Units
Dimension Limits
INCHES
NOM
14
.100 BSC
–
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
–
.210
.195
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.290
.240
.735
.115
.008
.045
.014
–
.130
–
.310
.250
.750
.130
.010
.060
.018
–
.325
.280
.775
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing §
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-005B
2005-2013 Microchip Technology Inc.
DS22018G-page 45
MCP2021/2/1P/2P
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22018G-page 46
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2005-2013 Microchip Technology Inc.
DS22018G-page 47
MCP2021/2/1P/2P
ꢀꢁꢂꢃꢄ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢄꢃꢈꢂꢂꢆꢉꢄꢃꢊꢋꢈxꢋꢌꢆꢃqꢂꢋꢍꢉꢌꢎꢃꢊꢏꢆꢋꢆꢃꢆꢆꢃꢄꢅꢆꢃꢐꢍꢈꢂꢁꢈꢅꢍꢊꢃQꢋꢈxꢋꢌꢍꢉꢌꢃꢑꢊꢆꢈꢍsꢍꢈꢋꢄꢍꢁꢉꢃꢏꢁꢈꢋꢄꢆqꢃꢋꢄꢃ
ꢅꢄꢄꢊ)ꢒꢒꢓꢇꢍꢈꢂꢁꢈꢅꢍꢊꢓꢈꢁꢇꢒꢊꢋꢈxꢋꢌꢍꢉꢌ
DS22018G-page 48
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
Note: For the moꢔt current package drawingꢔ, pleaꢔe ꢔee the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2005-2013 Microchip Technology Inc.
DS22018G-page 49
MCP2021/2/1P/2P
Note: For the moꢔt current package drawingꢔ, pleaꢔe ꢔee the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22018G-page 50
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2005-2013 Microchip Technology Inc.
DS22018G-page 51
MCP2021/2/1P/2P
NOTES:
DS22018G-page 52
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
Revision B (August 2007)
APPENDIX A: REVISION HISTORY
The following is the list of modifications:
1. Modified Block Diagram on page 2.
Revision G (July 2013)
The following has been modified:
2. Section 1.3.5
“Transmitter-OFF
Mode”:
Deleted text in 1st paragraph.
1. Added Note 2 in Section 2.3 “AC Specifica-
tion”.
3. Example 1-6: Removed +5V notation.
2. Added pull up to nFAULT/TXE pin in
4. Section 1.4 “Pin Descriptions”: Removed 10-
Section 1.4
“Pin
Descriptions”
and
pin DFN, MSOP column from table.
Section 1.5 “Typical Applications”.
5. Section 1.4.8 “Fault/TXE”: Deleted text from
2nd paragraph.
Revision F (January 2012)
6. Section 3.0 “Packaging Information”: Added
8-lead 4x4 and 6x5 DFN and 14-lead TSSOP
packages. Updated package outline drawings
and added drawings for 8-lead DFN and 14-lead
TSSOP drawings.
The following has been modified:
1. Added the MCP2021P and MCP2022P options
and related information throughout the
document.
Revision A (November 2005)
Revision E (February 2009)
Original Release of this Document.
The following is the list of modifications:
1. Added Example 1-7 and Example 1-8.
2. Updated Section 1.4.9 “RESET”.
3. Updated Section 1.7 “ICSP™ Consider-
ations”.
4. Updated Section 2.1 “Absolute Maximum
Ratings†”.
5. Updated Section 2.2 “DC Specifications” and
Section 2.3 “AC Specification”.
6. Added FIGURE 2-3: “ESR Curves for Load
Capacitor Selection.”.
7. Updated the Product Identification System
section.
Revision D (July 2008)
The following is the list of modifications:
1. Updated ESD specs under ‘Absolute DC’.
2. Updated notes in Example 1-1.
3. Updated Package Outline Drawings.
Revision C (April 2008)
The following is the list of modifications:
1. Added LIN2.1 and J2602 compliance statement
to Features section.
2. Added recommended RC network for CS/
LWAKE in Example 1-1.
3. Updated 2.1 “Absolute Maximum Ratings†”
to reflect current test results.
4. Updated 2.2 “DC Specifications” and 2.3 “AC
Specification” 2.3 AC Specifications to reflect
current production device.
5. Added 8-Lead SOIC Landing Pattern Outline
drawing.
2005-2013 Microchip Technology Inc.
DS22018G-page 53
MCP2021/2/1P/2P
NOTES:
DS22018G-page 54
2005-2013 Microchip Technology Inc.
MCP2021/2/1P/2P
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
–X
/XX
a)
b)
c)
d)
e)
f)
MCP2021-330E/SN: 3.3V, 8L-SOIC pkg.
MCP2021-330E/P: 3.3V, 8L-PDIP pkg.
Temperature
Range
Package
MCP2021-500E/MF: 5.0V, 8L-DFN-S pkg.
MCP2021-500E/SN: 5.0V, 8L-SOIC pkg.
MCP2021-500E/MD: 5.0V, 8L-DFN pkg.
Device:
MCP2021: LIN Transceiver with Voltage Regulator; wakes up on
dominant level of LIN bus.
MCP2021-500E/P:
5.0V, 8L-PDIP pkg.
MCP2021T: LIN Transceiver with Voltage Regulator; wakes up on
dominant level of LIN bus.
g)
MCP2021T-330E/SN: Tape and Reel,
3.3V, 8L-SOIC pkg.
(Tape and Reel) (SOIC only)
h)
i)
MCP2021T-500E/MD: Tape and Reel,
5.0V, 8L-DFN pkg.
MCP2022: LIN Transceiver with Voltage Regulator, and RESET
pin; wakes up on dominant level of LIN bus.
MCP2021T-500E/SN: Tape and Reel,
5.0V, 8L-SOIC pkg.
MCP2022T: LIN Transceiver with Voltage Regulator, and RESET
pin; wakes up on dominant level of LIN bus.
(Tape and Reel) (SOIC only)
MCP2021P: LIN Transceiver with Voltage Regulator; wakes up at a
falling edge of LIN bus level.
a)
b)
c)
d)
e)
MCP2022-330E/SL:
MCP2022-330E/P:
MCP2022-500E/SL:
MCP2022-500E/P:
3.3V, 14L-SOIC pkg.
3.3V, 14L-PDIP pkg.
5.0V, 14L-SOIC pkg.
5.0V, 14L-PDIP pkg.
MCP2021PT: LIN Transceiver with Voltage Regulator; wakes up at a
falling edge of LIN bus level
(Tape and Reel) (SOIC only)
MCP2022T-330E/SL: Tape and Reel,
3.3V, 14L-SOIC pkg.
MCP2022T-500E/SL: Tape and Reel,
5.0V, 14L-SOIC pkg.
MCP2022T-500E/ST: Tape and Reel,
5.0V, 14L-TSSOP pkg.
MCP2022P: LIN Transceiver with Voltage Regulator, and RESET
pin; wakes up at a falling edge of LIN bus level.
MCP2022PT: LIN Transceiver with Voltage Regulator, and RESET
pin; wakes up at a falling edge of LIN bus level.
(Tape and Reel) (SOIC only)
f)
g)
Temperature
Range:
E
=
-40°C to +125°C
Package:
MD
MF
P
SN
SL
ST
=
=
=
=
=
=
Plastic Micro Small Outline (4x4), 8-lead
Plastic Micro Small Outline (6x5), 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC, (150 mil Body), 8-lead
Plastic SOIC, (150 mil Body), 14-lead
Plastic Thin Shrink Small Outline, 14-lead
2005-2013 Microchip Technology Inc.
DS22018G-page 55
MCP2021/2/1P/2P
NOTES:
DS22018G-page 56
2005-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2005-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-345-1
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2005-2013 Microchip Technology Inc.
DS22018G-page 57
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11/29/12
DS22018G-page 58
2005-2013 Microchip Technology Inc.
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