MCP2025T-500E/P [MICROCHIP]
LIN Transceiver with Voltage Regulator;
| 型号： | MCP2025T-500E/P |
| 厂家： | 
MICROCHIP |
| 描述： | LIN Transceiver with Voltage Regulator |
| 文件： | 总38页 (文件大小：1068K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP2025
LIN Transceiver with Voltage Regulator
Features:
Description:
• Compliant with LIN Bus Specifications Version
1.3, 2.1 and with SAE J2602-2
The MCP2025 provides a bidirectional, half-duplex
communication physical interface to meet the LIN bus
specification Revision 2.1 and SAE J2602-2. The
device incorporates a voltage regulator with 5V or 3.3V
at 70 mA regulated power supply output. The device
has been designed to meet the stringent quiescent
current requirements of the automotive industry, and
will survive +43V load dump transients and double
battery jumps.
• Supports Baud Rates up to 20 kBaud
• 43V Load Dump Protected
• Maximum Continuous Input Voltage: 30V
• Wide LIN-Compliant Supply Voltage: 6.0-18.0V
• Extended Temperature Range: -40°C to +125°C
• Interface to PIC® EUSART and Standard USARTs
• Wake-Up on LIN Bus Activity or Local Wake Input
• Local Interconnect Network (LIN) Bus Pin:
The MCP2025 family members include:
- MCP2025-500, 8-pin, LIN driver with 5.0V
regulator
- Internal Pull-Up Termination Resistor and
Diode for Slave Node
- MCP2025-330, 8-pin, LIN driver with 3.3V
regulator
- Protected Against VBAT Shorts
- Protected Against Loss of Ground
- High-Current Drive
Package Types
• TXD and LIN Bus Dominant Time-Out Function
• Two Low-Power Modes:
MCP2025
PDIP, SOIC
- Transmitter Off: 90 µA (typical)
- Power Down: 4.5 µA (typical)
• MCP2025 On-Chip Voltage Regulator:
VREG
1
2
3
4
8
7
6
5
VBB
RESET
TXD
CS/LWAKE
VSS
- Output Voltage of 5.0V or 3.3V
at 70 mA Capability with Tolerances of ±3%
Over the Temperature Range
RXD
LBUS
MCP2025
- Internal Short-Circuit Current Limit
4x4 DFN
- External Components Limited to Filter
Capacitor and Load Capacitor
VBB
VREG
1
8
7
6
5
CS/LWAKE
VSS
RESET
TXD
2
• Automatic Thermal Shutdown
EP
9
3
4
• High Electromagnetic Immunity (EMI), Low
Electromagnetic Emission (EME)
LBUS
RXD
• Robust ESD Performance: ±15 kV for LBUS and
VBB Pin (IEC61000-4-2)
• Transient Protection for LBUS and VBB pins in
Automotive Environment (ISO7637)
• Meets Stringent Automotive Design Requirements,
including “OEM Hardware Requirements for LIN,
CAN and FlexRay Interfaces in Automotive
Applications”, Version 1.3, May 2012
• Multiple Package Options, Including Small
4x4 mm DFN Package
2012-2014 Microchip Technology Inc.
DS20002306B-page 1
MCP2025
MCP2025 Block Diagram
RESET
Thermal
Protection
Short-Circuit
Protection
Voltage
Regulator
VBB
Ratiometric
Reference
Wake-Up Logic
and
VREG
4.2V
Internal Circuits
Power Control
Bus Wake-Up
Slope Control
VREG
RXD
~ 30 k
CS/LWAKE
TXD
LBUS
VSS
Bus
Dominant
Timer
Thermal and
Short-Circuit
Protection
DS20002306B-page 2
2012-2014 Microchip Technology Inc.
MCP2025
1.1
Modes of Operation
1.0
DEVICE OVERVIEW
The MCP2025 works in five modes: Power-On Reset,
Power-Down, Ready, Operation and Transmitter Off.
For an overview of all operational modes, please refer
to Table 1-1. For the operational mode transition,
please refer to Figure 1-1.
The MCP2025 provides a physical interface between a
microcontroller and a LIN half-duplex bus. It is intended
for automotive and industrial applications with serial
bus baud rates up to 20 kBaud. This device will
translate the CMOS/TTL logic levels to LIN logic levels,
and vice versa.
The device offers optimum EMI and ESD performance
and it can withstand high voltage on the LIN bus. The
device supports two low-power modes to meet
automotive industry power consumption requirements.
The MCP2025 also provides a +5V or 3.3V regulated
power output at 70 mA.
FIGURE 1-1:
STATE DIAGRAM
CS/LWAKE = 0
READY
POR(2)
V
REG OFF
VREG ON
VBB > VON
CS/LWAKE = 1 &TXD = 1
VREG_OK = 1(1)
RX OFF
TX OFF
RX ON
TX OFF
CS = 1 &TXD = 0&
CS/LWAKE = 1&
T
XD = 1&
No Fault(3)
CS/LWAKE = 1 OR
Voltage Rising Edge on LBUS
TX OFF
OPERATION
V
REG ON
VREG ON
RX ON
RX ON
TX ON
TX OFF
CS/LWAKE = 0 or
Fault detected(3)
CS/LWAKE = 0
&TXD = 0
POWER-DOWN
V
REG OFF
RX OFF
TX OFF
Note 1: VREG_OK: Regulator Output Voltage > 0.8VREG_NOM.
2: If the voltage on pin VBB falls below VOFF, the device will enter Power-On Reset mode from all other
modes, which is not shown in the figure.
3: Faults include TXD/LBUS permanent dominant, LBUS short to VBB, thermal protection and VREG_OK is
false.
2012-2014 Microchip Technology Inc.
DS20002306B-page 3
MCP2025
1.1.1
POWER-ON RESET MODE
1.1.4
TRANSMITTER OFF MODE
Upon application of VBB, or whenever the voltage on
VBB is below the threshold of regulator turn-off voltage
VOFF (typically 4.50V), the device enters Power-On
Reset (POR) mode. During this mode, the device
maintains the digital section in a Reset mode and waits
until the voltage on the VBB pin rises above the
threshold of regulator turn-on voltage VON (typically
5.75V) to enter Ready mode. In Power-On Reset
mode, the LIN physical layer and voltage regulator are
disabled and the RESET pin is switched to ground.
If VREG is OK (VREG > 0.8*VREG_NOM), the Transmitter
Off mode can be reached from Ready mode by setting
CS/LWAKE to high when the TXD pin is low, or from
Operation mode by pulling down CS/LWAKE to low.
In Transmitter Off mode, the receiver is enabled but the
LBUS transmitter is off. It is a lower-power mode.
In order to minimize power consumption, the regulator
operates in a reduced-power mode. It has a lower
GBW product and it is thus slower. However, the 70 mA
drive capability is unchanged.
1.1.2
READY MODE
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption on the bus during times
of uncertain operation.
The device enters Ready mode from POR mode after
the voltage on VBB rises above the threshold of
regulator turn-on voltage VON, or from Power-Down
mode when a remote or local wake-up event happens.
1.1.5
POWER-DOWN MODE
Upon entering Ready mode, the voltage regulator and
the receiver section of the transceiver are powered-up.
The transmitter remains in an off state. The device is
ready to receive data, but not to transmit. In order to
minimize the power consumption, the regulator
operates in a reduced-power mode. It has a lower
GBW product and it is thus slower. However, the 70 mA
drive capability is unchanged.
Power-Down mode is entered by pulling down both the
CS/LWAKE pin and the TXD pin to low from Transmitter
Off mode. In Power-Down mode, the transceiver and
the voltage regulator are both off. Only the bus wake-up
section and the CS/LWAKE pin wake-up circuits are in
operation. This is the lowest-power mode.
If any bus activity (e.g., a Break character) occurs or
CS/LWAKE is set to high during Power-Down mode,
the device will immediately enter Ready mode and
enable the voltage regulator. Then, once the regulator
output has stabilized (approximately 0.3 ms to 1.2 ms),
it can go into either Operation mode or Transmitter Off
mode. Refer to Section 1.1.6 “Remote Wake-Up” for
more details.
The device stays in Ready mode until the output of the
voltage regulator has stabilized and the CS/LWAKE pin
is high (‘1’).
1.1.3
OPERATION MODE
If the CS/LWAKE pin changes to high while VREG is OK
(VREG > 0.8*VREG_NOM) and the TXD pin is high, the
part enters Operation mode from either Ready or
Transmitter Off mode.
1.1.6
REMOTE WAKE-UP
The Remote Wake-Up sub-module observes the LBUS
in order to detect bus activity. In Power-Down mode,
the normal LIN recessive/dominant threshold is
disabled and the LIN bus wake-up voltage threshold
VWK(LBUS) is used to detect bus activities. Bus activity
is detected when the voltage on the LBUS falls below
the LIN bus wake-up voltage threshold VWK(LBUS)
(approximately 3.4V) for at least tBDB (a typical duration
of 80 µs) followed by a rising edge. Such a condition
causes the device to leave Power-Down mode.
In this mode, all internal modules are operational. The
internal pull-up resistor between LBUS and VBB is
connected only in this mode.
The device goes into Transmitter Off mode at the falling
edge on the CS/LWAKE pin or when a fault is detected.
Note:
The TXD pin needs to be set high before
setting the CS/LWAKE pin to low in order
to jump and stay in Transmitter Off mode.
If the TXD pin is set or maintained low
before setting the CS/LWAKE pin to low,
the part will transition to Transmitter Off
mode and then jump to Power-Down
mode after a deglitch delay of about
20 µs.
DS20002306B-page 4
2012-2014 Microchip Technology Inc.
MCP2025
TABLE 1-1:
State
OVERVIEW OF OPERATIONAL MODES
Internal
Voltage
Transmitter Receiver Wake
Regulator
Operation
Comments
Module
POR
OFF
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
ON
Proceed to Ready mode after
VBB > VON.
—
Ready
Operation
If CS/LWAKE is high, then proceed to Bus Off
Operation or Transmitter Off mode. state
If CS/LWAKE is low, then proceed to Normal
Transmitter Off mode. Operation
mode
On LIN bus rising edge or CS/LWAKE Lowest-
ON
ON
Power-Down
OFF
OFF
OFF
ON
ON
Activity
Detect
OFF
ON
high level, go to Ready mode.
Power
mode
Transmitter Off
OFF
If TXD and CS/LWAKE are low, then
proceed to Power-Down mode.
Bus Off
state,
If TXD and CS/LWAKE are high, then lower-power
proceed to Operation mode.
mode
2012-2014 Microchip Technology Inc.
DS20002306B-page 5
MCP2025
1.2
Pin Descriptions
The descriptions of the pins are listed in Table 1-2.
TABLE 1-2:
Pin Name
PIN FUNCTION TABLE
Pin Number
Pin Type
Description
8-lead PDIP 4x4 DFN
VBB
CS/LWAKE
VSS
1
2
3
4
5
6
1
2
3
4
5
6
Power
TTL input, HV-tolerant
Power
Battery
Chip Select and Local Wake-up Input
Ground
LBUS
I/O, HV
LIN Bus
RXD
Output
Receive Data Output
Transmit Data Input
TXD
Input, HV-tolerant
RESET
VREG
EP
7
8
7
8
9
Open-drain output, HV-tolerant
Reset Output
Output
—
Voltage Regulator Output
Exposed Thermal Pad
—
1.2.1
BATTERY POSITIVE SUPPLY
VOLTAGE (VBB)
1.2.4
LIN BUS (LBUS)
LIN Bus pin. LBUS is a bidirectional LIN bus interface
pin and is controlled by the signal TXD. It has an open
collector output with a current limitation. To reduce
electromagnetic emission, the slopes during signal
changes are controlled and the LBUS pin has
corner-rounding control for both falling and rising
edges.
Battery Positive Supply Voltage pin. An external diode
is connected in series to prevent the device from being
reversely powered (refer to Figure 1-7).
1.2.2
CHIP SELECT AND LOCAL
WAKE-UP INPUT (CS/LWAKE)
The internal LIN receiver observes the activities on the
LIN bus and generates the output signal RXD that
follows the state of the LBUS. A 1st degree 160 kHz
low-pass input filter optimizes electromagnetic
immunity.
Chip Select and Local Wake-Up Input pin (TTL level,
high-voltage tolerant). This pin controls the device state
transition. Refer to Figure 1-1.
An internal pull-down resistor will keep the CS/LWAKE
pin low to ensure that no disruptive data will be present
on the bus while the microcontroller is executing a
Power-On Reset and I/O initialization sequence. When
CS/LWAKE is ‘1’, a weak pull-down (~600 kΩ) is used
to reduce current. When CS/LWAKE is ‘0’, a stronger
pull-down (~300 kΩ) is used to maintain the logic level.
1.2.5
RECEIVE DATA OUTPUT (RXD)
Receive Data Output pin. The RXD pin is a standard
CMOS output pin and it follows the state of the LBUS
pin.
This pin may also be used as a local wake-up input
(see Figure 1-7). The microcontroller will set the I/O pin
to control the CS/LWAKE. An external switch or
another source can then wake up both the transceiver
and the microcontroller.
1.2.6
TRANSMIT DATA INPUT (TXD)
Transmit Data Input pin (TTL level, HV-compliant,
adaptive pull-up). The transmitter reads the data
stream on the TXD pin and sends it to the LIN bus. The
LBUS pin is low (dominant) when TXD is low, and high
(recessive) when TXD is high.
Note:
CS/LWAKE should NOT be tied directly to
the VREG pin, as this could force the
MCP2025 into Operation mode before the
microcontroller is initialized.
TXD is internally pulled-up to approximately 4.2V. When
TXD is ‘0’, a weak pull-up (~900 kΩ) is used to reduce
current. When TXD is ‘1’, a stronger pull-up (~300 kΩ)
is used to maintain the logic level.
A series
1.2.3
GROUND (VSS)
reverse-blocking diode allows applying TXD input
voltages greater than the internally generated 4.2V and
renders the TXD pin HV-compliant up to 30V (see
MCP2025 Block Diagram).
Ground pin.
DS20002306B-page 6
2012-2014 Microchip Technology Inc.
MCP2025
1.2.7
RESET
FIGURE 1-2:
THERMAL SHUTDOWN
STATE DIAGRAMS
Reset output pin. This is an open-drain output pin. It
indicates the internal voltage has reached a valid,
stable level. As long as the internal voltage is valid
(above 0.8 VREG), this pin will present high impedance;
otherwise, the RESET pin switches to ground.
LIN Bus
Shorted to
Output
Overload
VBB
Voltage
Regulator
Shutdown
Operation
Mode
Transmitter
Shutdown
1.2.8
POSITIVE SUPPLY VOLTAGE
REGULATOR OUTPUT (VREG)
Positive Supply Voltage Regulator Output pin. An
on-chip Low Dropout Regulator (LDO) gives +5.0 or
+3.3V at 70 mA regulated voltage on this pin.
Temp < SHUTDOWNTEMP Temp < SHUTDOWNTEMP
1.3.3
TXD/LBUS TIME-OUT TIMER
1.2.9
EXPOSED THERMAL PAD (EP)
The LIN bus can be driven to a dominant level, either
from the TXD pin or externally. An internal timer
deactivates the LBUS transmitter if a dominant status
(low) on the LIN bus lasts longer than Bus Dominant
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
Time-Out
Time,
tTO(LIN)
(approximately
20 milliseconds). At the same time, the RXD output is
put in recessive (high) and the internal pull-up resistor
between LBUS and VBB is disconnected. The timer is
reset on any recessive LBUS status or POR mode. The
recessive status on LBUS can be caused either by the
bus being externally pulled-up or by the TXD pin being
returned high.
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (JA).
1.3
Fail-Safe Features
1.3.1
GENERAL FAIL-SAFE FEATURES
• An internal pull-down resistor on the CS/LWAKE
pin disables the transmitter if the pin is floating.
1.4
Internal Voltage Regulator
The MCP2025 has a positive regulator capable of
supplying +5.00 or +3.30 VDC ±3% at up to 70 mA of
load current over the entire operating temperature
range of -40°C to +125°C. The regulator uses an LDO
design, is short-circuit-protected and will turn the
regulator output off if its output falls below the shutdown
voltage threshold, VSD.
• An internal pull-up resistor on the TXD pin places
TXD in high and the LBUS in recessive if the TXD
pin is floating.
• High-Impedance and low-leakage current on LBUS
during loss of power or ground.
• The current limit on LBUS protects the transceiver
from being damaged if the pin is shorted to VBB.
With
a
load current of 70 mA, the minimum
1.3.2
THERMAL PROTECTION
input-to-output voltage differential required for the
output to remain in regulation is typically +0.5V (+1V
maximum over the full operating temperature range).
Quiescent current is less than 100 µA with a full 70 mA
load current when the input-to-output voltage
differential is greater than +3.00V.
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter and voltage regulator.
There are three causes for a thermal overload. A
thermal shutdown can be triggered by any one, or a
combination of, the following thermal overload
conditions:
Regarding the correlation between VBB, VREG and IDD,
please refer to Figures 1-4 and 1-5. When the input
voltage (VBB) drops below the differential needed to
provide stable regulation, the voltage regulator output,
VREG, will track the input down to approximately VOFF,
at which point the regulator will turn off the output. This
will allow PIC® microcontrollers with internal POR
circuits to generate a clean arming of the POR trip
point. The MCP2025 will then monitor VBB and turn on
the regulator when VBB is above the threshold of
regulator turn-on voltage, VON.
• Voltage regulator overload
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
The recovery time from the thermal shutdown is equal
to adequate cooling time.
Driving the TXD and checking the RXD pin make it
possible to determine whether there is a bus contention
(TXD = high, RXD = low) or
In Power-Down mode, the VBB monitor is turned off.
a
thermal overload
condition (TXD = low, RXD = high).
2012-2014 Microchip Technology Inc.
DS20002306B-page 7
MCP2025
Under specific ambient temperature and battery
voltage range, the voltage regulator can output as high
as 150 mA current. For current load capability of the
voltage regulator, refer to Figures 2-8 and 2-9.
In worst-case scenarios, the ceramic capacitor may
derate by 50%, based on tolerance, voltage and
temperature. Therefore, in order to ensure stability,
ceramic capacitors smaller than 10 µF may require a
small series resistance to meet the ESR requirements,
as shown in Table 1-3.
Note:
The regulator has an overload current limit
of approximately 250 mA. The regulator
output voltage, VREG, is monitored. If
output voltage VREG is lower than VSD, the
voltage regulator will turn off. After a
recovery time of about 3 ms, the VREG will
be checked again. If there is no short
circuit, (VREG > VSD), then the voltage
regulator remains on.
TABLE 1-3:
RECOMMENDED SERIES
RESISTANCE FOR CERAMIC
CAPACITORS
Resistance
Capacitor
1
1 µF
0.47
0.22
0.1
2.2 µF
4.7 µF
6.8 µF
The regulator requires an external output bypass
capacitor for stability. See Figure 2-1 for correct
capacity and ESR for stable operation.
Note:
A ceramic capacitor of at least 10 µF or a
tantalum capacitor of at least 2.2 µF is
recommended for stability.
FIGURE 1-3:
VOLTAGE REGULATOR BLOCK DIAGRAM
Pass
Element
VBB
VREG
Sampling
Network
Fast
Transient
Loop
Buffer
VSS
VREF
DS20002306B-page 8
2012-2014 Microchip Technology Inc.
MCP2025
FIGURE 1-4:
VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET
VBB
V
Minimum VBB to maintain regulation
8
6
4
2
0
VON
VOFF
t
VREG
V
VREG-NOM
5
4
3
2
1
0
t
(4)
(1)
(2)
(3)
Note 1: Start-up, VBB < VON, regulator off.
2: VBB > VON, regulator on.
3: VBB Minimum VBB to maintain regulation.
4: VBB < VOFF, regulator will turn off.
FIGURE 1-5:
VOLTAGE REGULATOR OUTPUT ON OVERCURRENT SITUATION
IREG
mA
ILIM
0
t
VREG
V
6
5
VREG-NOM
4
VSD
3
2
1
0
t
(1)
Note 1: IREG less than lLIM, regulator on.
2: After IREG exceeds lLIM, the voltage regulator output will be reduced until VSD is reached.
(2)
2012-2014 Microchip Technology Inc.
DS20002306B-page 9
MCP2025
EQUATION 1-2:
1.5
Optional External Protection
VRECESSIVE
RTP ---------------------------------
1.5.1
REVERSE BATTERY PROTECTION
IREGMAX
An external reverse-battery-blocking diode should be
used to provide polarity protection (see Figure 1-7).
Where:
VRECESSIVE = Maximum variation tolerated on
1.5.2
TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
the recessive level
An external 43V transient suppressor (TVS) diode,
between VBB and ground, with a transient protection
resistor (RTP) in series with the battery supply and the
VBB pin, protects the device from power transients and
ESD events greater than 43V (see Figure 1-7). The
maximum value for the RTP protection resistor depends
upon two parameters: the minimum voltage the part will
start at and the impacts of this RTP resistor on the VBB
value, thus on the bus recessive level and slopes.
Assume
that
VRECCESSIVE = 1V
and
IREGMAX = 50 mA. Equation 1-2 gives 20.
EQUATION 1-3:
Slope VBATMIN – 1V
RTP ----------------------------------------------------------------
IREGMAX
Where:
Slope = Maximum variation tolerated on the
This leads to a set of three equations to fulfill.
slope level
Equation 1-1 provides a maximum RTP value according
to the minimum battery voltage the user wants.
IREGMAX = Maximum current the current will
provide to the load
Equation 1-2 provides
a
maximum RTP value
VBATMIN > VOFF + 1.0V
according to the maximum error on the recessive level,
thus VBB, since the part uses VBB as the reference
value for the recessive level.
Assume that Slope = 15%, VBATMIN = 8V and
IREGMAX = 50 mA. Equation 1-3 gives 20.
Equation 1-3 provides
a
maximum RTP value
according to the maximum relative variation the user
can accept on the slope when IREG varies.
1.5.3
CBAT CAPACITOR
Selecting
CBAT = 10 x CREG
is recommended.
Since both Equations 1-1 and 1-2 must be fulfilled, the
maximum allowed value for RTP is thus the smaller of the
two values found when solving Equations 1-1 and 1-2.
However, this leads to a high-value capacitor. Lower
values for CBAT capacitor can be used with respect to
some rules. In any case, the voltage at the VBB pin
should remain above VOFF when the device is turned
on.
Usually, Equation 1-1 gives the higher constraint
(smaller value) for RTP, as shown in the following
example where VBATMIN is 8V.
The current peak at start-up (due to the fast charge of
the CREG and CBAT capacitors) may induce a
significant drop on the VBB pin. This drop is
proportional to the impedance of the VBAT connection
(see Figure 1-7).
However, the user needs to verify that the value found
with Equation 1-1 fulfills Equations 1-2 and 1-3.
While this protection is optional, it should be
considered as good engineering practice.
The VBAT connection is mainly inductive and resistive.
Therefore, it can be modeled as a resistor (RTOT) in
series with an inductor (L). RTOT and L can be
measured.
EQUATION 1-1:
VBATMIN – 5.5V
RTP ---------------------------------------
250 mA
The following formula gives an indication of the
minimum value of CBAT using RTOT and L:
5.5V = VOFF + 1.0V
EQUATION 1-4:
Where:
CBAT
100L2 + RT2OT
250 mA = Peak current at power-on when
VBB = 5.5V
------------- = ------------------------------------
RT2OT
CREG
1 + L2 + ------------
100
Assume that VBATMIN = 8V. Equation 1-1 gives 10.
Where:
L = Inductor (measured in mH)
RTOT = RLINE + RTP (measured in )
Equation 1-4 allows lower CBAT/CREG values than the
10x ratio we recommend.
DS20002306B-page 10
2012-2014 Microchip Technology Inc.
MCP2025
Assume that we have a good quality VBAT connection
with RTOT = 0.1 and L = 0.1 mH.
Solving the equation gives CBAT/CREG = 1.
If we increase RTOT up to 1, the result becomes
CBAT/CREG = 1.4. However, if the connection is highly
resistive or highly inductive (poor connection), the
CBAT/CREG ratio greatly increases.
TABLE 1-4:
CBAT/CREG RATIO BY VBAT
CONNECTION TYPE
Connection
Type
CBAT/CREG
RTOT
L
Ratio
Good
0.1 0.1 mH
1
1.4
7
Typical
1
0.1 mH
1 mH
Highly inductive 0.1
Highly resistive
10 0.1 mH
7
Figure 1-6 shows the minimum recommended
CBAT/CREG ratio as a function of the impedance of the
VBAT connection.
FIGURE 1-6:
Minimum Recommended
CBAT/CREG Ratio
CBAT/CREG Ratio as Function of the VBAT Line
Impedance
RBAT = 10
10
RBAT = 4
RBAT = 2
RBAT = 1
RBAT = 0.3
RBAT = 0.1
1
0.1
1
VBAT Line Inductance [mH]
2012-2014 Microchip Technology Inc.
DS20002306B-page 11
MCP2025
1.6
Typical Applications
FIGURE 1-7:
TYPICAL APPLICATION CIRCUIT
VBAT
VBAT
RTP
CBAT
220 k
43V(5)
Master Node Only
VBB
CREG
Wake-Up
VBB
VDD
VREG
TXD
RXD
TXD
RXD
(6)
1 k
LIN Bus
MMBZ27V (4)
LBUS
I/O
CS/LWAKE
RESET
VSS
(3)
RESET
VSS
220 pF
100 nF
Note 1: CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0-22 µF. See
Figure 2-1 to select the correct ESR.
2: CBAT is the filter capacitor for the external voltage supply. Typically 10 x CREG, with no ESR restriction. See
Figure 1-6 to select the minimum recommended value for CBAT. The RTP value is added to the line resistance.
3: This diode is only needed if CS/LWAKE is connected to the VBAT supply.
4: ESD protection diode.
5: This component is for additional load dump protection.
6: An external 10 kΩ resistor is recommended for some applications.
FIGURE 1-8:
TYPICAL LIN NETWORK CONFIGURATION
40m
+ Return
LIN bus
1 k
VBB
LIN bus
MCP2025
LIN bus
MCP205X
LIN bus
MCP202XA
LIN bus
MCP2003
Slave 1
(MCU)
Slave n <16
(MCU)
Slave 2
(MCU)
Master
(MCU)
DS20002306B-page 12
2012-2014 Microchip Technology Inc.
MCP2025
1.7
ICSP™ Considerations
The following should be considered when the MCP2025
are connected to pins supporting in-circuit programming:
• Power used for programming the microcontroller
can be supplied from the programmer or from
the MCP2025.
The voltage on the VREG pin should not exceed the
maximum value of VREG in DC Specifications.
2012-2014 Microchip Technology Inc.
DS20002306B-page 13
MCP2025
2.0
2.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VIN DC Voltage on RXD and RESET .................................................................................................-0.3V to VREG + 0.3
VIN DC Voltage on TXD, CS/LWAKE.............................................................................................................. -0.3 to +40V
VBB Battery Voltage, continuous, non-operating (Note 1)............................................................................. -0.3 to +40V
VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) (Note 2) ...................... -0.3 to +43V
VBB Battery Voltage, transient ISO 7637 Test 1 ..................................................................................................... -100V
VBB Battery Voltage, transient ISO 7637 Test 2a .....................................................................................................+75V
VBB Battery Voltage, transient ISO 7637 Test 3a ................................................................................................... -150V
VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+100V
VLBUS Bus Voltage, continuous...................................................................................................................... -18 to +30V
VLBUS Bus Voltage, transient (Note 3)........................................................................................................... -27 to +43V
ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA
ESD protection on LIN, VBB (IEC 61000-4-2) (Note 4)............................................................................................±15 V
ESD protection on LIN, VBB (Human Body Model) (Note 5)....................................................................................±8 kV
ESD protection on all other pins (Human Body Model) (Note 5) .............................................................................±4 kV
ESD protection on all pins (Charge Device Model) (Note 6).................................................................................±1500V
ESD protection on all pins (Machine Model) (Note 7).............................................................................................±200V
Maximum Junction Temperature.............................................................................................................................150C
Storage Temperature...................................................................................................................................-65 to +150C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Note 1: LIN 2.x compliant specification.
2: SAE J2602-2 compliant specification.
3: ISO 7637/1 load dump compliant (t < 500 ms).
4: According to IEC 61000-4-2, 330, 150 pF and Transceiver EMC Test Specifications [2] to [4].
5: According to AEC-Q100-002/JESD22-A114.
6: According to AEC-Q100-011B.
7: According to AEC-Q100-003/JESD22-A115.
2.2
Nomenclature Used in this Document
Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent
values are shown below.
LIN 2.1 Name
Term used in the following tables
Definition
ECU operating voltage
VBAT
not used
VBB
VSUP
Supply voltage at device pin
Current limit of driver
Recessive state
VBUS_LIM
VBUSREC
VBUSDOM
ISC
VIH(LBUS)
VIL(LBUS)
Dominant state
DS20002306B-page 14
2012-2014 Microchip Technology Inc.
MCP2025
2.3
DC Specifications
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V, TA = -40°C to +125°C, CREG = 10 µF.
DC Specifications
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Power
VBB Quiescent Operating
Current
IBBQ
—
—
200
µA
IOUT = 0 mA
LBUS recessive
VREG = 5.0V
—
—
—
—
—
—
—
—
—
—
—
4.5
200
100
100
100
100
8
µA
µA
µA
µA
µA
µA
IOUT = 0 mA
LBUS recessive
VREG = 3.3V
VBB Ready Current
IBBRD
IBBTO
IOUT = 0 mA
LBUS recessive
VREG = 5.0V
IOUT = 0 mA
LBUS recessive
VREG = 3.3V
VBB Transmitter-Off Current
with Watchdog Disabled
With voltage regulator on,
transmitter off, receiver on,
CS = VIH,VREG = 5.0V
With voltage regulator on,
transmitter off, receiver on,
CS = VIH,VREG = 3.3V
VBB Power-Down Current
IBBPD
With voltage regulator off,
receiver on and
transmitter off,
CS = VIL
—
VBB Current with VSS
Floating
IBBNOGND
-1
1
mA VBB = 12V, GND to VBB,
VLIN = 0 – 18V
Microcontroller Interface
—
—
—
High-Level Input Voltage
(TXD)
VIH
VIL
IIH
2.0
-0.3
-2.5
30
0.8
0.4
V
V
Low-Level Input Voltage
(TXD)
High-Level Input Current
(TXD)
µA
µA
Input voltage = 4.0V
~800 k internal adaptive
pull-up
Low-Level Input Current
(TXD)
IIL
-10
—
—
Input voltage = 0.5V
~800 k internal adaptive
pull-up
—
—
—
High-Level Input Voltage
(CS/LWAKE)
VIH
VIL
IIH
2
-0.3
—
30
0.8
8.0
V
V
Through a current-limiting
resistor
Low-Level Input Voltage
(CS/LWAKE)
High-Level Input Current
(CS/LWAKE)
µA
Input voltage = 0.8VREG
~1.3 M internal
pull-down to VSS
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB).
2: Characterized, not 100% tested.
3: In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect
bus activities.
2012-2014 Microchip Technology Inc.
DS20002306B-page 15
MCP2025
2.3
DC Specifications (Continued)
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V, TA = -40°C to +125°C, CREG = 10 µF.
DC Specifications
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
—
—
Low-Level Input Current
(CS/LWAKE)
IIL
5.0
µA
Input voltage = 0.2VREG
~1.3 M internal
pull-down to VSS
Low-Level Output Voltage
(RXD)
VOLRXD
VOHRXD
—
—
—
0.2VREG
—
V
V
IOL = 2 mA
IOH = 2 mA
High-Level Output Voltage
(RXD)
0.8VREG
Bus Interface
High-Level Input Voltage
Low-Level Input Voltage
Input Hysteresis
VIH(LBUS)
VIL(LBUS)
VHYS
0.6 VBB
—
—
—
—
—
V
V
V
Recessive state
-8
—
40
0.4 VBB
0.175 VBB
200
Dominant state
VIH(LBUS) – VIL(LBUS)
Low-Level Output Current
IOL(LBUS)
mA Output voltage = 0.1 VBB,
VBB = 12V
Pull-Up Current on Input
IPU(LBUS)
-180
—
-72
µA
~30 k internal pull-up
@ VIH(LBUS) = 0.7 VBB,
VBB = 12V
Short Circuit Current Limit
High-Level Output Voltage
Driver Dominant Voltage
ISC
50
0.8 VBB
—
—
—
—
200
VBB
1.1
mA Note 1
VOH(LBUS)
V_LOSUP
V
V
VBB = 7.3V
RLOAD = 1000
V_HISUP
—
-1
—
—
1.2
—
V
VBB = 18V
RLOAD = 1000
Input Leakage Current
(at the receiver during
dominant bus level)
IBUS_PAS_DOM
mA Driver off
VBUS = 0V
VBB = 12V
Input Leakage Current
(at the receiver during
recessive bus level)
IBUS_PAS_REC
IBUS_NO_GND
-20
-10
—
20
µA
Driver off
8V < VBB < 18V
8V < VBUS < 18V
VBUS VBB
Leakage Current
(disconnected from ground)
—
—
+10
+10
µA
GNDDEVICE = VBB
0V < VBUS < 18V
VBB = 12V
Leakage Current
(disconnected from VBB)
IBUS_NO_PWR
VBUS_CNT
-10
µA
V
VBB = GND
0 < VBUS < 18V
Receiver Center Voltage
0.475 VBB
0.5 0.525 VBB
VBB
VBUS_CNT = (VIL(LBUS) +
VIH(LBUS))/2
Slave Termination
RSLAVE
CSLAVE
20
—
—
30
—
—
47
50
k
pF
V
Note 2
Note 2
Capacitance of Slave Node
Wake-Up Voltage Thresh-
old on LIN Bus
VWK(LBUS)
3.4
Wake up from
Power-Down mode
(Note 3)
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB).
2: Characterized, not 100% tested.
3: In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect
bus activities.
DS20002306B-page 16
2012-2014 Microchip Technology Inc.
MCP2025
2.3
DC Specifications (Continued)
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V, TA = -40°C to +125°C, CREG = 10 µF.
DC Specifications
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Voltage Regulator – 5.0V
Output Voltage Range
Line Regulation
VREG
4.85
—
5.00
10
5.15
50
V
0 mA < IOUT < 70 mA
VOUT1
mV IOUT = 1 mA
6.0V < VBB < 18V
Load Regulation
VOUT2
PSRR
eN
—
—
—
10
—
—
50
50
mV 5 mA < IOUT < 70 mA
6.0V < VBB < 12V
Power Supply Ripple Reject
Output Noise Voltage
dB
1 VPP @ 10-20 kHz
ILOAD = 20 mA
100
µVRMS 10 Hz – 40 MHz
CFILTER = 10 µf
CBP = 0.1 µf
ILOAD = 20 mA
Shutdown Voltage
Threshold
VSD
VOFF
VON
3.5
3.9
—
—
—
4.0
4.5
6.0
V
V
V
See Figure 1-5 (Note 2)
Input Voltage to
Turn-Off Output
—
—
Input Voltage to
Turn-On Output
5.25
Voltage Regulator – 3.3V
Output Voltage
VREG
3.20
—
3.30
10
3.40
50
V
0 mA < IOUT < 70 mA
Line Regulation
VOUT1
mV IOUT = 1 mA
6.0V < VBB < 18V
Load Regulation
VOUT2
PSRR
eN
—
—
—
10
50
—
50
—
mV 5 mA < IOUT < 70 mA
6.0V < VBB < 12V
Power Supply Ripple Reject
Output Noise Voltage
dB
1 VPP @ 10-20 kHz
ILOAD = 20 mA
100
µVRMS 10 Hz – 40 MHz
/Hz CFILTER = 10 µF
CBP = 0.1 µF
ILOAD = 20 mA
Shutdown Voltage
VSD
2.5
3.9
—
—
2.7
4.5
V
V
See Figure 1-5 (Note 2)
Input Voltage to
Turn-Off Output
VOFF
—
Input Voltage to
Turn-On Output
VON
5.25
—
6
V
—
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB).
2: Characterized, not 100% tested.
3: In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect
bus activities.
2012-2014 Microchip Technology Inc.
DS20002306B-page 17
MCP2025
FIGURE 2-1:
ESR CURVES FOR LOAD CAPACITOR SELECTION
ESR Curves
10
1
Unstable
Stable only
with Tantalum or
Electrolytic cap.
Stable with
Tantalum,
Electrolytic and
Ceramic cap.
Unstable
Instable
0.1
0.01
0.001
Unstable
Instable
1000
0.1
1
100
10
Load Capacitance [uF]
Note 1: The graph shows the minimum required capacitance after derating due to tolerance, temperature and voltage.
DS20002306B-page 18
2012-2014 Microchip Technology Inc.
MCP2025
2.4
AC Specifications
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V; TA = -40°C to +125°C.
AC Characteristics
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Bus Interface – Constant Slope Time Parameters
Slope Rising and Falling
Edges
tSLOPE
tTRANSPD
tRECPD
3.5
—
—
—
—
22.5
6.0
µs
µs
µs
µs
7.3V VBB 18V
Propagation Delay of
Transmitter
—
tTRANSPD = max.
(tTRANSPDR or tTRANSPDF)
Propagation Delay of
Receiver
—
6.0
tRECPD = max.
(tRECPDR or tRECPDF)
Symmetry of Propagation
Delay of Receiver Rising
Edge w.r.t. Falling Edge
tRECSYM
-2.0
2.0
tRECSYM = max.
(tRECPDF – tRECPDR)
RRXD = 2.4 kto VCC
CRXD = 20 pF
Symmetry of Propagation
Delay of Transmitter Rising
Edge w.r.t. Falling Edge
tTRANSSYM
-2.0
—
2.0
µs
tTRANSSYM = max.
(tTRANSPDF – tTRANSPDR)
Bus Dominant Time-Out
Time
tTO(LIN)
—
—
25
—
—
—
mS
—
Duty Cycle 1 @ 20.0 kbps
Duty Cycle 2 @ 20.0 kbps
Duty Cycle 3 @ 10.4 kbps
Duty Cycle 4 @ 10.4 kbps
0.396
%tBIT CBUS; RBUS conditions:
1 nF; 1 k | 6.8 nF;
660 | 10 nF; 500
THREC(MAX) = 0.744 x VBB,
THDOM(MAX) = 0.581 x VBB,
VBB = 7.0V – 18V;
tBIT = 50 µs.
D1 = tBUS_REC(MIN)/2 x tBIT
—
—
—
—
0.417
—
—
—
—
0.581
%tBIT CBUS; RBUS conditions:
1 nF; 1 k | 6.8 nF;
660 | 10 nF; 500
THREC(MAX) = 0.284 x VBB,
THDOM(MAX) = 0.422 x VBB,
VBB = 7.6V – 18V;
tBIT = 50 µs.
D2 = tBUS_REC(MAX)/2 x tBIT
—
%tBIT CBUS; RBUS conditions:
1 nF; 1 k | 6.8 nF;
660 | 10 nF; 500
THREC(MAX) = 0.778 x VBB,
THDOM(MAX) = 0.616 x VBB,
VBB = 7.0V – 18V;
tBIT = 96 µs.
D3 = tBUS_REC(MIN)/2 x tBIT
0.590
%tBIT CBUS; RBUS conditions:
1 nF; 1 k | 6.8 nF;
660 | 10 nF; 500
THREC(MAX) = 0.251 x VBB,
THDOM(MAX) = 0.389 x VBB,
VBB = 7.6V – 18V;
tBIT = 96 µs.
D4 = tBUS_REC(MAX)/2 x tBIT
Note 1: Time depends on external capacitance and load. Test condition: CREG = 4.7 µF, no resistor load.
2: Characterized, not 100% tested.
2012-2014 Microchip Technology Inc.
DS20002306B-page 19
MCP2025
2.4
AC Specifications (Continued)
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V; TA = -40°C to +125°C.
AC Characteristics
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Voltage Regulator
Bus Activity Debounce Time
tBDB
30
35
80
—
250
200
µs
µs
—
—
Bus Activity to Voltage
Regulator Enabled
tBACTIVE
Voltage Regulator Enabled
to Ready
tVEVR
tCSR
Note 1
Note 2
300
—
1200
µs
Chip Select to Ready Mode
—
—
—
—
20
—
—
—
230
300
100
µs
µs
µs
Chip Select to Power-Down
Short Circuit to Shutdown
tCSPD
tSHUTDOWN
RESET Timing
VREG OK Detect to RESET
Inactive
tRPU
tRPD
Note 2
Note 2
—
—
—
—
60.0
60.0
µs
µs
VREG Not OK Detect to
RESET Active
Note 1: Time depends on external capacitance and load. Test condition: CREG = 4.7 µF, no resistor load.
2: Characterized, not 100% tested.
2.5
Thermal Specifications
Parameter
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Specified Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Recovery Temperature
TA
TJ
-40
—
—
—
+125
+150
+150
—
C
C
C
C
C
ms
—
—
—
—
—
—
TA
-65
—
—
RECOVERY
SHUTDOWN
tTHERM
+140
+150
1.5
—
Shutdown Temperature
—
Short Circuit Recovery Time
Thermal Package Resistances
Thermal Resistance, 8-PDIP
Thermal Resistance, 8-SOIC
Thermal Resistance, 8L-DFN
—
5.0
—
—
—
JA
JA
JA
—
—
—
89.3
149.5
48.0
C/W
C/W
C/W
—
—
—
Note 1: The maximum power dissipation is a function of TJMAX, JA and ambient temperature, TA. The maximum
allowable power dissipation at an ambient temperature is PD = (TJMAX – TA) JA. If this dissipation is
exceeded, the die temperature will rise above 150C and the MCP2025 will go into thermal shutdown.
DS20002306B-page 20
2012-2014 Microchip Technology Inc.
MCP2025
2.6
Typical Performance Curves
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VBB = 6.0V to 18.0V; TA = -40°C to +125°C.
200
180
160
140
120
100
80
180
160
140
120
100
80
VBB = 12V
VBB = 6V
VBB = 18V
VBB = 18V
VBB = 6V
VBB = 12V
60
60
40
40
20
20
0
0
-45
-10
25
90
130
-45
-10
25
90
130
Temperature (C)
Temperature (C)
FIGURE 2-2:
Temperature – 5.0V.
Typical IBBQ vs.
FIGURE 2-5:
Temperature – 3.3V.
Typical IBBQ vs.
80
90
80
70
60
70
VBB = 18V
VBB = 18V
60
VBB = 12V
VBB = 12V
VBB = 6V
50
VBB = 6V
50
40
30
20
10
0
40
30
20
10
0
-45
-10
25
90
130
-45
-10
25
90
130
Temperature (C)
Temperature (C)
FIGURE 2-3:
Temperature – 5.0V.
IBBQ Transmitter-Off vs.
FIGURE 2-6:
Temperature – 3.3V.
IBBQ Transmitter-Off vs.
6
6
5
VBB =
12V
5
VBB = 18V
VBB = 12V
VBB = 6V
VBB = 18V
4
4
3
2
1
0
VBB = 6V
3
2
1
0
-45
-10
25
90
130
-45
-10
25
90
130
Temperature (C)
Temperature (C)
FIGURE 2-4:
Temperature – 5.0V.
IBBQ Power-Down vs.
FIGURE 2-7:
Temperature – 3.3V.
IBBQ Power-Down vs.
2012-2014 Microchip Technology Inc.
DS20002306B-page 21
MCP2025
3.5
3
+25°C
-40°C
+90°C
2.5
2
+125°C
1.5
1
0.5
0
0
100
200
300
IREG (mA)
FIGURE 2-8:
5.0V VREG vs. IREG at
VBB = 12V.
6
5
4
3
2
1
-40°C
+25°C
+90°C
+125°C
0
0
100
200
300
IREG (mA)
FIGURE 2-9:
3.3V VREG vs. IREG at
VBB = 12V.
DS20002306B-page 22
2012-2014 Microchip Technology Inc.
MCP2025
2.7
Timing Diagrams and Specifications
FIGURE 2-10:
BUS TIMING DIAGRAM
TXD
50%
50%
LBUS
0.95 VLBUS
0.50 VBB
0.05 VLBUS
tTRANSPDR
0.0V
tTRANSPDF
tRECPDF
tRECPDR
RXD
50%
50%
FIGURE 2-11:
REGULATOR BUS WAKE TIMING DIAGRAM
LBUS
VWK(LBUS)
tVEVR
tBACTIVE
tBDB
VREG-NOM
VREG
2012-2014 Microchip Technology Inc.
DS20002306B-page 23
MCP2025
FIGURE 2-12:
CS/LWAKE, REGULATOR AND RESET TIMING DIAGRAM
CS/LWAKE
tCSR
tVEVR
VREG-NOM
VREG
tRPD
tCSPD
tRPU
RESET
DS20002306B-page 24
2012-2014 Microchip Technology Inc.
MCP2025
3.0
3.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (4x4x0.9 mm)
Example
202550
XXXXXX
XXXXXX
YYWW
NNN
e
3
E/MD
1426
256
PIN 1
PIN 1
8-Lead PDIP (300 mil)
Example
XXXXXXXX
XXXXXNNN
2025330
e
3
E/P 256
1426
YYWW
8-Lead SOIC (3.90 mm)
Example
2025-500
E/SN1426
256
NNN
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2012-2014 Microchip Technology Inc.
DS20002306B-page 25
MCP2025
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
DS20002306B-page 26
2012-2014 Microchip Technology Inc.
MCP2025
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
2012-2014 Microchip Technology Inc.
DS20002306B-page 27
MCP2025
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002306B-page 28
2012-2014 Microchip Technology Inc.
MCP2025
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
A2
A
C
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
2012-2014 Microchip Technology Inc.
DS20002306B-page 29
MCP2025
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
INCHES
NOM
8
.100 BSC
-
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
-
.210
.195
-
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
.130
-
.310
.250
.365
.130
.010
.060
.018
-
.325
.280
.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing
§
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
DS20002306B-page 30
2012-2014 Microchip Technology Inc.
MCP2025
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2014 Microchip Technology Inc.
DS20002306B-page 31
MCP2025
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002306B-page 32
2012-2014 Microchip Technology Inc.
MCP2025
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢍꢓꢔꢆꢕꢆꢓꢄꢖꢖꢗꢘꢙꢆꢚꢛꢜꢝꢆꢎꢎꢆꢞꢗꢅꢟꢆꢠꢍꢏꢡꢢꢣ
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ
2012-2014 Microchip Technology Inc.
DS20002306B-page 33
MCP2025
NOTES:
DS20002306B-page 34
2012-2014 Microchip Technology Inc.
MCP2025
APPENDIX A: REVISION HISTORY
Revision B (August 2014)
The following is the list of modifications:
1. Clarified CREG selection.
2. Updated Section 1.6 “Typical Applications”
with values used during ESD tests.
3. Minor typographical corrections.
Revision A (June 2012)
• Original Release of this Document.
2012-2014 Microchip Technology Inc.
DS20002306B-page 35
MCP2025
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
–X
X
/XX
a)
b)
c)
MCP2025-330E/MD: 3.3V, 8-lead DFN package
MCP2025-500E/MD: 5.0V, 8-lead DFN package
MCP2025T-330E/MD: 3.3V, 8-lead DFN package,
Tape and Reel
Voltage
Temperature
Range
Package
d)
MCP2025T-500E/MD: 5.0V, 8-lead DFN package,
Tape and Reel
Device:
Voltage:
MCP2025:
LIN Transceiver with Voltage Regulator
e)
f)
g)
h)
i)
MCP2025-330E/P:
MCP2025-500E/P:
MCP2025-330E/SN: 3.3V, 8-lead SOIC package
MCP2025-500E/SN: 5.0V, 8-lead SOIC package
MCP2025T-330E/SN: 3.3V, 8-lead SOIC package,
Tape and Reel
3.3V, 8-lead PDIP package
5.0V, 8-lead PDIP package
MCP2025T: LIN Transceiver with Voltage Regulator
(Tape and Reel)
330
500
=
=
3.3V
5.0V
j)
MCP2025T-500E/SN: 5.0V, 8-lead SOIC package,
Tape and Reel
Temperature Range:
Package:
E
= -40°C to +125°C
MD
P
=
8LD Plastic Dual Flat, No Lead – 4x4x0.8 mm
Body
=
8LD/14LD Plastic Dual In-Line – 300 mil Body
SN = 8LD Plastic Small Outline – Narrow, 3.90 mm
Body
DS20002306B-page 36
2012-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-499-7
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2012-2014 Microchip Technology Inc.
DS20002306B-page 37
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Austin, TX
Tel: 512-257-3370
Germany - Pforzheim
Tel: 49-7231-424750
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Poland - Warsaw
Tel: 48-22-3325737
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Sweden - Stockholm
Tel: 46-8-5090-4654
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Novi, MI
Tel: 248-848-4000
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Los Angeles
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
DS20002306B-page 38
2012-2014 Microchip Technology Inc.
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