MCP23017-E/MLT [MICROCHIP]
Parallel I/O Port, 16 I/O, CMOS, PQCC28;型号: | MCP23017-E/MLT |
厂家: | MICROCHIP |
描述: | Parallel I/O Port, 16 I/O, CMOS, PQCC28 外围集成电路 |
文件: | 总42页 (文件大小:845K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MCP23017/MCP23S17
16-Bit I/O Expander with Serial Interface
• Configurable Interrupt Source:
Features
- Interrupt-on-change from configured register
defaults or pin changes
• 16-Bit Remote Bidirectional I/O Port:
- I/O pins default to input
• High-Speed I2C Interface (MCP23017):
- 100 kHz
• Polarity Inversion Register to Configure the
Polarity of the Input Port Data
• External Reset Input
- 400 kHz
• Low Standby Current: 1 µA (max.)
• Operating Voltage:
- 1.7 MHz
• High-Speed SPI Interface (MCP23S17):
- 10 MHz (maximum)
- 1.8V to 5.5V @ -40°C to +85°C
- 2.7V to 5.5V @ -40°C to +85°C
- 4.5V to 5.5V @ -40°C to +125°C
• Three Hardware Address Pins to Allow Up to
Eight Devices On the Bus
• Configurable Interrupt Output Pins:
Packages
- Configurable as active-high, active-low or
open-drain
• 28-pin QFN, 6 x 6 mm Body
• 28-pin SOIC, Wide, 7.50 mm Body
• 28-pin SPDIP, 300 mil Body
• 28-pin SSOP, 5.30 mm Body
• INTA and INTB Can Be Configured to Operate
Independently or Together
Package Types
MCP23017
MCP23S17
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
RESET
A2
GPB0
GPB1
GPB2
GPB3
GPB4
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
RESET
A2
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
GPB5
SOIC
SPDIP
SSOP
GPB6
GPB7
VDD
V
DD
V
SS
VSS
NC
SCK
SDA
NC
CS
SCK
SI
A1
A0
A1
A0
SO
28272625242322
21
28272625242322
21
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
GPB4
GPB5
GPB6
GPB7
VDD
1
2
3
4
5
6
7
GPB4
1
2
3
4
5
6
7
20
19
18
17
16
15
20
19
18
17
16
15
GPB5
GPB6
GPB7
QFN
EP
29 *
EP
29 *
V
DD
V
SS
VSS
INTB
INTB
NC
CS
8 9 1011121314
8 9 1011121314
* Includes Exposed Thermal Pad; see Table 2-1.
2005-2016 Microchip Technology Inc.
DS20001952C-page 1
MCP23017/MCP23S17
Functional Block Diagram
MCP23S17
CS
SCK
SI
SPI
SO
MCP23017
GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0
Serializer/
Deserializer
SCL
SDA
I2C
3
GPIO
A2:A0
Decode
RESET
Control
16
INTA
INTB
Interrupt
Logic
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
8
GPIO
Configuration/
Control
Registers
DS20001952C-page 2
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature ...............................................................................................................................-65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +5.5V
Voltage on all other pins with respect to VSS (except VDD)............................................................. -0.6V to (VDD + 0.6V)
Total power dissipation.........................................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................125 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA
Maximum output current sunk by any output pin ....................................................................................................25 mA
Maximum output current sourced by any output pin ...............................................................................................25 mA
ESD protection on all pins (HBM:MM) ..............................................................................................................4 kV:400V
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
2005-2016 Microchip Technology Inc.
DS20001952C-page 3
MCP23017/MCP23S17
1.1
DC Characteristics
TABLE 1-1:
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No.
Characteristic
Sym.
Min.
Typ.(1)
Max.
Units
Conditions
D001 Supply Voltage
VDD
1.8
—
—
5.5
—
V
V
D002 VDD Start Voltage to
ensure Power-on Reset
VPOR
VSS
D003 VDD Rise Rate to ensure
Power-on Reset
SVDD
0.05
—
—
V/ms Design guidance only.
Not tested.
D004 Supply Current
D005 Standby current
IDD
—
—
—
—
—
—
1
1
3
mA
µA
µA
SCL/SCK = 1 MHz
IDDS8
-40°C TA +85°C
4.5V VDD 5.5V
+85°C TA +125C
(Note 1)
Input Low Voltage
D030 A0, A1, A2 (TTL buffer)
VIL
VIL
VSS
VSS
—
—
0.15 VDD
0.2 VDD
V
V
D031 CS, GPIO, SCL/SCK,
SDA, RESET
(Schmitt Trigger)
Input High Voltage
D040 A0, A1, A2 (TTL buffer)
VIH
VIH
0.25 VDD + 0.8
0.8 VDD
—
—
VDD
VDD
V
V
D041 CS, GPIO, SCL/SCK,
SDA, RESET
For entire VDD range
(Schmitt Trigger)
Input Leakage Current
D060 I/O port pins
IIL
—
—
±1
µA
VSS VPIN VDD
VSS VPIN VDD
Output Leakage Current
D065 I/O port pins
ILO
IPU
—
—
±1
µA
µA
D070 GPIO weak pull-up
current
40
75
115
VDD = 5V
GP pins = VSS
Output Low-Voltage
D080 GPIO
VOL
VOL
VOL
VOL
—
—
—
—
—
—
—
—
0.6
0.6
0.6
0.8
V
V
V
V
IOL = 8.0 mA
VDD = 4.5V
INT
IOL = 1.6 mA
VDD = 4.5V
SO, SDA
SDA
IOL = 3.0 mA
VDD = 1.8V
IOL = 3.0 mA
VDD = 4.5V
Output High-Voltage
D090 GPIO, INT, SO
VOH
VDD – 0.7
VDD – 0.7
—
—
—
—
V
IOH = -3.0 mA
DD = 4.5V
V
IOH = -400 µA
VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101 GPIO, SO, INT
D102 SDA
CIO
CB
—
—
—
—
50
pF
pF
400
Note 1: This parameter is characterized, not 100% tested.
DS20001952C-page 4
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
1.2
AC Characteristics
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
VDD
FIGURE 1-1:
Pin
1 k
SCL and
SDA pin
50 pF
MCP23017
135 pF
FIGURE 1-2:
RESET AND DEVICE RESET TIMER TIMING
VDD
RESET
30
32
Internal
RESET
34
Output pin
TABLE 1-2:
DEVICE RESET SPECIFICATIONS
AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No.
Characteristic
Sym.
Min.
Typ. (1) Max.
Units
Conditions
30
RESET Pulse Width
(Low)
TRSTL
1
—
0
—
—
1
µs
32
34
Device Active After Reset
high
THLD
—
—
ns
µs
VDD = 5.0V
Output High-Impedance
From RESET Low
TIOZ
—
Note 1: This parameter is characterized, not 100% tested.
2005-2016 Microchip Technology Inc.
DS20001952C-page 5
MCP23017/MCP23S17
FIGURE 1-3:
I2C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
Stop
Condition
Start
Condition
FIGURE 1-4:
I2C BUS DATA TIMING
103
102
92
100
101
109
SCL
90
106
91
107
SDA
In
110
109
SDA
Out
TABLE 1-3:
I2C BUS DATA REQUIREMENTS
I2C Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C, RPU (SCL,
SDA) = 1 k, CL (SCL, SDA) = 135 pF
Param.
No.
Characteristic
Sym.
Min.
Typ. Max. Units
Conditions
100 Clock High Time:
100 kHz mode
THIGH
4.0
0.6
—
—
—
—
—
—
µs 1.8V – 5.5V
400 kHz mode
µs 2.7V – 5.5V
µs 4.5V – 5.5V
1.7 MHz mode
0.12
101 Clock Low Time:
100 kHz mode
TLOW
4.7
1.3
—
—
—
—
—
—
µs 1.8V – 5.5V
µs 2.7V – 5.5V
µs 4.5V – 5.5V
400 kHz mode
1.7 MHz mode
0.32
(1)
102 SDA and SCL Rise Time:
100 kHz mode
TR
—
20 + 0.1 CB
20
—
—
—
1000
300
ns 1.8V – 5.5V
ns 2.7V – 5.5V
ns 4.5V – 5.5V
(2)
(2)
400 kHz mode
1.7 MHz mode
160
(1)
103 SDA and SCL Fall Time:
100 kHz mode
TF
—
20 + 0.1 CB
20
—
—
—
300
300
80
ns 1.8V – 5.5V
ns 2.7V – 5.5V
ns 4.5V – 5.5V
400 kHz mode
1.7 MHz mode
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified to be from 10 to 400 pF.
DS20001952C-page 6
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
TABLE 1-3:
I2C BUS DATA REQUIREMENTS (CONTINUED)
I2C Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C, RPU (SCL,
SDA) = 1 k, CL (SCL, SDA) = 135 pF
Param.
No.
Characteristic
Sym.
Min.
Typ. Max. Units
Conditions
90
START Condition Setup Time:
100 kHz mode
TSU:STA
4.7
0.6
—
—
—
—
—
—
µs 1.8V – 5.5V
400 kHz mode
µs 2.7V – 5.5V
µs 4.5V – 5.5V
1.7 MHz mode
0.16
91
START Condition Hold Time:
100 kHz mode
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
4.0
0.6
—
—
—
—
—
—
µs 1.8V – 5.5V
µs 2.7V – 5.5V
µs 4.5V – 5.5V
400 kHz mode
1.7 MHz mode
0.16
106 Data Input Hold Time:
100 kHz mode
0
0
0
—
—
—
3.45
0.9
µs 1.8V – 5.5V
µs 2.7V – 5.5V
µs 4.5V – 5.5V
400 kHz mode
1.7 MHz mode
0.15
107 Data Input Setup Time:
100 kHz mode
250
100
0.01
—
—
—
—
—
—
ns 1.8V – 5.5V
ns 2.7V – 5.5V
µs 4.5V – 5.5V
400 kHz mode
1.7 MHz mode
92
Stop Condition Setup Time:
100 kHz mode
4.0
0.6
—
—
—
—
—
—
µs 1.8V – 5.5V
µs 2.7V – 5.5V
µs 4.5V–5.5V
400 kHz mode
1.7 MHz mode
0.16
109 Output Valid From Clock:
100 kHz mode
—
—
—
—
—
—
3.45
0.9
µs 1.8V – 5.5V
µs 2.7V – 5.5V
µs 4.5V – 5.5V
400 kHz mode
1.7 MHz mode
0.18
110
Bus Free Time:
100 kHz mode
TBUF
4.7
1.3
N/A
—
—
—
—
—
µs 1.8V – 5.5V
µs 2.7V – 5.5V
µs 4.5V – 5.5V
400 kHz mode
1.7 MHz mode
N/A
111
112
Bus Capacitive Loading:
100 kHz and 400 kHz
1.7 MHz
CB
—
—
—
—
400
100
pF Note 1
pF Note 1
Input Filter Spike Suppression
(SDA and SCL):
TSP
100 kHz and 400 kHz
1.7 MHz
—
—
—
—
50
10
ns
ns Spike suppression off
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified to be from 10 to 400 pF.
2005-2016 Microchip Technology Inc.
DS20001952C-page 7
MCP23017/MCP23S17
FIGURE 1-5:
SPI INPUT TIMING
3
CS (1)
11
10
6
1
2
7
Mode 1,1
SCK
SI
Mode 0,0
4
5
MSB in
LSB in
High-Impedance
SO
Note 1: When using SPI Mode 1,1 the CS pin needs to be toggled once before the first communication after
power-up.
FIGURE 1-6:
SPI OUTPUT TIMING
CS
2
8
9
SCK
Mode 1,1
Mode 0,0
12
14
13
SO
SI
MSB out
LSB out
Don’t Care
TABLE 1-4:
SPI INTERFACE REQUIREMENTS
SPI Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No.
Characteristic
Clock Frequency
Sym.
Min.
Typ.
Max. Units
Conditions
—
FCLK
—
—
—
—
—
—
—
—
—
—
—
—
5
MHz 1.8V – 5.5V
MHz 2.7V – 5.5V
10
10
—
—
—
—
—
—
—
—
MHz 4.5V – 5.5V
ns
1
2
CS Setup Time
CS Hold Time
TCSS
TCSH
50
100
50
100
50
20
10
ns
ns
ns
ns
ns
ns
1.8V – 5.5V
2.7V – 5.5V
1.8V – 5.5V
2.7V – 5.5V
1.8V – 5.5V
2.7V – 5.5V
3
4
CS Disable Time
Data Setup Time
TCSD
TSU
Note 1: This parameter is characterized, not 100% tested.
DS20001952C-page 8
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
TABLE 1-4:
SPI INTERFACE REQUIREMENTS (CONTINUED)
SPI Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No.
Characteristic
Data Hold Time
Sym.
Min.
Typ.
Max. Units
Conditions
1.8V – 5.5V
5
THD
20
10
—
—
90
45
90
45
50
50
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7V – 5.5V
Note 1
6
7
8
CLK Rise Time
CLK Fall Time
Clock High Time
TR
TF
2
Note 1
THI
—
—
—
—
—
—
90
45
—
100
1.8V – 5.5V
2.7V – 5.5V
1.8V – 5.5V
2.7V – 5.5V
9
Clock Low Time
TLO
10
11
12
Clock Delay Time
TCLD
TCLE
TV
Clock Enable Time
Output Valid from Clock Low
1.8V – 5.5V
2.7V – 5.5V
13
14
Output Hold Time
THO
TDIS
Output Disable Time
—
Note 1: This parameter is characterized, not 100% tested.
FIGURE 1-7:
GPIO AND INT TIMING
SCL/SCK
SDA/SI
In
D1
D0
LSb of data byte zero
during a write or read
command, depending
on parameter
50
GPn
Output
Pin
51
INT
Pin
Inactive
53
INT Pin Active
GPn
Input
Pin
52
Register
Loaded
2005-2016 Microchip Technology Inc.
DS20001952C-page 9
MCP23017/MCP23S17
TABLE 1-5:
GP AND INT PINS REQUIREMENTS
GP and INT Pins AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No.
Characteristic
Sym.
Min.
Typ.
Max. Units
Conditions
50
51
52
Serial Data to Output Valid TGPOV
—
—
—
—
—
—
500
600
450
ns
ns
ns
Interrupt Pin Disable Time
TINTD
TGPIV
GP Input Change to
Register Valid
53
IOC Event to INT Active
Glitch Filter on GP Pins
TGPINT
—
—
—
—
600
150
ns
ns
TGLITCH
Note 1
Note 1: This parameter is characterized, not 100% tested.
DS20001952C-page 10
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PINOUT DESCRIPTION
SOIC
QFN SPDIP
Pin
Name
Pin
Type
Function
SSOP
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
25
26
27
28
1
1
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
2
3
4
5
2
6
3
7
4
8
V
V
5
9
P
P
I
Power
DD
SS
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
—
Ground
NC/CS
SCK
7
NC (MCP23017)/Chip Select (MCP23S17)
8
I
Serial clock input
SDA/SI
NC/SO
A0
9
I/O Serial data I/O (MCP23017)/Serial data input (MCP23S17)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
29
O
I
NC (MCP23017)/Serial data out (MCP23S17)
Hardware address pin. Must be externally biased.
A1
I
Hardware address pin. Must be externally biased.
A2
I
Hardware address pin. Must be externally biased.
RESET
INTB
INTA
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
EP
I
Hardware reset. Must be externally biased.
O
O
Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.
Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
—
Exposed Thermal Pad. Either connect to V , or leave unconnected.
SS
2005-2016 Microchip Technology Inc.
DS20001952C-page 11
MCP23017/MCP23S17
3.2
Serial Interface
3.0
DEVICE OVERVIEW
This block handles the functionality of the I2C
(MCP23017) or SPI (MCP23S17) interface protocol.
The MCP23X17 contains 22 individual registers (11
register pairs) that can be addressed through the Serial
Interface block, as shown in Table 3-1.
The MCP23017/MCP23S17 (MCP23X17) device
family provides 16-bit, general purpose parallel I/O
expansion for I2C bus or SPI applications. The two
devices differ only in the serial interface:
• MCP23017 – I2C interface
• MCP23S17 – SPI interface
TABLE 3-1:
Address
IOCON.BANK = 1 IOCON.BANK = 0
REGISTER ADDRESSES
Address
The MCP23X17 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits (IODIRA/B).
The data for each input or output is kept in the
corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity
Inversion register. All registers can be read by the
system master.
Access to:
00h
10h
01h
11h
02h
12h
03h
13h
04h
14h
05h
15h
06h
16h
07h
17h
08h
18h
09h
19h
0Ah
1Ah
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
IODIRA
IODIRB
IPOLA
IPOLB
GPINTENA
GPINTENB
DEFVALA
DEFVALB
INTCONA
INTCONB
IOCON
The 16-bit I/O port functionally consists of two 8-bit
ports (PORTA and PORTB). The MCP23X17 can be
configured to operate in the 8-bit or 16-bit modes via
IOCON.BANK.
There are two interrupt pins, INTA and INTB, that can
be associated with their respective ports, or can be
logically OR’ed together so that both pins will activate if
either port causes an interrupt.
IOCON
GPPUA
GPPUB
INTFA
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1. When any input state differs from its
corresponding Input Port register state. This is
used to indicate to the system master that an
input state has changed.
INTFB
INTCAPA
INTCAPB
GPIOA
2. When an input state differs from a preconfigured
register value (DEFVAL register).
GPIOB
OLATA
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
OLATB
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pins are used to determine the
device address.
3.1
Power-on Reset (POR)
The on-chip POR circuit holds the device in reset until
DD has reached a high enough voltage to deactivate
V
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in Section 1.0
“Electrical Characteristics”.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
DS20001952C-page 12
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
These two modes are not to be confused with single
writes/reads and continuous writes/reads that are
serial protocol sequences. For example, the device
may be configured for Byte mode and the master may
3.2.1
BYTE MODE AND SEQUENTIAL
MODE
The MCP23X17 family has the ability to operate in Byte
mode or Sequential mode (IOCON.SEQOP).
perform
a continuous read. In this case, the
Byte mode disables automatic Address Pointer
incrementing. When operating in Byte mode, the
MCP23X17 family does not increment its internal
address counter after each byte during the data
transfer. This gives the ability to continually access the
same address by providing extra clocks (without
additional control bytes). This is useful for polling the
GPIO register for data changes or for continually
writing to the output latches.
MCP23X17 would not increment the Address Pointer
and would repeatedly drive data from the same
location.
3.2.2
I2C INTERFACE
3.2.2.1
I2C Write Operation
The I2C write operation includes the control byte and
register address sequence, as shown in Figure 3-1.
This sequence is followed by eight bits of data from the
master and an Acknowledge (ACK) from the
MCP23017. The operation is ended with a Stop (P) or
Restart (SR) condition being generated by the master.
A special mode (Byte mode with IOCON.BANK = 0)
causes the address pointer to toggle between
associated A/B register pairs. For example, if the BANK
bit is cleared and the Address Pointer is initially set to
address 12h (GPIOA) or 13h (GPIOB), the pointer will
toggle between GPIOA and GPIOB. Note that the
Address Pointer can initially point to either address in
the register pair.
Data is written to the MCP23017 after every byte
transfer. If a Stop or Restart condition is generated
during a data transfer, the data will not be written to the
MCP23017.
Sequential mode enables automatic address pointer
incrementing. When operating in Sequential mode, the
MCP23X17 family increments its address counter after
each byte during the data transfer. The Address Pointer
automatically rolls over to address 00h after accessing
the last register.
Both “byte writes” and “sequential writes” are
supported by the MCP23017. If Sequential mode is
enabled
(IOCON,
SEQOP = 0) (default),
the
MCP23017 increments its address counter after each
ACK during the data transfer.
FIGURE 3-1:
BYTE AND SEQUENTIAL WRITE
- Start
S
SR
P
DIN
DIN
S
S
OP
OP
W
W
ADDR
ADDR
P
Byte
- Restart
DIN
....
P
Sequential
- Stop
- Write
- Read
W
R
- Device opcode
ADDR - Device register address
OP
DOUT
DIN
- Data out from MCP23017
- Data in to MCP23017
2005-2016 Microchip Technology Inc.
DS20001952C-page 13
MCP23017/MCP23S17
3.2.2.2
I2C Read Operation
I2C Read operations include the control byte sequence,
as shown in Figure 3-2. This sequence is followed by
another control byte (including the Start condition and
ACK) with the R/W bit set (R/W = 1). The MCP23017
then transmits the data contained in the addressed
register. The sequence is ended with the master
generating a Stop or Restart condition.
FIGURE 3-2:
BYTE AND SEQUENTIAL READ
DOUT
DOUT
Byte
S
S
W
W
OP
OP
SR OP
SR OP
R
R
P
DOUT
Sequential
....
P
I2C Sequential Write/Read
The sequence ends with the master sending a Stop or
Restart condition.
3.2.2.3
For sequential operations (Write or Read), instead of
transmitting a Stop or Restart condition after the data
transfer, the master clocks the next byte pointed to by
the address pointer (see Section 3.2.1 “Byte Mode
and Sequential Mode” for details regarding sequential
operation control).
The MCP23017 Address Pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 3-3.
FIGURE 3-3:
MCP23017 I2C DEVICE PROTOCOL
DIN
DIN
S
OP
W
ADDR
....
P
D OUT
DOUT
SR
OP
OP
R
P
P
....
....
DIN
DIN
SR
P
W
DOUT
DOUT
P
....
S
OP
R
DOUT
DOUT
SR
OP
R
P
....
....
DIN
DIN
P
SR
OP
W
ADDR
P
DS20001952C-page 14
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
four fixed bits and three user-defined hardware
address bits (pins A2, A1 and A0). Figure 3-4 shows
the control byte format.
3.2.3
SPI INTERFACE
3.2.3.1
SPI Write Operation
The SPI write operation is started by lowering CS. The
Write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
3.3.2
ADDRESSING SPI DEVICES
(MCP23S17)
The MCP23S17 is a slave SPI device. The slave
address contains four fixed bits and three user-defined
hardware address bits (if enabled via IOCON.HAEN)
(pins A2, A1 and A0) with the read/write bit filling out
the control byte. Figure 3-5 shows the control byte
format. The address pins should be externally biased
even if disabled (IOCON.HAEN = 0).
3.2.3.2
SPI Read Operation
The SPI read operation is started by lowering CS. The
SPI read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
FIGURE 3-4:
I2C CONTROL BYTE
FORMAT
3.2.3.3
SPI Sequential Write/Read
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the Address Pointer. (see Section 3.2.1
“Byte Mode and Sequential Mode” for details
regarding sequential operation control).
Control Byte
A2 A1 A0 R/W ACK
S
0
1
0
0
Slave Address
R/W bit
The sequence ends by the raising of CS.
Start
bit
The MCP23S17 Address Pointer will roll over to
address zero after reaching the last register address.
ACK bit
R/W = 0= write
R/W = 1= read
3.3
Hardware Address Decoder
FIGURE 3-5:
SPI CONTROL BYTE
FORMAT
The hardware address pins are used to determine the
device address. To address a device, the correspond-
ing address bits in the control byte must match the pin
state. The pins must be biased externally.
CS
ADDRESSING I2C DEVICES
Control Byte
3.3.1
(MCP23017)
0
1
0
0
A2 A1 A0 R/W
The MCP23017 is a slave I2C interface device that
supports 7-bit slave addressing, with the read/write bit
filling out the control byte. The slave address contains
Slave Address
R/W bit
R/W = 0= write
R/W = 1= read
FIGURE 3-6:
I2C ADDRESSING REGISTERS
A2 A1 A0 ACK * A7
S
0
1
0
0
0
A6
A5
A4
A3
A2
A1
A0 ACK *
R/W = 0
Device Opcode
Register Address
*The ACKs are provided by the MCP23017.
2005-2016 Microchip Technology Inc.
DS20001952C-page 15
MCP23017/MCP23S17
FIGURE 3-7:
SPI ADDRESSING REGISTERS
CS
0
1
0
0
A2 * A1 * A0 * R/W A7
A6
A5
A4
A3
A2
A1
A0
Device Opcode
Register Address
* Address pins are enabled/disabled via IOCON.HAEN.
Reading the GPIOn register reads the value on the
port. Reading the OLATn register only reads the
latches, not the actual value on the port.
3.4
GPIO Port
The GPIO module is a general purpose, 16-bit wide,
bidirectional port that is functionally split into two
8-bit wide ports.
Writing to the GPIOn register actually causes a write to
the latches (OLATn). Writing to the OLATn register
forces the associated output drivers to drive to the level
in OLATn. Pins configured as inputs turn off the
associated output driver and put it in high-impedance.
The GPIO module contains the data ports (GPIOn),
internal pull-up resistors and the output latches
(OLATn).
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1)
Register
Name
Address
(hex)
POR/RST
value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IODIRA
IPOLA
00
01
02
06
09
0A
10
11
12
16
19
1A
IO7
IP7
IO6
IP6
IO5
IP5
IO4
IP4
IO3
IP3
IO2
IP2
IO1
IP1
IO0
IP0
1111 1111
0000 0000
GPINTENA
GPPUA
GPIOA
GPINT7
PU7
GPINT6
PU6
GPINT5
PU5
GPINT4
PU4
GPINT3
PU3
GPINT2
PU2
GPINT1
PU1
GPINT0 0000 0000
PU0
GP0
OL0
IO0
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
GP7
OL7
GP6
OL6
GP5
OL5
GP4
OL4
GP3
OL3
GP2
OL2
GP1
OL1
OLATA
IODIRB
IPOLB
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
GPINTENB
GPPUB
GPIOB
GPINT7
PU7
GPINT6
PU6
GPINT5
PU5
GPINT4
PU4
GPINT3
PU3
GPINT2
PU2
GPINT1
PU1
GPINT0 0000 0000
PU0
GP0
OL0
0000 0000
0000 0000
0000 0000
GP7
OL7
GP6
OL6
GP5
OL5
GP4
OL4
GP3
OL3
GP2
OL2
GP1
OL1
OLATB
TABLE 3-3:
SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0)
Register
Name
Address
(hex)
POR/RST
value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IODIRA
IODIRB
IPOLA
00
01
02
03
04
05
0C
0D
12
13
14
15
IO7
IO7
IO6
IO6
IO5
IO5
IO4
IO4
IO3
IO3
IO2
IO2
IO1
IO1
IO0
IO0
IP0
IP0
1111 1111
1111 1111
0000 0000
0000 0000
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IPOLB
IP7
IP6
IP5
IP4
IP3
IP2
IP1
GPINTENA
GPINTENB
GPPUA
GPPUB
GPIOA
GPINT7
GPINT7
PU7
GPINT6
GPINT6
PU6
GPINT5
GPINT5
PU5
GPINT4
GPINT4
PU4
GPINT3
GPINT3
PU3
GPINT2
GPINT2
PU2
GPINT1
GPINT1
PU1
GPINT0 0000 0000
GPINT0 0000 0000
PU0
PU0
GP0
GP0
OL0
OL0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
PU7
PU6
PU5
PU4
PU3
PU2
PU1
GP7
GP7
OL7
GP6
GP6
OL6
GP5
GP5
OL5
GP4
GP4
OL4
GP3
GP3
OL3
GP2
GP2
OL2
GP1
GP1
OL1
GPIOB
OLATA
OLATB
OL7
OL6
OL5
OL4
OL3
OL2
OL1
DS20001952C-page 16
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
associated with PORTB. One register (IOCON) is
shared between the two ports. The PORTA registers
are identical to the PORTB registers, therefore, they
will be referred to without differentiating between the
port designation (i.e., they will not have the “A” or “B”
designator assigned) in the register tables.
3.5
Configuration and Control
Registers
There are 21 registers associated with the MCP23X17,
as shown in Tables 3-4 and3-5. The two tables show
the register mapping with the two BANK bit values. Ten
registers are associated with PORTA and ten are
TABLE 3-4:
CONTROL REGISTER SUMMARY (IOCON.BANK = 1)
Register
Name
Address
(hex)
POR/RST
value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IODIRA
IPOLA
00
01
02
03
04
05
06
07
08
09
0A
10
11
12
13
14
15
16
17
18
19
1A
IO7
IP7
IO6
IP6
IO5
IP5
IO4
IP4
IO3
IP3
IO2
IP2
IO1
IP1
IO0
IP0
1111 1111
0000 0000
GPINTENA
DEFVALA
INTCONA
IOCON
GPINT7
DEF7
IOC7
BANK
PU7
GPINT6
DEF6
IOC6
GPINT5
DEF5
IOC5
GPINT4
DEF4
IOC4
DISSLW
PU4
GPINT3
DEF3
IOC3
HAEN
PU3
GPINT2
DEF2
IOC2
ODR
PU2
GPINT1
DEF1
IOC1
INTPOL
PU1
GPINT0 0000 0000
DEF0
IOC0
—
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
MIRROR SEQOP
GPPUA
INTFA
PU6
INT6
ICP6
GP6
PU5
INT5
ICP5
GP5
PU0
INTO
ICP0
GP0
OL0
IO0
INT7
ICP7
GP7
INT4
INT3
ICP3
GP3
INT2
ICP2
GP2
INT1
ICP1
GP1
INTCAPA
GPIOA
ICP4
GP4
OLATA
OL7
OL6
OL5
OL4
OL3
OL2
OL1
IODIRB
IPOLB
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
GPINTENB
DEFVALB
INTCONB
IOCON
GPINT7
DEF7
IOC7
BANK
PU7
GPINT6
DEF6
IOC6
GPINT5
DEF5
IOC5
GPINT4
DEF4
IOC4
DISSLW
PU4
GPINT3
DEF3
IOC3
HAEN
PU3
GPINT2
DEF2
IOC2
ODR
PU2
GPINT1
DEF1
IOC1
INTPOL
PU1
GPINT0 0000 0000
DEF0
IOC0
—
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
MIRROR SEQOP
GPPUB
INTFB
PU6
INT6
ICP6
GP6
OL6
PU5
INT5
ICP5
GP5
OL5
PU0
INTO
ICP0
GP0
OL0
INT7
ICP7
GP7
INT4
INT3
ICP3
GP3
INT2
ICP2
GP2
INT1
ICP1
GP1
INTCAPB
GPIOB
ICP4
GP4
OLATB
OL7
OL4
OL3
OL2
OL1
TABLE 3-5:
CONTROL REGISTER SUMMARY (IOCON.BANK = 0)
Register
Name
Address
(hex)
POR/RST
value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IODIRA
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
IO7
IO7
IO6
IO6
IO5
IO5
IO4
IO4
IO3
IO3
IO2
IO2
IO1
IO1
IO0
IO0
IP0
IP0
1111 1111
1111 1111
0000 0000
0000 0000
IODIRB
IPOLA
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IPOLB
IP7
IP6
IP5
IP4
IP3
IP2
IP1
GPINTENA
GPINTENB
DEFVALA
DEFVALB
INTCONA
INTCONB
IOCON
GPINT7
GPINT7
DEF7
DEF7
IOC7
IOC7
BANK
BANK
PU7
GPINT6
GPINT6
DEF6
DEF6
IOC6
IOC6
GPINT5
GPINT5
DEF5
DEF5
IOC5
IOC5
GPINT4
GPINT4
DEF4
DEF4
IOC4
IOC4
DISSLW
DISSLW
PU4
GPINT3
GPINT3
DEF3
DEF3
IOC3
IOC3
HAEN
HAEN
PU3
GPINT2
GPINT2
DEF2
DEF2
IOC2
IOC2
ODR
ODR
PU2
GPINT1
GPINT1
DEF1
DEF1
IOC1
IOC1
INTPOL
INTPOL
PU1
GPINT0 0000 0000
GPINT0 0000 0000
DEF0
DEF0
IOC0
IOC0
—
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
MIRROR SEQOP
MIRROR SEQOP
IOCON
—
GPPUA
PU6
PU6
PU5
PU5
PU0
PU0
GPPUB
PU7
PU4
PU3
PU2
PU1
2005-2016 Microchip Technology Inc.
DS20001952C-page 17
MCP23017/MCP23S17
TABLE 3-5:
CONTROL REGISTER SUMMARY (IOCON.BANK = 0) (CONTINUED)
Register
Name
Address
(hex)
POR/RST
value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTFA
0E
0F
10
11
12
13
14
15
INT7
INT7
ICP7
ICP7
GP7
GP7
OL7
OL7
INT6
INT6
ICP6
ICP6
GP6
GP6
OL6
OL6
INT5
INT5
ICP5
ICP5
GP5
GP5
OL5
OL5
INT4
INT4
ICP4
ICP4
GP4
GP4
OL4
OL4
INT3
INT3
ICP3
ICP3
GP3
GP3
OL3
OL3
INT2
INT2
ICP2
ICP2
GP2
GP2
OL2
INT1
INT1
ICP1
ICP1
GP1
GP1
OL1
OL1
INTO
INTO
ICP0
ICP0
GP0
GP0
OL0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
INTFB
INTCAPA
INTCAPB
GPIOA
GPIOB
OLATA
OLATB
OL2
OL0
3.5.1
I/O DIRECTION REGISTER
Controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an
input. When a bit is clear, the corresponding pin
becomes an output.
REGISTER 3-1:
IODIR: I/O DIRECTION REGISTER (ADDR 0x00)
R/W-1
IO7
R/W-1
IO6
R/W-1
IO5
R/W-1
IO4
R/W-1
IO3
R/W-1
IO2
R/W-1
IO1
R/W-1
IO0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
IO<7:0>: Controls the direction of data I/O <7:0>
1= Pin is configured as an input.
0= Pin is configured as an output.
3.5.2
INPUT POLARITY REGISTER
This register allows the user to configure the polarity on
the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will
reflect the inverted value on the pin.
REGISTER 3-2:
IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)
R/W-0
IP7
R/W-0
IP6
R/W-0
IP5
R/W-0
IP4
R/W-0
IP3
R/W-0
IP2
R/W-0
IP1
R/W-0
IP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
IP<7:0>: Controls the polarity inversion of the input pins <7:0>
1= GPIO register bit reflects the opposite logic state of the input pin.
0= GPIO register bit reflects the same logic state of the input pin.
DS20001952C-page 18
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
3.5.3
The
INTERRUPT-ON-CHANGE
CONTROL REGISTER
GPINTEN
register
controls
the
interrupt-on-change feature for each pin.
If a bit is set, the corresponding pin is enabled for
interrupt-on-change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for interrupt-on-change.
REGISTER 3-3:
GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)
R/W-0
GPINT7
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
GPINT<7:0>: General purpose I/O interrupt-on-change bits <7:0>
1= Enables GPIO input pin for interrupt-on-change event.
0= Disables GPIO input pin for interrupt-on-change event.
Note 1: Refer to INTCON.
3.5.4
DEFAULT COMPARE REGISTER
FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
interrupt to occur.
REGISTER 3-4:
DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)
R/W-0
DEF7
R/W-0
DEF6
R/W-0
DEF5
R/W-0
DEF4
R/W-0
DEF3
R/W-0
DEF2
R/W-0
DEF1
R/W-0
DEF0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
DEF<7:0>: Sets the compare value for pins configured for interrupt-on-change from defaults <7:0>
(Note 1)
If the associated pin level is the opposite from the register bit, an interrupt occurs. (Note 2)
Note 1: Refer to INTCON.
2: Refer to INTCON and GPINTEN.
2005-2016 Microchip Technology Inc.
DS20001952C-page 19
MCP23017/MCP23S17
3.5.5
INTERRUPT CONTROL REGISTER
The INTCON register controls how the associated pin
value is compared for the interrupt-on-change feature.
If a bit is set, the corresponding I/O pin is compared
against the associated bit in the DEFVAL register. If a
bit value is clear, the corresponding I/O pin is compared
against the previous value.
REGISTER 3-5:
INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)
R/W-0
IOC7
R/W-0
IOC6
R/W-0
IOC5
R/W-0
IOC4
R/W-0
IOC3
R/W-0
IOC2
R/W-0
IOC1
R/W-0
IOC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
IOC<7:0>: Controls how the associated pin value is compared for interrupt-on-change <7:0>
1= Pin value is compared against the associated bit in the DEFVAL register.
0= Pin value is compared against the previous pin value.
Note 1: Refer to INTCON and GPINTEN.
3.5.6 CONFIGURATION REGISTER
For this reason, when changing the BANK bit, it is
advised to only perform byte writes to this register.
The IOCON register contains several bits for
configuring the device:
The MIRROR bit controls how the INTA and INTB pins
function with respect to each other.
The BANK bit changes how the registers are mapped
(see Tables 3-4 and3-5 for more details).
• When MIRROR = 1, the INTn pins are functionally
OR’ed so that an interrupt on either port will cause
both pins to activate.
• If BANK = 1, the registers associated with each
port are segregated. Registers associated with
PORTA are mapped from address 00h - 0Ah and
registers associated with PORTB are mapped
from 10h - 1Ah.
• When MIRROR = 0, the INT pins are separated.
Interrupt conditions on a port will cause its
respective INT pin to activate.
The Sequential Operation (SEQOP) controls the
incrementing function of the Address Pointer. If the
address pointer is disabled, the Address Pointer does
not automatically increment after each byte is clocked
during a serial transfer. This feature is useful when it is
desired to continuously poll (read) or modify (write) a
register.
• If BANK = 0, the A/B registers are paired. For
example, IODIRA is mapped to address 00h and
IODIRB is mapped to the next address (address
01h). The mapping for all registers is from 00h
-15h.
It is important to take care when changing the BANK bit
as the address mapping changes after the byte is
clocked into the device. The address pointer may point
to an invalid location after the bit is modified.
The Slew Rate (DISSLW) bit controls the slew rate
function on the SDA pin. If enabled, the SDA slew rate
will be controlled when driving from a high to low.
For example, if the device is configured to
automatically increment its internal Address Pointer,
the following scenario would occur:
The Hardware Address Enable (HAEN) bit
enables/disables hardware addressing on the
MCP23S17 only. The address pins (A2, A1 and A0)
must be externally biased, regardless of the HAEN bit
value.
• BANK = 0
• Write 80h to address 0Ah (IOCON) to set the
BANK bit
If enabled (HAEN = 1), the device’s hardware address
matches the address pins.
• Once the write completes, the internal address
now points to 0Bh which is an invalid address
when the BANK bit is set.
If disabled (HAEN = 0), the device’s hardware address
is A2 = A1 = A0 = 0.
DS20001952C-page 20
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
The Open-Drain (ODR) control bit enables/disables the
INT pin for open-drain configuration. Setting this bit
overrides the INTPOL bit.
The Interrupt Polarity (INTPOL) sets the polarity of the
INT pin. This bit is functional only when the ODR bit is
cleared, configuring the INT pin as active push-pull.
REGISTER 3-6:
IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)
R/W-0
BANK
R/W-0
R/W-0
R/W-0
R/W-0
HAEN
R/W-0
ODR
R/W-0
U-0
—
SEQOP
DISSLW
INTPOL
MIRROR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
BANK: Controls how the registers are addressed
1= The registers associated with each port are separated into different banks.
0= The registers are in the same bank (addresses are sequential).
MIRROR: INT Pins Mirror bit
1= The INT pins are internally connected
0= The INT pins are not connected. INTA is associated with PORTA and INTB is associated with
PORTB
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SEQOP: Sequential Operation mode bit
1= Sequential operation disabled, address pointer does not increment.
0= Sequential operation enabled, address pointer increments.
DISSLW: Slew Rate control bit for SDA output
1= Slew rate disabled
0= Slew rate enabled
HAEN: Hardware Address Enable bit (MCP23S17 only) (Note 1)
1= Enables the MCP23S17 address pins.
0= Disables the MCP23S17 address pins.
ODR: Configures the INT pin as an open-drain output
1= Open-drain output (overrides the INTPOL bit.)
0= Active driver output (INTPOL bit sets the polarity.)
INTPOL: This bit sets the polarity of the INT output pin
1= Active-high
0= Active-low
Unimplemented: Read as ‘0’
Note 1: Address pins are always enabled on the MCP23017.
2005-2016 Microchip Technology Inc.
DS20001952C-page 21
MCP23017/MCP23S17
3.5.7
PULL-UP RESISTOR
CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the
port pins. If a bit is set and the corresponding pin is
configured as an input, the corresponding port pin is
internally pulled up with a 100 k resistor.
REGISTER 3-7:
GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)
R/W-0
PU7
R/W-0
PU6
R/W-0
PU5
R/W-0
PU4
R/W-0
PU3
R/W-0
PU2
R/W-0
PU1
R/W-0
PU0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
PU<7:0> Controls the weak pull-up resistors on each pin (when configured as an input)
1= Pull-up enabled
0= Pull-up disabled
3.5.8
INTERRUPT FLAG REGISTER
The INTF register reflects the interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A set bit indicates that the
associated pin caused the interrupt.
This register is read-only. Writes to this register will be
ignored.
REGISTER 3-8:
INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)
R-0
INT7
R-0
R-0
R-0
R-0
R-0
R-0
R-0
INT6
INT5
INT4
INT3
INT2
INT1
INT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
INT<7:0>: Reflects the interrupt condition on the port. It reflects the change only if interrupts are
enabled per GPINTEN<7:0>.
1= Pin caused interrupt.
0= Interrupt not pending
DS20001952C-page 22
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
3.5.9
INTERRUPT CAPTURED REGISTER
The INTCAP register captures the GPIO port value at
the time the interrupt occurred. The register is
read-only and is updated only when an interrupt
occurs. The register remains unchanged until the
interrupt is cleared via a read of INTCAP or GPIO.
REGISTER 3-9:
INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)
R-x
ICP7
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ICP6
ICP5
ICP4
ICP3
ICP2
ICP1
ICP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
ICP<7:0>: Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0>
1= Logic-high
0= Logic-low
3.5.10
PORT REGISTER
The GPIO register reflects the value on the port.
Reading from this register reads the port. Writing to this
register modifies the Output Latch (OLAT) register.
REGISTER 3-10: GPIO: GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09)
R/W-0
GP7
R/W-0
GP6
R/W-0
GP5
R/W-0
GP4
R/W-0
GP3
R/W-0
GP2
R/W-0
GP1
R/W-0
GP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
GP<7:0>: Reflects the logic level on the pins <7:0>
1= Logic-high
0= Logic-low
2005-2016 Microchip Technology Inc.
DS20001952C-page 23
MCP23017/MCP23S17
3.5.11
OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches. A read from this register results in a read of the
OLAT and not the port itself. A write to this register
modifies the output latches that modifies the pins
configured as outputs.
REGISTER 3-11: OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)
R/W-0
OL7
R/W-0
OL6
R/W-0
OL5
R/W-0
OL4
R/W-0
OL3
R/W-0
OL2
R/W-0
OL1
R/W-0
OL0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
OL<7:0>: Reflects the logic level on the output latch <7:0>
1= Logic-high
0= Logic-low
If IOCON.MIRROR = 1, the internal signals are OR’ed
together and routed to the INTn pads. In this case, the
interrupt will only be cleared if the associated GPIO or
INTCAP is read (see Table 3-6).
3.6
Interrupt Logic
If enabled, the MCP23X17 activates the INTn interrupt
output when one of the port pins changes state or when
a pin does not match the preconfigured default. Each
pin is individually configurable as follows:
TABLE 3-6:
INTERRUPT OPERATION
• Enable/disable interrupt via GPINTEN
(IOCON.MIRROR = 1)
• Can interrupt on either pin change or change from
default as configured in DEFVAL
Interrupt
Condition
Interrupt
Read PORTn (1)
Result
Both conditions are referred to as Interrupt-on-Change
(IOC).
PORTA
PORTB
PORTA
PORTB
PORTA
PORTB
Clear
GPIOA
GPIOB
Unchanged
Unchanged
Clear
The interrupt control module uses the following
registers/bits:
• IOCON.MIRROR – controls if the two interrupt
pins mirror each other
Unchanged
Unchanged
• GPINTEN – Interrupt enable register
GPIOA and
GPIOB
• INTCON – controls the source for the IOC
Both PORTA and
PORTB
Clear
• DEFVAL – contains the register default for IOC
operation
Note 1: PORTn = GPIOn or INTCAPn
3.6.1
INTA AND INTB
3.6.2 IOC FROM PIN CHANGE
There are two interrupt pins: INTA and INTB. By
default, INTA is associated with GPAn pins (PORTA)
and INTB is associated with GPBn pins (PORTB).
Each port has an independent signal which is cleared if
its associated GPIO or INTCAP register is read.
If enabled, the MCP23X17 generates an interrupt if a
mismatch condition exists between the current port
value and the previous port value. Only IOC-enabled
pins will be compared. Refer to Registers 3-3 and 3-5.
3.6.3
IOC FROM REGISTER DEFAULT
3.6.1.1
Mirroring the INT pins
If enabled, the MCP23X17 generates an interrupt if a
mismatch occurs between the DEFVAL register and
the port. Only IOC enabled pins are compared. Refer to
Registers 3-3, 3-4 and 3-5.
Additionally, the INTn pins can be configured to mirror
each other so that any interrupt will cause both pins to
go active. This is controlled via IOCON.MIRROR.
If IOCON.MIRROR = 0, the internal signals are routed
independently to the INTA and INTB pads.
DS20001952C-page 24
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
3.6.4
INTERRUPT OPERATION
FIGURE 3-8:
INTERRUPT-ON-PIN
CHANGE
The INTn interrupt output can be configured as
active-low, active-high or open-drain via the IOCON
register.
GPx
Only those pins that are configured as an input (IODIR
register) with Interrupt-On-Change (IOC) enabled
(IOINTEN register) can cause an interrupt. Pins
defined as an output have no effect on the interrupt
output pin.
INT
ACTIVE
ACTIVE
Port value
is captured
into INTCAP
Read GPIO Port value
Input change activity on a port input pin that is enabled
for IOC generates an internal device interrupt and the
device captures the value of the port and copies it into
INTCAP. The interrupt remains active until the INTCAP
or GPIO register is read. Writing to these registers does
not affect the interrupt. The interrupt condition is
cleared after the LSb of the data is clocked out during
a read command of GPIO or INTCAP.
or INTCAP
is captured
into INTCAP
FIGURE 3-9:
INTERRUPT-ON-CHANGE
FROM REGISTER
DEFAULT
The first interrupt event causes the port contents to be
copied into the INTCAP register. Subsequent interrupt
conditions on the port will not cause an interrupt to
occur as long as the interrupt is not cleared by a read
of INTCAP or GPIO.
DEFVAL REGISTER
GPx<7:0>
7
6
5
4
3
2
0
1
0
X
X
X
X
X
X
X
Note:
The value in INTCAP can be lost if GPIO
is read before INTCAP while another IOC
is pending. After reading GPIO, the
interrupt will clear and then set due to the
pending IOC, causing the INTCAP
register to update.
GP2
Pin
INT
Pin
ACTIVE
ACTIVE
3.6.5
INTERRUPT CONDITIONS
There are two possible configurations that cause
interrupts (configured via INTCON):
Port value
is captured
into INTCAP
Read GPIO
or INTCAP
1. Pins configured for interrupt-on-pin change
will cause an interrupt to occur if a pin changes
to the opposite state. The default state is reset
after an interrupt occurs and after clearing the
interrupt condition (i.e., after reading GPIO or
INTCAP). For example, an interrupt occurs by
an input changing from ‘1’ to ‘0’. The new initial
state for the pin is a logic ‘0’ after the interrupt is
cleared.
(INT clears only if interrupt
condition does not exist.)
2. Pins configured for interrupt-on-change from
register value will cause an interrupt to occur if
the corresponding input pin differs from the
register bit. The interrupt condition will remain as
long as the condition exists, regardless if the
INTCAP or GPIO is read.
See Figures 3-8 and 3-9 for more information on
interrupt operations.
2005-2016 Microchip Technology Inc.
DS20001952C-page 25
MCP23017/MCP23S17
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
28-Lead QFN
Example:
23017
e
3
E/ML
1628256
28-Lead SOIC
Example:
e
3
MCP23017-E/SO
1628256
28-Lead SPDIP
Example:
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
e
3
MCP23017-E/SP
1628256
YYWWNN
28-Lead SSOP
Example:
MCP23017
XXXXXXXXXXXX
XXXXXXXXXXXX
e
3
E/SS
1628256
YYWWNNN
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20001952C-page 26
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
2005-2016 Microchip Technology Inc.
DS20001952C-page 27
MCP23017/MCP23S17
DS20001952C-page 28
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
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2005-2016 Microchip Technology Inc.
DS20001952C-page 29
MCP23017/MCP23S17
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001952C-page 30
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2005-2016 Microchip Technology Inc.
DS20001952C-page 31
MCP23017/MCP23S17
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001952C-page 32
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
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1ꢐ ꢕꢌ ꢆꢈ!ꢌꢁꢈ!ꢃꢕꢃꢊꢈ$ꢃ2ꢑꢃ$ꢁꢃꢈꢁꢄꢃꢌꢈꢇꢍ"$ꢆꢃ ꢁꢍ$ꢃ(ꢍꢊ!ꢅꢃꢁꢂꢃꢉꢂꢁꢄꢂ"!ꢌꢁꢈ!ꢐꢃꢎꢁꢍ$ꢃ(ꢍꢊ!ꢅꢃꢁꢂꢃꢉꢂꢁꢄꢂ"!ꢌꢁꢈ!ꢃ!ꢅꢊꢍꢍꢃꢈꢁꢄꢃꢆ-ꢇꢆꢆ$ꢃꢐꢖꢑꢖ3ꢃꢉꢆꢂꢃ!ꢌ$ꢆꢐ
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5ꢏ0) 5ꢊ!ꢌꢇꢃꢕꢌ ꢆꢈ!ꢌꢁꢈꢐꢃꢙꢅꢆꢁꢂꢆꢄꢌꢇꢊꢍꢍꢒꢃꢆ-ꢊꢇꢄꢃ,ꢊꢍ"ꢆꢃ!ꢅꢁ%ꢈꢃ%ꢌꢄꢅꢁ"ꢄꢃꢄꢁꢍꢆꢂꢊꢈꢇꢆ!ꢐ
ꢎꢌꢇꢂꢁꢇꢅꢌꢉ ꢙꢆꢇꢅꢈꢁꢍꢁꢋꢒ ꢕꢂꢊ%ꢌꢈꢋ 0ꢖꢗꢞꢖꢜꢖ5
2005-2016 Microchip Technology Inc.
DS20001952C-page 33
MCP23017/MCP23S17
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ+$/ꢌ)ꢔꢇ+ꢛꢅꢉꢉꢇ0ꢏꢋꢉꢌ)ꢄꢇꢖ++ꢘꢇMꢇ'&.%ꢇꢛꢛꢇꢜꢓꢆ ꢇ!++0ꢈ"
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ꢎꢌꢇꢂꢁꢇꢅꢌꢉ ꢙꢆꢇꢅꢈꢁꢍꢁꢋꢒ ꢕꢂꢊ%ꢌꢈꢋ 0ꢖꢗꢞꢖꢜ15
DS20001952C-page 34
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2005-2016 Microchip Technology Inc.
DS20001952C-page 35
MCP23017/MCP23S17
NOTES:
DS20001952C-page 36
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
APPENDIX A: REVISION HISTORY
Revision C (July 2016)
The following is the list of modifications:
1. Added ESD data to Section 1.0, Electrical
Characteristics.
2. Updated Table 2-1.
3. Updated package outline drawings.
4. Minor typographical errors
Revision B (February 2007)
1. Changed Byte and Sequential Read in
Figure 1-1 from “R” to “W”.
2. Table 2-4, Param No. 51 and 53: Changed from
450 to 600 and 500 to 600, respecively.
3. Added disclaimers to package outline drawings.
4. Updated package outline drawings.
Revision A (June 2005)
• Original release of this document.
2005-2016 Microchip Technology Inc.
DS20001952C-page 37
MCP23017/MCP23S17
NOTES:
DS20001952C-page 38
2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
Examples:
–
PART NO.
Device
X
/XX
X
a)
MCP23017-E/ML:
Extended temperature,
28LD QFN package
Temperature
Range
Package Tape and Reel
Option
b)
MCP23017T-E/ML:
Extended temperature,
28LD QFN package,
Tape and Reel
Device:
MCP23017:
MCP23S17:
16-Bit I/O Expander with I2C Interface
16-Bit I/O Expander with SPI Interface
c)
d)
e)
MCP23017-E/SP:
MCP23017-E/SO:
MCP23017T-E/SO:
Extended temperature ,
28LD SPDIP package
Extended temperature,
28LD SOIC package
Temperature
Range:
E
=
-40C to +125C (Extended)
Extended temperature,
28LD SOIC package,
Tape and Reel
f)
MCP23017-E/SS:
MCP23017T-E/SS:
Extended temperature,
28LD SSOP package
Package:
ML
SO
SP
SS
=
=
=
=
Plastic Quad Flat, No Lead Package, 6x6 mm
Body, QFN, 28-lead
Plastic Small Outline, Wide, 7.50 mm Body, SOIC,
28-Lead
g)
Extended temperature,
28LD SSOP package,
Tape and Reel
Skinny Plastic Dual In-Line, 300 mil Body, SPDIP,
28-Lead
Plastic Shrink Small Outline, 5.30 mm Body,
SSOP, 28-Lead
a)
b)
MCP23S17-E/ML:
MCP23S17T-E/ML:
Extended temperature,
28LD QFN package
Extended temperature,
28LD QFN package,
Tape and Reel
Tape and Reel
Option:
T
= Tape and Reel (1)
Blank = Tube
c)
d)
e)
MCP23S17-E/SP:
MCP23S17-E/SO:
MCP23S17T-E/SO:
Extended temperature,
28LD SPDIP package
Extended temperature,
28LD SOIC package
Extended temperature,
28LD SOIC package,
Tape and Reel
f)
MCP23S17-E/SS:
MCP23S17T-E/SS:
Extended temperature,
28LD SSOP package
g)
Extended temperature,
28LD SSOP package
Tape and Reel
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
2005-2016 Microchip Technology Inc.
DS20001952C-page 39
MCP23017/MCP23S17
NOTES:
DS20001952C-page 40
2005-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2005-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0755-3
== ISO/TS 16949 ==
2005-2016 Microchip Technology Inc.
DS20001952C-page 41
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
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Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
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Tel: 86-756-3210040
Fax: 86-756-3210049
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Tel: 45-4450-2828
Fax: 45-4485-2829
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
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Tel: 91-80-3090-4444
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06/23/16
DS20001952C-page 42
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