MCP23S09-E/MG [MICROCHIP]
8 I/O, PIA-GENERAL PURPOSE, PQCC16, 3 X 3 MM, 0.90 MM HEIGHT, PLASTIC, QFN-16;
| 型号： | MCP23S09-E/MG |
| 厂家： | 
MICROCHIP |
| 描述： | 8 I/O, PIA-GENERAL PURPOSE, PQCC16, 3 X 3 MM, 0.90 MM HEIGHT, PLASTIC, QFN-16 外围集成电路 |
| 文件： | 总52页 (文件大小：949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP23009/MCP23S09
8-Bit I/O Expander with Open-Drain Outputs
• Configurable Interrupt Source:
Features:
- Interrupt-on-Change from configured defaults
or pin change
• 8-Bit Remote Bidirectional I/O Port:
- I/O Pins Default to Input
• Open-Drain Outputs:
- 5.5V Tolerant
• Polarity inversion register to configure the polarity
of the input port data
• External Reset Input
- 25 mA Sink Capable (per Pin)
- 200 mA Total
• Low Standby Current:
- 1 µA (-40°C TA +85°C)
- 6 µA (+85°C TA +125°C)
• Operating Voltage:
• High-Speed I2C™ Interface (MCP23009):
- 100 kHz
- 400 kHz
- 1.8V to 5.5V
- 3.4 MHz
• Available Packages:
• High-Speed SPI Interface (MCP23S09):
- 10 MHz
- 16-Lead QFN (3x3x0.9 mm)
- 18-Lead PDIP (300 mil)
- 18-Lead SOIC (7.50 mm)
- 20-Lead SSOP (5.30 mm)
• Single Hardware Address Pin (MCP23009):
- Voltage input to allow up to eight devices on
the bus
• Configurable Interrupt Output Pins:
- Configurable as active-high, active-low or
open-drain
Block Diagram
MCP23S09
CS
SCK
SI
SO
SPI
MCP23009
Serializer/
SCL
SDA
I2C™
GP0
GP1
GP2
GP3
GP4
GP5
GP6
GP7
Deserializer
RESET
INT
8
GPIO
Control
8
Multi-Bit
Decode
ADDR
Configuration/
Control
Registers
2009-2014 Microchip Technology Inc.
DS20002121C-page 1
MCP23009/MCP23S09
Package Types
MCP23009
MCP23009
MCP23009
PDIP, SOIC
3 x 3 QFN*
SSOP
VDD
NC
1
VSS
NC
VSS
NC
VDD
NC
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
2
16 15 14 13
SCL
3
NC
NC
SCL
V
GP3
GP2
GP1
GP0
1
12
11
10
9
SS
SDA
ADDR
RESET
INT
4
GP7
GP6
GP5
GP4
GP3
GP2
NC
SDA
GP7
GP6
GP5
GP4
GP3
GP2
NC
2
3
4
EP
17
5
ADDR
RESET
INT
V
DD
6
SCL
7
GP0
8
5
6
7
8
GP0
GP1
9
GP1
NC
10
MCP23S09
MCP23S09
3 x 3 QFN*
PDIP/SOIC
VDD
NC
CS
1
2
3
4
5
6
7
8
9
18 VSS
17 NC
16 15 14 13
16 GP7
15 GP6
14 GP5
13 GP4
12 GP3
11 GP2
10 GP1
V
GP3
GP2
GP1
GP0
1
12
11
10
9
SS
SCK
SI
SCK
2
3
4
EP
17
V
DD
SO
CS
RESET
INT
5
6
7
8
GP0
* Includes Exposed Thermal Pad (EP); see Tables 1-1 and 1-2.
DS20002121C-page 2
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
1.0
DEVICE OVERVIEW
The MCP23X09 device provides 8-bit, general purpose
parallel I/O expansion for I2C bus or SPI applications.
The two devices differ only in the serial interface.
• MCP23009 – I2C interface
• MCP23S09 – SPI interface
The MCP23X09 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits. The data
for each input or output is kept in the corresponding
input or output register. The polarity of the input port
register can be inverted with the polarity inversion
register. All registers can be read by the system master.
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1. When any input state differs from its
corresponding input port register state. This is
used to indicate to the system master that an
input state has changed.
2. When an input state differs from
a
pre-configured
register).
register
value
(DEFVAL
The Interrupt Capture register captures port values at
the time of the Interrupt, thereby saving the condition
that caused the Interrupt.
The Power-On Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pin is used to determine the
device address.
2009-2014 Microchip Technology Inc.
DS20002121C-page 3
MCP23009/MCP23S09
1.1
Pin Descriptions
TABLE 1-1:
I2C™ PINOUT DESCRIPTION (MCP23009)
Pin Number
Pin
Pin
Name
Standard Function
16-lead 18-lead
QFN PDIP/SOIC
20-lead
SSOP
Type
VDD
NC
3
2
1
1
P
Power
2, 16-17
2, 10-11,
18-19
—
Not connected
SCL
SDA
4
5
6
3
4
5
3
4
5
I
Serial clock input
I/O Serial data I/O
ADDR
I
Hardware address pin allows up to eight slave devices on the
bus
RESET
INT
7
8
6
7
6
7
I
Hardware reset
O
Interrupt output for port. Can be configured as active-high,
active-low or open-drain.
GP0
GP1
GP2
GP3
GP4
GP5
GP6
GP7
9
8
8
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
10
11
12
13
14
15
16
9
9
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
10
11
12
13
14
15
12
13
14
15
16
17
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
VSS
EP
1
18
—
20
—
P
Ground
17
—
Exposed Thermal Pad (EP). Can be left floating or connected
to VSS.
DS20002121C-page 4
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
TABLE 1-2:
Pin
SPI PINOUT DESCRIPTION (MCP23S09)
Pin Number
Pin
Standard Function
16-lead 18-lead
QFN PDIP/SOIC
Name
Type
VDD
NC
3
1
P
Power (high-current capable)
Not connected
—
2, 17
—
CS
SCK
SI
4
2
5
6
3
4
5
6
I
I
Chip select
Serial clock input
Serial data input
Serial data out
I
SO
O
RESET
INT
7
8
7
8
I
Hardware reset (must be externally biased)
O
Interrupt output for port. Can be configured as active-high, active-low or
open-drain.
GP0
GP1
GP2
GP3
GP4
GP5
GP6
GP7
9
9
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
10
11
12
13
14
15
16
10
11
12
13
14
15
16
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
VSS
EP
1
18
—
P
Ground (high-current capable)
17
—
Exposed Thermal Pad (EP). Can be left floating or connected to VSS.
2009-2014 Microchip Technology Inc.
DS20002121C-page 5
MCP23009/MCP23S09
• Sequential mode enables automatic address
pointer incrementing. When operating in
Sequential mode, the MCP23X09 increments its
address counter after each byte during the data
transfer. The address pointer automatically rolls
over to address 00h after accessing the last
register.
1.2
Power-On Reset (POR)
The on-chip POR circuit holds the device in reset until
VDD has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in the
electrical specification section.
When the device exits the POR condition (releases
reset), the device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
These two modes are not to be confused with single
writes/reads and continuous writes/reads, which are
serial protocol sequences. For example, the device
may be configured for Byte mode and the master may
perform
a continuous read. In this case, the
1.3
Serial Interface
MCP23X09 would not increment the address pointer
and would repeatedly drive data from the same
location.
This block handles the functionality of the I2C
(MCP23009) or SPI (MCP23S09) interface protocol.
The MCP23X09 contains eleven (11) individual
registers which can be addressed through the Serial
Interface block (Table 1-3).
1.3.2
I2C INTERFACE
1.3.2.1
I2C Write Operation
The I2C write operation includes the control byte and
the register address sequence, as shown in the bottom
of Figure 1-1. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23009. The operation is ended with a Stop (P)
or Restart (SR) condition being generated by the
master.
TABLE 1-3:
Address
REGISTER ADDRESSES
Access to
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
IODIR
IPOL
GPINTEN
DEFVAL
INTCON
IOCON
GPPU
Data is written to the MCP23009 after every byte
transfer. If a Stop or Restart condition is generated
during a data transfer, the data will not be written to the
MCP23009.
INTF
Both Byte mode and Sequential mode are supported
by the MCP23009. If Sequential mode is enabled
(default), the MCP23009 increments its address
counter after each ACK during the data transfer.
INTCAP (read-only)
GPIO
OLAT
1.3.2.2
I2C Read Operation
1.3.1
BYTE MODE AND SEQUENTIAL
MODE
I2C read operations include the control byte sequence,
as shown in the bottom of Figure 1-1. This sequence is
followed by another control byte (including the Start
condition and ACK) with the R/W bit equal to a logic
one (R/W = 1). The MCP23009 then transmits the data
contained in the addressed register. The sequence is
ended with the master generating a Stop or Restart
condition.
The MCP23X09 has the ability to operate in Byte mode
or Sequential mode (IOCON.SEQOP). Byte mode and
Sequential mode are not to be confused with I2C byte
operations and sequential operations. The modes
explained here relate to the device’s internal address
pointer and whether or not it is incremented after each
byte is clocked on the serial interface.
1.3.2.3
I2C Sequential Write/Read
• Byte mode disables automatic address pointer
incrementing. When operating in Byte mode, the
MCP23X09 does not increment its internal
address counter after each byte during the data
transfer. This gives the ability to continually
access the same address by providing extra
clocks (without additional control bytes). This is
useful for polling the GPIO register for data
changes or for continually writing to the output
latches.
For sequential operations (Write or Read), instead of
transmitting a Stop or Restart condition after the data
transfer, the master clocks the next byte pointed to by
the address pointer (see Section 1.3.1 “Byte Mode
and Sequential Mode” for details regarding sequential
operation control).
The sequence ends with the master sending a Stop or
Restart condition.
The MCP23009 address pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 1-1.
DS20002121C-page 6
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
1.3.3
SPI INTERFACE
1.3.3.2
SPI Read Operation
The MCP23S09 operates in Mode 0,0 and Mode 1,1.
The difference between the two modes is the idle state
of the clock.
The SPI read operation is started by lowering CS. The
SPI read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
• Mode 0,0: The idle state of the clock is low. Input
data is latched on the rising edge of the clock; out-
put data is driven on the falling edge of the clock.
1.3.3.3
SPI Sequential Write/Read
• Mode 1,1: The idle state of the clock is high. Input
data is latched on the rising edge of the clock; out-
put data is driven on the falling edge of the clock.
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the address pointer (see Section 1.3.1
“Byte Mode and Sequential Mode” for details
regarding sequential operation control).
1.3.3.1
SPI Write Operation
The SPI write operation is started by lowering CS. The
write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
The sequence ends by the raising of CS.
The MCP23S09 address pointer will roll over to
address zero after reaching the last register address.
2009-2014 Microchip Technology Inc.
DS20002121C-page 7
MCP23009/MCP23S09
FIGURE 1-1:
MCP23009 I2C™ DEVICE PROTOCOL
DIN
DIN
S
OP
W
ADDR
....
P
DOUT
DIN
DOUT
SR
OP
OP
R
P
P
....
....
ADDR
SR
P
W
DOUT
DOUT
S
OP
R
P
....
DOUT
DIN
DOUT
DIN
SR
OP
R
P
P
....
....
SR
OP
W
ADDR
P
Byte and Sequential Write
DIN
DIN
S
OP
OP
W
W
ADDR
ADDR
P
Byte
Sequential
DIN
....
S
P
Byte and Sequential Read
DOUT
DOUT
Byte
S
S
OP
OP
W
W
ADDR
ADDR
SR
OP
R
R
P
DOUT
Sequential
....
P
SR OP
Legend:
- Start
S
SR
P
OP
ADDR
- Device opcode
- Device address
- Restart
- Stop
- Write
- Read
DOUT
DIN
- Data out from MCP23009
- Data in to MCP23009
W
R
DS20002121C-page 8
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
1.4.1
CALCULATING VOLTAGE ON ADDR
1.4
Multi-Bit Address Decoder
When calculating the required voltage on the ADDR pin
(V2), the set point should be the mid point of the LSb of
the ADC.
The ADDR pin is used to set the slave address of the
MCP23009 (I2C only) to allow up to eight devices on
the bus using only a single pin. Typically, this would
require three pins.
The examples in Figures 1-2 and 1-3 show how to
determine the mid-point voltage (V2) and the range of
voltages based on a voltage divider circuit. The
maximum tolerance is 20%, however, it is
recommended to use 5% tolerance worst-case (10%
total tolerance).
The multi-bit Address Decoder employs a basic FLASH
ADC architecture (Figure 1-4). The seven comparators
generate eight unique values based on the analog
input. This value is converted to a 3-bit code which
corresponds to the address bits (A2, A1, A0) in the
serial OPCODE.
Sequence of operation (see Figure 1-5 for
timings):
1. Upon power-up (after VDD stabilizes), the
module becomes active after time tADEN. Note
that the analog value on the ADDR pin must be
stable before this point to ensure accurate
address assignment.
2. The 3-bit address is latched after tADDRLAT.
3. The module powers down after the first rising
edge of the serial clock is detected (tADDIS).
Once the address bits are latched, the device will keep
the slave address until a POR or Reset condition
occurs.
FIGURE 1-2:
VOLTAGE DIVIDER EXAMPLE
VDD
VDD
ADDR
MCP23009 Only
A0
A1
A2
R1
V2
R2
VSS
VSS
2009-2014 Microchip Technology Inc.
DS20002121C-page 9
MCP23009/MCP23S09
FIGURE 1-3:
VOLTAGE AND CODE EXAMPLE
Assume:
n = A2, A1, A0 in opcode
ratio = R2/(R1+R2)
V2 = voltage on ADDR pin
V2(min) = V2 – (VDD/8) x %tolerance
V2(max) = V2 + (VDD/8) x %tolerance
VDD = 1.8
R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2)
10% Tolerance (total)
n
0
1
2
3
4
5
6
7
V2
V2(min)
0.00
0.32
0.54
0.77
0.99
1.22
1.44
1.67
V2(max)
0.14
0.0625
0.1875
0.3125
0.4375
0.5625
0.6875
0.8125
0.9375
1
15
13
11
9
0.113
0.338
0.563
0.788
1.013
1.238
1.463
1.688
3
0.36
5
0.59
7
0.81
9
7
1.04
11
13
15
5
1.26
3
1.49
1
1.80
VDD = 2.7
R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2)
10% Tolerance (total)
n
0
1
2
3
4
5
6
7
V2
V2(min)
0.00
0.48
0.82
1.16
1.50
1.83
2.17
2.51
V2(max)
0.19
1
3
15
13
11
9
0.0625
0.1875
0.3125
0.4375
0.5625
0.6875
0.8125
0.9375
0.169
0.506
0.844
1.181
1.519
1.856
2.194
2.531
0.53
5
0.87
7
1.20
9
7
1.54
11
13
15
5
1.88
3
1
2.22
2.70
VDD = 3.3
R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2)
10% Tolerance (total)
n
0
1
2
3
4
5
6
7
V2
V2(min)
0.00
0.60
1.01
1.42
1.83
2.25
2.66
3.07
V2(max)
0.23
1
15
13
11
9
0.0625
0.1875
0.3125
0.4375
0.5625
0.6875
0.8125
0.9375
0.206
0.619
1.031
1.444
1.856
2.269
2.681
3.094
3
5
0.64
1.05
7
1.47
9
7
1.88
11
13
15
5
2.29
3
1
2.70
3.30
VDD = 5.5
R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2)
10% Tolerance (total)
n
0
1
2
3
4
5
6
7
V2
V2(min)
0.00
1.01
1.70
2.38
3.07
3.76
4.45
5.13
V2(max)
0.37
1
15
13
11
9
0.0625
0.1875
0.3125
0.4375
0.5625
0.6875
0.8125
0.9375
0.344
1.031
1.719
2.406
3.094
3.781
4.469
5.156
3
5
1.05
1.74
7
2.43
9
7
3.12
11
13
15
5
3.80
3
1
4.49
5.50
DS20002121C-page 10
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
FIGURE 1-4:
FLASH ADC BLOCK DIAGRAM
VDD
ADDR
addr_out 6
addr<6:0>
adc_en
i2c_addr<2:0>
+
-
d
q
adc_en
addr_out 5
adc_en
'0'
en
+
-
adc_en
addr_out 4
reset
set
d
+
-
q
adc_en
addr_out 3
i2c_clk
+
-
adc_en
addr_out 2
+
-
adc_en
addr_out 1
+
-
adc_en
addr_out 0
+
-
adc_en
adc_en
VSS
2009-2014 Microchip Technology Inc.
DS20002121C-page 11
MCP23009/MCP23S09
FIGURE 1-5:
HARDWARE ADDRESS DECODE TIMING
tADEN
VDD
tADDRLAT
adc_en
i2c_addr[2:0]
i2c_clk
tADDIS
1.4.2
ADDRESSING I2C DEVICES
(MCP23009)
FIGURE 1-6:
I2C™ CONTROL BYTE
FORMAT
The MCP23009 is a slave I2C device that supports 7-bit
slave addressing, with the read/write bit filling out the
control byte. The slave address contains four fixed bits
and three user-defined hardware address bits
(configured via the ADDR pin). Figure 1-6 shows the
control byte format.
Control Byte
A2 A1 A0 R/W ACK
S
0
1
0
0
Slave Address
R/W bit
Start
bit
ACK bit
1.4.3
ADDRESSING SPI DEVICES
(MCP23S09)
R/W = 0= write
R/W = 1= read
The MCP23S09 is a slave SPI device. The slave
address contains seven fixed bits (no address bits),
with the read/write bit filling out the control byte.
Figure 1-7 shows the control byte format.
FIGURE 1-7:
SPI CONTROL BYTE
FORMAT
CS
Control Byte
0
1
0
0
0
0
0
R/W
Slave Address
R/W bit
R/W = 0= write
R/W = 1= read
DS20002121C-page 12
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
FIGURE 1-8:
I2C™ ADDRESSING REGISTERS
S
0
1
0
0
A2 A1 A0 ACK A7
0
A6
A5
A4
A3
A2
A1
A0 ACK
R/W = 0
Device Opcode
Register Address
The ACKs are provided by the MCP23009.
FIGURE 1-9:
SPI ADDRESSING REGISTERS
CS
0
1
0
0
0
0
0
R/W A7
A6
A5
A4
A3
A2
A1
A0
Device Opcode
Register Address
2009-2014 Microchip Technology Inc.
DS20002121C-page 13
MCP23009/MCP23S09
1.5
GPIO Port
The GPIO module is a general purpose 8-bit wide
bidirectional port.
The outputs are open-drain.
The GPIO module contains the data ports (GPIOn),
internal pull-up resistors and the output latches
(OLATn).
The pull-up resistors are individually configured and
can be enabled when the pin is configured as an input
or output.
Reading the GPIOn register reads the value on the
port. Reading the OLATn register only reads the
latches, not the actual value on the port.
Writing to the GPIOn register actually causes a write to
the latches (OLATn). Writing to the OLATn register
forces the associated output drivers to drive to the level
in OLATn. Pins configured as inputs turn off the
associated output driver and put it in high impedance.
DS20002121C-page 14
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
1.6
Configuration and Control
Registers
There are eleven (11) registers associated with the
MCP23X09, as shown in Table 1-4.
TABLE 1-4:
CONFIGURATION AND CONTROL REGISTERS
Register
Name
Address
(hex)
POR/RST
Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IODIR
IPOL
00
01
02
03
04
05
06
07
08
09
0A
IO7
IP7
IO6
IP6
IO5
IP5
IO4
IP4
IO3
IP3
IO2
IP2
IO1
IP1
IO0
IP0
1111 1111
0000 0000
GPINTEN
DEFVAL
INTCON
IOCON
GPPU
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEF7
IOC7
—
DEF6
IOC6
—
DEF5
IOC5
SEQOP
PU5
DEF4
IOC4
—
DEF3
IOC3
—
DEF2
IOC2
ODR
PU2
DEF1
IOC1
DEF0 0000 0000
IOC0 0000 0000
INTPOL INTCC 0000 0000
PU7
INT7
ICP7
GP7
OL7
PU6
INT6
ICP6
GP6
OL6
PU4
INT4
ICP4
GP4
OL4
PU3
INT3
ICP3
GP3
OL3
PU1
INT1
ICP1
GP1
OL1
PU0
0000 0000
INTF
INT5
INT2
ICP2
GP2
OL2
INTO 0000 0000
ICP0 0000 0000
INTCAP
GPIO
ICP5
GP5
GP0
OL0
0000 0000
0000 0000
OLAT
OL5
2009-2014 Microchip Technology Inc.
DS20002121C-page 15
MCP23009/MCP23S09
1.6.1
I/O DIRECTION REGISTER
This register controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an
input. When a bit is clear, the corresponding pin
becomes an output.
REGISTER 1-1:
IODIR – I/O DIRECTION REGISTER
R/W-1
IO7
R/W-1
IO6
R/W-1
IO5
R/W-1
IO4
R/W-1
IO3
R/W-1
IO2
R/W-1
IO1
R/W-1
IO0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
IO<7:0>: Controls the direction of data I/O <7:0>
1= Pin is configured as an input
0= Pin is configured as an output
DS20002121C-page 16
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
1.6.2
INPUT POLARITY REGISTER
This register allows the user to configure the polarity on
the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will
reflect the inverted value on the pin.
REGISTER 1-2:
IPOL – INPUT POLARITY PORT REGISTER
R/W-0
IP7
R/W-0
IP6
R/W-0
IP5
R/W-0
IP4
R/W-0
IP3
R/W-0
IP2
R/W-0
IP1
R/W-0
IP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
IP<7:0>: Controls the polarity inversion of the input pins <7:0>
1= GPIO register bit will reflect the opposite logic state of the input pin
0= GPIO register bit will reflect the same logic state of the input pin
2009-2014 Microchip Technology Inc.
DS20002121C-page 17
MCP23009/MCP23S09
1.6.3
INTERRUPT-ON-CHANGE
CONTROL REGISTER
The
GPINTEN
register
controls
the
Interrupt-on-Change feature for each pin.
If a bit is set, the corresponding pin is enabled for
Interrupt-on-Change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for Interrupt-on-Change.
REGISTER 1-3:
GPINTEN – INTERRUPT-ON-CHANGE PINS
R/W-0
GPINT7
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
GPINT<7:0>: General-purpose I/O interrupt-on-change pins <7:0>
1= Enable GPIO input pin for Interrupt-on-Change event
0= Disable GPIO input pin for Interrupt-on-Change event
Refer to the INTCON and DEFVAL registers.
DS20002121C-page 18
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
1.6.4
DEFAULT COMPARE REGISTER
FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
Interrupt to occur.
REGISTER 1-4:
DEFVAL – DEFAULT VALUE REGISTER
R/W-0
DEF7
R/W-0
DEF6
R/W-0
DEF5
R/W-0
DEF4
R/W-0
DEF3
R/W-0
DEF2
R/W-0
DEF1
R/W-0
DEF0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
DEF<7:0>: Sets the compare value for pins configured for Interrupt-on-Change from defaults <7:0>.
Refer to the INTCON register.
If the associated pin level is the opposite from the register bit, an Interrupt occurs.
Refer to the INTCON and GPINTEN registers.
2009-2014 Microchip Technology Inc.
DS20002121C-page 19
MCP23009/MCP23S09
1.6.5
INTERRUPT CONTROL REGISTER
The INTCON register controls how the associated pin
value is compared for the Interrupt-on-Change feature.
If a bit is set, the corresponding I/O pin is compared
against the associated bit in the DEFVAL register. If a
bit value is clear, the corresponding I/O pin is compared
against the previous value.
REGISTER 1-5:
INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER
R/W-0
IOC7
R/W-0
IOC6
R/W-0
IOC5
R/W-0
IOC4
R/W-0
IOC3
R/W-0
IOC2
R/W-0
IOC1
R/W-0
IOC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
IOC<7:0>: Controls how the associated pin value is compared for Interrupt-on-Change <7:0>.
1= Pin value is compared against the associated bit in the DEFVAL register
0= Pin value is compared against the previous pin value
Refer to the DEFVAL and GPINTEN registers.
DS20002121C-page 20
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
The Interrupt Polarity (INTPOL) bit sets the polarity of
the INT pin. This bit is functional only when the ODR bit
is cleared, configuring the INT pin as active push-pull.
1.6.6
CONFIGURATION REGISTER
The Sequential Operation (SEQOP) bit controls the
incrementing function of the address pointer. If the
address pointer is disabled, the address pointer does
not automatically increment after each byte is clocked
during a serial transfer. This feature is useful when it is
desired to continuously poll (read) or modify (write) a
register.
The Interrupt Clearing Control (INTCC) bit configures
how Interrupts are cleared. When set (INTCC = 1), the
Interrupt is cleared when the INTCAP register is read.
When cleared (INTCC = 0), the Interrupt is cleared
when the GPIO register is read.
The Interrupt can only be cleared when the Interrupt
condition is inactive. Refer to Section 1.7.4 “Clearing
Interrupts” for details.
The Open-Drain (ODR) control bit enables/disables the
INT pin for open-drain configuration.
REGISTER 1-6:
IOCON – I/O EXPANDER CONFIGURATION REGISTER
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
ODR
R/W-0
R/W-0
INTCC
SEQOP
INTPOL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
SEQOP: Sequential Operation mode bit.
1= Sequential operation disabled, address pointer does not increment
0= Sequential operation enabled, address pointer increments
bit 4
bit 3
bit 2
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
ODR: Configures the INT pin as an open-drain output.
1= Open-drain output (overrides the INTPOL bit)
0= Active driver output (INTPOL bit sets the polarity)
bit 1
bit 0
INTPOL: Sets the polarity of the INT output pin.
1= Active-High
0= Active-Low
INTCC: Interrupt Clearing Control
1= Reading INTCAP register clears the Interrupt
0= Reading GPIO register clears the Interrupt
2009-2014 Microchip Technology Inc.
DS20002121C-page 21
MCP23009/MCP23S09
1.6.7
PULL-UP RESISTOR
CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the
port pins. If a bit is set, the corresponding port pin is
internally pulled up with an internal resistor.
REGISTER 1-7:
GPPU – GPIO PULL-UP RESISTOR REGISTER
R/W-0
PU7
R/W-0
PU6
R/W-0
PU5
R/W-0
PU4
R/W-0
PU3
R/W-0
PU2
R/W-0
PU1
R/W-0
PU0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
PU<7:0>: Controls the internal pull-up resistors on each pin (when configured as an input or output)
<7:0>.
1= Pull-Up enabled
0= Pull-Up disabled
FIGURE 1-10:
TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS
GPIO Pin Internal Pull-Up Current vs. VDD
400
350
300
250
200
150
100
50
T = -40°C
T = +25°C
T = +125°C
T = +85°C
0
1.5
2
2.5
3
3.5
VDD (V)
4
4.5
5
5.5
DS20002121C-page 22
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
1.6.8
INTERRUPT FLAG REGISTER
The INTF register reflects the Interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A set bit indicates that the
associated pin caused the Interrupt.
This register is read-only. Writes to this register will be
ignored.
REGISTER 1-8:
INTF – INTERRUPT FLAG REGISTER
R-0
INT7
R-0
R-0
R-0
R-0
R-0
R-0
R-0
INT6
INT5
INT4
INT3
INT2
INT1
INT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
INT<7:0>: Reflects the interrupt condition on the port. Will reflect the change only if interrupts are
enabled (GPINTEN) <7:0>.
1= Pin caused Interrupt
0= Interrupt not pending
2009-2014 Microchip Technology Inc.
DS20002121C-page 23
MCP23009/MCP23S09
1.6.9
INTERRUPT CAPTURE REGISTER
The INTCAP register captures the GPIO port value at
the time the Interrupt occurred. The register is
read-only’ and is updated only when an Interrupt
occurs. The register will remain unchanged until the
Interrupt is cleared via a read of INTCAP or GPIO.
REGISTER 1-9:
INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER
R-x
ICP7
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ICP6
ICP5
ICP4
ICP3
ICP2
ICP1
ICP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
ICP<7:0>: Reflects the logic level on the port pins at the time of Interrupt due to pin change <7:0>.
1= Logic-High
0= Logic-Low
DS20002121C-page 24
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
1.6.10
PORT REGISTER
The GPIO register reflects the value on the port.
Reading from this register reads the port. Writing to this
register modifies the Output Latch (OLAT) register.
REGISTER 1-10: GPIO – GENERAL PURPOSE I/O PORT REGISTER
R/W-0
GP7
R/W-0
GP6
R/W-0
GP5
R/W-0
GP4
R/W-0
GP3
R/W-0
GP2
R/W-0
GP1
R/W-0
GP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
GP<7:0>: Reflects the logic level on the pins <7:0>.
1= Logic-High
0= Logic-Low
2009-2014 Microchip Technology Inc.
DS20002121C-page 25
MCP23009/MCP23S09
1.6.11
OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches. A read from this register results in a read of the
OLAT and not the port itself. A write to this register
modifies the output latches that modifies the pins
configured as outputs.
REGISTER 1-11: OLAT – OUTPUT LATCH REGISTER 0
R/W-0
OL7
R/W-0
OL6
R/W-0
OL5
R/W-0
OL4
R/W-0
OL3
R/W-0
OL2
R/W-0
OL1
R/W-0
OL0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
OL<7:0>: Reflects the logic level on the output latch <7:0>.
1= Logic-High
0= Logic-Low
DS20002121C-page 26
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
1.7.4
CLEARING INTERRUPTS
1.7
Interrupt Logic
The Interrupt will remain active until the INTCAP or
GPIO register is read (depending on IOCON.INTCC).
Writing to these registers will not affect the Interrupt.
The Interrupt condition will be cleared after the LSb of
the data is clocked out during a read operation of GPIO
or INTCAP (depending on IOCON.INTCC).
If enabled, the MCP23X09 activates the INT interrupt
output when one of the port pins changes state or when
a pin does not match the pre-configured default. Each
pin is individually configurable as follows:
• Enable/disable interrupt via GPINTEN
• Can Interrupt on either pin change or change from
default as configured in DEFVAL
Note:
Assuming
IOCON.INTCC = 0
(INT
cleared on GPIO read), the value in
INTCAP can be lost if GPIO is read before
INTCAP while another IOC is pending.
After reading GPIO, the Interrupt will clear
and then set due to the pending IOC,
causing the INTCAP register to update.
Both conditions are referred to as Interrupt-on-Change
(IOC).
The Interrupt Control Module uses the following
registers/bits:
• GPINTEN – Interrupt enable register
• INTCON – Controls the source for the IOC
• DEFVAL – Contains the register default for IOC
operation
• IOCON (ODR and INTPOL) – Configures the INT
pin as push-pull, open-drain and active level (high
or low).
1.7.1
IOC FROM PIN CHANGE
If enabled, the MCP23X09 will generate an Interrupt if
a mismatch condition exists between the current port
value and the previous port value. Only IOC-enabled
pins will be compared. See the GPINTEN and INTCON
registers.
1.7.2
IOC FROM REGISTER DEFAULT
If enabled, the MCP23X09 will generate an Interrupt if
a mismatch occurs between the DEFVAL register and
the port. Only IOC-enabled pins will be compared. See
the GPINTEN, INTCON and DEFVAL registers.
1.7.3
INTERRUPT OPERATION
The INT interrupt output can be configured as
active-low, active-high or open-drain via the IOCON
register.
Only those pins that are configured as an input (IODIR
register) with Interrupt-on-Change (IOC) enabled
(GPINTEN register) can cause an Interrupt. Pins
configured as an output have no effect on the interrupt
output pin.
Input change activity on a port input pin that is enabled
for IOC will generate an internal device Interrupt and
the device will capture the value of the port and copy it
into INTCAP.
The first Interrupt event will cause the port contents to
be copied into the INTCAP register. Subsequent
Interrupt conditions on the port will not cause an
Interrupt to occur as long as the Interrupt is not cleared
by a read of INTCAP or GPIO.
2009-2014 Microchip Technology Inc.
DS20002121C-page 27
MCP23009/MCP23S09
1.7.5
INTERRUPT CONDITIONS
FIGURE 1-11:
INTERRUPT-ON-PIN-CHANGE
There are two possible configurations to cause
Interrupts (configured via INTCON):
GPx
1. Pins configured for Interrupt-on-Pin-Change
will cause an Interrupt to occur if a pin changes
to the opposite state. The default state is reset
after an Interrupt occurs. For example, an
Interrupt occurs by an input changing from 1to
0. The new initial state for the pin is a logic 0.
INT
ACTIVE
ACTIVE
Port value
is captured
into INTCAP
Read GPIO Port value
or INTCAP
is captured
into INTCAP
2. Pins configured for Interrupt-on-Change from
register value will cause an Interrupt to occur if
the corresponding input pin differs from the
register bit. The Interrupt condition will remain
as long as the condition exists, regardless of
whether the INTAP or GPIO is read.
FIGURE 1-12:
INTERRUPT-ON-CHANGE
FROM REGISTER
DEFAULT
See Figures 1-11 and 1-12 for more information on the
interrupt operations.
DEFVAL
GP:
7
6
5
4
3
2
1
1
0
X
X
X
X
X
X
X
GP2
INT
ACTIVE
ACTIVE
Port value
is captured
into INTCAP
Read GPIO
or INTCAP
(INT clears only if Interrupt
condition does not exist.)
DS20002121C-page 28
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
2.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.0V
Voltage on RESET with respect to VSS ..................................................................................................... -0.3V to +14V
Voltage on all other pins with respect to VSS (except VDD and GPIOA/B) ..................................... -0.6V to (VDD + 0.6V)
Voltage on GPIO Pins .................................................................................................................................. -0.6V to 5.5V
Total power dissipation (Note 1) ..........................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................200 mA
Maximum current into VDD pin ..............................................................................................................................125 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any output pin ....................................................................................................25 mA
Maximum output current sunk by any output pin (VDD = 1.8V)...............................................................................10 mA
ESD protection on all pins (HBM:MM) ..............................................................................................................4 kV:400V
†
Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at those or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL).
2009-2014 Microchip Technology Inc.
DS20002121C-page 29
MCP23009/MCP23S09
2.1
DC Characteristics
Electrical Characteristics: Unless otherwise indicated, all limits are specified
for 1.8V VDD 5.5V at -40C TA +125C.
DC Characteristics
Param.
No.
Characteristic
Sym.
Min.
Typ.(2) Max.
Units
Conditions
D001 Supply Voltage
VDD
1.8
—
—
5.5
—
V
V
D002 VDD Start Voltage
VPOR
VSS
to Ensure Power-On Reset
D003 VDD Rise Rate to Ensure
Power-On Reset
SVDD
0.05
—
—
V/ms Design guidance only.
Not tested.
D004 Supply Current
IDD
—
—
—
—
—
—
1
1
6
mA SCL/SCK = 1 MHz
D005 Standby (Idle) current
IDDS
µA
µA
–40°C TA +85°C
+85°C TA +125°C
Input Low-Voltage
D031 CS, GPIO, SCL/SCK,
SDA, SI, RESET
VIL
VSS
—
0.2 VDD
V
Input High-Voltage
D041 CS, SCL/SCK, SDA, SI,
RESET
VIH
VIH
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
GPIO
Input Leakage Current
D060 I/O port pins
Output Leakage Current
D065 I/O port pins
IIL
—
—
±1
µA
VSS VPIN VDD
VSS VPIN VDD
ILO
IPU
—
—
—
±1
—
µA
µA
D070 GPIO internal pull-up
current
220
VDD = 5V, GP Pins = VSS
(Note 1)
Output Low-Voltage
D080 GPIO
VOL
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V
(open-drain)
INT
SO, SDA
—
—
—
—
—
—
0.6
0.6
0.8
IOL = 1.6 mA, VDD = 4.5V
IOL = 3.0 mA, VDD = 1.8V
IOL = 3.0 mA, VDD = 4.5V
SDA
Output High-Voltage
D090 INT, SO
VOH
VDD – 0.7
VDD – 0.7
—
—
—
—
V
IOH = -3.0 mA, VDD = 4.5V
IOH = -400 µA, VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101 GPIO, SO, INT
D102 SDA
CIO
CB
—
—
—
—
50
400(1)
pF
These are load conditions for
the timing specifications.
Refer to Figure 2-1.
SDA test condition is 135 pF.
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.
DS20002121C-page 30
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
2.2
AC CHARACTERISTICS
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
FIGURE 2-1:
VDD
Pin
1 k
SCL and
SDA pin
50 pF
MCP23009
135 pF
FIGURE 2-2:
RESET AND DEVICE RESET TIMER TIMING
VDD
RESET
30
32
31
Internal
RESET
34
Output pin
TABLE 2-1:
RESET AND DEVICE RESET TIMER REQUIREMENTS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
1.8V VDD 5.5V at -40C TA +125C.
AC Characteristics
Param.
Sym.
No.
Characteristic
Min. Typ.(2) Max. Units
Conditions
30
32
31
34
TRSTL
THLD
TPOR
TIOZ
RESET Pulse Width (low)
Device active after reset high
POR at device power-up
1
—
0
—
—
—
1
µs
µs
µs
µs
VDD = 5.0V
—
—
—
VDD = 5.0V
VDD = 5.0V
20
—
Output high-impedance from
RESET Low
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.
2009-2014 Microchip Technology Inc.
DS20002121C-page 31
MCP23009/MCP23S09
TABLE 2-2:
GP AND INT PINS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
1.8V VDD 5.5V at -40C TA +125C.
AC Characteristics
Param.
Sym.
No.
Characteristic
Min. Typ.(2) Max. Units
Conditions
50
51
52
53
54
tGPOV
tINTD
Serial data to output valid
Interrupt pin disable time
GP input change to register valid
IOC event to INT active
—
—
—
—
—
—
—
500
600
—
ns
ns
tGPIV
450
—
ns Note 1
ns
tGPINT
600
50
tGLITCH Glitch filter on GP pins
—
ns Note 1
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ.”) column is at 5V, +25C, unless otherwise stated.
FIGURE 2-3:
GPIO AND INT TIMING
SCL
SDA
In
D1
D0
LSb of data byte zero
during a write or read
command, depending
on parameter
50
51
GPn
Output
Pin
INT
Pin
INT pin
inactive
INT pin active
53
GPn
Input
Pin
52
Register
Loaded
DS20002121C-page 32
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
TABLE 2-3:
HARDWARE ADDRESS LATCH TIMING
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
1.8V VDD 5.5V at -40C TA +125C.
AC Characteristics
Param.
Sym.
No.
Characteristic
Min. Typ.(2) Max. Units
Conditions
40
41
42
tADEN
Time from VDD stable after
POR to ADC enable
—
—
—
0
—
—
—
µs
ns
ns
Note 1
Note 1
Note 1
tADDRLAT Time from ADC enable to
address decode and latch
50
10
tADDIS
Time from raising edge of
serial clock to ADC disable
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ.”) column is at 5V, +25C, unless otherwise stated.
FIGURE 2-4:
HARDWARE ADDRESS LATCH TIMING
40
VDD
41
adc_en
i2c_addr[2:0]
SCL
42
2009-2014 Microchip Technology Inc.
DS20002121C-page 33
MCP23009/MCP23S09
FIGURE 2-5:
I2C™ BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
Stop
Condition
Start
Condition
Note 1: Refer to Figure 2-1 for load conditions.
FIGURE 2-6:
I2C™ BUS DATA TIMING
103
102
100
101
109
SCL
90
106
91
92
107
SDA
In
110
109
SDA
Out
Note 1: Refer to Figure 2-1 for load conditions.
DS20002121C-page 34
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
TABLE 2-4:
I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Electrical Characteristics: Unless otherwise indicated, all limits are
specified for 1.8V VDD 5.5V at -40C TA +125C,
RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF.
I2C™ AC Characteristics
Param.
No.
Characteristic
Sym.
Min.
Typ. Max. Units
Conditions
100 Clock High Time:
100 kHz mode
THIGH
4.0
0.6
—
—
—
—
—
—
µs 1.8V – 5.5V
400 kHz mode
µs 1.8V – 5.5V
µs 2.7V – 5.5V
3.4 MHz mode
0.06
101 Clock Low Time:
100 kHz mode
TLOW
4.7
1.3
—
—
—
—
—
—
µs 1.8V – 5.5V
µs 1.8V – 5.5V
µs 2.7V – 5.5V
400 kHz mode
3.4 MHz mode
0.16
102 SDA and SCL Rise Time:
100 kHz mode
TR
(Note 1)
—
20 + 0.1 CB
10
—
—
—
1000
300
80
ns 1.8V – 5.5V
ns 1.8V – 5.5V
ns 2.7V – 5.5V
(2)
400 kHz mode
3.4 MHz mode
103 SDA and SCL Fall Time:
100 kHz mode
TF
(Note 1)
—
20 + 0.1 CB
10
—
—
—
300
300
80
ns 1.8V – 5.5V
ns 1.8V – 5.5V
ns 2.7V – 5.5V
(2)
400 kHz mode
3.4 MHz mode
90
91
Start Condition Setup Time:
100 kHz mode
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
4.7
0.6
—
—
—
—
—
—
µs 1.8V – 5.5V
µs 1.8V – 5.5V
µs 2.7V – 5.5V
400 kHz mode
3.4 MHz mode
0.16
Start Condition Hold Time:
100 kHz mode
4.0
0.6
—
—
—
—
—
—
µs 1.8V – 5.5V
µs 1.8V – 5.5V
µs 2.7V – 5.5V
400 kHz mode
3.4 MHz mode
0.16
106 Data Input Hold Time:
100 kHz mode
0
0
0
—
—
—
3.45
0.9
µs 1.8V – 5.5V
µs 1.8V – 5.5V
µs 2.7V – 5.5V
400 kHz mode
3.4 MHz mode
0.07
107 Data Input Setup Time:
100 kHz mode
250
100
0.01
—
—
—
—
—
—
ns 1.8V – 5.5V
ns 1.8V – 5.5V
µs 2.7V – 5.5V
400 kHz mode
3.4 MHz mode
92
Stop Condition Setup Time:
100 kHz mode
4.0
0.6
—
—
—
—
—
—
µs 1.8V – 5.5V
µs 1.8V – 5.5V
µs 2.7V – 5.5V
400 kHz mode
3.4 MHz mode
0.16
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified from 10 to 400 (pF).
3: This parameter is not applicable in high-speed mode (3.4 MHz).
2009-2014 Microchip Technology Inc.
DS20002121C-page 35
MCP23009/MCP23S09
TABLE 2-4:
I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, all limits are
specified for 1.8V VDD 5.5V at -40C TA +125C,
RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF.
I2C™ AC Characteristics
Param.
No.
Characteristic
Sym.
Min.
Typ. Max. Units
Conditions
109 Output Valid From Clock:
100 kHz mode
TAA
—
—
—
—
—
—
3.45
0.9
µs 1.8V – 5.5V
400 kHz mode
µs 1.8V – 5.5V
µs 2.7V – 5.5V
3.4 MHz mode
0.18
110 Bus Free Time:
100 kHz mode
TBUF
(Note 3)
4.7
1.3
N/A
—
—
—
—
—
µs 1.8V – 5.5V
µs 1.8V – 5.5V
µs 2.7V – 5.5V
400 kHz mode
3.4 MHz mode
N/A
Bus Capacitive Loading:
100 kHz and 400 kHz
3.4 MHz
CB
(Note 2)
—
—
—
—
400
100
pF Note 1
pF Note 1
Input Filter Spike
TSP
Suppression: (SDA and SCL)
100 kHz and 400 kHz
3.4 MHz
—
—
—
—
50
10
ns Note 1
ns Note 1
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified from 10 to 400 (pF).
3: This parameter is not applicable in high-speed mode (3.4 MHz).
FIGURE 2-7: SPI INPUT TIMING
3
CS
11
10
6
1
2
7
Mode 1,1
SCK
SI
Mode 0,0
4
5
MSB in
LSB in
high impedance
SO
DS20002121C-page 36
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
FIGURE 2-8:
SPI OUTPUT TIMING
CS
2
8
9
SCK
Mode 1,1
Mode 0,0
12
14
13
SO
SI
MSB out
LSB out
don’t care
2009-2014 Microchip Technology Inc.
DS20002121C-page 37
MCP23009/MCP23S09
TABLE 2-5:
SPI INTERFACE AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, all limits are specified
for 1.8V VDD 5.5V at -40C TA +125C.
SPI Interface AC Characteristics
Param.
Characteristic
No.
Sym.
Min.
Typ.
Max.
Units
Conditions
Clock Frequency
FCLK
TCSS
TCSH
—
50
50
—
—
—
10
—
—
MHz 1.8V – 5.5V
ns
1
2
CS Setup Time
CS Hold Time
ns
1.8V – 5.5V
3
4
CS Disable Time
Data Setup Time
Data Hold Time
CLK Rise Time
CLK Fall Time
TCSD
TSU
THD
TR
50
10
10
—
—
45
45
50
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
1.8V – 5.5V
1.8V – 5.5V
1.8V – 5.5V
Note 1
5
6
7
TF
2
Note 1
8
Clock High Time
Clock Low Time
Clock Delay Time
Clock Enable Time
THI
—
—
—
—
45
1.8V – 5.5V
1.8V – 5.5V
9
TLO
TCLD
TCLE
TV
10
11
12
Output Valid from Clock
Low
1.8V – 5.5V
13
14
Output Hold Time
THO
TDIS
0
—
—
—
ns
ns
Output Disable Time
—
100
Note 1: This parameter is characterized, not 100% tested.
FIGURE 2-9:
TYPICAL PERFORMANCE CURVE FOR SPI TV SPECIFICATION (PARAM #12)
TV vs. VDD
40
35
30
25
20
15
10
5
T = +125°C
T = +85°C
T = -40°C
T = +25°C
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
DS20002121C-page 38
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
3.0
3.1
PACKAGING INFORMATION
Package Marking Information
16-Lead QFN (3x3x0.9 mm)
Example
2S9
E432
256
EYWW
18-Lead PDIP (300 mil)
Example
MCP23S09
E/P
3
e
1432256
18-Lead SOIC (7.50 mm)
Example
MCP23S09
E/SO
e
3
1432
256
20-Lead SSOP (5.30 mm)
Example
MCP23009
e
3
E/SS
1432256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2014 Microchip Technology Inc.
DS20002121C-page 39
MCP23009/MCP23S09
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002121C-page 40
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002121C-page 41
MCP23009/MCP23S09
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002121C-page 42
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
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2009-2014 Microchip Technology Inc.
DS20002121C-page 43
MCP23009/MCP23S09
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002121C-page 44
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002121C-page 45
MCP23009/MCP23S09
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002121C-page 46
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
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2009-2014 Microchip Technology Inc.
DS20002121C-page 47
MCP23009/MCP23S09
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002121C-page 48
2009-2014 Microchip Technology Inc.
MCP23009/MCP23S09
APPENDIX A: REVISION HISTORY
Revision C (August 2014)
The following is the list of modifications:
1. Added ESD data in the Absolute Maximum
Ratings (†) section.
2. Updated Figure 1-1.
3. Updated the DC Characteristics table.
4. Updated the Package Marking Information
section.
5. Minor typographical changes.
Revision B (May 2009)
The following is the list of modifications:
1. Added the 3x3 QFN package (MG package
marking).
2. Updated Revision History.
Revision A (December 2008)
• Original Release of this Document.
2009-2014 Microchip Technology Inc.
DS20002121C-page 49
MCP23009/MCP23S09
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
-X
/XX
a) MCP23009-E/MG: Extended Temperature,
16LD QFN package
Temperature
Range
Package
b) MCP23009-E/P:
Extended Temperature,
18LD PDIP package
2
Device:
MCP23009:
8-Bit I/O Expander w/ I C™ Interface
c) MCP23009-E/SO: Extended Temperature,
18LD SOIC package
2
MCP23009T: 8-Bit I/O Expander w/ I C Interface
(Tape and Reel)
MCP23S09:
MCP23S09T: 8-Bit I/O Expander w/ SPI Interface
(Tape and Reel)
d) MCP23009T-E/SO: Tape and Reel,
Extended Temperature,
8-Bit I/O Expander w/ SPI Interface
18LD SOIC package
e) MCP23009-E/SS: Extended Temperature,
20LD SSOP package
f)
MCP23009T-E/SS: Tape and Reel,
Extended Temperature,
20LD SSOP package
Temperature
Range:
E
= -40C to +125C (Extended)
Package:
MG = Plastic Quad Flat, No Lead Package –
3x3x0.9 mm Body, 16-Lead
a) MCP23S09-E/MG: Extended Temperature,
16LD QFN package
P
= Plastic Dual In-Line – 300 mil Body, 18-Lead
b) MCP23S09T-E/MG: Tape and Reel,
Extended Temperature,
SO = Plastic Small Outline – Wide, 7.50 mm Body,
18-Lead
16LD QFN package
SS = Lead Plastic Shrink Small Outline –
5.30 mm Body, 20-Lead
c) MCP23S09-E/P:
Extended Temperature,
18LD PDIP package
d) MCP23S09-E/SO: Extended Temperature,
18LD SOIC package
e) MCP23S09T-E/SO: Tape and Reel,
Extended Temperature,
18LD SOIC package
DS20002121C-page 50
2009-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-540-6
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2009-2014 Microchip Technology Inc.
DS20002121C-page 51
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Austin, TX
Tel: 512-257-3370
Germany - Pforzheim
Tel: 49-7231-424750
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Poland - Warsaw
Tel: 48-22-3325737
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Sweden - Stockholm
Tel: 46-8-5090-4654
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Novi, MI
Tel: 248-848-4000
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Los Angeles
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
DS20002121C-page 52
2009-2014 Microchip Technology Inc.
相关型号：
MCP23S09T-E/MG
8 I/O, PIA-GENERAL PURPOSE, PQCC16, 3 X 3 MM, 0.90 MM HEIGHT, PLASTIC, QFN-16
MICROCHIP
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