MCP23S17T-E/ML_技术文档

MCP23017/MCP23S17

16-Bit I/O Expander with Serial Interface

Features

Package Types

• 16-bit remote bidirectional I/O port

- I/O pins default to input

• High-speed I²C™ interface (MCP23017)

- 100 kHz

• 1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GPA7

GPA6

GPA5

GPA4

GPA3

GPA2

GPA1

GPA0

INTA

INTB

RESET

A2

GPB0

GPB1

GPB2

GPB3

GPB4

PDIP,

SOIC,

SSOP

GPB5

GPB6

GPB7

VDD

- 400 kHz

9

- 1.7 MHz

VSS

10

11

12

13

14

• High-speed SPI interface (MCP23S17)

- 10 MHz (max.)

NC

SCL

SDA

NC

A1

A0

• Three hardware address pins to allow up to eight

devices on the bus

• Configurable interrupt output pins

QFN

- Configurable as active-high, active-low or

open-drain

28272625242322

21

GPA4

GPA3

GPA2

GPA1

GPA0

INTA

GPB4

1

2

3

4

5

6

7

• INTA and INTB can be configured to operate

independently or together

20

19

18

17

16

15

GPB5

GPB6

GPB7

MCP23017

• Configurable interrupt source

V

DD

V

SS

- Interrupt-on-change from configured register

defaults or pin changes

INTB

NC

8 9 1011121314

• Polarity Inversion register to configure the polarity

of the input port data

• External Reset input

• Low standby current: 1 µA (max.)

• Operating voltage:

• 1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GPA7

GPA6

GPA5

GPA4

GPA3

GPA2

GPA1

GPA0

INTA

INTB

RESET

A2

GPB0

GPB1

GPB2

GPB3

GPB4

PDIP,

SOIC,

SSOP

- 1.8V to 5.5V @ -40°C to +85°C

- 2.7V to 5.5V @ -40°C to +85°C

- 4.5V to 5.5V @ -40°C to +125°C

GPB5

GPB6

GPB7

VDD

Packages

9

VSS

10

11

12

13

14

• 28-pin PDIP (300 mil)

• 28-pin SOIC (300 mil)

• 28-pin SSOP

CS

SCK

SI

A1

A0

SO

• 28-pin QFN

QFN

28272625242322

21

1

GPA4

GPA3

GPA2

GPA1

GPA0

INTA

GPB4

20

19

18

17

16

15

2

3

4

5

6

7

GPB5

GPB6

GPB7

MCP23S17

V

DD

V

SS

INTB

CS

8 9 1011121314

DS21952B-page 1

MCP23017/MCP23S17

Functional Block Diagram

MCP23S17

CS

SCK

SI

SPI

SO

MCP23017

GPB7

GPB6

GPB5

GPB4

GPB3

GPB2

GPB1

GPB0

Serializer/

Deserializer

SCL

SDA

I²C™

3

GPIO

A2:A0

Decode

RESET

Control

16

INTA

INTB

Interrupt

Logic

GPA7

GPA6

GPA5

GPA4

GPA3

GPA2

GPA1

GPA0

8

GPIO

Configuration/

Control

Registers

DS21952B-page 2

MCP23017/MCP23S17

There are two interrupt pins, INTA and INTB, that can

be associated with their respective ports, or can be

logically OR’ed together so that both pins will activate if

either port causes an interrupt.

1.0

DEVICE OVERVIEW

The MCP23017/MCP23S17 (MCP23X17) device

family provides 16-bit, general purpose parallel I/O

expansion for I²C bus or SPI applications. The two

devices differ only in the serial interface.

The interrupt output can be configured to activate

under two conditions (mutually exclusive):

• MCP23017 – I²C interface

1. When any input state differs from its

corresponding Input Port register state. This is

used to indicate to the system master that an

input state has changed.

• MCP23S17 – SPI interface

The MCP23X17 consists of multiple 8-bit configuration

registers for input, output and polarity selection. The

system master can enable the I/Os as either inputs or

outputs by writing the I/O configuration bits (IODIRA/B).

The data for each input or output is kept in the

corresponding input or output register. The polarity of

the Input Port register can be inverted with the Polarity

Inversion register. All registers can be read by the

system master.

2. When an input state differs from a preconfigured

register value (DEFVAL register).

The Interrupt Capture register captures port values at

the time of the interrupt, thereby saving the condition

that caused the interrupt.

The Power-on Reset (POR) sets the registers to their

default values and initializes the device state machine.

The 16-bit I/O port functionally consists of two 8-bit

ports (PORTA and PORTB). The MCP23X17 can be

configured to operate in the 8-bit or 16-bit modes via

IOCON.BANK.

The hardware address pins are used to determine the

device address.

DS21952B-page 3

MCP23017/MCP23S17

1.1

Pin Descriptions

TABLE 1-1:

PINOUT DESCRIPTION

PDIP/

SOIC/

SSOP

Name

Type

QFN

Function

GPB0

GPB1

GPB2

GPB3

GPB4

GPB5

GPB6

GPB7

1

2

3

4

5

6

7

8

25

26

27

28

1

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

2

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

3

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

4

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

V_DD

9

5

6

P

I

Power

V_SS

10

11

12

13

14

15

16

17

18

19

20

21

Ground

NC/CS

SCL/SCK

SDA/SI

NC/SO

A0

7

NC (MCP23017), Chip Select (MCP23S17)

Serial clock input

8

I

9

I/O Serial data I/O (MCP23017), Serial data input (MCP23S17)

10

11

12

13

14

15

16

17

O

I

NC (MCP23017), Serial data out (MCP23S17)

Hardware address pin. Must be externally biased.

A1

I

Hardware address pin. Must be externally biased.

A2

I

Hardware address pin. Must be externally biased.

RESET

INTB

INTA

GPA0

I

Hardware reset. Must be externally biased.

O

Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.

Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

GPA1

GPA2

GPA3

GPA4

GPA5

GPA6

GPA7

22

23

24

25

26

27

28

18

19

20

21

22

23

24

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

resistor.

DS21952B-page 4

MCP23017/MCP23S17

1.3.1

BYTE MODE AND SEQUENTIAL

MODE

1.2

Power-on Reset (POR)

The on-chip POR circuit holds the device in reset until

VDD has reached a high enough voltage to deactivate

the POR circuit (i.e., release the device from reset).

The maximum VDD rise time is specified in Section 2.0

“Electrical Characteristics”.

The MCP23X17 family has the ability to operate in Byte

mode or Sequential mode (IOCON.SEQOP).

Byte Mode disables automatic Address Pointer

incrementing. When operating in Byte mode, the

MCP23X17 family does not increment its internal

address counter after each byte during the data

transfer. This gives the ability to continually access the

same address by providing extra clocks (without

additional control bytes). This is useful for polling the

GPIO register for data changes or for continually

writing to the output latches.

When the device exits the POR condition (releases

reset), device operating parameters (i.e., voltage,

temperature, serial bus frequency, etc.) must be met to

ensure proper operation.

1.3

Serial Interface

This block handles the functionality of the I²C

(MCP23017) or SPI (MCP23S17) interface protocol.

The MCP23X17 contains 22 individual registers (11

register pairs) that can be addressed through the Serial

Interface block, as shown in Table 1-2.

A special mode (Byte mode with IOCON.BANK = 0)

causes the address pointer to toggle between

associated A/B register pairs. For example, if the BANK

bit is cleared and the Address Pointer is initially set to

address 12h (GPIOA) or 13h (GPIOB), the pointer will

toggle between GPIOA and GPIOB. Note that the

Address Pointer can initially point to either address in

the register pair.

TABLE 1-2:

Address

IOCON.BANK = 1 IOCON.BANK = 0

REGISTER ADDRESSES

Address

Access to:

Sequential mode enables automatic address pointer

incrementing. When operating in Sequential mode, the

MCP23X17 family increments its address counter after

each byte during the data transfer. The Address Pointer

automatically rolls over to address 00h after accessing

the last register.

00h

10h

01h

11h

02h

12h

03h

13h

04h

14h

05h

15h

06h

16h

07h

17h

08h

18h

09h

19h

0Ah

1Ah

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

IODIRA

IODIRB

IPOLA

IPOLB

GPINTENA

GPINTENB

DEFVALA

DEFVALB

INTCONA

INTCONB

IOCON

These two modes are not to be confused with single

writes/reads and continuous writes/reads that are

serial protocol sequences. For example, the device

may be configured for Byte mode and the master may

perform

a continuous read. In this case, the

MCP23X17 would not increment the Address Pointer

and would repeatedly drive data from the same

location.

IOCON

2

1.3.2

I C INTERFACE

GPPUA

GPPUB

INTFA

2

1.3.2.1

I C Write Operation

The I²C write operation includes the control byte and

register address sequence, as shown in the bottom of

Figure 1-1. This sequence is followed by eight bits of

data from the master and an Acknowledge (ACK) from

the MCP23017. The operation is ended with a Stop (P)

or Restart (SR) condition being generated by the

master.

INTFB

INTCAPA

INTCAPB

GPIOA

GPIOB

OLATA

Data is written to the MCP23017 after every byte

transfer. If a Stop or Restart condition is generated

during a data transfer, the data will not be written to the

MCP23017.

OLATB

Both “byte writes” and “sequential writes” are

supported by the MCP23017. If Sequential mode is

enabled (IOCON, SEQOP

=

0) (default), the

MCP23017 increments its address counter after each

ACK during the data transfer.

DS21952B-page 5

MCP23017/MCP23S17

2

1.3.2.2

I C Read Operation

1.3.3

SPI INTERFACE

I²C Read operations include the control byte sequence,

as shown in the bottom of Figure 1-1. This sequence is

followed by another control byte (including the Start

condition and ACK) with the R/W bit set (R/W = 1). The

MCP23017 then transmits the data contained in the

addressed register. The sequence is ended with the

master generating a Stop or Restart condition.

1.3.3.1

SPI Write Operation

The SPI write operation is started by lowering CS. The

Write command (slave address with R/W bit cleared) is

then clocked into the device. The opcode is followed by

an address and at least one data byte.

1.3.3.2

SPI Read Operation

2

1.3.2.3

I C Sequential Write/Read

The SPI read operation is started by lowering CS. The

SPI read command (slave address with R/W bit set) is

then clocked into the device. The opcode is followed by

an address, with at least one data byte being clocked

out of the device.

For sequential operations (Write or Read), instead of

transmitting a Stop or Restart condition after the data

transfer, the master clocks the next byte pointed to by

the address pointer (see Section 1.3.1 “Byte Mode

and Sequential Mode” for details regarding sequential

operation control).

1.3.3.3

SPI Sequential Write/Read

For sequential operations, instead of deselecting the

device by raising CS, the master clocks the next byte

pointed to by the Address Pointer. (see Section 1.3.1

“Byte Mode and Sequential Mode” for details

regarding sequential operation control).

The sequence ends with the master sending a Stop or

Restart condition.

The MCP23017 Address Pointer will roll over to

address zero after reaching the last register address.

Refer to Figure 1-1.

The sequence ends by the raising of CS.

The MCP23S17 Address Pointer will roll over to

address zero after reaching the last register address.

DS21952B-page 6

MCP23017/MCP23S17

2

FIGURE 1-1:

MCP23017 I C™ DEVICE PROTOCOL

- Start

S

SR

P

- Restart

DIN

S

OP

W

ADDR

....

P

- Stop

- Write

- Read

w

DOUT

DIN

D

OUT

SR

OP

R

P

....

R

D

IN

SR

P

W

- Device opcode

ADDR - Device register address

OP

- Data out from MCP23017

- Data in to MCP23017

DOUT

DIN

DOUT

S

OP

R

P

....

DOUT

SR

OP

R

P

....

DIN

....

DIN

P

SR

OP

W

ADDR

P

Byte and Sequential Write

DIN

S

OP

W

ADDR

P

Byte

DIN

....

P

Sequential

Byte and Sequential Read

Byte

D

OUT

S

W

OP

SR

OP

R

P

D

OUT

Sequential

DOUT

....

P

DS21952B-page 7

MCP23017/MCP23S17

2

FIGURE 1-2:

I C™ CONTROL BYTE

1.4

Hardware Address Decoder

FORMAT

The hardware address pins are used to determine the

device address. To address a device, the correspond-

ing address bits in the control byte must match the pin

state. The pins must be biased externally.

Control Byte

A2 A1 A0 R/W ACK

S

0

1

0

2

Slave Address

R/W bit

1.4.1

ADDRESSING I C DEVICES

(MCP23017)

Start

bit

The MCP23017 is a slave I²C interface device that

supports 7-bit slave addressing, with the read/write bit

filling out the control byte. The slave address contains

four fixed bits and three user-defined hardware

address bits (pins A2, A1 and A0). Figure 1-2 shows

the control byte format.

ACK bit

R/W = 0= write

R/W = 1= read

FIGURE 1-3:

SPI CONTROL BYTE

FORMAT

1.4.2

ADDRESSING SPI DEVICES

(MCP23S17)

CS

The MCP23S17 is a slave SPI device. The slave

address contains four fixed bits and three user-defined

hardware address bits (if enabled via IOCON.HAEN)

(pins A2, A1 and A0) with the read/write bit filling out

the control byte. Figure 1-3 shows the control byte

format. The address pins should be externally biased

even if disabled (IOCON.HAEN = 0).

Control Byte

0

1

0

A2 A1 A0 R/W

Slave Address

R/W bit

R/W = 0= write

R/W = 1= read

2

FIGURE 1-4:

I C™ ADDRESSING REGISTERS

S

0

1

0

A2 A1 A0

0

ACK* A7

A6

A5

A4

A3

A2

A1

A0 ACK*

R/W = 0

Device Opcode

Register Address

*The ACKs are provided by the MCP23017.

FIGURE 1-5:

SPI ADDRESSING REGISTERS

CS

0

1

0

A2 A1 A0 R/W A7

A6

A5

A4

A3

A2

A1

A0

*

Device Opcode

Register Address

* Address pins are enabled/disabled via IOCON.HAEN.

DS21952B-page 8

MCP23017/MCP23S17

Reading the GPIOn register reads the value on the

port. Reading the OLATn register only reads the

latches, not the actual value on the port.

1.5

GPIO Port

The GPIO module is a general purpose, 16-bit wide,

bidirectional port that is functionally split into two 8-bit

wide ports.

Writing to the GPIOn register actually causes a write to

the latches (OLATn). Writing to the OLATn register

forces the associated output drivers to drive to the level

in OLATn. Pins configured as inputs turn off the

associated output driver and put it in high-impedance.

The GPIO module contains the data ports (GPIOn),

internal pull-up resistors and the output latches

(OLATn).

TABLE 1-3:

SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1)

Register

Name

Address

(hex)

POR/RST

value

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IODIRA

IPOLA

00

01

02

06

09

0A

10

11

12

16

19

1A

IO7

IP7

IO6

IP6

IO5

IP5

IO4

IP4

IO3

IP3

IO2

IP2

IO1

IP1

IO0

IP0

1111 1111

0000 0000

GPINTENA

GPPUA

GPIOA

GPINT7

PU7

GPINT6

PU6

GPINT5

PU5

GPINT4

PU4

GPINT3

PU3

GPINT2

PU2

GPINT1

PU1

GPINT0 0000 0000

PU0

GP0

OL0

IO0

0000 0000

1111 1111

0000 0000

GP7

OL7

GP6

OL6

GP5

OL5

GP4

OL4

GP3

OL3

GP2

OL2

GP1

OL1

OLATA

IODIRB

IPOLB

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

GPINTENB

GPPUB

GPIOB

GPINT7

PU7

GPINT6

PU6

GPINT5

PU5

GPINT4

PU4

GPINT3

PU3

GPINT2

PU2

GPINT1

PU1

GPINT0 0000 0000

PU0

GP0

OL0

0000 0000

GP7

OL7

GP6

OL6

GP5

OL5

GP4

OL4

GP3

OL3

GP2

OL2

GP1

OL1

OLATB

TABLE 1-4:

SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0)

Register

Name

Address

(hex)

POR/RST

value

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IODIRA

IODIRB

IPOLA

00

01

02

03

04

05

0C

0D

12

13

14

15

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

IP0

1111 1111

0000 0000

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IPOLB

IP7

IP6

IP5

IP4

IP3

IP2

IP1

GPINTENA

GPINTENB

GPPUA

GPPUB

GPIOA

GPINT7

PU7

GPINT6

PU6

GPINT5

PU5

GPINT4

PU4

GPINT3

PU3

GPINT2

PU2

GPINT1

PU1

GPINT0 0000 0000

PU0

GP0

OL0

0000 0000

PU7

PU6

PU5

PU4

PU3

PU2

PU1

GP7

OL7

GP6

OL6

GP5

OL5

GP4

OL4

GP3

OL3

GP2

OL2

GP1

OL1

GPIOB

OLATA

OLATB

OL7

OL6

OL5

OL4

OL3

OL2

OL1

DS21952B-page 9

MCP23017/MCP23S17

are associated with PortB. One register (IOCON) is

shared between the two ports. The PortA registers are

identical to the PortB registers, therefore, they will be

referred to without differentiating between the port

designation (i.e., they will not have the “A” or “B”

designator assigned) in the register tables.

1.6

Configuration and Control

Registers

There are 21 registers associated with the MCP23X17,

as shown in Table 1-5 and Table 1-6. The two tables

show the register mapping with the two BANK bit

values. Ten registers are associated with PortA and ten

TABLE 1-5:

CONTROL REGISTER SUMMARY (IOCON.BANK = 1)

Register

Name

Address

(hex)

POR/RST

value

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IODIRA

IPOLA

00

01

02

03

04

05

06

07

08

09

0A

10

11

12

13

14

15

16

17

18

19

1A

IO7

IP7

IO6

IP6

IO5

IP5

IO4

IP4

IO3

IP3

IO2

IP2

IO1

IP1

IO0

IP0

1111 1111

0000 0000

GPINTENA

DEFVALA

INTCONA

IOCON

GPINT7

DEF7

IOC7

BANK

PU7

GPINT6

DEF6

IOC6

GPINT5

DEF5

IOC5

GPINT4

DEF4

IOC4

GPINT3

DEF3

IOC3

HAEN

PU3

GPINT2

DEF2

IOC2

ODR

PU2

GPINT1

DEF1

IOC1

INTPOL

PU1

GPINT0 0000 0000

DEF0

IOC0

—

0000 0000

1111 1111

0000 0000

MIRROR SEQOP DISSLW

GPPUA

INTFA

PU6

INT6

ICP6

GP6

PU5

INT5

ICP5

GP5

PU4

INT4

ICP4

GP4

PU0

INTO

ICP0

GP0

OL0

IO0

INT7

ICP7

GP7

INT3

ICP3

GP3

INT2

ICP2

GP2

INT1

ICP1

GP1

INTCAPA

GPIOA

OLATA

OL7

OL6

OL5

OL4

OL3

OL2

OL1

IODIRB

IPOLB

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

GPINTENB

DEFVALB

INTCONB

IOCON

GPINT7

DEF7

IOC7

BANK

PU7

GPINT6

DEF6

IOC6

GPINT5

DEF5

IOC5

GPINT4

DEF4

IOC4

GPINT3

DEF3

IOC3

HAEN

PU3

GPINT2

DEF2

IOC2

ODR

PU2

GPINT1

DEF1

IOC1

INTPOL

PU1

GPINT0 0000 0000

DEF0

IOC0

—

0000 0000

MIRROR SEQOP DISSLW

GPPUB

INTFB

PU6

INT6

ICP6

GP6

OL6

PU5

INT5

ICP5

GP5

OL5

PU4

INT4

ICP4

GP4

OL4

PU0

INTO

ICP0

GP0

OL0

INT7

ICP7

GP7

INT3

ICP3

GP3

INT2

ICP2

GP2

INT1

ICP1

GP1

INTCAPB

GPIOB

OLATB

OL7

OL3

OL2

OL1

DS21952B-page 10

MCP23017/MCP23S17

TABLE 1-6:

CONTROL REGISTER SUMMARY (IOCON.BANK = 0)

Register

Name

Address

(hex)

POR/RST

value

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IODIRA

IODIRB

IPOLA

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

IP0

1111 1111

0000 0000

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IPOLB

IP7

IP6

IP5

IP4

IP3

IP2

IP1

GPINTENA

GPINTENB

DEFVALA

DEFVALB

INTCONA

INTCONB

IOCON

GPINT7

DEF7

IOC7

BANK

PU7

GPINT6

DEF6

IOC6

GPINT5

DEF5

IOC5

GPINT4

DEF4

IOC4

GPINT3

DEF3

IOC3

HAEN

PU3

GPINT2

DEF2

IOC2

ODR

PU2

GPINT1

DEF1

IOC1

INTPOL

PU1

GPINT0 0000 0000

DEF0

IOC0

—

0000 0000

MIRROR SEQOP DISSLW

IOCON

—

GPPUA

GPPUB

INTFA

PU6

INT6

ICP6

GP6

OL6

PU5

INT5

ICP5

GP5

OL5

PU4

INT4

ICP4

GP4

OL4

PU0

INTO

ICP0

GP0

OL0

PU7

PU3

PU2

PU1

INT7

ICP7

GP7

INT3

ICP3

GP3

INT2

ICP2

GP2

INT1

ICP1

GP1

INTFB

INTCAPA

INTCAPB

GPIOA

12

13

14

15

GPIOB

GP7

GP3

GP2

GP1

OLATA

OL7

OL3

OL2

OL1

OLATB

OL7

OL3

OL2

OL1

DS21952B-page 11

MCP23017/MCP23S17

1.6.1

I/O DIRECTION REGISTER

Controls the direction of the data I/O.

When a bit is set, the corresponding pin becomes an

input. When a bit is clear, the corresponding pin

becomes an output.

REGISTER 1-1:

IODIR – I/O DIRECTION REGISTER (ADDR 0x00)

R/W-1

IO7

R/W-1

IO6

R/W-1

IO5

R/W-1

IO4

R/W-1

IO3

R/W-1

IO2

R/W-1

IO1

R/W-1

IO0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

IO7:IO0: These bits control the direction of data I/O <7:0>

1= Pin is configured as an input.

0= Pin is configured as an output.

DS21952B-page 12

MCP23017/MCP23S17

1.6.2

INPUT POLARITY REGISTER

This register allows the user to configure the polarity on

the corresponding GPIO port bits.

If a bit is set, the corresponding GPIO register bit will

reflect the inverted value on the pin.

REGISTER 1-2:

IPOL – INPUT POLARITY PORT REGISTER (ADDR 0x01)

R/W-0

IP7

R/W-0

IP6

R/W-0

IP5

R/W-0

IP4

R/W-0

IP3

R/W-0

IP2

R/W-0

IP1

R/W-0

IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

IP7:IP0: These bits control the polarity inversion of the input pins <7:0>

1= GPIO register bit will reflect the opposite logic state of the input pin.

0= GPIO register bit will reflect the same logic state of the input pin.

DS21952B-page 13

MCP23017/MCP23S17

1.6.3

INTERRUPT-ON-CHANGE

CONTROL REGISTER

The GPINTEN register controls the interrupt-on-

change feature for each pin.

If a bit is set, the corresponding pin is enabled for

interrupt-on-change. The DEFVAL and INTCON

registers must also be configured if any pins are

enabled for interrupt-on-change.

REGISTER 1-3:

GPINTEN – INTERRUPT-ON-CHANGE PINS (ADDR 0x02)

R/W-0

GPINT7

bit 7

R/W-0

GPINT6

GPINT5

GPINT4

GPINT3

GPINT2

GPINT1

GPINT0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

GPINT7:GPINT0: General purpose I/O interrupt-on-change bits <7:0>

1= Enable GPIO input pin for interrupt-on-change event.

0= Disable GPIO input pin for interrupt-on-change event.

Refer to INTCON and GPINTEN.

DS21952B-page 14

MCP23017/MCP23S17

1.6.4

DEFAULT COMPARE REGISTER

FOR INTERRUPT-ON-CHANGE

The default comparison value is configured in the

DEFVAL register. If enabled (via GPINTEN and

INTCON) to compare against the DEFVAL register, an

opposite value on the associated pin will cause an

interrupt to occur.

REGISTER 1-4:

DEFVAL – DEFAULT VALUE REGISTER (ADDR 0x03)

R/W-0

DEF7

R/W-0

DEF6

R/W-0

DEF5

R/W-0

DEF4

R/W-0

DEF3

R/W-0

DEF2

R/W-0

DEF1

R/W-0

DEF0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

DEF7:DEF0: These bits set the compare value for pins configured for interrupt-on-change from

defaults <7:0>. Refer to INTCON.

If the associated pin level is the opposite from the register bit, an interrupt occurs.

Refer to INTCON and GPINTEN.

DS21952B-page 15

MCP23017/MCP23S17

1.6.5

INTERRUPT CONTROL REGISTER

The INTCON register controls how the associated pin

value is compared for the interrupt-on-change feature.

If a bit is set, the corresponding I/O pin is compared

against the associated bit in the DEFVAL register. If a

bit value is clear, the corresponding I/O pin is compared

against the previous value.

REGISTER 1-5:

INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04)

R/W-0

IOC7

R/W-0

IOC6

R/W-0

IOC5

R/W-0

IOC4

R/W-0

IOC3

R/W-0

IOC2

R/W-0

IOC1

R/W-0

IOC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

IOC7:IOC0: These bits control how the associated pin value is compared for interrupt-on-change

<7:0>

1= Controls how the associated pin value is compared for interrupt-on-change.

0= Pin value is compared against the previous pin value.

Refer to INTCON and GPINTEN.

DS21952B-page 16

MCP23017/MCP23S17

The MIRROR bit controls how the INTA and INTB pins

function with respect to each other.

1.6.6

CONFIGURATION REGISTER

The IOCON register contains several bits for

configuring the device:

• When MIRROR = 1, the INTn pins are functionally

OR’ed so that an interrupt on either port will cause

both pins to activate.

The BANK bit changes how the registers are mapped

(see Table 1-5 and Table 1-6 for more details).

• When MIRROR = 0, the INT pins are separated.

Interrupt conditions on a port will cause its

respective INT pin to activate.

• If BANK = 1, the registers associated with each

port are segregated. Registers associated with

PORTA are mapped from address 00h- 0Ahand

registers associated with PORTB are mapped

from 10h - 1Ah.

The Sequential Operation (SEQOP) controls the

incrementing function of the Address Pointer. If the

address pointer is disabled, the Address Pointer does

not automatically increment after each byte is clocked

during a serial transfer. This feature is useful when it is

desired to continuously poll (read) or modify (write) a

register.

• If BANK = 0, the A/B registers are paired. For

example, IODIRA is mapped to address 00h and

IODIRB is mapped to the next address (address

01h). The mapping for all registers is from 00h -

15h.

The Slew Rate (DISSLW) bit controls the slew rate

function on the SDA pin. If enabled, the SDA slew rate

will be controlled when driving from a high to low.

It is important to take care when changing the BANK bit

as the address mapping changes after the byte is

clocked into the device. The address pointer may point

to an invalid location after the bit is modified.

The Hardware Address Enable (HAEN) bit enables/

disables hardware addressing on the MCP23S17 only.

The address pins (A2, A1 and A0) must be externally

biased, regardless of the HAEN bit value.

For example, if the device is configured to

automatically increment its internal Address Pointer,

the following scenario would occur:

If enabled (HAEN = 1), the device’s hardware address

matches the address pins.

• BANK = 0

• Write 80h to address 0Ah (IOCON) to set the

BANK bit

If disabled (HAEN = 0), the device’s hardware address

is A2 = A1 = A0 = 0.

• Once the write completes, the internal address

now points to 0Bh which is an invalid address

when the BANK bit is set.

The Open-Drain (ODR) control bit enables/disables the

INT pin for open-drain configuration. Erasing this bit

overrides the INTPOL bit.

For this reason, it is advised to only perform byte writes

to this register when changing the BANK bit.

The Interrupt Polarity (INTPOL) sets the polarity of the

INT pin. This bit is functional only when the ODR bit is

cleared, configuring the INT pin as active push-pull.

DS21952B-page 17

MCP23017/MCP23S17

REGISTER 1-6:

IOCON – I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)

R/W-0

BANK

R/W-0

HAEN

R/W-0

ODR

R/W-0

U-0

—

SEQOP

DISSLW

INTPOL

MIRROR

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

BANK: Controls how the registers are addressed

1= The registers associated with each port are separated into different banks

0= The registers are in the same bank (addresses are sequential)

MIRROR: INT Pins Mirror bit

1= The INT pins are internally connected

0= The INT pins are not connected. INTA is associated with PortA and INTB is associated with PortB

SEQOP: Sequential Operation mode bit.

1= Sequential operation disabled, address pointer does not increment.

0= Sequential operation enabled, address pointer increments.

DISSLW: Slew Rate control bit for SDA output.

1= Slew rate disabled.

0= Slew rate enabled.

HAEN: Hardware Address Enable bit (MCP23S17 only).

Address pins are always enabled on MCP23017.

1= Enables the MCP23S17 address pins.

0= Disables the MCP23S17 address pins.

bit 2

bit 1

bit 0

ODR: This bit configures the INT pin as an open-drain output.

1= Open-drain output (overrides the INTPOL bit).

0= Active driver output (INTPOL bit sets the polarity).

INTPOL: This bit sets the polarity of the INT output pin.

1= Active-high.

0= Active-low.

Unimplemented: Read as ‘0’.

DS21952B-page 18

MCP23017/MCP23S17

1.6.7

PULL-UP RESISTOR

CONFIGURATION REGISTER

The GPPU register controls the pull-up resistors for the

port pins. If a bit is set and the corresponding pin is

configured as an input, the corresponding port pin is

internally pulled up with a 100 kΩ resistor.

REGISTER 1-7:

GPPU – GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)

R/W-0

PU7

R/W-0

PU6

R/W-0

PU5

R/W-0

PU4

R/W-0

PU3

R/W-0

PU2

R/W-0

PU1

R/W-0

PU0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

PU7:PU0: These bits control the weak pull-up resistors on each pin (when configured as an input)

<7:0>.

1= Pull-up enabled.

0= Pull-up disabled.

DS21952B-page 19

MCP23017/MCP23S17

1.6.8

INTERRUPT FLAG REGISTER

The INTF register reflects the interrupt condition on the

port pins of any pin that is enabled for interrupts via the

GPINTEN register. A ‘set’ bit indicates that the

associated pin caused the interrupt.

This register is ‘read-only’. Writes to this register will be

ignored.

REGISTER 1-8:

INTF – INTERRUPT FLAG REGISTER (ADDR 0x07)

R-0

INT7

R-0

INT6

INT5

INT4

INT3

INT2

INT1

INT0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

INT7:INT0: These bits reflect the interrupt condition on the port. Will reflect the change only if interrupts

are enabled (GPINTEN) <7:0>.

1= Pin caused interrupt.

0= Interrupt not pending.

DS21952B-page 20

MCP23017/MCP23S17

1.6.9

INTERRUPT CAPTURE REGISTER

The INTCAP register captures the GPIO port value at

the time the interrupt occurred. The register is ‘read

only’ and is updated only when an interrupt occurs. The

register will remain unchanged until the interrupt is

cleared via a read of INTCAP or GPIO.

REGISTER 1-9:

INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)

R-x

ICP7

R-x

ICP6

ICP5

ICP4

ICP3

ICP2

ICP1

ICP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ICP7:ICP0: These bits reflect the logic level on the port pins at the time of interrupt due to pin change

<7:0>

1= Logic-high.

0= Logic-low.

DS21952B-page 21

MCP23017/MCP23S17

1.6.10

PORT REGISTER

The GPIO register reflects the value on the port.

Reading from this register reads the port. Writing to this

register modifies the Output Latch (OLAT) register.

REGISTER 1-10: GPIO – GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09)

R/W-0

GP7

R/W-0

GP6

R/W-0

GP5

R/W-0

GP4

R/W-0

GP3

R/W-0

GP2

R/W-0

GP1

R/W-0

GP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

GP7:GP0: These bits reflect the logic level on the pins <7:0>

1= Logic-high.

0= Logic-low.

DS21952B-page 22

MCP23017/MCP23S17

1.6.11

OUTPUT LATCH REGISTER (OLAT)

The OLAT register provides access to the output

latches. A read from this register results in a read of the

OLAT and not the port itself. A write to this register

modifies the output latches that modifies the pins

configured as outputs.

REGISTER 1-11: OLAT – OUTPUT LATCH REGISTER 0 (ADDR 0x0A)

R/W-0

OL7

R/W-0

OL6

R/W-0

OL5

R/W-0

OL4

R/W-0

OL3

R/W-0

OL2

R/W-0

OL1

R/W-0

OL0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

OL7:OL0: These bits reflect the logic level on the output latch <7:0>

1= Logic-high.

0= Logic-low.

DS21952B-page 23

MCP23017/MCP23S17

1.7.2

IOC FROM PIN CHANGE

1.7

Interrupt Logic

If enabled, the MCP23X17 will generate an interrupt if

a mismatch condition exists between the current port

value and the previous port value. Only IOC enabled

pins will be compared. Refer to Register 1-3 and

Register 1-5.

If enabled, the MCP23X17 activates the INTn interrupt

output when one of the port pins changes state or when

a pin does not match the preconfigured default. Each

pin is individually configurable as follows:

• Enable/disable interrupt via GPINTEN

• Can interrupt on either pin change or change from

default as configured in DEFVAL

1.7.3

IOC FROM REGISTER DEFAULT

If enabled, the MCP23X17 will generate an interrupt if

a mismatch occurs between the DEFVAL register and

the port. Only IOC enabled pins will be compared.

Refer to Register 1-3, Register 1-5 and Register 1-4.

Both conditions are referred to as Interrupt-on-Change

(IOC).

The interrupt control module uses the following

registers/bits:

1.7.4

INTERRUPT OPERATION

• IOCON.MIRROR – controls if the two interrupt

pins mirror each other

The INTn interrupt output can be configured as active-

low, active-high or open-drain via the IOCON register.

• GPINTEN – Interrupt enable register

Only those pins that are configured as an input (IODIR

register) with Interrupt-On-Change (IOC) enabled

(IOINTEN register) can cause an interrupt. Pins

defined as an output have no effect on the interrupt

output pin.

• INTCON – Controls the source for the IOC

• DEFVAL – Contains the register default for IOC

operation

1.7.1

INTA AND INTB

Input change activity on a port input pin that is enabled

for IOC will generate an internal device interrupt and

the device will capture the value of the port and copy it

into INTCAP. The interrupt will remain active until the

INTCAP or GPIO register is read. Writing to these

registers will not affect the interrupt. The interrupt

condition will be cleared after the LSb of the data is

clocked out during a read command of GPIO or

INTCAP.

There are two interrupt pins: INTA and INTB. By

default, INTA is associated with GPAn pins (PortA) and

INTB is associated with GPBn pins (PortB). Each port

has an independent signal which is cleared if its

associated GPIO or INTCAP register is read.

1.7.1.1

Mirroring the INT pins

Additionally, the INTn pins can be configured to mirror

each other so that any interrupt will cause both pins to

go active. This is controlled via IOCON.MIRROR.

The first interrupt event will cause the port contents to

be copied into the INTCAP register. Subsequent

interrupt conditions on the port will not cause an

interrupt to occur as long as the interrupt is not cleared

by a read of INTCAP or GPIO.

If IOCON.MIRROR = 0, the internal signals are routed

independently to the INTA and INTB pads.

If IOCON.MIRROR = 1, the internal signals are OR’ed

together and routed to the INTn pads. In this case, the

interrupt will only be cleared if the associated GPIO or

INTCAP is read (see Table 1-7).

Note:

The value in INTCAP can be lost if GPIO is

read before INTCAP while another IOC is

pending. After reading GPIO, the interrupt

will clear and then set due to the pending

IOC, causing the INTCAP register to

update.

TABLE 1-7:

INTERRUPT OPERATION

(IOCON.MIRROR = 1)

Interrupt

Condition

Read Portn * Interupt Result

PortA

PortB

PortA

PortB

PortA

PortB

Clear

GPIOA

GPIOB

Unchanged

Clear

Unchanged

Clear

GPIOA and

GPIOB

Both PortA and

PortB

* Port n = GPIOn or INTCAPn

DS21952B-page 24

MCP23017/MCP23S17

1.7.5

INTERRUPT CONDITIONS

FIGURE 1-7:

INTERRUPT-ON-CHANGE

FROM REGISTER

DEFAULT

There are two possible configurations that cause

interrupts (configured via INTCON):

1. Pins configured for interrupt-on-pin change

will cause an interrupt to occur if a pin changes

to the opposite state. The default state is reset

after an interrupt occurs and after clearing the

interrupt condition (i.e., after reading GPIO or

INTCAP). For example, an interrupt occurs by

an input changing from ‘1’ to ‘0’. The new initial

state for the pin is a logic 0after the interrupt is

cleared.

DEFVAL REGISTER

GP:

7

6

5

4

3

2

0

1

0

X

GP2

2. Pins configured for interrupt-on-change from

register value will cause an interrupt to occur if

the corresponding input pin differs from the

register bit. The interrupt condition will remain as

long as the condition exists, regardless if the

INTCAP or GPIO is read.

INT

ACTIVE

Port value

is captured

into INTCAP

Read GPIU

or INTCAP

See Figure 1-6 and Figure 1-7 for more information on

interrupt operations.

(INT clears only if interrupt

condition does not exist.)

FIGURE 1-6:

INTERRUPT-ON-PIN

CHANGE

GPx

INT

ACTIVE

Port value

is captured

into INTCAP

Read GPIO Port value

or INTCAP

is captured

into INTCAP

DS21952B-page 25

MCP23017/MCP23S17

NOTES:

DS21952B-page 26

MCP23017/MCP23S17

2.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature ...............................................................................................................................-65°C to +150°C

Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +5.5V

Voltage on all other pins with respect to VSS (except VDD)............................................................. -0.6V to (VDD + 0.6V)

Total power dissipation (Note) .............................................................................................................................700 mW

Maximum current out of VSS pin ...........................................................................................................................150 mA

Maximum current into VDD pin ..............................................................................................................................125 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA

Maximum output current sunk by any output pin ....................................................................................................25 mA

Maximum output current sourced by any output pin ...............................................................................................25 mA

Note:

Power dissipation is calculated as follows:

PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOL x IOL)

^†NOTE: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested

or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., out-

side specified power supply range) and therefore outside the warranted range.

DS21952B-page 27

MCP23017/MCP23S17

2.1

DC Characteristics

Operating Conditions (unless otherwise indicated):

1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp)

4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

DC Characteristics

Param

Typ

(Note 1(

Characteristic

Sym

Min

Max

Units

Conditions

No.

D001 Supply Voltage

VDD

1.8

—

5.5

—

V

D002 VDD Start Voltage to

Ensure Power-on

Reset

VPOR

VSS

D003 VDD Rise Rate to

Ensure Power-on

Reset

SVDD

0.05

—

V/ms Design guidance only.

Not tested.

D004 Supply Current

D005 Standby current

IDD

—

1

3

mA SCL/SCK = 1 MHz

µA

IDDS

µA

4.5V-5.5V @ +125°C

(Note 1)

Input Low Voltage

D030 A0, A1 (TTL buffer)

VIL

VIH

VSS

—

0.15 VDD

0.2 VDD

V

D031 CS, GPIO, SCL/SCK,

SDA, A2, RESET

(Schmitt Trigger)

Input High Voltage

D040 A0, A1

(TTL buffer)

0.25 VDD + 0.8

0.8 VDD

—

VDD

V

D041 CS, GPIO, SCL/SCK,

SDA, A2, RESET

For entire VDD range

(Schmitt Trigger)

Input Leakage Current

D060 I/O port pins

IIL

—

±1

µA

VSS ≤ VPIN ≤ VDD

Output Leakage Current

D065 I/O port pins

ILO

IPU

—

±1

µA

D070 GPIO weak pull-up

current

40

75

115

VDD = 5V, GP Pins = VSS

–40°C ≤ TA ≤ +85°C

Output Low-Voltage

D080 GPIO

VOL

—

0.6

0.8

V

IOL = 8.0 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V

IOL = 3.0 mA, VDD = 1.8V

IOL = 3.0 mA, VDD = 4.5V

INT

SO, SDA

SDA

Output High-Voltage

D090 GPIO, INT, SO

VOH

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V

IOH = -400 µA, VDD = 1.8V

Capacitive Loading Specs on Output Pins

D101 GPIO, SO, INT

D102 SDA

CIO

CB

—

50

pF

400

Note 1: This parameter is characterized, not 100% tested.

DS21952B-page 28

MCP23017/MCP23S17

FIGURE 2-1:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

VDD

1 kΩ

SCL and

SDA pin

50 pF

MCP23017

135 pF

FIGURE 2-2:

RESET AND DEVICE RESET TIMER TIMING

VDD

RESET

30

32

Internal

RESET

34

Output pin

DS21952B-page 29

MCP23017/MCP23S17

TABLE 2-1:

DEVICE RESET SPECIFICATIONS

Operating Conditions (unless otherwise indicated):

1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp)

4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

AC Characteristics

Param

Characteristic

Sym

Min

Typ⁽¹⁾

Max

Units

Conditions

No.

30

RESET Pulse Width

(Low)

TRSTL

1

—

µs

32

34

Device Active After Reset

high

THLD

TIOZ

—

0

—

1

ns

µs

VDD = 5.0V

Output High-Impedance

From RESET Low

—

Note 1: This parameter is characterized, not 100% tested.

2

FIGURE 2-3:

I C™ BUS START/STOP BITS TIMING

SCL

93

91

90

92

SDA

Stop

Condition

Start

Condition

2

FIGURE 2-4:

I C™ BUS DATA TIMING

103

100

102

92

101

109

SCL

90

106

91

107

SDA

In

110

109

SDA

Out

DS21952B-page 30

MCP23017/MCP23S17

2

TABLE 2-2:

I C™ BUS DATA REQUIREMENTS

Operating Conditions (unless otherwise indicated):

1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp)

4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

RPU (SCL, SDA) = 1 kΩ, CL (SCL, SDA) = 135 pF

I²C™ AC Characteristics

Param

No.

Characteristic

Sym

Min

Typ Max Units

Conditions

100

101

102

103

90

Clock High Time:

100 kHz mode

THIGH

4.0

0.6

—

µs 1.8V–5.5V (I-Temp)

µs 2.7V–5.5V (I-Temp)

µs 4.5V–5.5V (E-Temp)

400 kHz mode

1.7 MHz mode

0.12

Clock Low Time:

100 kHz mode

TLOW

4.7

1.3

—

µs 1.8V–5.5V (I-Temp)

µs 2.7V–5.5V (I-Temp)

µs 4.5V–5.5V (E-Temp)

400 kHz mode

1.7 MHz mode

0.32

SDA and SCL Rise Time:

100 kHz mode

TR

(Note 1)

—

20 + 0.1 CB

20

—

1000

300

ns 1.8V–5.5V (I-Temp)

ns 2.7V–5.5V (I-Temp)

ns 4.5V–5.5V (E-Temp)

(2)

400 kHz mode

1.7 MHz mode

160

SDA and SCL Fall Time:

100 kHz mode

TF

(Note 1)

—

20 + 0.1 CB

20

—

300

80

ns 1.8V–5.5V (I-Temp)

ns 2.7V–5.5V (I-Temp)

ns 4.5V–5.5V (E-Temp)

(2)

400 kHz mode

1.7 MHz mode

START Condition Setup Time: TSU:STA

100 kHz mode

4.7

0.6

—

µs 1.8V–5.5V (I-Temp)

µs 2.7V–5.5V (I-Temp)

µs 4.5V–5.5V (E-Temp)

400 kHz mode

1.7 MHz mode

0.16

91

START Condition Hold Time:

100 kHz mode

THD:STA

THD:DAT

TSU:DAT

TSU:STO

4.0

0.6

—

µs 1.8V–5.5V (I-Temp)

µs 2.7V–5.5V (I-Temp)

µs 4.5V–5.5V (E-Temp)

400 kHz mode

1.7 MHz mode

0.16

106

107

92

Data Input Hold Time:

100 kHz mode

0

—

3.45

0.9

µs 1.8V–5.5V (I-Temp)

µs 2.7V–5.5V (I-Temp)

µs 4.5V–5.5V (E-Temp)

400 kHz mode

1.7 MHz mode

0.15

Data Input Setup Time:

100 kHz mode

250

100

0.01

—

ns 1.8V–5.5V (I-Temp)

ns 2.7V–5.5V (I-Temp)

µs 4.5V–5.5V (E-Temp)

400 kHz mode

1.7 MHz mode

Stop Condition Setup Time:

100 kHz mode

4.0

0.6

—

µs 1.8V–5.5V (I-Temp)

µs 2.7V–5.5V (I-Temp)

µs 4.5V–5.5V (E-Temp)

400 kHz mode

1.7 MHz mode

0.16

Note 1: This parameter is characterized, not 100% tested.

2: CB is specified to be from 10 to 400 pF.

DS21952B-page 31

MCP23017/MCP23S17

2

TABLE 2-2:

I C™ BUS DATA REQUIREMENTS (CONTINUED)

Operating Conditions (unless otherwise indicated):

1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp)

4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

RPU (SCL, SDA) = 1 kΩ, CL (SCL, SDA) = 135 pF

I²C™ AC Characteristics

Param

No.

Characteristic

Sym

Min

Typ Max Units

Conditions

109

Output Valid From Clock:

100 kHz mode

TAA

—

3.45

0.9

µs 1.8V–5.5V (I-Temp)

µs 2.7V–5.5V (I-Temp)

µs 4.5V–5.5V (E-Temp)

400 kHz mode

1.7 MHz mode

0.18

110

Bus Free Time:

100 kHz mode

TBUF

4.7

1.3

—

µs 1.8V–5.5V (I-Temp)

µs 2.7V–5.5V (I-Temp)

µs 4.5V – 5.5V (E-Temp)

400 kHz mode

1.7 MHz mode

N/A

Bus Capacitive Loading:

100 kHz and 400 kHz

1.7 MHz

CB

—

400

100

pF Note 1

Input Filter Spike Suppression

(SDA and SCL)

TSP

100 kHz and 400 kHz

1.7 MHz

—

50

10

ns

ns Spike suppression off

Note 1: This parameter is characterized, not 100% tested.

2: CB is specified to be from 10 to 400 pF.

FIGURE 2-5:

SPI INPUT TIMING

3

CS

11

10

6

1

2

7

Mode 1,1

SCK

SI

Mode 0,0

4

5

MSB in

LSB in

High-Impedance

SO

DS21952B-page 32

MCP23017/MCP23S17

FIGURE 2-6:

SPI OUTPUT TIMING

CS

2

8

9

SCK

Mode 1,1

Mode 0,0

12

14

13

SO

SI

MSB out

LSB out

Don’t Care

TABLE 2-3:

SPI INTERFACE AC CHARACTERISTICS

Operating Conditions (unless otherwise indicated):

1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp)

SPI Interface AC Characteristics

4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

Param

Characteristic

No.

Sym

Min

Typ

Max

Units

Conditions

Clock Frequency

FCLK

—

5

MHz 1.8V–5.5V (I-Temp)

MHz 2.7V–5.5V (I-Temp)

MHz 4.5V–5.5V (E-Temp)

ns

10

—

2

—

1

2

CS Setup Time

CS Hold Time

TCSS

TCSH

50

100

50

100

50

20

10

20

10

—

ns

µs

ns

1.8V–5.5V (I-Temp)

2.7V–5.5V (I-Temp)

4.5V–5.5V (E-Temp)

1.8V–5.5V (I-Temp)

2.7V–5.5V (I-Temp)

4.5V–5.5V (E-Temp)

1.8V–5.5V (I-Temp)

2.7V–5.5V (I-Temp)

4.5V–5.5V (E-Temp)

1.8V–5.5V (I-Temp)

2.7V–5.5V (I-Temp)

4.5V–5.5V (E-Temp)

Note 1

3

4

5

CS Disable Time

Data Setup Time

Data Hold Time

TCSD

TSU

THD

6

7

8

CLK Rise Time

CLK Fall Time

Clock High Time

TR

TF

—

2

Note 1

THI

90

45

—

1.8V–5.5V (I-Temp)

2.7V–5.5V (I-Temp)

4.5V–5.5V (E-Temp)

Note 1: This parameter is characterized, not 100% tested.

DS21952B-page 33

MCP23017/MCP23S17

TABLE 2-3:

SPI INTERFACE AC CHARACTERISTICS (CONTINUED)

Operating Conditions (unless otherwise indicated):

1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp)

SPI Interface AC Characteristics

4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

Param

Characteristic

No.

Sym

Min

Typ

Max

Units

Conditions

9

Clock Low Time

TLO

90

45

50

—

0

—

ns

1.8V–5.5V (I-Temp)

2.7V–5.5V (I-Temp)

4.5V–5.5V (E-Temp)

—

10

11

12

Clock Delay Time

TCLD

TCLE

TV

—

Clock Enable Time

—

Output Valid from Clock Low

90

45

—

1.8V–5.5V (I-Temp)

2.7V–5.5V (I-Temp)

4.5V–5.5V (E-Temp)

13

14

Output Hold Time

THO

TDIS

Output Disable Time

—

100

Note 1: This parameter is characterized, not 100% tested.

FIGURE 2-7:

GPIO AND INT TIMING

SCL/SCK

SDA/SI

In

D1

D0

LSb of data byte zero

during a write or read

command, depending

on parameter

50

GPn

Output

51

INT

Inactive

53

INT Pin Active

GPn

Input

52

Register

Loaded

DS21952B-page 34

MCP23017/MCP23S17

TABLE 2-4:

GP AND INT PINS

Operating Conditions (unless otherwise indicated):

AC Characteristics

Param

1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp)

4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1)

Characteristic

Sym

Min

Typ

Max Units

Conditions

No.

50

51

52

Serial Data to Output Valid

Interrupt Pin Disable Time

TGPOV

TINTD

TGPIV

—

500

600

450

ns

GP Input Change to

Register Valid

53

IOC Event to INT Active

Glitch Filter on GP Pins

TGPINT

—

600

150

ns

TGLITCH

Note 1

Note 1: This parameter is characterized, not 100% tested

DS21952B-page 35

MCP23017/MCP23S17

NOTES:

DS21952B-page 36

MCP23017/MCP23S17

3.0

3.1

PACKAGING INFORMATION

Package Marking Information

28-Lead PDIP (Skinny DIP)

Example:

XXXXXXXXXXXXXXXXX

e

3

MCP23017-E/SP^^

0648256

YYWWNN

28-Lead QFN

Example:

XXXXXXXX

YYWWNNN

23017

e

3

E/ML^^

0648256

28-Lead SOIC

Example:

XXXXXXXXXXXXXXXXX

e

3

MCP23017-E/SO^^

0648256

YYWWNNN

28-Lead SSOP

Example:

MCP23017

E/SS^^

XXXXXXXXXXXX

e

3

0648256

YYWWNNN

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21952B-page 37

MCP23017/MCP23S17

28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

1

2 3

D

E

A2

A

L

c

b1

A1

b

e

eB

Units

INCHES

NOM

28

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.200

.150

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.120

.015

.290

.240

1.345

.110

.008

.040

.014

–

.135

–

.310

.285

1.365

.130

.010

.050

.018

–

.335

.295

1.400

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-070B

DS21952B-page 38

MCP23017/MCP23S17

28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]

with 0.55 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

D2

EXPOSED

PAD

e

E

b

E2

2

1

2

1

K

N

NOTE 1

L

BOTTOM VIEW

TOP VIEW

A

A3

A1

Units

MILLIMETERS

NOM

Dimension Limits

MIN

MAX

Number of Pins

N

e

28

Pitch

0.65 BSC

0.90

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

E

0.02

Contact Thickness

Overall Width

0.20 REF

6.00 BSC

3.70

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

E2

D

3.65

4.20

6.00 BSC

3.70

D2

b

3.65

0.23

0.50

0.20

4.20

0.35

0.70

–

0.30

L

0.55

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-105B

DS21952B-page 39

MCP23017/MCP23S17

28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

b

h

α

h

c

φ

A2

A

L

A1

L1

β

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

28

1.27 BSC

Overall Height

A

–

2.65

–

Molded Package Thickness

Standoff §

A2

A1

E

2.05

0.10

–

0.30

Overall Width

10.30 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

7.50 BSC

17.90 BSC

0.25

0.40

–

0.75

1.27

L

–

Footprint

L1

φ

1.40 REF

Foot Angle Top

Lead Thickness

Lead Width

0°

0.18

0.31

5°

–

8°

c

0.33

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-052B

DS21952B-page 40

MCP23017/MCP23S17

28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

1

2

b

NOTE 1

e

c

A2

A

φ

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

28

0.65 BSC

Overall Height

Molded Package Thickness

Standoff

A

–

1.75

–

2.00

1.85

–

A2

A1

E

1.65

0.05

7.40

5.00

9.90

0.55

Overall Width

Molded Package Width

Overall Length

Foot Length

7.80

5.30

10.20

0.75

1.25 REF

–

8.20

5.60

10.50

0.95

E1

D

L

Footprint

L1

c

Lead Thickness

Foot Angle

0.09

0°

0.25

8°

φ

4°

Lead Width

b

0.22

–

0.38

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-073B

DS21952B-page 41

MCP23017/MCP23S17

NOTES:

DS21952B-page 42

MCP23017/MCP23S17

APPENDIX A: REVISION HISTORY

Revision B (February 2007)

1. Changed Byte and Sequential Read in

Figure 1-1 from “R” to “W”.

2. Table 2-4, Param No. 51 and 53: Changed from

450 to 600 and 500 to 600, respecively.

3. Added disclaimers to package outline drawings.

4. Updated package outline drawings.

Revision A (June 2005)

• Original Release of this Document.

DS21952B-page 39

MCP23017/MCP23S17

NOTES:

DS21952B-page 40

MCP23017/MCP23S17

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

–

PART NO.

Device

X

/XX

a) MCP23017-E/SP: Extended Temp.,

28LD PDIP package.

Temperature

Range

Package

b) MCP23017-E/SO: Extended Temp.,

28LD SOIC package.

16-Bit I/O Expander w/I²C™ Interface

c) MCP23017T-E/SO: Tape and Reel,

Extended Temp.,

Device

MCP23017:

MCP23017T: 16-Bit I/O Expander w/I²C Interface

(Tape and Reel)

28LD SOIC package.

d) MCP23017-E/SS: Extended Temp.,

28LD SSOP package.

MCP23S17:

16-Bit I/O Expander w/SPI Interface

MCP23S17T: 16-Bit I/O Expander w/SPI Interface

(Tape and Reel)

e) MCP23017T-E/SS: Tape and Reel,

Extended Temp.,

28LD SSOP package.

Temperature

Range

a) MCP23S17-E/SP: Extended Temp.,

28LD PDIP package.

E

=

-40°C to +125°C (Extended)

b) MCP23S17-E/SO: Extended Temp.,

28LD SOIC package.

Package

ML

SP

SO

SS

=

Plastic Quad, Flat No Leads (QFN), 28-lead

Plastic DIP (300 mil Body), 28-Lead

Plastic SOIC (300 mil Body), 28-Lead

SSOP, (209 mil Body, 5.30 mm), 28-Lead

c) MCP23S17T-E/SO: Tape and Reel,

Extended Temp.,

28LD SOIC package.

d) MCP23S17-E/SS: Extended Temp.,

28LD SSOP package.

e) MCP23S17T-E/SS: Tape and Reel,

Extended Temp.,

28LD SSOP package.

DS21952B-page 41

MCP23017/MCP23S17

NOTES:

DS21952B-page 42

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and

SmartShunt are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC^®DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS21952B-page 43

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS21952B-page 44


型号：	MCP23S17T-E/ML
厂家：	MICROCHIP
描述：	16-Bit I/O Expander with Serial Interface 16位I / O扩展器，串行接口
文件：	总48页 (文件大小：914K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP23S17T-E/ML [MICROCHIP]

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