MCP25020TI/P_技术文档

MCP2502X/5X

CAN I/O Expander Family

Features

Description

• Implements CAN V2.0B

The MCP2502X/5X devices operate as I/O expanders

for

a Controller Area Network (CAN) system,

- Programmable bit rate up to 1 Mb/s

- One programmable mask

- Two programmable filters

- Three auto-transmit buffers

- Two message reception buffers

supporting CAN V2.0B active, with bus rates up to

1 Mb/s. The MCP2502X/5X allows a simple CAN node

to be implemented without the need for

microcontroller.

a

The devices are identical, with the following

exceptions:

- Does not require synchronization or

configuration messages

• Hardware Features

One Wire

- Non-volatile memory for user configuration

Device

A/D

Digital

CANbus

- User configuration automatically loaded on

power-up

MCP25020

MCP25025

MCP25050

MCP25055

No

Yes

No

- Eight general-purpose I/O lines individually

selectable as inputs or outputs

Yes

- Individually selectable transmit-on-pin-

change for each input

Yes

The MCP2502X/5X devices feature a number of

peripherals, including digital I/Os, four-channel 10-bit

A/D (MCP2505X) and PWM outputs with automatic

message transmission on change-of-input state. This

includes an analog input exceeding a preset threshold.

- Four 10-bit, analog input channels with

programmable conversion clock and VREF

sources (MCP2505X devices only)

- Message scheduling capability

- Two 10-bit PWM outputs with independently

programmable frequencies

One mask and two acceptance filters are provided to

give maximum flexibility during system design with

respect to identifiers that the device will respond to.

The device can also be configured to automatically

transmit a unique message whenever any of several

error conditions occur.

- Device configuration can be modified via

CAN bus messages

- In-Circuit Serial Programming™ (ICSP™) of

default configuration memory

- Optional 1-wire CAN bus operation

• Low-power CMOS technology

- Operates from 2.7V to 5.5V

The device is pre-programmed in non-volatile memory

so that the part defaults to a specific configuration at

power-up.

- 10 mA active current, typical

- 30 µA standby current (CAN Sleep mode)

• 14-pin PDIP (300 mil) and SOIC (150 mil)

packages

• Available temperature ranges:

- Industrial (I): -40°C to +85°C

- Extended (E): -40°C to +125°C

DS21664D-page 1

MCP2502X/5X

Threshold Detection - refers to the MCP2502X/5X’s

ability to automatically transmit a message when a

predefined analog threshold is reached.

Package Types

PDIP/SOIC

VDD

GP0/AN0

1

14

2

3

4

5

13

12

11

10

9

TXCAN/TXRXCAN*

RXCAN/NC*

GP1/AN1

GP2/AN2/PWM1

GP3/AN3/PWM2

GP4/VREF-

GP7/RST/VPP

GP6/CLKOUT

OSC2

6

7

GP5/VREF+

VSS

8

OSC1/CLKIN

* One-wire option available on MCP250X5 devices.

Definition of Terms

The following terms are used throughout this

document:

I/O Expander - refers to the integrated circuit (IC)

device being described (MCP2502X/5X).

Input Message - term given to messages that are

received by the MCP2502X/5X and cause the internal

registers to be modified. Once the register modification

has been performed, the MCP2502X/5X transmits a

Command Acknowledge message to indicate that the

command was received and processed.

Command Acknowledge Message - term given to the

message that is automatically transmitted by the

MCP2502X/5X after receiving and processing an input

message.

Information Request Message - term given to

Remote Request messages that are received by the

MCP2502X/5X that subsequently generate an output

message (data frame) in response.

Output Message - term given to the message that the

MCP2502X/5X sends in response to an Information

Request message.

On Bus Message - term given to the message that the

MCP2502X/5X transmits after completing the power-on/

self-configuration sequence at timed intervals, if

enabled.

Self-Configuration - term used to describe the

process of transferring the contents of the EPROM

memory array to the SRAM memory array.

On Bus - term used to describe the condition when the

MCP2502X/5X is fully-configured and ready to

transmit, or receive, on the bus. This is the only state in

which the MCP2502X/5X can transmit on the bus.

Edge Detection - refers to the MCP2502X/5X’s ability

to automatically transmit a message based upon the

occurance of a predefined edge on any digital input.

DS21664D-page 2

MCP2502X/5X

Figure 1-1 is the block diagram of the MCP2502X/5X

and Table 1-1 is the pinout description.

1.0

DEVICE OVERVIEW

This document contains device-specific information on

the MCP2502X/5X family of CAN I/O expanders. The

CAN protocol is not discussed in depth in this

document. Additional information on the CAN protocol

can be found in the CAN specification, as defined by

Robert Bosch GmbH.

The following sections detail the modules as listed in

Figure 1-1.

FIGURE 1-1:

MCP2502X/5X BLOCK DIAGRAM

GPIO

GP0/AN0

GP1/AN1

GP2/AN2/PWM1

GP3/AN3/PWM2

GP4/VREF-

GP5/VREF+

User

Memory

GP6/CLKOUT

GP7RST/VPP

State Machine

and

Control Logic

TXCAN/

TXRXCAN

OSC1/CLKIN

OSC2/CLKOUT

CAN

Protocol

Timing

Generation

Engine

RXCAN

*

A/D

PWM2

PWM1

* Only the MCP2505X devices have the A/D module.

TABLE 1-1:

PINOUT DESCRIPTION

Name

Number

Standard

Function

Alternate

Function

Programming

Mode Function

GP0/AN0 *

1

2

Bidirectional I/O pin, TTL input buffer

Ground

Analog input channel

Analog input/PWM output

External VREF-

None

Data

GP1/AN1 *

GP2/AN2/PWM2 *

GP3/AN3/PWM3 *

GP4/VREF-

3

4

5

GP5/VREF+

VSS

6

External VREF input

None

Clock

Ground

None

Vpp

7

OSC1/CLKIN

OSC2

8

External oscillator input

External clock input

None

9

External oscillator output

GP6/CLKOUT

GP7/RST/VPP

RXCAN

10

11

12

13

Bidirectional I/O pin, TTL input buffer

Input pin, TTL input buffer

CLKOUT output

External Reset input

Not connected for 1-wire

CAN data receive input

None

TXCAN/TXRXCAN

CAN data transmit output

CAN TX and RX for 1-wire

operation (MCP250X5)

VDD

14

Power

None

Power

* Only the MCP2505X devices have the A/D module.

DS21664D-page 3

MCP2502X/5X

NOTES:

DS21664D-page 4

MCP2502X/5X

• One full-acceptance mask (standard and

extended)

2.0

CAN MODULE

The CAN module is a protocol controller that converts

between raw digital data and CAN message packets.

The main functional block of the CAN module is shown

in Figure 2-1 and consists of:

• Two full-acceptance filters (standard and

extended)

• One filter for each receive buffer

• Three prioritized transmit buffers for transmitting

predefined message types

• CAN protocol engine

• Buffers, masks and filters

• Automatic wake-up on bus traffic function

The module features include:

• Error management logic for transmit and receive

error states

• Implementation of the CAN protocol

• Low-power SLEEP mode

• Double-buffered receiver with two separate

receive buffers

FIGURE 2-1:

BUFFERS

CAN MODULE

TXB0

TXB1

TXB2

A

Acceptance Mask

RXM

c

e

p

t

c

e

p

t

Acceptance Filter

RXF1

RXF0

R

X

B

0

R

X

B

1

M

A

B

Message

Queue

Control

Identifier

Transmit Byte Sequencer

Data Field

Receive

Error

Counter

REC

TEC

PROTOCOL

ENGINE

Transmit

Error

Counter

ErrPas

BusOff

Transmit<7:0>

Receive<7:0>

Shift<14:0>

{Transmit<5:0>, Receive<8:0>}

Comparator

Protocol

Finite

State

CRC<14:0>

Machine

Bit

Timing

Logic

Transmit

Logic

Clock

Generator

TXCAN/TXRXCAN

RXCAN

Configuration

Registers

DS21664D-page 5

MCP2502X/5X

2.1

CAN Protocol Finite State Machine

2.3

Error Management Logic

The heart of the engine is the Finite State Machine

(FSM). This state machine sequences through

messages on a bit-by-bit basis, changing states as the

fields of the various frame types are transmitted or

received. The FSM is a sequencer controlling the

sequential data stream between the TX/RX Shift

register, the CRC register and the bus line. The FSM

also controls the Error Management Logic (EML) and

the parallel data stream between the TX/RX Shift

registers and the buffers. The FSM insures that the pro-

cesses of reception, arbitration, transmission and error

signaling are performed according to the CAN protocol.

The automatic retransmission of messages on the bus

line is also handled.

The error management logic is responsible for the fault

confinement of the CAN device. Its two counters (the

Receive Error Counter (REC) and the Transmit Error

Counter (TEC)) are incremented and decremented by

commands from the Bit Stream processor. According to

the values of the error counters, the MCP2502X/5X is

set into the states error-active, error-passive or bus-off.

Error-active: Both error counters are below the error-

passive limit of 128.

Error-passive: At least one of the error counters (TEC

or REC) equals or exceeds 128.

Bus-off: The transmit error counter (TEC) equals or

exceeds the bus-off limit of 256. The device remains in

this state until the bus-off recovery sequence is

received. The bus-off recovery sequence consists of

128 occurrences of 11 consecutive recessive bits.

2.2

Cyclic Redundancy Check (CRC)

The Cyclic Redundancy Check register generates the

Cyclic Redundancy Check (CRC) code that is

transmitted after either the Control field (for messages

with 0 data bytes) or the Data field and is used to check

the CRC field of incoming messages.

Note: The MCP2502X/5X, after going bus-off,

will recover back to error-active

automatically if the bus remains idle for

128 x 11 bits. OPTREG2.ERRE must be

set to force the MCP2502X/5X to enter

Listen-only mode instead of Normal mode

during bus recovery. The current error

mode (except for bus-off) of the

MCP2502X/5X can be determined by

reading the EFLG register via the Read

CAN error message.

FIGURE 2-2:

ERROR MODES STATE DIAGRAM

RESET

Error-Active

REC < 127 or

TEC < 127

128 occurrences of

11 consecutive

“recessive” bits

REC > 127 or

TEC > 127

Error-Passive

TEC > 255

Bus-Off

DS21664D-page 6

MCP2502X/5X

REGISTER 2-1:

TEC - TRANSMITTER ERROR COUNTER

R-0

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

bit 7

bit 0

bit 7-0

TEC7:TEC0: Transmit Error Counter bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 2-2:

REC - RECEIVER ERROR COUNTER

R-0

REC7

REC6

REC5

REC4

REC3

REC2

REC1

REC0

bit 7

bit 0

bit 7-0

REC7:REC0: Receive Error Counter bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

FIGURE 2-3:

BIT TIME PARTITIONING

Input Signal

Prop

Segment

Phase

Segment 1

Phase

Segment 2

Sync

Sample Point

TQ

nominal bit time is calculated by programming the TQ

length and the number of TQ in each time segment, as

discussed below.

2.4

Bit Timing Logic

The Bit Timing Logic (BTL) monitors the bus line input

and handles the bus-related bit timing based on the

CAN protocol. The BTL synchronizes on a recessive-

to-dominant bus transition at Start-of-Frame (hard

synchronization) and on any further recessive-to-

dominant bus line transition if the CAN controller itself

does not transmit a dominant bit (resynchronization).

The BTL also provides programmable time segments

to compensate for the propagation delay time, phase

shifts and to define the position of the sample point

within the bit time. These programmable segments are

made up of integer units called Time Quanta (TQ). The

2.4.1

TIME QUANTUM (TQ)

Time Quantum is a fixed unit of time derived from the

oscillator period. There is a programmable baud rate

prescaler (BRP) (with integral values ranging from 1 to

64) as well as a fixed division by two for clock

generation.

DS21664D-page 7

MCP2502X/5X

The base TQ is defined as twice the oscillator period.

Adding the BRP into the equation yields:

2.4.2.3

Phase Buffer Segments

The Phase Buffer Segments are used to optimally

locate the sampling point of the received bit within the

nominal bit time. The sampling point occurs between

PS1 and PS2. These segments can be automatically

lengthened or shortened by the resynchronization

process. Thus, the variation of the values of the phase

buffer segments represent the DPLL functionality.

T_Q= 2*T_OSC*(BRP + 1)

where BRP = binary value represented by

CNF1.BRP<5:0>

By definition, the nominal bit time is programmable

from a minimum of 8 TQ to 25 TQ. Also, the minimum

nominal bit time is 1 µs, which corresponds to 1 Mb/s.

Phase Segment 1 (PS1): The end of PS1 determines

the sampling point within a bit time. PS1 is programma-

ble from 1 TQ - 8 TQ in duration.

2.4.2

TIME SEGMENTS

Phase Segment 2 (PS2): PS2 provides delay before

the next transmitted data transition and is also pro-

grammable from 1 TQ - 8 TQ in duration. However, due

to IPT requirements, the actual minimum length of

phase segment 2 is 2 TQ. It may also be defined to be

equal to the greater of PS1 or the information process-

ing time (IPT).

Time segments make up the nominal bit time. The

nominal bit time can be thought of as being divided into

separate non-overlapping time segments. These

segments are shown in Figure 2-3.

• Synchronization Segment (SyncSeg)

• Propagation Segment (PropSeg)

• Phase Buffer Segment 1 (PS1)

• Phase Buffer Segment 2 (PS2)

2.4.3

SAMPLE POINT

The sample point is the point of time at which the bus

level is read and the value of the received bit is

determined. The sampling point occurs at the end of

PS1. If desired, it is possible to specify multiple

sampling of the bus line at the sample point. The value

of the received bit is determined to be the value of the

majority decision of three values. The three samples

are taken at the sample point, and twice before, with a

time of TQ/2 between each sample.

Nominal Bit Time = T_Q*(Sync_Seg + PropSeg

+ Phase_Seg1 + Phase_Seg2)

Rules for Programming the Segments

There are a few rules to follow when programming the

time segments:

• PropSeg + PS1 ≥ PS2

• PS2 > Sync Jump Width

• PS2 ≥ Information Processing Time

2.4.4

INFORMATION PROCESSING TIME

The Information Processing Time (IPT) is the time

segment (starting at the sample point) that is reserved

for calculation of the subsequent bit level. The CAN

specification defines this time to be less than or equal

to 2 TQ. The MCP2502X/5X defines this time to be

2 TQ. Thus, PS2 must be at least 2 TQ long.

2.4.2.1

Synchronization Segment

This part of the bit time is used to synchronize the

various CAN nodes on the bus. The edge of the input

signal is expected to occur during the SyncSeg. The

duration is fixed at 1 TQ.

2.4.2.2

Propagation Segment

2.4.5

SYNCHRONIZATION JUMP WIDTH

This part of the bit time is used to compensate for

physical delay times within the network. These delay

times consist of the signal propagation time on the bus

line and the internal delay time of the nodes. The delay

is calculated as being the round-trip time from

transmitter to receiver (twice the signal's propagation

time on the bus line), the input comparator delay and

the output driver delay. The length of the Propagation

Segment can be programmed from 1 TQ to 8 TQ by

setting the PRSEG2:PRSEG0 bits of the CNF2

register.

To compensate for phase shifts and oscillator

tolerances between the nodes in the system, each

CAN controller must be able to synchronize to the

relevant signal edge of the incoming signal. When a

recessive-to-dominant edge in the transmitted data is

detected, the logic will compare the location of the edge

to the expected time (SyncSeg). The circuit will then

adjust the values of PS1 and PS2, as necessary, using

the programmed Synchronization Jump Width (SJW).

This adjustment is made for resynchronization during a

message and not hard synchronization, which occurs

only at the message Start-of-Frame (SOF).

DS21664D-page 8

MCP2502X/5X

As a result of resynchronization, PS1 may be

lengthened or PS2 may be shortened. The amount of

lengthening or shortening of the phase buffer segments

has an upper-bound given by the SJW. The SJW is

programmable between 1 TQ and 4 TQ. The value of

the SJW will be added to PS1 (or subtracted from PS2)

depending on the phase error (e) of the edge in relation

to the receiver’s SyncSeg. The phase error is defined

as follows:

2.4.6.2

CNF2

The PRSEG<2:0> bits set the length (in TQ’s) of the

propagation segment. The PS1<2:0> bits set the length

(in TQ’s) of phase segment 1. The SAM bit controls how

many times the RXCAN pin is sampled. Setting this bit

to a ‘1’ causes the bus to be sampled three times.

Twice at TQ/2 before the sample point and once at the

normal sample point (which is at the end of PS1). The

value of the bus is determined to be the value read

during at least two of the samples. If the SAM bit is set

to a ‘0’, the RXCAN pin is sampled only once at the

sample point. The BTLMODE bit controls how the

length of PS2 is determined. If this bit is set to a ‘1’, the

length of PS2 is determined by the PS2<2:0> bits of

CNF3. If the BTLMODE bit is set to a ‘0’ then the length

of PS2 is the greater of PS1 and the information

processing time (which is fixed at 2 TQ for the

MCP2502X/5X).

• e = 0 if the edge lies within SYNCESEG

- No resynchronization is required.

• e > 0 if the edge lies before the sample point

- PS1 will be lengthened by the amount of the

SJW.

• e < 0 if the edge lies after the sample point of the

previous bit and before the SyncSeg of the

current bit

- PS2 will be shortened by the amount of the

SJW.

2.4.6.3

CNF3

The PS2<2:0> bits set the length, in TQ’s, of PS2, if the

CNF2.BTLMODE bit is set to a ‘1’. If the BTLMODE bit

is set to a ‘0’, the PS2<2:0> bits have no effect.

2.4.6

CONFIGURATION REGISTERS

There are three registers (in the configuration register

module) associated with the CAN bit timing logic that

controls the bit timing for the CAN bus interface.

Additionally, the wake-up filter (CNF3.WAKFIL) is

implemented in the CNF3 register. This filter is a low-

pass filter that can be used to prevent the MCP2502X/

5X from waking up due to short glitches on the CAN

bus.

2.4.6.1

CNF1

The BRP<5:0> bits control the baud rate prescaler.

These bits set the length of TQ relative to the OSC1

input frequency, with the minimum length of TQ being

2 TOSC in length (when BRP<5:0> are set to 000000).

The SJW<1:0> bits select the synchronization jump

width in terms of number of TQ’s.

REGISTER 2-3:

CNF1 - CAN CONFIGURATION REGISTER 1

R/W-0

SJW1

R/W-0

SJW0

R/W-0

BRP5

R/W-0

BRP4

R/W-0

BRP3

R/W-0

BRP2

R/W-0

BRP1

R/W-0

BRP0

bit 7

bit 0

bit 7-6

bit 5-0

SJW1:SJW0: Synchronized Jump Width bits

11= Length = 4 x TQ

10= Length = 3 x TQ

01= Length = 2 x TQ

00= Length = 1 x TQ

BRP5:BRP0: Baud Rate Prescaler bits

111111=TQ = 2 x 64 x 1/FOSC

-

000000=TQ = 2 x 1 x 1/FOSC

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 9

MCP2502X/5X

REGISTER 2-4:

CNF2 - CAN CONFIGURATION REGISTER 2

R/W-0

SAM

R/W-0

PRSEG0

bit 0

BTLMODE

bit 7

PHSEG12 PHSEG11

PHSEG10

PRSEG2 PRSEG1

bit 7

BTL MODE: Length determination of PHSEG2 bit

1= Length of Phase_Seg2 determined by bits 2:0 of CNF3

0= Length of Phase_Seg2 is the greater of Phase_Seg1 or IPT(2Tq)

bit 6

SAM: Sample of the CAN bus line bit

1= Bus line is sampled three times at the sample point

0= Bus line is sampled once at the sample point

bit 5-3

PHSEG12:PHSEG10: Phase Buffer Segment1 bits

111= length = 8 x TQ

-

000= length = 1 x TQ

bit 2-0

PRSEG2:PRSEG0: Propagation Time Segment bits

111= length = 8 x TQ

-

000= length = 1 x TΘ

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 2-5:

CNF3 - CAN CONFIGURATION REGISTER 3

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

WAKFIL

PHSEG22 PHSEG21 PHSEG20

bit 0

bit 7

bit 6

Unimplemented: (Reads as 0)

WAKFIL: Wake-up filter bit

1= Wake-up filter enabled

0= Wake-up filter disabled

bit 5-3

bit 2-0

Unimplemented: (Reads as 0)

PHSEG22:PHSEG20: Phase Buffer Segment2 bits

111= length = 8 x TQ

-

001= length = 2 x TQ

000= Invalid

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 10

MCP2502X/5X

Command Acknowledge: TXID1 sends a Command

Acknowledge message when the MCP2502X/5X

receives an Input Message and processes the

instruction (and OPTREG2.CAEN = 1). This message

is used as a hand shake for the node requesting the

modification of the MCP2502X/5X. There is no data

associated with this message.

2.5

Buffers, Masks, and Filters

This part of the CAN module supports the transmitting,

receiving and acceptance of CAN messages.

Three transmit buffers are used for the three transmit

message IDs, as discussed later in this section. Two

receive buffers store the CAN message’s arbitration

field, control field and the data field.

Receive Overflow: TXID1 sends a Receive Overflow

message if there is a Receive Overflow condition (and

OPTREG2.CAEN = 0). This only occurs if the device

has received a valid message before processing the

previous valid message from the same receive buffer.

There is no data associated with this message.

One mask defines which bits are to be applied to either

filter. The mask can be regarded as defining “don’t

care” bits for the filter.

Each of the two filters define a bit pattern that will be

compared to all incoming messages. All filter bits that

have not been defined as “don’t care” by the mask are

applied to the message.

Error Condition: An Error Condition message is

transmitted if the TEC or REC counters reach error

warning (> 95) or error passive (> 127). This message

contains the TXID1 identifier and the TEC, REC and

EFLG counters.

2.5.1

TRANSMIT MESSAGE ID’S

The MCP2502X/5X device contains three separate

transmit message ID’s: TXID0, TXID1 and TXID2. The

data length code is predefined for each of the various

output messages, with the data that is transmitted

coming directly from the contents of the device’s

peripheral registers.

A hysteresis is implemented in hardware that prevents

messages from repeatedly being transmitted due to

error counts changing by one or two bits. Once a

message is sent for an error warning (TEC or REC >

95), the message will not trigger again until the error

counter ≤ 79 and back to > 95 (hysteresis = 17 counts).

Similarly, an error passive message is sent at TEC or

REC > 127 and is not sent again until the error counter

≤ 111 and back to >127 (hysteresis = 17 counts).

2.5.1.1

Transmit Message ID0 (TXID0)

TXID0 contains the identifier that is used when trans-

mitting the On Bus message. If enabled

(STCON.STEN = 1), the On Bus message will be

transmitted at predefined intervals. Depending on the

message-select bit (STCON.STMS = 1), the CAN

message will send GPIO and A/D data.

2.5.1.3

Transmit Message ID2 (TXID2)

Transmit ID2 contains the identifier that is used when

transmitting auto-conversion-initiated messages,

including digital input edge detection and/or analog

input exceeding a threshold. This message will also be

sent when the device wakes up from sleep due to a

digital input change-of-state condition (i.e., change-of-

state occurs on input configured to transmit on

change-of-state).

Transmit Message ID0 will not automatically be sent

when the device is brought out of sleep.

2.5.1.2

Transmit Message ID1 (TXID1)

TXID1 contains the identifier that is used when the

MCP2502X/5X sends the Command Acknowledge

message, the Receive Overflow message and/or the

Error Condition message. All message types use the

same identifier.

2.6

Receive Buffers

The MCP2505X contains two receive buffers, each

with their own filter. There is also a Message Assembly

Buffer (MAB) that acts as a third receive buffer (see

Figure 2-1).

The CAEN bit, in the OPTREG2 register, selects

between the Command Acknowledge and Receive

Overflow operation. These message types have a DLC

of 0and do not contain any data. The Error Condition

message can occur anytime, has a DLC of 3 and

contains the EFLG, TEC and REC data values.

The two receive buffers, combined with the MAB help,

insure that received messages will be processed while

minimizing the chances of receive buffer overrun due to

maximum bus loading of messages destined for the

MCP2502X/5X.

Note: A zero data length On Bus message will be

transmitted

once

after

power-up,

regardless of scheduled transmission-

enable status.

Note: The receive buffers are used by the

MCP2502X/5X to implement the command

messages and are not externally

accessible.

DS21664D-page 11

MCP2502X/5X

Message with an extended ID - the three least

significant bits of the standard identifier

(RXMSIDL.SID2:SID0) are configurable and the three

least significant bits of the extended identifier

(RXMEID0.EID2:EID0) are always ‘don’t cares’ and

effectively becomes ‘0’.

2.7

Acceptance Mask

The acceptance mask is used to define which bits in the

CAN ID are to be compared against the programmable

filters. Individual bits within the mask correspond to bits

in the CAN ID that, in turn, correspond to bits in the

acceptance filters. Any bit in the mask that is set to a ‘1’

will cause the corresponding CAN ID bit to be

compared against the associated filter bit. Any bit in the

mask that is set to a ‘0’ is not compared and effectively

sets the associated CAN ID bit to ‘don’t care’.

Note: The EXIDE bit in the Mask register

(RXMSIDL) can be used to mask the IDE

bit in the corresponding Receive buffer

register (RXBnSIDL).

2.7.1

MASKS AND STANDARD/

EXTENDED IDS

2.8

Acceptance Filters

There are two separate acceptance filters defined for

the MCP2502X/5X: RXF0 and RXF1. RXF0 is used for

Information Request messages and RXF1 is used for

input messages (see Table 4-2 and Table 4-3). Each bit

in the filters corresponds to a bit in the CAN ID. Every

bit in the CAN ID, for which the corresponding Mask bit

is set, must match the associated filter bit in order for

the message to be accepted. Messages that fail to

meet the mask/fIlter criteria are ignored.

To insure proper operation of the information request

and input messages, some mask bits (as configured in

the mask registers) may be ignored as explained:

Message with a standard ID - the three least

significant

bits

of

a

standard

identifier

(RXMSIDL.SID2:SID0) are ‘don’t care’ for the mask

registers and effectively become ‘0’.

REGISTER 2-6:

TXIDNSIDH - TRANSMIT IDENTIFIER N STANDARD IDENTIFIER HIGH

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 12

MCP2502X/5X

REGISTER 2-7:

TXIDNSIDL - TRANSMIT IDENTIFIER N STANDARD IDENTIFIER LOW

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

R/W-x

EXIDE

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

bit 4

SID2:SID0: Standard Identifier bits

Unimplemented: Read as '0’

bit 3

EXIDE: Extended Identifier Enable bit

1= Message will transmit extended identifier

0= Message will transmit standard identifier

bit 2

Unimplemented: Read as '0’

bit 1-0

EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 2-8:

TXIDNEID8 - TRANSMIT IDENTIFIER N EXTENDED IDENTIFIER HIGH

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 7

bit 0

bit 7-0

EID15:EID8: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 2-9:

TXIDNEID0 - TRANSMIT IDENTIFIER N EXTENDED IDENTIFIER LOW

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 13

MCP2502X/5X

REGISTER 2-10: RXMSIDH - ACCEPTANCE FILTER MASK STANDARD IDENTIFIER HIGH

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3*

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier bits

* If OPTREG2.MTYPE = 1, then SID3 is forced to zero.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 2-11: RXMSIDL - ACCEPTANCE FILTER MASK STANDARD IDENTIFIER LOW

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

R/W-x

EXIDE

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

SID2:SID0: Standard Identifier bits

Standard messages, bits = b’000’

Extended messages, bits = SID2:SID0

bit 4

bit 3

Unimplemented: Read as '0’

EXIDE: Extended Identifier Enable bit

1= Apply filter to RXFnSIDL.EXIDE (filter applies to standard or extended message frames

depending on filter bit)

0= Do not apply filter to RXFnSIDL.EXIDE (filter will be applied to both standard and extended

message frames)

bit 2

Unimplemented: Read as '0’

bit 1-0

EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 2-12: RXMEID8 - ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER MID

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 7

bit 0

bit 7-0

EID15:EID8: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 14

MCP2502X/5X

REGISTER 2-13: RXMEID0 - ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER LOW

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-3

bit 2-0

EID7:EID3: Extended Identifier bits

EID2:EID0: Extended Identifier bits (always reads as ‘0’)

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 2-14: RXFNSIDH - ACCEPTANCE FILTER N STANDARD IDENTIFIER HIGH

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3*

bit 7

bit 0

bit 7-0

SID10:SID3: Standard Identifier bits

* If OPTREG2.MTYPE = 1, then SID3 = X

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 2-15: RXFNSIDL - ACCEPTANCE FILTER N STANDARD IDENTIFIER LOW

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

R/W-x

EXIDE

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

SID2:SID0: Standard Identifier bits

1= When EXIDE = 1, SID2:SID0 = b’xxx’

0= When EXIDE = 0, SID2:SID0 = as configured

bit 4

bit 3

Unimplemented: Read as ‘0’

EXIDE: Extended Identifier Enable bit

1= Filter will apply to extended identifier

0= Filter will apply to standard identifier

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 15

MCP2502X/5X

REGISTER 2-16: RXFNEID8 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER MID

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 7

bit 0

bit 7-0

EID15:EID8: Extended Identifier Bit

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 2-17: RXFNEID0 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER LOW

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-0

EID7:EID0: Extended Identifier Bit (always = b’xxx’)

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 16

MCP2502X/5X

REGISTER 2-18: EFLG - ERROR FLAG REGISTER

R-0

EWARN

bit 0

ESCF

RBO

TXBO

TXEP

RXEP

TXWAR RXWAR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

ESCF: Error State Change (for sending Error state message)

1= An error state change occurred

0= No error state change

RBO: Receive Buffer Overflow

1= Overflow occurred

0= No overflow occurred

TXBO: Transmitter in Bus Off Error State bit

1= TEC reaches 256

0= Indicates a successful bus recovery sequence

TXEP: Transmitter in Error Passive State bit

1= TEC is equal to or greater than 128

0= TEC is less than 128

RXEP: Receiver in Error Passive State bit

1= REC is equal to or greater than 128

0= REC is less than 128

TXWAR: Transmitter in Error Warning State bit

1= TEC is equal to or greater than 96

0= TEC is less than 96

RXWAR: Receiver in Error Warning State bit

1= REC is equal to or greater than 96

0= REC is less than 96

EWARN; Either the Receive Error counter or Transmit error counter has reached or exceeded

96 errors

1= TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)

0= Both REC and TEC are less than 96

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 17

MCP2502X/5X

NOTES:

DS21664D-page 18

MCP2502X/5X

3.0

3.1

USER REGISTERS

Description

Note 1: When transferred to RAM, the register

addresses are offset by 1Ch. Accessing

individual registers using the “Write

Register” or “Read Register command

requires use of the offset address. Also,

see Table 3-2 for information on

accessible registers not contained in user

EPROM.

The MCP2502X/5X allows the user to pre-program

registers pertaining to CAN module and device

configuration into non-volatile EPROM memory. In this

way, the device is initialized to a default state after

power-up. The user registers are transferred to SRAM

during the power-up sequence and many of the

registers are able to be accessed via the CAN bus once

the device establishes a connection with the bus.

Additionally, there are 16 user-defined registers that

can be used to store information about the part (e.g.,

serial number, node identifier, etc.). The registers are

summarized in Table 3-1.

2: Do not address locations outside of the

user memory map or unexpected results

may occur.

TABLE 3-1:

USER MEMORY MAP

Address

Name

Description

Address

Name

Description

00h

IOINTEN Enable inputs for Transmit-On-Change

feature

1Bh

RXF0EID0 Acceptance Filter 0, Extended ID

LSB

01h

IOINTPO Defines polarity for I/O or greater than/

less than operator for A/D Transmit-On-

Change inputs

1Ch

1Dh

RXF1SIDH Acceptance Filter 1, Standard ID

MSB

02h

GPLAT

General Purpose I/O (GPIO) Register

RXF1SIDL Acceptance Filter 1, Standard ID

LSB, Extended ID USB, and

Extended ID enable

03h

04h

0xFF

Reserved

1Eh

1Fh

RXF1EID8 Acceptance Filter 1, Extended ID

MSB

OPTREG1 Configuration options, including GPIO

pull-up enable, clockout enable and

prescaler

RXF1EID0 Acceptance Filter 1, Extended ID

LSB

05h

06h

T1CON

PWM1 Timer Control Register; contains

enable bit, clock prescale and DC LSBs

20h

21h

TXID0SIDH Transmit Buffer 0, Standard ID MSB

T2CON

PWM2 Timer Control Register; contains

enable bits, clock prescale and DC LSBs

TXID0SIDL Transmit Buffer 0, Standard ID LSB,

Extended ID USB, and Extended ID

enable

07h

08h

09h

0Ah

PR1

PR2

PWM1 Period Register

PWM2 Period Register

22h

23h

24h

25h

TXID0EID8 Transmit Buffer 0, Extended ID MSB

TXID0EID0 Transmit Buffer 0, Extended ID LSB

TXID1SIDH Transmit Buffer 1, Standard ID MSB

PWM1DCH PWM1 Duty Cycle (DC) MSBs

PWM2DCH PWM2 Duty Cycle (DC) MSBs

TXID1SIDL Transmit Buffer 1, Standard ID LSB,

Extended ID USB, and Extended ID

enable

3

0Bh

0Ch

0Dh

CNF1

CNF2

CNF3

CAN module register configures

synchronization jump width and baud rate

prescaler

26h

27h

28h

TXID1EID8 Transmit Buffer 1, Extended ID MSB

TXID1EID0 Transmit Buffer 1, Extended ID LSB

TXID2SIDH Transmit Buffer 2, Standard ID MSB

3

CAN module register configures

propagation segment, phase segment 1,

and determines number of sample points

CAN module register configures phase

buffer segment 2, Sleep mode

Note 1: GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch.

2: User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem”

commands.

3: Cannot be modified from initial programmed values.

4: Unimplemented on MCP2502X devices and read 0x00(exception, ADCON1 = 0x0F).

DS21664D-page 19

MCP2502X/5X

TABLE 3-1:

USER MEMORY MAP (CONTINUED)

Address

Name

Description

Address

Name

Description

4

0Eh

0Fh

ADCON0

ADCON1

STCON

A/D Control Register; contains enable,

conversion rate, channel select bits

29h

TXID2SIDL Transmit Buffer 2, Standard ID LSB,

Extended ID USB, and Extended ID

enable

A/D Control Register; contains voltage

reference source, conversion rate and

A/D input enable bits

2Ah

TXID2EID8 Transmit Buffer 2, Extended ID MSB

10h

11h

Scheduled Transmission Control Register

2Bh

2Ch

TXID2EID0 Transmit Buffer 2, Extended ID LSB

4

OPTREG2 Configuration options, including Sleep

mode, RTR message and error recovery

enables

ADCMP3H Analog Channel 3 Compare Value

MSB

4

12h

13h

14h

15h

16h

17h

18h

19h

—

Reserved

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

ADCMP3L Analog Channel 3 Compare Value

LSb’s

4

—

Reserved

ADCMP2H Analog Channel 2 Compare Value

MSB

4

RXMSIDH Acceptance Filter Mask, Standard ID MSB

ADCMP2L Analog Channel 2 Compare Value

LSb’s

4

RXMSIDL Acceptance Filter Mask, Standard ID LSB

and Extended ID USB

ADCMP1H Analog Channel 1 Compare Value

MSB

4

RXMEID8 Acceptance Filter Mask, Extended ID

MSB

ADCMP1L Analog Channel 1 Compare Value

LSb’s

4

RXMEID0 Acceptance Filter Mask, Extended ID LSB

ADCMP0H Analog Channel 0 Compare Value

MSB

4

RXF0SIDH Acceptance Filter 0, Standard ID MSB

ADCMP0L Analog Channel 0 Compare Value

LSb’s

1

RXF0SIDL Acceptance Filter 0, Standard ID LSB,

Extended ID USB, and Extended ID

enable

GPDDR

General Purpose I/O Data Direction

Register

2

1Ah

RXF0EID8 Acceptance Filter 0, Extended ID MSB

35-44h USER[0:F] User Defined Bytes (0-15)

Note 1: GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch.

2: User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem”

commands.

3: Cannot be modified from initial programmed values.

4: Unimplemented on MCP2502X devices and read 0x00(exception, ADCON1 = 0x0F).

TABLE 3-2:

ACCESSIBLE RAM REGISTERS NOT IN THE EPROM MAP

Value on

POR

Value on

RST

Addr*

Name

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

1Fh**

18h

19h

1Ah

50h

51h

52h

53h

54h

55h

56h

57h

GPDDR

EFLG

—

DDR6

RBO

DDR4

TXEP

DDR4

TXEP

DDR3

RXEP

DDR2

DDR1

DDR0

-111 1111

ESCF

TXWAR

RXWAR

EWARN 0000 0000 0000 0000

0000 0000 0000 0000

TEC

Transmit Error Counters

Receive Error Counters

REC

0000 0000 0000 0000

ADRES3H

ADRES3L

ADRES2H

ADRES2L

ADRES1H

ADRES1L

ADRES0H

ADRES0L

AN3.9

AN3.1

AN2.9

AN2.1

AN1.9

AN1.1

AN0.9

AN0.1

AN3.8

AN3.0

AN2.8

AN2.0

AN1.8

AN1.0

AN0.8

AN0.0

AN3.6

—

AN3.6

—

AN3.5

—

AN3.4

—

AN3.3

—

AN3.2

—

xxxx xxxx uuuu uuuu

xx-- ---- uu-- ----

xxxx xxxx uuuu uuuu

xx-- ---- uu-- ----

xxxx xxxx uuuu uuuu

xx-- ---- uu-- ----

xxxx xxxx uuuu uuuu

xx-- ---- uu-- ----

AN2.6

—

AN2.6

—

AN2.5

—

AN2.4

—

AN2.3

—

AN2.2

—

AN1.6

—

AN1.6

—

AN1.5

—

AN1.4

—

AN1.3

—

AN1.2

—

AN0.6

—

AN0.6

—

AN0.5

—

AN0.4

—

AN0.3

—

AN0.2

—

*

These addresses are used when using the “Write Register” or “Read Register” command

** The GPDDR register is not offset to RAM the same as the other registers in the EPROM

DS21664D-page 20

MCP2502X/5X

Scheduled Transmissions

4.0

4.1

DEVICE OPERATION

Power-Up Sequence

Once the MCP2502X/5X has gone on bus it will

transmit the On Bus message once, regardless of

whether enabled or not. This message notifies the

network of the MCP2502X/5X’s presence. The On Bus

message will (if enabled STCON.STEN) repeat at a

frequency determined by the STCON register

(Register 4-1).

The following sections describe the events/actions of

the MCP2502X/5X during normal power-up and

operation.

4.1.1

POWER-ON RESET

This message can also be configured to send the

“Read A/D Register” data bytes along with the

The MCP2502X/5X goes through a sequence of events

at power-on reset (POR) in order to load the

programmed configuration and insure that errors are

not introduced on the bus. During this time, the device

is prevented from generating a low condition on the

TXCAN pin. The TXCAN pin must remain high from

power-on until the device goes on bus.

predefined

identifier

in

TXID2

by

setting

STCON.STMS = 1.

Note: The first On Bus message sent after

power-up will NOT send the “Read A/D

Register” data bytes, regardless of the

STCON.STMS value.

Operational Mode at Power-On

Note: If the MCP2502X/5X enters SLEEP mode,

the scheduled transmissions will cease

until the device wakes up again. This

implies that SLEEP mode has priority over

scheduled transmissions.

The MCP2502X/5X initially powers up in Configuration

mode. While in this mode, the MCP2502X/5X will be

prevented from sending or receiving messages via the

CAN interface. The ADC and PWM peripherals are

disabled while in this mode.

Self-Configuration

4.2

Message Functions

Once the MCP2502X/5X is out of reset, it will perform

The MCP2502X/5X uses the global mask (RXMASK),

two filters (RXF0 and RXF1) and two receive buffers

(RB0 and RB1) to determine if a received message

should be acted upon. There are 16 functions that can

be performed by the MCP2502X/5X based on received

messages (see Table 4-1).These functions allow the

device to not only be accessed for Information

Request/Input/Output operations, but also to be

reconfigured via the CAN bus, if necessary.

a

self-configuration. This is accomplished by

transferring the contents of the EPROM array to the

corresponding locations within the SRAM array. In

addition, the checksum of the data written to SRAM will

be compared to a pre-programmed value as a test of

valid data.

Going On Bus

Once the self-configuration cycle has successfully

completed, the MCP2502X/5X switches to Listen-only

mode. It will remain in this mode until an error-free CAN

message is detected. This is done to ensure that the

device is at the correct bus rate for the system.

4.3

Message Types

There are three types of messages that are used to

implement the functions of Table 4-1.

Once the device detects an error-free message, it waits

for CAN bus idle before switching to Normal mode. This

prevents it from going on bus in the middle of another

node’s transmission and generating an error frame.

1. Information Request Messages (IRM)

- Received by the MCP2502X/5X.

2. Output Messages

- Transmitted from the

MCP2502X/5X as a response to IRMs.

Alternately, the MCP2505X may directly enter Normal

mode (without first entering Listen-only Mode) after

completing its self-configuration. This is configured by

the user via a control bit (OPTREG2.PUNRM).

3. Input Messages - Received by the MCP2502X/

5X and used to modify registers.

Note: Information Request Messages (IRMs)

and Input messages are both input

messages to the MCP2502X/5X. IRMs are

received into receive buffer 0 and input

messages are received into receive buffer

1. This must be taken into account while

configuring the acceptance filters.

Once the MCP2502X/5X enters Normal mode, it is

ready to send/receive messages via the CAN interface.

At this point the ADC and PWM peripherals are

operational, if enabled.

DS21664D-page 21

MCP2502X/5X

4.3.1

INFORMATION REQUEST

MESSAGES

4.3.1.1

When

RTR Message Type

RTR message types

are

selected

(OPTREG2.MTYPE) and a node in the system wants

information from the MCP2502X/5X, it has to send a

remote frame on the bus. The identifier for the remote

frame must be such that it will be accepted through the

MCP2502X/5X’s mask/filter process (using RXF0). The

RTR message type (remote frames) is the default

configuration (MTYPE bit = 0).

Information Request Messages (IRM) are messages

that the MCP2502X/5X receives into Receive Buffer 0

(matches Filter 0) and then responds to by transmitting

a message (output message) containing the requested

data.

IRMs can be implemented as either a Remote Transfer

Request (RTR) or a Data Frame message by

configuring the MTYPE bit in the OPTREG2 register.

Information Request “RTR” messages must not only

meet the RXMASK/RXF0 criteria but must also have

the RTR bit of the CAN ID set (since the filter registers

do not contain an explicit RTR bit). If a message passes

the mask/filter process and the RTR bit is a ‘0’, that

message will be ignored.

TABLE 4-1:

MESSAGE FUNCTION

Name

Description

Read A/D

Registers

Transmits a single message containing

the current state of the analog and I/O

registers, including the configuration

Once the MCP2502X/5X has received a remote frame,

it will determine the function to be performed based

upon the three LSb’s (RXB0SIDL.SID2:SID0 for

standard messages and RXB0EID0.EID2:EID0 for

extended messages) of the received remote frame.

Read Control

Registers

Transmits several control registers not

included in other messages

Read Configura-

tion Registers

Transmits the contents of many of the

configuration registers

Additionally, a predefined Data Length Code (DLC)

must be sent to signify the number of data bytes that

the MCP2502X/5X must return in it’s output message

(see Table 4-2 and Table 4-3).

Read CAN

error states

Transmits the error flag register and

the error counts

Read PWM

Configuration

Transmits the registers associated with

the PWM modules

Read User

Registers 1

Transmits the values in bytes 0 - 7 of

the user memory

4.3.1.2

Data Frame Message Type

When a non-RTR (or data frame) message type is

selected and a node in the system wants information

from the MCP2502X/5X, it sends an Information

Request in the form of a data frame. The identifier for

this request must be such that it will be accepted

through the MCP2502X/5X’s mask/filter process (using

RXF0).

Read User

Registers 2

Transmits the values in bytes 8 -15 of

the user memory

Read Register*

Transmits a single byte containing the

value in an addressed user memory

register

Write Register

Uses a mask to write a value to an

addressed register

Information request messages in the data frame format

must not only meet the RXMASK/RXF0 criteria, but

must also have the RTR bit of the CAN ID cleared

(since the filter registers do not contain an explicit RTR

bit). If a message passes the mask/filter process and

the RTR bit is a ‘1’, that message will be ignored.

Write TX Message Writes the identifiers to a specified

ID0 (TXID0) value

Write TX Message Writes the identifiers to a specified

ID1 (TXID1) value

Write TX Message Writes the identifiers to a specified

ID2 (TXID2)

value

Once the MCP2502X/5X has received a data frame

information request, it will determine the function to be

Write I/O

Configuration

Registers

Writes specified values to the three

IOCON registers

performed

based

upon

the

three

LSb’s

(RXB0SIDL.SID2:SID0 for standard messages and

RXB0EID0.EID2:EID0 for extended messages) of the

received data frame. Also, Bit 3 of the received

message ID must be set to a ‘1’.

Write RX Mask

Write RX Filter0

Write RX Filter1

Changes the receive mask to the

specified value

Changes the specified filter to the

specified value

In addition, the data length code (DLC) must be set to

a zero. Refer to Table 4-2 and Table 4-3 for more

information.

Changes the specified filter to the

specified value

* The Read Register command is available when using

extended message format only. Not available with

standard message format.

Regardless of the message format, all messages

except the Read Register message can use either

standard or extended identifiers. The Read Register

message has one additional requirement; it must be an

extended identifier. This is discussed in more detail in

Table 4-1 and Table 4-3 for more information.

DS21664D-page 22

MCP2502X/5X

three

bits

of

the

standard

identifier

4.3.2

OUTPUT MESSAGES

(RXF1SIDL.SID2:SID0) will indicate which register(s)

are to be written. The values for the register(s) are

contained in the data byte registers as defined in

Table 4-2.

The data frame sent in response to the information

request message is defined as an output message.

If the data fame is in response to a remote frame, it will

have the same identifier (standard or extended) and

contain the same number of data bytes specified by the

DLC of the remote frame (per the CAN 2.0B

specification).

Note: If using more than one controlling node, the

MCP2502X/5X must be set up to accept

input messages with different identifiers in

order to avoid possible message collisions in

the DLC or data bytes if transmitted at the

same time.

Note: If the DLC of the incoming remote frame

differs from the message definitions

summarized in Table 4-2 and Table 4-3, the

resulting output message will limit itself to the

erroneous DLC that was received (to

maintain compliance with the Bosch CAN

specification). The output message will

concatenate the number of data bytes for an

erroneous DLC that is less than the defined

number. For an erroneous DLC that is

greater than the defined number, the

MCP2502X/5X will extend the number of

data bytes, with the data value of the last

defined data byte being repeated in the extra

bytes in the data field.

Note 1: IRMs can theoretically be sent by more

than one controlling node because the

message is a predefined constant and

destructive collisions will not occur.

2: The number of data bytes in an input

message must match the DLC number as

defined in Table 4-2 and Table 4-3. If the

user specifies and transmits an input

message with a DLC that is less than the

required number of data bytes, the

MCP25020 will operate on corrupted data

for the bytes that it did not receive and

unknown results will occur.

If the output message is in response to a data frame,

the lower-three LSb’s of the identifier (standard or

extended) must be the same as the received message,

as well as the upper-seven MSb’s in the case of a

standard identifier, or the upper 25 MSb’s in the case of

an extended identifier. Bit 3 of a standard or extended

identifier of the output message will differ from the

received information request message in that the value

equals ‘1’ for an IRM and equals ‘0’ for the resulting

output message.

4.4

Dynamic Message Handling

The design insures that transmit and receive messages

are handled properly for variable bus-loading

conditions and different transmit/receive combinations.

4.4.1

MESSAGE ACCEPTANCE/

REJECTION

Messages received that meet the Mask/RXFn criteria

are then compared to the requirements for input

messages or IRMs, as determined by the filter used to

accept the message. If the message meets the

requirements of one of the associated input or

information request messages, the appropriate actions

for that message function are taken.

Output messages contain the requested data (in the

data field). Example: The information request

message Read CAN error is a remote transmit request

received by the MCP2502X/5X with a DLC of 3. The

responding output message will return a data frame

that contains the same identifier (standard or extended)

as the receive message. The accompanying data bytes

will contain the values of the predefined GPIO registers

and related control/status registers, as shown in

Table 4-2 and 4-3.

4.4.2

RECEIVING MULTIPLE MESSAGES

The MCP2502X/5X can only receive and process one

message at a time. While the MCP2502X/5X should

have ample time to process any received message

before another is completely received, a second

message received before the first message is finished

processing will be lost.

4.3.3

INPUT MESSAGES

Input messages are received into receive buffer 1 and

are used to change the values of the pre-defined

groups of registers. There is also an input message

that can change a single register’s contents. The

primary purpose of input messages are to reconfigure

MCP2502X/5X parameters (if needed) while in an

operating CAN system and are, therefore, optional in

system implementation. These messages are in the

form of standard (or extended) data frames (per the

CAN 2.0B specification) that have identifiers which

pass the MCP2502X/5X’s mask/filter process (using

RXF1). After passing the mask and filter, the lower-

However, the MCP2502X/5X has the ability to notify the

network if a message is lost. TXID1 can be configured

to transmit a message if a receive overflow occurs

(OPTREG2.CAEN = 0).

DS21664D-page 23

MCP2502X/5X

4.4.3

TRANSMIT MESSAGE PRIORITY

There is a priority for all transmit messages, including

TXIDn and all “Output” messages.

The transmit message priority is as follows:

1. Output messages have the highest priority.

Prioritization of the individual output message

types is determined by the three bits that

determine message type, with the lowest value

having the highest priority (e.g., Read A/D Regs

is a higher priority than Read Control Regs).

2. TXID2 (Transmit auto-converted messages) has

the second-highest priority.

3. TXID1 (Command acknowledge) has the third-

highest priority.

4. TXID0 (On Bus message) has the lowest

priority.

In the event two or more messages are pending

transmission, transmit-message-prioritization will occur

and the highest message type will be sent first.

Messages that are currently transmitting will not be

prioritized.

DS21664D-page 24

MCP2502X/5X

A hysteresis example:

4.5

Automatic Transmission

• The user sets the upper-eight bits of the 10-bit

compare register (ADCMP0H). The lower-two bits

of the compare register are not configurable by

the user and are forced to either b’11’or b’00’

depending on the polarity of the compare

threshold (i.e., transmit is triggered above or

below the compare value via the IOINTPO

register).

The MCP2502X/5X can automatically initiate four

different message types to indicate the following

situations:

• Edge detected on a digital input (TXID2).

• Threshold exceeded on an analog input (TXID2).

• Error condition (Read Error output message).

• Scheduled transmissions (TXID0).

• The user sets the polarity of the compare

threshold (IOINTPO). In this example, the

threshold is set for triggering a message on an

A/D > compare register. The two LSb’s are forced

to b’11’.

The buffers have an implied transmit priority, where

buffer 2 is the highest and buffer 0 is the lowest.

Therefore, multiple message buffers can be requested

for transmission and each one will be sent in order of

priority.

• When the A/D conversion exceeds the compare

register (b’nnnn nnnn 11’), an automatic

transmission will occur once.

4.5.1

DIGITAL INPUT EDGE DETECTION

Each GPIO pin configured as a digital input can be

individually configured to automatically transmit a

message when a defined edge occurs, as explained in

the GPIO module section. When transmitting this

message, the MCP2502X/5X uses TXID2. The DLC is

set to two and the first two bytes of the Read A/D

registers (IOINTFL and GPIO) are sent.

• In order for the automatic transmission to occur

again, the A/D value must first drop below the

compare register b’nnnn nnnn 00’and then

back above the compare register

b’nnnn nnnn 11’.

FIGURE 4-1:

HYSTERESIS

FUNCTION

4.5.2

ANALOG INPUT THRESHOLD

DETECTION

Set to Trigger when A/D>Compare Register

Each GPIO pin that has been configured as an analog

input can be individually configured to automatically

transmit a message when a threshold is exceeded as

described in the Analog-to-Digital Converter Module

section. The MCP2502X/5X sends TXID2 when

transmitting this message. The DLC is set to eight and

the eight bytes of the ‘Read A/D Registers’ are sent.

LSbs = b’11’

LSbs = b’00’

A/D above compare,

Message sent

A/D above compare,

Message sent

A/D below compare,

Reset

Note: The GPIO register that is sent with the

message (data byte 2) can be ignored if

there are no digital inputs enabled for

change-of-state, as it contains no useful

information for the Analog Input Threshold

Detect function.

Set to Trigger when A/D<Compare Register

LSbs = b’11’

LSbs = b’00’

A/D above compare,

Reset

4.5.2.1

Hysteresis Function

A/D below compare,

This function is automatic and will insure that an analog

value that is on the compare edge (i.e., toggling LSb)

does not fill the CAN bus with continuous A/D message

transmissions.

Message sent

A/D below compare,

Message sent

4.5.3

ERROR CONDITION

The hysteresis uses the two LSb’s of the compare

register. These two bits are forced and are not

configurable by the user. They will be forced to either

b’00’or b’11’, depending on the compare polarity. If

configured for A/D result > compare register, the

automatic transmission will occur when the A/D value

is greater than or equal to b’nnnn nnnn 11’ and

reset when less than or equal to b’nnnn nnnn 00’.

The opposite conditions must occur if the compare

polarity is set for A/D result < compare register.

The MCP2502X/5X can be configured to automatically

transmit a message whenever one or more of the

following error conditions occur:

• Receiver has entered error-warning state

• Receiver has entered error-passive state

• Transmitter has entered error-warning state

• Transmitter has entered error-passive state

• A Receive buffer has overflowed

DS21664D-page 27

MCP2502X/5X

If the Error Condition message is enabled

(OPTREG2.TXONE = 1) and one of the above

conditions occur, the MCP2502X/5X sends TXID1

identifier with output message Read CAN Error States

data field (three data bytes).

Scheduled Transmission

= STBF1:STBF0(STM3:STM0)

Message Type - The message sent for scheduled

transmissions consists of either TXID0 with zero data

bytes or TXID0 with eight data bytes containing the

Read A/D Regs message, depending on STMS bit in

the STCON register.

4.5.4

SCHEDULED TRANSMISSIONS

The MCP2502X/5X has the capability of sending

scheduled transmissions (On Bus message), if

enabled.

Note: The actual scheduled transmission

intervals may vary slightly due to the

internal event que of the control module.

The scheduled transmission control register (STCON)

enables and configures the occurrence of the

scheduled message. Setting the STEN bit in the

STCON register enables the scheduled message. The

STBF1:STBF0 and STM3:STM0 bits allow a scheduled

transmission to be initiated from a minimum of 256 µs

to a maximum of 16.8 seconds (using a 16 MHz FOSC)

and the following equation:

REGISTER 4-1:

STCON - SCHEDULED TRANSMISSION CONTROL REGISTER

R/W-0

STEN

R/W-0

STMS

R/W-1

STM3

R/W-1

STM2

R/W-1

STM1

R/W-1

STM0

STBF1

STBF0

bit 7

bit 0

bit 7

STEN: Scheduled Transmission Enable bits

1= Enabled

0= Disabled

bit 6

STMS: Scheduled Transmission Message Select

1= Sends Transmit ID 0 (TXID0) with the “Read A/D Regs” data (DLC = 8)

0= Sends Transmit ID 0 (TXID0) with no data (DLC = 0)

bit 5-4

STBF1:STBF0: Base Transmission Frequency bits

00= 4096TOSC

01= 16•(4096TOSC)

10= 256•(4096TOSC)

10= 4096•(4096TOSC)

(e.g., STBF1:STBF0 => 00 => 256 µs for a 16 MHz FOSC)

bit 3-0

STM3:STM0: Scheduled Transmission Multiplier bits

0000= 1

0001= 2

-

1110= 15

1111= 16

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 28

MCP2502X/5X

TABLE 4-4:

REGISTERS ASSOCIATED WITH THE CAN MODULE

Value on

POR

Value on

RST

Addr

Name

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

0Bh

0Ch

CNF1

CNF2

SJW1

SJW0

SAM

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

xxxx xxxx

uuuu uuuu

BTLM-

ODE

PHSEG12 PHSEG11 PHSEG10

PRSEG2

PRSEG1

PRSEG0

0Dh

10h

11h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

CNF3

—

WAKF

STMS

ERRE

SID9

SID1

EID14

EID6

SID9

SID1

EID14

EID6

SID9

SID1

EID14

EID6

SID9

SID1

EID14

EID6

SID9

SID1

EID14

EID6

SID9

SID1

EID14

EID6

—

STBF1

TXONE

SID8

SID0

EID13

EID5

SID8

SID0

EID13

EID5

SID8

SID0

EID13

EID5

SID8

SID0

EID13

EID5

SID8

SID0

EID13

EID5

SID8

SID0

EID13

EID5

—

STBF0

SLPEN

SID7

—

STM3

MTYPE

SID6

—

PHSEG22 PHSEG21 PHSEG20

-x-- xxxx

-u-- uuuu

STCON

STEM

CAEN

SID10

SID2

STM2

PDEFEN

SID5

—

STM1

PUSLP

SID4

EID17

EID9

EID1

SID4

EID17

EID9

EID1

SID4

EID17

EID9

EID1

SID4

EID17

EID9

EID1

SID4

EID17

EID9

EID1

SID4

EID17

EID9

EID1

STM0

PUNRM

SID3

EID16

EID8

EID0

SID3

EID16

EID8

EID0

SID3

EID16

EID8

EID0

SID3

EID16

EID8

EID0

SID3

EID16

EID8

EID0

SID3

EID16

EID8

EID0

0xxx xxxx

0uuu uuuu

OPTREG2

RXMSIDH

RXMSIDL

RXMEID8

RXMEID0

RXF0SIDH

RXF0SIDL

RXF0EID8

RXF0EID0

RXF1SIDH

RXF1SIDL

RXF1EID8

RXF1EID0

TXB0SIDH

TXB0SIDL

TXB0EID8

TXB0EID0

TXB1SIDH

TXB1SIDL

TXB1EID8

TXB1EID0

TXB2SIDH

TXB2SIDL

TXB2EID8

TXB2EID0

0000 0000 uuuu uuuu

xxxx xxxx

xxx- --xx

xxxx xxxx

xxx- --xx

xxxx xxxx

xxx- --xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

uuuu uuuu

uuu- --uu

uuuu uuuu

uuu- --uu

uuuu uuuu

uuu- --uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

EID15

EID7

EID12

EID4

SID7

—

EID11

EID3

SID6

—

EID10

EID2

SID5

—

SID10

SID2

EID15

EID7

EID12

EID4

SID7

—

EID11

EID3

SID6

—

EID10

EID2

SID5

—

SID10

SID2

EID15

EID7

EID12

EID4

SID7

—

EID11

EID3

SID6

EXIDE

EID11

EID3

SID6

EXIDE

EID11

EID3

SID6

EXIDE

EID11

EID3

EID10

EID2

SID5

—

SID10

SID2

EID15

EID7

EID12

EID4

SID7

—

EID10

EID2

SID5

—

SID10

SID2

EID15

EID7

EID12

EID4

SID7

—

EID10

EID2

SID5

—

SID10

SID2

EID15

EID7

EID12

EID4

EID10

EID2

DS21664D-page 29

MCP2502X/5X

NOTES:

DS21664D-page 30

MCP2502X/5X

5.2

Digital Input Edge Detection

5.0

5.1

GPIO MODULE

Description

All GPIO pins have a digital input edge detection

feature that will automatically transmit a message when

an edge with the proper polarity occurs on any of the

digital inputs. Only pins configured as inputs and

enabled for this function via control register IOINTPO

will perform this operation.

The MCP2502X/5X has eight general-purpose input/

output pins (GP0 to GP7), collectively labeled GPIO. All

GPIO port pins have TTL input levels and full CMOS

output drivers, with the exception of GP7, which is input

only. Pins GP6:GP0 can be individually configured as

input or output via the GPDDR register.

Note: Refer to Section 7.4 “A/D Threshold

Detection” for information regarding A/D

channels.

Note: The GPDDR register controls the direction

of the GPIO pins, even when they are

being used as analog inputs. The user

must ensure that the bits in the GPDDR

register are maintained set (input) when

using them as analog inputs.

Three control registers are associated with this

function. An enable pin for each GPIO pin resides in the

IOINTEN register. When a bit is set to a '1', the

corresponding GPIO pin is enabled to generate a

transmit-on-change message (TXID2) when an edge of

specified polarity occurs.

Each of the GPIO pins has a weak internal pull-up

resistor. A single control bit (OPTREG.GPPU) can turn

on/off all the pull-ups. The weak pull-up is automatically

turned off when the port pin is configured as an output.

The pull-ups are disabled during a Power-on Reset.

The digital edge detection function on a GPIO pin

configured as a digital input is edge triggered. A rising-

edge will generate a transmission if the corresponding

bit in the IOINTPO register is set. A falling-edge will

generate a transmission if the bit is cleared. When a

valid edge appears on the enabled GPIO pin, CAN

message TXID2 is initiated.

All pins are multiplexed with an alternate function,

including analog-to-digital conversion on up to four of

the GPIO pins, analog VREF inputs up to two pins, PWM

outputs up to two pins, clock-out function and external

reset. The operation of each pin is selected by clearing,

or setting, control bits in various control registers. GPIO

pin functions are summarized in Table 5-1.

The edge-detection function on any given GPIO pin

(configured as a digital input) can wake up the

processor from SLEEP if the corresponding interrupt

enable bit in the IOINTEN register was set prior to

going into SLEEP mode. If a wake-up from SLEEP is

caused in this manner, the device will immediately

initiate a transmit message (TXID2).

TABLE 5-1:

Name

GPIO FUNCTIONS

Bit

Function

#

GP0/AN0

bit0 I/O or analog input

bit1 I/O or analog input

GP1/AN1

GP2/AN2/PWM2

bit2 I/O, analog input

or PWM out

GP3/AN3/PWM3

GP4/VREF-

bit3 I/O, analog input

or PWM out

bit4 I/O or analog voltage

reference

GP5/VREF+

bit5 I/O or analog voltage

reference

GP6/CLKOUT

GP7/nRST/VPP

bit6 I/O or Clock output

bit7 Input, external reset input

or programming voltage

input

DS21664D-page 31

MCP2502X/5X

REGISTER 5-1:

GPDDR - DATA DIRECTION REGISTER

U-0

—

R/W-1

DDR6

R/W-1

DDR5

R/W-1

DDR4

R/W-1

DDR3

R/W-1

DDR2

R/W-1

DDR1

R/W-1

DDR0

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

DDR6:DDR0: Data Direction Register* bits

bit 6-0

1= corresponding GPIO pin is configured as an input

0= corresponding GPIO pin is configured as an output

* must bet set if corresponding analog channel is enabled (see ADCON1)

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 5-2:

GPLAT - GPIO OUTPUT REGISTER

U-0

—

R/W-0

GP6

R/W-0

GP5

R/W-0

GP4

R/W-0

GP3

R/W-0

GP2

R/W-0

GP1

R/W-0

GP0

bit 7

bit 0

bit 7

Unimplemented: Read as '0’

GP6:GP0: GPIO Bits

bit 6-0

1= corresponding GPIO pin output latch is a ‘1’

0= corresponding GPIO pin output latch is a ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 5-3:

IOINTEN REGISTER

R/W-0

GP7TXC GP6TXC GP5TXC GP4TXC

bit 7

GP3TXC GP2TXC GP1TXC GP0TXC

bit 0

bit 7-0

GP7TXC:GP0TXC: Transmit-on-change Enable bits

1= Enable Transmit-On-Change/Compare For Corresponding GPIO/AN Channel

0= Disable Transmit-On-Change/Compare For Corresponding GPIO/AN Channel

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 32

MCP2502X/5X

REGISTER 5-4:

IOINTPO REGISTER

R/W-0 R/W-0

R/W-0

GP7POL GP6POL GP5POL GP4POL

bit 7

GP3POL GP2POL GP1POL GP0POL

bit 0

bit 7-0

GP7POL:GP0POL: Transmit-on-change Polarity bits

1= Digital Inputs: Low-to-High Transition On Corresponding GPIO Input Pin Generates a

transmit message

Analog Inputs: A/D result above compare value generates a transmit message

0= Digital Inputs: High-to-Low Transition On Corresponding GPIO Input Generates transmit

message

Analog Inputs: A/D result below compare value generates a transmit message

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 5-5:

IOINTFL REGISTER

R-0

GP7TXF GP6TXF GP5TXF GP4TXF

bit 7

GP3TXF

GP2TXF GP1TXF GP0TXF

bit 0

bit 7-0

GP7TXF:GP0TXF: Transmit-on-change Polarity bits

1= Digital Inputs: A valid edge has occurred on the digital input

Analog Inputs: A/D result does exceed the compare threshold

0= Digital Inputs: A valid edge has not occurred on the digital input

Analog Inputs: A/D result does not exceed the compare threshold

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 33

MCP2502X/5X

REGISTER 5-6:

OPTREG1 REGISTER

R/W-1

GPPU

R/W-1

U-0

—

R/W-0

AQT1

R/W-0

AQT0

CLKEN

CLKPS1 CLKPS0

CMREQ

bit 7

bit 0

bit 7

GPPU: Weak pull-up enabled

1= Weak pull-ups disabled

0= Weak pull-ups enabled (GP7:GP0)

bit 6

CLKEN:

1= Clock Out Function disabled

0= Clock Out Function enabled

bit 5-4

CLKPS1:CLKPS0: CLKOUT Prescaler bits

00= FOSC/1

01= FOSC/2

10= FOSC/4

11= FOSC/8

bit 3

bit 2

Reserved:

CMREQ: Requests mode of operation (allows mode changes via the CAN bus)

1= Requests Listen-only mode

0= Requests Normal mode *

* CMREQ must be cleared as default to avoid device entering Listen-only mode on first “Input”

message.

bit 1-0

AQT1:AQT0: Analog Acquisition Time bits

00= 64TOSC

01= 2•(64TOSC)

10= 4•(64TOSC)

11= 8•(64TOSC)

(e.g., AQT1:AQT0 => 00 => 2.56 µs for a 25 MHz FOSC)

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 34

MCP2502X/5X

REGISTER 5-7:

OPTREG2 REGISTER

R/W-0

CAEN

R/W-0

PUNRM

bit 0

ERREN TXONEN SLPEN

MTYPE

PDEFEN

PUSLP

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

CAEN: Command Acknowledge Enable bit

1= Enables the command acknowledge message (TXID1)

0= Enables the receive overflow message (TXID1)

ERREN: Error Recovery Enable bit

1= MCP2502X/5X will recover into Listen-only mode from bus off

0= MCP2502X/5X will recover into Normal mode from bus-off

TXONEN: Transmit on Error Condition bit(REC or TEC)

1= Enable, will send message if error counter(s) go high enough

0= Disable, will NOT send message regardless of error counter values

SLPEN: Low power SLEEP mode enable/disable

1= Device will enter Sleep if bus is idle for at least 1408 bit times

0= SLEEP mode is disabled

MTYPE: Determines if information request messages use RTR or not

1= RTR is NOT used for IRM (Data Frame)

0= RTR is used for IRM (Remote Frame)

PDEFEN: Enables PWM outputs to return to POR default values when CAN bus communication

is lost

1= Enables PWM output default values

0= Disables PWM output default values

bit 1

bit 0

PUSLP: Allows device to enter SLEEP while in Listen-only mode during power-up sequence

1= Enables SLEEP when in Listen-only mode during power-up sequence

0= Disables SLEEP when in Listen-only mode during power-up sequence

PUNRM: Enters Normal mode after completing self-configuration during power-up sequence

1= Enters “Normal” mode after completing self-configuration during power-up sequence

0= Enables “Listen-only” mode after completing self-configuration during power-up sequence

and waits for an error-free message before switching to Normal mode

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH GPIO MODULE

Value on

POR

Value on

RST

Addr

Name

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Bank 0

34h

GPDDR

IOINTEN

IOINTPO

OPTREG1

—

DDR6

GP6TXC

GP6POL

CLKEN

DDR5

DDR4

DDR3

GP3TXC

GP3POL

—

DDR2

DDR1

GP1TXC

GP1POL

AQT1

DDR0

-111 1111 -111 1111

00h

GP7TXC

GP7POL

GPPU

GP5TXC

GP5POL

CLKPS1

GP4TXC

GP4POL

CLKPS0

GP2TXC

GP2POL

CMREQ

GP0TXC 0000 0000 0000 0000

GP0POL 0000 0000 0000 0000

01h

04h

AQT0

0000 ---- 0000 ----

Legend: x = unknown, U = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by module.

DS21664D-page 35

MCP2502X/5X

NOTES:

DS21664D-page 36

MCP2502X/5X

reconfigure to their default conditions. This includes the

PWM module itself being disabled and the GPIO being

forced low, high or tri-state.

6.0

6.1

PWM MODULE

Description

There are two Pulse Width Modulation (PWM) modules

(PWM1 and PWM2) that generate up to a 10-bit

resolution output signal on GP2 and GP3, respectively.

Each of these outputs can be separately enabled, with

each having its own associated timer, duty cycle and

period registers for controlling the PWM output shape.

FIGURE 6-2:

Period

PWM OUTPUT

Duty Cycle TMRn = PRn

TMRn=Duty Cycle

Each PWM module contains a set of master/slave duty

cycle registers, providing up to a 10-bit resolution PWM

output. Figure 6-1 shows a simplified block diagram of

the PWM module. A PWM output has a time base

(period) and a time that the output stays high (duty

cycle), as shown in Figure 6-2. The frequency of the

PWM is the inverse of the period (1/period).

TMRn = PRn

6.2

PWM Timer Modules

There are two 8-bit timers supporting the two PWM

outputs. Both timers have a prescaler only. The timers

are readable and writable and are cleared on any

device reset or when the timer is turned off.

At power-on, the PWM outputs are not enabled until

after the self-configuration sequence has been

completed (i.e., all SRAM registers have been loaded

with their default values) to prevent invalid signals from

occurring on the PWM outputs.

The input clock (F^OSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits TnCKPS[1:0] in

register TnCON<5:4> (where n corresponds to the

appropriate timer).

FIGURE 6-1:

SIMPLIFIED BLOCK

DIAGRAM

Each timer module has an 8-bit period register, PRn.

PRn is a readable and writable register. The timer

module increments from 00huntil it matches PRn and

then resets to 00h on the next increment cycle. The

PRn register is set when the device is reset.

Duty cycle

registers

TnCON

(2 LSB)

PWMnDCH

PWMnDBH

Comparator

Each timer can be shut off by clearing control bit

TMRnON (TnCON<7>).

6.2.1

TIMER MODULE PRESCALER

The prescaler counters are cleared when a write to the

TnCON or TMRn register or any device reset (RST

reset or Power-on reset) occurs.

R

S

Q

GP<Y>

(PWMn)

Note

DDR<Y>

TMRn

Comparator

Prn

1

6.3

PWM Modules

Each PWM module contains a set of master/slave duty

cycle registers, providing up to a 10-bit resolution PWM

output. Figure 6-2 shows a simplified block diagram of

the PWM module.

6.3.1

PWM PERIOD

Note 1: 8-bit timer is concatenated with 2-bit internal

Q clock or 2 bits of the prescaler to create

10-bit time base

The PWM period is specified by writing to the PRn

register. The PWM period can be calculated using the

following formula:

PWM period = [(PR ) + 1]*4T

*(TMRn prescale value)

n

OSC

The PWM outputs can be forced to their default POR

conditions if CAN bus communication is lost and is

enabled via OPTREG2.PDEFEN. The system designer

must implement a hand-shaking protocol, such that the

MCP2505X will receive a valid message into one of the

receive buffers before four successive scheduled

transmissions occur. If a valid message is not received,

the PWM outputs GP2 and GP3 will automatically

PWM frequency = 1 ⁄ (PWM period)

When TMRn is equal to PRn, the following two events

occur on the next cycle:

• TMRn is cleared

• The PWM duty cycle is latched from PWMnDCH

into PWMnDBH

DS21664D-page 37

MCP2502X/5X

When the PWMnDBH and 2-bit latch match TMRn

concatenated with an internal 2-bit Q clock or 2 bits of

the TMRn prescaler, the PWM output pin is cleared.

6.3.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

PWMnDCH and TnCON registers. Up to 10-bit

resolution is available. The PWMnDCH contains the

eight MSb’s, while the TnCON register contains the two

LSb’s. This 10-bit value is represented by

PWM1DCH:T1CON<1:0> for PWM Module 1 and

PWM2DCH:T2CON<1:0> for PWM Module 2.

Maximum PWM resolution (bits) for a given PWM

frequency is equal to:

log((F_OSC) ⁄ (Fpwm)) ⁄ (log(2)bits)

The following equation is used to calculate the PMW

duty cycle:

Note: If the PWM duty cycle value is longer than

the PWM period (PWM duty cycle

= 100%), the PWM output pin will not be

cleared.

PWMDC = (PWMnDC)*T_OSC*TMRn (prescale)

In order to achieve higher resolution, the PWM

frequency must be decreased. In order to achieve

higher PWM frequency, the resolution must be

decreased. Table 6-1 lists example PWM frequencies

and resolutions for F^OSC= 20 MHz. TMRn prescaler

and PRn values are also shown.

PWMnDCH can be written to at any time, but the duty

cycle value is not latched into PWMnDBH until after a

match between PRn and TMRn occurs (i.e., the period

is complete).

The PWMnDBH register and 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

TABLE 6-1:

PWM FREQUENCIES AND RESOLUTIONS AT 20 MHZ

PWM Frequency

1.22 kHz

4.88 kHz

19.53 kHz 78.12 kHz 156.30 kHz 208.30 kHz

Timer Prescaler (1, 4, 16)

PRn Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

5.5

Maximum Resolution (bits)

REGISTER 6-1:

PWM1 DUTY CYCLE REGISTER MSB (PWM1DCH)

R/W-x

DC1B4

R/W-x

DC1B3

R/W-x

DC1B9

DC1B8

DC1B7

DC1B6

DC1B5

DC1B2

bit 7

bit 0

bit 7-0

DC1B9:DC1B2: Most Significant PWM0 Duty Cycle bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 6-2:

PWM2 DUTY CYCLE REGISTER MSB (PWM2DCH)

R/W-x

DC2B9

DC2B8

DC2B7

DC2B6

DC2B5

DC2B4

DC2B3

DC2B2

bit 7

bit 0

bit 7-0

DC2B9:DC2B2: Most Significant PWM2 Duty Cycle bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 38

MCP2502X/5X

REGISTER 6-3:

T1CON: TIMER1 CONTROL REGISTER

R/W-0

TMR1ON

bit 7

U-0

—

R/W-0

U-0

—

U-0

—

R/W-x

T1CKPS1 T1CKPS0

DC1B1

DC1B0

bit 0

bit 7

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Disables Timer1

bit 6

Unimplemented: Read as '0'

bit 5-4

T1CKPS1:T1CKPS0: Timer1 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

bit 3-2

bit 1-0

Unimplemented: Read as '0'

DC1B1:DC1B0: Least Significant PWM1 Duty Cycle bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 6-4:

T2CON: TIMER2 CONTROL REGISTER

R/W-0

TMR2ON

bit 7

U-0

—

R/W-0

U-0

—

U-0

—

R/W-x

T2CKPS1 T2CKPS0

DC2B1

DC2B0

bit 0

bit 7

TMR2ON: Timer2 On bit

1= Enables Timer2

0= Disables Timer2

bit 6

Unimplemented: Read as '0'

bit 5-4

T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

bit 3-2

bit 1-0

Unimplemented: Read as '0'

DC2B1:DC2B0: Least Significant PWM2 Duty Cycle bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 39

MCP2502X/5X

REGISTER 6-5:

PR1: PERIOD REGISTER

R/W-x

PR1B7

PR1B6

PR1B5

PR1B4

PR1B3

PR1B2

PR1B1

PR1B0

bit 7

bit 0

bit 7-0

PR1B7:PR1B0: PWM1 Period Register bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 6-6:

PR2: PERIOD REGISTER

R/W-x

PR2B5

R/W-x

PR2B7

PR2B6

PR2B4

PR2B3

PR2B2

PR2B1

PR2B0

bit 7

bit 0

bit 7-0

PR2B7:PR2B0: PWM2 Period Register bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

TABLE 6-2:

REGISTERS ASSOCIATED WITH THE PWM MODULE

Value on

POR

Value on

RST

Addr

Name

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

34h

05h

06h

07h

08h

09h

0Ah

GPDDR

T1CON

T2CON

PR1

—

DDR6

—

DDR5

DDR4

DDR3

—

DDR2

—

DDR1

DC1B1

DC2B1

DDR0

DC1B0

DC2B0

-111 1111 -111 1111

0-00 --xx 0-00 --uu

1111 1111 1111 1111

xxxx xxxx uuuu uuuu

TMR1ON

TMR2ON

T1CKPS1

T2CKPS1

T1CKPS0

T2CKPS0

—

Timer 1 Module’s Period Register

Timer 2 Module’s Period Register

PR2

PWM1DCH

PWM2DCH

DC1B9

DC2B9

DC1B8

DC2B8

DC1B7

DC2B7

DC1B6

DC2B6

DC1B5

DC2B5

DC1B4

DC2B4

DC1B3

DC2B3

DC1B2

DC2B2

Legend: x = unknown, U = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by module.

DS21664D-page 40

MCP2502X/5X

7.3

A/D Conversion Modes

7.0

7.1

ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

There are two modes of conversion that can be

individually selected for each analog channel that has

been enabled. These are auto-conversion and

conversion-on-request.

Description

The Analog-to-Digital (A/D) module is a four-channel,

10-bit successive approximation type of A/D. The A/D

allows conversion of an analog input signal to a

corresponding 10-bit number. The four channels are

multiplexed on the GP[3:0] pins. The converter is

turned off/on via the ADCON0 register and each

channel is individually enabled via the ADCON1 control

register. The VREF+ and VREF- sources are user-

selectable as internal or external. Each channel can be

set to one of two conversion modes:

7.3.1

AUTO-CONVERSION MODE

If the Auto-conversion mode is selected (STCON), an

A/D conversion is performed sequentially for each

channel that has been set to Analog Input mode and

has been configured for Auto-conversion mode.

Conversion starts with AN0 and is immediately

followed by AN1, etc. Once the conversion has

completed, the value is stored in the analog channel

registers for the respective channel.

1. Auto-conversion

The rate of the auto-conversion is determined by a

timer and prescaler. The formula for determining

conversion rates is:

2. Convert-on-request.

7.2

A/D Module Registers

(T_OSC)(1024)(Prescaler rate)

The A/D module itself has several registers. The

registers are:

Typical conversion rates with a 20 MHz oscillator input

are shown in Table 7-1.

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

TABLE 7-1:

AUTO-CONVERSION RATES

FOR GIVEN PRESCALE

RATES AT 20 MHZ

• Transmit-on-Change Register (IOINTEN)

• Compare and Polarity Register (ADCMPnL)

• A/D Result Registers (ADRESnL, ADRESnH)

Prescale

Rate

Auto-Conversion

Rate

TOPS[2:0]

The ADCON0 register controls the operation of the

A/D module, including auto-conversion rate and enable

bit. The ADCON1 register enables the A/D function on

port pins GP3:GP0, A/D conversion rate and selects

the voltage reference source. The IOINTEN register’s

four least significant bits enable/disable the transmit-

on-change function. The ADCMPnL.ADPOL bit sets

the polarity (above or below threshold) for the transmit-

on-change function.

000

001

010

011

100

101

110

111

1:1

51 µs

410 µs

2 ms

1:8

1:32

1:128

1:512

1:1024

1:2048

1:4096

7 ms

26 ms

52 ms

105 ms

210 ms

The result of an A/D conversion is made available to

the user within the data field of the Read A/D Registers

output message via the CAN bus. This message can

be directly requested by another CAN node or be

automatically transmitted (TXIDO), as has been

described previously.

The timer is turned on if one of the GPnTXC bits are set

in the IOINTEN register and configured as analog

input.

The prescaler counter is cleared when the device is

reset (RST reset or Power-on reset).

Additionally, the individual channel results may be read

using the “Read Register” command as described in

Section 4.3.1 “Information Request Messages” and

as shown in Table 3-2 by addressing the appropriate

A/D result register (ADRESnL and ADRESnH).

Note: The GPDDR register controls the direction

of the GPIO pins, even when they are

being used as analog inputs. The user

must ensure that the bits in the GPDDR

register are maintained set (input) when

using them as analog inputs.

DS21664D-page 41

MCP2502X/5X

7.3.2

CONVERSION-ON-REQUEST

MODE

7.4

A/D Threshold Detection

Once an A/D auto-conversion has been completed, the

A/D channel result(s) can be compared to a value

stored in the associated A/D channel comparator

registers.

If the Conversion-on-request mode is selected, the

device performs an A/D conversion only after receiving

a Read A/D Registers or Read Register Receive

message (IRM). In the case of the Read A/D Registers

command, all of the GPIO pins that have been

configured as analog input channels will have an A/D

conversion done before the data frame is sent. When a

Read Register Receive message is initiated (extended

message format only), the A/D conversion is performed

when the MSB of the analog channel is requested, with

the MSB result being transferred. A subsequent read of

the LSB will transmit the value latched when the MSB

was requested (it is recommended that the Read A/D

Registers receive message is used to obtain complete

analog channel values in one message).

If the value in the analog channel result registers (i.e.,

AN0L and AN10H registers for analog channel 0) is

lower or higher than the value in the A/D comparator

registers (as specified by a corresponding polarity bit),

a transmit-on-change message will be sent (TXID2).

The threshold-detection function for all analog

channels is bit-selectable.

If the A/D channel has been configured for transmit-on-

change mode, the MCP2505 will send a transmit

message with the appropriate data. It is possible that

more than one A/D channel has a change-of-state

condition. This does not pose a problem since all

analog channel data is provided in the transmit

message.

REGISTER 7-1:

A/D MODULE RESULT REGISTER MSB (ADRESNH)

R-x

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

bit 7

bit 0

bit 7-0

AD9:AD2: Most Significant A/D Result bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 7-2:

A/D MODULE RESULT REGISTER LSB (ADRESNL)

R-x

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

AD1

AD0

bit 7

bit 0

bit 7-6

bit 5-0

AD1:AD0: Least significant A/D Result bits

Unimplemented: Reads as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 42

MCP2502X/5X

REGISTER 7-3:

R/W-x

ANnCMP9 ANnCMP8 ANnCMP7 ANnCMP6 ANnCMP5 ANnCMP4 ANnCMP3 ANnCMP2

A/D MODULE COMPARE REGISTER MSB (ADCMPNH)

R/W-x R/W-x R/W-x R/W-x R/W-x

R/W-x

bit 0

bit 7

bit 7-0

ANnCMP9:ANnCMP2: Most Significant A/D Compare bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 7-4:

A/D MODULE COMPARE REGISTER LSB (ADCMPNL)

R/W-x

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

ANnCMP1 ANnCMP0

bit 7

—

bit 0

bit 7-6

bit 5-0

ANnCMP1:ANnCMP0: Least Significant A/D Compare bits

Unimplemented: Reads as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

REGISTER 7-5:

ADCON0 REGISTER

R/W-0

ADON

R/W-0

T0PS2

R/W-0

T0PS1

R/W-0

T0PS0

U-x

—

U-0

—

U-x

—

U-x

—

bit 7

bit 0

bit 7

ADON: A/D On Bit

1= A/D converter module is operating

0= A/D converter module is shut off and consumes no operating current

bit 6-4

T0PS2:T0PS0: Timer0 Prescaler Rate Select bits (used for auto-conversions)

000= 1:1 Prescaller Rate

001= 1:8 Prescaller Rate

010= 1:32 Prescaller Rate

011= 1:128 Prescaller Rate

100= 1:512 Prescaller Rate

101= 1:1024 Prescaller Rate

110= 1:2048 Prescaller Rate

111= 1:4096 Prescaller Rate

Formula: (TOSC)(1024) (Prescaler Rate)

bit 3

Reserved

bit 2

Unimplemented: Reads as ‘0’

Reserved

bit 1-0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

DS21664D-page 43

MCP2502X/5X

REGISTER 7-6:

ADCON1 REGISTER

R/W-0

ADCS1

ADCS0

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

bit 7

bit 0

bit 7-6

bit 5-4

ADCS1:ADCS0: A/D Conversion Select bits

00= FOSC/2

01= FOSC/8

10= FOSC/32

11= Reserved

VCFG1:VCFG0: Voltage Reference Configuration bits

VCFG1:VCFG0

A/D VREF+

A/D VREF-

00

01

10

11

VDD

VSS

External VREF+

VDD

VSS

External VREF-

External VREF+

bit 3-0

PCFG3:PCFG0: A/D Port Configuration Control bits*

1= Corresponding GPIO pin configured as Digital I/O

0= Corresponding GPIO pin configured as A/D Input

* corresponding data direction bit (GPDDR register) must be set for each enabled analog

channel.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 44

MCP2502X/5X

7.5

Read A/D Registers Output

Message

When the MCP2502X/5X responds to a Read A/D Regs

IRM with an OM, the analog values are contained in

Register 7-7, Register 7-8 and Register 7-9.

REGISTER 7-7:

A/D OM RESULT REGISTER (ANnH)

R-x

ANnR9

ANnR8

ANnR7

ANnR6

ANnR5

ANnR4

ANnR3

ANnR2

bit 7

bit 0

bit 7-0

ANnR9:ANnR2: Bits 9-2 of channel ‘n’ results

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 7-8:

A/D OM RESULT REGISTER (AN32L)

R-x

U-x

—

U-x

—

R-x

U-x

—

U-x

—

AN3R.1

AN3R.0

AN2R.1

AN2R.0

bit 7

bit 0

bit 7-6

bit 5-4

bit 3-2

bit 1-0

AN3R.1:AN3R.0: A/D Channel 3, bits 1:0 results

Unimplemented: Reads as ‘0’

AN2R.1:AN2R.0: A/D Channel 2, bits 1:0 results

Unimplemented: Reads as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS21664D-page 45

MCP2502X/5X

REGISTER 7-9:

A/D OM RESULT REGISTER (AN10L)

R-x

U-x

—

U-x

—

R-x

U-x

—

U-x

—

AN1R.1

AN1R.0

AN0R.1

AN0R.0

bit 7

bit 0

bit 7-6

bit 5-4

bit 3-2

bit 1-0

AN1R.1:AN1R.0: A/D Channel 1, bits 1:0 results

Unimplemented: Reads as ‘0’

AN0R.1:AN0R.0: A/D Channel 0, bits 1:0 results

Unimplemented: Reads as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

TABLE 7-2:

REGISTERS ASSOCIATED WITH THE A/D MODULE

Value on

POR

Value on

RST

Addr

Name

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

1Eh

34h

00h

01h

0Eh

0Fh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

10h

GPPIN

GP7

—

GP6

GP5

GP4

GP3

DDR3

GP2

DDR2

GP1

DDR1

GP0

0000 0000 0000 0000

-111 1111 -111 1111

GPDDR *

DDR6

DDR5

DDR4

DDR0

IOINTEN GP7TXC GP6TXC

IOINTPO GP7POL GP6POL

GP5TXC

GP5POL

T0PS1

VCFG1

GP4TXC

GP4POL

T0PS0

VCFG0

GP3TXC

GP3POL

GO/DONE

PCFG3

GP2TXC

GP2POL

—

GP1TXC

GP1POL

CHS1

GP0TXC 0000 0000 0000 0000

GP0POL 0000 0000 0000 0000

ADCON0

ADON

T0PS2

ADCS0

CHS0

0000 0-00 0000 0-00

0000 0000 0000 0000

ADCON1 ADCS1

PCFG2

PCFG1

PCFG0

ADCMP3 AN3CM AN3CMP. AN3CMP. AN3CMP. AN3CMP.5 AN3CMP.4 AN3CMP. AN3CMP2 xxxx xxxx uuuu uuuu

ADCMP3 AN3CM AN3CMP. Reserved ADPOL xx-- ---- uu-- ----

ADCMP2 AN2CM AN2CMP. AN2CMP. AN2CMP. AN2CMP.5 AN2CMP.4 AN2CMP. AN2CMP2 xxxx xxxx uuuu uuuu

ADCMP2 AN2CM AN2CMP. Reserved ADPOL xx-- ---- uu-- ----

ADCMP1 AN1CM AN1CMP. AN1CMP. AN1CMP. AN1CMP.5 AN1CMP.4 AN1CMP. AN1CMP2 xxxx xxxx uuuu uuuu

ADCMP1 AN1CM AN1CMP. Reserved ADPOL xx-- ---- uu-- ----

ADCMP0 AN0CM AN0CMP. AN0CMP. AN0CMP. AN0CMP.5 AN0CMP.4 AN0CMP. AN0CMP2 xxxx xxxx uuuu uuuu

—

ADCMP0 AN0CM AN0CMP.

STCON STEM STMS

—

Reserved

STM2

—

xx-- ---- uu-- ----

0xxx xxxx 0uuu uuuu

STBF1

STBF0

STM3

STM1

STM0

*

The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure

that the bits in the GPDDR register are maintained set (input) when using them as analog inputs.

DS21664D-page 46

MCP2502X/5X

FIGURE 8-2:

EXTERNAL CLOCK INPUT

OPERATION

8.0

8.1

SPECIAL FEATURES OF THE

MCP2502X/5X

Description

Clock from

ext. System

There are a number of special circuits in the

MCP2502X/5X that deal with the needs of real-time

applications. These features are intended to maximize

system reliability, minimize cost through elimination of

external components and provide power-saving

operating modes. These are:

OSC1

MCP2505X

Open

OSC2

• Oscillator selection

• Reset

8.2

Configuration Bits

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

• SLEEP

The configuration bits can be either programmed (read

as ‘0’) or unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped in

program memory location 2007h. The configuration

register is actually beyond program memory space and

belongs to the special test/configuration memory space

(2000h-3FFFh) that can be accessed only during

programming.

• In-Circuit Serial Programming

Several oscillator options are offered to allow the

device to fit the application. XT and HS modes allow

the device to support a wide range of crystal

frequencies while the LP crystal option saves power.

Two timers are implemented to offer necessary delays

on power-up. One is the Oscillator Start-up Timer

(OST), intended to keep the device in reset until the

crystal oscillator is stable. The other is the Power-up

Timer (PWRT), which provides a fixed delay of 72 ms

(nominal) on power-up only, designed to keep the part

in reset while the power supply stabilizes. With these

two timers on-chip, most applications need no external

reset circuitry.

8.3

Oscillator Configurations

Four different oscillator modes may be selected. The

user can program two configuration bits

(F_OSC1:F_OSC0) in the CONFIG register to select one of

these modes:

• LP = Low-Power Crystal

• XT = Crystal/Resonator

• HS = High-speed Crystal Resonator

SLEEP mode is designed to offer a very low current

power-down mode. The user can wake-up from SLEEP

through external reset, transmit-on-change or CAN bus

activity.

In all modes, a crystal or ceramic resonator is

connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 8-1). The oscillator

design requires the use of a parallel-cut crystal. The

device can also have an external clock source to drive

the OSC1/CLKIN pin (Figure 8-2).

A set of configuration bits are used to select various

options.

The device will default to HS mode if the CONFIG

register is not programmed.

FIGURE 8-1:

CRYSTAL/CERAMIC

RESONATOR

OPERATION

OSC1

TO INTERNAL

LOGIC

C1

C2

XTAL

RF

SLEEP

OSC2

MCP2505X

DS21664D-page 47

MCP2502X/5X

REGISTER 8-1:

CONFIGURATION REGISTER

U-0

—

U-0

R/W-x

R

R/W-x

R

R/W-x

R

R/W-x

R

—

bit 13

bit 8

R/W-x

R

R/W-x

R

R/W

R

RSTEN

FOSC1

FOSC0

bit 7

bit 0

bit 13-11

bit 10-3

bit 2

Unimplemented: Read as '0'

Reserved: do not attempt to modify

RSTEN: Enable RST input on GP7

1= RST input Enabled

0= RST input Disabled

bit 1-0

F_OSC1:F_OSC0: Oscillator Selection bits

11= HS oscillator

10= Reserved for Test (EC oscillator)

01= XT oscillator

00= LP oscillator

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

8.4.1

POWER-ON RESET

8.4

Reset

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.5V to 2.1V). If the

RST input on the GP7 pin is selected, the RST pin may

be tied through a series resistor to V_DD, eliminating the

need for external RC components usually required for

a Power-on Reset. A maximum rise time for V_DDis

specified in Section 9.0 “Electrical Characteristics”

of this document.

The MCP2502X/5X differentiates between two kinds of

reset:

• Power-on Reset (POR)

• External RST reset

Some registers are not affected in any reset condition.

Their status is unknown on POR and unchanged in any

other reset. Most other registers are reset to a reset

state on Power-on Reset (POR), on RST and on RST

during SLEEP. They are not affected by a wake-up from

SLEEP, which is viewed as the resumption of normal

operation. A simplified block diagram of the on-chip

reset circuit is shown in Figure 8-3. The MCP2502X/5X

has a RST noise filter in the RST reset path. The filter

will detect and ignore small pulses.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, etc.) must be met to ensure

proper operation. For additional information, refer to

AN607, “Power-up Troubleshooting”, DS00607).

DS21664D-page 48

MCP2502X/5X

FIGURE 8-3:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RST

VDD Rise

Detect

Power-on Reset

S

V

DD

OST

Chip Reset

Q

10-bit Ripple Counter

OSC1

PWRT

On-chip

RC OSC

10-bit Ripple Counter

Enable PWRT

Enable OST

as a valid message before entering Normal mode. This

feature is enabled via the PUSLP bit in the OPTREG2

register.

8.4.2

POWER-UP TIMER

The Power-up Timer (PWRT) provides a fixed, 72 ms

nominal time-out, on power-up only, from the POR. The

Power-up Timer operates on an internal RC oscillator,

with the device being kept in reset as long as the PWRT

is active. The PWRT's time delay allows V_DDto rise to

an acceptable level. The power-up time delay will vary

from device to device due to V_DD, temperature and

process variation. For more information, please see

Section 9.2 “DC Characteristics”.

While in SLEEP, the I/O ports maintain the status they

had before the SLEEP instruction was executed

(driving high, low or hi-impedance).

The following operations will not function while the

device is in SLEEP:

• A/D Module data conversion

• Auto-conversion mode

• Auto-messaging

8.5

Oscillator Start-up Timer

• PWM module and outputs

• Clock output

The Oscillator Start-up Timer (OST) provides a 512

oscillator cycle (T^OSC) delay after the PWRT delay is

complete. This ensures that the crystal oscillator has

started and stabilized and must be less than the total

time it takes (704 oscillator cycles or 44 TQ) for the

minimum standard data frame or remote transmit

message to be completed on the CAN bus once a

wake-up from SLEEP occurs. The OST time-out is

invoked only on Power-on Reset or wake-up from

SLEEP.

8.6.1

WAKE-UP FROM SLEEP

The MCP2502X/5X can wake-up from SLEEP through

one of the following events:

• External reset input on RST pin

• Transmit-on-change due to edge detected on

GPIO pin

• Activity detected on CAN bus

For the device to wake-up due to a GPIO transmit-on-

change, the corresponding interrupt enable bit must be

set (enabled). Wake-up occurs regardless of the state

of the GIE bit.

8.6

Power-down Mode (SLEEP)

Power-down mode (or SLEEP) is enabled via the

SLPEN bit in the OPTREG2 register. When enabled,

the MCP2502X/5X will enter SLEEP once the CAN bus

has been idle for a minimum 1408 bit times while in

Normal mode.

If a wake-up from SLEEP is caused by activity on the

CAN bus, the message that caused the wake-up will not

be received or acknowledged by the MCP2502X/5X.

Additionally, the device may be configured to enter

SLEEP while in Listen-only mode immediately after

power-up if there is no activity on the CAN bus.

Subsequent CAN bus activity will wake the device up

from SLEEP and the NEXT message will be confirmed

DS21664D-page 49

MCP2502X/5X

8.7

In-Circuit Serial Programming

The MCP2502X/5X can be serially programmed while

in the end application circuit. This is simply done with

two lines for clock and data, and three other lines for

power, ground and the programming voltage. This

allows customers to manufacture boards with

unprogrammed devices and then program the device

just before shipping the product, also allowing the

most recent firmware (or a custom firmware) to be

programmed.

The device is placed into a program/verify mode by

holding the GP4 and GP5 pins low while raising GP7

(VPP) pin from VIL to VIH (see the MCP2502X/5X

programming specification, “MCP250XX In-Circuit

Serial Programming™ (ICSP)”, DS20072, for more

information). GP4 becomes the programming data and

GP5 becomes the programming clock. Both GP4 and

GP5 are Schmitt Trigger inputs in this mode. The signal

definitions are summarized in Table 8-1

TABLE 8-1:

IN-CIRCUIT SERIAL

PROGRAMMING PIN

FUNCTIONS

Number

Programming Mode

Pin Name

Function

VSS

GP4

GP5

GP7

VDD

7

5

Ground

Data

6

Clock

VPP

11

14

Power

DS21664D-page 50

MCP2502X/5X

9.0

9.1

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings†

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage temperature ...............................................................................................................................-65°C to +150°C

Voltage on any pin with respect to Vss (except VDD and RST)....................................................... -0.3V to (VDD + 0.6V)

VDD................................................................................................................................................................... 0V to 7.0V

Voltage on RST with respect to Vss.................................................................................................................. 0V to 14V

Total power dissipation (Note 1) ..............................................................................................................................1.0 W

Maximum source current out of VSS pin ...............................................................................................................300 mA

Maximum sink current into VDD pin.......................................................................................................................250 mA

Input clamp current, Iik (Vi < 0 or Vi > VDD) ..........................................................................................................±20 mA

Output clamp current, Iok (VO < 0 or VO > VDD)....................................................................................................±20 mA

Maximum current sunk by any I/O pin.....................................................................................................................25 mA

Maximum current sourced by any input pin ............................................................................................................25 mA

Maximum current sunk by GPIO port....................................................................................................................200 mA

Maximum current sourced by GPIO port ..............................................................................................................200 mA

Soldering temperature of leads (10 seconds)....................................................................................................... +300°C

ESD protection on all pins .................................................................................................................................................. ≥ 3.5 kV

Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

FIGURE 9-1:

MCP2505X VOLTAGE-FREQUENCY GRAPH

6.0V

5.5V

5.0V

4.5V

4.0V

MCP2505X

4.5V

3.5V

3.0V

2.7V

2.0V

25 MHz

8 MHz

Frequency

Fmax = (9.44 MHz/V) (VDDAPPMIN - 2.7V) + 8 MHz

Note: VDDAPPMIN is the minimum voltage of the MCP2505X device in the application.

Characterized and not 100% tested.

DS21664D-page 51

MCP2502X/5X

9.2

DC Characteristics

Industrial (I):

TAMB = -40°C to +85°C VCC = 2.7V to 5.5V

DC Characteristics

Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V

Param.

Sym

Characteristics

Supply Voltage

Min

Max

Units

Test Conditions

No.

VDD

2.7

4.5

5.5

V

XT and LP OSC configuration

HS OSC configuration (Note 2)

SVDD VDD Rise Rate to ensure

internal power-on reset signal

0.05

—

V/ms (Note 3)

High-level input voltage

VIH

GPIO pins

2

VDD+0.3

VDD

V

RXCAN (Schmitt Trigger)

OSC1

.7 VDD

.85 VDD

VDD

Low-level input voltage

RXCAN (Schmitt Trigger)

GPIO pins

—

VIL

VSS

-0.3

VSS

0.2 VDD

0.5V

V

OSC1

0.2 VDD

Low-level output voltage

TXCAN GPIO pins

High-level output voltage

TXCAN, GPIO pins

VOL

VOH

—

0.6

—

V

IOL = 8.5 mA, VDD = 4.5V

VDD -0.7

IOH =-3.0 mA, VDD = 4.5V,

I-temp

Input leakage current

All I/O except OSC1, GP7

OSC1, GP7 pin

ILI

-1

-5

—

+1

+5

7

µA

pF

CINT Internal Capacitance

(all inputs and outputs, except

TAMB = 25°C, fC = 1.0 MHz,

VDD = 5.0V (Note 3)

GP7)

GP7

—

15

20

pF

IDD

Operating Current

mA

XT OSC VDD = 5.5V;

F^OSC= 25 MHz

IDDS Standby Current

(CAN Sleep Mode)

—

30

µA

Inputs tied to VDD or VSS

Note 1: This is the limit to which V_DDcan be lowered in SLEEP mode without losing RAM data.

2: Refer to Figure 9-1.

3: This parameter is periodically sampled and not 100% tested.

DS21664D-page 52

MCP2502X/5X

9.3

AC Characteristics

Industrial (I):

TAMB = -40°C to +85°C VCC = 2.7V to 5.5V

AC Characteristics

Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V

Param.

Sym

Characteristics

CLKIN Frequency

Min

Max

Units

Test Conditions

No.

FOS

DC

0.1

4

25

200

4

MHz XT osc mode

MHz HS osc mode (Note 3)

kHz LP osc mode

FOS

Oscillator Frequency

CLKIN Period

MHz XT osc mode

25

200

—

MHz HS osc mode (Note 3)

kHz LP osc mode

5

1

T^OSC

250

40

5

ns

µs

ns

µs

ns

µs

ns

µs

XT osc mode

HS osc mode

LP osc mode

XT osc mode

HS osc mode

LP osc mode

XT osc mode

HS osc mode

LP osc mode

XT osc mode (Note 1)

HS osc mode (Note 1)

LP osc mode (Note 1)

VDD = 4.5 V (Note 2)

Note 2

—

Oscillator Period

0.25

40

5

10

250

—

3

4

TOSL

TOSH

CLKIN High or Low Time

CLKIN Rise or Fall Time

100

15

2.5

—

Tosr

25

50

15

60

100

200

40

—

10

12

13

20

21

30

32

33

34

TDCLKOUT CLKOUT Propagation Delay

—

TCKR

TIOR

TIOF

CLKOUT Rise Time

CLKOUT Fall Time

Port output rise time

Port output fall time

RST Pulse Low

—

Note 2

—

Note 1

—

Note 1

TMCL

TOST

TPWRT

TIOZ

2

VDD = 5V

Oscillation Start-up Timer

Power-up Timer

512

28

—

Tosc TOSC = OSC1 period

132

2.1

ms

µs

VDD = 5V

I/O Hi-impedance from RST

low

Note 1

TPWMR

TPWMF

TAD

PWM output rise time

PWM output fall time

A/D clock period

—

25

—

13

ns

Note 1

1.6

3.0

—

µs

VREFΔ ≥ 2.5V

VREF full range

µs

TCNV

Conversion Time (not

TAD

including acquisition time)

Note 1: This parameter is periodically sampled and not 100% tested.

2: Measurements are taken with CLKOUT output configured as 4 x TOSC.

3: Refer to Figure 9-1.

DS21664D-page 53

MCP2502X/5X

FIGURE 9-2:

I/O TIMING

OSC1

I/O Pin

(input)

I/O Pin

(output)

New Value

Old Value

20, 21

10

13

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins.

12

FIGURE 9-3:

RESET, OST AND POWER-UP-TIMER

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

RESET

34

I/O Pins

DS21664D-page 54

MCP2502X/5X

9.4

A/D Converter Characteristics

Industrial (I):

TAMB = -40°C to +85°C VCC = 2.7V to 5.5V

AC Converter Characteristics

Param.

Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V

Sym

Characteristics

Min

Max

Units

Test Conditions

No.

NR

A/D resolution

—

10-bits

VREF = VDD = 5.12V, VSS ≤ in

≤VREF

NINT

NDIF

NG

A/D Integral error

A/D Differential error

A/D Gain error

—

less than

±1 LSb

VREF+ = VDD = 5.12V,

VSS- = VSS = 0 V (I TEMP)

less than

±1 LSb

VREF+ = VDD = 5.12V,

VSS- = VSS = 0 V (I TEMP)

less than

±1 LSb

VREF+ = VDD = 5.12V,

VSS- = VSS = 0 V

NOFF

A/D Offset error

less than

±2 LSb

VREF+ = VDD = 5.12V,

VSS- = VSS = 0 V

Monotonicity

—

V^SS≤ in ≤VREF

VREF

VREF+

VREF-

Reference Voltage

4.096

VDD+0.3

V

Absolute minimum to ensure

10-bit accuracy.

Reference V high

Reference V low

Analog input V

VREF-

VDD+0.3

VREF+

Minimum resolution for A/D is

1 mV.

VSS-0.3

Minimum resolution for A/D is

1 mV.

VAIN

ZAIN

VREF-

—

VREF+

2.5

V

Recommended impedance

of analog voltage source

kΩ

Note

IREF

VREF input current

—

10

µA

NHYS

Analog Transmit-on-change

Hysteresis

2 LSb

Specified by design (see

Section 4.5.2.1 “Hysteresis

Function”)

Note: Design guidance only

DS21664D-page 55

MCP2502X/5X

NOTES:

DS21664D-page 56

MCP2502X/5X

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

14-Lead PDIP (300 mil)

Example:

e

3

XXXXXXXXXXXXXX

MCP25050

XXXXXXXXXXXXXX

YYWWNNN

0725NNN

14-Lead SOIC (208 mil)

Example:

XXXXXXXXXXX

MCP25055

XXXXXXXXXXX

e

3

YYWWNNN

0737NNN

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21664D-page 57

MCP2502X/5X

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

c

A1

b1

b

e

eB

Units

INCHES

NOM

14

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.735

.115

.008

.045

.014

–

.130

–

.310

.250

.750

.130

.010

.060

.018

–

.325

.280

.775

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-005B

DS21664D-page 58

MCP2502X/5X

14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

h

b

α

h

c

φ

A2

A

L

A1

β

L1

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

14

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff §

A2

A1

E

1.25

0.10

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

E1

D

h

3.90 BSC

8.65 BSC

Chamfer (optional)

Foot Length

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-065B

DS21664D-page 59

MCP2502X/5X

NOTES:

DS21664D-page 60

MCP2502X/5X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a)

b)

c)

MCP25020–I/P:

Industrial temperature,

PDIP package.

Temperature

Range

Package

MCP25025–I/SL: Industrial temperature,

SOIC package.

MCP25050T-E/SL: Tape and Reel,

Extended temperature,

SOIC package.

Device:

MCP25020: CAN I/O Expander

MCP25020T: CAN I/O Expander (Tape and Reel)

MCP25025: CAN I/O Expander

MCP25025T: CAN I/O Expander (Tape and Reel)

MCP25050: Mixed Signal CAN I/O Expander

MCP25050T: Mixed Signal CAN I/O Expander

(Tape and Reel)

d)

MCP25055-I/SL:

Industrial temperature

SOIC package.

MCP25055: Mixed Signal CAN I/O Expander

MCP25055T: Mixed Signal CAN I/O Expander

(Tape and Reel)

Temperature Range:

Package:

I

E

=

-40°C to +85°C

-40°C to +125°C (not available on MCP25025

or MCP25055 devices)

P

SL

=

Plastic DIP (300 mil Body), 14-lead

Plastic SOIC (150 mil Body), 14-lead

DS21664D-page 61

MCP2502X/5X

NOTES:

DS21664D-page 62

MCP2502X/5X

APPENDIX A: REVISION HISTORY

Revision D (January 2007)

This revision includes updates to the packaging

diagrams.

DS21664D-page 63

NOTES:

DS21664D-page 64

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS21664D-page 65

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS21664D-page 66


型号：	MCP25020TI/P
厂家：	MICROCHIP
描述：	CAN I/O Expander Family CAN I / O扩展器系列
文件：	总66页 (文件大小：1110K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP25020TI/P [MICROCHIP]

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