MCP2510T-ISO_技术文档

M

MCP25

Stand-Alone CAN Controller with SPI^ΤΜInterfac

FEATURES

DESCRIPTION

• Implements Full CAN V2.0A and V2.0B at 1 Mb/s

The Microchip Technology Inc. MCP2510 is

troller Area Network (CAN) protocol contro

menting CAN speciﬁcation V2.0 A/B. It sup

1.2, CAN 2.0A, CAN 2.0B Passive, and CAN

versions of the protocol, and is capable of t

and receiving standard and extended mess

also capable of both acceptance ﬁltering an

management. It includes three transmit buffe

receive buffers that reduce the amount of mic

(MCU) management required. The MCU com

is implemented via an industry standard Se

eral Interface (SPI ) with data rates up to 5M

- 0 - 8 byte message length

- Standard and extended data frames

- Programmable bit rate up to 1 Mb/s

- Support for remote frames

- Two receive buffers with prioritized message

storage

- Six full acceptance ﬁlters

- Two full acceptance ﬁlter masks

- Three transmit buffers with prioritization and

abort features

- Loop-back mode for self test operation

• Hardware Features

PACKAGE TYPES

18 LEAD PDIP

- High Speed SPI Interface (5 MHz at 4.5V)

- Supports SPI modes 0,0 and 1,1

1

VDD

TXCAN

18

2

3

4

5

RESET

CS

17

16

RXCAN

- Clock out pin with programmable prescaler

- Interrupt output pin with selectable enables

CLKOUT

- ‘Buffer full’ output pins conﬁgure able as

interrupt pins for each receive buffer or as

general purpose digital outputs

SO

SI

15

14

TX0RTS

TX1RTS

13

12

11

10

SCK

6

7

TX2RTS

OSC2

- ‘Request to Send’ input pins conﬁgure able

as control pins to request immediate mes-

sage transmission for each transmit buffer or

as general purpose digital inputs

INT

RX0BF

RX1BF

8

9

OSC1

Vss

- Low Power Sleep mode

18 LEAD SOIC

• Low power CMOS technology

- Operates from 2.7V to 5.5V

1

18

VDD

TXCAN

RXCAN

CLKOUT

TX0RTS

TX1RTS

TX2RTS

OSC2

17

16

15

14

13

12

2

3

4

5

6

7

8

9

RESET

- 5 mA active current typical

CS

SO

SI

- 10 µA standby current typical at 5.5V

• 18-pin PDIP/SOIC and 20-pin TSSOP packages

• Temperature ranges supported:

SCK

INT

11

10

-40°C to +85°C

-40°C to +125°C

- Industrial (I):

- Extended (E):

OSC1

RX0BF

RX1BF

Vss

20 LEAD TSSOP

20

19

18

17

16

15

14

13

12

1

2

3

4

5

6

7

8

VDD

TXCAN

RXCAN

CLKOUT

TX0RTS

TX1RTS

NC

RESET

CS

SO

SI

NC

SCK

INT

TX2RTS

OSC2

OSC1

Vss

9

10

RX0BF

RX1BF

11

SPI is a trademark of Motorola Inc.

1999 Microchip Technology Inc.

Preliminary

DS212

MCP2510

Table of Contents

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

Device Functionality..................................................................................................................................................................... 3

CAN Message Frames ................................................................................................................................................................ 7

Message Transmission.............................................................................................................................................................. 15

Message Reception................................................................................................................................................................... 21

Bit Timing................................................................................................................................................................................... 33

Error Detection........................................................................................................................................................................... 39

Interrupts.................................................................................................................................................................................... 43

Oscillator.................................................................................................................................................................................... 47

Modes of Operation ................................................................................................................................................................... 49

10.0 Register Map ............................................................................................................................................................................. 53

11.0 SPI Interface.............................................................................................................................................................................. 55

12.0 Electrical Characteristics ........................................................................................................................................................... 59

13.0 Packaging Information............................................................................................................................................................... 63

On-line Support ................................................................................................................................................................................... 67

Reader Response ............................................................................................................................................................................... 68

Product Identification System .............................................................................................................................................................. 69

Index ................................................................................................................................................................................................... 71

List Of Figures..................................................................................................................................................................................... 73

List Of Tables ...................................................................................................................................................................................... 73

List Of Registers................................................................................................................................................................................... 73

Worldwide Sales and Service .............................................................................................................................................................. 74

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended

workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the

revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure

that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing

or appears in error, please:

•

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We appreciate your assistance in making this a better document.

DS21291B-page 2

Preliminary

1999 Microchip Technology Inc.

MCP2510

The MCU interfaces to the device via the SPI interface.

Writing to and reading from all registers is done using

standard SPI read and write commands.

1.0

DEVICE FUNCTIONALITY

1.1

Overview

Interrupt pins are provided to allow greater system flex-

ibility. There is one multi-purpose interrupt pin as well

as specific interrupt pins for each of the receive regis-

ters that can be used to indicate when a valid message

has been received and loaded into one of the receive

buffers. Use of the specific interrupt pins is optional,

and the general purpose interrupt pin as well as status

registers (accessed via the SPI interface) can also be

used to determine when a valid message has been

received.

The MCP2510 is a stand-alone CAN controller devel-

oped to simplify applications that require interfacing

with a CAN bus. A simple block diagram of the

MCP2510 is shown in Figure 1-1. The device consists

of three main blocks:

1. the CAN protocol engine,

2. the control logic and SRAM registers that are

used to configure the device and its operation,

and

3. the SPI protocol block.

There are also three pins available to initiate immediate

transmission of a message that has been loaded into

one of the three transmit registers. Use of these pins is

optional and initiating message transmission can also

be done by utilizing control registers accessed via the

SPI interface.

A typical system implementation using the device is

shown in Figure 1-2.

The CAN protocol engine handles all functions for

receiving and transmitting messages on the bus. Mes-

sages are transmitted by first loading the appropriate

message buffer and control registers. Transmission is

initiated by using control register bits, via the SPI inter-

face, or by using the transmit enable pins. Status and

errors can be checked by reading the appropriate reg-

isters. Any message detected on the CAN bus is

checked for errors and then matched against the user

defined filters to see if it should be moved into one of

the two receive buffers.

Table 1-1 gives a complete list of all of the pins on the

MCP2510.

RXCAN

2 RX Buffers

CAN

SPI

Interface

Logic

CS

SCK

SI

6

Acceptance

Filters

3 TX

Protocol

SPI

Bus

Buffers

Engine

Message Assembly

Buffer

TXCAN

SO

Control Logic

INT

RX0BF

RX1BF

TX0RTS

TX1RTS

TX2RTS

FIGURE 1-1: Block Diagram

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 3

MCP2510

Main

System

Controller

MCP2510

CAN

Transceiver

CAN

BUS

CAN

Transceiver

MCP2510

SPI

INTERFACE

Node

Controller

FIGURE 1-2: Typical System Implementation

DIP/

SOIC

Pin #

TSSOP

Pin #

I/O/P

Type

Name

Description

TXCAN

RXCAN

CLKOUT

TX0RTS

TX1RTS

TX2RTS

OSC2

OSC1

V_SS

1

2

1

2

O

I

Transmit output pin to CAN bus

Receive input pin from CAN bus

3

O

I

Clock output pin with programmable prescaler

4

Transmit buffer TXB0 request to send or general purpose digital input.

Transmit buffer TXB1 request to send or general purpose digital input.

Transmit buffer TXB2 request to send or general purpose digital input.

Oscillator output

5

I

6

7

I

7

8

O

I

8

9

Oscillator input

9

10

11

12

13

14

16

17

18

19

20

6,15

P

O

I

Ground reference for logic and I/O pins

Receive buffer RXB1 interrupt pin or general purpose digital output

Receive buffer RXB0 interrupt pin or general purpose digital output

Interrupt output pin

RX1BF

RX0BF

INT

10

11

12

13

14

15

16

17

18

—

SCK

Clock input pin for SPI interface

SI

I

Data input pin for SPI interface

SO

O

I

Data output pin for SPI interface

CS

Chip select input pin for SPI interface

Active low device reset input

RESET

V_DD

I

P

—

Positive supply for logic and I/O pins

NC

No internal connection

Note: Type Identification: I=Input; O=Output; P=Power

TABLE 1-1: Pin Descriptions

DS21219B-page 4

Preliminary

1999 Microchip Technology Inc.

MCP2510

1.2

Transmit/Receive Buffers

The MCP2510 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a

total of six acceptance filters. Figure 1-3 is a block diagram of these buffers and their connection to the protocol engine.

Acceptance Mask

RXM1

BUFFERS

Acceptance Filter

RXF2

Acceptance Mask

RXM0

Acceptance Filter

RXF3

A

c

e

p

t

A

c

e

p

t

TXB0

TXB1

TXB2

Acceptance Filter

RXF0

Acceptance Filter

RXF4

Acceptance Filter

RXF1

Acceptance Filter

RXF5

R

X

B

0

R

X

B

1

M

A

B

Identifier

Message

Queue

Control

Transmit Byte Sequencer

Data Field

Receive

Error

Counter

REC

TEC

PROTOCOL

ENGINE

Transmit

Error

Counter

ErrPas

BusOff

Transmit<7:0>

Shift<14:0>

Receive<7:0>

{Transmit<5:0>, Receive<8:0>}

Comparator

Protocol

Finite

State

Machine

CRC<14:0>

Bit

Timing

Logic

Transmit

Logic

Clock

Generator

TX

RX

Configuration

Registers

FIGURE 1-3: CAN Buffers and Protocol Engine Block Diagram

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 5

MCP2510

1.3

CAN Protocol Engine

1.6

Error Management Logic

The Error Management Logic is responsible for the fault

confinement of the CAN device. Its two counters, the

Receive Error Counter (REC) and the Transmit Error

Counter (TEC), are incremented and decremented by

commands from the Bit Stream Processor. According to

the values of the error counters, the CAN controller is set

into the states error-active, error-passive or bus-off.

The CAN protocol engine combines several functional

blocks, shown in Figure 1-4. These blocks and their

functions are described below.

1.4

Protocol Finite State Machine

The heart of the engine is the Finite State Machine

(FSM). This state machine sequences through mes-

sages on a bit by bit basis, changing states as the fields

of the various frame types are transmitted or received.

The FSM is a sequencer controlling the sequential data

stream between the TX/RX Shift Register, the CRC Reg-

ister, and the bus line. The FSM also controls the Error

Management Logic (EML) and the parallel data stream

between the TX/RX Shift Registers and the buffers. The

FSM insures that the processes of reception, arbitration,

transmission, and error signaling are performed accord-

ing to the CAN protocol. The automatic retransmission of

messages on the bus line is also handled by the FSM.

1.7

Bit Timing Logic

The Bit Timing Logic (BTL) monitors the bus line input

and handles the bus related bit timing according to the

CAN protocol. The BTL synchronizes on a recessive to

dominant bus transition at Start of Frame (hard syn-

chronization) and on any further recessive to dominant

bus line transition if the CAN controller itself does not

transmit a dominant bit (resynchronization). The BTL

also provides programmable time segments to com-

pensate for the propagation delay time, phase shifts,

and to define the position of the Sample Point within the

bit time. The programming of the BTL depends upon

the baud rate and external physical delay times.

1.5

Cyclic Redundancy Check

The Cyclic Redundancy Check Register generates the

Cyclic Redundancy Check (CRC) code which is trans-

mitted after either the Control Field (for messages with

0 data bytes) or the Data Field, and is used to check the

CRC field of incoming messages.

Tx

Rx

Bit Timing Logic

Transmit Logic

SAM

REC

Receive

Sample<2:0>

Error Counter

TEC

StuffReg<5:0>

Transmit

ErrPas

Majority

Decision

Error Counter

BusOff

BusMon

Comparator

CRC<14:0>

Comparator

Protocol

FSM

Shift<14:0>

(Transmit<5:0>, Receive<7:0>)

Receive<7:0>

RecData<7:0>

Transmit<7:0>

TrmData<7:0>

Rec/Trm Addr.

Interface to Standard Buffer

FIGURE 1-4: CAN Protocol Engine Block Diagram

DS21219B-page 6

Preliminary

1999 Microchip Technology Inc.

MCP2510

It should be noted that if arbitration remains unresolved

after transmission of the first 11 bits of the identifier,

and one of the nodes involved in the arbitration is send-

ing a standard CAN frame (11-bit identifier), then the

standard CAN frame will win arbitration due to the

assertion of a dominant lDE bit. Also, the SRR bit in an

extended CAN frame must be recessive to allow the

assertion of a dominant RTR bit by a node that is send-

ing a standard CAN remote frame.

2.0

CAN MESSAGE FRAMES

The MCP2510 supports Standard Data Frames,

Extended Data Frames, and Remote Frames (Standard

and Extended) as defined in the CAN 2.0B specification.

2.1

Standard Data Frame

The CAN Standard Data Frame is shown in Figure 2-1.

In common with all other frames, the frame begins with

a Start Of Frame (SOF) bit, which is of the dominant

state, which allows hard synchronization of all nodes.

The SRR and lDE bits are followed by the remaining 18

bits of the identifier (Extended lD) and the remote trans-

mission request bit.

The SOF is followed by the arbitration field, consisting

of 12 bits; the 11-bit ldentifier and the Remote Trans-

mission Request (RTR) bit. The RTR bit is used to dis-

tinguish a data frame (RTR bit dominant) from a remote

frame (RTR bit recessive).

To enable standard and extended frames to be sent

across a shared network, it is necessary to split the

29-bit extended message identifier into 11-bit (most

significant) and 18-bit (least significant) sections. This

split ensures that the lDE bit can remain at the same bit

position in both standard and extended frames.

Following the arbitration field is the control field, con-

sisting of six bits. The first bit of this field is the Identifier

Extension (IDE) bit which must be dominant to specify

a standard frame. The following bit, Reserved Bit Zero

(RB0), is reserved and is defined to be a dominant bit

by the can protocol. the remaining four bits of the con-

trol field are the Data Length Code (DLC) which speci-

fies the number of bytes of data contained in the

message.

Following the arbitration field is the six-bit control field.

the first two bits of this field are reserved and must be

dominant. the remaining four bits of the control field are

the Data Length Code (DLC) which specifies the num-

ber of data bytes contained in the message.

The remaining portion of the frame (data field, CRC

field, acknowledge field, end of frame and lntermission)

is constructed in the same way as for a standard data

frame (see Section 2.1).

After the control field is the data field, which contains

any data bytes that are being sent, and is of the length

defined by the DLC above (0-8 bytes).

2.3

Remote Frame

The Cyclic Redundancy Check (CRC) Field follows the

data field and is used to detect transmission errors. The

CRC Field consists of a 15-bit CRC sequence, followed

by the recessive CRC Delimiter bit.

Normally, data transmission is performed on an auton-

omous basis by the data source node (e.g. a sensor

sending out a data frame). It is possible, however, for a

destination node to request data from the source. To

accomplish this, the destination node sends a remote

frame with an identifier that matches the identifier of the

required data frame. The appropriate data source node

will then send a data frame in response to the remote

frame request.

The final field is the two-bit acknowledge field. During

the ACK Slot bit, the transmitting node sends out a

recessive bit. Any node that has received an error free

frame acknowledges the correct reception of the frame

by sending back a dominant bit (regardless of whether

the node is configured to accept that specific message

or not). The recessive acknowledge delimiter com-

pletes the acknowledge field and may not be overwrit-

ten by a dominant bit.

There are two differences between a remote frame

(shown in Figure 2-3) and a data frame. First, the RTR

bit is at the recessive state, and second, there is no

data field. In the event of a data frame and a remote

frame with the same identifier being transmitted at the

same time, the data frame wins arbitration due to the

dominant RTR bit following the identifier. In this way, the

node that transmitted the remote frame receives the

desired data immediately.

2.2

Extended Data Frame

In the Extended CAN Data Frame, shown in Figure 2-2,

the SOF bit is followed by the arbitration field which

consists of 32 bits. The first 11 bits are the most signif-

icant bits (Base-lD) of the 29-bit identifier. These 11 bits

are followed by the Substitute Remote Request (SRR)

bit which is defined to be recessive. The SRR bit is fol-

lowed by the lDE bit which is recessive to denote an

extended CAN frame.

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 7

MCP2510

2.4

Error Frame

2.5

Overload Frame

An Error Frame is generated by any node that detects

a bus error. An error frame, shown in Figure 2-4, con-

sists of two fields, an error flag field followed by an error

delimiter field. There are two types of error flag fields.

Which type of error flag field is sent depends upon the

error status of the node that detects and generates the

error flag field.

An Overload Frame, shown in Figure 2-5, has the same

format as an active error frame. An overload frame,

however can only be generated during an lnterframe

space. In this way an overload frame can be differenti-

ated from an error frame (an error frame is sent during

the transmission of a message). The overload frame

consists of two fields, an overload flag followed by an

overload delimiter. The overload flag consists of six

dominant bits followed by overload flags generated by

other nodes (and, as for an active error flag, giving a

maximum of twelve dominant bits). The overload delim-

iter consists of eight recessive bits. An overload frame

can be generated by a node as a result of two condi-

tions. First, the node detects a dominant bit during the

interframe space which is an illegal condition. Second,

due to internal conditions the node is not yet able to

start reception of the next message. A node may gen-

erate a maximum of two sequential overload frames to

delay the start of the next message.

If an error-active node detects a bus error then the

node interrupts transmission of the current message by

generating an active error flag. The active error flag is

composed of six consecutive dominant bits. This bit

sequence actively violates the bit stuffing rule. All other

stations recognize the resulting bit stuffing error and in

turn generate error frames themselves, called error

echo flags. The error flag field, therefore, consists of

between six and twelve consecutive dominant bits

(generated by one or more nodes). The error delimiter

field completes the error frame. After completion of the

error frame, bus activity returns to normal and the inter-

rupted node attempts to resend the aborted message.

2.6

Interframe Space

If an error-passive node detects a bus error then the

node transmits an error-passive flag followed by the

error delimiter field. The error-passive flag consists of

six consecutive recessive bits, and the error frame for

an error-passive node consists of 14 recessive bits.

From this, it follows that unless the bus error is detected

by the node that is actually transmitting, the transmis-

sion of an error frame by an error-passive node will not

affect any other node on the network. If the transmitting

node generates an error-passive flag then this will

cause other nodes to generate error frames due to the

resulting bit stuffing violation. After transmission of an

error frame, an error-passive node must wait for six

consecutive recessive bits on the bus before attempt-

ing to rejoin bus communications.

The lnterframe Space separates a preceeding frame

(of any type) from a subsequent data or remote frame.

The interframe space is composed of at least three

recessive bits called the Intermission. This is provided

to allow nodes time for internal processing before the

start of the next message frame. After the intermission,

the bus line remains in the recessive state (bus idle)

until the next transmission starts.

The error delimiter consists of eight recessive bits and

allows the bus nodes to restart bus communications

cleanly after an error has occurred.

DS21219B-page 8

Preliminary

1999 Microchip Technology Inc.

MCP2510

l e D K A C

o t S B l k i t A c

l e C D C R

C 0 D L

3 C D L

R B 0

t

e v d B s i e r R

E I D

R R T

0 I D

3 I D

0 1 I D

e

a r m F o t f a r S t

FIGURE 2-1: Standard Data Frame

S

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 9

MCP2510

l e D K A C

o t S B l k i t A c

l e

R C D

C 0 D L

C 3 D L

R B 0

s t i

e v d r b e s e R

R B 1

R R T

E I D 0

E I D 1 7

I D E

S R R

I D 0

3 I D

0 1 I D

a r m e F o f t r a S t

FIGURE 2-2: Extended Data Frame

DS21219B-page 10

Preliminary

1999 Microchip Technology Inc.

MCP2510

l e D K A C

k S A l o c t B i t

C D C e R

l

0 C D L

3 C D L

0

1

R B

t i s b d e v r e s e R

R R T

D 0 E I

D 1 E 7 I

E I D

R S R

I D 0

3 I D

0 1 I D

a r m e F o f t r a S t

FIGURE 2-3: Remote Data Frame

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 11

MCP2510

C 0 D L

C 3 D L

0

R B

I D E

t

B d i e v r s e R

R R T

0 I D

3 I D

0 1 I D

a r m e F o f t r a S t

FIGURE 2-4: Error Frame

DS21219B-page 12

Preliminary

1999 Microchip Technology Inc.

MCP2510

l e D K A C

B i S l k o t A c

t

l

D e C R C

C 0 D L

C 3 D L

R B 0

E I D

R R T

0 I D

0 1 I D

e

a r m F o t f a r S t

FIGURE 2-5: Overload Frame

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 13

MCP2510

NOTES:

DS21219B-page 14

Preliminary

1999 Microchip Technology Inc.

MCP2510

When TXBNCTRL.TXREQ is set, the TXBNCTRL.ABTF,

TXBNCTRL.MLOA and TXBNCTRL.TXERR bits will be

cleared.

3.0

MESSAGE TRANSMISSION

3.1

Transmit Buffers

Setting the TXBNCTRL.TXREQ bit does not initiate a

message transmission, it merely flags a message

buffer as ready for transmission. Transmission will start

when the device detects that the bus is available. The

device will then begin transmission of the highest prior-

ity message that is ready.

The MCP2510 implements three Transmit Buffers. Each

of these buffers occupies 14 bytes of SRAM and are

mapped into the device memory maps. The first byte,

TXBNCTRL, is a control register associated with the mes-

sage buffer. The information in this register determines

the conditions under which the message will be transmit-

ted and indicates the status of the message transmission.

(see Register 3-2). Five bytes are used to hold the stan-

dard and extended identifiers and other message arbitra-

tion information (see Register 3-3 through Register 3-8).

The last eight bytes are for the eight possible data bytes

of the message to be transmitted (see Register 3-8).

When the transmission has completed successfully the

TXBNCTRL.TXREQ bit will be cleared, the CAN-

INTF.TXNIF bit will be set, and an interrupt will be gen-

erated if the CANINTE.TXNIE bit is set.

If the message transmission fails, the TXBNCTRL.TXREQ

will remain set indicating that the message is still pending

for transmission and one of the following condition flags

will be set. If the message started to transmit but encoun-

tered an error condition, the TXBNCTRL. TXERR and the

CANINTF.MERRF bits will be set and an interrupt will be

generated on the INT pin if the CANINTE.MERRE bit is

set. If the message lost arbitration the TXBNCTRL.MLOA

bit will be set.

For the MCU to have write access to the message buffer,

the TXBNCTRL.TXREQ bit must be clear, indicating that

the message buffer is clear of any pending message to be

transmitted. At a minimum, the TXBNSIDH, TXBNSIDL,

and TXBNDLC registers must be loaded. If data bytes are

present in the message, the TXBNDm registers must also

be loaded. If the message is to use extended identifiers,

the TXBNEIDm registers must also be loaded and the

TXBNSIDL.EXIDE bit set.

3.4

TXnRTS Pins

Prior to sending the message, the MCU must initialize

the CANINTE.TXINE bit to enable or disable the gener-

ation of an interrupt when the message is sent. The

MCU must also initialize the TXBNCTRL.TXP priority

bits (see Section 3.2).

The TXNRTS Pins are input pins that can be configured

as request-to-send inputs, which provides a secondary

means of initiating the transmission of a message from

any of the transmit buffers, or as standard digital inputs.

Configuration and control of these pins is accomplished

using the TXRTSCTRL register (see Register 3-2). The

TXRTSCTRL register can only be modified when the

MCP2510 is in configuration mode (see Section 9.0). If

configured to operate as a request to send pin, the pin

is mapped into the respective TXBNCTRL.TXREQ bit

for the transmit buffer. The TXREQ bit is latched by the

falling edge of the TXNRTS pin. The TXNRTS pins are

designed to allow them to be tied directly to the RXNBF

pins to automatically initiate a message transmission

when the RXNBF pin goes low. The TXNRTS pins have

internal pullup resistors of 100K ohms (nominal).

3.2

Transmit Priority

Transmit priority is a prioritization, within the MCP2510,

of the pending transmittable messages. This is indepen-

dent from, and not necessarily related to, any prioritiza-

tion implicit in the message arbitration scheme built into

the CAN protocol. Prior to sending the SOF, the priority

of all buffers that are queued for transmission is com-

pared. The transmit buffer with the highest priority will be

sent first. For example, if transmit buffer 0 has a higher

priority setting than transmit buffer 1, buffer 0 will be sent

first. If two buffers have the same priority setting, the

buffer with the highest buffer number will be sent first. For

example, if transmit buffer 1 has the same priority setting

as transmit buffer 0, buffer 1 will be sent first. There are

four levels of transmit priority. If TXBNCTRL.TXP<1:0>

for a particular message buffer is set to 11, that buffer has

the highest possible priority. If TXBNCTRL.TXP<1:0> for

a particular message buffer is 00, that buffer has the low-

est possible priority.

3.5

Aborting Transmission

The MCU can abort a message in a specific message

buffer by clearing the associated TXBNCTRL.TXREQ

bit. If the message has not yet started transmission, or

if the message started but loses arbitration, or if an

error occurs, the abort will be processed. The abort is

indicated by the TXBNCTRL.ABTF bits. Additionally,

setting the CANCTRL.ABAT bit will request an abort of

all pending messages. The CANCTRL.ABAT bit has to

be cleared by the MCU, typically after verifying all mes-

sages have been aborted by reading the individual

TXREQ bits or via the SPI Read Status command.

3.3

Initiating Transmission

To initiate message transmission the TXBNCTRL.TXREQ

bit must be set for each buffer to be transmitted. This can

be done by writing to the register via the SPI interface or

by setting the TXNRTS pin low for the particular transmit

buffer(s) that are to be transmitted. If transmission is initi-

ated via the SPI interface, the TXREQ bit can be set at the

same time as the TXP priority bits.

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 15

MCP2510

Start

The message transmission

sequence begins when the

device determines that the

TXBNCTRL.TXREQ for any of

the transmit registers has been

set.

Are any

No

TXBNCTRL.TXREQ

bits = 1

?

Yes

Clearing the TxBNCTRL.TXREQ

Clear:

bit while it is set, or setting the

CANCTRL.ABAT bit before the

message has started transmission

will abort the message.

TXBNCTRL.ABTF

TXBNCTRL.MLOA

TXBNCTRL.TXERR

is

Is

No

TXBNCTRL.TXREQ=0

CAN Bus available

to start transmission

?

or

CANCTRL.ABAT=1

?

Yes

Examine TXBNCTRL.TXP <1:0> to

Determine Highest Priority Message

Transmit Message

Was

No

Did

Yes

Set

Message Transmitted

Successfully?

a message error

occur?

TxBNCTRL.TXERR=1

No

Yes

Set TxBNCTRL.TXREQ=0

Was

Yes

Set

Arbitration lost during

transmission?

TxBNCTRL.MLOA=1

Yes

Generate

Interrupt

CANINTE.TXnIE=1?

No

A message can also be

aborted if a message error or

lost arbitration condition

is

occurred during transmission.

TXBNCTRL.TXREQ=0 Yes

or CANCTRL.ABAT=1

?

Set

CANTINF.TXNIF=1

The CANINTE.TXnIE bit

determines if an interrupt

should be generated when

a message is successfully

transmitted.

No

About Transmission:

Set TxBNCTRL.ABTF=1

GOTO START

FIGURE 3-1: Transmit Message Flowchart

DS21219B-page 16

Preliminary

1999 Microchip Technology Inc.

MCP2510

U-0

R-0

R/W-0

U-0

R/W-0

TXP0

bit 0

—

ABTF MLOA TXERR TXREQ

—

TXP1

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

bit 7

- n = Value at POR reset

bit 7:

bit 6:

Unimplemented: Reads as ‘0’

ABTF: Message Aborted Flag

1 = Message was aborted

0 = Message completed transmission successfully

bit 5:

bit 4:

bit 3:

MLOA: Message Lost Arbitration

1 = Message lost arbitration while being sent

0 = Message did not lose arbitration while being sent

TXERR: Transmission Error Detected

1 = A bus error occurred while the message was being transmitted

0 = No bus error occurred while the message was being transmitted

TXREQ: Message Transmit Request

1 = Buffer is currently pending transmission

(MCU sets this bit to request message be transmitted - bit is automatically cleared when

the message is sent)

0 = Buffer is not currently pending transmission

(MCU can clear this bit to request a message abort)

bit 2:

Unimplemented: Reads as ‘0’

bit 1-0: TXP<1:0>: Transmit Buffer Priority

11 = Highest Message Priority

10 = High Intermediate Message Priority

01 = Low Intermediate Message Priority

00 = Lowest Message Priority

REGISTER 3-1: TXBNCTRL Transmit Buffer N Control Register (ADDRESS: 30h, 40h, 50h)

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 17

MCP2510

U-0

R-x

R/W-0

—

B2RTS B1RTS B0RTS B2RTSM B1RTSM B0RTSM

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

bit 7

U = Unimplemented -

reads as ‘0’

- n = Value at POR reset

bit 7:

bit 6:

bit 5:

Unimplemented: Reads as ‘0’

B2RTS: TX2RTS Pin State

- Reads state of TX2RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

bit 4:

B1RTS: TX1RTX Pin State

- Reads state of TX1RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

bit 3:

bit 2:

bit 1:

bit 0:

B0RTS: TX0RTS Pin State

- Reads state of TX0RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

B2RTSM: TX2RTS Pin Mode

1 = Pin is used to request message transmission of TXB2 buffer (on falling edge)

0 = Digital input

B1RTSM: TX1RTS Pin Mode

1 = Pin is used to request message transmission of TXB1 buffer (on falling edge)

0 = Digital input

B0RTSM: TX0RTS Pin Mode

1 = Pin is used to request message transmission of TXB0 buffer (on falling edge)

0 = Digital input

REGISTER 3-2: TXRTSCTRL - TXNRTS Pin Control and Status Register (ADDRESS: 0Dh)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10

bit 7

SID9

SID8

SID7

SID6

SID5

SID4

SID3

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: SID10:SID3: Standard Identifier Bits <10:3>

REGISTER 3-3: TXBNSIDH - Transmit Buffer N Standard Identifier High (ADDRESS: 31h, 41h, 51h)

DS21219B-page 18

Preliminary

1999 Microchip Technology Inc.

MCP2510

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID2

bit 7

SID1

SID0

—

EXIDE

—

EID17 EID16

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-5: SID2:SID0: Standard Identifier Bits <2:0>

bit 4:

bit 3:

Unimplemented: Reads as '0’

EXIDE: Extended Identifier Enable

1 = Message will transmit extended identifier

0 = Message will transmit standard identifier

bit 2:

Unimplemented: Reads as '0’

bit 1-0: EID17:EID16: Extended Identifier Bits <17:16>

REGISTER 3-4: TXBNSIDL - Transmit Buffer N Standard Identifier Low (ADDRESS: 32h, 42h, 52h)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10

bit 7

EID9

EID8

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: EID15:EID8: Extended Identifier Bits <15:8>

REGISTER 3-5: TXBNEID8 - Transmit Buffer N Extended Identifier High (ADDRESS: 33h, 43h, 53h)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7

bit 7

EID6

EID5

EID4

EID3

EID2

EID1

EID0

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: EID7:EID0: Extended Identifier Bits <7:0>

REGISTER 3-6: TXBNEID0 - Transmit Buffer N Extended Identifier LOW (ADDRESS: 34h, 44h, 54h)

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 19

MCP2510

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—

RTR

—

DLC3

DLC2

DLC1

DLC0

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

bit 7

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7:

bit 6:

Unimplemented: Reads as ‘0’

RTR: Remote Transmission Request Bit

bit 5-4: Unimplemented: Reads as ‘0’

bit 3-0: DLC3:DLC0: Data Length Code

REGISTER 3-7: TXBNDLC - Transmit Buffer N Data Length Code (ADDRESS: 35h, 45h, 55h)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

TXBNDm7 TXBNDm6 TXBNDm5 TXBNDm4 TXBNDm3 TXBNDm2 TXBNDm1 TXBNDm0 R = Readable bit

W = Writable bit

C = Bit can be

cleared by

bit 7

bit 0

MCU but not set

U = Unimplemented

- reads as ‘0’

- n = Value at POR

reset

bit 7-0: TXBNDm7:TXBNDm0: Transmit Buffer N Data Field Byte m

REGISTER 3-8: TXBNDM - Transmit Buffer N Data Field Byte m (ADDRESS: 36h-3Dh, 46h-4Dh, 56h-5Dh)

DS21219B-page 20

Preliminary

1999 Microchip Technology Inc.

MCP2510

When a message is received, bits <3:0> of the RXBNCTRL

Register will indicate the acceptance filter number that

enabled reception, and whether the received message is a

remote transfer request.

4.0

MESSAGE RECEPTION

4.1

Receive Message Buffering

The MCP2510 includes two full receive buffers with

multiple acceptance filters for each. There is also a

separate Message Assembly Buffer (MAB) which acts

as a third receive buffer (see Figure 4-1).

The RXBNCTRL.RXM bits set special receive modes.

Normally, these bits are set to 00 to enable reception of

all valid messages as determined by the appropriate

acceptance filters. In this case, the determination of

whether or not to receive standard or extended mes-

sages is determined by the RFXNSIDL.EXIDE bit in the

acceptance filter register. If the RXBNCTRL.RXM bits

are set to 01 or 10, the receiver will accept only mes-

sages with standard or extended identifiers respec-

tively. If an acceptance filter has the RFXNSIDL.EXIDE

bit set such that it does not correspond with the

RXBNCTRL.RXM mode, that acceptance filter is ren-

dered useless. These two modes of RXBNCTRL.RXM

bits can be used in systems where it is known that only

standard or extended messages will be on the bus. If

the RXBNCTRL.RXM bits are set to 11, the buffer will

receive all messages regardless of the values of the

acceptance filters. Also, if a message has an error

before the end of frame, that portion of the message

assembled in the MAB before the error frame will be

loaded into the buffer. This mode has some value in

debugging a CAN system and would not be used in an

actual system environment.

4.2

Receive Buffers

Of the three Receive Buffers, the MAB is always com-

mitted to receiving the next message from the bus. The

remaining two receive buffers are called RXB0 and

RXB1 and can receive a complete message from the

protocol engine. The MCU can access one buffer while

the other buffer is available for message reception or

holding a previously received message.

The MAB assembles all messages received. These

messages will be transferred to the RXBN buffers (See

Register 4-4 to Register 4-9) only if the acceptance fil-

ter criteria are met.

Note: The entire contents of the MAB is moved into

the receive buffer once

a message is

accepted. This means that regardless of the

type of identifier (standard or extended) and

the number of data bytes received, the entire

receive buffer is overwritten with the MAB

contents. Therefore the contents of all regis-

ters in the buffer must be assumed to have

been modified when any message is

received.

4.4

RX0BF and RX1BF Pins

In addition to the INT pin which provides an interrupt

signal to the MCU for many different conditions, the

receive buffer full pins (RX0BF and RX1BF) can be

used to indicate that a valid message has been loaded

into RXB0 or RXB1, respectively.

When a message is moved into either of the receive

buffers the appropriate CANINTF.RXNIF bit is set. This

bit must be cleared by the MCU, when it has completed

processing the message in the buffer, in order to allow

a new message to be received into the buffer. This bit

provides a positive lockout to ensure that the MCU has

finished with the message before the MCP2510

attempts to load a new message into the receive buffer.

If the CANINTE.RXNIE and bit is set an interrupt will be

generated on the INT pin to indicate that a valid mes-

sage has been received.

The RXBNBF full pins can be configured to act as buffer

full interrupt pins or as standard digital outputs. Config-

uration and status of these pins is available via the

BFPCTRL register (Register 4-3). When set to operate

in interrupt mode (by setting BFPCTRL.BxBFE and

BFPCTRL.BxBFM bits to a 1), these pins are active low

and are mapped to the CANINTF.RXNIF bit for each

receive buffer. When this bit goes high for one of the

receive buffers, indicating that a valid message has

been loaded into the buffer, the corresponding RXNBF

pin will go low. When the CANINTF.RXNIF bit is cleared

by the MCU, then the corresponding interrupt pin will go

to the logic high state until the next message is loaded

into the receive buffer.

4.3

Receive Priority

RXB0 is the higher priority buffer and has two message

acceptance filters associated with it. RXB1 is the lower

priority buffer and has four acceptance filters associ-

ated with it. The lower number of acceptance filters

makes the match on RXB0 more restrictive and implies

a higher priority for that buffer. Additionally, the

RXB0CTRL register can be configured such that if

RXB0 contains a valid message, and another valid

message is received, an overflow error will not occur

and the new message will be moved into RXB1 regard-

less of the acceptance criteria of RXB1. There are also

two programmable acceptance filter masks available,

one for each receive buffer (see Section 4.5).

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 21

MCP2510

Acceptance Mask

RXM1

Acceptance Filter

RXF2

Acceptance Mask

RXM0

Acceptance Filter

RXF3

A

c

e

p

t

Acceptance Filter

RXF0

Acceptance Filter

RXF4

A

c

e

p

t

Acceptance Filter

RXF1

Acceptance Filter

RXF5

R

X

B

0

M

A

B

R

X

B

1

Identifier

Data Field

FIGURE 4-1: Receive Buffer Block Diagram

DS21219B-page 22

Preliminary

1999 Microchip Technology Inc.

MCP2510

Start

Detect

Start of

Message

?

No

Yes

Begin Loading Message into

Message Assembly Buffer (MAB)

Valid

Generate

Error

Frame

No

Message

Received

?

Yes

Yes, meets criteria

for RXBO

Yes, meets criteria

for RXB1

Message

Identifier meets

a filter criteria

?

No

Go to Start

The CANINTF.RXNIF bit

determines if the receive

register is empty and able

to accept a new message

The RXB0CTRL.BUKT

bit determines if RXB0

can roll over into RXB1

Is

RXB0CTRL.BUKT=1

Is

Yes

No

CANINTF.RX0IF=0

?

No

Yes

Is

No

Generate Overflow Error:

Set EFLG.RX0OVR

Generate Overflow Error:

Set EFLG.RX1OVR

Move message into RXB0

CANINTF.RX1IF = 0

?

Set CANINTF.RX0IF=1

Yes

Move message into RXB1

No

Is

Set RXB0CTRL.FILHIT <0>

according to which filter criteria

CANINTE.ERRIE=1

?

Set CANINTF.RX1IF=1

Yes

Go to Start

Set RXB0CTRL.FILHIT <2:0>

according to which filter criteria

was met

Yes

Generate

CANINTE.RX0IE=1?

CANINTE.RX1IE=1?

No

Interrupt on INT

No

RXB1

RXB0

Set CANSTAT <3:0> accord-

ing to which receive buffer

the message was loaded into

Yes

Are

Yes

Are

Set RXBF0

Pin = 0

Set RXBF1

Pin = 0

BFPCTRL.B0BFM=1

BFPCTRL.B1BFM=1

and

BF1CTRL.B0BFE=1

BF1CTRL.B1BFE=1

?

No

FIGURE 4-2: Message Reception Flowchart

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 23

MCP2510

U-0

R/W-0 R/W-0

RXM1 RXM0

U-0

R-0

R/W-0

R-0

—

RXRTR BUKT

BUKT1 FILHIT0

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

bit 7

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7:

Unimplemented: Reads as ‘0’

bit 6-5: RXM<1:0>: Receive Buffer Operating Mode

11 = Turn mask/filters off; receive any message

10 = Receive only valid messages with extended identifiers that meet filter criteria

01 = Receive only valid messages with standard identifiers that meet filter criteria

00 = Receive all valid messages using either standard or extended identifiers that meet filter criteria

bit 4:

bit 3:

Unimplemented: Reads as ‘0’

RXRTR: Received Remote Transfer Request

1 = Remote Transfer Request Received

0 = No Remote Transfer Request Received

bit 2:

BUKT: Rollover Enable

1 = RXB0 message will rollover and be written to RXB1 if RXB0 is full

0 = Rollover disabled

bit 1:

bit 0:

BUKT1: Read Only Copy of BUKT Bit (used internally by the MCP2510).

FILHIT<0>: Filter Hit - indicates which acceptance filter enabled reception of message

1 = Acceptance Filter 1 (RXF1)

0 = Acceptance Filter 0 (RXF0)

REGISTER 4-1: RXB0CTRL - Receive Buffer 0 Control Register (ADDRESS: 60h)

DS21219B-page 24

Preliminary

1999 Microchip Technology Inc.

MCP2510

U-0

R/W-0 R/W-0

U-0

R-0

—

RXM1 RXM0

—

RXRTR FILHIT2 FILHIT1 FILHIT0

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

bit 7

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7:

Unimplemented: Reads as ‘0’

bit 6-5: RXM<1:0>: Receive Buffer Operating Mode

11 = Turn mask/filters off; receive any message

10 = Receive only valid messages with extended identifiers that meet filter criteria

01 = Receive only valid messages with standard identifiers that meet filter criteria

00 = Receive all valid messages using either standard or extended identifiers that meet filter criteria

bit 4:

bit 3:

Unimplemented: Reads as ‘0’

RXRTR: Received Remote Transfer Request

1 = Remote Transfer Request Received

0 = No Remote Transfer Request Received

bit 2-0: FILHIT<2:0>: Filter Hit - indicates which acceptance filter enabled reception of message

101 = Acceptance Filter 5 (RXF5)

100 = Acceptance Filter 4 (RXF4)

011 = Acceptance Filter 3 (RXF3)

010 = Acceptance Filter 2 (RXF2)

001 = Acceptance Filter 1 (RXF1) (Only if BUKT bit set in RXB0CTRL)

000 = Acceptance Filter 0 (RXF0) (Only if BUKT bit set in RXB0CTRL)

REGISTER 4-2: RXB1CTRL - Receive Buffer 1 Control Register (ADDRESS: 70h)

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 25

MCP2510

U-0

R/W-0

—

B1BFS B0BFS B1BFE B0BFE B1BFM B0BFM

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

bit 7

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7:

bit 6:

bit 5:

Unimplemented: Reads as ‘0’

B1BFS: RX1BF Pin State (digital output mode only)

Reads as 0 when RX1BF is configured as interrupt pin

B0BFS: RX0BF Pin State (digital output mode only)

Reads as 0 when RX0BF is configured as interrupt pin

B1BFE: RX1BF Pin Function Enable

bit 4:

bit 3:

1 = Pin function enabled, operation mode determined by B1BFM bit

0 = Pin function disabled, pin goes to high impedance state

bit 2:

bit 1:

bit 0:

B0BFE: RX0BF Pin Function Enable

1 = Pin function enabled, operation mode determined by B0BFM bit

0 = Pin Function disabled, pin goes to high impedance state

B1BFM: RX1BF Pin Operation Mode

1 = Pin is used as interrupt when valid message loaded into RXB1

0 = Digital output mode

B0BFM: RX0BF Pin Operation Mode

1 = Pin is used as interrupt when valid message loaded into RXB0

0 = Digital output mode

REGISTER 4-3: BFPCTRL - RXNBF Pin Control and Status Register (ADDRESS: 0Ch)

R-x

SID10

bit 7

R-x

SID9

SID8

SID7

SID6

SID5

SID4

SID3

R = Readable bit

W = Writable bit

C = Bit can be cleared by

bit 0

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: SID10:SID3: Standard Identifier Bits <10:3>

REGISTER 4-4: RXBNSIDH - Receive Buffer N Standard Identifier High (ADDRESS: 61h, 71h)

DS21219B-page 26

Preliminary

1999 Microchip Technology Inc.

MCP2510

R-x

IDE

U-0

R-x

EID16

bit 0

SID2

SID1

SID0

SRR

EID17

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

—

bit 7

- n = Value at POR reset

bit 7-5: SID2:SID0: Standard Identifier Bits <2:0>

bit 4:

bit 3:

bit 2:

SRR: Substitute Remote Request Bit when IDE=1, RTR bit when IDE=0

IDE: Extended Identifier Flag

Unimplemented: Reads as '0'

bit 1-0: EID17:EID16: Extended Identifier Bits <17:16>

REGISTER 4-5: RXBNSIDL - Receive Buffer N Standard Identifier Low (ADDRESS: 62h, 72h)

R-x

EID15 EID14 EID13

bit 7

EID12

EID11

EID10

EID9

EID8

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

bit 0

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: EID15:EID8: Extended Identifier Bits <15:8>

REGISTER 4-6: RXBNEID8 - Receive Buffer N Extended Identifier Mid (ADDRESS: 63h, 73h)

R-x

EID7

EID6

EID5

EID4

EID3

EID2

EID1

EID0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

bit 7

bit 0

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: EID7:EID0: Extended Identifier Bits <7:0>

REGISTER 4-7: RXBNEID0 - Receive Buffer N Extended Identifier Low (ADDRESS: 64h, 74h)

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 27

MCP2510

U-0

R-x

DLC0

bit 0

RTR

RB1

RB0

DLC3

DLC2

DLC1

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

—

bit 7

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7:

bit 6:

bit 5:

bit 4:

Unimplemented: Reads as '0'

RTR: Remote Transmission Request Bit when RXBnSIDL.IDE = 1

RB1: Reserved Bit 1

RB0: Reserved Bit 0

bit 3-0: DLC3:DLC0: Data Length Code

REGISTER 4-8: RXBNDLC - Receive Buffer N Data Length Code (ADDRESS: 65h, 75h)

R-x

RBNDm7 RBNDm6 RBNDm5 RBNDm4 RBNDm3 RBNDm2 RBNDm1 RBNDm0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

bit 7

bit 0

U = Unimplemented -

reads as ‘0’

- n = Value at POR reset

bit 7-0: RBNDm7:RBNDm0: Receive Buffer N Data Field Byte m

REGISTER 4-9: RXBNDM - Receive Buffer N Data Field Byte m (ADDRESS: 66h-6Dh, 76h-7Dh)

DS21219B-page 28

Preliminary

1999 Microchip Technology Inc.

MCP2510

As shown in the Receive Buffers Block Diagram

(Figure 4-1), acceptance filters RXF0 and RXF1, and

filter mask RXM0 are associated with RXB0. Filters

RXF2, RXF3, RXF4, and RXF5 and mask RXM1 are

associated with RXB1. When a filter matches and a

message is loaded into the receive buffer, the filter

number that enabled the message reception is loaded

into the RXBNCTRL register FILHIT bit(s). For RXB1

the RXB1CTRL register contains the FILHIT<2:0> bits.

They are coded as follows:

4.5

Message Acceptance Filters and

Masks

The Message Acceptance Filters And Masks are used

to determine if a message in the message assembly

buffer should be loaded into either of the receive buffers

(see Figure 4-3). Once a valid message has been

received into the MAB, the identifier fields of the mes-

sage are compared to the filter values. If there is a

match, that message will be loaded into the appropriate

receive buffer. The filter masks (see Register 4-10

through Register 4-17) are used to determine which

bits in the identifier are examined with the filters. A truth

table is shown below in Table 4-10 that indicates how

each bit in the identifier is compared to the masks and

filters to determine if a the message should be loaded

into a receive buffer. The mask essentially determines

which bits to apply the acceptance filters to. If any mask

bit is set to a zero, then that bit will automatically be

accepted regardless of the filter bit.

101 = Acceptance Filter 5 (RXF5)

100 = Acceptance Filter 4 (RXF4)

011 = Acceptance Filter 3 (RXF3)

010 = Acceptance Filter 2 (RXF2)

001 = Acceptance Filter 1 (RXF1)

000 = Acceptance Filter 0 (RXF0)

Note: 000 and 001 can only occur if the BUKT bit

(see Table 4-1) is set in the RXB0CTRL

register allowing RXB0 messages to roll

over into RXB1.

Message

Identifier bit

n001

Mask Bit Filter Bit

Accept or

reject bit n

n

RXB0CTRL contains two copies of the BUKT bit and

the FILHIT<0> bit.

0

X

0

1

0

1

Accept

Reject

Accept

The coding of the BUKT bit enables these three bits to

be used similarly to the RXB1CTRL.FILHIT bits and to

distinguish a hit on filter RXF0 and RXF1 in either

RXB0 or after a roll over into RXB1.

1

0

1

0

1

111 = Acceptance Filter 1 (RXF1)

110 = Acceptance Filter 0 (RXF0)

001 = Acceptance Filter 1 (RXF1)

000 = Acceptance Filter 0

1

Note:

X = don’t care

TABLE 4-10: Filter/Mask Truth Table

If the BUKT bit is clear, there are six codes correspond-

ing to the six filters. If the BUKT bit is set, there are six

codes corresponding to the six filters plus two addi-

tional codes corresponding to RXF0 and RXF1 filters

that roll over into RXB1.

If more than one acceptance filter matches, the FILHIT

bits will encode the binary value of the lowest num-

bered filter that matched. In other words, if filter RXF2

and filter RXF4 match, FILHIT will be loaded with the

value for RXF2. This essentially prioritizes the accep-

tance filters with a lower number filter having higher pri-

ority. Messages are compared to filters in ascending

order of filter number.

The mask and filter registers can only be modified

when the MCP2510 is in configuration mode (see

Section 9.0).

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 29

MCP2510

Acceptance Filter Register

Acceptance Mask Register

RXFn₀

RXMn₀

RXMn₁

RxRqst

RXFn₁

RXFn_n

RXMn_n

Message Assembly Buffer

Identifier

FIGURE 4-3: Message Acceptance Mask and Filter Operation

R/W-x R/W-x R/W-x

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 0

SID10

SID9

SID8

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

bit 7

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: SID10:SID3: Standard Identifier

REGISTER 4-10: RXFNSIDH - Acceptance Filter N Standard Identifier High (Address: 00h, 04h, 08h, 10h, 14h, 18h, 20h, 24h)

R/W-x R/W-x R/W-x

SID2 SID1 SID0

bit 7

U-0

—

R/W-x

U-0

—

R/W-x R/W-x

EID17 EID16

bit 0

EXIDE

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-5: SID2:SID0: Standard Identifier Bits <2:0>

bit 4:

bit 3:

bit 2:

Unimplemented: Reads as '0'

EXIDE: Extended Identifier Enable - bit determines whether filter applies to Standard or Extended Frames

Unimplemented: Reads as '0'

bit 1-0: EID17:EID16: Extended Identifier Bits <17:16>

REGISTER 4-11: RXFNSIDL - Acceptance Filter N Standard Identifier Low (Address: 01h, 05h, 09h, 11h, 15h, 19h, 21h, 25h)

DS21219B-page 30

Preliminary

1999 Microchip Technology Inc.

MCP2510

R/W-x R/W-x R/W-x

EID15 EID14 EID13

bit 7

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: EID15:EID8: Extended Identifier Bits <15:8>

REGISTER 4-12: RXFNEID8 - Acceptance Filter N Extended Identifier High (Address: 02h, 06h, 0Ah, 12h, 16h, 1Ah, 22h, 26h)

R/W-x R/W-x R/W-x

EID7 EID6 EID5

bit 7

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: EID7:EID0: Extended Identifier Bits <7:0>

REGISTER 4-13: RXFNEID0 - Acceptance Filter N Extended Identifier Low (Address: 03h, 07h, 0Bh, 13h, 17h, 1Bh, 23h, 27h)

R/W-x R/W-x R/W-x

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 0

SID10

bit 7

SID9

SID8

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: SID10:SID3: Standard Identifier Bits <10:3>

REGISTER 4-14: RXMNSIDH - Acceptance Filter Mask N Standard Identifier High (Address: 20h, 24h)

R/W-x R/W-x R/W-x

SID2 SID1 SID0

bit 7

U-0

—

U-0

—

U-0

—

R/W-x

EID16

bit 0

EID17

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-5: SID2:SID0: Standard Identifier Bits <2:0>

bit 4-2: Unimplemented: Reads as '0'

bit 1-0: EID17:EID16: Extended Identifier Bits <17:16>

REGISTER 4-15: RXMNSIDL - Acceptance Filter Mask N Standard Identifier Low (Address: 21h, 25h)

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 31

MCP2510

R/W-x R/W-x R/W-x

EID15 EID14 EID13

bit 7

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: EID15:EID8: Extended Identifier Bits <15:8>

REGISTER 4-16: RXMNEID8 - Acceptance Filter Mask N Extended Identifier High (Address: 22h, 26h)

R/W-x R/W-x R/W-x

EID7 EID6 EID5

bit 7

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: EID7:EID0: Extended Identifier Bits <7:0>

REGISTER 4-17: RXMNEID0 - Acceptance Filter Mask N Extended Identifier Low (Address: 23h, 27h)

DS21219B-page 32

Preliminary

1999 Microchip Technology Inc.

MCP2510

The nominal bit rate is the number of bits transmitted

per second assuming an ideal transmitter with an ideal

oscillator, in the absence of resynchronization. The

nominal bit rate is defined to be a maximum of 1Mb/s.

5.0

BIT TIMING

All nodes on a given CAN bus must have the same

nominal bit rate. The CAN protocol uses Non Return to

Zero (NRZ) coding which does not encode a clock

within the data stream. Therefore, the receive clock

must be recovered by the receiving nodes and synchro-

nized to the transmitters clock.

Nominal Bit Time is defined as:

T_BIT= 1 / NOMlNAL BlT RATE

The nominal bit time can be thought of as being divided

into separate non-overlapping time segments. These

segments are shown in Figure 5-1.

As oscillators and transmission time may vary from

node to node, the receiver must have some type of

Phase Lock Loop (PLL) synchronized to data transmis-

sion edges to synchronize and maintain the receiver

clock. Since the data is NRZ coded, it is necessary to

include bit stuffing to ensure that an edge occurs at

least every six bit times, to maintain the Digital Phase

Lock Loop (DPLL) synchronization.

- Synchronization Segment (Sync_Seg)

- Propagation Time Segment (Prop_Seg)

- Phase Buffer Segment 1 (Phase_Seg1)

- Phase Buffer Segment 2 [Phase_Seg2)

Nominal Bit Time = T_Q* (Sync_Seg + Prop_Seg +

Phase_Seg1 + Phase_Seg2)

The bit timing of the MCP2510 is implemented using a

DPLL that is configured to synchronize to the incoming

data, and provide the nominal timing for the transmitted

data. The DPLL breaks each bit time into multiple seg-

ments made up of minimal periods of time called the

time quanta (T_Q).

The time segments and also the nominal bit time are

made up of integer units of time called time quanta or

T^Q(see Figure 5-1). By definition, the nominal bit time

is programmable from a minimum of 8 T_Qto a maxi-

mum of 25 T_Q. Also, by definition the minimum nominal

bit time is 1 µs, corresponding to a maximum 1 Mb/s

rate.

Bus timing functions executed within the bit time frame,

such as synchronization to the local oscillator, network

transmission delay compensation, and sample point

positioning, are defined by the programmable bit timing

logic of the DPLL.

All devices on the CAN bus must use the same bit rate.

However, all devices are not required to have the same

master oscillator clock frequency. For the different clock

frequencies of the individual devices, the bit rate has to

be adjusted by appropriately setting the baud rate pres-

caler and number of time quanta in each segment.

Input Signal

Prop

Sync

Phase

Segment 1

Phase

Segment 2

Segment

Sample Point

T_Q

FIGURE 5-1: Bit Time Partitioning

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 33

MCP2510

The total delay is calculated from the following individ-

ual delays:

5.1

Time Quanta

The Time Quanta is a fixed unit of time derived from the

oscillator period. There is a programmable baud-rate

prescaler, with integral values ranging from 1 to 64, in

addition to a fixed divide by two for clock generation.

2 * physical bus end to end delay; T_BUS(defined by

CAN specification as max. 100 ns)

2 * input comparator delay; T_COMP(depends on appli-

cation circuit)

Time quanta is defined as:

2 * output driver delay; T_DRIVE(depends on application

circuit)

T_Q= 2 * (Baud Rate +1) * T_OSC

where Baud Rate is the binary value represented by

CNF1.BRP<5:0>

1 * input to output of CAN controller; T_CAN(maximum

defined as 1 T_Q+ delay ns)

For some examples:

T_PROPOGATION= 2 * (T_BUS+ T_COMP+ T_DRIVE) + T_CAN

Prop_Seg = T_PROPOGATION/ T_Q

If Fosc = 16 MHz, BRP<5:0> = 00h, and Nominal Bit

Time = 8 T_Q;

5.4

Phase Buffer Segments

then T_Q= 125 nsec and Nominal Bit Rate = 1 Mb/s

If F_OSC= 20 MHz, BRP<5:0> = 01h, and Nominal Bit

Time = 8 T_Q;

The Phase Buffer Segments are used to optimally locate

the sampling point of the received bit within the nominal

bit time. The sampling point occurs between phase seg-

ment 1 and phase segment 2. These segments can be

lengthened or shortened by the resynchronization pro-

cess (see Section 5.7.2). Thus, the variation of the val-

ues of the phase buffer segments represent the DPLL

functionality. The end of phase segment 1 determines

the sampling point within a bit time. phase segment 1 is

programmable from 1 T_Qto 8 T_Qin duration. Phase seg-

ment 2 provides delay before the next transmitted data

transition and is also programmable from 1 T_Qto 8 T_Qin

duration (however due to IPT requirements the actual

minimum length of phase segment 2 is 2 T_Q- see Sec-

tion 5.6 below), or it may be defined to be equal to the

greater of phase segment 1 or the Information Process-

ing Time (IPT). (see Section 5.6).

then T_Q= 200nsec and Nominal Bit Rate = 625 Kb/s

If Fosc = 25 MHz, BRP<5:0> = 3Fh, and Nominal Bit

Time = 25 T_Q;

then T_Q= 5.12 usec and Nominal Bit Rate = 7.8 Kb/s

The frequencies of the oscillators in the different nodes

must be coordinated in order to provide a system-wide

specified nominal bit time. This means that all oscilla-

tors must have a T_OSCthat is a integral divisor of T_Q.

5.2

Synchronization Segment

This part of the bit time is used to synchronize the var-

ious CAN nodes on the bus. The edge of the input sig-

nal is expected to occur during the sync segment. The

duration is 1 T_Q.

5.5

Sample Point

5.3

Propagation Segment

The Sample Point is the point of time at which the bus

level is read and value of the received bit is determined.

The Sampling point occurs at the end of phase seg-

ment 1. If the bit timing is slow and contains many T_Q,

it is possible to specify multiple sampling of the bus line

at the sample point. The value of the received bit is

determined to be the value of the majority decision of

three values. The three samples are taken at the sam-

ple point, and twice before with a time of T_Q/2 between

each sample.

This part of the bit time is used to compensate for phys-

ical delay times within the network. These delay times

consist of the signal propagation time on the bus line

and the internal delay time of the nodes. The delay is

calculated as being the round trip time from transmitter

to receiver (twice the signal’s propagation time on the

bus line), the input comparator delay, and the output

driver delay. The length of the Propagation Segment

can be programmed from 1 T_Qto 8 T_Qby setting the

PRSEG2:PRSEG0 bits of the CNF2 register (Table

6-2).

5.6

Information Processing Time

The Information Processing Time (IPT) is the time seg-

ment, starting at the sample point, that is reserved for

calculation of the subsequent bit level. The CAN speci-

fication defines this time to be less than or equal to 2 T_Q.

The MCP2510 defines this time to be 2 T_Q. Thus, phase

segment 2 must be at least 2 T_Qlong.

DS21219B-page 34

Preliminary

1999 Microchip Technology Inc.

MCP2510

The phase error of an edge is given by the position of

the edge relative to Sync Seg, measured in T_Q. The

phase error is defined in magnitude of T_Qas follows:

5.7

Synchronization

To compensate for phase shifts between the oscillator

frequencies of each of the nodes on the bus, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. Synchronization is

the process by which the DPLL function is imple-

mented. When an edge in the transmitted data is

detected, the logic will compare the location of the edge

to the expected time (Sync Seg). The circuit will then

adjust the values of phase segment 1 and phase seg-

ment 2 as necessary. There are two mechanisms used

for synchronization.

• e = 0 if the edge lies within SYNCESEG.

• e > 0 if the edge lies before the SAMPLE POINT.

• e < 0 if the edge lies after the SAMPLE POINT of

the previous bit.

If the magnitude of the phase error is less than or equal

to the programmed value of the synchronization jump

width, the effect of a resynchronization is the same as

that of a hard synchronization.

If the magnitude of the phase error is larger than the

synchronization jump width, and if the phase error is

positive, then phase segment 1 is lengthened by an

amount equal to the synchronization jump width.

5.7.1

HARD SYNCHRONIZATION

Hard Synchronization is only done when there is a

recessive to dominant edge during a BUS IDLE condi-

tion, indicating the start of a message. After hard syn-

chronization, the bit time counters are restarted with

Sync Seg. Hard synchronization forces the edge which

has occurred to lie within the synchronization segment

of the restarted bit time. Due to the rules of synchroni-

zation, if a hard synchronization occurs there will not be

a resynchronization within that bit time.

If the magnitude of the phase error is larger than the

resynchronization jump width, and if the phase error is

negative, then phase segment 2 is shortened by an

amount equal to the synchronization jump width.

5.7.3

SYNCHRONIZATION RULES

• Only one synchronization within one bit time is

allowed.

5.7.2

RESYNCHRONIZATION

• An edge will be used for synchronization only if

the value detected at the previous sample point

(previously read bus value) differs from the bus

value immediately after the edge.

As a result of Resynchronization, phase segment 1

may be lengthened or phase segment 2 may be short-

ened. The amount of lengthening or shortening of the

phase buffer segments has an upper bound given by

the Synchronization Jump Width (SJW). The value of

the SJW will be added to phase segment 1 (see

Figure 5-2) or subtracted from phase segment 2 (see

Figure 5-3). The SJW represents the loop filtering of

the DPLL. The SJW is programmable between 1 T_Q

and 4 T_Q.

• All other recessive to dominant edges fulfilling

rules 1 and 2 will be used for resynchronization

with the exception that a node transmitting a dom-

inant bit will not perform a resynchronization as a

result of a recessive to dominant edge with a pos-

itive phase error.

Clocking information will only be derived from recessive

to dominant transitions. The property that only a fixed

maximum number of successive bits have the same

value ensures resynchronization to the bit stream dur-

ing a frame.

Input Signal

Prop

Segment

Phase

Segment 1

Phase

Segment 2

Sync

≤ SJW

Actual Bit

Length

Nominal

Bit Length

Sample

Point

T_Q

FIGURE 5-2: Lengthening a Bit Period

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 35

MCP2510

Input Signal

Prop

Segment

Phase

Segment 1

Phase

Segment 2

Sync

≤ SJW

Sample

Point

Actual

Bit Length

Nominal

Bit Length

TQ

FIGURE 5-3: Shortening a Bit Period

5.8 Programming Time Segments

5.9

Oscillator Tolerance

Some requirements for programming of the time seg-

ments:

The bit timing requirements allow ceramic resonators

to be used in applications with transmission rates of up

to 125 kbit/sec, as a rule of thumb. For the full bus

speed range of the CAN protocol, a quartz oscillator is

required. A maximum node-to-node oscillator variation

of 1.7% is allowed.

• Prop Seg + Phase Seg 1 >= Phase Seg 2

• Prop Seg + Phase Seg 1 >= T_DELAY

• Phase Seg 2 > Sync Jump Width

For example, assuming that a 125 kHz CAN baud rate

with F_OSC= 20 MHz is desired:

T_OSC= 50 nsec, choose BRP<5:0> = 04h, then T_Q

=

500nsec. To obtain 125 kHz, the bit time must be 16 T_Q.

Typically, the sampling of the bit should take place at

about 60-70% of the bit time, depending on the system

parameters. Also, typically, the T_DELAYis 1-2 T_Q.

Sync Seg = 1 T_Q; Prop Seg = 2 TQ; So setting Phase

Seg 1 = 7 T_Qwould place the sample at 10 T_Qafter the

transition. This would leave 6 T_Qfor Phase Seg 2.

Since Phase Seg 2 is 6, by the rules, SJW could be the

maximum of 4 T_Q. However, normally a large SJW is

only necessary when the clock generation of the differ-

ent nodes is inaccurate or unstable, such as using

ceramic resonators. So an SJW of 1 is typically

enough.

DS21219B-page 36

Preliminary

1999 Microchip Technology Inc.

MCP2510

ting this bit to a ‘1’ causes the bus to be sampled three

times; twice at T_Q/2 before the sample point, and once

at the normal sample point (which is at the end of

phase segment 1). The value of the bus is determined

to be the value read during at least two of the samples.

If the SAM bit is set to a ‘0’ then the RXCAN pin is sam-

pled only once at the sample point. The BTLMODE bit

controls how the length of phase segment 2 is deter-

mined. If this bit is set to a ‘1’ then the length of phase

segment 2 is determined by the PHSEG2<2:0> bits of

CNF3 (see Section 5.10.3). If the BTLMODE bit is set

to a ‘0’ then the length of phase segment 2 is the

greater of phase segment 1 and the information pro-

cessing time (which is fixed at 2 T_Qfor the MCP2510).

5.10

Bit Timing Configuration Registers

The configuration registers (CNF1, CNF2, CNF3) con-

trol the bit timing for the CAN bus interface. These reg-

isters can only be modified when the MCP2510 is in

configuration mode (see Section 9.0).

5.10.1 CNF1

The BRP<5:0> bits control the baud rate prescaler.

These bits set the length of T_Qrelative to the OSC1

input frequency, with the minimum length of T_Qbeing 2

OSC1 clock cycles in length (when BRP<5:0> are set

to 000000). The SJW<1:0> bits select the synchroniza-

tion jump width in terms of number of T_Q’s.

5.10.2 CNF2

5.10.3 CNF3

The PRSEG<2:0> bits set the length, in T_Q’s, of the

propagation segment. The PHSEG1<2:0> bits set the

length, in T_Q’s, of phase segment 1. The SAM bit con-

trols how many times the RXCAN pin is sampled. Set-

The PHSEG2<2:0> bits set the length, in T_Q’s, of

Phase Segment 2, if the CNF2.BTLMODE bit is set to

a ‘1’. If the BTLMODE bit is set to a ‘0’ then the

PHSEG2<2:0> bits have no effect.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SJW1

bit 7

SJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-6: SJW1:SJW0: Synchronization Jump Width Length

11 = Length = 4 x T_Q

10 = Length = 3 x T_Q

01 = Length = 2 x T_Q

00 = Length = 1 x T_Q

bit 5-0: BRP5:BRP0: Baud Rate Prescaler

111111 = T_Q= 2 x 64 x 1/F_OSC

-

000000 = T_Q= 2 x 1 x 1/F_OSC

REGISTER 5-1: CNF1 - Configuration Register1 (ADDRESS: 2Ah)

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 37

MCP2510

R/W-0

BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0

R = Readable bit

W = Writable bit

C = Bit can be cleared

by MCU but not set

U = Unimplemented -

reads as ‘0’

bit 7

bit 0

- n = Value at POR

reset

bit 7:

BTLMODE: Phase Segment 2 Bit Time Length

1 = Length of Phase Seg 2 determined by PHSEG22:PHSEG20 bits of CNF3

0 = Length of Phase Seg 2 is the greater of Phase Seg 1 and IPT (2T_Q)

bit 6:

SAM: Sample Point Configuration

1 = Bus line is sampled three times at the sample point

0 = Bus line is sampled once at the sample point

bit 5-3: PHSEG12:PHSEG10: Phase Segment 1 Length

111 = Length = 8 x T_Q

-

000 = Length = 1 x T_Q

bit 2-0 PRSEG2:PRSEG0: Propagation Segment Length

111 = Length = 8 x T_Q

-

000 = Length = 1 x T_Q

REGISTER 5-2: CNF2 - Configuration Register2 (ADDRESS: 29h)

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

WAKFIL

PHSEG22 PHSEG21 PHSEG20

bit 0

R = Readable bit

W = Writable bit

C = Bit can be cleared

by MCU but not set

U = Unimplemented -

reads as ‘0’

bit 7

- n = Value at POR reset

bit 7:

bit 6:

Unimplemented: Reads as '0'

WAKFIL:

0 = Wake-up filter disabled

1 = Wake-up filter enabled

bit 7:

Unimplemented: Reads as '0'

bit 2-0 PHSEG22:PHSEG20: Phase Buffer Segment 2

111 = Length = 8 x TQ

-

000 = Length = 1 x TQ

REGISTER 5-3: CNF3 - Configuration Register 3 (ADDRESS: 28h)

DS21219B-page 38

Preliminary

1999 Microchip Technology Inc.

MCP2510

6.6

Error States

6.0

ERROR DETECTION

Detected errors are made public to all other nodes via

error frames. The transmission of the erroneous mes-

sage is aborted and the frame is repeated as soon as

possible. Furthermore, each CAN node is in one of the

three error states “error-active”, “error-passive” or

“bus-off” according to the value of the internal error

counters. The error-active state is the usual state

where the bus node can transmit messages and active

error frames (made of dominant bits) without any

restrictions. In the error-passive state, messages and

passive error frames (made of recessive bits) may be

transmitted. The bus-off state makes it temporarily

impossible for the station to participate in the bus com-

munication. During this state, messages can neither be

received nor transmitted.

The CAN protocol provides sophisticated error detec-

tion mechanisms. The following errors can be detected.

6.1

CRC Error

With the Cyclic Redundancy Check (CRC), the trans-

mitter calculates special check bits for the bit sequence

from the start of a frame until the end of the data field.

This CRC sequence is transmitted in the CRC Field.

The receiving node also calculates the CRC sequence

using the same formula and performs a comparison to

the received sequence. If a mismatch is detected, a

CRC error has occurred and an error frame is gener-

ated. The message is repeated.

6.2

Acknowledge Error

In the acknowledge field of a message, the transmitter

checks if the acknowledge slot (which has sent out as

a recessive bit) contains a dominant bit. If not, no other

node has received the frame correctly. An acknowledge

error has occurred; an error frame is generated; and

the message will have to be repeated.

6.7

Error Modes and Error Counters

The MCP2510 contains two error counters: the

Receive Error Counter (REC) (see Register 6-2), and

the Transmit Error Counter (TEC) (see Register 6-1).

The values of both counters can be read by the MCU.

These counters are incremented or decremented in

accordance with the CAN bus specification.

6.3

Form Error

lf a node detects a dominant bit in one of the four seg-

ments including end of frame, interframe space,

acknowledge delimiter or CRC delimiter; then a form

error has occurred and an error frame is generated.

The message is repeated.

The MCP2510 is error-active if both error counters are

below the error-passive limit of 128. It is error-passive

if at least one of the error counters equals or exceeds

128. It goes to bus-off if the transmit error counter

equals or exceeds the bus-off limit of 256. The device

remains in this state, until the bus-off recovery

sequence is received. The bus-off recovery sequence

consists of 128 occurrences and 11 consecutive reces-

sive bits (see Figure 6-1). Note that the MCP2510, after

going bus-off, will recover back to error-active, without

any intervention by the MCU, if the bus remains idle for

128 X 11 bit times. If this is not desired, the error inter-

rupt service routine should address this. The current

error mode of the MCP2510 can be read by the MCU

via the EFLG register (Register 6-3).

6.4

Bit Error

A Bit Error occurs if a transmitter sends a dominant bit

and detects a recessive bit or if it sends a recessive bit

and detects a dominant bit when monitoring the actual

bus level and comparing it to the just transmitted bit. In

the case where the transmitter sends a recessive bit

and a dominant bit is detected during the arbitration

field and the acknowledge slot, no bit error is generated

because normal arbitration is occurring.

6.5

Stuff Error

Additionally, there is an error state warning flag bit,

EFLG:EWARN, which is set if at least one of the error

counters equals or exceeds the error warning limit of

96. EWARN is reset if both error counters are less than

the error warning limit.

lf, between the start of frame and the CRC delimiter, six

consecutive bits with the same polarity are detected,

the bit stuffing rule has been violated. A stuff error

occurs and an error frame is generated. The message

is repeated.

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 39

MCP2510

RESET

Error-Active

REC > 127 or

TEC > 127

128 occurrences of

11 consecutive

“recessive” bits

REC < 127 or

TEC < 127

Error-Passive

TEC > 255

Bus-Off

FIGURE 6-1: Error Modes State Diagram

R-0

TEC7

bit 7

R-0

TEC0

bit 0

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: TEC7:TEC0: Transmit Error Count

REGISTER 6-1: TEC - Transmitter Error Counter (ADDRESS: 1Ch)

R-0

REC7

bit 7

R-0

REC0

bit 0

REC6

REC5

REC4

REC3

REC2

REC1

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-0: REC7:REC0: Receive Error Count

REGISTER 6-2: REC - Receiver Error Counter (ADDRESS: 1Dh)

DS21219B-page 40

Preliminary

1999 Microchip Technology Inc.

MCP2510

R/W-0

R-0

RX1OVR RX0OVR TXBO

TXEP

RXEP TXWAR RXWAR EWARN

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

bit 7

bit 0

U = Unimplemented -

reads as ‘0’

- n = Value at POR reset

bit 7:

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

RX1OVR: Receive Buffer 1 Overflow Flag

- Set when a valid message is received for RXB1 and CANINTF.RX1IF = 1

- Must be reset by MCU

RX0OVR: Receive Buffer 0 Overflow Flag

- Set when a valid message is received for RXB0 and CANINTF.RX0IF = 1

- Must be reset by MCU

TXBO: Bus-Off Error Flag

- Bit set when TEC reaches 256

- Reset after a successful bus recovery sequence

TXEP: Transmit Error-Passive Flag

- Set when TEC is equal to or greater than 128

- Reset when TEC is less than 128

RXEP: Receive Error-Passive Flag

- Set when REC is equal to or greater than 128

- Reset when REC is less than 128

TXWAR: Transmit Error Warning Flag

- Set when TEC is equal to or greater than 96

- Reset when TEC is less than 96

RXWAR: Receive Error Warning Flag

- Set when REC is equal to or greater than 96

- Reset when REC is less than 96

EWARN: Error Warning Flag

- Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)

- Reset when both REC and TEC are less than 96

REGISTER 6-3: EFLG - Error Flag Register (ADDRESS: 2Dh)

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 41

MCP2510

NOTES:

DS21219B-page 42

Preliminary

1999 Microchip Technology Inc.

MCP2510

7.2

Transmit Interrupt

7.0

INTERRUPTS

The device has eight sources of interrupts. The CANINTE

register contains the individual interrupt enable bits for

each interrupt source. The CANINTF register contains the

corresponding interrupt flag bit for each interrupt source.

When an interrupt occurs the INT pin is driven low by the

MCP2510 and will remain low until the Interrupt is cleared

by the MCU. An Interrupt can not be cleared if the respec-

tive condition still prevails.

When the Transmit Interrupt is enabled (CANINTE.TXNIE

= 1) an Interrupt will be generated on the INT pin when

the associated transmit buffer becomes empty and is

ready to be loaded with a new message. The CAN-

INTF.TXNIF bit will be set to indicate the source of the

interrupt. The interrupt is cleared by the MCU resetting

the TXNIF bit to a ‘0’.

7.3

Receive Interrupt

It is recommended that the bit modify command be

used to reset flag bits in the CANINTF register rather

than normal write operations. This is to prevent unin-

tentionally changing a flag that changes during the

write command, potentially causing an interrupt to be

missed.

When the Receive Interrupt is enabled (CAN-

INTE.RXNIE = 1) an interrupt will be generated on the

INT pin when a message has been successfully

received and loaded into the associated receive buffer.

This interrupt is activated immediately after receiving the

EOF field. The CANINTF.RXNIF bit will be set to indicate

the source of the interrupt. The interrupt is cleared by the

MCU resetting the RXNIF bit to a ‘0’.

It should be noted that the CANINTF flags are read/

write and an Interrupt can be generated by the MCU

setting any of these bits, provided the associated CAN-

INTE bit is also set.

7.4

Message Error Interrupt

7.1

Interrupt Code Bits

When an error occurs during transmission or reception of

a message the message error flag (CANINTF.MERRF)

will be set and, if the CANINTE.MERRE bit is set, an inter-

rupt will be generated on the INT pin. This is intended to

be used to facilitate baud rate determination when used in

conjunction with listen-only mode.

The source of a pending interrupt is indicated in the

CANSTAT.ICOD (interrupt code) bits as indicated in

Register 9-2. In the event that multiple interrupts occur,

the INT will remain low until all interrupts have been

reset by the MCU, and the CANSTAT.ICOD bits will

reflect the code for the highest priority interrupt that is

currently pending. Interrupts are internally prioritized

such that the lower the ICOD value the higher the inter-

rupt priority. Once the highest priority interrupt condi-

tion has been cleared, the code for the next highest

priority interrupt that is pending (if any) will be reflected

by the ICOD bits (see Table 7-1). Note that only those

interrupt sources that have their associated CANINTE

enable bit set will be reflected in the ICOD bits.

7.5

Bus Activity Wakeup Interrupt

When the MCP2510 is in sleep mode and the bus activ-

ity wakeup interrupt is enabled (CANINTE.WAKIE = 1),

an interrupt will be generated on the INT pin, and the

CANINTF.WAKIF bit will be set when activity is

detected on the CAN bus. This interrupt causes the

MCP2510 to exit sleep mode. The interrupt is reset by

the MCU clearing the WAKIF bit.

ICOD<2:0>

000

Boolean Expression

ERR•WAK•TX0•TX1•TX2•RX0•RX1

ERR

001

010

ERR•WAK

011

ERR•WAK•TX0

100

ERR•WAK•TX0•TX1

101

ERR•WAK•TX0•TX1•TX2

ERR•WAK•TX0•TX1•TX2•RX0

ERR•WAK•TX0•TX1•TX2•RX0•RX1

110

111

TABLE 7-1: ICOD<2:0> Decode

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 43

MCP2510

7.6.4

RECEIVER ERROR-PASSIVE

7.6

Error Interrupt

The receive error counter has exceeded the error- pas-

sive limit of 127 and the device has gone to error- pas-

sive state.

When the error interrupt is enabled (CANINTE.ERRIE

= 1) an interrupt is generated on the INT pin if an over-

flow condition occurs or if the error state of transmitter

or receiver has changed. The Error Flag Register

(EFLG) will indicate one of the following conditions.

7.6.5

TRANSMITTER ERROR-PASSIVE

The transmit error counter has exceeded the error-

passive limit of 127 and the device has gone to error-

passive state.

7.6.1

RECEIVER OVERFLOW

An overflow condition occurs when the MAB has assem-

bled a valid received message (the message meets the

criteria of the acceptance filters) and the receive buffer

associated with the filter is not available for loading of a

new message. The associated EFLG.RXNOVR bit will

be set to indicate the overflow condition. This bit must be

cleared by the MCU.

7.6.6

BUS-OFF

The transmit error counter has exceeded 255 and the

device has gone to bus-off state.

7.7

Interrupt Acknowledge

Interrupts are directly associated with one or more sta-

tus flags in the CANINTF register. Interrupts are pend-

ing as long as one of the flags is set. Once an interrupt

flag is set by the device, the flag can not be reset by the

MCU until the interrupt condition is removed.

7.6.2

RECEIVER WARNING

The receive error counter has reached the MCU warn-

ing limit of 96.

7.6.3

TRANSMITTER WARNING

The transmit error counter has reached the MCU warn-

ing limit of 96.

R/W-0

R/W-0 R/W-0 R/W-0 R/W-0

R/W-0

TX0IE

R/W-0 R/W-0

MERRE WAKIE ERRIE TX2IE TX1IE

RX1IE RX0IE

R = Readable bit

W = Writable bit

C = Bit can be cleared by

bit 7

bit 0

MCU but not set

U = Unimplemented - readsas ‘0’

- n = Value at POR reset

bit 7:

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

MERRE: Message Error Interrupt Enable

0 = Disabled

1 = Interrupt on error during message reception or transmission

WAKIE: Wakeup Interrupt Enable

0 = Disabled

1 = Interrupt on CAN bus activity

ERRIE: Error Interrupt Enable (multiple sources in EFLG register)

0 = Disabled

1 = Interrupt on EFLG error condition change

TX2IE: Transmit Buffer 2 Empty Interrupt Enable

0 = Disabled

1 = Interrupt on TXB2 becoming empty

TX1IE: Transmit Buffer 1 Empty Interrupt Enable

0 = Disabled

1 = Interrupt on TXB1 becoming empty

TX0IE: Transmit Buffer 0 Empty Interrupt Enable

0 = Disabled

1 = Interrupt on TXB0 becoming empty

RX1IE: Receive Buffer 1 Full Interrupt Enable

0 = Disabled

1 = Interrupt when message received in RXB1

RX0IE: Receive Buffer 0 Full Interrupt Enable

0 = Disabled

1 = Interrupt when message received in RXB0

REGISTER 7-1: CANINTE - Interrupt Enable Register (ADDRESS: 2Bh)

DS21219B-page 44

Preliminary

1999 Microchip Technology Inc.

MCP2510

R/W-0

TX1IF

R/W-0

TX0IF

R/W-0

RX1IF

R/W-0

RX0IF

bit 0

MERRF WAKIF ERRIF TX2IF

R = Readable bit

W = Writable bit

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

bit 7

- n = Value at POR reset

bit 7:

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

MERRF: Message Error Interrupt Flag

WAKIF: Wakeup Interrupt Flag

ERRIF: Error Interrupt Flag (multiple sources in EFLG register)

TX2IF: Transmit Buffer 2 Empty Interrupt Flag

TX1IF: Transmit Buffer 1 Empty Interrupt Flag

TX0IF: Transmit Buffer 0 Empty Interrupt Flag

RX1IF: Receive Buffer 1 Full Interrupt Flag

RX0IF: Receive Buffer 0 Full Interrupt Flag

For all bits unless otherwise specified:

0 = No interrupt pending

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)

REGISTER 7-2: CANINTF - Interrupt FLAG Register (ADDRESS: 2Ch)

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 45

MCP2510

NOTES:

DS21219B-page 46

Preliminary

1999 Microchip Technology Inc.

MCP2510

8.2

CLKOUT Pin

8.0

OSCILLATOR

The MCP2510 is designed to be operated with a crystal

or ceramic resonator connected to the OSC1 and

OSC2 pins. The MCP2510 oscillator design requires

the use of a parallel cut crystal. Use of a series cut crys-

tal may give a frequency out of the crystal manufactur-

ers specifications. A typical oscillator circuit is shown in

Figure 8-1. The MCP2510 may also be driven by an

external clock source connected to the OSC1 pin as

shown in Figure 8-2 and Figure 8-3.

The clock out pin is provided to the system designer for

use as the main system clock or as a clock input for other

devices in the system. The CLKOUT has an internal

prescaler which can divide F_OSCby 1, 2, 4 and 8. The

CLKOUT function is enabled and the prescaler is

selected via the CANCNTRL register (see Register 9-1).

The CLKOUT pin will be active upon system reset and

default to the slowest speed (divide by 8) so that it can be

used as the MCU clock. When sleep mode is requested,

the MCP2510 will drive sixteen additional clock cycles on

the CLKOUT pin before entering sleep mode. The idle

state of the CLKOUT pin in sleep mode is low. When the

CLKOUT function is disabled (CANCNTRL.CLKEN = ‘0’)

the CLKOUT pin is in a high impedance state.

8.1

Oscillator Startup Timer

The MCP2510 utilizes an oscillator startup timer

(OST), which holds the MCP2510 in reset, to insure

that the oscillator has stabilized before the internal

state machine begins to operate. The OST maintains

reset for the first 128 OSC1 clock cycles after power up

or wake up from sleep mode occurs.

The CLKOUT function is designed to guarantee that

t_hCLKOUTand t_lCLKOUTtimings are preserved when the

CLKOUT pin function is enabled, disabled, or the pres-

caler value is changed.

OSC1

C1

To internal logic

SLEEP

XTAL

(2)

R_F

(1)

R_S

OSC2

C2

Note 1: A series resistor, R , may be required for AT strip cut crystals.

S

Note 2: The feedback resistor, R , is typically in the range of 2 to 10 MΩ.

F

FIGURE 8-1: Crystal/Ceramic Resonator Operation

clock from

OSC1

external system

(1)

OSC2

Open

Note 1: A resistor to ground may be used to reduce system noise. This may increase system current.

Note 2: Duty cycle restrictions must be observed (see Table 12-2).

FIGURE 8-2: External Clock Source

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 47

MCP2510

To Other

Devices

330 kΩ

74AS04

330 kΩ

74AS04

MCP2510

OSC1

0.1 mF

XTAL

Note 1: Duty cycle restrictions must be observed (see Table 12-2).

FIGURE 8-3: External Series Resonant Crystal Oscillator Circuit

DS21219B-page 48

Preliminary

1999 Microchip Technology Inc.

MCP2510

When in sleep mode the MCP2510 stops its internal

oscillator. The MCP2510 will wake-up when bus activity

occurs or when the MCU sets, via the SPI interface, the

CANINTF.WAKIF bit to ‘generate’ a wake up attempt

(the CANINTF.WAKIF bit must also be set in order for

the wakeup interrupt to occur). The TXCAN pin will

remain in the recessive state while the MCP2510 is in

sleep mode.

9.0

MODES OF OPERATION

The MCP2510 has five modes of operation. These

modes are:

1. Configuration Mode

2. Normal Mode

3. Sleep Mode

4. Listen-Only Mode

5. Loopback Mode

9.2.1

WAKE-UP FUNCTIONS

The operational mode is selected via the CANCTRL.

REQOP bits (see Register 9-1). When changing modes,

the mode will not actually change until all pending mes-

sage transmissions and receptions are complete.

Because of this, the user must verify that the device has

actually changed into the requested mode before further

operations are executed. Verification of the current oper-

ating mode is done by reading the CANSTAT. OPMODE

bits (see Register 9-2).

The device will monitor the RXCAN pin for activity while

it is in sleep mode. If the CANINTE.WAKIE bit is set, the

device will wake up and generate an interrupt. Since the

internal oscillator is shut down when sleep mode is

entered, it will take some amount of time for the oscilla-

tor to start up and the device to enable itself to receive

messages. The device will ignore the message that

caused the wake-up from sleep mode as well as any

messages that occur while the device is ‘waking up.’

The device will wake up in listen-only mode. The MCU

must set normal mode before the MCP2510 will be able

to communicate on the bus.

9.1

Configuration Mode

The MCP2510 must be initialized before activation. This

is only possible if the device is in the configuration mode.

Configuration mode is automatically selected after pow-

erup or a reset, or can be entered from any other mode

by setting the CANTRL.REQOP<2> bit to ‘1’. When con-

figuration mode is entered all error counters are cleared.

Configuration mode is the only mode where the follow-

ing registers are modifiable:

The device can be programmed to apply a low-pass fil-

ter function to the RXCAN input line while in internal

sleep mode. This feature can be used to prevent the

device from waking up due to short glitches on the CAN

bus lines. The CNF3.WAKFIL bit enables or disables

the filter.

9.3

Listen Only Mode

• CNF1, CNF2, CNF3

• TXRTSCTRL

Listen-only mode provides a means for the MCP2510

to receive all messages including messages with

errors. This mode can be used for bus monitor applica-

tions or for detecting the baud rate in ‘hot plugging’ sit-

uations. For auto-baud detection it is necessary that

there are at least two other nodes, which are communi-

cating with each other. The baud rate can be detected

empirically by testing different values until valid mes-

sages are received. The listen-only mode is a silent

mode, meaning no messages will be transmitted while

in this state, including error flags or acknowledge sig-

nals. The filters and masks can be used to allow only

particular messages to be loaded into the receive reg-

isters, or the filter masks can be set to all zeros to allow

a message with any identifier to pass. The error

counters are deactivated in this state. The listen-only

mode is activated by setting the mode request bits in

the CANCTRL register.

• Acceptance Filter Registers

• Acceptance Mask Registers

Only when the CANSTAT.OPMODE bits read as ‘100’

can the initialization be performed, allowing the config-

uration registers, acceptance mask registers, and the

acceptance filter registers to be written. After the con-

figuration is complete, the device can be activated by

programming the CANCTRL.REQOP bits for normal

operation mode (or any other mode).

9.2

Sleep Mode

The MCP2510 has an internal sleep mode that is used

to minimize the current consumption of the device. The

SPI interface remains active even when the MCP2510

is in sleep mode, allowing access to all registers.

To enter sleep mode, the mode request bits are set in

the CANCTRL register. The CANSTAT.OPMODE bits

indicate whether the device successfully entered

sleep mode. These bits should be read after sending

the sleep command to the MCP2510. The MCP2510 is

active and has not yet entered sleep mode until these

bits indicate that sleep mode has been entered. When

in internal sleep mode, the wakeup interrupt is still

active (if enabled). This is done so the MCU can also

be placed into a sleep mode and use the MCP2510 to

wake it up upon detecting activity on the bus.

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 49

MCP2510

9.4

Loopback Mode

9.5

Normal Mode

This mode will allow internal transmission of messages

from the transmit buffers to the receive buffers without

actually transmitting messages on the CAN bus. This

mode can be used in system development and testing.

In this mode the ACK bit is ignored and the device will

allow incoming messages from itself just as if they were

coming from another node. The loopback mode is a

silent mode, meaning no messages will be transmitted

while in this state, including error flags or acknowledge

signals. The TXCAN pin will be in a reccessive state

while the device is in this mode. The filters and masks

can be used to allow only particular messages to be

loaded into the receive registers. The masks can be set

to all zeros to provide a mode that accepts all mes-

sages. The loopback mode is activated by setting the

mode request bits in the CANCTRL register.

This is the standard operating mode of the MCP2510.

In this mode the device actively monitors all bus mes-

sages and generates acknowledge bits, error frames,

etc. This is also the only mode in which the MCP2510

will transmit messages over the CAN bus.

R/W-1

R/W-0

U-0

R/W-1

REQOP2 REQOP1 REQOP0 ABAT

—

CLKEN CLKPRE1CLKPRE0 R = Readable bit

W = Writable bit

bit 7

bit 0

C = Bit can be cleared by

MCU but not set

U = Unimplemented - reads

as ‘0’

- n = Value at POR reset

bit 7-5: REQOP<2:0>: Request Operation Mode

000 = Set Normal Operation Mode

001 = Set Sleep Mode

010 = Set Loopback Mode

011 = Set Listen Only Mode

100 = Set Configuration Mode

All other values for REQOP bits are invalid and should not be used

bit 4:

ABAT: Abort All Pending Transmissions

1 = Request abort of all pending transmit buffers

0 = Terminate request to abort all transmissions

bit 3:

bit 2:

Unimplemented: Reads as ‘0’

CLKEN: CLKOUT Pin Enable

0 = CLKOUT pin disabled (Pin is in high impedance state)

1 =CLKOUT pin enabled

bit 1-0: CLKPRE<1:0>: CLKOUT Pin Prescaler

00 = F_CLKOUT= System Clock/1

01 = F_CLKOUT= System Clock/2

10 = F_CLKOUT= System Clock/4

11 = F_CLKOUT= System Clock/8

REGISTER 9-1: CANCTRL - CAN Control Register (ADDRESS: xFh)

DS21219B-page 50

Preliminary

1999 Microchip Technology Inc.

MCP2510

R-1

R-0

U-0

R-0

U-0

OPMOD2 OPMOD1 OPMOD0

—

ICOD2 ICOD1 ICOD0

—

R = Readable bit

W = Writable bit

C = Bit can be cleared

by MCU but not set

U = Unimplemented -

reads as ‘0’

bit 7

bit 0

- n = Value at POR reset

bit 7-5: OPMOD<2:0>: Operation Mode

000 = Device is in Normal Operation Mode

001 = Device is in Sleep Mode

010 = Device is in Loopback Mode

011 = Device is in Listen Only Mode

100 = Device is in Configuration Mode

bit 4:

Unimplemented: Reads as ‘0’

bit 3-1: ICOD<2:0>: Interrupt Flag Code

000 = No Interrupt

001 = Error Interrupt

010 = Wake Up Interrupt

011 = TXB0 Interrupt

100 = TXB1 Interrupt

101 = TXB2 Interrupt

110 = RXB0 Interrupt

111 = RXB1 Interrupt

bit 0:

Unimplemented: Reads as ‘0’

REGISTER 9-2: CANSTAT - CAN Status Register (ADDRESS: xEh)

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 51

MCP2510

NOTES:

DS21219B-page 52

Preliminary

1999 Microchip Technology Inc.

MCP2510

writing of data. Some specific control and status regis-

ters allow individual bit modification using the SPI Bit

Modify command. The registers that allow this com-

mand are shown as shaded locations in Table 10-1. A

summary of the MCP2510 control registers is shown in

Table 10-2.

10.0 REGISTER MAP

The register map for the MCP2510 is shown in

Table 10-1. Address locations for each register are

determined by using the column (higher order 4 bits)

and row (lower order 4 bits) values. The registers have

been arranged to optimize the sequential reading and

Higher Order Address Bits

Lower

Address Bits

x000 xxxx x001 xxxx

x010 xxxx x0011 xxxx x100 xxxx

x101 xxxx

x110 xxxx

x111 xxxx

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

RXF0SIDH RXF3SIDH RXM0SIDH TXB0CTRL TXB1CTRL TXB2CTRL RXB0CTRL RXB1CTRL

RXF0SIDL RXF3SIDL RXM0SIDL

RXF0EID8 RXF3EID8 RXM0EID8

RXF0EID0 RXF3EID0 RXM0EID0

RXF1SIDH RXF4SIDH RXM1SIDH

RXF1SIDL RXF4SIDL RXM1SIDL

RXF1EID8 RXF4EID8 RXM1EID8

RXF1EID0 RXF4EID0 RXM1EID0

TXB0SIDH TXB1SIDH TXB2SIDH RXB0SIDH RXB1SIDH

TXB0SIDL

TXB0EID8

TXB0EID0

TXB0DLC

TXB0D0

TXB0D1

TXB0D2

TXB0D3

TXB0D4

TXB0D5

TXB0D6

TXB0D7

CANSTAT

CANCTRL

TXB1SIDL

TXB1EID8

TXB1EID0

TXB1DLC

TXB1D0

TXB1D1

TXB1D2

TXB1D3

TXB1D4

TXB1D5

TXB1D6

TXB1D7

CANSTAT

CANCTRL

TXB2SIDL

TXB2EID8

TXB2EID0

TXB2DLC

TXB2D0

TXB2D1

TXB2D2

TXB2D3

TXB2D4

TXB2D5

TXB2D6

TXB2D7

CANSTAT

CANCTRL

RXB0SIDL RXB1SIDL

RXB0EID8 RXB1EID8

RXB0EID0 RXB1EID0

RXB0DLC

RXB0D0

RXB0D1

RXB0D2

RXB0D3

RXB0D4

RXB0D5

RXB0D6

RXB0D7

CANSTAT

CANCTRL

RXB1DLC

RXB1D0

RXB1D1

RXB1D2

RXB1D3

RXB1D4

RXB1D5

RXB1D6

RXB1D7

CANSTAT

CANCTRL

RXF2SIDH RXF5SIDH

RXF2SIDL RXF5SIDL

RXF2EID8 RXF5EID8

RXF2EID0 RXF5EID0

CNF3

CNF2

CNF1

CANINTE

CANINTF

EFLG

BFPCTRL

TXRTSCTRL

CANSTAT

TEC

REC

CANSTAT

CANCTRL

CANCTRL CANCTRL

Note:

Shaded register locations indicate that these allow the user to manipulate individual bits using the ‘Bit Modify’

Command

TABLE 10-1: CAN Controller Register Map

Register

Name

Address

(Hex)

POR/RST

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BFPCTRL

TXRTSCTRL

CANSTAT

CANCTRL

TEC

0C

0D

xE

xF

1C

1D

28

29

2A

2B

2C

2D

30

40

50

60

70

B1BFS

B2RTS

B0BFS

B1RTS

B1BFE

B0RTS

ICOD2

B0BFE

B1BFM

B0BFM --00 0000

–

B2RTSM B1RTSM B0RTSM --xx x000

ICOD1 ICOD0 100- 000-

OPMOD2 OPMOD1 OPMOD0

–

ABAT

–

REQOP2 REQOP1 REQOP0

CLKEN CLKPRE1 CLKPRE0 1110 -111

0000 0000

–

Transmit Error Counter

Receive Error Counter

REC

0000 0000

CNF3

WAKFIL

PHSEG22 PHSEG21 PHSEG20 -0-- -000

–

CNF2

BTLMODE

SAM

SJW0

WAKIE

WAKIF

PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0 0000 0000

CNF1

SJW1

BRP5

ERRIE

ERRIF

TXB0

BRP4

TX2IE

TX2IF

BRP3

TX1IE

BRP2

TX0IE

TX0IF

BRP1

RX1IE

RX1IF

RXWAR

TXP1

BRP0

RX0IE

RX0IF

0000 0000

CANINTE

CANINTF

EFLG

MERRE

MERRF

TX1IF

RX1OVR RX0OVR

TXEP

RXEP

TXWAR

EWARN 0000 0000

TXB0CTRL

TXB1CTRL

TXB2CTRL

RXB0CTRL

RXB1CTRL

ABTF

MLOA

RXM0

TXERR

TXREQ

RXRTR

TXP0

-000 0-00

–

ABTF

TXP1

–

ABTF

TXP1

–

BUKT

RXM1

BUKT

FILHIT1

FILHIT0 -00- 0000

–

RSM1

FILHIT2

–

TABLE 10-2: Control Register Summary

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 53

MCP2510

NOTES:

DS21219B-page 54

Preliminary

1999 Microchip Technology Inc.

MCP2510

11.5

Read Status Instruction

11.0 SPI INTERFACE

The Read Status Instruction allows single instruction

access to some of the often used status bits for mes-

sage reception and transmission.

11.1

Overview

The MCP2510 is designed to interface directly with the

Serial Peripheral Interface (SPI) port available on many

microcontrollers and supports Mode 0,0 and Mode 1,1.

Commands and data are sent to the device via the SI

pin, with data being clocked in on the rising edge of

SCK. Data is driven out by the MCP2510, on the SO

line, on the falling edge of SCK. The CS pin must be

held low while any operation is performed. Table 11-1

shows the instruction bytes for all operations. Refer to

Figure 11-8 and Figure 11-9 for detailed input and out-

put timing diagrams for both Mode 0,0 and Mode 1,1

operation.

The part is selected by lowering the CS pin and the read

status command byte, shown in Figure 11-6, is sent to

the MCP2510. After the command byte is sent, the

MCP2510 will return eight bits of data that contain the

status. If additional clocks are sent after the first eight

bits are transmitted, the MCP2510 will continue to output

the status bits as long as the CS pin is held low and

clocks are provided on SCK. Each status bit returned in

this command may also be read by using the standard

read command with the appropriate register address.

11.6

Bit Modify Instruction

11.2

Read Instruction

The Bit Modify Instruction provides a means for setting

or clearing individual bits in specific status and control

registers. This command is not available for all regis-

ters. See Section 10.0 (register map) to determine

which registers allow the use of this command.

The Read Instruction is started by lowering the CS pin.

The read instruction is then set to the MCP2510 fol-

lowed by the 8-bit address (A7 through A0). After the

read instruction and address are sent, the data stored

in the register at the selected address will be shifted out

on the SO pin. The internal address pointer is automat-

ically incremented to the next address after each byte

of data is shifted out. Therefore it is possible to read the

next consecutive register address by continuing to pro-

vide clock pulses. Any number of consecutive register

locations can be read sequentially using this method.

The read operation is terminated by raising the CS pin

(Figure 11-2).

The part is selected by lowering the CS pin and the Bit

Modify command byte is then sent to the MCP2510.

After the command byte is sent, the address for the reg-

ister is sent followed by the mask byte and then the

data byte. The mask byte determines which bits in the

register will be allowed to change. A ‘1’ in the mask byte

will allow a bit in the register to change and a ‘0’ will not.

The data byte determines what value the modified bits

in the register will be changed to. A ‘1’ in the data byte

will set the bit and a ‘0’ will clear the bit, provided that

the mask for that bit is set to a ‘1’. (see Figure 11-1)

11.3

Write Instruction

The Write Instruction is started by lowering the CS pin.

The write instruction is then set to the MCP2510 fol-

lowed by the address and at least one byte of data. It is

possible to write to sequential registers by continuing to

clock in data bytes, as long as CS is held low. Data will

actually be written to the register on the rising edge of

the SCK line for the D0 bit. If the CS line is brought high

before eight bits are loaded, the write will be aborted for

that data byte, previous bytes in the command will have

been written. Refer to the timing diagram in Figure 11-3

for more detailed illustration of the byte write sequence.

11.7

Reset Instruction

The Reset Instruction can be used to re-initialize the

internal registers of the MCP2510 and set configuration

mode. This command provides the same functionality,

via the SPI interface, as the RESET pin. The Reset

instruction is a single byte instruction which requires

selecting the device by pulling CS low, sending the

instruction byte, and then raising CS. It is highly recom-

mended that the reset command be sent (or the

RESET pin be lowered) as part of the power-on initial-

ization sequence.

11.4

Request To Send (RTS) Instruction

The RTS command can be used to initiate message

transmission for one or more of the transmit buffers.

0 0 1 1 0 1 0 1

X X 1 0 X 0 X 1

0 1 0 1 0 0 0 1

0 1 1 0 0 0 0 1

Mask byte

Data byte

The part is selected by lowering the CS pin and the RTS

command byte is then set to the MCP2510. As shown in

Figure 11-4, the last 3 bits of this command indicate

which transmit buffer(s) are enabled to send. This com-

mand will set the TxBnCTRL.TXREQ bit for the respec-

tive buffer(s). Any or all of the last three bits can be set in

a single command. If the RTS command is sent with

nnn=000, the command will be ignored.

Contents

Resulting

Register

Contents

FIGURE 11-1: Bit Modify

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 55

MCP2510

Instruction Name Instruction Format

Description

RESET

READ

1100 0000

0000 0011

0000 0010

1000 0nnn

Resets internal registers to default state, set configuration mode

Read data from register beginning at selected address

Write data to register beginning at selected address

Sets TXBnCTRL.TXREQ bit for one or more transmit buffers

WRITE

RTS

(Request To Send)

1000 0nnn

Request to send for TXB2

Request to send for TXBO

Request to send for TXB1

Read Status

Bit Modify

1010 0000

0000 0101

Polling command that outputs status bits for transmit/receive functions

Bit modify selected registers

TABLE 11-1: SPI Instruction Set

CS

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

instruction

address byte

0

1

A7

6

5

4

3

2

1

A0

don’t care

SI

data out

high impedance

SO

7

6

5

4

3

2

1

0

FIGURE 11-2: Read Instruction

CS

0

1

0

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

address byte

data byte

instruction

7

6

5

4

3

2

1

0

1

0

A7

6

5

4

3

2

1

A0

SI

high impedance

SO

FIGURE 11-3: Byte Write Instruction

DS21219B-page 56

Preliminary

1999 Microchip Technology Inc.

MCP2510

CS

0

1

0

2

3

4

5

6

7

SCK

instruction

T1

0

T2

T0

SI

high impedance

SO

FIGURE 11-4: Request To Send Instruction

CS

23 24 25 26 27 28 29 30 31

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

0

SCK

data byte

mask byte

address byte

instruction

7

6 5 4 3 2 1 0

7

0 0 0 0 1 0 1 A7 6 5 4 3 2

1

A0

SI

high impedance

SO

Note: Not all registers can be accessed with this command. See the register map in Section 10.0 for a list of

the registers that apply.

FIGURE 11-5: BIT Modify instruction

CS

0

1

0

2

3

4

5

0

6

0

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

instruction

don’t care

repeat

1

0

SI

data out

high impedance

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

CANINTF.RX0IF

CANINTF.RX1IF

TXB0CNTRL.TXREQ

CANINTF.TX0IF

TXB1CNTRL.TXREQ

CANINTF.TX1IF

TXB2CNTRL.TXREQ

CANINTF.TX2IF

FIGURE 11-6: Read Status Instruction

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 57

MCP2510

CS

0

1

2

3

4

5

0

6

0

7

SCK

instruction

0

SI

high impedance

SO

FIGURE 11-7: RESET Instruction

TCSD

CS

TCLE

TCLD

TR

TCSS

TF

TCSH

Mode 1,1

SCK

SI

Mode 0,0

TSU

THD

MSB in

LSB in

high impedance

SO

FIGURE 11-8: SPI Input Timing

CS

TCSH

THI

TLO

SCK

Mode 1,1

Mode 0,0

TV

TDIS

THO

SO

MSB out

LSB out

don’t care

SI

FIGURE 11-9: SPI Output Timing

DS21219B-page 58

Preliminary

1999 Microchip Technology Inc.

MCP2510

12.0 ELECTRICAL CHARACTERISTICS

*Notice: Stresses above those listed under “Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied. Expo-

sure to maximum rating conditions for extended periods may

affect device reliability.

12.1

Maximum Ratings

V

...................................................................................7.0V

DD

All inputs and outputs w.r.t. V ............... -0.6V to V +1.0V

SS

DD

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................-65°C to +125°C

Soldering temperature of leads (10 seconds) .............+300°C

ESD protection on all pins..................................................≥ 4 kV

All parameters apply over the

specified operating ranges

unless otherwise noted.

Industrial (I):

Automotive (E):

T

= -40°C to +85°C

= -40°C to +125°C

V

= 2.7V to 5.5V

= 4.5V to 5.5V

AMB

DD

T

AMB

Parameter

Symbol

Min

2.7

2.4

Max

Units

Test Conditions

Supply Voltage

V

5.5

V

DD

Register Retention Voltage

High Level Input Voltage

RXCAN,TXnRTS Pins

SCK (Schmitt Trigger), CS,SI

OSC1

V

–

RET

Note

V

2

V

+1

V

IH

DD

.7 V

V

+1

DD

.85 V

V

DD

RESET (Schmitt Trigger)

Low Level Input Voltage

RXCAN,TXnRTS Pins

SCK (Schmitt Trigger), CS,SI

OSC1

Note

V

-0.3

.15 V

.8

V

IL

DD

V

.3 V

.15 V

SS

DD

RESET (Schmitt Trigger)

Low Level Output Voltage

TXCAN

V

DD

V

0.4

0.6

V

I

= -6.0 mA

–

OL

RXnBF Pins

= -8.5 mA, V = 4.5V

DD

SO, CLKOUT

= -2.1 mA, V = 4.5V

DD

INT

= -1.6 mA, V = 4.5V

DD

High Level Output Voltage

TXCAN, RXnBF Pins

SO, CLKOUT

V

-0.7

I

= 3.0mA, V = 4.5V, I temp

–

OH

DD

OH

DD

-0.5

= 400µA

INT

-0.7

= 1.0mA, V = 4.5V

DD

Hysteresis

V

.05 V

HYS

DD

Input Leakage Current

All I/O except OSC1

OSC1 Pin

I

-1

-5

+1

+5

10

7

µA

pF

CS = V , V = V to V

DD IN SS DD

LI

Output Leakage Current

I

-10

CS = V , V

= V to V

LO

DD OUT SS DD

Internal Capacitance

(All Inputs And Outputs)

C

T

= 25°C, f = 1.0 MHz,

–

INT

AMB

C

V

= 5.0V (Note)

DD

Operating Current

I

10

20

mA

V

= 5.5V; F

=5.0 MHz; SO = Open

CLK

–

DD

Standby Current (Sleep Mode)

I

--

µA

CS, TXnRTS = V , Inputs tied to V or V

DD DD SS

DDS

Note:

This parameter is not 100% tested.

TABLE 12-1: DC Characteristics

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 59

MCP2510

All parameters apply over the

specified operating ranges unless

otherwise noted.

Industrial (I):

Automotive (E):

T

= -40°C to +85°C

= -40°C to +125°C

V

= 2.7V to 5.5V

= 4.5V to 5.5V

AMB

DD

T

AMB

Parameter

Symbol

Min

Max

Units

Conditions

Clock In Frequency

F

1

25

MHz

OSC

Clock In Period

T

40

1000

ns

OSC

Clock In High, Low Time

T

, T

10

5

ns

Note

–

OSL OSH

Clock In Rise, Fall Time

T

, T

OSR OSF

Duty Cycle (External Clock Input)

T

.30

.70

T

/ (T

+ T

)

–

DUTY

OSH

OSL

Note:

This parameter is periodically sampled and not 100% tested.

TABLE 12-2: Oscillator Timing Characteristics

All parameters apply over the

specified operating ranges

unless otherwise noted.

Industrial (I):

Automotive (E):

T

= -40°C to +85°C

= -40°C to +125°C

V

= 2.7V to 5.5V

= 4.5V to 5.5V

AMB

DD

T

AMB

Parameter

Symbol

Min

100

Max

–

Units

Conditions

Wakeup Noise Filter

T

ns

WF

CLOCKOUT Propagation Delay

T

100

ns

–

DCLK

TABLE 12-3: CAN Interface AC Characteristics

All parameters apply over the

specified operating ranges

unless otherwise noted.

Industrial (I):

Automotive (E):

T

= -40°C to +85°C

= -40°C to +125°C

V

= 2.7V to 5.5V

= 4.5V to 5.5V

AMB

CC

T

AMB

Parameter

Symbol

Min

Max

Units

Conditions

CLKOUT Pin High Time

t

15

ns

T

= 40 ns, CLKOUT prescaler set

–

hCLKOUT

OSC

to divide by one

CLKOUT Pin Low Time

t

15

ns

T

OSC

to divide by one

= 40 ns, CLKOUT prescaler set

–

lCLKOUT

CLKOUT Pin Rise Time

t

5

ns

V

Measured from 0.3 V to 0.7 V

–

rCLKOUT

DD

CLKOUT Pin Fall Time

t

Measured from 0.7 V to 0.3 V

fCLKOUT

DD

CLOCKOUT Propagation Delay

CLKOUT Pin Output Low Voltage

CLKOUT Pin Output High Voltage

t

100

0.3 V

dCLKOUT

V

I

= 0

OLCLKOUT

DD

OL

V

0.7 V

V

–

OHCLKOUT

DD

TABLE 12-4: CLKOUT Pin AC/DC Characteristics

DS21219B-page 60

Preliminary

1999 Microchip Technology Inc.

MCP2510

All parameters apply over the

specified operating ranges

unless otherwise noted.

Industrial (I):

Automotive (E):

T

= -40°C to +85°C

= -40°C to +125°C

V

= 2.7V to 5.5V

= 4.5V to 5.5V

AMB

DD

T

AMB

Parameter

Symbol

Min

Max

Units

Test Conditions

F

Clock Frequency

–

5

3

MHz

V

= 4.5V to 5.5V

= 2.7V to 4.5V

CLK

DD

T

CS Setup Time

CS Hold Time

100

–

ns

CSS

T

100

150

–

ns

V

= 4.5V to 5.5V

= 2.7V to 4.5V

CSH

DD

T

CS Disable Time

Data Setup Time

Data Hold Time

100

250

–

ns

V

= 4.5V to 5.5V

= 2.7V to 4.5V

CSD

DD

T

20

30

–

ns

V

= 4.5V to 5.5V

= 2.7V to 4.5V

SU

DD

20

50

–

ns

V

= 4.5V to 5.5V

= 2.7V to 4.5V

HD

DD

CLK Rise Time

CLK Fall Time

Clock High Time

T

–

2

ms

Note

R

T

F

T

80

150

–

ns

V

= 4.5V to 5.5V

= 2.7V to 4.5V

HI

DD

Clock Low Time

T

80

150

–

ns

V

= 4.5V to 5.5V

= 2.7V to 4.5V

LO

DD

Clock Delay Time

T

50

–

ns

CLD

Clock Enable Time

CLE

Output Valid from Clock Low

T

–

100

150

ns

V

= 4.5V to 5.5V

= 2.7V to 4.5V

V

DD

Output Hold Time

T

0

–

ns

Note

HO

Output Disable Time

T

200

DIS

Note:

This parameter is periodically sampled and not 100% tested.

TABLE 12-5: SPI Interface AC Characteristics

1999 Microchip Technology Inc.

Preliminary

DS21219B-page 61

MCP2510

NOTES:

DS21219B-page 62

Preliminary

1999 Microchip Technology Inc.

MCP2510

14.2

Package Details

13.0 PACKAGING INFORMATION

The following sections give the technical details of the

packages.

14.1

Package Marking Information

Not available at the time of printing. Will be made

available after definition of QS9000 compliant

standard.

1999 Microchip Technology Inc.

Advance Information

DS21291B-page 63

MCP2510

Package Type: 18-Lead Plastic Dual In-line (P) – 300 mil

E1

D

2

α

n

1

E

A2

L

A

c

A1

B1

β

p

B

eB

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

18

MAX

n

p

Number of Pins

Pitch

18

.100

.155

.130

2.54

Top to Seating Plane

A

.140

.170

3.56

2.92

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.890

.125

.008

.045

.014

.310

5

.145

3.68

0.38

7.62

6.10

22.61

3.18

0.20

1.14

0.36

7.87

5

.313

.250

.898

.130

.012

.058

.018

.370

10

.325

.260

.905

.135

.015

.070

.022

.430

15

7.94

6.35

22.80

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

22.99

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

*Controlling Parameter

Notes:

eB

α

β

5

10

15

5

10

15

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-007

DS21291B-page 64

Advance Information

1999 Microchip Technology Inc.

MCP2510

Package Type: 18-Lead Plastic Small Outline (SO) – Wide, 300 mil

E

p

E1

D

2

B

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

NOM

MILLIMETERS

NOM

Dimension Limits

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

18

.050

.099

.091

.008

.407

.295

.454

.020

.033

4

1.27

2.50

2.31

0.20

10.34

7.49

11.53

0.50

0.84

4

Overall Height

A

.093

.104

2.36

2.64

Molded Package Thickness

Standoff

A2

A1

E

.088

.004

.394

.291

.446

.010

.016

0

.094

.012

.420

.299

.462

.029

.050

8

2.24

0.10

10.01

7.39

11.33

0.25

0.41

0

2.39

0.30

10.67

7.59

11.73

0.74

1.27

8

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.009

.014

0

.011

.017

12

.012

.020

15

0.23

0.36

0

0.27

0.42

12

0.30

0.51

15

B

α

Mold Draft Angle Top

Mold Draft Angle Bottom

*Controlling Parameter

Notes:

β

0

12

15

0

12

15

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-051

1999 Microchip Technology Inc.

Advance Information

DS21291B-page 65

MCP2510

Package Type: 20-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm

E

p

E1

D

B

2

1

n

α

A

c

φ

β

A2

L

A1

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

20

MAX

n

p

Number of Pins

Pitch

20

.026

.041

.035

.004

.251

.173

.256

.024

4

0.65

Overall Height

A

.039

.033

.002

.246

.169

.252

.020

0

.043

1.00

0.85

1.05

0.90

0.10

6.38

4.40

6.50

0.60

4

1.10

0.95

0.15

6.50

4.50

6.60

0.70

8

Molded Package Thickness

Standoff

A2

A1

E

.037

.006

.256

.177

.260

.028

8

0.05

6.25

4.30

6.40

0.50

0

Overall Width

Molded Package Width

Molded Package Length

Foot Length

E1

D

L

φ

Foot Angle

c

Lead Thickness

.004

.007

0

.006

.010

5

.008

.012

10

0.09

0.19

0

0.15

0.25

5

0.20

0.30

10

Lead Width

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

10

0

5

10

*Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-088

DS21291B-page 63

Advance Information

1999 Microchip Technolo

MCP2510

Systems Information and Upgrade Hot Line

ON-LINE SUPPORT

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip’s development systems software products.

Plus, this line provides information on how customers

can receive any currently available upgrade kits.The

Hot Line Numbers are:

Microchip provides on-line support on the Microchip

World Wide Web (WWW) site.

The web site is used by Microchip as a means to make

files and information easily available to customers. To

view the site, the user must have access to the Internet

and a web browser, such as Netscape or Microsoft

Explorer. Files are also available for FTP download

from our FTP site.

1-800-755-2345 for U.S. and most of Canada, and

1-602-786-7302 for the rest of the world.

980106

ConnectingtotheMicrochipInternetWebSite

The Microchip web site is available by using your

favorite Internet browser to attach to:

www.microchip.com

The file transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.futureone.com/pub/microchip

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User’s Guides, Articles and Sample Programs. A vari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for consideration is:

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PICSTART, PICMASTER and PRO MATE are registered

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• Latest Microchip Press Releases

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All other trademarks mentioned herein are the property of

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• Job Postings

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• Links to other useful web sites related to

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tems, technical information and more

• Listing of seminars and events

1999 Microchip Technology Inc.

21291B-page 67

MCP2510

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

To:

Technical Publications Manager

Reader Response

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RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

Literature Number:

21291B

Device:

MCP2510

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

21291B-page 68

1998 Microchip Technology Inc.

MCP2510

MCP2510 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

MCP2510 T /P

—

P

SO

ST

=

Plastic DIP (300 mil Body), 18-lead

Plastic SOIC (300 mil Body), 18-lead

TSSOP, (4.4 mil), 20-lead

Package:

Temperature

Range:

I

E

=

–40°C to +85°C

–40°C to +125°C

MCP2510

MCP2510T

Device:

(Tape and Reel)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

1999 Microchip Technology Inc.

21291B-page 69

MCP2510

NOTES:

21291B-page 70

1999 Microchip Technology Inc.

MCP2510

L

INDEX

Lenghtening a Bit Period . . . . . . . . . . . . . . . . . . . . . . . . . 35

Listen Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

A

Acknowledge Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

M

B

Maximim Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Message Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . 30

Message Acceptance Filters and Masks . . . . . . . . . . . . . 29

Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Message Reception Flowchart . . . . . . . . . . . . . . . . . . . . . 23

Message Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

BFpctrl - RXNBF Pin Control and Status Register . . . . . . 26

Bit Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Bit Modify Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Bit Timing Configuration Registers . . . . . . . . . . . . . . . . . . 37

Bit Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Bus Activity Wakeup Interrupt. . . . . . . . . . . . . . . . . . . . . . 43

Bus Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Byte Write instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

N

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

O

C

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Oscillator Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Overload Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

CAN Buffers and Protocol Engine Block Diagram . . . . . . . 5

CAN Controller Register Map . . . . . . . . . . . . . . . . . . . . . . 53

CAN Interface AC Characteristics. . . . . . . . . . . . . . . . . . . 60

CAN Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

CAN Protocol Engine Block Diagram . . . . . . . . . . . . . . . . . . 6

CANCTRL - CAN Control Register . . . . . . . . . . . . . . . . . . 50

CANINTE - Interrupt Enable Register . . . . . . . . . . . . . . . . 44

CANSTAT - CAN Status Register. . . . . . . . . . . . . . . . . . . 51

CNF1 - Configuration Register1 . . . . . . . . . . . . . . . . . . . . . 37

CNF2 - Configuration Register2 . . . . . . . . . . . . . . . . . . . . . 38

CNF3 - Configuration Register3 . . . . . . . . . . . . . . . . . . . . 38

Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

CRC Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Crystal/Ceramic Resonator Operation . . . . . . . . . . . . . . . . 47

Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . 6

P

Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Phase Buffer Segments . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Programming Time Segments . . . . . . . . . . . . . . . . . . . . . 36

Propagation Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Protocol Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . 6

R

Read Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Read instruction Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 56

Read Status Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Read Status instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

REC - Receiver Error Count . . . . . . . . . . . . . . . . . . . . . . . 40

Receive Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Receive Buffers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 22

Receive Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Receive Message Buffering . . . . . . . . . . . . . . . . . . . . . . . 21

Receiver Error Passive . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Receiver Overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Receiver Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Remote Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Request To Send (RTS) Instruction . . . . . . . . . . . . . . 55, 57

Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

RXB0BF and RXB1BF Pins . . . . . . . . . . . . . . . . . . . . . . . 21

RXB0CTRL - Receive Buffer 0 Control Register . . . . . . . 24

RXB1CTRL - Receive Buffer 1 Control Register . . . . . . . 25

RXBnDLC - Receive Buffer N Data Length Code . . . . . . . 28

RXBNDm - Receive Buffer N Data Field Byte M . . . . . . . . .28

RXBNEID0 - Receive Buffer N Extended

D

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

E

EFLG - Error Flag Register . . . . . . . . . . . . . . . . . . . . . . . . 41

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 59

Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Error Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 13

Error Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Error Management Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Error Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Error Modes and Error Counters . . . . . . . . . . . . . . . . . . . . 39

Error States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Extended Data Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

External Clock (Osc1) Timing Characteristics . . . . . . . . . . 60

External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

External Series Resonant Crystal Oscillator Circuit . . . . . 48

F

Identifier Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

RXBNEID8 - Receive Buffer N Extended

Identifier Mid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

RXBNSIDH - Receive Buffer N Standard

Identifier High . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

RXBNSIDL - Receive Buffer N Standard

Identifier Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

RXFNEID0 - Acceptance Filter N Extended

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Filter/Mask Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Form Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Frame Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

H

Hard Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

I

Initiating Message Transmission . . . . . . . . . . . . . . . . . . . . 15

Interframe Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Identifier Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

RXFNEID8 - Acceptance Filter N Extended

Identifier Mid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

1999 Microchip Technology Inc.

DS21291B-page 71

MCP2510

RXFNSIDH - Acceptance Filter N Standard

T

Identifier High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

RXFNSIDL - Acceptance Filter N Standard

TEC - Transmitter Error Count . . . . . . . . . . . . . . . . . . . . . 40

Time Quanta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Transmit Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Transmit Message Aborting . . . . . . . . . . . . . . . . . . . . . . . 15

Transmit Message Buffering . . . . . . . . . . . . . . . . . . . . . . . 15

Transmit Message Buffers. . . . . . . . . . . . . . . . . . . . . . . . . 15

Transmit Message Flowchart . . . . . . . . . . . . . . . . . . . . . . 16

Transmit Message Priority . . . . . . . . . . . . . . . . . . . . . . . . 15

Transmitter Error-Passive . . . . . . . . . . . . . . . . . . . . . . . . . 44

Transmitter Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

TXBNCTRL Transmit buffer N Control Register . . . . . . . . 17

TXBNDm - Transmit Buffer N Data Field Byte M . . . . . . . . 20

TXBNEID0 - Transmit Buffer N Extended

Identifier Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

TXBNEID8 - Transmit Buffer N Extended

Identifier Mid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TXBNEIDH - Transmit Buffer N Extended

Identifier High . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TXBNSIDH - Transmit Buffer N Standard

Identifier High . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TXBNSIDL - Transmit Buffer N Standard

Identifier Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

RXMNEID0 - Acceptance Filter Mask N Extended

Identifier Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

RXMNEID8 - Acceptance Filter Mask N Extended

Identifier Mid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

RXMNSIDH - Acceptance Filter Mask N Standard

Identifier High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

RXMNSIDL - Acceptance Filter Mask N Standard

Identifier Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

S

Sample Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Shortening a Bit Period . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

SPI Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .55

SPI PORT AC Characteristics . . . . . . . . . . . . . . . . . . . . . .61

Standard Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Stuff Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Synchronization Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Synchronization Segment . . . . . . . . . . . . . . . . . . . . . . . . .34

Identifier Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TXNRTS Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TXRTSCTRL - TXBNRTS Pin Control and

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Typical System Implementation . . . . . . . . . . . . . . . . . . . . . 4

W

WAKE-UP Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Worldwide Sales and Service . . . . . . . . . . . . . . . . . . . . . . 74

Write Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

DS21291B-page 72

1999 Microchip Technology Inc.

MCP2510

LIST OF FIGURES

LIST OF REGISTERS

Figure 1-1:

Figure 1-2:

Figure 1-3:

Block Diagram .............................................. 3

Typical System Implementation.................... 4

Can Buffers And Protocol Engine

Register 3-1: TXBNCTRL Transmit Buffer N Control

Register...................................................... 17

Register 3-2: TXRTSCTRL - TXNRTS Pin Control

And Status Register .................................. 18

Register 3-3: TXBNSIDH - Transmit Buffer N

Standard Identifier High ............................. 18

Register 3-4: TXBNSIDL - Transmit Buffer N

Standard Identifier Low ............................. 19

Register 3-5: TXBNEID8 - Transmit Buffer N

Extended Identifier Mid .............................. 19

Register 3-6: TXBNEID0 - Transmit Buffer N

Extended Identifier Low ............................. 19

Register 3-7: TXBNDLC - Transmit Buffer N

Data Length Code ..................................... 20

Register 3-8: TXBNDM - Transmit Buffer N Data Field

Byte M ....................................................... 20

Register 4-1: RXB0CTRL - Receive Buffer 0 Control

Register .................................................... 24

Register 4-2: RXB1CTRL - Receive Buffer 1 Control

Register ..................................................... 25

Register 4-3: BFPCTRL - RXNBF Pin Control And

Status Register .......................................... 26

Register 4-4: RXBNSIDH - Receive Buffer N Standard

Identifier High ............................................ 26

Register 4-5: RXBNSIDL - Receive Buffer N Standard

Identifier Low ............................................. 27

Register 4-6: RXBNEID8 - Receive Buffer N Extended

Identifier Mid .............................................. 27

Register 4-7: RXBNEID0 - Receive Buffer N Extended

Identifier Low ............................................. 27

Register 4-8: RXBNDLC - Receive Buffer N Data Length

Code .......................................................... 28

Register 4-9: RXBNDM - Receive Buffer N Data Field

Byte M ....................................................... 28

Register 4-10: RXFNSIDH - Acceptance Filter N Standard

Identifier High ............................................ 30

Register 4-11: RXFNSIDl - Acceptance Filter N Standard

Identifier Low ............................................. 30

Register 4-12: RXFNEID8 - Acceptance Filter N Extended

Identifier Mid .............................................. 31

Register 4-13: RXFNEID0 - Acceptance Filter N Extended

Identifier Low ............................................. 31

Register 4-14: RXMNSIDH - Acceptance Filter Mask N

Standard Identifier High ............................. 31

Register 4-15: RXMNSIDl - Acceptance Filter Mask N

Standard Identifier Low ............................. 31

Register 4-16: RXMNEID8 - Acceptance Filter Mask N

Extended Identifier Mid .............................. 32

Register 4-17: RXMNEID0 - Acceptance Filter Mask N

Extended Identifier Low ............................. 32

Block Diagram .............................................. 5

Can Protocol Engine Block Diagram ............ 6

Standard Data Frame ................................... 9

Extended Data Frame................................. 10

Remote Data Frame ................................... 11

Error Frame ................................................ 12

Overload Frame ...................................... 13

Transmit Message Flowchart...................... 16

Receive Buffer Block Diagram.................... 22

Message Reception Flowchart ................... 23

Message Acceptance Filter ....................... 30

Bit Time Partitioning.................................... 33

Lengthening A Bit Period .......................... 35

Shortening A Bit Period ............................ 36

Error Modes ............................................... 40

Crystal/Ceramic Resonator Operation........ 47

External Clock Source ................................ 47

External Series Resonant Crystal

Figure 1-4:

Figure 2-1:

Figure 2-2:

Figure 2-3:

Figure 2-4:

Figure 2-5:

Figure 3-1:

Figure 4-1:

Figure 4-2:

Figure 4-3:

Figure 5-1:

Figure 5-2:

Figure 5-3:

Figure 6-1:

Figure 8-1:

Figure 8-2:

Figure 8-3:

Oscillator Circuit ......................................... 48

Figure 11-1: Bit Modify Command Example ................... 55

Figure 11-2: Read Instruction.......................................... 56

Figure 11-3: Byte Write Instruction.................................. 56

Figure 11-4: Request To Send (RTS) Instruction............ 57

Figure 11-5: Bit Modify Instruction .................................. 57

Figure 11-6: Read Status Instruction .............................. 57

Figure 11-7: Reset Instruction......................................... 57

Figure 11-8: SPI Input Timing ......................................... 58

Figure 11-9: SPI Output Timing ...................................... 58

LIST OF TABLES

Table 1-1:

Table 4-10:

Table 7-1:

Pin Descriptions............................................ 4

Filter/Mask Truth Table............................... 29

ICOD<2:0> Decode .................................... 43

CAN Controller Register Map ..................... 53

CAN Controller Register Summary............. 53

SPI Instruction Set...................................... 56

DC Characteristics...................................... 59

Oscillator Timing Characteristics ................ 60

CAN Interface AC Characteristics ............. 60

CLKOUT Pin AC/DC Characteristics.......... 60

SPI Interface AC Characteristics ................ 61

Table 10-1:

Table 10-2:

Table 11-1:

Table 12-1:

Table 12-2:

Table 12-3:

Table 12-4:

Table 12-5:

Register 5-1: CNF1 - Configuration Register1

Register 5-2: CNF2 - Configuration Register2 ............. 38

Register 5-3: CNF3 - Configuration Register3 ............ 38

............ 37

Register 6-1: TEC - Transmitter Error Count .................. 40

Register 6-2: REC - Receiver Error Count ...................... 40

Register 6-3: EFLG - Error Flag Register

.................. 41

Register 7-1: CANINTE - Interrupt Enable Register ........ 44

Register 7-2: CANINTF - Interrupt FLAG Register .......... 45

Register 9-1: CANCTRL - CAN Control Register ............ 50

Register 9-2: CANSTAT - CAN Status Register ............. 51

1999 Microchip Technology Inc.

DS21291B-page 73

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®

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Our field-programmable PICmicro 8-

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Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed

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DS21291B-page 74

1999 Microchip Technology Inc.


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