MCP3201T-I/SN_技术文档

MCP3201

2.7V 12-Bit A/D Converter with SPI^™Serial Interface

Features

Package Types

• 12-bit resolution

MSOP, PDIP, SOIC, TSSOP

• ±1 LSB max DNL

• ±1 LSB max INL (MCP3201-B)

• ±2 LSB max INL (MCP3201-C)

• On-chip sample and hold

• SPI^™serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V - 5.5V

• 100ksps max. sampling rate at V_DD= 5V

• 50ksps max. sampling rate at V_DD= 2.7V

• Low power CMOS technology

V_REF

1

8

V_DD

IN+

IN–

V_SS

2

3

4

7

6

5

CLK

D_OUT

CS/SHDN

• 500 nA typical standby current, 2 µA max.

• 400 µA max. active current at 5V

• Industrial temp range: -40°C to +85°C

• 8-pin MSOP, PDIP, SOIC and TSSOP packages

Functional Block Diagram

V_SS

V_DD

V_REF

Applications

• Sensor Interface

DAC

• Process Control

Comparator

• Data Acquisition

12-Bit SAR

• Battery Operated Systems

IN+

IN-

Sample

and

Hold

Description

The Microchip Technology Inc. MCP3201 is a succes-

sive approximation 12-bit Analog-to-Digital (A/D) Con-

verter with on-board sample and hold circuitry. The

device provides a single pseudo-differential input. Dif-

ferential Nonlinearity (DNL) is specified at ±1 LSB, and

Integral Nonlinearity (INL) is offered in ±1 LSB

(MCP3201-B) and ±2 LSB (MCP3201-C) versions.

Communication with the device is done using a simple

serial interface compatible with the SPI protocol. The

device is capable of sample rates of up to 100 ksps at

a clock rate of 1.6 MHz. The MCP3201 operates over

a broad voltage range (2.7V - 5.5V). Low current

design permits operation with typical standby and

active currents of only 500 nA and 300 µA, respec-

tively. The device is offered in 8-pin MSOP, PDIP,

TSSOP and 150 mil SOIC packages.

Shift

Register

Control Logic

CS/SHDN CLK

D_OUT

DS21290D-page 1

MCP3201

1.0

ELECTRICAL

PIN FUNCTION TABLE

CHARACTERISTICS

Name

Function

1.1

Maximum Ratings*

V_DD

+2.7V to 5.5V Power Supply

Ground

V_SS

V_DD.........................................................................7.0V

All inputs and outputs w.r.t. V_SS...... -0.6V to V_DD+0.6V

Storage temperature ..........................-65°C to +150°C

Ambient temp. with power applied .....-65°C to +125°C

ESD protection on all pins (HBM).......................> 4 kV

IN+

Positive Analog Input

Negative Analog Input

Serial Clock

IN-

CLK

D_OUT

CS/SHDN

V_REF

Serial Data Out

Chip Select/Shutdown Input

Reference Voltage Input

*Notice: Stresses above those listed under “Maximum ratings” may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at those or any other conditions

above those indicated in the operational listings of this specification is

not implied. Exposure to maximum rating conditions for extended peri-

ods may affect device reliability.

ELECTRICAL CHARACTERISTICS

All parameters apply at V_DD= 5V, V_SS= 0V, V_REF= 5V, T_AMB= -40°C to +85°C, f_SAMPLE= 100 ksps, and f_CLK= 16*f_SAMPLE

unless otherwise noted.

Parameter

Conversion Rate:

Sym

Min

Typ

Max

Units

Conditions

Conversion Time

t_CONV

t_SAMPLE

f_SAMPLE

—

1.5

—

12

clock

cycles

Analog Input Sample Time

Throughput Rate

clock

cycles

—

100

50

ksps

V_DD= V_REF= 5V

_DD= V_REF= 2.7V

V

DC Accuracy:

Resolution

12

bits

Integral Nonlinearity

INL

—

±0.75

±1

±2

LSB

MCP3201-B

MCP3201-C

Differential Nonlinearity

DNL

—

±0.5

±1

LSB

No missing codes over

temperature

Offset Error

—

±1.25

±3

±5

LSB

Gain Error

Dynamic Performance:

Total Harmonic Distortion

THD

—

-82

72

—

dB

V_IN= 0.1V to 4.9V@1 kHz

Signal to Noise and Distortion

(SINAD)

SINAD

Spurious Free Dynamic Range

Reference Input:

SFDR

—

86

—

dB

V_IN= 0.1V to 4.9V@1 kHz

Voltage Range

0.25

V_DD

V

Note 2

Current Drain

—

100

.001

150

3

µA

CS = V_DD= 5V

Analog Inputs:

Input Voltage Range (IN+)

IN+

IN-

—

V_REF+IN-

V_SS+100

V

Input Voltage Range (IN-)

V

_SS-100

mV

Leakage Current

Switch Resistance

—

0.001

1K

±1

—

µA

W

R_SS

See Figure 4-1

Note 1: This parameter is established by characterization and not 100% tested.

2: See graph that relates linearity performance to V_REFlevel.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,

especially at elevated temperatures. See Section 6.2 for more information.

DS21290D-page 2

MCP3201

ELECTRICAL CHARACTERISTICS (CONTINUED)

All parameters apply at V_DD= 5V, V_SS= 0V, V_REF= 5V, T_AMB= -40°C to +85°C, f_SAMPLE= 100 ksps, and f_CLK= 16*f_SAMPLE

unless otherwise noted.

Parameter

Sample Capacitor

Sym

Min

Typ

Max

Units

Conditions

See Figure 4-1

C_SAMPLE

—

20

—

pF

Digital Input/Output:

Data Coding Format

High Level Input Voltage

Straight Binary

—

V_IH

V_IL

0.7 V_DD

—

0.3 V_DD

—

V

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Output Leakage Current

—

V_OH

4.1

—

V

I_OH= -1 mA, V_DD= 4.5V

I_OL= 1 mA, V_DD= 4.5V

V_IN= V_SSor V_DD

V_OL

0.4

V

I_LI

-10

—

10

µA

pF

I_LO

10

V_OUT= V_SSor V_DD

Pin Capacitance

C_IN, C_OUT

10

V_DD= 5.0V (Note 1)

(all inputs/outputs)

T_AMB= 25°C, f = 1 MHz

Timing Parameters:

Clock Frequency

f_CLK

—

1.6

0.8

MHz

V_DD= 5V (Note 3)

_DD= 2.7V (Note 3)

V

Clock High Time

t_HI

t_LO

t_SUCS

t_DO

312

100

—

ns

Clock Low Time

CS Fall To First Rising CLK Edge

CLK Fall To Output Data Valid

CLK Fall To Output Enable

CS Rise To Output Disable

—

200

100

See Test Circuits, Figure 1-2

t_EN

—

t_DIS

—

See Test Circuits, Figure 1-2

(Note 1)

CS Disable Time

t_CSH

625

—

ns

D

_OUTRise Time

t

100

See Test Circuits, Figure 1-2

(Note 1)

R

D_OUTFall Time

t

—

100

ns

See Test Circuits, Figure 1-2

F

(Note 1)

Power Requirements:

Operating Voltage

V_DD

I_DD

2.7

—

5.5

V

Operating Current

—

300

210

400

—

µA

V_DD= 5.0V, D_OUTunloaded

V_DD= 2.7V, D_OUTunloaded

Standby Current

I_DDS

—

0.5

2

µA

CS = V_DD= 5.0V

Temperature Ranges:

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistance:

Thermal Resistance, 8L-PDIP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-TSSOP

T_A

-40

-65

—

+85

°C

+150

q_JA

—

85

—

°C/W

163

206

124

Note 1: This parameter is established by characterization and not 100% tested.

2: See graph that relates linearity performance to V_REFlevel.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,

especially at elevated temperatures. See Section 6.2 for more information.

DS21290D-page 3

MCP3201

t_CSH

CS

t_SUCS

t_HI

t_LO

CLK

t_EN

t_DO

t_DIS

t_R

t_F

HI-Z

D_OUT

MSB OUT

LSB

NULL BIT

FIGURE 1-1: Serial Timing.

Load circuit for t_DISand t_EN

Load circuit for t_R, t_F, t_DO

1.4V

Test Point

V_DD

t_DISWaveform 2

t_ENWaveform

3 kΩ

Test Point

V_DD/2

3 kΩ

D_OUT

30 pF

t_DISWaveform 1

C_L= 30 pF

V_SS

Voltage Waveforms for t_R, t_F

Voltage Waveforms for t_EN

V_OH

V_OL

D_OUT

CS

t_F

t_R

1

2

3

4

CLK

D_OUT

B9

t_EN

Voltage Waveforms for t_DO

Voltage Waveforms for t_DIS

V_IH

CS

CLK

D_OUT

Waveform 1*

90%

t_DO

t_DIS

D_OUT

10%

D_OUT

Waveform 2†

* Waveform 1 is for an output with internal condi-

tions such that the output is high, unless disabled

by the output control.

† Waveform 2 is for an output with internal condi-

tions such that the output is low, unless disabled

by the output control.

FIGURE 1-2: Test Circuits.

DS21290D-page 4

MCP3201

2.0

TYPICAL PERFORMANCE CHARACTERISTICS

Note: The graphs provided following this note are a statistical summary based on a limited number of samples

and are provided for informational purposes only. The performance characteristics listed herein are not

tested or guaranteed. In some graphs, the data presented may be outside the specified operating range

(e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE,T_A= 25°C

1.0

2.0

V_DD= V_REF= 2.7V

Positive INL

0.8

0.6

Positive INL

Negative INL

1.5

1.0

0.4

0.5

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.5

-1.0

-1.5

-2.0

Negative INL

0

20

40

60

80

100

0

25

50

75

100

125

150

Sample Rate (ksps)

FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample

FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample

Rate.

Rate (V_DD= 2.7V).

2.0

1.5

1.0

2.0

V_DD= 2.7V

1.5

F

_SAMPLE= 50 ksps

1.0

0.5

Positive INL

0.5

0.0

-0.5

-1.0

-1.5

-2.0

Negative INL

-1.0

-1.5

-2.0

0

1

2

3

4

5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

V_REF(V)

FIGURE 2-2: Integral Nonlinearity (INL) vs. V_REF.

FIGURE 2-5: Integral Nonlinearity (INL) vs. V_REF

(V_DD= 2.7V).

1.0

0.8

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Digital Code

FIGURE 2-3: Integral Nonlinearity (INL) vs. Code

FIGURE 2-6: Integral Nonlinearity (INL) vs. Code

(Representative Part).

(Representative Part, V_DD= 2.7V).

DS21290D-page 5

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE,T_A= 25°C

1.0

0.8

1.0

0.8

V_DD= V_REF= 2.7V

_SAMPLE= 50 ksps

Positive INL

F

0.6

Positive INL

0.4

0.2

0.0

Negative INL

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

Negative INL

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-10: Integral

Nonlinearity

(INL)

vs.

FIGURE 2-7: Integral

Nonlinearity

(INL)

vs.

Temperature (V_DD= 2.7V).

Temperature.

1.0

0.8

0.6

0.4

2.0

V_DD= V_REF= 2.7V

1.5

1.0

Positive DNL

0.5

0.0

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.5

-1.0

-1.5

-2.0

Negative DNL

0

25

50

75

100

125

150

0

20

40

60

80

100

Sample Rate (ksps)

FIGURE 2-11: Differential Nonlinearity (DNL) vs.

FIGURE 2-8: Differential Nonlinearity (DNL) vs.

Sample Rate (V_DD= 2.7V).

Sample Rate.

3.0

2.0

3.0

V_DD= 2.7V

2.0

1.0

F_SAMPLE= 50 ksps

Positive DNL

Negative DNL

1.0

Positive DNL

0.0

-1.0

-2.0

-3.0

Negative DNL

-1.0

-2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0

1

2

3

4

5

V_REF(V)

FIGURE 2-12: Differential Nonlinearity (DNL) vs. V_REF

(V_DD= 2.7V).

FIGURE 2-9: Differential Nonlinearity (DNL) vs.

V_REF

.

DS21290D-page 6

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE,T_A= 25°C

1.0

0.8

1.0

0.8

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Digital Code

FIGURE 2-13: Differential Nonlinearity (DNL) vs.

FIGURE 2-16: Differential Nonlinearity (DNL) vs.

Code (Representative Part).

Code (Representative Part, V_DD= 2.7V).

1.0

0.8

0.6

1.0

V_DD= V_REF= 2.7V

0.8

F_SAMPLE= 50 ksps

0.6

Positive DNL

0.4

Positive DNL

0.2

0.0

0.2

0.0

-0.2

Negative DNL

-0.4

-0.6

-0.8

-1.0

-0.6

-0.8

-1.0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-14: Differential Nonlinearity (DNL) vs.

FIGURE 2-17: Differential Nonlinearity (DNL) vs.

Temperature.

Temperature (V_DD= 2.7V).

20

18

5

4

16

14

12

10

8

V_DD= 5V

V_DD= 2.7V

3

F_SAMPLE= 100 ksps

F_SAMPLE= 50 ksps

2

1

V_DD= 2.7V

6

0

F_SAMPLE= 50ksps

V_DD= 5V

_SAMPLE= 100 ksps

4

-1

-2

F

2

0

1

2

3

4

5

0

1

2

3

4

5

V_REF(V)

FIGURE 2-15: Gain Error vs. V_REF

.

FIGURE 2-18: Offset Error vs. V_REF.

DS21290D-page 7

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE,T_A= 25°C

1.0

0.8

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.6

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

V_DD= V_REF= 5V

_SAMPLE= 100 ksps

0.4

F

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

V_DD= V_REF= 2.7V

_SAMPLE= 50 ksps

F

V_DD= V_REF= 5V

F_SAMPLE= 100 ksps

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-19: Gain Error vs. Temperature.

FIGURE 2-22: Offset Error vs. Temperature.

100

V_DD= V_REF= 5V

F_SAMPLE= 100 ksps

V_DD= V_REF= 5V

_SAMPLE= 100 ksps

90

80

70

60

50

40

30

20

10

0

90

F

80

70

60

50

40

30

20

10

0

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

V_DD= V_REF= 2.7V

_SAMPLE= 50 ksps

F

1

10

100

1

10

100

Input Frequency (kHz)

FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input

FIGURE 2-23:

Signal to Noise and Distortion

Frequency.

(SINAD) vs. Input Frequency.

0

-10

-20

-30

80

V_DD= V_REF= 5V

F_SAMPLE= 100 ksps

70

60

50

40

30

20

10

0

-40

-50

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

V_DD= V_REF= 2.7V

_SAMPLE= 50 ksps

F

-60

-70

-80

-90

V_DD= V_REF= 5V, F_SAMPLE= 100 ksps

10

-100

-40

-35

-30

-25

-20

-15

-10

-5

0

1

100

Input Signal Level (dB)

Input Frequency (kHz)

FIGURE 2-21: Total Harmonic Distortion (THD) vs.

FIGURE 2-24:

Signal to Noise and Distortion

Input Frequency.

(SINAD) vs. Input Signal Level.

DS21290D-page 8

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE,T_A= 25°C

12.0

11.5

11.0

10.5

10.0

9.5

12.00

11.75

11.50

11.25

11.00

10.75

10.50

10.25

10.00

9.75

V_DD= 5V

_SAMPLE= 100 ksps

F

V_DD= V_REF= 5V

F_SAMPLE=100 ksps

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

9.0

V_DD= 2.7V

_SAMPLE= 50 ksps

9.50

9.25

8.5

F

9.00

8.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

1

10

100

V_REF(V)

Input Frequency (kHz)

FIGURE 2-25: Effective Number of Bits (ENOB) vs.

V_REF

FIGURE 2-28: Effective Number of Bits (ENOB) vs.

Input Frequency.

.

0

-10

-20

-30

-40

-50

-60

-70

-80

100

90

80

70

60

50

40

30

20

10

0

V_DD= V_REF= 5V, F_SAMPLE= 100 ksps

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

1

10

100

1

10

100

1000

10000

Input Frequency (kHz)

Ripple Frequency (kHz)

FIGURE 2-26: Spurious Free Dynamic Range

FIGURE 2-29: Power Supply Rejection (PSR) vs.

(SFDR) vs. Input Frequency.

Ripple Frequency.

0

-10

-20

-30

-40

0

-10

-20

-30

-40

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

V_DD= V_REF= 5V

F_SAMPLE= 100 ksps

F_INPUT= 998.76 Hz

F_INPUT= 9.985kHz

4096 points

-50

-60

-70

-80

-90

-100

-110

-120

-130

-100

-110

-120

-130

0

10000

20000

30000

40000

50000

0

5000

10000

15000

20000

25000

Frequency (Hz)

FIGURE 2-27: Frequency Spectrum of 10 kHz input

FIGURE 2-30: Frequency Spectrum of 1 kHz input

(Representative Part).

(Representative Part, V_DD= 2.7V).

DS21290D-page 9

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE,T_A= 25°C

500

100

V_{REF =}V_DD

V_REF= V_DD

450

400

350

300

250

200

150

100

50

90

80

70

60

50

40

30

20

10

0

All points at F_CLK= 1.6 MHz, except

at V_REF= V_DD= 2.5V, F_CLK= 800 kHz

All points at F_CLK= 1.6 MHz, except

at V_REF= V_DD= 2.5V, F_CLK= 800 kHz

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

10000

100

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

V_DD(V)

FIGURE 2-31: I_DDvs. V_DD

.

FIGURE 2-34: I_REFvs. V_DD

.

400

350

100

90

80

70

60

50

40

30

20

10

0

V_DD= V_REF= 5V

300

250

200

150

100

50

V_DD= V_REF= 2.7V

0

10

100

1000

10

100

1000

10000

Clock Frequency (kHz)

FIGURE 2-35: I_REFvs. Clock Frequency.

FIGURE 2-32: I_DDvs. Clock Frequency.

400

100

V_DD= V_REF= 5V

_CLK= 1.6 MHz

90

80

70

60

50

40

30

20

10

0

V_DD= V_REF= 5V

F_CLK= 1.6 MHz

350

300

250

200

150

100

50

F

V_DD= V_REF= 2.7V

_CLK= 800 kHz

F

V_DD= V_REF= 2.7V

_CLK= 800 kHz

F

0

-50

-25

0

25

50

75

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-36: I_REFvs. Temperature.

FIGURE 2-33: I_DDvs. Temperature.

DS21290D-page 10

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE,T_A= 25°C

80

70

60

50

40

30

20

10

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

V_REF= CS = V_DD

V_DD= V_REF= 5V

F_CLK= 1.6 MHz

-50

-25

0

25

50

75

100

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Temperature (°C)

V_DD(V)

FIGURE 2-39: Analog Input Leakage Current vs.

Temperature.

FIGURE 2-37: I_DDSvs. V_DD

.

100.00

V_DD= V_REF= CS = 5V

10.00

1.00

0.10

0.01

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-38: I_DDSvs. Temperature.

DS21290D-page 11

MCP3201

In this diagram, it is shown that the source impedance

(R_S) adds to the internal sampling switch (R_SS) imped-

ance, directly affecting the time that is required to

charge the capacitor (C_SAMPLE). Consequently, a larger

source impedance increases the offset, gain, and inte-

gral linearity errors of the conversion.

3.0

PIN DESCRIPTIONS

3.1

IN+

Positive analog input. This input can vary from IN- to

V_REF+ IN-.

Ideally, the impedance of the signal source should be

near zero. This is achievable with an operational ampli-

fier such as the MCP601, which has a closed loop out-

put impedance of tens of ohms. The adverse affects of

higher source impedances are shown in Figure 4-2.

3.2

IN-

Negative analog input. This input can vary ±100 mV

from V_SS.

3.3

Chip Select/Shutdown (CS/SHDN)

If the voltage level of IN+ is equal to or less than IN-, the

resultant code will be 000h. If the voltage at IN+ is equal

to or greater than {[V_REF+ (IN-)] - 1 LSB}, then the out-

put code will be FFFh. If the voltage level at IN- is more

than 1 LSB below V_SS, then the voltage level at the IN+

input will have to go below V_SSto see the 000h output

code. Conversely, if IN- is more than 1 LSB above

Vss, then the FFFh code will not be seen unless the

IN+ input level goes above V_REFlevel.

The CS/SHDN pin is used to initiate communication

with the device when pulled low and will end a conver-

sion and put the device in low power standby when

pulled high. The CS/SHDN pin must be pulled high

between conversions.

3.4

Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and to

clock out each bit of the conversion as it takes place.

See Section 6.2 for constraints on clock speed.

4.2

Reference Input

3.5

Serial Data Output (DOUT)

The reference input (V_REF) determines the analog input

voltage range and the LSB size, as shown below.

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place.

V_REF

LSB Size = ------------

4096

As the reference input is reduced, the LSB size is

reduced accordingly. The theoretical digital output code

produced by the A/D Converter is a function of the ana-

log input signal and the reference input as shown

below.

4.0

DEVICE OPERATION

The MCP3201 A/D Converter employs a conventional

SAR architecture. With this architecture, a sample is

acquired on an internal sample/hold capacitor for

1.5 clock cycles starting on the first rising edge of the

serial clock after CS has been pulled low. Following this

sample time, the input switch of the converter opens

and the device uses the collected charge on the inter-

nal sample and hold capacitor to produce a serial 12-bit

digital output code. Conversion rates of 100 ksps are

possible on the MCP3201. See Section 6.2 for informa-

tion on minimum clock rates. Communication with the

device is done using a 3-wire SPI-compatible interface.

4096*V_IN

Digital Output Code = ------------------------

V_REF

where:

V_IN= analog input voltage = V(IN+) - V(IN-)

V_REF= reference voltage

When using an external voltage reference device, the

system designer should always refer to the manufac-

turer’s recommendations for circuit layout. Any instabil-

ity in the operation of the reference device will have a

direct effect on the operation of the A/D Converter.

4.1

Analog Inputs

The MCP3201 provides a single pseudo-differential

input. The IN+ input can range from IN- to V_REF

(V_REF+IN-). The IN- input is limited to ±100 mV from the

V_SSrail. The IN- input can be used to cancel small sig-

nal common-mode noise which is present on both the

IN+ and IN- inputs.

For the A/D Converter to meet specification, the charge

holding capacitor (C_SAMPLE) must be given enough time

to acquire a 12-bit accurate voltage level during the

1.5 clock cycle sampling period. The analog input

model is shown in Figure 4-1.

DS21290D-page 12

MCP3201

V_DD

Sampling

Switch

V_T= 0.6V

R_S= 1 kΩ

CHx

SS

R_SS

C_SAMPLE

= DAC capacitance

= 20 pF

C_PIN

7 pF

I_LEAKAGE

±1 nA

VA

V_SS

LEGEND

VA

=

Signal Source

R

Source Impedance

Input Channel Pad

ss

CHX

C_PIN

Input Pin Capacitance

Threshold Voltage

V_T

I_LEAKAGE

Leakage Current At The Pin

Due To Various Junctions

Sampling Switch

SS

=

R

Sampling Switch Resistor

Sample/hold Capacitance

s

C_SAMPLE

FIGURE 4-1: Analog Input Model.

1.8

1.6

1.4

1.2

1.0

0.8

V_DD= V_REF= 5V

V_DD= V_REF= 2.7V

0.6

0.4

0.2

0.0

100

1000

10000

Input Resistance (Ohms)

FIGURE 4-2: Maximum Clock Frequency vs. Input

Resistance (R_S) to maintain less than a 0.1 LSB

deviation in INL from nominal conditions.

DS21290D-page 13

MCP3201

sion with MSB first, as shown in Figure 5-1. Data is

always output from the device on the falling edge of the

clock. If all 12 data bits have been transmitted and the

device continues to receive clocks while the CS is held

low, the device will output the conversion result LSB

first, as shown in Figure 5-2. If more clocks are pro-

vided to the device while CS is still low (after the LSB

first data has been transmitted), the device will clock

out zeros indefinitely.

5.0

SERIAL COMMUNICATIONS

Communication with the device is done using a stan-

dard SPI-compatible serial interface. Initiating commu-

nication with the MCP3201 begins with the CS going

low. If the device was powered up with the CS pin low,

it must be brought high and back low to initiate commu-

nication. The device will begin to sample the analog

input on the first rising edge after CS goes low. The

sample period will end in the falling edge of the second

clock, at which time the device will output a low null bit.

The next 12 clocks will output the result of the conver-

t_CYC

T_CSH

CS

POWER

DOWN

T_SUCS

CLK

t_DATA**

t_CONV

B7 B6

T_SAMPLE

HI-Z

NULL

BIT

NULL

BIT

D_OUT

B11 B10 B9

B8

B5

B4

B3

B2

B1 B0*

B11 B10 B9

B8

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed

by zeros indefinitely. See Figure below.

** t_DATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance

node, leaving the CLK running to clock out the LSB-first data or zeros.

FIGURE 5-1: Communication with MCP3201 using MSB first Format.

t_CYC

t_CSH

CS

t_SUCS

POWER DOWN

CLK

t_SAMPLE

t_DATA**

t_CONV

HI-Z

NULL

BIT

D_OUT

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11*

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.

** t_DATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance

node, leaving the CLK running to clock out the LSB-first data or zeros.

FIGURE 5-2: Communication with MCP3201 using LSB first Format.

DS21290D-page 14

MCP3201

controller’s receive buffer will contain two unknown bits

(the output is at high impedance for the first two

clocks), the null bit and the highest order five bits of the

conversion. After the second eight clocks have been

sent to the device, the MCU receive register will contain

the lowest order seven bits and the B1 bit repeated as

the A/D Converter has begun to shift out LSB first data

with the extra clock. Typical procedure would then call

for the lower order byte of data to be shifted right by one

bit to remove the extra B1 bit. The B7 bit is then trans-

ferred from the high order byte to the lower order byte,

and then the higher order byte is shifted one bit to the

right as well. Easier manipulation of the converted data

can be obtained by using this method.

6.0

APPLICATIONS INFORMATION

6.1

Using the MCP3201 with

Microcontroller SPI Ports

With most microcontroller SPI ports, it is required to

clock out eight bits at a time. If this is the case, it will be

necessary to provide more clocks than are required for

the MCP3201. As an example, Figure 6-1 and

Figure 6-2 show how the MCP3201 can be interfaced

to a microcontroller with a standard SPI port. Since the

MCP3201 always clocks data out on the falling edge of

clock, the MCU SPI port must be configured to match

this operation. SPI Mode 0,0 (clock idles low) and SPI

Mode 1,1 (clock idles high) are both compatible with

the MCP3201. Figure 6-1 depicts the operation shown

in SPI Mode 0,0, which requires that the CLK from the

microcontroller idles in the ‘low’ state. As shown in the

diagram, the MSB is clocked out of the A/D Converter

on the falling edge of the third clock pulse. After the first

eight clocks have been sent to the device, the micro-

Figure 6-2 shows the same thing in SPI Mode 1,1

which requires that the clock idles in the high state. As

with mode 0,0, the A/D Converter outputs data on the

falling edge of the clock and the MCU latches data from

the A/D Converter in on the rising edge of the clock.

CS

MCU latches data from A/D

Converter on rising edges of SCLK

CLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

B1

Data is clocked out of A/D

Converter on falling edges

HI-Z

B2

NULL

BIT

B11 B10 B9

B7

B6

B5 B4 B3 B2 B1 B0

B8

D_OUT

LSB first data begins

to come out

?

0

B11 B10 B9 B8 B7

B6 B5 B4 B3 B2 B1 B0 B1

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

CS

MCU latches data from A/D

Converter on rising edges of SCLK

CLK

1

2

3

4

5

6

7

8

9

10

11

12

13 14

15

16

B1

Data is clocked out of A/D

Converter on falling edges

HI-Z

NULL

BIT

B11 B10 B9 B8

B7

B6 B5 B4 B3 B2 B1 B0

D_OUT

LSB first data begins

to come out

?

0

B11 B10 B9 B8 B7

B6 B5 B4 B3 B2 B1 B0 B1

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

DS21290D-page 15

MCP3201

6.2

Maintaining Minimum Clock Speed

6.4

Layout Considerations

When the MCP3201 initiates the sample period, charge

is stored on the sample capacitor. When the sample

period is complete, the device converts one bit for each

clock that is received. It is important for the user to note

that a slow clock rate will allow charge to bleed off the

sample cap while the conversion is taking place. At

85°C (worst case condition), the part will maintain

proper charge on the sample capacitor for at least

1.2 ms after the sample period has ended. This means

that the time between the end of the sample period and

the time that all 12 data bits have been clocked out

must not exceed 1.2 ms (effective clock frequency of

10 kHz). Failure to meet this criteria may induce linear-

ity errors into the conversion outside the rated specifi-

cations. It should be noted that during the entire

conversion cycle, the A/D Converter does not require a

constant clock speed or duty cycle, as long as all timing

specifications are met.

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

noise wherever possible. A bypass capacitor should

always be used with this device and should be placed

as close as possible to the device pin. A bypass capac-

itor value of 1 µF is recommended.

Digital and analog traces should be separated as much

as possible on the board and no traces should run

underneath the device or the bypass capacitor. Extra

precautions should be taken to keep traces with high

frequency signals (such as clock lines) as far as possi-

ble from analog traces.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing V_DDconnections to

devices in a “star” configuration can also reduce noise

by eliminating current return paths and associated

errors. See Figure 6-4. For more information on layout

tips when using A/D Converter, refer to AN688 “Layout

Tips for 12-Bit A/D Converter Applications”.

6.3

Buffering/Filtering the Analog Inputs

If the signal source for the A/D Converter is not a low

impedance source, it will have to be buffered or inaccu-

rate conversion results may occur. See Figure 4-2. It is

also recommended that a filter be used to eliminate any

signals that may be aliased back into the conversion

results. This is illustrated in Figure 6-3 where an op

amp is used to drive the analog input of the MCP3201.

This amplifier provides a low impedance source for the

converter input and a low pass filter, which eliminates

unwanted high frequency noise.

V_DD

Connection

Device 4

Low pass (anti-aliasing) filters can be designed using

Microchip’s interactive FilterLab™ software. FilterLab

will calculate capacitor and resistor values, as well as

determine the number of poles that are required for the

application. For more information on filtering signals,

see the application note AN699 “Anti-Aliasing Analog

Filters for Data Acquisition Systems.”

Device 1

Device 3

Device 2

V_DD

FIGURE 6-4: V_DDtraces arranged in

configuration in order to reduce errors caused by

current return paths.

a

‘Star’

10 µF

4.096V

Reference

10 µF

C_L

0.1 µF

MCP1541

1 µF

V_REF

IN+

MCP3201

IN-

C₁

MCP601

R₁

V_IN

+

R₂

C₂

-

R₄

R₃

FIGURE 6-3: The MCP601 Operational Amplifier is

used to implement a 2nd order anti-aliasing filter for

the signal being converted by the MCP3201.

DS21290D-page 16

MCP3201

7.0

PACKAGING INFORMATION

7.1

Package Marking Information

8-Lead PDIP (300 mil)

Example:

XXXXXXXX

XXXXXNNN

MCP3201

I/PNNN

e

3

YYWW

0725

8-Lead SOIC (150 mil)

Example:

XXXXXXXX

MCP3201

XXXXYYWW

ISN 0725

e

3

NNN

Example:

8-Lead MSOP

XXXXXX

3201I

e

3

YWWNNN

725NNN

Example:

8-Lead TSSOP

3201

0725

NNN

XXXX

YYWW

NNN

e3

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21290D-page 17

MCP3201

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

A1

c

e

eB

b1

b

Units

INCHES

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.348

.115

.008

.040

.014

–

.130

–

.310

.250

.365

.130

.010

.060

.018

–

.325

.280

.400

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-018B

DS21290D-page 18

MCP3201

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

e

N

E

E1

NOTE 1

1

2

3

α

h

b

h

c

φ

A2

A

L

A1

L1

β

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff

A2

A1

E

1.25

0.10

–

§

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

3.90 BSC

4.90 BSC

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-057B

DS21290D-page 19

MCP3201

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

2

b

1

e

c

φ

A2

A

L

L1

A1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

0.65 BSC

Overall Height

A

–

1.10

0.95

0.15

Molded Package Thickness

Standoff

A2

A1

E

0.75

0.00

0.85

–

4.90 BSC

3.00 BSC

0.60

Overall Width

Molded Package Width

Overall Length

Foot Length

E1

D

L

0.40

0.80

Footprint

L1

φ

0.95 REF

–

Foot Angle

0°

8°

Lead Thickness

Lead Width

c

0.08

–

0.23

0.40

b

0.22

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-111B

DS21290D-page 20

MCP3201

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

b

e

c

φ

A

A2

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

0.65 BSC

Overall Height

A

–

1.20

1.05

0.15

Molded Package Thickness

Standoff

A2

A1

E

0.80

0.05

1.00

–

Overall Width

6.40 BSC

Molded Package Width

Molded Package Length

Foot Length

E1

D

4.30

2.90

0.45

4.40

4.50

3.10

0.75

3.00

L

0.60

Footprint

L1

φ

1.00 REF

Foot Angle

0°

–

8°

Lead Thickness

c

0.09

0.20

0.30

Lead Width

b

0.19

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-086B

DS21290D-page 21

MCP3201

NOTES:

DS21290D-page 22

MCP3201

APPENDIX A: REVISION HISTORY

Revision D (January 2007)

This revision includes updates to the packaging

diagrams.

DS21290D-page 23

MCP3201

NOTES:

DS21290D-page 24

MCP3201

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

Examples:

Temperature Package

Range

a)

MCP3201-I/P: Industrial Temperature,

PDIP package.

b)

MCP3201-I/SN: Industrial Temperature,

SOIC package.

Device:

MCP3201: 12-Bit A/D Converter w/SPI Interface

MCP3201T: 12-Bit A/D Converter w/SPI Interface

(Tape and Reel) (SOIC and TSSOP only)

c)

d)

MCP3201-I/ST: Industrial Temperature,

TSSOP package.

MCP3201-I/MS: Industrial Temperature,

MSOP package.

Temperature Range:

Package:

I

=

-40°C to +85°C

MS

P

SN

ST

=

Plastic Micro Small Outline (MSOP), 8-lead

Plastic DIP (300 mil Body), 8-lead

Plastic SOIC (150 mil Body), 8-lead

Plastic TSSOP (4.4 mm), 8-lead

DS21290D-page25

MCP3201

NOTES:

DS21290D-page 26

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS21290D-page 27

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

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Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

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Fax: 43-7242-2244-393

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Chandler, AZ 85224-6199

Tel: 480-792-7200

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Technical Support:

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Web Address:

www.microchip.com

Denmark - Copenhagen

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Boston

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82-2-558-5934

Chicago

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Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS21290D-page 28


型号：	MCP3201T-I/SN
厂家：	MICROCHIP
描述：	2.7V 12-Bit A/D Converter with SPI Serial Interface 2.7V 12位A / D转换器，带有SPI串行接口转换器
文件：	总28页 (文件大小：473K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP3201T-I/SN [MICROCHIP]

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