MCP3208-BI/SL_技术文档

MCP3204/3208

2.7V 4-Channel/8-Channel 12-Bit A/D Converters

with SPI^™Serial Interface

Features

Description

• 12-bit resolution

The Microchip Technology Inc. MCP3204/3208

devices are successive approximation 12-bit Analog-

to-Digital (A/D) Converters with on-board sample and

hold circuitry. The MCP3204 is programmable to pro-

vide two pseudo-differential input pairs or four single-

ended inputs. The MCP3208 is programmable to pro-

vide four pseudo-differential input pairs or eight single-

ended inputs. Differential Nonlinearity (DNL) is speci-

fied at ±1 LSB, while Integral Nonlinearity (INL) is

offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB

(MCP3204/3208-C) versions.

• ± 1 LSB max DNL

• ± 1 LSB max INL (MCP3204/3208-B)

• ± 2 LSB max INL (MCP3204/3208-C)

• 4 (MCP3204) or 8 (MCP3208) input channels

• Analog inputs programmable as single-ended or

pseudo-differential pairs

• On-chip sample and hold

• SPI serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V - 5.5V

• 100 ksps max. sampling rate at V_DD= 5V

• 50 ksps max. sampling rate at V_DD= 2.7V

• Low power CMOS technology:

Communication with the devices is accomplished using

a simple serial interface compatible with the SPI proto-

col. The devices are capable of conversion rates of up

to 100 ksps. The MCP3204/3208 devices operate over

a broad voltage range (2.7V - 5.5V). Low current

design permits operation with typical standby and

active currents of only 500 nA and 320 µA, respec-

tively. The MCP3204 is offered in 14-pin PDIP, 150 mil

SOIC and TSSOP packages. The MCP3208 is offered

in 16-pin PDIP and SOIC packages.

- 500 nA typical standby current, 2 µA max.

- 400 µA max. active current at 5V

• Industrial temp range: -40°C to +85°C

• Available in PDIP, SOIC and TSSOP packages

Applications

• Sensor Interface

Functional Block Diagram

• Process Control

V_SS

V_DD

• Data Acquisition

V_REF

• Battery Operated Systems

CH0

CH1

Input

Channel

Mux

Package Types

PDIP, SOIC, TSSOP

DAC

CH7*

Comparator

CH0

CH1

CH2

CH3

NC

1

2

3

4

5

6

7

14

13

V_DD

V_REF

12-Bit SAR

Sample

12 AGND

and

CLK

11

10

9

Hold

D_OUT

D_IN

Shift

Register

NC

Control Logic

DGND

8

CS/SHDN

PDIP, SOIC

CS/SHDN D_IN

CLK

D_OUT

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

1

16 V_DD

V_REF

15

14 AGND

13 CLK

* Note: Channels 5-7 available on MCP3208 Only

2

3

4

5

12 D_OUT

D_IN

6

7

8

11

10

9

CS/SHDN

DGND

DS21298D-page 1

MCP3204/3208

1.0

ELECTRICAL

PIN FUNCTION TABLE

CHARACTERISTICS

Name

Function

Absolute Maximum Ratings*

V_DD

+2.7V to 5.5V Power Supply

Digital Ground

DGND

AGND

CH0-CH7

CLK

V

...................................................................................7.0V

DD

Analog Ground

All inputs and outputs w.r.t. V ............... -0.6V to V +0.6V

SS

DD

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................-65°C to +125°C

Soldering temperature of leads (10 seconds) .............+300°C

ESD protection on all pins.............................................> 4 kV

Analog Inputs

Serial Clock

D_IN

Serial Data In

D_OUT

Serial Data Out

*Notice: Stresses above those listed under "Maximum

Ratings" may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect

device reliability.

CS/SHDN

V_REF

Chip Select/Shutdown Input

Reference Voltage Input

ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise noted, all parameters apply at V_DD= 5V, V_SS= 0V, V_REF= 5V,

_AMB= -40°C to +85°C,f_SAMPLE= 100 ksps and f_CLK= 20*f_SAMPLE

T

Parameters

Sym

Min

Typ

Max

Units

Conditions

Conversion Rate

Conversion Time

t_CONV

—

12

clock

cycles

Analog Input Sample Time

Throughput Rate

t_SAMPLE

f_SAMPLE

1.5

clock

cycles

—

100

50

ksps V_DD= V_REF= 5V

ksps V_DD= V_REF= 2.7V

DC Accuracy

Resolution

12

bits

Integral Nonlinearity

INL

—

±0.75

±1.0

±1

±2

LSB MCP3204/3208-B

MCP3204/3208-C

Differential Nonlinearity

DNL

—

±0.5

±1

LSB No missing codes

over-temperature

Offset Error

—

±1.25

±3

±5

LSB

Gain Error

Dynamic Performance

Total Harmonic Distortion

—

-82

72

—

dB V_IN= 0.1V to 4.9V@1 kHz

Signal to Noise and Distortion

(SINAD)

Spurious Free Dynamic

Range

—

86

—

dB V_IN= 0.1V to 4.9V@1 kHz

Reference Input

Voltage Range

Current Drain

0.25

—

V_DD

V

Note 2

—

100

0.001

150

3.0

µA

µA CS = V_DD= 5V

Note 1: This parameter is established by characterization and not 100% tested.

2: See graphs that relate linearity performance to V_REFlevels.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity

performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,

for more information.

DS21298D-page 2

MCP3204/3208

ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at V_DD= 5V, V_SS= 0V, V_REF= 5V,

T_AMB= -40°C to +85°C,f_SAMPLE= 100 ksps and f_CLK= 20*f_SAMPLE

Parameters

Sym

Min

Typ

Max

Units

Conditions

Analog Inputs

Input Voltage Range for CH0-

CH7 in Single-Ended Mode

V_SS

—

V_REF

V

Input Voltage Range for IN+ in

pseudo-differential Mode

Input Voltage Range for IN- in

pseudo-differential Mode

IN-

—

V

_REF+IN-

V

_SS-100

V_SS+100

mV

Leakage Current

—

0.001

1000

20

±1

—

µA

Ω

Switch Resistance

See Figure 4-1

Sample Capacitor

pF

See Figure 4-1

Digital Input/Output

Data Coding Format

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Output Leakage Current

Straight Binary

V_IH

V_IL

0.7 V_DD

—

0.3 V_DD

—

V

V_OH

V_OL

4.1

I_OH= -1 mA, V_DD= 4.5V

I_OL= 1 mA, V_DD= 4.5V

—

0.4

I_LI

-10

—

10

µA V_IN= V_SSor V_DD

µA V_OUT= V_SSor V_DD

I_LO

10

Pin Capacitance

(All Inputs/Outputs)

C_IN,C_OUT

10

pF

V_DD= 5.0V (Note 1)

T_AMB= 25°C, f = 1 MHz

Timing Parameters

Clock Frequency

f_CLK

—

2.0

1.0

MHz V_DD= 5V (Note 3)

MHz

V_DD= 2.7V (Note 3)

Clock High Time

Clock Low Time

t_HI

t_LO

250

100

—

ns

CS Fall To First Rising CLK

Edge

t_SUCS

ns

Data Input Setup Time

Data Input Hold Time

CLK Fall To Output Data Valid

CLK Fall To Output Enable

CS Rise To Output Disable

CS Disable Time

t_SU

t_HD

t_DO

t_EN

t_DIS

t_CSH

t_R

—

50

ns

—

200

100

—

See Figures 1-2 and 1-3

—

500

—

D_OUTRise Time

100

See Figures 1-2 and 1-3 (Note 1)

D_OUTFall Time

t_F

—

Power Requirements

Operating Voltage

V_DD

I_DD

2.7

—

5.5

V

Operating Current

—

320

225

400

—

µA V_DD=V_REF= 5V, D_OUTunloaded

V_DD=V_REF= 2.7V, D_OUTunloaded

Standby Current

I_DDS

—

0.5

2.0

µA CS = V_DD= 5.0V

Note 1: This parameter is established by characterization and not 100% tested.

2: See graphs that relate linearity performance to V_REFlevels.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity

performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,

for more information.

DS21298D-page 3

MCP3204/3208

ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at V_DD= 5V, V_SS= 0V, V_REF= 5V,

T_AMB= -40°C to +85°C,f_SAMPLE= 100 ksps and f_CLK= 20*f_SAMPLE

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

T_A

-40

—

+85

°C

Operating Temperature

Range

Storage Temperature Range

T_A

-65

—

+150

°C

Thermal Package Resistance

Thermal Resistance,

14L-PDIP

θ_JA

—

70

108

100

70

—

°C/W

Thermal Resistance,

14L-SOIC

Thermal Resistance,

14L-TSSOP

Thermal Resistance,

16L-PDIP

Thermal Resistance,

16L-SOIC

90

Note 1: This parameter is established by characterization and not 100% tested.

2: See graphs that relate linearity performance to V_REFlevels.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity

performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,

for more information.

t

CSH

CS

t

SUCS

t

LO

HI

CLK

t

HD

SU

D

IN

MSB IN

t

DIS

t

R

F

DO

t

EN

D

OUT

Null Bit

MSB OUT

LSB

FIGURE 1-1:

Serial Interface Timing.

DS21298D-page 4

MCP3204/3208

Test Point

1.4V

V

DD

t

_DISWaveform 2

Waveform

3 kΩ

Test Point

V

/2

3 kΩ

DD

t

D

EN

OUT

100 pF

_DISWaveform 1

C = 100 pF

L

V

SS

Voltage Waveforms for t , t

R

F

Voltage Waveforms for t

EN

V

OH

V

OL

D

OUT

CS

t

F

R

1

2

3

4

CLK

Voltage Waveforms for t

DO

B11

D

OUT

CLK

t

EN

t

DO

Voltage Waveforms for t

DIS

D

OUT

V

IH

CS

D

FIGURE 1-2:

Load Circuit for t_R, t_F, t_DO.

OUT

90%

10%

Waveform 1*

T

DIS

D

OUT

Waveform 2†

* Waveform 1 is for an output with internal

conditions such that the output is high,

unless disabled by the output control.

† Waveform 2 is for an output with internal

conditions such that the output is low,

unless disabled by the output control.

FIGURE 1-3:

Load circuit for t_DISand t_EN.

DS21298D-page 5

MCP3204/3208

2.0

TYPICAL PERFORMANCE CHARACTERISTICS

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 20* f_SAMPLE,T_A= 25°C.

1.0

2.0

V_DD= V_REF= 2.7 V

0.8

0.6

Positive INL

1.5

1.0

0.4

Positive INL

0.5

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.5

-1.0

-1.5

-2.0

Negative INL

0

10

20

30

40

50

60

70

80

0

25

50

75

100

125

150

Sample Rate (ksps)

FIGURE 2-1:

Integral Nonlinearity (INL)

FIGURE 2-4:

Integral Nonlinearity (INL)

vs. Sample Rate.

vs. Sample Rate (V_DD= 2.7V).

2.5

2.0

1.5

1.0

2.0

1.5

Positive INL

1.0

Positive INL

0.5

0.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-0.5

Negative INL

-1.0

Negative INL

-1.5

-2.0

0

1

2

3

4

5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

VREF (V)

FIGURE 2-2:

vs. V_REF

Integral Nonlinearity (INL)

FIGURE 2-5:

vs. V_REF(V_DD= 2.7V).

Integral Nonlinearity (INL)

.

1.0

0.8

V_DD= V_REF= 2.7 V

0.8

F_SAMPLE= 50 ksps

0.6

0.4

0.2

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

512

1024 1536 2048 2560 3072 3584 4096

Digital Code

0

512

1024 1536 2048 2560 3072 3584 4096

Digital Code

FIGURE 2-3:

Integral Nonlinearity (INL)

FIGURE 2-6:

Integral Nonlinearity (INL)

vs. Code (Representative Part).

vs. Code (Representative Part, V_DD= 2.7V).

DS21298D-page 6

MCP3204/3208

Note: Unless otherwise indicated, V_DD= V_REF= 5 V, V_SS= 0 V, f_SAMPLE= 100 ksps, f_CLK= 20* f_SAMPLE,T_A= 25°C.

1.0

0.8

1.0

0.8

V_DD= V_REF= 2.7 V

F_SAMPLE= 50 ksps

Positive INL

0.6

Positive INL

0.4

0.2

0.0

Negative INL

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

Negative INL

25

-50

-25

0

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-7:

Integral Nonlinearity (INL)

FIGURE 2-10:

Integral Nonlinearity (INL)

vs. Temperature.

vs. Temperature (V_DD= 2.7V).

2.0

1.0

0.8

V_DD= V_REF= 2.7 V

1.5

0.6

1.0

0.5

0.4

0.2

Positive DNL

Negative DNL

0.0

-0.5

-1.0

-1.5

-2.0

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

Negative DNL

0

25

50

75

100

125

150

0

10

20

30

40

50

60

70

80

Sample Rate (ksps)

FIGURE 2-8:

Differential Nonlinearity

FIGURE 2-11:

Differential Nonlinearity

(DNL) vs. Sample Rate.

(DNL) vs. Sample Rate (V_DD= 2.7V).

3.0

2.0

3.0

V_DD= V_REF= 2.7 V

F

_SAMPLE= 50 ksps

2.0

1.0

Positive DNL

1.0

Positive DNL

0.0

Negative DNL

-1.0

-2.0

-3.0

-1.0

-2.0

-3.0

0

1

2

3

4

5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

VREF (V)

FIGURE 2-9:

(DNL) vs. V_REF

Differential Nonlinearity

FIGURE 2-12:

(DNL) vs. V_REF(V_DD= 2.7V)_.

Differential Nonlinearity

.

DS21298D-page 7

MCP3204/3208

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 20* f_SAMPLE,T_A= 25°C.

1.0

0.8

1.0

0.8

V_DD= V_REF= 2.7 V

_SAMPLE= 50 ksps

F

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

512

1024 1536 2048 2560 3072 3584 4096

Digital Code

0

512

1024 1536 2048 2560 3072 3584 4096

Digital Code

FIGURE 2-13:

Differential Nonlinearity

FIGURE 2-16:

Differential Nonlinearity

(DNL) vs. Code (Representative Part).

(DNL) vs. Code (Representative Part, V_DD

2.7V).

=

1.0

0.8

0.6

1.0

V_DD= V_REF= 2.7 V

0.8

F_SAMPLE= 50 ksps

0.6

0.4

Positive DNL

0.2

0.0

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.4

Negative DNL

-0.6

-0.8

-1.0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-14:

Differential Nonlinearity

FIGURE 2-17:

Differential Nonlinearity

(DNL) vs. Temperature.

(DNL) vs. Temperature (V_DD= 2.7V).

4

3

20

18

16

V_DD= V_REF= 2.7 V

_SAMPLE= 50 ksps

F

2

1

V_DD= V_REF= 5V

14

F_SAMPLE= 100 ksps

12

10

8

0

-1

-2

-3

-4

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

6

V_DD= V_REF= 5 V

_SAMPLE= 100 ksps

4

F

2

0

1

2

3

4

5

0

1

2

3

4

5

V_REF(V)

FIGURE 2-15:

Gain Error vs. V_REF.

FIGURE 2-18:

Offset Error vs. V_REF.

DS21298D-page 8

MCP3204/3208

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 20* f_SAMPLE,T_A= 25°C.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.2

0.0

V_DD= V_REF= 2.7 V

F_SAMPLE= 50 ksps

V_DD= V_REF= 5 V

F_SAMPLE= 100 ksps

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

-1.8

V_DD= V_REF= 2.7 V

F_SAMPLE= 50 ksps

V_DD= V_REF= 5 V

F

_SAMPLE= 100 ksps

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-19:

Gain Error vs. Temperature.

FIGURE 2-22:

Offset Error vs.

Temperature.

100

90

80

70

60

50

40

30

20

10

100

90

V_DD= V_REF= 5 V

_SAMPLE= 100 ksps

V_DD= V_REF= 5 V

F

_SAMPLE= 100 ksps

80

70

60

V_DD= V_REF= 2.7 V

_SAMPLE= 50 ksps

50

40

30

20

10

0

F

V_DD= V_REF= 2.7V

F

_SAMPLE= 50 ksps

0

1

10

100

1

10

100

Input Frequency (kHz)

FIGURE 2-20:

Signal to Noise (SNR) vs.

FIGURE 2-23:

Signal to Noise and

Input Frequency.

Distortion (SINAD) vs. Input Frequency.

0

-10

-20

-30

-40

80

V_DD= V_REF= 5 V

F_SAMPLE= 100 ksps

70

60

50

V_DD= V_REF= 2.7V

_SAMPLE= 50 ksps

F

V_DD= V_REF= 2.7 V

_SAMPLE= 50 ksps

-50

-60

F

40

30

20

10

0

-70

-80

V_DD= V_REF= 5V

F_SAMPLE= 100 ksps

-90

-100

1

10

100

-40

-35

-30

-25

-20

-15

-10

-5

0

Input Frequency (kHz)

Input Signal Level (dB)

FIGURE 2-21:

Total Harmonic Distortion

FIGURE 2-24:

Signal to Noise and

(THD) vs. Input Frequency.

Distortion (SINAD) vs. Input Signal Level.

DS21298D-page 9

MCP3204/3208

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 20* f_SAMPLE,T_A= 25°C.

12.0

12.00

11.75

11.50

11.25

11.00

10.75

10.50

10.25

10.00

9.75

11.5

11.0

10.5

10.0

9.5

V_DD= V_REF= 5 V

F_SAMPLE=100 ksps

V_DD= V_REF= 5 V

_SAMPLE= 100 ksps

V_DD= V_REF= 2.7 V

_SAMPLE= 50 ksps

F

V_DD= V_REF= 2.7 V

F_SAMPLE= 50 ksps

9.0

9.50

8.5

9.25

9.00

8.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

V_REF(V)

1

10

100

Input Frequency (kHz)

FIGURE 2-25:

Effective Number of Bits

FIGURE 2-28:

Effective Number of Bits

(ENOB) vs. V_REF

.

(ENOB) vs. Input Frequency.

0

-10

-20

-30

-40

-50

-60

-70

-80

100

90

V_DD= V_REF= 5 V

F_SAMPLE= 100 ksps

80

70

60

V_DD= V_REF= 2.7 V

_SAMPLE= 50 ksps

50

40

30

20

10

0

F

1

10

100

1000

10000

1

10

100

Input Frequency (kHz)

Ripple Frequency (kHz)

FIGURE 2-26:

Spurious Free Dynamic

FIGURE 2-29:

Power Supply Rejection

Range (SFDR) vs. Input Frequency.

(PSR) vs. Ripple Frequency.

0

-10

0

V_DD= V_REF= 5 V

V_DD= V_REF= 2.7 V

F_SAMPLE= 50 ksps

-10

-20

F

_SAMPLE= 100 ksps

_INPUT= 9.985 kHz

-20

F

_INPUT= 998.76 Hz

-30

4096 points

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-100

-110

-120

-130

0

5000

10000

15000

20000

25000

0

10000

20000

30000

40000

50000

Frequency (Hz)

FIGURE 2-27:

Frequency Spectrum of

FIGURE 2-30:

Frequency Spectrum of

10 kHz input (Representative Part).

1 kHz input (Representative Part, V_DD= 2.7V).

DS21298D-page 10

MCP3204/3208

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 20* f_SAMPLE,T_A= 25°C.

500

450

400

350

300

250

200

150

100

50

100

90

80

70

60

50

40

30

20

10

0

V_REF= V_DD

All points at F_CLK= 2 MHz except

at V_REF= V_DD= 2.5 V, F_CLK= 1 MHz

V_REF= V_DD

All points at F_CLK= 2 MHz, except

at V_REF= V_DD= 2.5 V, F_CLK= 1 MHz

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

V_DD(V)

FIGURE 2-31:

I_DDvs. V_DD

.

FIGURE 2-34:

I_REFvs. V_DD.

100

90

80

70

60

50

40

30

20

10

400

350

300

250

200

150

100

50

V_DD= V_REF= 5 V

V_DD= V_REF= 2.7 V

0

10

100

1000

10000

10

100

1000

10000

Clock Frequency (kHz)

FIGURE 2-32:

I_DDvs. Clock Frequency.

FIGURE 2-35:

I_REFvs. Clock Frequency.

400

100

90

80

70

60

50

40

30

20

10

0

V_DD= V_REF= 5 V

F_CLK= 2 MHz

V_DD= V_REF= 5 V

F_CLK= 2 MHz

350

300

250

200

150

100

50

V_DD= V_REF= 2.7 V

_CLK= 1 MHz

F

V_DD= V_REF= 2.7 V

_CLK= 1 MHz

F

0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-33:

I_DDvs. Temperature.

FIGURE 2-36:

I_REFvs. Temperature.

DS21298D-page 11

MCP3204/3208

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 20* f_SAMPLE,T_A= 25°C.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

80

70

60

50

40

30

20

10

0

V_REF= CS = V_DD

V_DD= V_REF= 5 V

_CLK= 2 MHz

F

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

-50

-25

0

25

50

75

100

V_DD(V)

Temperature (°C)

FIGURE 2-37:

I_DDSvs. V_DD

.

FIGURE 2-39:

Analog Input Leakage

Current vs. Temperature.

100.00

V_DD= V_REF= CS = 5 V

10.00

1.00

0.10

0.01

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-38:

I_DDSvs. Temperature.

DS21298D-page 12

MCP3204/3208

3.7

Chip Select/Shutdown (CS/SHDN)

3.0

PIN DESCRIPTIONS

The CS/SHDN pin is used to initiate communication

with the device when pulled low and will end a conver-

sion and put the device in low power standby when

pulled high. The CS/SHDN pin must be pulled high

between conversions.

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

Name

PIN FUNCTION TABLE

Function

V_DD

+2.7V to 5.5V Power Supply

Digital Ground

DGND

AGND

CH0-CH7

CLK

4.0

DEVICE OPERATION

Analog Ground

The MCP3204/3208 A/D converters employ a conven-

tional SAR architecture. With this architecture, a sam-

ple is acquired on an internal sample/hold capacitor for

1.5 clock cycles starting on the fourth rising edge of the

serial clock after the start bit has been received. Fol-

lowing this sample time, the device uses the collected

charge on the internal sample/hold capacitor to pro-

duce a serial 12-bit digital output code. Conversion

rates of 100 ksps are possible on the MCP3204/3208.

See Section 6.2, “Maintaining Minimum Clock Speed”,

for information on minimum clock rates. Communica-

tion with the device is accomplished using a 4-wire SPI-

compatible interface.

Analog Inputs

Serial Clock

D_IN

Serial Data In

D_OUT

Serial Data Out

CS/SHDN

V_REF

Chip Select/Shutdown Input

Reference Voltage Input

3.1

DGND

Digital ground connection to internal digital circuitry.

3.2

AGND

4.1

Analog Inputs

Analog ground connection to internal analog circuitry.

The MCP3204/3208 devices offer the choice of using

the analog input channels configured as single-ended

inputs or pseudo-differential pairs. The MCP3204 can

be configured to provide two pseudo-differential input

pairs or four single-ended inputs, while the MCP3208

can be configured to provide four pseudo-differential

input pairs or eight single-ended inputs. Configuration

is done as part of the serial command before each con-

version begins. When used in the pseudo-differential

mode, each channel pair (i.e., CH0 and CH1, CH2 and

CH3 etc.) is programmed to be the IN+ and IN- inputs

as part of the command string transmitted to the

device. The IN+ input can range from IN- to (V_REF+ IN-

). The IN- input is limited to ±100 mV from the V_SSrail.

The IN- input can be used to cancel small signal com-

mon-mode noise which is present on both the IN+ and

IN- inputs.

3.3

CH0 - CH7

Analog inputs for channels 0 - 7 for the multiplexed

inputs. Each pair of channels can be programmed to be

used as two independent channels in single-ended

mode or as a single pseudo-differential input, where

one channel is IN+ and one channel is IN. See

Section 4.1, “Analog Inputs”, and Section 5.0, “Serial

Communications”, for information on programming the

channel configuration.

3.4

Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and

clock out each bit of the conversion as it takes place.

See Section 6.2, “Maintaining Minimum Clock Speed”,

for constraints on clock speed.

When operating in the pseudo-differential mode, if the

voltage level of IN+ is equal to or less than IN-, the

resultant code will be 000h. If the voltage at IN+ is

equal to or greater than {[V_REF+ (IN-)] - 1 LSB}, then

the output code will be FFFh. If the voltage level at IN-

is more than 1 LSB below V_SS, the voltage level at the

IN+ input will have to go below V_SSto see the 000h

output code. Conversely, if IN- is more than 1 LSB

above V_SS, then the FFFh code will not be seen unless

the IN+ input level goes above V_REFlevel.

3.5

Serial Data Input (D_IN)

The SPI port serial data input pin is used to load

channel configuration data into the device.

3.6

Serial Data Output (D_OUT)

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place.

For the A/D converter to meet specification, the charge

holding capacitor (C_SAMPLE) must be given enough

time to acquire a 12-bit accurate voltage level during

the 1.5 clock cycle sampling period. The analog input

model is shown in Figure 4-1.

DS21298D-page 13

MCP3204/3208

This diagram illustrates that the source impedance (R_S)

adds to the internal sampling switch (R_SS) impedance,

directly effecting the time that is required to charge the

capacitor (Csample). Consequently, larger source

impedances increase the offset, gain and integral

linearity errors of the conversion (see Figure 4-2).

EQUATION

Digital Output Code =

4096 × V_IN

--------------------------

V_REF

V_IN= analog input voltage

_REF= reference voltage

V

4.2

Reference Input

When using an external voltage reference device, the

system designer should always refer to the manufac-

turer’s recommendations for circuit layout. Any instabil-

ity in the operation of the reference device will have a

direct effect on the operation of the A/D converter.

For each device in the family, the reference input

(V_REF) determines the analog input voltage range. As

the reference input is reduced, the LSB size is reduced

accordingly. The theoretical digital output code pro-

duced by the A/D converter is a function of the analog

input signal and the reference input, as shown below.

V_DD

Sampling

Switch

V_T= 0.6V

R_S= 1 kΩ

CHx

R_SS

SS

C_SAMPLE

= DAC capacitance

= 20 pF

C_PIN

7 pF

I_LEAKAGE

VA

V_T= 0.6V

±1 nA

V_SS

Legend

VA

Signal Source

Leakage Current At The Pin

Due To Various Junctions

=

I

=

leakage

SS

Source Impedance

Input Channel Pad

Input Pin Capacitance

Threshold Voltage

Sampling switch

R

=

ss

CHx

Sampling switch resistor

Sample/hold capacitance

R

s

C

sample

V

t

FIGURE 4-1:

Analog Input Model.

2.5

2.0

1.5

1.0

0.5

V_DD= 5 V

V_DD= 2.7 V

0.0

100

1000

10000

Input Resistance (Ohms)

FIGURE 4-2:

Maximum Clock Frequency

vs. Input resistance (R_S) to maintain less than a

0.1 LSB deviation in INL from nominal

conditions.

DS21298D-page 14

MCP3204/3208

TABLE 5-1:

CONFIGURATION BITS FOR

THE MCP3204

5.0

SERIAL COMMUNICATIONS

Communication with the MCP3204/3208 devices is

accomplished using a standard SPI-compatible serial

interface. Initiating communication with either device is

done by bringing the CS line low (see Figure 5-1). If the

device was powered up with the CS pin low, it must be

brought high and back low to initiate communication.

The first clock received with CS low and D_INhigh will

constitute a start bit. The SGL/DIFF bit follows the start

bit and will determine if the conversion will be done

using single-ended or differential input mode. The next

three bits (D0, D1 and D2) are used to select the input

channel configuration. Table 5-1 and Table 5-2 show

the configuration bits for the MCP3204 and MCP3208,

respectively. The device will begin to sample the ana-

log input on the fourth rising edge of the clock after the

start bit has been received. The sample period will end

on the falling edge of the fifth clock following the start

bit.

Control Bit

Selections

Input

Channel

Configuration Selection

Single/

D2* D1 D0

Diff

1

0

X

0

1

0

1

0

1

0

single-ended

differential

CH0

CH1

CH2

CH3

CH0 = IN+

CH1 = IN-

0

X

0

1

0

1

differential

CH0 = IN-

CH1 = IN+

CH2 = IN+

CH3 = IN-

CH2 = IN-

CH3 = IN+

Once the D0 bit is input, one more clock is required to

complete the sample and hold period (D_INis a “don’t

care” for this clock). On the falling edge of the next

clock, the device will output a low null bit. The next 12

clocks will output the result of the conversion with MSB

first, as shown in Figure 5-1. Data is always output from

the device on the falling edge of the clock. If all 12 data

bits have been transmitted and the device continues to

receive clocks while the CS is held low, the device will

output the conversion result LSB first, as shown in

Figure 5-2. If more clocks are provided to the device

while CS is still low (after the LSB first data has been

transmitted), the device will clock out zeros indefinitely.

* D2 is a “don’t care” for MCP3204

TABLE 5-2:

CONFIGURATION BITS FOR

THE MCP3208

Control Bit

Selections

Input

Channel

Configuration Selection

Single

D2 D1 D0

/Diff

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

single-ended

differential

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

If necessary, it is possible to bring CS low and clock in

leading zeros on the D_INline before the start bit. This is

often done when dealing with microcontroller-based

SPI ports that must send 8 bits at a time. Refer to

Section 6.1 for more details on using the MCP3204/

3208 devices with hardware SPI ports.

CH0 = IN+

CH1 = IN-

0

1

0

1

0

1

0

1

0

1

0

1

differential

CH0 = IN-

CH1 = IN+

CH2 = IN+

CH3 = IN-

CH2 = IN-

CH3 = IN+

CH4 = IN+

CH5 = IN-

CH4 = IN-

CH5 = IN+

CH6 = IN+

CH7 = IN-

CH6 = IN-

CH7 = IN+

DS21298D-page 15

MCP3204/3208

t

CYC

t

CSH

CS

t

SUCS

CLK

SGL/

DIFF

SGL/

DIFF

D

Don’t Care

Start

D2 D1 D0

D2

IN

HI-Z

Null

Bit

D

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*

OUT

t

CONV

t

**

SAMPLE

DATA

* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB

first data, followed by zeros indefinitely (see Figure 5-2 below).

** t_DATA: during this time, the bias current and the comparator power down while the reference input becomes

a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.

FIGURE 5-1:

Communication with the MCP3204 or MCP3208.

t

CYC

t

CSH

CS

t

SUCS

Power Down

CLK

Start

D

Don’t Care

D2 D1 D0

IN

SGL/

DIFF

HI-Z

*

Null

Bit

HI-Z

B11

B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11

B10 B9

D

OUT

(MSB)

t

**

t

DATA

CONV

t

SAMPLE

* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros

indefinitely.

** t_DATA: During this time, the bias circuit and the comparator power down while the reference input becomes a

high impedance node, leaving the CLK running to clock out LSB first data or zeroes.

FIGURE 5-2:

Communication with MCP3204 or MCP3208 in LSB First Format.

DS21298D-page 16

MCP3204/3208

6.0

6.1

APPLICATIONS INFORMATION

Using the MCP3204/3208 with

Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required to

send groups of eight bits. It is also required that the

microcontroller SPI port be configured to clock out data

on the falling edge of clock and latch data in on the ris-

ing edge. Because communication with the MCP3204/

3208 devices may not need multiples of eight clocks, it

will be necessary to provide more clocks than are

required. This is usually done by sending ‘leading

zeros’ before the start bit. As an example, Figure 6-1

and Figure 6-2 illustrate how the MCP3204/3208 can

be interfaced to a MCU with a hardware SPI port.

Figure 6-1 depicts the operation shown in SPI Mode

0,0, which requires that the SCLK from the MCU idles

in the ‘low’ state, while Figure 6-2 shows the similar

case of SPI Mode 1,1, where the clock idles in the ‘high’

state.

As is shown in Figure 6-1, the first byte transmitted to

the A/D converter contains five leading zeros before

the start bit. Arranging the leading zeros this way

allows the output 12 bits to fall in positions easily

manipulated by the MCU. The MSB is clocked out of

the A/D converter on the falling edge of clock number

12. Once the second eight clocks have been sent to the

device, the MCU’s receive buffer will contain three

unknown bits (the output is at high impedance for the

first two clocks), the null bit and the highest order four

bits of the conversion. Once the third byte has been

sent to the device, the receive register will contain the

lowest order eight bits of the conversion results.

Employing this method ensures simpler manipulation

of the converted data.

Figure 6-2 shows the same thing in SPI Mode 1,1,

which requires that the clock idles in the high state. As

with mode 0,0, the A/D converter outputs data on the

falling edge of the clock and the MCU latches data from

the A/D converter in on the rising edge of the clock.

DS21298D-page 17

MCP3204/3208

CS

MCU latches data from A/D

converter on rising edges of SCLK

SCLK

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

17 18 19 20 21 22 23 24

Data is clocked out of A/D

converter on falling edges

SGL/

D2

DO

D1

DDonon’t’tCCaarree

D_IN

DIFF

Start

NULL

BIT

HI-Z

B7

B6 B5 B4 B3 B2 B1 B0

B11 B10 B9 B8

D_OUT

Start

Bit

MCU Transmitted Data

(Aligned with falling

edge of clock)

SSGGLL//

0

D2

1

D11 DOO

?

X X

X

XX

X X X

D2

X

X X

XX

X

DDIIFFFF

MCU Received Data

(Aligned with rising

edge of clock)

0

?

(Null)

B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

?

Data stored into MCU receive

register after transmission of first

8 bits

Data stored into MCU receive

register after transmission of

second 8 bits

Data stored into MCU receive

register after transmission of last

8 bits

X = “Don’t Care” Bits

FIGURE 6-1:

SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

CS

MCU latches data from A/D converter

on rising edges of SCLK

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

16

17 18 19 20 21 22 23 24

SCLK

D_IN

Data is clocked out of A/D

converter on falling edges

SGL/

DIFF

Don’t Care

D2

D1 DO

Start

HI-Z

NULL

BIT

B11 B10 B9

B8

B7 B6 B5 B4 B3 B2 B1 B0

D

OUT

Start

Bit

MCU Transmitted Data

(Aligned with falling

edge of clock)

SGL/

DIFF

0

1

D2

D1 DO

X

0

X

MCU Received Data

(Aligned with rising

edge of clock)

?

B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

(Null)

Data stored into MCU receive

register after transmission of first

8 bits

Data stored into MCU receive

register after transmission of

second 8 bits

Data stored into MCU receive

register after transmission of last

8 bits

X = “Don’t Care” Bits

FIGURE 6-2:

SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

DS21298D-page 18

MCP3204/3208

6.2

Maintaining Minimum Clock

Speed

6.3

Buffering/Filtering the Analog

Inputs

When the MCP3204/3208 initiates the sample period,

charge is stored on the sample capacitor. When the

sample period is complete, the device converts one bit

for each clock that is received. It is important for the

user to note that a slow clock rate will allow charge to

bleed off the sample capacitor while the conversion is

taking place. At 85°C (worst case condition), the part

will maintain proper charge on the sample capacitor for

at least 1.2 ms after the sample period has ended. This

means that the time between the end of the sample

period and the time that all 12 data bits have been

clocked out must not exceed 1.2 ms (effective clock

frequency of 10 kHz). Failure to meet this criterion may

introduce linearity errors into the conversion outside

the rated specifications. It should be noted that during

the entire conversion cycle, the A/D converter does not

require a constant clock speed or duty cycle, as long as

all timing specifications are met.

If the signal source for the A/D converter is not a low

impedance source, it will have to be buffered or inaccu-

rate conversion results may occur (see Figure 4-2). It is

also recommended that a filter be used to eliminate any

signals that may be aliased back into the conversion

results, as is illustrated in Figure 6-3, where an op amp

is used to drive the analog input of the MCP3204/3208.

This amplifier provides a low impedance source for the

converter input, and a low pass filter, which eliminates

unwanted high frequency noise.

Low pass (anti-aliasing) filters can be designed using

Microchip’s free interactive FilterLab™ software. Filter-

Lab will calculate capacitor and resistor values, as well

as determine the number of poles that are required for

the application. For more information on filtering sig-

nals, see AN699, “Anti-Aliasing Analog Filters for Data

Acquisition Systems”.

V_DD

10 µF

4.096V

Reference

0.1 µF

1 µF

MCP1541

1 µF

IN+

IN-

V_REF

MCP3204

C₁

R₂

MCP601

R₁

V_IN

+

-

C₂

R₄

R₃

FIGURE 6-3:

The MCP601 Operational Amplifier is used to implement a second order anti-aliasing

filter for the signal being converted by the MCP3204.

DS21298D-page 19

MCP3204/3208

6.4

Layout Considerations

6.5

Utilizing the Digital and Analog

Ground Pins

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

noise wherever possible. A bypass capacitor should

always be used with this device, placed as close as

possible to the device pin. A bypass capacitor value of

1 µF is recommended.

The MCP3204/3208 devices provide both digital and

analog ground connections to provide another means

of noise reduction. As shown in Figure 6-5, the analog

and digital circuitry is separated internal to the device.

This reduces noise from the digital portion of the device

being coupled into the analog portion of the device. The

two grounds are connected internally through the sub-

strate, which has a resistance of 5 -10Ω.

Digital and analog traces should be separated as much

as possible on the board, with no traces running under-

neath the device or the bypass capacitor. Extra precau-

tions should be taken to keep traces with high

frequency signals (such as clock lines) as far as

possible from analog traces.

If no ground plane is utilized, then both grounds must

be connected to V_SSon the board. If a ground plane is

available, both digital and analog ground pins should

be connected to the analog ground plane. If both an

analog and a digital ground plane are available, both

the digital and the analog ground pins should be con-

nected to the analog ground plane. Following these

steps will reduce the amount of digital noise from the

rest of the board being coupled into the A/D converter.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing V_DDconnections to

devices in a “star” configuration can also reduce noise

by eliminating return current paths and associated

errors (see Figure 6-4). For more information on layout

tips when using A/D converters, refer to AN688,

“Layout Tips for 12-Bit A/D converter Applications”.

V_DD

MCP3204/08

Connection

Digital Side

Analog Side

-SPI Interface

-Shift Register

-Control Logic

-Sample Cap

-Capacitor Array

-Comparator

Substrate

5 - 10Ω

Device 4

Device 1

DGND

AGND

0.1 µF

Device 3

Analog Ground Plane

Device 2

FIGURE 6-5:

Separation of Analog and

Digital Ground Pins.

FIGURE 6-4:

V_DDtraces arranged in a

‘Star’ configuration in order to reduce errors

caused by current return paths.

DS21298D-page 20

MCP3204/3208

7.0

7.1

PACKAGING INFORMATION

Package Marking Information

14-Lead PDIP (300 mil)

Example:

XXXXXXXXXXXXXX

MCP3204-B

e

3

I/P

YYWWNNN

0723NNN

14-Lead SOIC (150 mil)

Example:

e

3

MCP3204-B

XXXXXXXXXXX

YYWWNNN

0723NNN

14-Lead TSSOP (4.4mm) *

Example:

XXXXXXXX

YYWW

3204-C

e3

0723

NNN

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21298D-page 21

MCP3204/3208

Package Marking Information (Continued)

16-Lead PDIP (300 mil) (MCP3304)

Example:

XXXXXXXXXXXXXX

MCP3208-B _e

3

I/P

YYWWNNN

0723NNN

16-Lead SOIC (150 mil) (MCP3304)

Example:

e

3

MCP3208-B

XXXXXXXXXX

XXXXXXXXXXXXX

YYWWNNN

IYWWNNN

DS21298D-page 22

MCP3204/3208

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

c

A1

b1

b

e

eB

Units

INCHES

NOM

14

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.735

.115

.008

.045

.014

–

.130

–

.310

.250

.750

.130

.010

.060

.018

–

.325

.280

.775

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-005B

DS21298D-page 23

MCP3204/3208

14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

h

b

α

h

c

φ

A2

A

L

A1

β

L1

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

14

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff §

A2

A1

E

1.25

0.10

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

E1

D

h

3.90 BSC

8.65 BSC

Chamfer (optional)

Foot Length

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-065B

DS21298D-page 24

MCP3204/3208

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

e

b

c

φ

A2

A

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

14

0.65 BSC

Overall Height

Molded Package Thickness

Standoff

A

–

1.20

1.05

0.15

A2

A1

E

0.80

0.05

1.00

–

Overall Width

Molded Package Width

Molded Package Length

Foot Length

6.40 BSC

E1

D

4.30

4.90

0.45

4.40

4.50

5.10

0.75

5.00

L

0.60

Footprint

L1

φ

1.00 REF

Foot Angle

0°

–

8°

Lead Thickness

Lead Width

c

0.09

0.19

0.20

0.30

b

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-087B

DS21298D-page 25

MCP3204/3208

16-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

1

2

3

D

E

A

A2

L

c

A1

b1

e

eB

b

Units

INCHES

NOM

16

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.735

.115

.008

.045

.014

–

.130

–

.310

.250

.755

.130

.010

.060

.018

–

.325

.280

.775

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-017B

DS21298D-page 26

MCP3204/3208

16-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

3

1

2

e

b

h

α

h

c

φ

A2

A

L

β

A1

L1

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

16

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff §

A2

A1

E

1.25

0.10

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

E1

D

h

3.90 BSC

9.90 BSC

Chamfer (optional)

Foot Length

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-108B

DS21298D-page 27

MCP3204/3208

NOTES:

DS21298D-page 28

MCP3204/3208

APPENDIX A: REVISION HISTORY

Revision D (January 2007)

This revision includes updates to the packaging dia-

grams.

DS21298D-page 29

MCP3204/3208

NOTES:

DS21298D-page 30

MCP3204/3208

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

Examples:

a)

b)

c)

MCP3204-BI/P: ±1 LSB INL, Industrial Tem-

perature, PDIP package.

Grade Temperature Package

Range

MCP3204-BI/SL: ±1 LSB INL, Industrial

Temperature, SOIC package.

Device:

MCP3204: 4-Channel 12-Bit Serial A/D Converter

MCP3204T: 4-Channel 12-Bit Serial A/D Converter

(Tape and Reel)

MCP3204-CI/ST: ±2 LSB INL, Industrial

Temperature, TSSOP package.

MCP3208: 8-Channel 12-Bit Serial A/D Converter

MCP3208T: 8-Channel 12-Bit Serial A/D Converter

(Tape and Reel)

a)

b)

c)

MCP3208-BI/P: ±1 LSB INL, Industrial

Temperature, PDIP package.

MCP3208-BI/SL: ±1 LSB INL, Industrial

Temperature, SOIC package.

Grade:

B

C

=

±1 LSB INL

±2 LSB INL

MCP3208-CI/ST: ±2 LSB INL, Industrial

Temperature, TSSOP package.

Temperature Range:

Package:

I

=

-40°C to +85°C

P

SL

ST

=

Plastic DIP (300 mil Body), 14-lead, 16-lead

Plastic SOIC (150 mil Body), 14-lead, 16-lead

Plastic TSSOP (4.4mm), 14-lead

DS21298D-page31

MCP3204/3208

NOTES:

DS21298D-page 32

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS21298D-page 33

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS21298D-page 34


型号：	MCP3208-BI/SL
厂家：	MICROCHIP
描述：	2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI⑩ Serial Interface 2.7V 4通道/ 8通道12位与SPI⑩串行接口的A / D转换器转换器模数转换器光电二极管 PC
文件：	总34页 (文件大小：598K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP3208-BI/SL [MICROCHIP]

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MCP3208-CI/SL

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