MCP3302T-I/P [MICROCHIP]
13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface; 13位差分输入，低功耗A / D转换器，带有SPI串行接口
| 型号： | MCP3302T-I/P |
| 厂家： | 
MICROCHIP |
| 描述： | 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface |
| 文件： | 总40页 (文件大小：790K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP3302/04
M
13-Bit Differential Input, Low Power A/D Converter
with SPI™ Serial Interface
Features
General Description
• Full Differential Inputs
The Microchip Technology Inc. MCP3302/04 13-bit A/D
converters feature full differential inputs and low power
consumption in a small package that is ideal for battery
powered systems and remote data acquisition applica-
tions. The MCP3302 is programmable to provide two
differential input pairs or four single ended inputs. The
MCP3304 is programmable and provides four differen-
tial input pairs or eight single ended inputs.
• MCP3302: 2 Differential or 4 Single ended Inputs
• MCP3304: 4 Differential or 8 Single ended Inputs
• ±1 LSB max DNL
• ±1 LSB max INL (MCP3302/04-B)
• ±2 LSB max INL (MCP3302/04-C)
• Single supply operation: 2.7V to 5.5V
• 100 ksps sampling rate with 5V supply voltage
• 50 ksps sampling rate with 2.7V supply voltage
• 50 nA typical standby current, 1 µA max
• 450 µA max active current at 5V
Incorporating a successive approximation architecture
with on-board sample and hold circuitry, these 13-bit
A/D converters are specified to have ±1 LSB Differen-
tial Nonlinearity (DNL); ±1 LSB Integral Nonlinearity
(INL) for B-grade and ±2 LSB for C-grade devices. The
industry-standard SPI™ serial interface enables 13-bit
• Industrial temp range: -40°C to +85°C
• 14 and 16-pin PDIP, SOIC and TSSOP packages
®
A/D converter capability to be added to any PICmicro
microcontroller.
TM
• MXDEV Evaluation kit available
The MCP3302/04 devices feature low current design
that permits operation with typical standby and active
currents of only 50 nA and 300 µA, respectively. The
devices operate over a broad voltage range of 2.7V to
5.5V and are capable of conversion rates of up to
100 ksps. The reference voltage can be varied from
400 mV to 5V, yielding input-referred resolution
between 98 µV and 1.22 mV.
The MCP3302 is available in 14-pin PDIP, 150 mil
SOIC and TSSOP packages. The MCP3304 is avail-
able in 16-pin PDIP and 150 mil SOIC packages. The
full differential inputs of these devices enable a wide
variety of signals to be used in applications such as
remote data acquisition, portable instrumentation and
battery operated applications.
Applications
• Remote Sensors
• Battery Operated Systems
• Transducer Interface
Package Types
PDIP, SOIC, TSSOP
14
13
CH0
CH1
CH2
CH3
NC
VDD
VREF
12 AGND
1
2
3
4
5
CLK
DOUT
DIN
11
10
9
8
NC
6
7
DGND
CS/SHDN
PDIP, SOIC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
3
4
5
6
7
8
16 VDD
VREF
14 AGND
13
12 DOUT
15
CLK
DIN
11
10
9
CS/SHDN
DGND
2002 Microchip Technology Inc.
DS21697B-page 1
MCP3302/04
Functional Block Diagram
AGND DGND
VDD
VREF
CH0
CH1
Input
Channel
Mux
CH7*
CDAC
Comparator
-
Sample
& Hold
Circuits
13-Bit SAR
+
Shift
Control Logic
Register
CS/SHDN DIN
CLK
DOUT
* Channels 5-7 available on MCP3304 Only
DS21697B-page 2
2002 Microchip Technology Inc.
MCP3302/04
1.0
ELECTRICAL
PIN FUNCTION TABLE
CHARACTERISTICS
Name
Function
Maximum Ratings*
CH0-CH7
DGND
CS/SHDN
Analog Inputs
Digital Ground
Chip Select / Shutdown Input
Serial Data In
Serial Data Out
Serial Clock
Analog Ground
Reference Voltage Input
+2.7V to 5.5V Power Supply
V
........................................................................7.0V
DD
All inputs and outputs w.r.t. V .....-0.3V to V +0.3V
SS
DD
D
D
IN
Storage temperature .......................... -65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
Maximum Junction Temperature ....................... 150°C
ESD protection on all pins (HBM)......................... > 4 kV
*Notice: Stresses above those listed under “Maximum rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
OUT
CLK
AGND
V
V
REF
DD
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential
input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
TAMB = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Conversion Rate
Maximum Sampling Frequency
FSAMPLE
—
—
—
—
100
50
ksps Note 8
ksps VDD = VREF = 2.7V, VCM =1.35V
Conversion Time
Acquisition Time
TCONV
TACQ
13
CLK
periods
1.5
CLK
periods
DC Accuracy
Resolution
12 data bits + sign
bits
Integral Nonlinearity
INL
—
—
—
-3
-3
-3
±0.5
±1
±0.5
-0.75
-0.5
+3
±1
LSB
LSB
LSB
LSB
LSB
LSB
MCP3302/04-B
MCP3302/04-C
Monotonic over temperature
±2
±1
+2
+2
+6
Differential Nonlinearity
Positive Gain Error
Negative Gain Error
Offset Error
DNL
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to VREF level.
3:
VIN = 0.1V to 4.9V @ 1 kHz.
4: VDD =5VP-P ±500 mV @ 1 kHz, see test circuit Figure 3-3.
5: Maximum clock frequency specification must be met.
6:
VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz
7: TSSOP devices are only specified at 25°C and +85°C.
8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.
2002 Microchip Technology Inc.
DS21697B-page 3
MCP3302/04
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential
input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
TAMB = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Dynamic Performance
Total Harmonic Distortion
Signal to Noise and Distortion
Spurious Free Dynamic Range
Common Mode Rejection
Channel to Channel Crosstalk
Power Supply Rejection
Reference Input
THD
SINAD
SFDR
CMRR
CT
—
—
—
—
—
—
-91
78
92
79
> -110
74
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
Note 3
Note 3
Note 3
Note 6
Note 6
Note 4
PSR
Voltage Range
0.4
—
VDD
V
Note 2
Current Drain
—
—
100
0.001
150
3
µA
µA
CS = VDD = 5V
Analog Inputs
Full Scale Input Span
Absolute Input Voltage
Leakage Current
Switch Resistance
Sample Capacitor
CH0 - CH7
CH0 - CH7
-VREF
-0.3
—
—
—
—
—
0.001
1
VREF
VDD + 0.3
V
V
µA
kΩ
pF
±1
—
—
RS
CSAMPLE
See Figure 6-3
See Figure 6-3
25
Digital Input/Output
Data Coding Format
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current
Pin Capacitance
Binary Two’s Complement
VIH
VIL
VOH
VOL
ILI
0.7 VDD
—
—
—
—
—
—
—
—
—
0.3 VDD
—
V
V
V
4.1
IOH = -1 mA, VDD = 4.5V
IOL = 1 mA, VDD = 4.5V
VIN = VSS or VDD
VOUT = VSS or VDD
TAMB = 25°C, F = 1 MHz, Note 1
—
0.4
V
-10
-10
—
10
10
10
µA
µA
pF
ILO
CIN, COUT
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to VREF level.
3:
VIN = 0.1V to 4.9V @ 1 kHz.
4: VDD =5VP-P ±500 mV @ 1 kHz, see test circuit Figure 3-3.
5: Maximum clock frequency specification must be met.
6:
VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz
7: TSSOP devices are only specified at 25°C and +85°C.
8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.
DS21697B-page 4
2002 Microchip Technology Inc.
MCP3302/04
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential
input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
TAMB = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Timing Specifications:
Clock Frequency (Note 8)
FCLK
0.105
0.105
210
210
100
50
—
—
2.1
MHz VDD = 5V, FSAMPLE = 100 ksps
1.05
MHz
ns
VDD = 2.7V, FSAMPLE = 50 ksps
Clock High Time
Clock Low Time
CS Fall To First Rising CLK Edge
Data In Setup time
Data In Hold Time
THI
TLO
TSUCS
TSU
THD
TDO
—
—
—
—
—
—
—
—
—
—
50
Note 5
Note 5
ns
ns
ns
ns
—
—
CLK Fall To Output Data Valid
125
200
ns
ns
VDD = 5V, see Figure 3-1
V
DD = 2.7V, see Figure 3-1
CLK Fall To Output Enable
CS Rise To Output Disable
TEN
—
—
—
—
125
200
100
ns
ns
ns
VDD = 5V, see Figure 3-1
DD = 2.7V, see Figure 3-1
See test circuits, Figure 3-1
Note 1
V
TDIS
CS Disable Time
DOUT Rise Time
TCSH
TR
475
—
—
—
—
100
ns
ns
See test circuits, Figure 3-1
Note 1
DOUT Fall Time
TF
—
—
100
ns
See test circuits, Figure 3-1
Note 1
Power Requirements:
Operating Voltage
Operating Current
VDD
IDD
2.7
—
—
—
300
200
5.5
450
—
V
µA
VDD, VREF = 5V, DOUT unloaded
V
DD, VREF = 2.7V, DOUT unloaded
Standby Current
IDDS
—
0.05
1
µA
CS = VDD = 5.0V
Temperature Ranges:
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistance:
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
Thermal Resistance, 16L-PDIP
Thermal Resistance, 16L-SOIC
TA
TA
TA
-40
-40
-65
—
—
—
+85
+85
+150
°C
°C
°C
θJA
θJA
θJA
θJA
θJA
—
—
—
—
—
70
108
100
70
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
90
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to VREF level.
3:
VIN = 0.1V to 4.9V @ 1 kHz.
4: VDD =5VP-P ±500 mV @ 1 kHz, see test circuit Figure 3-3.
5: Maximum clock frequency specification must be met.
6:
VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz
7: TSSOP devices are only specified at 25°C and +85°C.
8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.
2002 Microchip Technology Inc.
DS21697B-page 5
MCP3302/04
.
TCSH
CS
TSUCS
TLO
THI
CLK
THD
TSU
MSB IN
DIN
TR
TF
TDO
Null Bit
TDIS
TEN
DOUT
LSB
Sign BIT
FIGURE 1-1:
Timing Parameters
DS21697B-page 6
2002 Microchip Technology Inc.
MCP3302/04
2.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, V = V
= 5V, Full differential input configuration, V = 0V,
SS
DD
REF
F
= 100 ksps, F
= 21*F
, T = 25°C.
SAMPLE
CLK
SAMPLE
A
.
.
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
VDD=VREF=2.7V
Positive INL
Positive INL
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Negative INL
Negative INL
0
10
20
30
40
50
60
70
0
50
100
150
200
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-1:
Integral Nonlinearity (INL)
FIGURE 2-4:
Integral Nonlinearity (INL)
DD
vs. Sample Rate
vs. Sample Rate (V = 2.7V)
.
2
1.5
1
2
VDD = 2.7V
1.5
1
0.5
0
Positive INL
Negative INL
Positive INL
Negative INL
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
1
2
3
4
5
0
0.5
1
1.5
VREF(V)
2
2.5
3
VREF(V)
FIGURE 2-2:
Integral Nonlinearity (INL)
FIGURE 2-5:
Integral Nonlinearity (INL)
vs. V
vs. V
(V = 2.7V)
REF.
REF
DD
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
VDD=VREF=2.7V
FSAMPLE = 50 ksps
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
-4096 -3072 -2048 -1024
0
1024
2048
3072
4096
-4096 -3072 -2048 -1024
0
1024
2048
3072
4096
Code
Code
FIGURE 2-3:
Integral Nonlinearity (INL)
FIGURE 2-6:
Integral Nonlinearity (INL)
vs. Code (Representative Part).
vs. Code (Representative Part, V = 2.7V).
DD
2002 Microchip Technology Inc.
DS21697B-page 7
MCP3302/04
Note: Unless otherwise indicated, V = V
= 5V, Full differential input configuration, V = 0V,
SS
DD
REF
F
= 100 ksps, F
= 21*F
, T = 25°C.
SAMPLE A
SAMPLE
CLK
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
VDD=VREF=2.7V
FSAMPLE = 50 ksps
Positive INL
Positive INL
Negative INL
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Negative INL
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature(°C)
Temperature (°C)
FIGURE 2-7:
Integral Nonlinearity (INL)
FIGURE 2-10:
Integral Nonlinearity (INL)
DD
vs. Temperature.
vs. Temperature (V = 2.7V).
1
0.8
0.6
0.4
0.2
0
1
VDD=VREF=2.7V
0.8
0.6
Positive DNL
Positive DNL
Negative DNL
0.4
0.2
0
-0.2
-0.2
-0.4
-0.6
-0.8
Negative DNL
-0.4
-0.6
-0.8
-1
0
10
20
30
40
50
60
70
-1
0
50
100
150
200
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-8:
Differential Nonlinearity
FIGURE 2-11:
Differential Nonlinearity
(DNL) vs. Sample Rate.
(DNL) vs. Sample Rate (V = 2.7V).
DD
2
1.5
1
2
VDD=2.7V
FSAMPLE = 50 ksps
1.5
1
Positive DNL
Positive DNL
0.5
0
0.5
0
Negative DNL
-0.5
-1
Negative DNL
-0.5
-1
-1.5
-2
-1.5
-2
0
1
2
3
4
5
6
0
0.5
1
1.5
2
2.5
3
VREF(V)
VREF (V)
FIGURE 2-9:
Differential Nonlinearity
FIGURE 2-12:
(DNL) vs. V
Differential Nonlinearity
(V = 2.7V).]
(DNL) vs. V
.
REF
REF
DD
DS21697B-page 8
2002 Microchip Technology Inc.
MCP3302/04
Note: Unless otherwise indicated, V = V
= 5V, Full differential input configuration, V = 0V,
SS
DD
REF
F
= 100 ksps, F
= 21*F
, T = 25°C.
SAMPLE A
SAMPLE
CLK
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
VDD=VREF=2.7V
FSAMPLE = 50 ksps
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
-4096 -3072 -2048 -1024
0
1024
2048
3072
4096
-4096 -3072 -2048 -1024
0
1024
2048
3072
4096
Code
Code
FIGURE 2-13:
Differential Nonlinearity
FIGURE 2-16:
Differential Nonlinearity
(DNL) vs. Code (Representative Part).
(DNL) vs. Code (Representative Part,
V
= 2.7V).
DD
1
0.8
0.6
1
VDD=VREF=2.7V
FSAMPLE = 50 ksps
0.8
0.6
0.4
0.2
0
Positive DNL
Negative DNL
Positive DNL
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Negaitive DNL
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
FIGURE 2-14:
Differential Nonlinearity
FIGURE 2-17:
Differential Nonlinearity
(DNL) vs. Temperature.
(DNL) vs. Temperature (V = 2.7V).
DD
4
3
2
20
18
16
14
12
VDD=5V
FSAMPLE = 100 ksps
VDD = 5V
FSAMPLE = 100 ksps
1
10
0
-1
-2
-3
8
6
4
VDD = 2.7V
SAMPLE = 50 ksps
2
0
F
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VREF(V)
VREF(V)
FIGURE 2-15:
REF
Positive Gain Error vs.
FIGURE 2-18:
Offset Error vs. V
.
REF
V
.
2002 Microchip Technology Inc.
DS21697B-page 9
MCP3302/04
Note: Unless otherwise indicated, V = V
= 5V, Full differential input configuration, V = 0V,
SS
DD
REF
F
= 100 ksps, F
= 21*F
, T = 25°C.
SAMPLE A
SAMPLE
CLK
0
-0.2
-0.4
-0.6
-0.8
-1
3.5
3
VDD=VREF=5V
SAMPLE = 100 ksps
F
VDD=VREF=5V
FSAMPLE = 100 ksps
2.5
2
VDD=VREF=2.7V
SAMPLE = 50 ksps
F
1.5
1
-1.2
-1.4
-1.6
-1.8
VDD=VREF=2.7V
FSAMPLE = 50 ksps
0.5
0
-50
0
50
100
150
-50
0
50
Temperature (°C)
100
150
Temperature (°C)
FIGURE 2-19:
Positive Gain Error vs.
FIGURE 2-22:
Offset Error vs.
Temperature.
Temperature.
90
80
70
100
90
80
70
60
50
40
30
20
10
VDD=VREF=5V
F
SAMPLE = 100 ksps
60
50
40
30
20
10
0
VDD=VREF=2.7V
FSAMPLE = 50 ksps
VDD=VREF=2.7V
SAMPLE = 50 ksps
F
VDD=VREF=5V
FSAMPLE = 100 ksps
0
1
1
10
100
10
100
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-20:
Signal to Noise Ratio (SNR)
FIGURE 2-23:
Signal to Noise and
vs. Input Frequency.
Distortion (SINAD) vs. Input Frequency.
0
-10
-20
-30
80
70
60
50
40
VDD=VREF=2.7V
-40
VDD=VREF=5V
SAMPLE = 100 ksps
F
SAMPLE = 50 ksps
F
-50
-60
VDD=VREF=2.7V
FSAMPLE = 50 ksps
VDD=VREF=5V
FSAMPLE = 100 ksps
30
20
10
0
-70
-80
-90
-100
-40
-35
-30
-25
-20
-15
-10
-5
0
1
10
Input Frequency (kHz)
100
Input Signal Level (dB)
FIGURE 2-21:
Total Harmonic Distortion
FIGURE 2-24:
Signal to Noise and
(THD) vs. Input Frequency.
Distortion (SINAD) vs. Input Signal Level.
DS21697B-page 10
2002 Microchip Technology Inc.
MCP3302/04
Note: Unless otherwise indicated, V = V
= 5V, Full differential input configuration, V = 0V,
SS
DD
REF
F
= 100 ksps, F
= 21*F
, T = 25°C.
SAMPLE A
SAMPLE
CLK
13
12
11
10
9
13
12.8
12.6
12.4
12.2
12
VDD=VREF=5V
FSAMPLE = 100 ksps
VDD=2.7V
FSAMPLE = 50 ksps
VDD=5V
FSAMPLE = 100 ksps
VDD=VREF=2.7V
FSAMPLE = 50 ksps
11.8
11.6
11.4
11.2
8
7
1
10
Input Frequency (kHz)
100
0
1
2
3
4
5
VREF(V)
FIGURE 2-25:
Effective Number of Bits
FIGURE 2-28:
Effective Number of Bits
(ENOB) vs. V
.
(ENOB) vs. Input Frequency.
REF
100
90
80
70
60
50
40
30
20
10
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
VDD=VREF=5V
0.1 µF Bypass
Capacitor
FSAMPLE = 100 ksps
VDD=VREF=2.7V
FSAMPLE = 50 ksps
0
1
10
Input Frequency (kHz)
100
1
10
100
1000
10000
Ripple Frequency (kHz)
FIGURE 2-26:
Spurious Free Dynamic
FIGURE 2-29:
Power Supply Rejection
Range (SFDR) vs. Input Frequency.
(PSR) vs. Ripple Frequency.
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-100
-110
-120
-130
-140
-150
0
10000
20000
30000
40000
50000
0
5000
10000
15000
20000
25000
Frequency (Hz)
Frequency (Hz)
FIGURE 2-27:
Frequency Spectrum of
FIGURE 2-30:
Frequency Spectrum of
10 kHz Input (Representative Part).
1 kHz Input (Representative Part, V = 2.7V).
DD
2002 Microchip Technology Inc.
DS21697B-page 11
MCP3302/04
Note: Unless otherwise indicated, V = V
= 5V, Full differential input configuration, V = 0V,
SS
DD
REF
F
= 100 ksps, F
= 21*F
, T = 25°C.
SAMPLE A
SAMPLE
CLK
450
400
350
300
250
200
150
100
50
120
100
80
60
40
20
0
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
FIGURE 2-31:
I
vs. V
.
FIGURE 2-34:
I
vs. V
.
DD
DD
DD
REF
600
500
400
300
200
100
120
100
80
VDD=VREF=5V
VDD=VREF=5V
60
40
VDD=VREF=2.7V
VDD=VREF=2.7V
20
0
0
0
0
50
100
150
200
50
100
150
200
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-32:
I
vs. Sample Rate.
FIGURE 2-35:
I
vs. Sample Rate.
DD
REF
400
350
300
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
VDD=VREF=5V
VDD=VREF=5V
FSAMPLE = 100 ksps
FSAMPLE = 100 ksps
VDD=VREF=2.7V
FSAMPLE = 50 ksps
VDD=VREF=2.7V
SAMPLE = 50 ksps
F
0
0
-50
0
50
100
150
-50
0
50
Temperature (°C)
100
150
Temperature (°C)
FIGURE 2-33:
I
vs. Temperature.
FIGURE 2-36:
I
vs. Temperature.
DD
REF
DS21697B-page 12
2002 Microchip Technology Inc.
MCP3302/04
Note: Unless otherwise indicated, V = V
= 5V, Full differential input configuration, V = 0V,
DD
REF
SS
F
= 100 ksps, F
= 21*F
, T = 25°C.
SAMPLE A
SAMPLE
CLK
80
70
60
50
40
30
20
10
0
2
1.5
1
VDD=VREF=2.7V
FSAMPLE = 50 ksps
VDD=VREF=5V
FSAMPLE = 100 ksps
0.5
0
-0.5
-1
-1.5
-2
2
2.5
3
3.5
4
4.5
5
5.5
6
-50
0
50
100
150
VDD (V)
Temperature (°C)
FIGURE 2-37:
I
vs. V
.
DD
FIGURE 2-40:
Negative Gain Error vs.
DDS
Temperature.
100
10
80
79
78
77
76
75
74
73
72
71
1
0.1
0.01
0.001
-50
-25
0
25
50
75
100
70
1
Temperature (°C)
10
100
1000
Input Frequency (kHz)
FIGURE 2-38:
I
vs. Temperature.
DDS
FIGURE 2-41:
Common Mode Rejection
vs. Frequency.
4
3.5
3
2.5
2
1.5
1
VDD=5V
FSAMPLE = 100 ksps
0.5
0
-0.5
-1
0
1
2
3
4
5
6
VREF (V)
FIGURE 2-39:
Negative Gain Error vs.
Reference Voltage.
2002 Microchip Technology Inc.
DS21697B-page 13
MCP3302/04
3.0
TEST CIRCUITS
1/2 MCP602
1 kΩ
1 kΩ
+
-
1.4V
5V ±500 mVP-P
To V DD on DUT
20 kΩ
5VP-P
3 kΩ
Test Point
DOUT
1 kΩ
2.63V
CL = 100 pF
FIGURE 3-3:
Power Supply Sensitivity
FIGURE 3-1:
Test Point
Load Circuit for T , T , T
.
DO
R
F
Test Circuit (PSRR).
VREF = 5V
1 µF
VDD = 5V
0.1 µF
VDD
VDD/2
TDIS Waveform 2
TEN Waveform
3 kΩ
100 pF
DOUT
0.1 µF
5VP-P
TDIS Waveform 1
IN(+)
IN(-)
VREF VDD
MCP330X
VSS
VSS
5VP-P
Voltage Waveforms for TDIS
VIH
VCM = 2.5V
CS
DOUT
90%
10%
FIGURE 3-4:
Full Differential Test
Waveform 1*
Configuration Example.
TDIS
DOUT
Waveform 2†
VREF = 2.5V
1µF
VDD = 5V
0.1µF
*Waveform 1 is for an output with internal con-
ditions such that the output is high, unless dis-
abled by the output control.
†Waveform 2 is for an output with internal con-
ditions such that the output is low, unless dis-
abled by the output control.
0.1µF
IN(+)
VREF VDD
MCP330X
5VP-P
IN(-)
VSS
VCM = 2.5V
FIGURE 3-2:
Load circuit for
T
and
DIS
T
.
EN
FIGURE 3-5:
Pseudo Differential Test
Configuration Example.
DS21697B-page 14
2002 Microchip Technology Inc.
MCP3302/04
4.6
Serial Clock (CLK)
4.0
PIN DESCRIPTIONS
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed. See
Figure 7-2 for serial communication protocol.
The descriptions of the pins are listed in Table 4-1.
TABLE 4-1:
Name
PIN FUNCTION TABLE
Function
4.7
AGND
CH0-CH7
DGND
CS/SHDN
Analog Inputs
Digital Ground
Chip Select / Shutdown Input
Serial Data In
Serial Data Out
Ground connection to internal analog circuitry. To
ensure accuracy, this pin must be connected to the
same ground as DGND. If an analog ground plane is
available, it is recommended that this device be tied to
the analog ground plane in the circuit. See Section 6.6
for more information regarding circuit layout.
D
D
IN
OUT
CLK
Serial Clock
AGND
Analog Ground
Reference Voltage Input
+2.7V to 5.5V Power Supply
4.8
Voltage Reference (V
)
REF
V
V
REF
DD
This input pin provides the reference voltage for the
device, which determines the maximum range of the
analog input signal and the LSB size.
The LSB size is determined according to the equation
shown below. As the reference input is reduced, the
LSB size is reduced accordingly.
4.1
CH0-CH7
Analog input channels. These pins have an absolute
voltage range of V - 0.3V to V + 0.3V. The full scale
SS
DD
differential input range is defined as the absolute value
of (IN+) - (IN-). This difference can not exceed the
EQUATION
value of V
occur.
- 1 LSB or digital code saturation will
REF
2 x V
REF
LSB Size =
8192
4.2
DGND
Ground connection to internal digital circuitry. To
ensure accuracy this pin must be connected to the
same ground as AGND. If an analog ground plane is
available, it is recommended that this device be tied to
the analog ground plane in the circuit. See Section 6.6
for more information regarding circuit layout.
When using an external voltage reference device, the
system designer should always refer to the manufac-
turer’s recommendations for circuit layout. Any instabil-
ity in the operation of the reference device will have a
direct effect on the accuracy of the ADC conversion
results.
4.3
Chip Select/Shutdown (CS/SHDN)
4.9
V
DD
The CS/SHDN pin is used to initiate communication
with the device when pulled low. This pin will end a con-
version and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions and cannot be tied low for multi-
ple conversions. See Figure 7-2 for serial communica-
tion protocol.
The voltage on this pin can range from 2.7 to 5.5V. To
ensure accuracy, a 0.1 µF ceramic bypass capacitor
should be placed as close as possible to the pin. See
Section 6.6 for more information regarding circuit lay-
out.
4.4
Serial Data Input (D )
IN
The SPI port serial data input pin is used to clock in
input channel configuration data. Data is latched on the
rising edge of the clock. See Figure 7-2 for serial com-
munication protocol.
4.5
Serial Data Output (D
)
OUT
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place. See Figure 7-2 for serial communication
protocol.
2002 Microchip Technology Inc.
DS21697B-page 15
MCP3302/04
Signal to Noise Ratio - Signal to Noise Ratio (SNR) is
defined as the ratio of the signal to noise measured at
the output of the converter. The signal is defined as the
rms amplitude of the fundamental frequency of the
input signal. The noise value is dependant on the
device noise as well as the quantization error of the
converter and is directly affected by the number of bits
in the converter. The theoretical signal to noise ratio
limit based on quantization error only for an N-bit con-
verter is defined as:
5.0
DEFINITION OF TERMS
Bipolar Operation - This applies to either a differential
or single ended input configuration, where both positive
and negative codes are output from the A/D converter.
Full bipolar range includes all 8192 codes. For bipolar
operation on a single ended input signal, the A/D con-
verter must be configured to operate in pseudo differ-
ential mode.
Unipolar Operation - This applies to either a single
ended or differential input signal where only one side of
the device transfer is being used. This could be either
the positive or negative side, depending on which input
(IN+ or IN-) is being used for the DC bias. Full unipolar
operation is equivalent to a 12-bit converter.
EQUATION
SNR = (6.02N + 1.76)dB
For a 13-bit converter, the theoretical SNR limit is
80.02 dB.
Total Harmonic Distortion - Total Harmonic Distortion
(THD) is the ratio of the rms sum of the harmonics to
the fundamental, measured at the output of the con-
verter. For the MCP3302/04, it is defined using the first
9 harmonics, as is shown in the following equation:
Full Differential Operation - Applying a full differential
signal to both the IN(+) and IN(-) inputs is referred to as
full differential operation. This configuration is
described in Figure 3-4.
Pseudo-Differential Operation - Applying a single
ended signal to only one of the input channels with a
bipolar output is referred to as pseudo differential oper-
ation. To obtain a bipolar output from a single ended
input signal the inverting input of the A/D converter
EQUATION
V22 + V23 + V24 + ..... + V28 + V29
must be biased above V . This operation is described
SS
THD(-dB) = –20 log
--------------------------------------------------------------------------
in Figure 3-5.
V21
Integral Nonlinearity - The maximum deviation from a
straight line passing through the endpoints of the bipo-
lar transfer function is defined as the maximum integral
nonlinearity error. The endpoints of the transfer func-
tion are a point 1/2 LSB above the first code transition
(0x1000) and 1/2 LSB below the last code transition
(0x0FFF).
Differential Nonlinearity - The difference between two
measured adjacent code transitions and the 1 LSB
ideal is defined as differential nonlinearity.
Here V is the rms amplitude of the fundamental and V
1
2
through V are the rms amplitudes of the second
9
through ninth harmonics.
Signal to Noise plus Distortion (SINAD) - Numeri-
cally defined, SINAD is the calculated combination of
SNR and THD. This number represents the dynamic
performance of the converter, including any harmonic
distortion.
Positive Gain Error - This is the deviation between the
EQUATION
last positive code transition (0x0FFF) and the ideal volt-
age level of V
-1/2 LSB, after the bipolar offset error
REF
SINAD(dB) = 20 log 10(SNR ⁄ 10) + 10–(THD ⁄ 10)
has been adjusted out.
Negative Gain Error - This is the deviation between
EffectIve Number of Bits - Effective Number of Bits
(ENOB) states the relative performance of the ADC in
terms of its resolution. This term is directly related to
SINAD by the following equation:
the last negative code transition (0X1000) and the ideal
voltage level of -V
-1/2 LSB, after the bipolar offset
REF
error has been adjusted out.
Offset Error - This is the deviation between the first
positive code transition (0x0001) and the ideal 1/2 LSB
voltage level.
EQUATION
SINAD – 1.76
ENOB(N) = ----------------------------------
6.02
Acquisition Time - The acquisition time is defined as
the time during which the internal sample capacitor is
charging. This occurs for 1.5 clock cycles of the exter-
nal CLK as defined in Figure 7-2.
Conversion Time - The conversion time occurs imme-
diately after the acquisition time. During this time, suc-
cessive approximation of the input signal occurs as the
13-bit result is being calculated by the internal circuitry.
This occurs for 13 clock cycles of the external CLK as
defined in Figure 7-2.
For SINAD performance of 78 dB, the effective number
of bits is 12.66.
Spurious Free Dynamic Range - Spurious Free
Dynamic Range (SFDR) is the ratio of the rms value of
the fundamental to the next largest component in
ADC’s output spectrum. This is, typically, the first har-
monic, but could also be a noise peak.
DS21697B-page 16
2002 Microchip Technology Inc.
MCP3302/04
6.2
Driving the Analog Input
6.0
6.1
APPLICATIONS INFORMATION
Conversion Description
The analog input of the MCP3302/04 is easily driven,
either differentially or single ended. Any signal that is
common to the two input channels will be rejected by
the common mode rejection of the device. During the
charging time of the sample capacitor, a small charging
current will be required. For low source impedances,
this input can be driven directly. For larger source
impedances, a larger acquisition time will be required
due to the RC time constant that includes the source
impedance. For the A/D Converter to meet specifica-
The MCP3302/04 A/D converters employ a conven-
tional SAR architecture. With this architecture, the
potential between the IN+ and IN- inputs are simulta-
neously sampled and stored with the internal sample
circuits for 1.5 clock cycles. Following this sampling
time, the input hold switches of the converter open and
the device uses the collected charge to produce a
serial 13-bit binary two’s complement output code. This
conversion process is driven by the external clock and
must include 13 clock cycles, one for each bit. During
this process, the most significant bit (MSB) is output
first. This bit is the sign bit and indicates if the IN+ or IN-
input is at a higher potential.
tion, the charge holding capacitor (C
given enough time to acquire a 13-bit accurate voltage
level during the 1.5 clock cycle acquisition period.
) must be
SAMPLE
An analog input model is shown in Figure 6-3. This
model is accurate for an analog input, regardless if it is
configured as a single ended input, or the IN+ and IN-
input in differential mode. In this diagram, it is shown
CDAC
that the source impedance (R ) adds to the internal
S
Hold
IN+
sampling switch (R ) impedance, directly affecting the
SS
time that is required to charge the capacitor (C
).
SAMPLE
CSAMP
Consequently, a larger source impedance with no addi-
tional acquisition time increases the offset, gain and
integral linearity errors of the conversion. To overcome
this, a slower clock speed can be used to allow for the
longer charging time. Figure 6-2 shows the maximum
clock speed associated with source impedances.
+
Comp
13-Bit SAR
-
CSAMP
IN-
Shift
Register
Hold
DOUT
2.5
2.0
1.5
1.0
0.5
0.0
FIGURE 6-1:
Simplified Block Diagram.
100
1000
10000
100000
Source Resistance (ohms)
FIGURE 6-2:
Maximum Clock Frequency
vs. Source Resistance (R ) to maintain ±1 LSB
S
INL.
2002 Microchip Technology Inc.
DS21697B-page 17
MCP3302/04
V
DD
Sampling
Switch
V = 0.6V
T
R = 1 kΩ
CHx
SS
R
S
SS
C
SAMPLE
C
I
PIN
LEAKAGE
±1 nA
VA
= DAC capacitance
= 25 pF
V = 0.6V
T
7 pF
V
SS
Legend
VA
signal source
=
=
=
=
=
=
source impedance
input channel pad
input pin capacitance
threshold voltage
R
SS
CHx
C
PIN
V
T
leakage current at the pin
due to various junctions
I
LEAKAGE
SS
sampling switch
=
=
=
sampling switch resistor
sample/hold capacitance
R
S
C
SAMPLE
bring down the high pass corner. The value of R will
need to be 1 kΩ, or less, since higher input impedances
require additional acquisition time. Using the RC values
in Figure 6-4, we have a 100 Hz corner frequency. See
Figure 2-12 for relation between input impedance and
acquisition time.
FIGURE 6-3:
6.2.1
Analog Input Model.
MAINTAINING MINIMUM CLOCK
SPEED
When the MCP3302/04 initiates, charge is stored on
the sample capacitor. When the sample period is com-
plete, the device converts one bit for each clock that is
received. It is important for the user to note that a slow
clock rate will allow charge to bleed off the sample cap
while the conversion is taking place. For the MCP330X
devices, the recommended minimum clock speed dur-
VDD = 5V
0.1 µF
ing the conversion cycle (T
) is 105 kHz. Failure to
C
CONV
10 µF
meet this criteria may induce linearity errors into the
conversion outside the rated specifications. It should
be noted that during the entire conversion cycle, the
A/D converter does not have requirements for clock
speed or duty cycle, as long as all timing specifications
are met.
IN+
VIN
MCP330X
R
1 kΩ
IN-
VREF
VIN
VOUT
6.3
Biasing Solutions
MCP1525
0.1 µF
1 µF
For pseudo-differential bipolar operation, the biasing
circuit (shown in Figure 6-4) shows a single ended
input AC coupled to the converter. This configuration
will give a digital output range of -4096 to +4095. With
the 2.5V reference, the LSB size equal to 610 µV.
FIGURE 6-4:
Pseudo-differential biasing
circuit for bipolar operation.
Using an external operation amplifier on the input
allows for gain and also buffers the input signal from the
input to the ADC allowing for a higher source imped-
ance. This circuit is shown in Figure 6-5.
Although the ADC is not production tested with a 2.5V
reference as shown, linearity will not change more than
0.1 LSB. See Figure 2-2 and Figure 2-9 for DNL and
INL errors versus V
at V = 5V. A trade-off exists
DD
REF
between the high pass corner and the acquisition time.
The value of C will need to be quite large in order to
DS21697B-page 18
2002 Microchip Technology Inc.
MCP3302/04
6.4
Common Mode Input Range
The common mode input range has no restriction and is
VDD = 5V
0.1 µF
equal to the absolute input voltage range: V -0.3V to
SS
V
+ 0.3V. However, for a given V
, the common
DD
REF
10 kΩ
mode voltage has a limited swing, if the entire range of
the A/D converter is to be used. Figure 6-7 and
MCP6021
1 kΩ
Figure 6-8 show the relationship between V
common mode voltage swing. A smaller V
and the
REF
-
IN+
IN-
allows for
REF
REF
VIN
+
MCP330X
wider flexibility in a common mode voltage. V
levels,
1 µF
VREF
down to 400 mv, exhibit less than 0.1 LSB change in
DNL and INL. For characterization graphs that show
this performance relationship, see Figure 2-9 and
Figure 2-12.
1 MΩ
VOUT
VIN
MCP1525
1 µF
V
DD = 5V
0.1 µF
5
4
4.05V
0.95V
2.8V
3
2
1
0
FIGURE 6-5:
Adding an amplifier allows
for gain and also buffers the input from any high
impedance sources.
2.3V
This circuit shows that some headroom will be lost due
to the amplifier output not being able to swing all the
way to the rail. An example would be for an output
swing of 0V to 5V. This limitation can be overcome by
-1
supplying a V
that is slightly less than the common
REF
0.25
1.0
5.0
2.5
VREF (V)
4.0
mode voltage. Using a 2.048V reference for the A/D
converter while biasing the input signal at 2.5V solves
the problem. This circuit is shown in Figure 6-5.
FIGURE 6-7:
Common Mode Input Range
of Full Differential Input Signal versus V
.
REF
VDD = 5V
VDD = 5V
10 kΩ
0.1 µF
5
4.05V
4
MCP606
1 kΩ
2.8V
2.3V
3
2
-
+
IN+
IN-
VIN
MCP330X
1 µF
VREF
1 MΩ
1
0.95V
10 kΩ
0
2.048V
VIN
-1
0.25
0.5
2.5
1.25
VREF (V)
2.0
VOUT
MCP1525
1 µF
0.1 µF
FIGURE 6-8: Common Mode Input Range
for Pseudo Differential Input.
versus V
REF
FIGURE 6-6:
Circuit solution to overcome
amplifier output swing limitation.
2002 Microchip Technology Inc.
DS21697B-page 19
MCP3302/04
6.5
Buffering/Filtering the Analog
6.6
Layout Considerations
Inputs
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
Inaccurate conversion results may occur if the signal
source for the A/D converter is not a low impedance
source. Buffering the input will overcome the imped-
ance issue. It is also recommended that an analog filter
be used to eliminate any signals that may be aliased
back into the conversion results. This is illustrated in
Figure 6-9, where an op amp is used to drive the ana-
log input of the MCP3302/04. This amplifier provides a
low impedance source for the converter input and a low
pass filter, which eliminates unwanted high frequency
noise. Values shown are for a 10 Hz Butterworth Low
Pass filter.
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see Application Note 699 “Anti-Aliasing Analog Filters
for Data Acquisition Systems”.
noise wherever possible. A bypass capacitor from V
DD
to ground should always be used with this device and
should be placed as close as possible to the device pin.
A bypass capacitor value of 0.1 µF is recommended.
Digital and analog traces on the board should be sepa-
rated as much as possible, with no traces running
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possi-
ble from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing V
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors (see Figure 6-10). For more information on lay-
out tips when using the MCP3302/04, or other ADC
devices, refer to Application Note 688, “Layout Tips for
12-Bit A/D Converter Applications”.
®
connections to
DD
VDD
10 µF
VDD
Connection
4.096V
Reference
1 µF
0.1 µF
MCP1541
CL
0.1 µF
VREF
IN+
MCP330X
IN-
Device 4
2.2 µF
MCP601
+
7.86 kΩ
VIN
14.6 kΩ
1 µF
-
Device 1
FIGURE 6-9:
The MCP601 Operational
Device 3
Amplifier is used to implement a 2nd order anti-
aliasing filter for the signal being converted by
the MCP3302/04.
Device 2
FIGURE 6-10:
V
traces arranged in a
DD
‘Star’ configuration in order to reduce errors
caused by current return paths.
DS21697B-page 20
2002 Microchip Technology Inc.
MCP3302/04
6.7
Utilizing the Digital and Analog
Ground Pins
The MCP3302/04 devices provide both digital and ana-
log ground connections to provide another means of
noise reduction. As shown in Figure 6-11, the analog
and digital circuitry are separated internal to the device.
This reduces noise from the digital portion of the device
being coupled into the analog portion of the device. The
two grounds are connected internally through the sub-
strate which has a resistance of 5 -10 Ω.
If no ground plane is utilized, then both grounds must
be connected to V on the board. If a ground plane is
SS
available, both digital and analog ground pins should
be connected to the analog ground plane. If both an
analog and a digital ground plane are available, both
the digital and the analog ground pins should be con-
nected to the analog ground plane, as shown in
Figure 6-11. Following these steps will reduce the
amount of digital noise from the rest of the board being
coupled into the A/D Converter.
V
DD
MCP3302/04
Analog Side
Digital Side
-Sample Cap
-Capacitor Array
-Comparator
-SPI Interface
-Shift Register
-Control Logic
Substrate
5 - 10
Ω
DGND
AGND
0.1 µF
Analog Ground Plane
FIGURE 6-11:
Separation of Analog and
Digital Ground Pins.
2002 Microchip Technology Inc.
DS21697B-page 21
MCP3302/04
TABLE 7-1:
BINARY TWO’S
7.0
SERIAL COMMUNICATIONS
COMPLEMENT OUTPUT
CODE EXAMPLES.
7.1
Output Code Format
Sign
Decimal
The output code format is a binary two’s complement
scheme, with a leading sign bit that indicates the sign
of the output. If the IN+ input is higher than the IN-
input, the sign bit will be a zero. If the IN- input is higher,
the sign bit will be a ‘1’.
Analog Input Levels
Binary Data
Bit
DATA
Full Scale Positive
(IN+)-(IN-)=VREF-1 LSB
0
0
0
0
0
1
1
1
1111 1111 1111
1111 1111 1110
0000 0000 0010
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
0000 0000 0001
+4095
+4094
+2
+1
0
-1
-2
-4095
(IN+)-(IN-) = VREF-2 LSB
IN+ = (IN-) +2 LSB
IN+ = (IN-) +1 LSB
IN+ = IN-
IN+ = (IN-) - 1 LSB
IN+ = (IN-) - 2 LSB
(IN+)-(IN-) = VREF-2 LSB
The diagram shown in Figure 7-1 shows the output
code transfer function. In this diagram, the horizontal
axis is the analog input voltage and the vertical axis is
the output code of the ADC. It shows that when IN+ is
equal to IN-, both the sign bit and the data word is zero.
As IN+ gets larger with respect to IN-, the sign bit is a
zero and the data word gets larger. The full scale output
code is reached at +4095 when the input [(IN+) - (IN-)]
Full Scale Negative
(IN+)-(IN-) = VREF-1 LSB
1
0000 0000 0000
-4096
reaches V
- 1 LSB. When IN- is larger than IN+, the
REF
two’s complement output codes will be seen with the
sign bit being a one. Some examples of analog input
levels and corresponding output codes are shown in
Table 7-1.
Output
Code
Positive Full
Scale Output = V
-1 LSB
REF
0 + 1111 1111 1111 (+4095)
0 + 1111 1111 1110 (+4094)
0 + 0000 0000 0011 (+3)
0 + 0000 0000 0010 (+2)
0 + 0000 0000 0001 (+1)
Analog Input
Voltage
IN+ > IN-
0 + 0000 0000 0000 (0)
IN+ - IN-
IN+ < IN-
1 + 1111 1111 1111 (-1)
1 + 1111 1111 1110 (-2)
1 + 1111 1111 1101 (-3)
-V
REF
V
REF
1 + 0000 0000 0001 (-4095)
1 + 0000 0000 0000 (-4096)
Negative Full
Scale Output = -V
REF
FIGURE 7-1:
Output Code Transfer Function.
DS21697B-page 22
2002 Microchip Technology Inc.
MCP3302/04
TABLE 7-2:
CONFIGURATION BITS FOR
7.2
Communicating with the MCP3302
and MCP3304
THE MCP3302
Control Bit
Selections
Communication with the MCP3302/04 devices is done
using a standard SPI-compatible serial interface. Initi-
ating communication with either device is done by
bringing the CS line low (see Figure 7-2). If the device
was powered up with the CS pin low, it must be brought
high and back low to initiate communication. The first
Input
Channel
Configuration Selection
Single
D2* D1 D0
/Diff
1
1
1
1
0
X
X
X
X
X
0
0
1
1
0
0
1
0
1
0
single ended
single ended
single ended
single ended
differential
CH0
CH1
CH2
CH3
clock received with CS low and D high will constitute
IN
a start bit. The SGL/DIFF bit follows the start bit and will
determine if the conversion will be done using single
ended or differential input mode. Each channel in
single ended mode will operate as a 12-bit converter
with a unipolar output. No negative codes will be output
in single ended mode. The next three bits (D0, D1 and
D2) are used to select the input channel configuration.
Table 7-2 and Table 7-3 show the configuration bits for
the MCP3302 and MCP3304, respectively. The device
will begin to sample the analog input on the fourth rising
edge of the clock after the start bit has been received.
The sample period will end on the falling edge of the
fifth clock following the start bit.
CH0 = IN+
CH1 = IN-
0
0
0
X
X
X
0
1
1
1
0
1
differential
differential
differential
CH0 = IN-
CH1 = IN+
CH2 = IN+
CH3 = IN-
CH2 = IN-
CH3 = IN+
*D2 is don’t care for MCP3302
After the D0 bit is input, one more clock is required to
TABLE 7-3:
CONFIGURATION BITS FOR
THE MCP3304
complete the sample and hold period (D is a “don’t
IN
care” for this clock). On the falling edge of the next
clock, the device will output a low null bit. The next 13
clocks will output the result of the conversion with the
sign bit first, followed by the 12 remaining data bits, as
shown in Figure 7-2. Note that if the device is operating
in the single ended mode, the sign bit will always be
transmitted as a ‘0’. Data is always output from the
device on the falling edge of the clock. If all 13 data bits
have been transmitted, and the device continues to
receive clocks while the CS is held low, the device will
output the conversion result, LSB, first, as shown in
Figure 7-3. If more clocks are provided to the device
while CS is still low (after the LSB first data has been
transmitted), the device will clock out zeros indefinitely.
Control Bit
Selections
Input
Channel
Configuration Selection
SinglE
D2 D1 D0
/Diff
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
single ended
single ended
single ended
single ended
single ended
single ended
single ended
single ended
differential
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
If necessary, it is possible to bring CS low and clock in
leading zeros on the D line before the start bit. This is
IN
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 7.3 for more details on using the MCP3302/04
devices with hardware SPI ports
CH0 = IN+
CH1 = IN-
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
differential
differential
differential
differential
differential
differential
differential
CH0 = IN-
CH1 = IN+
CH2 = IN+
CH3 = IN-
CH2 = IN-
CH3 = IN+
CH4 = IN+
CH5 = IN-
CH4 = IN-
CH5 = IN+
CH6 = IN+
CH7 = IN-
CH6 = IN-
CH7 = IN+
2002 Microchip Technology Inc.
DS21697B-page 23
MCP3302/04
TSAMPLE
TSAMPLE
TCSH
CS
TSUCS
CLK
SGL/
SGL/
Don’t Care
Start
Start
D2 D1 D0
D2
DIN
DIFF
DIFF
HI-Z
HI-Z
Null
Bit
DOUT
B7
SB† B11 B10 B9 B8
B6 B5 B4 B3 B2 B1 B0 *
TCONV
TACQ
TDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB
first data, followed by zeros indefinitely. See Figure 7-3 below.
** T
: during this time, the bias current and the comparator power down while the reference input becomes
DATA
a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
†
When operating in single ended mode, the sign bit will always be transmitted as a ‘0’.
FIGURE 7-2:
Communication with MCP3302/04 (MSB first Format).
TSAMPLE
TCSH
CS
TSUCS
Power Down
CLK
Start
DIN
D2 D1 D0
SGL/
DIFF
Don’t Care
HI-Z
Null
Bit
HI-Z
SB† B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 SB*
DOUT
(MSB)
TCONV
TDATA **
TACQ
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros
indefinitely.
** T
: During this time, the bias circuit and the comparator power down while the reference input becomes
DATA
a high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
†
When operating in single ended mode, the sign bit will always be transmitted as a ‘0’.
FIGURE 7-3:
Communication with MCP3302/04 (LSB first Format).
DS21697B-page 24
2002 Microchip Technology Inc.
MCP3302/04
7.3
Using the MCP3302/04 with
Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the ris-
ing edge. Because communication with the MCP3302
and MCP3304 devices may not need multiples of eight
clocks, it will be necessary to provide more clocks than
are required. This is usually done by sending ‘leading
zeros’ before the start bit. For example, Figure 7-4 and
Figure 7-5 show how the MCP3302/04 devices can be
interfaced to a MCU with a hardware SPI port.
Figure 7-4 depicts the operation shown in SPI Mode
0,0, which requires that the SCLK from the MCU idles
in the ‘low’ state, while Figure 7-5 shows the similar
case of SPI Mode 1,1, where the clock idles in the ‘high’
state.
As shown in Figure 7-4, the first byte transmitted to the
A/D Converter contains 6 leading zeros before the start
bit. Arranging the leading zeros this way produces the
13 data bits to fall in positions easily manipulated by the
MCU. The sign bit is clocked out of the A/D Converter
on the falling edge of clock number 11, followed by the
remaining data bits (MSB first). After the second eight
clocks have been sent to the device, the MCU receive
buffer will contain 2 unknown bits (the output is at high
impedance for the first two clocks), the null bit, the sign
bit and the 4 highest order bits of the conversion. After
the third byte has been sent to the device, the receive
register will contain the lowest order eight bits of the
conversion results. Easier manipulation of the con-
verted data can be obtained by using this method.
Figure 7-5 shows the same situation in SPI Mode 1,1,
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
2002 Microchip Technology Inc.
DS21697B-page 25
MCP3302/04
CS
MCU latches data from A/D Converter
on rising edges of SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
SCLK
Data is clocked out of
A/D Converter on falling edges
SGL/
DIFF
D2 D1
Start
D0
Don’t Care
D
IN
HI-Z
NULL
B1 B0
SB B11 B10 B9 B8
BIT
B7
B6 B5 B4 B3 B2
D
OUT
Start
Bit
1
MCU Transmitted Data
(Aligned with falling
edge of clock)
SGL/
X
X
0
0
0
0
D2 D1
DO
X
X
X
X
X
X
X
X
X
X
X
X
X
DIFF
MCU Received Data
(Aligned with rising
edge of clock)
0
?
?
?
?
?
?
?
?
?
?
SB B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
(Null)
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
Data stored into MCU receive register
after transmission of last 8 bits
? = Unknown Bits
X = Don’t Care Bits
FIGURE 7-4:
SPI Communication with the MCP3302/04 using 8-bit segments (Mode 0,0: SCLK
idles low).
MCU latches data from A/D Converter
on rising edges of SCLK
CS
4
9
1
2
3
5
6
7
8
10 11 12 13 14 15
16
17 18 19 20 21 22 23
24
SCLK
Data is clocked out of
A/D Converter on falling edges
SGL/
Don’t Care
Start
D2
D1
D0
D
IN
DIFF
HI-Z
NULL
SB B11 B10 B9
BIT
B8
B7 B6 B5 B4 B3 B2 B1 B0
D
OUT
Start
Bit
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
SGL/
DIFF
0
0
0
0
1
D2 D1
?
DO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
?
?
?
?
?
?
?
?
?
SB B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
(Null)
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
Data stored into MCU receive register
after transmission of last 8 bits
? = Unknown Bits
X = Don’t Care Bits
FIGURE 7-5:
SPI Communication with the MCP3302/04 using 8-bit segments (Mode 1,1: SCLK
idles high).
DS21697B-page 26
2002 Microchip Technology Inc.
MCP3302/04
8.0
8.1
PACKAGING INFORMATION
Package Marking Information
14-Lead PDIP (300 mil)
Example:
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP3302-B
I/P
0125NNN
YYWWNNN
14-Lead SOIC (150 mil)
MCP3302-B
XXXXXXXXXXX
0YWWNNN
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP (4.4mm) †
Example:
XXXXXXXX
YYWW
3302-C
IYWW
NNN
NNN
†Please contact Microchip Factory for B-Grade TSSOP devices
Legend: XX...X
Customer specific information*
YY
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
WW
NNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard marking consists of Microchip part number, year code, week code, traceability code (facility code,
mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your
Microchip Sales Office.
2002 Microchip Technology Inc.
DS21697B-page 27
MCP3302/04
Package Marking Information (Continued)
16-Lead PDIP (300 mil) (MCP3304)
Example:
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP3304-B
I/P
YYWWNNN
YYWWNNN
16-Lead SOIC (150 mil) (MCP3304)
MCP3304-B
XXXXXXXXXX
XXXXXXXXXXXXX
XXXXXXXXXXXXX
YYWWNNN
IYWWNNN
Legend: XX...X
Customer specific information*
YY
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
WW
NNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard marking consists of Microchip part number, year code, week code, traceability code (facility code,
mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your
Microchip Sales Office.
DS21697B-page 28
2002 Microchip Technology Inc.
MCP3302/04
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
MAX
n
p
A
A2
A1
E
E1
D
L
c
B1
B
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
14
14
.100
.155
.130
2.54
3.94
3.30
.140
.170
.145
3.56
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
4.32
3.68
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
2002 Microchip Technology Inc.
DS21697B-page 29
MCP3302/04
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
14
MAX
n
p
A
A2
A1
E
E1
D
Number of Pins
Pitch
Overall Height
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
.053
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
.052
.004
.228
.150
.337
.010
.016
0
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
Standoff
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
h
L
φ
c
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
0
12
15
0
12
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
DS21697B-page 30
2002 Microchip Technology Inc.
MCP3302/04
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
A1
A2
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
Overall Height
14
14
.026
0.65
A
.043
1.10
Molded Package Thickness
A2
A1
E
E1
D
.033
.002
.246
.169
.193
.020
0
.004
.007
0
.035
.004
.251
.173
.197
.024
4
.006
.010
5
.037
.006
.256
.177
.201
.028
8
.008
.012
10
0.85
0.90
0.10
6.38
4.40
5.00
0.60
4
0.15
0.25
5
0.95
0.15
6.50
4.50
5.10
0.70
8
0.20
0.30
10
Standoff
§
0.05
6.25
4.30
4.90
0.50
0
0.09
0.19
0
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
L
φ
c
B1
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
2002 Microchip Technology Inc.
DS21697B-page 31
MCP3302/04
16-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
16
MAX
n
p
A
A2
A1
E
E1
D
L
c
B1
B
Number of Pins
Pitch
Top to Seating Plane
16
.100
.155
.130
2.54
3.94
3.30
.140
.170
.145
3.56
2.92
4.32
3.68
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
0.38
7.62
6.10
18.80
3.18
0.20
1.14
.036
7.87
5
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-017
DS21697B-page 32
2002 Microchip Technology Inc.
MCP3302/04
16-Lead Plastic Small Outline (SL) – Narrow 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
L
A1
β
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
MAX
n
p
A
A2
A1
E
E1
D
Number of Pins
Pitch
16
16
.050
.061
.057
.007
.237
.154
.390
.015
.033
4
1.27
1.55
1.44
0.18
6.02
3.90
9.91
0.38
0.84
4
Overall Height
.053
.069
1.35
1.75
Molded Package Thickness
Standoff
.052
.004
.228
.150
.386
.010
.016
0
.061
.010
.244
.157
.394
.020
.050
8
1.32
0.10
5.79
3.81
9.80
0.25
0.41
0
1.55
0.25
6.20
3.99
10.01
0.51
1.27
8
§
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
h
L
φ
c
B
α
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
Mold Draft Angle Top
β
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
0
12
15
0
12
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-108
2002 Microchip Technology Inc.
DS21697B-page 33
MCP3302/04
NOTES:
DS21697B-page 34
2002 Microchip Technology Inc.
MCP3302/04
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
013001
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2002 Microchip Technology Inc.
DS21697B-page 35
MCP3302/04
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Application (optional):
Would you like a reply?
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Literature Number:
DS21697B
Device:
MCP3302/04
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS21697B-page 36
2002 Microchip Technology Inc.
MCP3302/04
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
X
/XX
Examples:
a)
b)
c)
MCP3302-BI/P: ±1 LSB INL, Industrial Tem-
Grade Temperature Package
Range
perature, PDIP package
MCP3302-BI/SL: ±1 LSB INL, Industrial
Temperature, SOIC package
MCP3302-CI/ST: ±2 LSB INL, Industrial
Temperature, TSSOP package
Device:
MCP3302: 13-Bit Serial A/D Converter
MCP3302T: 13-Bit Serial A/D Converter (Tape and Reel)
MCP3304: 13-Bit Serial A/D Converter
MCP3304T: 13-Bit Serial A/D Converter (Tape and Reel)
a)
b)
MCP3304-BI/P: ±1 LSB INL, Industrial
Temperature, PDIP package
MCP3304-BI/SL: ±1 LSB INL, Industrial
Temperature, SOIC package
Grade:
B
C
=
=
±1 LSB INL
±2 LSB INL
Temperature Range:
Package:
I
=
-40°C to +85°C
P
=
=
=
Plastic DIP (300 mil Body), 14-lead, 16-lead
Plastic SOIC (150 mil Body), 14-lead, 16-lead
Plastic TSSOP (4.4mm), 14-lead
SL
ST
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21697B-page37
MCP3302/04
NOTES:
DS21697B-page 38
2002 Microchip Technology Inc.
MCP3302/04
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
®
PICmicro 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21697B-page 39
M
WORLDWIDE SALES AND SERVICE
Japan
AMERICAS
ASIA/PACIFIC
Microchip Technology Japan K.K.
Benex S-1 6F
Corporate Office
Australia
2355 West Chandler Blvd.
Microchip Technology Australia Pty Ltd
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
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Austria
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Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
05/16/02
DS21697B-page 40
2002 Microchip Technology Inc.
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