MCP3304T [MICROCHIP]
13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface; 13位差分输入，低功耗A / D转换器，带有SPI串行接口
| 型号： | MCP3304T |
| 厂家： | 
MICROCHIP |
| 描述： | 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface |
| 文件： | 总48页 (文件大小：1255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP3302/04
13-Bit Differential Input, Low Power A/D Converter
with SPI Serial Interface
Features
General Description
• Full Differential Inputs
The MCP3302/04 13-bit A/D converter features full
differential inputs and low-power consumption in a
small package that is ideal for battery-powered
systems and remote data acquisition applications.
• 2 Differential or 4 Single-ended inputs (MCP3302)
• 4 Differential or 8 Single-ended Inputs (MCP3304)
• ±1 LSB maximum DNL
The MCP3302 is user-programmable to provide two
differential input pairs or four single-ended inputs.
• ±1 LSB maximum INL (MCP3302/04-B)
• ±2 LSB maximum INL (MCP3302/04-C)
• Single supply operation: 4.5V to 5.5V
• 100 ksps sampling rate with 5V supply voltage
• 50 nA typical standby current, 1 µA maximum
• 450 µA maximum active current at 5V
• Industrial Temperature Range: -40°C to +85°C
• 14 and 16-pin PDIP, SOIC, and TSSOP packages
The MCP3304 is also user-programmable to configure
into four differential input pairs or eight single-ended
inputs.
Incorporating a successive approximation architecture
with on-board sample and hold circuitry, these 13-bit
A/D converters are specified to have ±1 LSB
Differential Nonlinearity (DNL); ±1 LSB Integral
Nonlinearity (INL) for B-grade and ±2 LSB for C-grade
devices. The industry-standard SPI serial interface
enables 13-bit A/D converter capability to be added to
any PIC® microcontroller.
• Mixed Signal PICtail™ Demo Board (P/N:
MXSIGDM) compatible
Applications
The MCP3302/04 devices feature low current design
that permits operation with typical standby and active
currents of only 50 nA and 300 µA, respectively. The
device is capable of conversion rates of up to 100 ksps
with tested specifications over a 4.5V to 5.5V supply
range. The reference voltage can be varied from
400 mV to 5V, yielding input-referred resolution
between 98 µV and 1.22 mV.
• Remote Sensors
• Battery-operated Systems
• Transducer Interface
The MCP3302 is available in 14-pin PDIP, 150 mil
SOIC and TSSOP packages. The MCP3304 is
available in 16-pin PDIP and 150 mil SOIC packages.
The full differential inputs of these devices enable a
wide variety of signals to be used in applications such
as remote data acquisition, portable instrumentation,
and battery-operated applications.
Package Types
PDIP, SOIC, TSSOP
PDIP, SOIC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
16 VDD
CH0
CH1
CH2
CH3
NC
1
2
3
4
5
6
7
14
13
VDD
VREF
2
3
4
5
15
14
VREF
AGND
12 AGND
13 CLK
CLK
11
10
9
12 DOUT
DOUT
DIN
DIN
6
7
8
11
10
9
NC
CS/SHDN
DGND
DGND
8
CS/SHDN
2011 Microchip Technology Inc.
DS21697F-page 1
MCP3302/04
Functional Block Diagram
VREF
VDD
AGND DGND
CH0
CH1
Input
Channel
Mux
CH7*
CDAC
Comparator
-
Sample
& Hold
Circuits
13-Bit SAR
+
Shift
Register
Control Logic
CS/SHDN DIN
CLK
DOUT
* Channels 5-7 available on MCP3304 Only
DS21697F-page 2
2011 Microchip Technology Inc.
MCP3302/04
† Notice: Stresses above those listed under “Maximum
ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
...................................................................................7.0V
DD
All inputs and outputs w.r.t. V ............... -0.3V to V +0.3V
SS
DD
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Maximum Junction Temperature ..................................150°C
ESD protection on all pins (HBM) 4 kV
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, and V = 5V. Full differential
REF
DD
SS
input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
T = -40°C to +85°C (Note 7). Conversion speed (F ) is 100 ksps with F = 21*F
A
SAMPLE
CLK
SAMPLE
Parameter
Conversion Rate
Symbol
Min
Typ
Max
Units
Conditions
Maximum Sampling Frequency
Conversion Time
F
—
—
100
ksps See F
specification. Note 8
CLK
SAMPLE
T
13
CLK
CONV
periods
Acquisition Time
T
1.5
CLK
ACQ
periods
DC Accuracy
Resolution
12 data bits + sign
bits
Integral Nonlinearity
INL
—
—
—
-3
-3
-3
±0.5
±1
±1
LSB
LSB
LSB
LSB
LSB
LSB
MCP3302/04-B
±2
±1
+2
+2
+6
MCP3302/04-C
Differential Nonlinearity
Positive Gain Error
DNL
±0.5
-0.75
-0.5
+3
Monotonic over temperature
Negative Gain Error
Offset Error
Dynamic Performance
Total Harmonic Distortion
Signal-to-Noise and Distortion
Spurious Free Dynamic Range
Common Mode Rejection
Channel to Channel Crosstalk
Power Supply Rejection
Reference Input
THD
SINAD
SFDR
CMRR
CT
—
—
—
—
—
—
-91
78
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
Note 3
Note 3
Note 3
Note 6
Note 6
Note 4
92
79
> -110
74
PSR
Voltage Range
0.4
—
—
V
V
Note 2
DD
Current Drain
100
150
3
µA
µA
—
0.001
CS = V = 5V
DD
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to V level.
REF
3:
4:
V
V
= 0.1V to 4.9V @ 1 kHz.
IN
=5V DC ±500 mV
@ 1 kHz, see test circuit Figure 1-4.
P-P
DD
5: Maximum clock frequency specification must be met.
6: = 400 mV, V = 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25°C and +85°C.
V
REF
IN
8: For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.
2011 Microchip Technology Inc.
DS21697F-page 3
MCP3302/04
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, and V = 5V. Full differential
REF
DD
SS
input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
T = -40°C to +85°C (Note 7). Conversion speed (F ) is 100 ksps with F = 21*F
A
SAMPLE
CLK
SAMPLE
Parameter
Analog Inputs
Symbol
Min
Typ
Max
Units
Conditions
Full Scale Input Span
Absolute Input Voltage
Leakage Current
CH0 - CH7
CH0 - CH7
-V
—
—
V
V
V
REF
REF
-0.3
V
+ 0.3
DD
—
—
—
0.001
1
±1
µA
kΩ
pF
Switch Resistance
R
—
—
See Figure 5-3
See Figure 5-3
S
Sample Capacitor
C
25
SAMPLE
Digital Input/Output
Data Coding Format
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current
Pin Capacitance
Binary Two’s Complement
V
0.7 V
—
—
—
—
—
—
—
—
—
0.3 V
—
V
V
IH
DD
V
IL
DD
V
4.1
—
V
I
I
= -1 mA, V = 4.5V
DD
OH
OH
OL
V
I
0.4
10
10
10
V
= 1 mA, V = 4.5V
DD
OL
LI
-10
-10
—
µA
µA
pF
V
V
= V or V
SS DD
IN
I
= V or V
SS DD
LO
OUT
C
, C
T = +25°C, F = 1 MHz, Note 1
A
IN
OUT
Timing Specifications:
Clock Frequency (Note 8)
Clock High Time
F
0.105
210
210
100
50
—
—
—
—
—
—
—
—
—
—
—
2.1
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
= 5V, F
= 100 ksps
CLK
DD
SAMPLE
T
Note 5
Note 5
HI
LO
Clock Low Time
T
—
CS Fall To First Rising CLK Edge
Data In Setup time
T
—
SUCS
T
T
—
SU
HD
DO
Data In Hold Time
50
—
CLK Fall To Output Data Valid
T
—
125
200
125
200
100
V
V
V
V
= 5V, see Figure 1-2
= 2.7V, see Figure 1-2
= 5V, see Figure 1-2
= 2.7V, see Figure 1-2
DD
DD
DD
DD
—
CLK Fall To Output Enable
T
—
EN
—
CS Rise To Output Disable
CS Disable Time
T
—
See test circuits, Figure 1-2
Note 1
DIS
T
475
—
—
—
—
ns
ns
CSH
D
Rise Time
T
100
See test circuits, Figure 1-2
OUT
R
Note 1
D
Fall Time
T
—
—
100
ns
See test circuits, Figure 1-2
OUT
F
Note 1
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to V level.
REF
3:
4:
V
V
= 0.1V to 4.9V @ 1 kHz.
IN
=5V DC ±500 mV
@ 1 kHz, see test circuit Figure 1-4.
P-P
DD
5: Maximum clock frequency specification must be met.
6: = 400 mV, V = 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25°C and +85°C.
V
REF
IN
8: For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.
DS21697F-page 4
2011 Microchip Technology Inc.
MCP3302/04
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, and V = 5V. Full differential
REF
DD
SS
input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
T = -40°C to +85°C (Note 7). Conversion speed (F ) is 100 ksps with F = 21*F
A
SAMPLE
CLK
SAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Power Requirements:
Operating Voltage
Operating Current
V
4.5
—
—
—
—
5.5
450
—
V
Note 9
DD
I
300
200
0.05
µA
µA
µA
V
V
, V
, V
= 5V, D
unloaded
OUT
DD
DD
DD
REF
REF
= 2.7V, D
unloaded
OUT
Standby Current
I
1
CS = V = 5.0V
DD
DDS
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to V level.
REF
3:
4:
V
V
= 0.1V to 4.9V @ 1 kHz.
IN
=5V DC ±500 mV
@ 1 kHz, see test circuit Figure 1-4.
P-P
DD
5: Maximum clock frequency specification must be met.
6: = 400 mV, V = 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25°C and +85°C.
V
REF
IN
8: For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
Thermal Resistance, 16L-PDIP
Thermal Resistance, 16L-SOIC
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
JA
JA
JA
JA
JA
—
—
—
—
—
70
95.3
100
70
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
86.1
TCSH
CS
TSUCS
TLO
THI
CLK
THD
MSB IN
TSU
DIN
T
TF
TDO
Null Bit
TDIS
TEN
DOUT
LSB
Sign BIT
FIGURE 1-1:
Timing Parameters.
2011 Microchip Technology Inc.
DS21697F-page 5
MCP3302/04
1.1
Test Circuits
VREF = 5V
VDD = 5V
0.1 µF
1 µF
1.4V
DOUT
0.1 µF
3 kΩ
5VP-P
Test Point
IN(+)
VREFVDD
CL = 100 pF
MCP330X
IN(-)
VSS
5VP-P
FIGURE 1-2:
Load Circuit for TR, TF, TDO
.
VCM = 2.5V
Test Point
VDD
FIGURE 1-5:
Configuration Example.
Full Differential Test
TDIS Waveform 2
VDD/2
3 kΩ
DOUT
TEN Waveform
DIS Waveform 1
100 pF
T
VREF = 2.5V
1µF
VDD = 5V
0.1µF
VSS
0.1µF
Voltage Waveforms for TDIS
VIH
IN(+)
VREFVDD
MCP330X
5VP-P
CS
IN(-)
VSS
DOUT
90%
10%
Waveform 1*
V
CM = 2.5V
TDIS
DOUT
FIGURE 1-6:
Pseudo Differential Test
Waveform 2†
Configuration Example.
*Waveform 1 is for an output with internal
conditions such that the output is high, unless
disabled by the output control.
†Waveform 2 is for an output with internal
conditions such that the output is low, unless
disabled by the output control.
FIGURE 1-3:
TEN
Load circuit for TDIS and
.
1 k
1/2 MCP602
+
-
5V ±500 mV
To VDD on DUT
P-P
1 k
20 kΩ
5V
1 k
2.63V
P-P
FIGURE 1-4:
Power Supply Sensitivity
Test Circuit (PSRR).
DS21697F-page 6
2011 Microchip Technology Inc.
MCP3302/04
2.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = VREF = 5V, full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps,
FCLK = 21*FSAMPLE, TA = +25°C.
.
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
Positive INL
Negative INL
Positive INL
Negative INL
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
50
100
Sample Rate (ksps)
150
200
-50
-25
0
25
50
75
100
125
150
Temperature(°C)
FIGURE 2-1:
Integral Nonlinearity (INL)
FIGURE 2-4:
Integral Nonlinearity (INL)
vs. Sample Rate.
vs. Temperature.
2
1.5
1
1
0.8
0.6
0.4
0.2
0
Positive DNL
Positive INL
Negative INL
0.5
0
-0.2
-0.4
-0.6
-0.8
-1
-0.5
-1
Negative DNL
-1.5
-2
0
1
2
3
4
5
0
50
100
150
200
VREF(V)
Sample Rate (ksps)
FIGURE 2-2:
Integral Nonlinearity (INL)
FIGURE 2-5:
Differential Nonlinearity
vs. VREF.
(DNL) vs. Sample Rate.
1
0.8
0.6
0.4
0.2
0
2
1.5
1
Positive DNL
0.5
0
-0.2
-0.4
-0.6
-0.8
-1
-0.5
-1
Negative DNL
-1.5
-2
-4096 -3072 -2048 -1024
0
1024
2048
3072
4096
0
1
2
3
4
5
6
Code
VREF(V)
FIGURE 2-3:
vs. Code (Representative Part).
Integral Nonlinearity (INL)
FIGURE 2-6:
(DNL) vs. VREF
Differential Nonlinearity
.
2011 Microchip Technology Inc.
DS21697F-page 7
MCP3302/04
Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps,
FCLK = 21*FSAMPLE, TA = +25°C.
1
0.8
0.6
0.4
0.2
0
20
18
16
14
12
10
8
-0.2
-0.4
-0.6
-0.8
-1
6
4
2
0
-4096 -3072 -2048 -1024
0
1024
2048
3072
4096
0
1
2
3
4
5
6
VREF(V)
Code
FIGURE 2-7:
Differential Nonlinearity
FIGURE 2-10:
Offset Error vs. VREF.
(DNL) vs. Code (Representative Part).
0
-0.2
-0.4
-0.6
-0.8
-1
1
0.8
0.6
Positive DNL
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
Negaitive DNL
-1.2
-50
-25
0
25
50
75
100
125
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
FIGURE 2-8:
Differential Nonlinearity
FIGURE 2-11:
Positive Gain Error vs.
(DNL) vs. Temperature.
Temperature.
4
3
100
90
80
70
60
50
40
20
10
2
1
0
-1
-2
-3
0
1
0
1
2
3
4
5
6
10
100
VREF(V)
Input Frequency (kHz)
FIGURE 2-9:
Positive Gain Error vs. VREF
.
FIGURE 2-12:
Signal-to-Noise Ratio (SNR)
vs. Input Frequency.
DS21697F-page 8
2011 Microchip Technology Inc.
MCP3302/04
Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps,
FCLK = 21*FSAMPLE, TA = +25°C.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
80
70
60
50
40
30
20
10
0
-40
-30
-20
-10
0
1
10
100
Input Frequency (kHz)
Input Signal Level (dB)
FIGURE 2-13:
Total Harmonic Distortion
FIGURE 2-16:
Signal-to-Noise and
(THD) vs. Input Frequency.
Distortion (SINAD) vs. Input Signal Level.
3.1
3
13
12
11
10
9
2.9
2.8
2.7
2.6
2.5
8
-50
0
50
100
150
7
0
1
2
3
4
5
6
Temperature (°C)
V
REF (V)
FIGURE 2-14:
Temperature.
Offset Error vs.
FIGURE 2-17:
(ENOB) vs. VREF
Effective Number of Bits
.
79
78
77
76
75
74
73
72
71
70
100
90
80
70
60
50
40
30
20
10
69
1
0
1
10
100
10
100
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-15:
Distortion (SINAD) vs. Input Frequency.
Signal-to-Noise and
FIGURE 2-18:
Range (SFDR) vs. Input Frequency.
Spurious Free Dynamic
2011 Microchip Technology Inc.
DS21697F-page 9
MCP3302/04
Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps,
FCLK = 21*FSAMPLE, TA = +25°C.
450
0
-10
400
-20
-30
-40
350
300
250
200
150
100
50
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0
2
2.5
3
50
0
3.5
4
4.5
5
5.5
6
0
10000
20000
Frequency (Hz)
30000
40000
50000
VDD (V)
FIGURE 2-19:
10 kHz Input (Representative Part).
Frequency Spectrum of
FIGURE 2-22:
IDD vs. VDD.
12.85
12.8
600
500
400
300
200
100
12.75
12.7
12.65
12.6
0
0
100
150
200
1
10
100
Input Frequency (kHz)
Sample Rate (ksps)
FIGURE 2-20:
(ENOB) vs. Input Frequency.
Effective Number of Bits
FIGURE 2-23:
IDD vs. Sample Rate.
-30
-35
-40
-45
-50
-55
-60
-70
-75
-80
390
380
370
360
350
330
320
-50
50
100
150
1
10
100
1000
10000
Ripple Frequency (kHz)
Temperature (°C)
FIGURE 2-21:
Power Supply Rejection
FIGURE 2-24:
IDD vs. Temperature.
(PSR) vs. Ripple Frequency. A 0.1 µF bypass
capacitor is connected to the VDD pin.
DS21697F-page 10
2011 Microchip Technology Inc.
MCP3302/04
Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps,
FCLK = 21*FSAMPLE, TA = +25°C.
120
80
70
100
60
80
50
60
40
20
0
40
30
20
10
0
2
2.5
3
50
0
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
FIGURE 2-25:
IREF vs. VDD
.
FIGURE 2-28:
IDDS vs. VDD.
120
100
80
100
10
1
60
0.1
40
0.01
0.001
20
0
0
-50
-25
0
25
50
75
100
100
150
200
Sample Rate (ksps)
Temperature (°C)
FIGURE 2-26:
IREF vs. Sample Rate.
FIGURE 2-29:
IDDS vs. Temperature.
93
92
91
90
89
87
4
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
86
-50
50
100
150
0
1
2
3
4
5
6
VREF (V)
Temperature (°C)
FIGURE 2-27:
IREF vs. Temperature.
FIGURE 2-30:
Reference Voltage.
Negative Gain Error vs.
2011 Microchip Technology Inc.
DS21697F-page 11
MCP3302/04
Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps,
FCLK = 21*FSAMPLE, TA = +25°C.
2
1.5
1
80
79
78
77
76
75
74
73
72
71
70
0.5
0
-0.5
-1
-1.5
-2
-50
0
50
100
150
1
10
100
1000
Temperature (°C)
Input Frequency (kHz)
FIGURE 2-31:
Negative Gain Error vs.
FIGURE 2-32:
Common Mode Rejection
Temperature.
vs. Frequency.
DS21697F-page 12
2011 Microchip Technology Inc.
MCP3302/04
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP3302
PDIP, SOIC, TSSOP
MCP3304
Symbol
Description
PDIP, SOIC
1
2
1
2
CH0
CH1
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
3
3
CH2
4
4
CH3
—
—
—
—
7
5
CH4
6
CH5
7
CH6
8
CH7
9
DGND
CS/SHDN
DIN
Digital Ground
8
10
11
12
13
14
15
16
—
Chip Select / Shutdown Input
Serial Data In
9
10
11
12
13
14
5, 6
DOUT
CLK
Serial Data Out
Serial Clock
AGND
VREF
VDD
Analog Ground
Reference Voltage Input
+4.5V to 5.5V Power Supply
No Connection
NC
3.1
Analog Inputs (CH0-CH7)
3.4
Serial Data Input (D )
IN
Analog input channels. These pins have an absolute
voltage range of VSS - 0.3V to VDD+ 0.3V. The full scale
differential input range is defined as the absolute value
of (IN+) - (IN-). This difference can not exceed the
value of VREF - 1 LSB or digital code saturation will
occur.
The SPI port serial data input pin is used to clock in
input channel configuration data. Data is latched on the
rising edge of the clock. See Figure 6-2 for serial
communication protocol.
3.5
Serial Data Output (D
)
OUT
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place. See Figure 6-2 for serial communication
protocol.
3.2
Digital Ground (DGND)
Ground connection to internal digital circuitry. To
ensure accuracy this pin must be connected to the
same ground as AGND. If an analog ground plane is
available, it is recommended that this device be tied to
the analog ground plane in the circuit. See Section 5.6
“Layout Considerations” for more information
regarding circuit layout.
3.6
Serial Clock (CLK)
The SPI clock pin is used to initiate a conversion, as
well as to clock out each bit of the conversion as it takes
place. See Section 5.2 “Driving the Analog Input”
for constraints on clock speed, and Figure 6-2 for serial
communication protocol.
3.3
Chip Select/Shutdown (CS/SHDN)
The CS/SHDN pin is used to initiate communication
with the device when pulled low. This pin will end a
conversion and put the device in low-power standby
when pulled high. The CS/SHDN pin must be pulled
high between conversions and cannot be tied low for
multiple conversions. See Figure 6-2 for serial
communication protocol.
2011 Microchip Technology Inc.
DS21697F-page 13
MCP3302/04
3.7
Analog Ground (AGND)
3.9
Power Supply (V
)
DD
Ground connection to internal analog circuitry. To
ensure accuracy, this pin must be connected to the
same ground as DGND. If an analog ground plane is
available, it is recommended that this device be tied to
the analog ground plane in the circuit. See Section 5.6
“Layout Considerations” for more information
regarding circuit layout.
The device can operate from 2.7V to 5.5V, but the data
conversion performance is from 4.5V to 5.5V supply
range. To ensure accuracy, a 0.1 µF ceramic bypass
capacitor should be placed as close as possible to the
pin. See Section 5.6 “Layout Considerations” for
more information regarding circuit layout.
3.8
Voltage Reference (V
)
REF
This input pin provides the reference voltage for the
device, which determines the maximum range of the
analog input signal and the LSB size.
The LSB size is determined according to the equation
shown below. As the reference input is reduced, the
LSB size is reduced accordingly.
EQUATION 3-1:
2 x VREF
LSB Size =
8192
When using an external voltage reference device, the
system designer should always refer to the
manufacturer’s recommendations for circuit layout.
Any instability in the operation of the reference device
will have a direct effect on the accuracy of the ADC
conversion results.
DS21697F-page 14
2011 Microchip Technology Inc.
MCP3302/04
Signal-to-Noise Ratio - Signal-to-Noise Ratio (SNR)
is defined as the ratio of the signal-to-noise measured
at the output of the converter. The signal is defined as
the rms amplitude of the fundamental frequency of the
input signal. The noise value is dependant on the
device noise as well as the quantization error of the
converter and is directly affected by the number of bits
in the converter. The theoretical signal-to-noise ratio
limit based on quantization error only for an N-bit
converter is defined as:
4.0
DEFINITION OF TERMS
Bipolar Operation - This applies to either a differential
or single-ended input configuration, where both
positive and negative codes are output from the A/D
converter. Full bipolar range includes all 8192 codes.
For bipolar operation on a single-ended input signal,
the A/D converter must be configured to operate in
pseudo differential mode.
Unipolar Operation - This applies to either a single-
ended or differential input signal where only one side of
the device transfer is being used. This could be either
the positive or negative side, depending on which input
(IN+ or IN-) is being used for the DC bias. Full unipolar
operation is equivalent to a 12-bit converter.
EQUATION 4-1:
SNR = 6.02N + 1.76dB
For a 13-bit converter, the theoretical SNR limit is
80.02 dB.
Full Differential Operation - Applying a full differential
signal to both the IN(+) and IN(-) inputs is referred to as
full differential operation. This configuration is
described in Figure 1-5.
Total Harmonic Distortion - Total Harmonic Distortion
(THD) is the ratio of the rms sum of the harmonics to
the fundamental, measured at the output of the
converter. For the MCP3302/04, it is defined using the
first 9 harmonics, as is shown in the following equation:
Pseudo-Differential Operation - Applying a single-
ended signal to only one of the input channels with a
bipolar output is referred to as pseudo differential
operation. To obtain a bipolar output from a single-
ended input signal the inverting input of the A/D
converter must be biased above VSS. This operation is
described in Figure 1-6.
EQUATION 4-2:
V22 + V23 + V24 + ..... + V28 + V29
THD(-dB) = –20 log-------------------------------------------------------------------------------
V21
Integral Nonlinearity - The maximum deviation from a
straight line passing through the endpoints of the
bipolar transfer function is defined as the maximum
integral nonlinearity error. The endpoints of the transfer
function are a point 1/2 LSB above the first code
transition (0x1000) and 1/2 LSB below the last code
transition (0x0FFF).
Here V1 is the rms amplitude of the fundamental and V2
through V9 are the rms amplitudes of the second
through ninth harmonics.
Signal-to-Noise plus Distortion (SINAD) - Numeri-
cally defined, SINAD is the calculated combination of
SNR and THD. This number represents the dynamic
performance of the converter, including any harmonic
distortion.
Differential Nonlinearity - The difference between two
measured adjacent code transitions and the 1 LSB
ideal is defined as differential nonlinearity.
Positive Gain Error - This is the deviation between the
last positive code transition (0x0FFF) and the ideal
voltage level of VREF-1/2 LSB, after the bipolar offset
error has been adjusted out.
EQUATION 4-3:
SINAD(dB) = 20 log 10SNR 10 + 10–THD 10
Negative Gain Error - This is the deviation between
the last negative code transition (0X1000) and the ideal
voltage level of -VREF-1/2 LSB, after the bipolar offset
error has been adjusted out.
EffectIve Number of Bits - Effective Number of Bits
(ENOB) states the relative performance of the ADC in
terms of its resolution. This term is directly related to
SINAD by the following equation:
Offset Error - This is the deviation between the first
positive code transition (0x0001) and the ideal 1/2 LSB
voltage level.
EQUATION 4-4:
Acquisition Time - The acquisition time is defined as
the time during which the internal sample capacitor is
charging. This occurs for 1.5 clock cycles of the
external CLK as defined in Figure 6-2.
SINAD – 1.76
ENOBN = -----------------------------------
6.02
For SINAD performance of 78 dB, the effective number
of bits is 12.66.
Conversion Time - The conversion time occurs
immediately after the acquisition time. During this time,
successive approximation of the input signal occurs as
the 13-bit result is being calculated by the internal
circuitry. This occurs for 13 clock cycles of the external
CLK as defined in Figure 6-2.
Spurious Free Dynamic Range - Spurious Free
Dynamic Range (SFDR) is the ratio of the rms value of
the fundamental to the next largest component in the
output spectrum of the ADC. This is, typically, the first
harmonic, but could also be a noise peak.
2011 Microchip Technology Inc.
DS21697F-page 15
MCP3302/04
NOTES:
DS21697F-page 16
2011 Microchip Technology Inc.
MCP3302/04
5.2
Driving the Analog Input
5.0
5.1
APPLICATIONS INFORMATION
Conversion Description
The analog input of the MCP3302/04 is easily driven,
either differentially or single ended. Any signal that is
common to the two input channels will be rejected by
the common mode rejection of the device. During the
charging time of the sample capacitor, a small charging
current will be required. For low-source impedances,
this input can be driven directly. For larger source
impedances, a larger acquisition time will be required,
due to the RC time constant that includes the source
impedance. For the A/D Converter to meet specifica-
tion, the charge holding capacitor (CSAMPLE) must be
given enough time to acquire a 13-bit accurate voltage
level during the 1.5 clock cycle acquisition period.
The MCP3302/04 A/D converter employ a conven-
tional SAR architecture. With this architecture, the
potential between the IN+ and IN- inputs are
simultaneously sampled and stored with the internal
sample circuits for 1.5 clock cycles (tACQ). Following
this sampling time, the input hold switches of the con-
verter open and the device uses the collected charge to
produce a serial 13-bit binary two’s complement output
code. This conversion process is driven by the external
clock and must include 13 clock cycles, one for each
bit. During this process, the most significant bit (MSB)
is output first. This bit is the sign bit and indicates
whether the IN+ input or the IN- input is at a higher
potential.
An analog input model is shown in Figure 5-3. This
model is accurate for an analog input, regardless of
whether it is configured as a single-ended input, or the
IN+ and IN- input in differential mode. In this diagram,
it is shown that the source impedance (RS) adds to the
internal sampling switch (RSS) impedance, directly
affecting the time that is required to charge the capaci-
tor (CSAMPLE). Consequently, a larger source imped-
ance with no additional acquisition time increases the
offset, gain, and integral linearity errors of the conver-
sion. To overcome this, a slower clock speed can be
used to allow for the longer charging time. Figure 5-2
shows the maximum clock speed associated with
source impedances.
CDAC
Hold
IN+
CSAMP
+
Comp
13-Bit SAR
-
CSAMP
IN-
Shift
Register
Hold
2.5
2.0
1.5
1.0
0.5
0.0
DOUT
FIGURE 5-1:
Simplified Block Diagram.
100
1000
10000
100000
Source Resistance (ohms)
FIGURE 5-2:
Maximum Clock Frequency
vs. Source Resistance (RS) to maintain ±1 LSB
INL.
2011 Microchip Technology Inc.
DS21697F-page 17
MCP3302/04
VDD
Sampling
Switch
VT = 0.6V
VT = 0.6V
RSS = 1 k
CHx
RS
SS
CSAMPLE
= DAC capacitance
= 25 pF
CPIN
7 pF
ILEAKAGE
±1 nA
VA
VSS
Legend
VA = signal source
RS = source impedance
CHx = input channel pad
CPIN = input pin capacitance
VT = threshold voltage
ILEAKAGE = leakage current at the pindue to various junctions
SS = sampling switch
RSS = sampling switch resistor
CSAMPLE = sample/hold capacitance
FIGURE 5-3:
5.2.1
Analog Input Model.
Using the values in Figure 5-4, we have a 100 Hz cor-
ner frequency. See Figure 5-2 for relation between
input impedance and acquisition time.
MAINTAINING MINIMUM CLOCK
SPEED
When the MCP3302/04 initiates, charge is stored on
the sample capacitor. When the sample period is
complete, the device converts one bit for each clock
that is received. It is important for the user to note that
a slow clock rate will allow charge to bleed off the
sample capacitor while the conversion is taking place.
For the MCP330X devices, the recommended mini-
V
= 5V
DD
0.1 µF
mum clock speed during the conversion cycle (TCONV
)
C
10 µF
is 105 kHz. Failure to meet this criteria may induce
linearity errors into the conversion outside the rated
specifications. It should be noted that during the entire
conversion cycle, the A/D converter does not have
requirements for clock speed or duty cycle, as long as
all timing specifications are met.
IN+
IN-
V
IN
MCP330X
R
1 k
V
REF
5.3
Biasing Solutions
V
V
IN
OUT
For pseudo-differential bipolar operation, the biasing
circuit shown in Figure 5-4 shows a single-ended input
AC coupled to the converter. This configuration will give
a digital output range of -4096 to +4095. With the 2.5V
reference, the LSB size equal to 610 µV.
MCP1525
0.1 µF
1 µF
Although the ADC is not production tested with a 2.5V
reference as shown, linearity will not change more than
0.1 LSB. See Figure 2-2 and Figure 2-6 for INL and
DNL errors versus VREF at VDD = 5V. A trade-off exists
between the high-pass corner and the acquisition time.
The value of C will need to be quite large in order to
bring down the high-pass corner. The value of R needs
to be 1 kΩ, or less, since higher input impedances
require additional acquisition time.
FIGURE 5-4:
circuit for bipolar operation.
Pseudo-differential biasing
DS21697F-page 18
2011 Microchip Technology Inc.
MCP3302/04
Using an external operation amplifier on the input
allows for gain and also buffers the input signal from the
input to the ADC allowing for a higher source
impedance. This circuit is shown in Figure 5-5.
5.4
Common Mode Input Range
The common mode input range has no restriction and is
equal to the absolute input voltage range: VSS -0.3V to
VDD + 0.3V. However, for a given VREF, the common
mode voltage has a limited swing, if the entire range of
the A/D converter is to be used. Figure 5-7 and
Figure 5-8 show the relationship between VREF and the
common mode voltage swing. A smaller VREF allows for
wider flexibility in a common mode voltage. VREF levels,
down to 400 mV, exhibit less than 0.1 LSB change in
INL and DNL.
VDD = 5V
10 k
0.1 µF
MCP6021
1 k
-
IN+
IN-
MCP330X
VIN
+
For characterization graphs that show this performance
relationship, see Figure 2-2 and Figure 2-6.
1 µF
VREF
1 M
VDD = 5V
5
VOUT VIN
4.05V
MCP1525
4
1 µF
0.1 µF
2.8V
3
2
2.3V
FIGURE 5-5:
Adding an amplifier allows
for gain and also buffers the input from any high-
impedance sources.
1
0.95V
0
This circuit shows that some headroom will be lost due
to the amplifier output not being able to swing all the
way to the rail. An example would be for an output
swing of 0V to 5V. This limitation can be overcome by
supplying a VREF that is slightly less than the common
mode voltage. Using a 2.048V reference for the A/D
converter while biasing the input signal at 2.5V solves
the problem. This circuit is shown in Figure 5-6.
-1
0.25
1.0
5.0
2.5
4.0
VREF(V)
FIGURE 5-7:
of Full Differential Input Signal versus VREF
Common Mode Input Range
.
VDD = 5V
5
4
VDD = 5V
4.05V
0.95V
10 k
0.1 µF
2.8V
2.3V
3
2
1
0
MCP606
1 k
-
IN+
IN-
MCP330X
VIN
+
1 µF
VREF
1 M
10 k
-1
0.25
0.5
2.5
1.25
2.0
2.048V
VREF (V)
Common Mode Input Range
FIGURE 5-8:
versus VREF for Pseudo Differential Input.
VOUT VIN
MCP1525
1 µF
0.1 µF
FIGURE 5-6:
Circuit solution to overcome
amplifier output swing limitation.
2011 Microchip Technology Inc.
DS21697F-page 19
MCP3302/04
5.5
Buffering/Filtering the Analog
Inputs
5.6
Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor from VDD
to ground should always be used with this device and
should be placed as close as possible to the device pin.
A bypass capacitor value of 0.1 µF is recommended.
Inaccurate conversion results may occur if the signal
source for the A/D converter is not a low-impedance
source. Buffering the input will overcome the
impedance issue. It is also recommended that an
analog filter be used to eliminate any signals that may
be aliased back into the conversion results. This is
illustrated in Figure 5-9, where an op amp is used to
drive the analog input of the MCP3302/04. This
amplifier provides a low-impedance source for the
converter input and a low-pass filter, which eliminates
unwanted high-frequency noise. Values shown are for
a 10 Hz Butterworth Low-Pass filter.
Digital and analog traces on the board should be
separated as much as possible, with no traces running
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high-
frequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors (see Figure 5-10). Layout tips for using the
MCP3302, MCP3304, or other ADC devices, are avail-
able in AN688, “Layout Tips for 12-Bit A/D Converter
Applications”, from www.microchip.com.
Low-pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab® software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more detailed information on filtering
signals, see AN699 “Anti-Aliasing, Analog Filters for
Data Acquisition Systems”, at www.microchip.com.
V
DD
10 µF
VDD
Connection
4.096V
Reference
1 µF
0.1 µF
MCP1541
C
L
0.1 µF
V
REF
IN+
MCP330X
IN-
Device 4
2.2 µF
MCP601
7.86 k
IN
+
-
V
14.6 k
1 µF
Device 1
FIGURE 5-9:
The MCP601 Operational
Device 3
Amplifier is used to implement a 2nd order anti-
aliasing filter for the signal being converted by
the MCP3302/04.
Device 2
FIGURE 5-10:
VDD traces arranged in a
‘Star’ configuration in order to reduce errors
caused by current return paths.
DS21697F-page 20
2011 Microchip Technology Inc.
MCP3302/04
5.7
Utilizing the Digital and Analog
Ground Pins
The MCP3302/04 devices provide both digital and
analog ground connections to provide another means
of noise reduction. As shown in Figure 5-11, the analog
and digital circuitry are separated internal to the device.
This reduces noise from the digital portion of the device
being coupled into the analog portion of the device. The
two grounds are connected internally through the
substrate which has a resistance of 5 -10Ω.
If no ground plane is utilized, then both grounds must
be connected to VSS on the board. If a ground plane is
available, both digital and analog ground pins should
be connected to the analog ground plane. If both an
analog and a digital ground plane are available, both
the digital and the analog ground pins should be
connected to the analog ground plane, as shown in
Figure 5-11. Following these steps will reduce the
amount of digital noise from the rest of the board being
coupled into the A/D Converter.
V
DD
MCP3302/04
Digital Side
Analog Side
-Sample Cap
-Capacitor Array
-Comparator
-SPI Interface
-Shift Register
-Control Logic
Substrate
5 - 10
AGND
DGND
0.1 µF
Analog Ground Plane
FIGURE 5-11:
Separation of Analog and
Digital Ground Pins.MCP3302/04.
2011 Microchip Technology Inc.
DS21697F-page 21
MCP3302/04
NOTES:
DS21697F-page 22
2011 Microchip Technology Inc.
MCP3302/04
6.0
6.1
SERIAL COMMUNICATIONS
Output Code Format
The output code format is a binary two’s complement
scheme, with a leading sign bit that indicates the sign
of the output. If the IN+ input is higher than the IN-
input, the sign bit will be a zero. If the IN- input is higher,
the sign bit will be a ‘1’.
The diagram shown in Figure 6-1 shows the output
code transfer function. In this diagram, the horizontal
axis is the analog input voltage and the vertical axis is
the output code of the ADC. It shows that when IN+ is
equal to IN-, both the sign bit and the data word is zero.
As IN+ gets larger with respect to IN-, the sign bit is a
zero and the data word gets larger. The full scale output
code is reached at +4095 when the input [(IN+) - (IN-)]
reaches VREF - 1 LSB. When IN- is larger than IN+, the
two’s complement output codes will be seen with the
sign bit being a one. Some examples of analog input
levels and corresponding output codes are shown in
Table 6-1.
TABLE 6-1:
BINARY TWO’S COMPLEMENT OUTPUT CODE EXAMPLES.
Sign
Bit
Decimal
Binary Data
Analog Input Levels
DATA
0
1111 1111 1111
+4095
Full Scale Positive
(IN+)-(IN-)=VREF-1 LSB
(IN+)-(IN-) = VREF-2 LSB
IN+ = (IN-) +2 LSB
IN+ = (IN-) +1 LSB
IN+ = IN-
0
0
0
0
1
1
1
1
1111 1111 1110
0000 0000 0010
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
0000 0000 0001
0000 0000 0000
+4094
+2
+1
0
IN+ = (IN-) - 1 LSB
IN+ = (IN-) - 2 LSB
IN+ - IN- = -VREF +1 LSB
IN+ - IN- = -VREF
-1
-2
-4095
-4096
Full Scale Negative
2011 Microchip Technology Inc.
DS21697F-page 23
MCP3302/04
Output
Code
Positive Full
Scale Output = VREF -1 LSB
0 + 1111 1111 1111 (+4095)
0 + 1111 1111 1110 (+4094)
0 + 0000 0000 0011 (+3)
0 + 0000 0000 0010 (+2)
0 + 0000 0000 0001 (+1)
Analog Input
IN+ > IN-
0 + 0000 0000 0000 (0)
Voltage
IN+ - IN-
IN+ < IN-
1 + 1111 1111 1111 (-1)
1 + 1111 1111 1110 (-2)
1 + 1111 1111 1101 (-3)
-VREF
VREF
1 + 0000 0000 0001 (-4095)
1 + 0000 0000 0000 (-4096)
Negative Full
Scale Output = -VREF
FIGURE 6-1:
Output Code Transfer Function.
clocks will output the result of the conversion with the
sign bit first, followed by the 12 remaining data bits, as
shown in Figure 6-2. Note that if the device is operating
in the Single-ended mode, the sign bit will always be
transmitted as a ‘0’. Data is always output from the
device on the falling edge of the clock. If all 13 data bits
have been transmitted, and the device continues to
receive clocks while the CS is held low, the device will
output the conversion result, LSB, first, as shown in
Figure 6-3. If more clocks are provided to the device
while CS is still low (after the LSB first data has been
transmitted), the device will clock out zeros indefinitely.
6.2
Communicating with the MCP3302
and MCP3304
Communication with the MCP3302/04 devices is done
using a standard SPI-compatible serial interface.
Initiating communication with either device is done by
bringing the CS line low (see Figure 6-2). If the device
was powered up with the CS pin low, it must be brought
high and back low to initiate communication. The first
clock received with CS low and DIN high will constitute
a start bit. The SGL/DIFF bit follows the start bit and will
determine if the conversion will be done using single-
ended or differential input mode. Each channel in
Single-ended mode will operate as a 12-bit converter
with a unipolar output. No negative codes will be output
in Single-ended mode. The next three bits (D0, D1, and
D2) are used to select the input channel configuration.
Table 6-1 and Table 6-2 show the configuration bits for
the MCP3302 and MCP3304, respectively. The device
will begin to sample the analog input on the fourth rising
edge of the clock after the start bit has been received.
The sample period will end on the falling edge of the
fifth clock following the start bit.
If necessary, it is possible to bring CS low and clock in
leading zeros on the DIN line before the start bit. This is
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 6.3
“Using
the
MCP3302/04
with
Microcontroller (MCU) SPI Ports” for more details on
using the MCP3302/04 devices with hardware SPI
ports.
After the D0 bit is input, one more clock is required to
complete the sample and hold period (DIN is a “don’t
care” for this clock). On the falling edge of the next
clock, the device will output a low null bit. The next 13
DS21697F-page 24
2011 Microchip Technology Inc.
MCP3302/04
TABLE 6-1:
CONFIGURATION BITS FOR
THE MCP3302
TABLE 6-2:
CONFIGURATION BITS FOR
THE MCP3304
Control Bit
Selections
Control Bit
Selections
Input
Channel
Input
Channel
Configuration Selection
Configuration Selection
Single
/Diff
Single
/Diff
D2* D1 D0
D2 D1 D0
1
1
1
1
0
X
X
X
X
X
0
0
1
1
0
0
1
0
1
0
single ended
single ended
single ended
single ended
differential
CH0
CH1
CH2
CH3
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
single ended
single ended
single ended
single ended
single ended
single ended
single ended
single ended
differential
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0 = IN+
CH1 = IN-
0
0
0
X
X
X
0
1
1
1
0
1
differential
differential
differential
CH0 = IN-
CH1 = IN+
CH2 = IN+
CH3 = IN-
CH0 = IN+
CH1 = IN-
CH2 = IN-
CH3 = IN+
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
differential
differential
differential
differential
differential
differential
differential
CH0 = IN-
CH1 = IN+
*D2 is don’t care for MCP3302
CH2 = IN+
CH3 = IN-
CH2 = IN-
CH3 = IN+
CH4 = IN+
CH5 = IN-
CH4 = IN-
CH5 = IN+
CH6 = IN+
CH7 = IN-
CH6 = IN-
CH7 = IN+
2011 Microchip Technology Inc.
DS21697F-page 25
MCP3302/04
TSAMPLE
TSAMPLE
TCSH
CS
TSUCS
CLK
SGL/
DIFF
SGL/
D2
Start
Start
Don’t Care
D2 D1 D0
DIN
DIFF
HI-Z
HI-Z
Null
Bit
DOUT
SB† B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 *
TCONV
TACQ
TDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB
first data, followed by zeros indefinitely. See Figure 6-3 below.
** TDATA: during this time, the bias current and the comparator power down while the reference input becomes
a high-impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
† When operating in Single-ended mode, the sign bit will always be transmitted as a ‘0’.
FIGURE 6-2:
Communication with MCP3302/04 (MSB first Format).
TSAMPLE
TCSH
CS
T
SUCS
Power Down
CLK
Start
DIN
D2 D1 D0
SGL/
DIFF
Don’t Care
HI-Z
Null
Bit
HI-Z
SB† B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 SB*
DOUT
(MSB)
TCONV
TDATA **
TACQ
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros
indefinitely.
** TDATA: During this time, the bias circuit and the comparator power down while the reference input becomes
a high-impedance node, leaving the CLK running to clock out LSB first data or zeroes.
† When operating in Single-ended mode, the sign bit will always be transmitted as a ‘0’.
FIGURE 6-3:
Communication with MCP3302/04 (LSB first Format).
DS21697F-page 26
2011 Microchip Technology Inc.
MCP3302/04
As shown in Figure 6-4, the first byte transmitted to the
A/D Converter contains 6 leading zeros before the start
bit. Arranging the leading zeros this way produces the
13 data bits to fall in positions easily manipulated by the
MCU. The sign bit is clocked out of the A/D Converter
on the falling edge of clock number 11, followed by the
remaining data bits (MSB first). After the second eight
clocks have been sent to the device, the MCU receive
buffer will contain 2 unknown bits (the output is at high-
impedance for the first two clocks), the null bit, the sign
bit, and the 4 highest order bits of the conversion. After
the third byte has been sent to the device, the receive
register will contain the lowest order eight bits of the
conversion results. Easier manipulation of the
converted data can be obtained by using this method.
6.3
Using the MCP3302/04 with
Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the
rising edge. Because communication with the
MCP3302 and MCP3304 devices may not need
multiples of eight clocks, it will be necessary to provide
more clocks than are required. This is usually done by
sending ‘leading zeros’ before the start bit. For
example, Figure 6-4 and Figure 6-5 show how the
MCP3302/04 devices can be interfaced to a MCU with
a hardware SPI port. Figure 6-4 depicts the operation
shown in SPI Mode 0,0, which requires that the SCLK
from the MCU idles in the ‘low’ state, while Figure 6-5
shows the similar case of SPI Mode 1,1, where the
clock idles in the ‘high’ state.
Figure 6-5 shows the same situation in SPI Mode 1,1,
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
CS
MCU latches data from A/D Converter
on rising edges of SCLK
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
Data is clocked out of
A/D Converter on falling edges
SGL/
DIFF
D2 D1
D0
Start
Don’t Care
DIN
HI-Z
NULL
BIT
SB B11 B10 B9 B8
B7
B6 B5 B4 B3 B2 B1 B0
DOUT
Start
Bit
MCU Transmitted Data
(Aligned with falling
edge of clock)
SGL/
DIFF
X
X
X
X
X
X
X
0
0
0
0
1
D2
D1
DO
X
X
X
X
X
X
X
X
MCU Received Data
(Aligned with rising
edge of clock)
0
?
?
?
?
?
?
?
?
?
?
SB B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
(Null)
Data stored into MCU receive
register after transmission of first 8
bits
Data stored into MCU receive
register after transmission of
second 8 bits
Data stored into MCU receive
register after transmission of last
8 bits
? = Unknown Bits
X = Don’t Care Bits
FIGURE 6-4:
SPI Communication with the MCP3302/04 using 8-bit segments
(Mode 0,0: SCLK idles low).
2011 Microchip Technology Inc.
DS21697F-page 27
MCP3302/04
MCU latches data from A/D Converter
on rising edges of SCLK
CS
4
9
1
2
3
5
6
7
8
10 11 12 13 14 15
16
17 18 19 20 21 22 23
24
SCLK
Data is clocked out of
A/D Converter on falling edges
SGL/
Don’tCare
Start
D2
D1
D0
DIN
DIFF
HI-Z
NULL
BIT
SB B11 B10 B9
B8
B7 B6 B5 B4 B3 B2 B1 B0
DOUT
Start
MCU Transmitted Data
(Aligned with falling
edge of clock)
Bit
SGL/
DIFF
0
0
0
0
1
D2 D1
?
DO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MCU Received Data
(Aligned with rising
edge of clock)
0
(Null)
?
?
?
?
?
?
?
?
?
SB B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
Data stored into MCU receive
register after transmission of first
8 bits
Data stored into MCU receive
register after transmission of
second 8 bits
Data stored into MCU receive
register after transmission of last
8 bits
? = Unknown Bits
X = Don’t Care Bits
FIGURE 6-5:
SPI Communication with the MCP3302/04 using 8-bit segments
(Mode 1,1: SCLK idles high).
DS21697F-page 28
2011 Microchip Technology Inc.
MCP3302/04
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
14-Lead PDIP (300 mil)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP3302-B
I/P^
e
3
YYWWNNN
1112256
14-Lead SOIC (150 mil)
Example:
MCP3302-B
XXXXXXXXXXX
XXXXXXXXXXX
I/SL^
e
3
YYWWNNN
1112256
14-Lead TSSOP (4.4mm)
Example:
XXXXXXXX
XYWW
3302-C
I112
256
NNN
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2011 Microchip Technology Inc.
DS21697F-page 29
MCP3302/04
7.2
Package Marking Information (Continued)
16-Lead PDIP (300 mil)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP3304-B
I/P
e
3
YYWWNNN
1112256
16-Lead SOIC (150 mil)
Example:
MCP3304-B
XXXXXXXXXXXXX
XXXXXXXXXXXXX
XXXIII/XSXLXXXX
e
3
YYWWNNN
1112256
DS21697F-page 30
2011 Microchip Technology Inc.
MCP3302/04
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ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
c
A1
b1
b
e
eB
ꢯꢄꢃꢏꢇꢰꢱꢝꢲꢠꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ
ꢢꢰꢱ
ꢱꢴꢢ
ꢢꢦꢵ
ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ
ꢂꢃꢏꢖꢘ
ꢫꢕꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢀꢥ
ꢌ
ꢁꢀꢣꢣꢅꢩꢛꢝ
ꢶ
ꢦ
ꢶ
ꢁꢙꢀꢣ
ꢁꢀꢷꢨ
ꢶ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢸꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ
ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ
ꢫꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ
ꢦꢙ
ꢦꢀ
ꢠ
ꢠꢀ
ꢟ
ꢳ
ꢖ
ꢔꢀ
ꢔ
ꢌꢩ
ꢁꢀꢀꢨ
ꢁꢣꢀꢨ
ꢁꢙꢷꢣ
ꢁꢙꢥꢣ
ꢁꢺꢞꢨ
ꢁꢀꢀꢨ
ꢁꢣꢣꢹ
ꢁꢣꢥꢨ
ꢁꢣꢀꢥ
ꢶ
ꢁꢀꢞꢣ
ꢶ
ꢁꢞꢀꢣ
ꢁꢙꢨꢣ
ꢁꢺꢨꢣ
ꢁꢀꢞꢣ
ꢁꢣꢀꢣ
ꢁꢣꢻꢣ
ꢁꢣꢀꢹ
ꢶ
ꢁꢞꢙꢨ
ꢁꢙꢹꢣ
ꢁꢺꢺꢨ
ꢁꢀꢨꢣ
ꢁꢣꢀꢨ
ꢁꢣꢺꢣ
ꢁꢣꢙꢙ
ꢁꢥꢞꢣ
ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ
ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ
ꢝꢙꢋꢄꢊꢞ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
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ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ
ꢩꢛꢝꢪꢅꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢣꢨꢩ
2011 Microchip Technology Inc.
DS21697F-page 31
MCP3302/04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS21697F-page 32
2011 Microchip Technology Inc.
MCP3302/04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS21697F-page 33
MCP3302/04
ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
DS21697F-page 34
2011 Microchip Technology Inc.
MCP3302/04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS21697F-page 35
MCP3302/04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS21697F-page 36
2011 Microchip Technology Inc.
MCP3302/04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS21697F-page 37
MCP3302/04
ꢀꢟꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢅꢉꢇꢐꢑꢂꢃꢌꢑꢄꢇꢒꢈꢓꢇꢔꢇꢕꢖꢖꢇꢗꢌꢉꢇꢘꢙꢆꢚꢇꢛꢈꢎꢐꢈꢜ
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ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
N
NOTE 1
E1
1
2
3
D
E
A
A2
L
c
A1
b1
e
eB
b
ꢯꢄꢃꢏꢇꢰꢱꢝꢲꢠꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ ꢢꢰꢱ
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DS21697F-page 38
2011 Microchip Technology Inc.
MCP3302/04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS21697F-page 39
MCP3302/04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS21697F-page 40
2011 Microchip Technology Inc.
MCP3302/04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS21697F-page 41
MCP3302/04
NOTES:
DS21697F-page 42
2011 Microchip Technology Inc.
MCP3302/04
APPENDIX A: REVISION HISTORY
Revision F (April 2011)
The following is the list of modifications:
1. Updated content to designate that the devices
now have tested specifications in the 4.5V to
5.5V supply range.
2. Removed figures 2.4 to 2.6, 2.10 to 2.12, 2.16
and 2.17 in Section 2.0 “Typical Performance
Curves”.
Revision E (December 2008)
The following is the list of modifications:
Update to Package Outline Drawings.
Revision D (December 2007)
The following is the list of modifications:
Update to Package Outline Drawings.
Revision C (January 2007)
The following is the list of modifications:
Update to Package Outline Drawings.
Revision B (February 2002)
The following is the list of modifications:
Undocumented Changes.
Revision A (November 2001)
Original Release of this Document.
2011 Microchip Technology Inc.
DS21697F-page 43
MCP3302/04
NOTES:
DS21697F-page 44
2011 Microchip Technology Inc.
MCP3302/04
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact the local Microchip sales office.
PART NO.
Device
-X
X
/XX
Examples:
a) MCP3302-BI/P: ±1 LSB INL,
Industrial Temperature,
14-LD PDIP package
b) MCP3302-BI/SL: ±1 LSB INL,
Grade
Temperature
Range
Package
Device
MCP3302: 13-Bit Serial A/D Converter
MCP3302T: 13-Bit Serial A/D Converter (Tape and Reel)
MCP3304: 13-Bit Serial A/D Converter
Industrial Temperature,
14-LD SOIC package
c) MCP3302-CI/ST: ±2 LSB INL,
MCP3304T: 13-Bit Serial A/D Converter (Tape and Reel)
Industrial Temperature,
14-LD TSSOP package
Grade:
B
C
=
=
±1 LSB INL
±2 LSB INL
a) MCP3304-BI/P: ±1 LSB INL,
Industrial Temperature,
16-LD PDIP package
Temperature Range
Package
I
=
-40C to +85C (Industrial)
b) MCP3304-BI/SL: ±1 LSB INL,
Industrial Temperature,
16-LD SOIC package
P
SL
ST
=
=
=
Plastic DIP (300 mil Body), 14-lead, 16-lead
Plastic SOIC (150 mil Body), 14-lead, 16-lead
Plastic TSSOP (4.4mm), 14-lead
2011 Microchip Technology Inc.
DS21697F-page 45
MCP3302/04
NOTES:
DS21697F-page 46
2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-005-9
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2011 Microchip Technology Inc.
DS21697F-page 47
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
Los Angeles
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Toronto
Mississauga, Ontario,
Canada
China - Zhuhai
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-756-3210040
Fax: 86-756-3210049
02/18/11
DS21697F-page 48
2011 Microchip Technology Inc.
相关型号：
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