MCP33131D-05 [MICROCHIP]
1 Msps/500 kSPS 16/14/12-Bit Differential Input SAR ADC;
| 型号： | MCP33131D-05 |
| 厂家： | 
MICROCHIP |
| 描述： | 1 Msps/500 kSPS 16/14/12-Bit Differential Input SAR ADC |
| 文件： | 总59页 (文件大小：3359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP33131D/21D/11D-XX
1 Msps/500 kSPS 16/14/12-Bit Differential Input SAR ADC
Features
Typical Applications
• Sample Rate (Throughput):
• High-Precision Data Acquisition
• Medical Instruments
- MCP33131D/21D/11D-10: 1 Msps
- MCP33131D/21D/11D-05: 500 kSPS
• Test Equipment
• 16/14/12-Bit Resolution with No Missing Codes
• No Latency Output
• Electric Vehicle Battery Management Systems
• Motor Control Applications
• Wide Operating Voltage Range:
- Analog Supply Voltage (AVDD): 1.8V
• Switch-Mode Power Supply Applications
• Battery-Powered Equipment
- Digital Input/Output Interface Voltage (DVIO):
1.7V - 5.5V
System Design Supports
- External Reference (VREF): 2.5V - 5.1V
• Differential Input Operation
The MCP331x1D-XX Evaluation Kit demonstrates the
performance of the MCP331x1D-XX SAR ADC family
devices. The evaluation kit includes: (a) MCP331x1D
Evaluation Board, (b) PIC32MZ EF Curiosity Board for
data collection, and (c) SAR ADC Utility PC GUI.
- Input Full-Scale Range: -VREF to +VREF
• Ultra Low Current Consumption (typical):
- During Input Acquisition (Standby): ~ 0.8 µA
- During Conversion:
Contact Microchip Technology Inc. for the evaluation
tools and the PIC32 MCU firmware example codes.
MCP33131D/21D/11D-10: ~1.6 mA
MCP33131D/21D/11D-05: ~1.4 mA
Package Types
• SPI-Compatible Serial Communication:
- SCLK Clock Rate: up to 100 MHz
VREF
AVDD
1
10 DVIO
9 SDI
• ADC Self-Calibration for Offset, Gain, and
Linearity Errors:
MSOP-10
TDFN-10
2
3
4
5
Top View
AIN+
AIN-
8 SCLK
- During Power-Up (automatic)
SDO
7
- On-Demand via user’s command during
normal operation
GND
6 CNVST
• AEC-Q100 Qualified:
VREF
DV
IO
1
2
10
9
- Temperature Grade 1: -40°C to +125°C
• Package Options: MSOP-10 and TDFN-10
AVDD
AIN+
AIN-
SDI
Top View
SCLK
3
4
5
8
7
6
SDO
CNVST
GND
MCP331x1D-XX Device Offering (Note 1):
Performance (Typical)
Sample
Rate
Input Range
(Differential)
Part Number Resolution
Input Type
SNR
(dBFS)
SFDR
THD
(dB)
INL
DNL
(dB)
(LSB)
(LSB)
MCP33131D-10
MCP33121D-10
MCP33111D-10
MCP33131D-05
MCP33121D-05
MCP33111D-05
16-bit
14-bit
12-bit
16-bit
14-bit
12-bit
1 Msps
1 Msps
1 Msps
Differential
Differential
Differential
±5.1V
±5.1V
±5.1V
±5.1V
±5.1V
±5.1V
91.3
85.1
73.9
91.3
85.1
73.9
103.5
103.5
99.3
-99.3
-99.2
-96.7
-99.3
-99.2
-96.7
±2
±0.5
±0.12
±2
±0.8
±0.25
±0.06
±0.8
500 kSPS Differential
500 kSPS Differential
500 kSPS Differential
103.5
103.5
99.3
±0.5
±0.12
±0.25
±0.06
Note 1: SNR, SFDR, and THD are measured with fIN = 10 kHz, VIN = -1 dBFS, VREF = 5.1V.
2018 Microchip Technology Inc.
DS20005947B-page 1
MCP33131D/MCP33121D/MCP33111D-XX
Application Diagram
1.8V to 5.5V
2.5V to 5.1V 1.8V
V
DV
IO
AV
REF
DD
22Ω
1.7 nF
22Ω
1.7 nF
A
+
IN
0V to V
REF
REF
SDI
MCP331x1D-XX
Host Device
CNVST
SCLK
SDO
(PIC32MZ)
A
-
IN
0V to V
GND
During Standby, most of the internal analog circuitry is
shutdown in order to reduce current consumption.
Typically, the device consumes less than 1 µA during
Standby. A new conversion is started on the rising edge
of CNVST. When the conversion is complete and the
host lowers CNVST, the output data is presented on
SDO, and the device enters Standby to begin acquiring
the next input sample. The user can clock out the ADC
output data using the SPI-compatible serial clock
during Standby.
Description
The MCP33131D/MCP33121D/MCP33111D-10 and
MCP33131D/MCP33121D/MCP33111D-05 are
fully-differential 16, 14, and 12-bit, single-channel
1 Msps and 500 kSPS ADC family devices,
respectively, featuring low power consumption and
high performance, using a successive approximation
register (SAR) architecture.
The device operates with a 2.5V to 5.1V external
reference (VREF), which supports a wide range of input
full-scale range from -VREF to +VREF. The reference
voltage setting is independent of the analog supply
voltage (AVDD
conversion output is available through an easy-to-use
simple SPI- compatible 3-wire interface.
The ADC system clock is generated by the internal
on-chip clock, therefore the conversion is performed
independent of the SPI serial clock (SCLK).
) and is higher than AVDD. The
This device can be used for various high-speed and
high-accuracy analog-to-digital data conversion
applications, where design simplicity, low power, and
no output latency are needed.
The device requires a 1.8V analog supply voltage
(AVDD) and a 1.7V to 5.5V digital I/O interface supply
voltage (DVIO). The wide digital I/O interface supply
(DVIO) range (1.7V – 5.5V) allows the device to
interface with most host devices (Master) available in
the current industry such as the PIC32
microcontrollers, without using external voltage level
shifters.
The device is AEC-Q100 qualified for automotive appli-
cations and operates over the extended temperature
range of -40°C to +125°C. The available package
options are Pb-free small 3 mm x 3 mm TDFN-10 and
MSOP-10.
When the device is first powered-up, it performs a
self-calibration to minimize offset, gain and linearity
errors. The device performance stays stable across the
specified temperature range. However, when extreme
changes in the operating environment, such as in the
reference voltage, are made with respect to the initial
conditions (e.g. the reference voltage was not fully
settled during the initial power-up sequence), the user
may send a recalibrate command anytime to initiate
another
self-calibration
to
restore
optimum
performance.
When the initial power-up sequence is completed, the
device enters a low-current input acquisition mode,
where sampling capacitors are connected to the input
pins. This mode is called Standby.
DS20005947B-page 2
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
†Notice: Stresses above those listed under “Absolute
1.0
1.1
KEY ELECTRICAL
Maximum Ratings” may cause permanent damage to the
CHARACTERISTICS
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
Absolute Maximum Ratings†
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
External Analog Supply Voltage (AVDD)............. -0.3V to 2.0V
External Digital Supply Voltage (DVIO)............... -0.3V to 5.8V
External Reference Voltage (VREF).................... -0.3V to 5.8V
Analog Inputs w.r.t GND ......................... -0.3V to VREF+0.3V
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ..........................±250 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD protection on all pins .... ≤2kV HBM, ≤200V MM, ≤2kV CDM
periods may affect device reliability.
1.2
Electrical Specifications
TABLE 1-1:
KEY ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF
IN
IN
LOAD_SDO
•
•
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Power Supply Requirements
Analog Supply Voltage Range
AV
1.7
1.7
1.8
—
1.9
5.5
V
V
(Note 3)
(Note 3)
DD
Digital Input/Output Interface Voltage
Range
DV
IO
Analog Supply Current at AV pin:
DD
During Conversion
I
—
—
—
1.6
1.4
0.8
2.4
2.0
—
mA
mA
µA
f
f
= 1 Msps (MCP331x1D-10)
= 500 kSPS (MCP331x1D-05)
DDAN
s
s
During Standby
I
During input acquisition (t
)
DDAN_STBY
ACQ
Digital Supply Current At DV pin:
DD
During Output Data Reading
I
—
—
—
290
200
30
—
—
—
A
A
nA
f
f
= 1 Msps (MCP331x1D-10)
= 500 kSPS (MCP331x1D-05)
IO_DATA
s
s
During Standby
I
During input acquisition (t
)
IO_STBY
ACQ
External Reference Voltage Input
Reference Voltage
(Note 2), (Note 3)
V
2.5
2.7
5.1
5.1
V
-40°C ≤ T ≤ 85°C
A
REF
85°C < T ≤ 125°C
A
Reference Load Current at V
During Conversion
pin:
REF
I
—
—
450
220
240
600
360
—
µA
µA
nA
f
f
= 1 Msps (MCP331x1D-10)
= 500 kSPS (MCP331x1D-05)
REF
s
s
During Standby
I
During input acquisition (t
)
REF_STBY
ACQ
Total Power Consumption (Including AVDD, DVIO, VREF pins)
MCP331x1D-10
at 1 Msps
P
—
—
—
—
6.2
3.1
0.6
2.6
—
—
—
—
mW
mW
mW
W
Averaged power for t
+ t
ACQ
DISS_TOTAL
CNV
at 500 kSPS
at 100 kSPS
During Standby
P
During input acquisition (t
)
DISS_STBY
ACQ
MCP331x1D-05
at 500 kSPS
at 100 kSPS
During Standby
P
—
—
—
4.2
0.8
2.6
—
—
—
mW
mW
W
Averaged power for t
+ t
ACQ
DISS_TOTAL
CNV
P
During input acquisition (t
)
DISS_STBY
ACQ
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AV pin: 1 F ceramic capacitor, (b) DV pin: 0.1 F ceramic capacitor, (c) V pin: 10 F tantalum capacitor.
REF
DD
IO
4: Differential Input Full-Scale Range (FSR) = 2 x V
REF
5: PSRR (dB) = -20 log (D
/AV ), where D
= change in conversion result.
VOUT
VOUT
DD
6: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc.
DS20005947B-page 3
MCP33131D/MCP33121D/MCP33111D-XX
TABLE 1-1:
KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF
IN
IN
LOAD_SDO
•
•
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Analog Inputs
Input Voltage Range
(Note 2)
V
-0.1
-0.1
—
—
—
V
V
+0.1
+0.1
V
V
Differential Input:
= (V - V )
IN-
IN+
REF
REF
V
IN
IN+
V
IN-
Input Full-Scale Voltage Range
Input Common-Mode Voltage Range
Input Sampling Capacitance
-3dB Input Bandwidth
FSR
-V
+V
V
PP
Differential Input (Note 2), (Note 4)
REF
REF
V
0
V
/2
V
(Note 2)
(Note 1)
(Note 1)
CM
REF
31
REF
C
—
—
—
—
pF
S
BW
25
—
MHz
ns
-3dB
Aperture Delay
(Note 1)
2.5
—
Time delay between CNVST rising
edge and when input is sampled
Leakage Current at Analog Input Pin
I
—
±2
±200
nA
During input acquisition (t
)
ACQ
LEAK_AN_INPUT
System Performance
Sample Rate
(Throughput rate)
f
—
—
—
—
—
—
—
±2
1
500
—
Msps
kSPS
Bits
MCP331x1D-10
MCP331x1D-05
s
Resolution
(No Missing Codes)
16
14
12
-6
MCP33131D-10 and MCP33131D-05
MCP33121D-10 and MCP33121D-05
MCP33111D-10 and MCP33111D-05
MCP33131D-10 and MCP33131D-05
MCP33121D-10 and MCP33121D-05
MCP33111D-10 and MCP33111D-05
MCP33131D-10 and MCP33131D-05
MCP33121D-10 and MCP33121D-05
MCP33111D-10 and MCP33111D-05
MCP33131D-10 and MCP33131D-05
MCP33121D-10 and MCP33121D-05
MCP33111D-10 and MCP33111D-05
—
Bits
—
Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
+6
LSB
LSB
LSB
LSB
LSB
LSB
mV
-1.5
±0.5
±0.12
±0.8
±0.25
±0.06
±0.1
±0.125
±0.8
±0.8
±2
+1.5
DNL
-0.98
-0.8
+1.8
+0.8
+0.3
±2.3
±3
-0.3
—
—
—
—
—
—
—
—
—
mV
±3.66
—
mV
o
Offset Error Drift with Temperature
Gain Error
V/ C
G
—
LSB
LSB
LSB
MCP33131D-10 and MCP33131D-05
MCP33121D-10 and MCP33121D-05
MCP33111D-10 and MCP33111D-05
ER
±0.5
±0.1
±0.35
84
—
—
o
Gain Error Drift with temperature
Input common-mode rejection ratio
Power Supply Rejection Ratio
—
V/ C
CMRR
PSRR
—
dB
dB
70
—
(Note 5)
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AV pin: 1 F ceramic capacitor, (b) DV pin: 0.1 F ceramic capacitor, (c) V pin: 10 F tantalum capacitor.
REF
DD
IO
4: Differential Input Full-Scale Range (FSR) = 2 x V
REF
5: PSRR (dB) = -20 log (D
/AV ), where D
= change in conversion result.
VOUT
VOUT
DD
6: ENOB = (SINAD - 1.76)/6.02
DS20005947B-page 4
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
TABLE 1-1:
KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF
IN
IN
LOAD_SDO
•
•
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Dynamic Performance
Signal-to-Noise Ratio
SNR
MCP33131D-10 and MCP33131D-05: 16-bit ADC
—
—
91.6
86.6
91.3
86.6
—
—
—
—
dBFS
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
88.7
—
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
MCP33121D-10 and MCP33121D-05: 14-bit ADC
—
—
85.2
83.5
85.1
83.5
—
—
—
—
dBFS
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
81.7
—
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
MCP33111D-10 and MCP33111D-05: 12-bit ADC
—
—
73.9
73.8
73.9
73.8
—
—
—
—
dBFS
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
71.1
—
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
Signal-to-Noise and Distortion Ratio
SINAD
MCP33131D-10 and MCP33131D-05: 16-bit ADC
(Note 6)
—
—
—
—
91.5
86.6
91
—
—
—
—
dBFS
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
= 5V, f = 10 kHz
IN
86.2
= 2.5V, f = 10 kHz
IN
MCP33121D-10 and MCP33121D-05: 14-bit ADC
—
—
—
—
85.2
83.5
85
—
—
—
—
dBFS
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
= 5V, f = 10 kHz
IN
83.3
= 2.5V, f = 10 kHz
IN
MCP33111D-10 and MCP33111D-05: 12-bit ADC
—
—
—
—
73.9
73.8
73.9
73.8
—
—
—
—
dBFS
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AV pin: 1 F ceramic capacitor, (b) DV pin: 0.1 F ceramic capacitor, (c) V pin: 10 F tantalum capacitor.
REF
DD
IO
4: Differential Input Full-Scale Range (FSR) = 2 x V
REF
5: PSRR (dB) = -20 log (D
/AV ), where D
= change in conversion result.
VOUT
VOUT
DD
6: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc.
DS20005947B-page 5
MCP33131D/MCP33121D/MCP33111D-XX
TABLE 1-1:
KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF
IN
IN
LOAD_SDO
•
•
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Spurious Free Dynamic Range
SFDR
MCP33131D-10 and MCP33131D-05: 16-bit ADC
—
—
—
—
103.7
98
—
—
—
—
dBc
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
103.5
97.5
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
MCP33121D-10 and MCP33121D-05: 14-bit ADC
—
—
—
—
103.6
98
—
—
—
—
dBc
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
103.5
97.4
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
MCP33111D-10 and MCP33111D-05: 12-bit ADC
—
—
—
—
99.3
97.7
99.3
97.2
—
—
—
—
dBc
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
Total Harmonic Distortion
(first five harmonics)
THD
MCP33131D-10 and MCP33131D-05: 16-bit ADC
—
—
—
—
-100.4
-95.4
-99.3
-95.4
—
—
—
—
dBc
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
MCP33121D-10 and MCP33121D-05: 14-bit ADC
—
—
—
—
-100.1
-95.3
-99.2
-95.3
—
—
—
—
dBc
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
MCP33111D-10 and MCP33111D-05: 12-bit ADC
—
—
—
—
-97.5
-94.4
-96.7
-94.4
—
—
—
—
dBc
V
V
V
V
= 5V, f = 1 kHz
IN
REF
REF
REF
REF
= 2.5V, f = 1 kHz
IN
= 5V, f = 10 kHz
IN
= 2.5V, f = 10 kHz
IN
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AV pin: 1 F ceramic capacitor, (b) DV pin: 0.1 F ceramic capacitor, (c) V pin: 10 F tantalum capacitor.
REF
DD
IO
4: Differential Input Full-Scale Range (FSR) = 2 x V
REF
5: PSRR (dB) = -20 log (D
/AV ), where D
= change in conversion result.
VOUT
VOUT
DD
6: ENOB = (SINAD - 1.76)/6.02
DS20005947B-page 6
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
TABLE 1-1:
KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF
IN
IN
LOAD_SDO
•
•
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
System Self-Calibration
Self-Calibration Time
t
—
—
500
650
—
ms
(Note 2)
Includes clocks for data bits
CAL
Number of SCLK Clocks for
Recalibrate Command
ReCal
1024
clocks
NSCLK
Serial Interface Timing Information: See Table 1-2
Digital Inputs/Outputs
High-level Input voltage
Low-level input voltage
V
0.7 * DV
0.9 * DV
-0.3
—
—
DV + 0.3
V
V
DV ≥ 2.3V
IO
IH
IO
IO
DV + 0.3
DV < 2.3V
IO
IO
IO
V
—
0.3 * DV
0.2 * DV
—
V
DV ≥ 2.3V
IO
IL
IO
IO
-0.3
—
V
DV < 2.3V
IO
Hysteresis of Schmitt Trigger Inputs
Low-level output voltage
High-level output voltage
Input leakage current
V
—
0.2 * DV
—
V
All digital inputs
HYST
IO
V
—
0.2 * DV
—
V
I
= 500 µA (sink)
OL
IO
OL
OL
V
I
0.8 * DV
—
—
V
I
= - 500 µA (source)
OH
IO
I
—
±1
µA
µA
CNVST/SDI/SCLK = GND or DV
Output is high-Z, SDO = GND or
LI
IO
Output leakage current
—
—
±1
LO
DV
IO
Internal capacitance
C
—
7
—
pF
T
= 25°C (Note 1)
INT
A
(all digital inputs and outputs)
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AV pin: 1 F ceramic capacitor, (b) DV pin: 0.1 F ceramic capacitor, (c) V
pin: 10 F tantalum capacitor.
DD
IO
REF
4: Differential Input Full-Scale Range (FSR) = 2 x V
REF
5: PSRR (dB) = -20 log (D
/AV ), where D
= change in conversion result.
VOUT
VOUT
DD
6: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc.
DS20005947B-page 7
MCP33131D/MCP33121D/MCP33111D-XX
TABLE 1-2:
SERIAL INTERFACE TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF. +25°C is applied for typical value. All timings are
IN
IN
LOAD_SDO
measured at 50%. See Figure 1-1 for timing diagram.
•
•
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Serial Clock frequency
SCLK Period
f
—
10
12
16
3
—
—
—
—
—
—
—
—
—
—
—
—
100
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See t
specification
SCLK
SCLK
SCLK
t
DV ≥ 3.3V, f
= 100 MHz (Max)
= 83.3 MHz (Max)
= 62.5 MHz (Max)
IO
SCLK
SCLK
SCLK
—
DV ≥ 2.3V, f
IO
—
DV ≥ 1.7V, f
IO
SCLK Low Time
t
—
DV ≥ 2.3V
SCLK_L
IO
4.5
3
—
DV ≥ 1.7V
IO
SCLK High Time
t
—
DV ≥ 2.3V
SCLK_H
IO
4.5
—
—
—
10
—
DV ≥ 1.7V
IO
Output Valid from SCLK Low
t
9.5
12
16
—
DV ≥ 3.3V
IO
DO
DV ≥ 2.3V
IO
DV ≥ 1.7V
IO
Quiet time
t
(Note 2)
QUIET
3-Wire Operation:
SDI Valid Setup time
CNVST Pulse Width High Time
Output Enable Time
t
5
—
—
—
—
—
—
—
10
15
15
ns
ns
ns
ns
ns
SDI High to CNVST Rising Edge
SU_SDIH_CNV
t
10
—
—
—
CNVH
t
DV ≥ 2.3V
IO
EN
DV ≥ 1.7V
IO
Output Disable Time
MCP331x1D-10
Sample Rate
t
(Note 2)
DIS
f
—
—
1
Msps Throughput rate
s
Input Acquisition Time
(Note 2)
t
290
250
300
—
—
ns
ns
µs
-40°C ≤ T ≤ 85°C
A
ACQ
85°C < T ≤ 125°C
A
Data Conversion Time
t
—
—
700
—
710
750
-40°C ≤ T ≤ 85°C
A
CNV
CYC
85°C < T ≤ 125°C
A
Time between Conversions
MCP331x1D-05
t
1
—
t
= t
+ t
, f = 1 Msps
CYC
ACQ
CNV S
Sample Rate
f
—
700
—
—
800
1200
—
500
—
kSPS Throughput rate
s
Input Acquisition Time (Note 2)
Data Conversion Time
Time between Conversions
t
ns
ns
µs
-40°C ≤ T ≤ 125°C
A
ACQ
t
1300
—
-40°C ≤ T ≤ 125°C
A
CNV
CYC
t
2
t
= t
+ t
, f = 500 kSPS
CYC
ACQ
CNV S
Note 1:
2:
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
TABLE 1-3:
TEMPERATURE CHARACTERISTICS
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Temperature Ranges
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistance
Thermal Resistance, MSOP-10
Thermal Resistance, TDFN-10
T
-40
-65
—
—
+125
+150
°C
°C
(Note 1)
(Note 1)
A
T
A
—
—
202
68
—
—
°C/W
°C/W
JA
JA
o
Note 1:
The internal junction temperature (T ) must not exceed the absolute maximum specification of +150 C.
j
DS20005947B-page 8
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
tCYC
= 1/fS
SDI = “High”
t
CNVH
t
SU_SDIH_CNV
CNVST
t
SCLK
(Note 1)
1
n
3
n-1
2
SCLK
t
t
DO
QUIET
t
t
SCLK_L
SCLK_H
t
DIS
Hi-Z
(MAX)
D
(MSB)
Hi-Z
n-1
SDO
D
1
D
0
D
D
n-2
n-3
t
CNV
t
EN
(Note 2)
(Note 3)
t
EN
ADC State
Input Acquisition
Conversion
Input Acquisition
(t
)
(t
)
(t
)
ACQ
CNV
ACQ
Note 1: n = 16 for 16-bit, 14 for 14-bit device, and 12 for 12-bit device.
2: t when CNVST is lowered after t (MAX).
EN
CNV
3: t when CNVST is lowered before t
(MAX).
EN
CNV
FIGURE 1-1:
Interface Timing Diagram. CNVST is used as chip select. See Figure 7-2 for more
details.
2018 Microchip Technology Inc.
DS20005947B-page 9
MCP33131D/MCP33121D/MCP33111D-XX
NOTES:
DS20005947B-page 10
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
2.0
TYPICAL PERFORMANCE CURVES FOR 16-BIT DEVICES (MCP33131D-XX)
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
2
1
3
V
= 5V
V
= 2.5V
REF
REF
2
1
0
0
-1
-2
-3
-1
-2
0
16,384
32,768
Code
49,152
65,536
0
16,384
32,768
Code
49,152
65,536
FIGURE 2-1:
INL vs. Output Code.
FIGURE 2-4:
INL vs. Output Code.
1
0.5
0
1
0.5
0
V
= 2.5V
V
= 5V
REF
REF
-0.5
-0.5
-1
0
-1
0
16,384
32,768
Code
49,152
65,536
16,384
32,768
Code
49,152
65,536
FIGURE 2-2:
DNL vs. Output Code.
FIGURE 2-5:
DNL vs. Output Code.
1
0.5
0
3
2
Max DNL (LSB)
Max INL (LSB)
1
V
= 5V
V
= 5V
0
REF
REF
-1
-2
-0.5
Min INL (LSB)
Min DNL (LSB)
-1
-3
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 2-3:
INL vs. Temperature.
FIGURE 2-6:
DNL vs. Temperature.
2017 Microchip Technology Inc.
DS20005947B-page 11
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
4
3
1
Max INL (LSB)
Max DNL (LSB)
0.5
2
1
0
0
-1
-2
-3
-0.5
Min DNL (LSB)
Min INL (LSB)
-4
2
-1
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 2-7:
INL vs. Reference Voltage.
FIGURE 2-10:
DNL vs. Reference Voltage.
MCP33131D-10
MCP33131D-10
0
0
V
= 5V
V
= 2.5V
REF
REF
-20
-40
f = 1 Msps
s
-20
-40
f = 1 Msps
s
SNR = 91.5 dBFS
SINAD = 91.3 dBFS
SFDR = 108.5 dBc
THD = -102.2 dBc
Offset = 1 LSB
SNR = 86.7 dBFS
SINAD = 86.2 dBFS
SFDR = 97.4 dBc
THD = -95.6 dBc
Offset = -2 LSB
-60
-60
-80
-80
Resolution = 16-bit
Resolution = 16-bit
-100
-120
-140
-160
-100
-120
-140
-160
0
100
200
300
400
500
0
100
200
300
400
500
Frequency (kHz)
Frequency (kHz)
FIGURE 2-8:
FFT for 10 kHz Input Signal:
= 5V.
FIGURE 2-11:
FFT for 10 kHz Input Signal:
= 2.5V.
f = 1 Msps, V = -1 dBFS, V
f = 1 Msps, V = -1 dBFS, V
S
IN
REF
S
IN
REF
MCP33131D-05
MCP33131D-05
0
-20
0
-20
V
= 5V
V
= 2.5V
REF
REF
f
= 0.5 Msps
f
= 0.5 Msps
s
s
SNR = 91.5 dBFS
SINAD = 91.3 dBFS
SFDR = 108.0 dBc
THD = -102.5 dBc
Offset = 1 LSB
SNR = 86.9 dBFS
SINAD = 86.5 dBFS
SFDR = 97.2 dBc
THD = -95.6 dBc
Offset = -2 LSB
-40
-40
-60
-60
-80
-80
Resolution = 16-bit
Resolution = 16-bit
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
FIGURE 2-9:
FFT for 10 kHz Input Signal:
= 5V.
FIGURE 2-12:
f = 500 kSPS, V = -1 dBFS, V
REF
FFT for 10 kHz Input Signal:
f = 500 kSPS, V = -1 dBFS, V
= 2.5V.
S
IN
REF
S
IN
DS20005947B-page 12
2017 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
95
92.5
90
15.5
14.5
13.5
12.5
-92
-95
107
102
97
THD (dB)
87.5
85
SFDR (dB)
-98
ENOB
82.5
SNR (dB)
SINAD (dB)
80
2
-101
92
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 2-13:
SNR/SINAD/ENOB vs. VREF
FIGURE 2-16:
SFDR/THD vs. V
REF
87
86
85
84
90.6
90.4
90.2
90
V
= 2.5V
V
= 5V
REF
REF
SNR (dB)
SNR (dB)
SINAD (dB)
89.8
SINAD (dB)
83
89.6
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 2-17:
Temperature: V
SNR/SINAD vs.
= 2.5V.
FIGURE 2-14:
Temperature: V
SNR/SINAD vs.
= 5V.
REF
REF
90
89
88
87
86
85
84
83
95
93
91
89
V
= 2.5V
V
= 5V
REF
REF
SNR (dBFS)
SINAD(dBFS)
SNR (dBFS)
SINAD(dBFS)
82
81
80
87
85
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 2-18:
SNR/SINAD vs. Input
FIGURE 2-15:
SNR/SINAD vs. Input
Amplitude: F = 10 kHz.
Amplitude: F = 10 kHz.
IN
IN
2017 Microchip Technology Inc.
DS20005947B-page 13
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
95
90
85
80
75
70
95
V
= 5V
V
= 2.5V
REF
REF
90
85
80
75
70
SNR (dB)
SNR (dB)
SINAD (dB)
SINAD (dB)
100
101
102
103
100
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-19:
SNR/SINAD vs.Input
FIGURE 2-22:
SNR/SINAD vs.Input
Frequency: V = -1 dBFS.
Frequency: V = -1 dBFS.
IN
IN
-92
100
-92
106
THD (dB)
THD (dB)
SFDR (dB)
SFDR (dB)
-93
99
98
97
96
95
94
-94
-96
104
102
100
98
-94
V
= 2.5V
V
= 5V
-95
-96
-97
-98
REF
REF
-98
-100
-102
96
-40 -20
0
20 40 60 80 100 120 140
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
Temperature (oC)
FIGURE 2-20:
THD/SFDR vs.
FIGURE 2-23:
THD/SFDR vs.
Temperature: V
= 5V.
Temperature: V
= 2.5V.
REF
REF
-75
-80
110
105
100
95
-75
-80
110
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-85
-85
-90
-90
-95
90
-95
90
-100
-105
85
-100
-105
85
80
80
V
= 5V
V
= 2.5V
REF
REF
-110
100
75
-110
100
75
101
102
103
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-21:
THD/SFDR vs. Input
= 5V.
FIGURE 2-24:
THD/SFDR vs. Input
= 2.5V.
Frequency: V
Frequency: V
REF
REF
DS20005947B-page 14
2017 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
-65
-70
110
105
100
95
-65
-70
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-75
-75
-80
-80
90
V
= 5V
V
= 2.5V
-85
90
-85
85
REF
REF
-90
85
-90
80
-95
80
-95
75
-100
-105
75
-100
-105
70
65
70
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 2-25:
THD/SFDR vs. Input
= 5V.
FIGURE 2-28:
Amplitude: V
THD/SFDR vs. Input
= 2.5V.
REF
Amplitude: V
REF
ꢀ105
ꢀ105
8
6
V
= 2.5V
665631
REF
V
= 5V
485575
REF
5
4
3
2
1
0
6
4
2
0
242712
83720
125959
165598
134228
63608
13523
73
32905
490
41867
33
41102
117
10
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
-10-9 -8 -7 -6 -5 -4 -3 -2 -1 0
Output Code
1 2 3 4 5 6
Output Code
FIGURE 2-26:
= 5V.
Shorted Input Histogram:
FIGURE 2-29:
V = 2.5V.
REF
Shorted Input Histogram:
V
REF
600
3.9
3.3
2.6
400
5.2
3.9
2.6
1.3
0
500
400
300
200
100
0
300
200
100
0
Gain Error
2
1.3
0.66
0
Gain Error
-100
-200
-300
-1.3
Offset Error
V
= 5V
V
= 2.5V
-2.6
REF
REF
Offset Error
-100
-0.66
-3.9
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 2-27:
Offset and Gain Error vs.
FIGURE 2-30:
Offset and Gain Error vs.
Temperature: V
= 5V.
Temperature: V
= 2.5V.
REF
REF
2017 Microchip Technology Inc.
DS20005947B-page 15
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
86
84
82
80
78
76
8
16
12
8
VREF = 5V
6
Total Power Consumption
4
IIO_STBY (DVIO = 3.3V)
2
4
IREF_STBY (VREF = 5V)
0
0
74
10-3
10-2
10-1
Input Frequency (kHz)
100
101
102
103
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-31:
= 5V.
CMRR vs. Input Frequency:
FIGURE 2-34:
Temperature during Shutdown.
Power Consumption vs.
V
REF
2
8
6
4
2
0
2
8
6
4
2
0
MCP331x1D-05
MCP331x1D-10
1.5
1
1.5
1
0.5
0
0.5
0
0.1
0.2
0.3
0.4
0.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Sample Rate (Msps)
1
Sample Rate (Msps)
FIGURE 2-32:
Sample Rate: C
Power Consumption vs.
= 20 pF.
FIGURE 2-35:
Sample Rate: CLOAD_SDO = 20 pF.
Power Consumption vs.
LOAD_SDO
2.5
10
8
2
8
6
4
2
0
MCP331x1D-10
MCP331x1D-05
2
1.5
1
1.5
1
6
4
IREF (VREF = 5V)
0.5
2
0.5
IREF (VREF = 5V)
IIO_DATA (DVIO = 3.3V)
IIO_DATA (DVIO = 3.3V)
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-33:
Temperature: C
Power Consumption vs.
FIGURE 2-36:
Temperature: CLOAD_SDO = 20 pF.
Power Consumption vs.
= 20 pF.
LOAD_SDO
DS20005947B-page 16
2017 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
3.0
TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33121D-XX)
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
1
0.5
0
1
V
= 5V
V
= 2.5V
REF
REF
0.5
0
-0.5
-0.5
-1
-1
0
4,096
8,192
Code
12,288
16,384
0
4,096
8,192
Code
12,288
16,384
FIGURE 3-1:
INL vs. Output Code.
FIGURE 3-4:
INL vs. Output Code.
1
0.5
0
1
0.5
0
V
= 5V
V
= 2.5V
REF
REF
-0.5
-0.5
-1
0
-1
0
4,096
8,192
Code
12,288
16,384
4,096
8,192
Code
12,288
16,384
FIGURE 3-2:
DNL vs. Output Code.
FIGURE 3-5:
DNL vs. Output Code.
1
0.5
0
1
0.5
0
Max INL (LSB)
Max DNL (LSB)
V
= 5V
V
= 5V
REF
REF
-0.5
-0.5
Min INL (LSB)
Min DNL (LSB)
-1
-1
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 3-3:
INL vs. Temperature.
FIGURE 3-6:
DNL vs. Temperature.
2017 Microchip Technology Inc.
DS20005947B-page 17
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
1
1
0.5
0
Max INL (LSB)
0.5
0
Max DNL (LSB)
-0.5
-1
-0.5
-1
Min DNL (LSB)
Min INL (LSB)
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 3-7:
INL vs. Reference Voltage.
FIGURE 3-10:
DNL vs. Reference Voltage.
MCP33121D-10
MCP33121D-10
0
0
V
= 2.5V
V
= 5V
REF
REF
f = 1 Msps
s
-20
-40
f = 1 Msps
s
-20
-40
SNR = 83.4 dBFS
SINAD = 83.2 dBFS
SFDR = 96.9 dBc
THD = -95.4 dBc
Offset = -1 LSB
SNR = 85.2 dBFS
SINAD = 85.2 dBFS
SFDR = 106.9 dBc
THD = -100.2 dBc
Offset = 0 LSB
-60
-60
-80
-80
Resolution = 14-bit
Resolution = 14-bit
-100
-120
-140
-160
-100
-120
-140
-160
0
100
200
300
400
500
0
100
200
300
400
500
Frequency (kHz)
Frequency (kHz)
FIGURE 3-8:
FFT for 10 kHz Input Signal:
= 5V.
FIGURE 3-11:
FFT for 10 kHz Input Signal:
= 2.5V.
f = 1 Msps, V = -1 dBFS, V
f = 1 Msps, V = -1 dBFS, V
S
IN
REF
S
IN
REF
MCP33121D-05
MCP33121D-05
0
-20
0
-20
V
= 2.5V
V
= 5V
REF
REF
f
= 0.5 Msps
f
= 0.5 Msps
s
s
SNR = 83.6 dBFS
SINAD = 83.4 dBFS
SFDR = 97.3 dBc
THD = -95.5 dBc
Offset = -1 LSB
SNR = 85.1 dBFS
SINAD = 85.1 dBFS
SFDR = 107.9 dBc
THD = -102.1 dBc
Offset = 0 LSB
-40
-40
-60
-60
-80
-80
Resolution = 14-bit
Resolution = 14-bit
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
FIGURE 3-9:
FFT for 10 kHz Input Signal:
= 5V.
FIGURE 3-12:
f = 500 kSPS, V = -1 dBFS, V
REF
FFT for 10 kHz Input Signal:
f = 500 kSPS, V = -1 dBFS, V
= 2.5V.
S
IN
REF
S
IN
DS20005947B-page 18
2017 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
-92
-95
107
102
97
86
85
84
83
82
81
14.5
13.5
12.5
11.5
THD (dB)
SFDR (dB)
-98
ENOB
SNR (dB)
SINAD (dB)
-101
92
80
2
2
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 3-13:
SNR/SINAD/ENOB vs. VREF
FIGURE 3-16:
SFDR/THD vs. V
REF
83
82.5
82
84.6
84.4
84.2
84
V
= 2.5V
V
= 5V
REF
REF
SNR (dB)
81.5
SNR (dB)
SINAD (dB)
83.8
SINAD (dB)
81
83.6
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 3-17:
Temperature: V
SNR/SINAD vs.
= 2.5V.
FIGURE 3-14:
Temperature: V
SNR/SINAD vs.
= 5V.
REF
REF
88
86
84
82
88
86
84
82
V
= 5V
V
= 2.5V
REF
REF
SNR (dBFS)
SINAD(dBFS)
SNR (dBFS)
SINAD(dBFS)
80
78
80
78
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 3-18:
SNR/SINAD vs. Input
FIGURE 3-15:
SNR/SINAD vs. Input
Amplitude: F = 10 kHz.
Amplitude: F = 10 kHz.
IN
IN
2017 Microchip Technology Inc.
DS20005947B-page 19
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
90
85
80
75
70
65
90
V
= 5V
V
= 2.5V
REF
REF
85
80
75
70
65
SNR (dB)
SNR (dB)
SINAD (dB)
SINAD (dB)
100
101
102
103
100
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 3-19:
SNR/SINAD vs.Input
FIGURE 3-22:
SNR/SINAD vs.Input
Frequency: V = -1 dBFS.
Frequency: V = -1 dBFS.
IN
IN
-92
106
104
102
100
98
-92
100
98
SFDR (dB)
THD (dB)
THD (dB)
SFDR (dB)
-94
-96
-94
V
= 5V
V
= 2.5V
REF
REF
-98
-96
96
-100
-102
96
-98
94
-40 -20
0
20 40 60 80 100 120 140
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
o
Temperature ( C)
FIGURE 3-20:
THD/SFDR vs.
FIGURE 3-23:
THD/SFDR vs.
Temperature: V
= 5V.
Temperature: V
= 2.5V.
REF
REF
-75
-80
110
105
100
95
-75
-80
110
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-85
-85
-90
-90
-95
90
-95
90
-100
-105
85
-100
-105
85
80
80
V
= 2.5V
V
= 5V
REF
REF
-110
100
75
-110
100
75
101
102
103
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 3-21:
THD/SFDR vs. Input
= 5V.
FIGURE 3-24:
THD/SFDR vs. Input
= 2.5V.
Frequency: V
Frequency: V
REF
REF
DS20005947B-page 20
2017 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
-65
-70
110
105
100
95
-65
-70
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-75
-75
-80
-80
90
V
= 5V
V
= 2.5V
-85
90
-85
85
REF
REF
-90
85
-90
80
-95
80
-95
75
-100
-105
75
-100
-105
70
70
65
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 3-25:
THD/SFDR vs. Input
= 5V.
FIGURE 3-28:
Amplitude: V
THD/SFDR vs. Input
= 2.5V.
REF
Amplitude: V
REF
ꢀ105
ꢀ105
10
10
872448
V
= 5V
V
= 2.5V
844912
REF
REF
8
6
4
2
8
6
4
2
0
203163
176128
501
0
-3
-2
-1
0
1
2
3
-4
-3
-2
-1
0
1
2
3
Output Code
Output Code
FIGURE 3-26:
= 5V.
Shorted Input Histogram:
FIGURE 3-29:
V = 2.5V.
REF
Shorted Input Histogram:
V
REF
300
0.98
0.66
0.33
0
500
0.82
0.66
0.49
200
100
0
400
300
200
100
0
Gain Error
0.33
0.16
0
Gain Error
-100
-200
-300
-400
-0.33
-0.66
-0.98
-1.3
Offset Error
Offset Error
V
= 2.5V
REF
V
= 5V
-100
-200
-0.16
-0.33
REF
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 3-30:
Temperature: V
Offset and Gain Error vs.
= 2.5V.
FIGURE 3-27:
Temperature: V
Offset and Gain Error vs.
= 5V.
REF
REF
2017 Microchip Technology Inc.
DS20005947B-page 21
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
86
84
82
80
78
76
8
16
12
8
VREF = 5V
6
Total Power Consumption
4
IIO_STBY (DVIO = 3.3V)
2
4
IREF_STBY (VREF = 5V)
74
0
0
10-3
10-2
10-1
100
101
102
103
-40 -25 -10
5
20 35 50 65 80 95 110 125
Input Frequency (kHz)
Temperature (°C)
FIGURE 3-31:
= 5V.
CMRR vs. Input Frequency:
FIGURE 3-34:
Temperature during Shutdown.
Power Consumption vs.
V
REF
2
8
6
4
2
0
2
8
6
4
2
0
MCP331x1D-10
MCP331x1D-05
1.5
1
1.5
1
0.5
0
0.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Sample Rate (Msps)
1
0.1
0.2
0.3
0.4
0.5
Sample Rate (Msps)
FIGURE 3-32:
Sample Rate: C
Power Consumption vs.
= 20 pF.
FIGURE 3-35:
Sample Rate: CLOAD_SDO = 20 pF.
Power Consumption vs.
LOAD_SDO
2.5
10
8
2
8
6
4
2
0
MCP331x1D-10
MCP331x1D-05
2
1.5
1
1.5
1
6
4
IREF (VREF = 5V)
0.5
2
0.5
IREF (VREF = 5V)
IIO_DATA (DVIO = 3.3V)
IIO_DATA (DVIO = 3.3V)
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 3-33:
Temperature: C
Power Consumption vs.
FIGURE 3-36:
Power Consumption vs.
= 20 pF.
LOAD_SDO
DS20005947B-page 22
2017 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
4.0
TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33111D-XX)
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
0.5
0.3
0.5
V
= 5V
V
= 2.5V
REF
REF
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
0
1,024
2,048
Code
3,072
4,096
0
1,024
2,048
Code
3,072
4,096
FIGURE 4-1:
INL vs. Output Code.
FIGURE 4-4:
INL vs. Output Code.
0.5
0.3
0.5
0.3
V
= 2.5V
V
= 5V
REF
REF
0.1
0.1
-0.1
-0.3
-0.1
-0.3
-0.5
0
-0.5
0
1,024
2,048
Code
3,072
4,096
1,024
2,048
Code
3,072
4,096
FIGURE 4-2:
DNL vs. Output Code.
FIGURE 4-5:
DNL vs. Output Code.
0.2
0.15
0.1
0.2
0.15
0.1
Max INL (LSB)
Max DNL (LSB)
0.05
0
0.05
0
V
= 5V
V
= 5V
REF
REF
-0.05
-0.1
-0.15
-0.05
-0.1
-0.15
Min DNL (LSB)
Min INL (LSB)
-0.2
-0.2
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 4-3:
INL vs. Temperature.
FIGURE 4-6:
DNL vs. Temperature.
2017 Microchip Technology Inc.
DS20005947B-page 23
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
0.4
0.3
0.2
0.1
0
0.4
0.3
Max INL (LSB)
0.2
Max DNL (LSB)
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.1
Min INL (LSB)
-0.2
-0.3
-0.4
Min DNL (LSB)
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 4-7:
INL vs. Reference Voltage.
FIGURE 4-10:
DNL vs. Reference Voltage.
MCP33111D-10
MCP33111D-10
0
0
V
= 5V
V
= 2.5V
REF
REF
f
= 1 Msps
f
= 1 Msps
s
s
-20
-40
-20
-40
SNR = 73.9 dBFS
SINAD = 73.9 dBFS
SFDR = 99.8 dBc
THD = -96.5 dBc
Offset = 0 LSB
SNR = 73.8 dBFS
SINAD = 73.7 dBFS
SFDR = 97.0 dBc
THD = -95.6 dBc
Offset = -1 LSB
-60
-60
Resolution = 12-bit
Resolution = 12-bit
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Frequency (kHz)
Frequency (kHz)
FIGURE 4-8:
FFT for 10 kHz Input Signal:
= 5V.
FIGURE 4-11:
FFT for 10 kHz Input Signal:
= 2.5V.
f = 1 Msps, V = -1 dBFS, V
f = 1 Msps, V = -1 dBFS, V
S
IN
REF
S
IN
REF
MCP33111D-05
MCP33111D-05
0
-20
0
-20
V
= 5V
V
= 2.5V
REF
REF
f
= 0.5 Msps
f
= 0.5 Msps
s
s
SNR = 74.0 dBFS
SINAD = 73.9 dBFS
SFDR = 99.5 dBc
THD = -95.1 dBc
Offset = 0 LSB
SNR = 73.8 dBFS
SINAD = 73.8 dBFS
SFDR = 96.2 dBc
THD = -94.3 dBc
Offset = -1 LSB
-40
-40
-60
-60
Resolution = 12-bit
Resolution = 12-bit
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
FIGURE 4-9:
FFT for 10 kHz Input Signal:
= 5V.
FIGURE 4-12:
f = 500 kSPS, V = -1 dBFS, V
REF
FFT for 10 kHz Input Signal:
f = 500 kSPS, V = -1 dBFS, V
= 2.5V.
S
IN
REF
S
IN
DS20005947B-page 24
2017 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
73.2
73
13
12
11
10
-91
-94
105
100
95
THD (dB)
SFDR (dB)
-97
72.8
72.6
ENOB
SNR (dB)
SINAD (dB)
-100
90
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 4-13:
SNR/SINAD/ENOB vs. VREF
FIGURE 4-16:
SFDR/THD vs. V
REF
72.9
72.85
72.8
72.98
72.97
72.96
72.95
72.94
72.93
V
= 2.5V
V
= 5V
REF
REF
72.75
72.7
SNR (dB)
SNR (dB)
SINAD (dB)
SINAD (dB)
72.65
72.92
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 4-14:
Temperature: V
SNR/SINAD vs.
= 5V.
FIGURE 4-17:
Temperature: V
SNR/SINAD vs.
= 2.5V.
REF
REF
75
74
73
72
75
74
73
72
V
= 5V
V
= 2.5V
REF
REF
SNR (dBFS)
SINAD(dBFS)
SNR (dBFS)
SINAD(dBFS)
71
70
71
70
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 4-15:
SNR/SINAD vs. Input
FIGURE 4-18:
SNR/SINAD vs. Input
Amplitude: F = 10 kHz.
Amplitude: F = 10 kHz.
IN
IN
2017 Microchip Technology Inc.
DS20005947B-page 25
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
80
75
70
65
60
80
V
= 5V
V
= 2.5V
REF
REF
75
70
65
60
SNR (dB)
SNR (dB)
SINAD (dB)
SINAD (dB)
100
101
102
103
100
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 4-19:
SNR/SINAD vs. Input
FIGURE 4-22:
SNR/SINAD vs. Input
Frequency: V = -1 dBFS
Frequency: V = -1 dBFS.
IN
IN
-91
99
98
97
96
95
94
-92
102
100
98
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-93
-94
-95
-96
-97
-98
-92
-93
-94
-95
-96
V
= 2.5V
V
= 5V
REF
REF
96
94
-40 -20
0
20 40 60 80 100 120 140
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
Temperature (oC)
FIGURE 4-20:
THD/SFDR vs.
FIGURE 4-23:
THD/SFDR vs.
Temperature: V
= 5V.
Temperature: V
= 2.5V.
REF
REF
-75
-80
110
105
100
95
-75
-80
110
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-85
-85
-90
-90
-95
90
-95
90
-100
-105
85
-100
-105
85
80
80
V
= 2.5V
V
= 5V
REF
REF
-110
100
75
-110
100
75
101
102
103
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 4-21:
THD/SFDR vs. Input
= 5V.
FIGURE 4-24:
THD/SFDR vs. Input
= 2.5V.
Frequency: V
Frequency: V
REF
REF
DS20005947B-page 26
2017 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
-60
-65
105
100
95
-60
-65
105
100
95
90
85
80
75
70
65
60
THD (dB)
THD (dB)
SFDR (dB)
SFDR (dB)
-70
-70
-75
90
-75
-80
85
-80
V
= 5V
V
= 2.5V
REF
REF
-85
80
-85
-90
75
-90
-95
70
-95
-100
-105
65
-100
-105
60
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 4-25:
THD/SFDR vs. Input
= 5V.
FIGURE 4-28:
THD/SFDR vs. Input
= 2.5V.
Amplitude: V
Amplitude: V
REF
REF
ꢀ105
ꢀ105
10
10
872448
V
= 5V
V
= 2.5V
845413
REF
REF
8
6
4
2
0
8
6
4
2
203163
176128
0
-3
-2
-1
0
1
2
-3
-2
-1
0
1
2
3
Output Code
Output Code
FIGURE 4-26:
= 5V.
Shorted Input Histogram:
FIGURE 4-29:
Shorted Input Histogram:
V
V
= 2.5V.
REF
REF
400
0.16
0
0
200
0
0.082
Gain Error
Gain Error
-200
-0.16
-0.33
-0.49
-0.66
0
-200
-400
-600
-800
-1000
-0.082
-0.16
-0.25
-0.33
-0.41
-400
-600
-800
Offset Error
Offset Error
V
= 2.5V
V
= 5V
REF
REF
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 4-27:
Temperature: V
Offset and Gain Error vs.
= 5V.
FIGURE 4-30:
Temperature: V
Offset and Gain Error vs.
= 2.5V.
REF
REF
2017 Microchip Technology Inc.
DS20005947B-page 27
MCP33131D/MCP33121D/MCP33111D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
86
84
82
80
78
76
8
16
12
8
VREF = 5V
6
Total Power Consumption
4
IIO_STBY (DVIO = 3.3V)
2
4
IREF_STBY (VREF = 5V)
0
0
74
10-3
10-2
10-1
Input Frequency (kHz)
100
101
102
103
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 4-31:
= 5V.
CMRR vs. Input Frequency:
FIGURE 4-34:
Temperature during Shutdown.
Power Consumption vs.
V
REF
2
8
6
4
2
0
2
8
6
4
2
0
MCP331x1D-05
MCP331x1D-10
1.5
1
1.5
1
0.5
0
0.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Sample Rate (Msps)
1
0.1
0.2
0.3
0.4
0.5
Sample Rate (Msps)
FIGURE 4-32:
Sample Rate: C
Power Consumption vs.
= 20 pF.
FIGURE 4-35:
Sample Rate: CLOAD_SDO = 20 pF.
Power Consumption vs.
LOAD_SDO
MCP331x1D-10
2
8
6
4
2
0
2.5
10
8
MCP331x1D-05
MCP331x1D-10
2
1.5
1
1.5
1
6
4
IREF (VREF = 5V)
0.5
0.5
2
IREF (VREF = 5V)
IIO_DATA (DVIO = 3.3V)
IIO_DATA (DVIO = 3.3V)
0
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 4-33:
Power Consumption vs.
FIGURE 4-36:
Power Consumption vs.
Temperature: C
= 20 pF.
Temperature: CLOAD_SDO = 20 pF.
LOAD_SDO
DS20005947B-page 28
2017 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
5.0
PIN FUNCTION DESCRIPTIONS
TABLE 5-1:
Pin Number
1
PIN FUNCTION TABLE
Pin Name
Function
VREF
Reference voltage input (2.5V - 5.1V).
This pin should be decoupled with a 10 F tantalum capacitor.
2
AVDD
DC supply voltage input for analog section (1.8V).
This pin should be decoupled with a 1 F ceramic capacitor.
3
4
5
AIN+
AIN-
Differential positive analog input.
Differential negative analog input.
GND
Power supply ground reference. This pin is a common ground for both the analog
power supply (AVDD) and digital I/O supply (DVIO).
6
CNVST
Conversion-start control and active-low SPI chip-select digital input.
A new conversion is started on the rising edge of CNVST.
When the conversion is complete, output data is available at SDO by lowering CNVST.
7
8
SDO
SPI-compatible serial digital data output: ADC conversion data is shifted out by SCLK
clock, with MSB first.
SCLK
SPI-compatible serial data clock digital input.
The ADC output is synchronously shifted out by this clock.
9
SDI
SPI-compatible serial data digital input. Tie to DVIO for normal operation.
10
DVIO
DC supply voltage for digital input/output interface (1.7V - 5.5V).
This pin should be decoupled with a 0.1 F ceramic capacitor.
5.1
Supply Voltages and Reference
Voltage
Note:
During the initial power-up sequence, the
reference voltage (VREF must be
provided prior to supplying AVDD or within
about 64 ms after supplying AVDD
Otherwise, it is strongly recommended to
send recalibrate command. See
)
The device has two power supply pins:
a) Analog power supply (AVDD): 1.8V
.
b) Digital input/output interface power supply
(DVIO): 1.7V to 5.5V.
a
Section 7.1 “Recalibrate Command” for
more details.
The large supply voltage range of DVIO allows the
device to interface with various host devices that are
5.2.1
VOLTAGE REFERENCE
SELECTION
y
operating with different supply voltages. See Table 1-2
for timing specifications for I/O interface signal param-
eters depending on DVIO voltage.
The performance of the voltage reference has a large
impact on the accuracy of high-precision data
acquisition systems. The voltage reference should
have high-accuracy, low-noise, and low-temperature
drift. A ±0.1% output accuracy of the reference directly
corresponds to ±0.1% absolute accuracy of the ADC
output. The RMS output noise voltage of the reference
should be less than 1/2 LSB of the ADC.
Note:
Proper decoupling capacitors (1 F to
AVDD, 0.1 F to DVIO) should be mounted
as close as possible to the respective
pins.
5.2
Reference Voltage (VREF)
The device requires a single-ended external reference
voltage (VREF). The external input reference range is
from 2.5V to 5.1V. This reference voltage sets the
input full-scale range from 0V to VREF. See Figure 6-2
to Figure 6-8 for example application circuits and
reference voltage settings.
Note:
The reference pin needs a tantalum
decoupling capacitor (10 F, 10V rating).
Additional multiple ceramic capacitors can
be added in parallel to decouple
high-frequency noises.
2018 Microchip Technology Inc.
DS20005947B-page 29
MCP33131D/MCP33121D/MCP33111D-XX
6.0
DEVICE OVERVIEW
When the MCP33131D/MCP33121D/MCP33111D-XX
is first powered-up, it performs a self-calibration and
enters a low current input acquisition mode (Standby)
by itself.
MCP331x1D-XX
VREF
V
= 0.6V
T
Sample VIN
+
D
SW1+
R
SON
+
The external reference voltage (VREF) ranging from
2.5V to 5.1V sets the differential input full-scale range
A +
IN
CS
SW2+
1
CPIN
(200 )
(31 pF)
(FSR) from -VREF to +VREF
.
D
2
I
LEAKAGE
(~ ±1 nA)
The differential input signal needs an appropriate input
common-mode voltage from 0V to VREF, depending on
the input signal condition. VREF/2 is typically used for a
symmetric differential input.
VREF
V
= 0.6V
T
Sample VIN
-
D
1
SW1-
-
During input acquisition (Standby), the internal input
sampling capacitors are connected to the input signal,
while most of the internal analog circuits are shutdown
to save power. During this input acquisition time
(tACQ), the device consumes less than 1 A.
CS
A
-
R
SW2-
SON
IN
CPIN
(200 )
(31 pF)
D
2
I
LEAKAGE
(~ ±1 nA)
The user can operate the device with an easy-to-use
SPI-compatible 3-wire interface.
where:
The device initiates data conversion on the rising edge
of the conversion-start control (CNVST). The data con-
version time (tCNV) is set by the internal clock. Once
the conversion is complete and the host lowers
CNVST, the output data is available on SDO and the
device starts the next input acquisition by itself. During
this input acquisition time (tACQ), the user can clock
out the output data by providing the SPI-compatible
serial clock (SCLK).
+
-
C
, C
S
S
= Input sample and hold capacitor ≈ 31 pF.
R
SON
= On-resistance of the sampling switch ≈ 200
= Package pin + ESD capacitor ≈ 2 pF.
CPIN
FIGURE 6-1:
Analog Input Circuit.
Simplified Equivalent
6.1.1
ABSOLUTE MAXIMUM INPUT
VOLTAGE RANGE
The input voltage at each input pin (AIN+ and AIN-)
must meet the following absolute maximum input
voltage limits:
The device provides conversion data with no missing
codes. This ADC device family has a large input
full-scale range, high precision, high throughput with
no output latency, and is an ideal choice for various
ADC applications.
• (VIN+, VIN-) < VREF + 0.1V
• (VIN+, VIN-) > GND - 0.1V
6.1
Analog Inputs
Note:
The ESD diodes at the analog input pins
are biased from VREF. Any input voltage
outside the absolute maximum range can
turn on the input ESD protection diodes
and results in input leakage current which
may cause conversion errors and
permanent damage to the device. Care
must be taken in setting the input voltage
ranges so that the input voltage does not
exceed the absolute maximum input
voltage range.
Figure 6-1 shows a simplified equivalent circuit of the
differential input architecture with a switched capacitor
input stage. The input sampling capacitors
(CS+ and CS ) are about 31 pF each. The back-to-back
-
diodes (D1 - D2) at each input are ESD protection
diodes. Note that these ESD diodes are tied to VREF, so
that each input signal can swing from 0V to +VREF and
from -VREF to +VREF differentially.
During input acquisition (Standby), the sampling
switches are closed and each input sees the sampling
capacitor (≈ 31 pF) in series with the on-resistance of
the sampling switch, RSON (≈ 200).
For high-precision data conversion applications, the
input voltage needs to be fully settled within 1/2 LSB
during the input acquisition period (tACQ). The settling
time is directly related to the source impedance: A
lower impedance source results in faster input settling
time. Although the device can be driven directly with a
low impedance source, using a low noise input driver is
highly recommended.
DS20005947B-page 30
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Figure 6-2 is the reference circuit that is used to collect
most of the linearity performance data shown in
Table 1-1.
6.1.2
INPUT VOLTAGE RANGE
The differential input (VIN) and common-mode voltage
(VCM) at the input pins are defined by:
The differential input driver shown in Figure 6-2 can be
replaced with a low noise dual-channel op-amp. See
Section 6.3 “ADC Input Driver Selection” for the
driver selection.
EQUATION 6-1:
DIFFERENTIAL INPUT
VIN = VIN+ – VIN
-
VIN+ + VIN
-
6.2.2
ARBITRARY WAVEFORM INPUT
SIGNALS
VCM = ----------------------------
2
The MCP33131D/MCP33121D/MCP33111D-XX can
convert input signals with arbitrary waveforms at the
inputs AIN+ and AIN-. These inputs can be symmetric,
non-symmetric or independent with respect to each
other.
where VIN+ is the input at the AIN+ pin and VIN- is the
input at AIN- pin. The input signal swings around an
input common-mode voltage (VCM), typically centered
at VREF/2 for the best performance.
The absolute value of the differential input (VIN) needs
to be less than the reference voltage. The device will
output saturated output codes (all 0s or all 1s except
sign bit) if the absolute value of the input (VIN) is greater
than the reference voltage.
In the arbitrary input configuration, each ADC analog
input is connected to a single ended source ranging
from 0V to VREF. In this case, the ADC converts the
voltage difference between the two input signals.
Figure 6-4 shows the configuration example for the
arbitrary input signals.
The differential input full-scale voltage range (FSR) is
given by the external reference voltage (VREF) setting:
6.2.3
SINGLE-ENDED INPUT SIGNALS
EQUATION 6-2:
FSR AND INPUT RANGE
= 2VREF
Although the MCP33131D/MCP33121D/MCP33111D-XX
is a fully-differential input device, it can also convert
single-ended input signals. The most commonly
recommended single-ended configurations are:
Input Full-Scale Range (FSR)
Input Range:
–VREF VIN VREF – 1LSB
(a) pseudo-differential bipolar configuration and
(b) pseudo-differential unipolar configuration.
6.2
Analog Input Conditioning
Circuits
6.2.3.1
Pseudo-Differential Bipolar
Configuration
The
MCP33131D/MCP33121D/MCP33111D-XX
supports various input types, such as: (a)
fully-differential inputs, (b) arbitrary waveform inputs
and (c) single-ended inputs.
In the pseudo-differential bipolar configuration, one of
the ADC analog inputs (typically AIN-) is driven with a
fixed DC voltage (typically VREF/2), while the other
(AIN+) is connected to a single-ended signal in the
6.2.1
FULLY-DIFFERENTIAL INPUT
SIGNALS
range 0V to VREF
.
In this case, the ADC converts the voltage difference
between the single-ended signal and the DC voltage.
Figure 6-5 shows the configuration example and
Figure 6-6 shows its transfer function.
The
MCP33131D/MCP33121D/MCP33111D-XX
provides the best linearity performance with
fully-differential inputs. Figure 6-2 shows an example
of a fully-differential input conditioning circuit with a
differential input driver followed by an RC anti-aliasing
filter. Figure 6-3 shows its transfer function.
6.2.3.2
Pseudo-Differential Unipolar
Configuration
The differential input (VIN) between the two differential
In the pseudo-differential unipolar input configuration,
one of the ADC analog inputs (typically AIN-) is
connected to ground, while the other (AIN+) is
connected to a single ended signal in the range 0V to
ADC analog input pins (AIN+, AIN-) swings from -VREF
-
to +VREF centered at the input common-mode voltage
(VOCM).
VREF
.
The front-end differential driver provides a low output
impedance, which provides fast settling of the analog
inputs during the acquisition phase and provides
isolation between the signal source and the ADC. The
RC low-pass anti-aliasing filter band-limits the output
noise of the input driver and attenuates the kick-back
noise spikes from the ADC during conversion.
In this case, the ADC converts the voltage difference
between the single ended signal and ground.
Figure 6-7 shows the configuration example and
Figure 6-8 shows its transfer function.
2018 Microchip Technology Inc.
DS20005947B-page 31
MCP33131D/MCP33121D/MCP33111D-XX
V
REF
Voltage
Reference
V
DC
C
R
(Note 2)
10 F
1.8V to 5.5V
1.8V
R
F1
VREF
Differential Inputs
V
/2
REF
0V
R
R
V
+
DV
IO
AV
G1
R1
REF
DD
VREF
A
IN
+
(22 ±0.1%
)
0V
C1
V
/2
SDI
CNVST
SCLK
SDO
REF
(1.7nF, NPO)
Host Device
VOCM
MCP331x1D-XX
R1
(PIC32MZ)
G2
VREF
0V
A
-
IN
-
(22 ±0.1%
)
VREF
V
GND
C1
/2
R
REF
(1.7nF, NPO)
F2
0V
Input Driver
(Note 1)
1
fC
=
2R C
1
1
Note 1: Contact Microchip Technology Inc. for availability of the differential input driver amplifiers.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
FIGURE 6-2:
Input Conditional Circuit for Fully-Differential Input.
Digital Output Code (Two’s Complement)
n
2 /2 - 1
-V
REF
+V
- 1 LSB
REF
V
IN
0
Differential Input Voltage
n
- 2 /2
Available V range
IN
FIGURE 6-3:
Transfer Function for Figure 6-2.
DS20005947B-page 32
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
V
REF
Voltage
Reference
V
DC
C
R
(Note 2)
10 F
1.8V to 5.5V
1.8V
Arbitrary Waveform Differential Inputs
V
+
DV
IO
R1
R1
AV
REF
DD
VREF
A
IN
C1
C1
SDI
0V
Host Device
MCP331x1D-XX
CNVST
SCLK
SDO
(PIC32MZ)
VREF
A
-
IN
GND
1
0V
fC
=
2R C
1
1
Low Noise Input Buffer
(Note 1)
Note 1: Contact Microchip Technology Inc. for availability of the low-noise input driver amplifiers.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
FIGURE 6-4:
Input Configuration for Arbitrary Waveform Input Signals.
V
REF
Voltage
Reference
V
DC
C
R
(Note 2)
10 F
1.8V to 5.5V
1.8V
AV
Low Noise Input Buffer
(Note 1)
VREF
Single-Ended Input
V
/2
REF
R1
(22 ±0.1%
V
+
DV
IO
REF
DD
0V
VREF
A
IN
V
/2
)
REF
C1
0V
SDI
CNVST
SCLK
(1.7nF, NPO)
Host Device
MCP331x1D-XX
R1
(PIC32MZ)
V
/2
REF
A
-
IN
SDO
(22 ±0.1%
)
V
/2
GND
REF
C1
1 F
(1.7nF, NPO)
1
fC
=
2R C
1
1
Note 1: Contact Microchip Technology Inc. for availability of the low-noise input driver amplifiers.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
FIGURE 6-5:
Pseudo-Differential Bipolar-Input Configuration for Single-Ended Input Signal.
Digital Output Code (Two’s Complement)
n
2 /2 - 1
n
2 /4
-V
/2
-V
REF
REF
V
IN
+V
- 1 LSB
0
REF
+V
/2
REF
Analog Input Voltage
n
- 2 /4
Available V range
IN
n
- 2 /2
FIGURE 6-6:
Transfer Function for Figure 6-5.
2018 Microchip Technology Inc.
DS20005947B-page 33
MCP33131D/MCP33121D/MCP33111D-XX
V
REF
Voltage
Reference
V
DC
C
R
(Note 2)
10 F
1.8V to 5.5V
1.8V
VREF
V
/2
REF
0V
Single-Ended Input
R1
(22 ±0.1%
V
+
DV
IO
AV
REF
DD
A
IN
VREF
)
C1
V
/2
REF
0V
(1.7nF, NPO)
SDI
CNVST
SCLK
Host Device
Low Noise Input Buffer
(Note 1)
MCP331x1D-XX
R1
(PIC32MZ)
A
-
IN
SDO
(22 ±0.1%
C1
(1.7nF, NPO)
)
GND
Note 1: Contact Microchip Technology Inc. for availability of the low-noise input driver amplifiers.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
FIGURE 6-7:
Pseudo-Differential Unipolar-Input Configuration for Single-Ended Input Signal.
Digital Output Code (Two’s Complement)
n
2 /2 - 1
n
2 /4
-V
/2
-V
REF
REF
V
IN
0
+V
/2 +V
REF
REF
Analog Input Voltage
Available V range
IN
n
- 2 /4
n
- 2 /2
FIGURE 6-8:
Transfer Function for Figure 6-7.
DS20005947B-page 34
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
EQUATION 6-5:
VN_ADC Input-Referred Noise
FSR
ADC INPUT-REFERRED
NOISE
6.3
ADC Input Driver Selection
The noise and distortion of the ADC input driver can
degrade the dynamic performance (SNR, SFDR, and
THD) of the overall ADC application system. Therefore,
the ADC input driver needs better performance
specifications than the ADC itself. The data sheet of the
driver typically shows the output noise voltage and
harmonic distortion parameters.
SNR
–-----------
20
(V)
-----------
=
=
=
10
2
2
SNR
–-----------
.
VREF
--------------
2
20
for differential input
10
10
SNR
Figure 6-9 shows
presentation block diagram for the front-end driver and
ADC.
a
simplified system noise
–----------
VREF
20
for single-ended input
--------------
2
2
where FSR is the input full-scale range of ADC.
Front-End Driver
R
• Noise Contribution from the Front-End Driver:
The noise from the input driver can degrade the ADC’s
SNR performance. Therefore, the selected input driver
should have the lowest possible broadband noise
density and 1/f noise. When an anti-aliasing filter is
used after the input driver, the output noise density of
the input driver is integrated over the -3 dB bandwidth
of the filter.
- +
- +
ADC
C
VN_RMS_Driver Noise
VN_ADC Input-Referred Noise
FIGURE 6-9:
Simplified System Noise
Representation.
Equation 6-6 shows the RMS output noise voltage
calculation using the RC filter’s bandwidth and noise
density (eN) of the input driver. GN in Equation 6-6 is
the noise gain of the driver amplifier and becomes 1 for
a unity gain buffer driver.
• Unity-Gain Bandwidth:
An input driver with higher bandwidth usually results in
better overall linearity performance. Typically, the driver
should have the unity-gain bandwidth greater than 5
times the -3 dB cutoff frequency of the anti-aliasing
filter:
EQUATION 6-6:
NOISE FROM FRONT-END
DRIVER AMPLIFIER
EQUATION 6-3:
BANDWIDTH
REQUIREMENT FOR ADC
INPUT DRIVER
eN
VN_RMS_Driver Noise
------
2
(V)
GN
f
B
BW
where eN is the broadband noise density (V/√Hz) of the
front-end driver amplifier and is typically given in its
data sheet. In Equation 6-6, 1/f noise (eNFlicker) is
ignored assuming it is very small compared to the
broadband noise (eN).
Input Driver
5 x f
(Hz)
B
5
--------------
for a single-pole RC filter
2RC
where, fB = -3 dB bandwidth of RC anti-aliasing filter as
shown in Figure 6-9.
For high precision ADC applications, the noise
contribution from the front-end input driver amplifier is
typically constrained to be less than about 20% (or 1/5
times) of the ADC input-referred noise as shown in
Equation 6-7:
• Distortion:
The nonlinearity characteristics of the input driver
cause distortions in the ADC output. Therefore, the
input driver should have less distortion than the ADC
itself. The recommended total harmonic distortion
(THD) of the driver is at least 10 dB less than that of the
ADC:
EQUATION 6-7:
RECOMMENDED ADC
INPUT DRIVER NOISE
1
5
VN_RMS_Driver Noise
V
--
N_ADC Input-Referred Noise
EQUATION 6-4:
RECOMMENDED THD
FOR ADC INPUT DRIVER
Using Equation 6-5 to Equation 6-7, the recommended
noise voltage density (eN) limit of the ADC input driver
is expressed in Equation 6-8:
THDInput Driver ≤ THDADC -10
(dB)
• ADC Input-Referred Noise:
When the ADC is operating with a full-scale input
range, the ADC input-referred RMS noise is
approximated as shown in Equation 6-5.
2018 Microchip Technology Inc.
DS20005947B-page 35
MCP33131D/MCP33121D/MCP33111D-XX
EQUATION 6-8:
NOISE DENSITY FOR ADC
INPUT DRIVER
TABLE 6-2:
Noise Voltage Density (eN) of
Input Driver for MCP33121D-XX
ADC
(Note 1)
RC
ADC Input Driver
eN
1
--
Filter Amplifier (G = 1)
------
N
GN
f
VN_ADC Input-Referred Noise
B
5
2
ADC
SNR
Noise Voltage
f
B
V
Input-Referred
Noise
REF
(a) eN for differential input ADC:
(dBFS)
(Note 2)
Density (e )
N
SNR
20
–-----------
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
10.3 nV/√Hz
8.9 nV/√Hz
8 nV/√Hz
1
1
V
------------------
---------------
eN
VREF 10
2.5V
3.3V
5V
84
84.5
85
111.5V
139 V
----------
5 GN
f
Hz
B
12.8 nV/√Hz
11.1 nV/√Hz
9.9 nV/√Hz
18.3 nV/√Hz
15.9 nV/√Hz
14.2 nV/√Hz
(b) eN for single-ended input ADC:
SNR
–-----------
1
20
V
1
----------
--------------------- ---------------
eN
VREF 10
10 GN
Hz
f
198.8 V
B
Note 1:
2:
See Equation 6-5 for the ADC input-referred noise
calculation for differential input.
Using Equation 6-8, the recommended maximum
noise voltage density limit for unity gain input driver for
differential input ADC can be estimated. Table 6-1 to
Table 6-3 show a few example results with GN = 1. The
user may use these tables as a reference when
selecting the ADC input driver amplifier.
f
is -3dB bandwidth of the RC anti-aliasing filter.
B
TABLE 6-3:
Noise Voltage Density (eN) of
Input Driver for MCP33111D-XX
RC
Filter
ADC Input Driver
ADC
(Note 1)
Amplifier (G = 1)
N
TABLE 6-1:
Noise Voltage Density (eN) of
Input Driver for MCP33131D-XX
ADC
Input-Referred
Noise
SNR
(dBFS)
Noise Voltage
f
B
V
REF
(Note 2)
Density (e )
RC
Filter
ADC Input Driver
ADC
(Note 1)
N
Amplifier (G = 1)
N
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
33.3 nV/√Hz
28.8 nV/√Hz
25.8 nV/√Hz
43.4 nV/√Hz
37.6 nV/√Hz
33.6 nV/√Hz
65 nV/√Hz
ADC
Input-Referred
Noise
2.5V
3.3V
5V
73.8
73.9
74
360.9V
471 V
SNR
(dBFS)
Noise Voltage
f
B
V
REF
(Table 2)
Density (e )
N
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
7.3 nV/√Hz
6.3 nV/√Hz
5.6 nV/√Hz
7.6 nV/√Hz
6.6 nV/√Hz
5.9 nV/√Hz
8.2 nV/√Hz
7.1 nV/√Hz
6.3 nV/√Hz
2.5V
3.3V
5V
87
89
92
79.1V
82.8 V
88.8 V
705.4 V
56.3 nV/√Hz
50.3 nV/√Hz
Note 1:
2:
See Equation 6-5 for the ADC input-referred noise cal-
culation for differential input.
is -3dB bandwidth of the RC anti-aliasing filter.
f
B
Note 1:
2:
See Equation 6-5 for the ADC input-referred noise
calculation for differential input.
f
is -3dB bandwidth of the RC anti-aliasing filter.
B
DS20005947B-page 36
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
6.4.2
DATA CONVERSION PHASE
6.4
Device Operation
The start of the conversion is controlled by CNVST. On
the rising edge of CNVST, the sampled charge is
locked (sample switches are opened) and the ADC
performs the conversion. Once a conversion is started,
it will not stop until the current conversion is complete.
When the MCP33131D/MCP33121D/MCP33111D-XX
is first powered-up, it self-calibrates internal systems
and enters input acquisition mode by itself. The device
operates in two phases: (a) Input Acquisition (Standby)
and (b) Data Conversion. Figure 6-10 shows the ADC
operating sequence.
The data conversion time (tCNV) is not user
controllable. After the conversion is complete and the
host lowers CNVST, the output data is presented on
SDO.
6.4.1
INPUT ACQUISITION PHASE
(STANDBY)
Any noise injection during the conversion phase may
affect the accuracy of the conversion. To reduce
external environment noise, minimize I/O events and
running clocks during the conversion time.
During the input acquisition phase (tACQ), also called
+
Standby, the two input sampling capacitors, CS and
-
CS , are connected to the AIN+ and AIN- pins,
respectively. The input voltage is sampled until a rising
edge on CNVST is detected. The input voltage should
The output data is clocked out MSB first. While the
output data is being transferred, the device enters the
next input acquisition phase.
be fully settled within 1/2 LSB during tACQ
During this input acquisition time (tACQ), the ADC
consumes less than 1 A. The acquisition time (tACQ
.
)
Note:
Transferring output data during the
acquisition phase can disturb the next
input sample. It is highly recommended to
allow at least tQUIET (10 ns, typical)
between the last edge on the SPI interface
and the rising edge on CNVST. See
is user-controllable. The system designer can increase
the acquisition time (tACQ) as long as needed for
additional power savings.
Figure 1-1 for tQUIET
.
tCYC = 1/fS
Input Acquisition
Input Acquisition
(Standby)
Data Conversion
tCNV
(Standby)
Operating
Condition
tACQ
tACQ
MCP331x1D-10: 300 ns (typical)
MCP331x1D-05: 800 ns (typical)
MCP331x1D-10: 700 ns (typical)
MCP331x1D-05: 1200 ns (typical)
MCP331x1D-10: 300 ns (typical)
MCP331x1D-05: 800 ns (typical)
(a) At the falling edge of CNVST,
ADC output is available at SDO.
(a) ADC acquires input sample #1. (a) Conversion is initiated at the rising edge of CNVST.
(b) No ADC output is available yet.
(b) All circuits are turned-on.
(b) ADC output can be clocked out
by providing clocks.
(c) Most analog circuits are
turned off.
(c) ADC output is not available yet.
(c) ADC acquires input sample #2.
MCP331x1D-10: ~1.6 mA
MCP331x1D-05: ~1.4 mA
(d) Most analog circuits are turned off.
IDDAN
I
~ 0.8 A
Off
(a) Device is first powered-up and
(b) Performs a power-up self-calibration.
Output Data
SDO
FIGURE 6-10:
Device Operating Sequence.
2018 Microchip Technology Inc.
DS20005947B-page 37
MCP33131D/MCP33121D/MCP33111D-XX
the input acquisition time (tACQ). For the continuous
sampling rate (fS), the minimum SPI clock frequency
requirement is determined by the following equation:
6.4.3
SAMPLE (THROUGHPUT) RATE
The device completes data conversion within the
maximum specification of the data conversion time
(tCNV). The continuous input sample rate is the inverse
of the sum of input acquisition time (tACQ) and data
conversion time (tCNV). Equation 6-9 shows the
continuous sample rate calculation using the minimum
and maximum specifications of the input acquisition
time (tACQ) and data conversion time (tCNV).
EQUATION 6-10: SPI CLOCK FREQUENCY
REQUIREMENT
tACQ = N TSCLK + tQUIET + tEN
1
N
---------------
-----------------------------------------------------
tACQ – tQUIET + tEN
fSCLK
=
=
TSCLK
where N is the number of output data bits, given by
EQUATION 6-9:
SAMPLE RATE
N = 16-bit for MCP33131D-XX
= 14-bit for MCP33121D-XX
= 12-bit for MCP33111D-XX
1
----------------------------------
Sample Rate =
tACQ + tCNV
TSCLK = Period of SPI clock
N x TSCLK = Output data window
(a) MCP331x1D-10:
---------------------------------------- = 1 Msps
1
Sample Rate =
tQUIET = Quiet time between the last output bit and
beginning of the next conversion start.
= 10 ns (min)
290ns + 710ns
(b) MCP331x1D-05:
Sample Rate =
1
------------------------------------------- = 500 kSPS
t
EN = Output enable time = 10 ns (max),
700ns + 1300ns
with DVIO 2.3V
Note: See Figure 1-1 for interface timing diagram.
6.4.4
SERIAL SPI CLOCK FREQUENCY
REQUIREMENT
where fSCLK is the minimum SPI serial clock frequency
required to transfer all N-bits of the output data during
input acquisition time (tACQ).
The ADC output is collected during the input acquisition
time (tACQ). For continuous input sampling and data
conversion sequence, the SPI clock frequency should
be fast enough to clock out all output data bits during
Table 6-4 and Table 6-5 show the examples of
calculated minimum SPI clock (fSCLK) requirements for
various input acquisition times for 1 Msps and 500 kSPS
family devices, respectively.
TABLE 6-4:
SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (T
) FOR MCP331X1D-10
ACQ
SPI Clock (fSCLK) Speed Requirement
Input
Acquisition Time:
(Note 1), (Note 2)
Data Conversion
Time (nS)
Sample Rate:
Conditions
fS (Msps)
t
(nS)
MCP33131D-10
(16-bit)
MCP33121D-10
(14-bit)
MCP33111D-10
(12-bit)
ACQ
250
69.57 MHz
64 MHz
60.87 MHz
56 MHz
52.17 MHz
48 MHz
1
85°C < T ≤ 125°C
A
270
280
0.98
0.97
1
750
(Note 3)
61.54 MHz
59.26 MHz
57.15 MHz
53.33 MHz
42.11 MHz
30.77 MHz
22.86 MHz
17.2 MHz
12.6 MHz
9.04 MHz
6.15 MHz
3.75 MHz
1.73 MHz
53.85 MHz
51.85 MHz
50 MHz
46.15 MHz
44.44 MHz
42.86 MHz
40 MHz
290
300
0.99
0.97
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-40°C ≤ T ≤ 85°C
A
320
46.67 MHz
36.84 MHz
26.92 MHz
20 MHz
400
30 MHz
540
23.08 MHz
17.14 MHz
12.9 MHz
9.45 MHz
6.78 MHz
4.62 MHz
2.81 MHz
1.3 MHz
710
720
720
15.05MHz
11.02 MHz
7.91 MHz
5.39 MHz
3.28 MHz
1.51 MHz
1290
1750
2620
4290
9290
Note 1:
This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (t
), when
ACQ
the ADC is operating in continuous input sampling mode.
2:
3:
See Equation 6-10 for the calculation of the SPI clock speed requirement.
In extended temperature range, the device takes longer data conversion time (t
: 750 nS, max). Using a shorter input acquisition time
CNV
is recommended (t
: 250 nS) for 1 Msps throughput rate.
ACQ
DS20005947B-page 38
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
TABLE 6-5:
SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (T
) FOR MCP331X1D-05
ACQ
SPI Clock (fSCLK) Speed Requirement
Input
Acquisition Time:
(Note 1), (Note 2)
Data Conversion
Sample Rate:
Conditions
Time (nS)
f
S (kSPS)
t
(nS)
MCP33131D-05
(16-bit)
MCP33121D-05
(14-bit)
MCP33111D-05
ACQ
(12-bit)
700
23.53MHz
22.22 MHz
20.78 MHz
17.58 MHz
13.56 MHz
10.39 MHz
7.96 MHz
5.97 MHz
4.35 MHz
2.99 MHz
1.84 MHz
20.59 MHz
19.44 MHz
18.18 MHz
15.39 MHz
11.86 MHz
9.09 MHz
6.97 MHz
5.22MHz
17.65 MHz
16.67 MHz
15.58 MHz
13.19 MHz
10.17 MHz
7.79 MHz
5.97 MHz
4.48 MHz
3.26 MHz
2.25 MHz
1.38 MHz
500
490
480
450
400
350
300
250
200
150
100
740
790
-40°C ≤ T ≤ 125°C
A
930
1300
1200
1560
2030
2700
3700
5370
8700
3.8 MHz
2.62 MHz
1.61 MHz
Note 1:
2:
This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (t
ADC is operating in continuous input sampling mode.
See Equation 6-10 for the calculation of the SPI clock speed requirement.
), when the
ACQ
6.5
Transfer Function
Digital Output Code (Two’s Complement)
The differential analog input is
VIN = (VIN+) - (VIN-).
011 ...111
011 ...110
The LSB size is given by Equation 6-11. and an
example of LSB size vs. reference voltage is
summarized in Table 6-6.
000 ...000
EQUATION 6-11: LSB SIZE - EXAMPLE
2VREF
LSB = ---------------
2N
where N is the resolution of the ADC in bits.
100 ...001
100 ...000
TABLE 6-6:
LSB SIZE VS. REFERENCE
0V
LSB Size
Reference
Voltage
-V
+ 1 LSB
REF
+V
- 1.5 LSB
+V
-V
+ 0.5 LSB
MCP33131D-XX MCP33121D-XX MCP33111D-XX
REF
REF
(VREF
)
-V
- 1 LSB
(16-bit)
(14-bit)
(12-bit)
REF
REF
Differential Analog Input Voltage
2.5V
2.7V
3V
76.3 V
82.4 V
305.2 V
329.6 V
366.2 V
402.8 V
427.3 V
488.3 V
549.3 V
610.4 V
622.6 V
1.2207 mV
1.3184 mV
1.4648 mV
1.6113 mV
1.7090 mV
1.9531 mV
2.1973 mV
2.4414 mV
2.4902 mV
FIGURE 6-11:
Ideal Transfer Function for
Fully-Differential Input Signal.
91.6 V
3.3V
3.5V
4V
100.7 V
106.8 V
122.1 V
137.3 V
152.6 V
155.6 V
4.5V
5V
5.1V
Figure 6-11 shows the ideal transfer function and
Table 6-7 shows the digital output codes for the
MCP33131D/MCP33121D/MCP33111D-XX.
2018 Microchip Technology Inc.
DS20005947B-page 39
MCP33131D/MCP33121D/MCP33111D-XX
6.6
Digital Output Code
The digital output code is proportional to the input
voltage. The output data is in binary two’s complement
format. With this coding scheme the MSB can be
considered a sign indicator. When the MSB is a logic
‘0’, the input is positive. When the MSB is a logic ‘1’, the
input is negative. The following is an example of the
output code:
(a) for a negative full-scale input:
Analog Input: (VIN+) - (VIN-) = -VREF
Output Code: 1000...0000
(b) for a zero differential input:
Analog Input: (VIN+) - (VIN-) = 0V
Output Code: 0000...0000
(c) for a positive full-scale input:
Analog Input: (VIN+) - (VIN-) = +VREF
Output Code: 0111...1111
The MSB (sign bit) is always transmitted first through
the SDO pin.
The code will be locked at 0111...11 for all voltages
greater than (VREF - 1 LSB) and 1000...00 for
voltages less than -VREF. Table 6-7 shows an example
of output codes of various input levels.
TABLE 6-7:
DIGITAL OUTPUT CODE
Digital Output Codes
Input Voltage (V)
MCP33131D-XX
(16-bit)
MCP33121D-XX
(14-bit)
MCP33111D-XX
(12-bit)
VREF
0111-1111-1111-1111
0111-1111-1111-1111
01-1111-1111-1111
01-1111-1111-1111
0111-1111-1111
0111-1111-1111
V
REF - 1 LSB
.
.
.
.
.
.
.
.
2 LSB
1 LSB
0V
0000-0000-0000-0010
0000-0000-0000-0001
0000-0000-0000-0000
1111-1111-1111-1111
1111-1111-1111-1110
00-0000-0000-0010
00-0000-0000-0001
00-0000-0000-0000
11-1111-1111-1111
11-1111-1111-1110
0000-0000-0010
0000-0000-0001
0000-0000-0000
1111-1111-1111
1111-1111-1110
-1 LSB
-2 LSB
.
.
.
.
.
.
.
.
- VREF
1000-0000-0000-0000
1000-0000-0000-0000
10-0000-0000-0000
10-0000-0000-0000
1000-0000-0000
1000-0000-0000
< -VREF
DS20005947B-page 40
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
SDO returns to high-Z state after the last data bit is
clocked out or when CNVST goes high, whichever
occurs first.
7.0
DIGITAL SERIAL INTERFACE
The device has
interface using four digital pins: CNVST, SDI, SDO and
SCLK.
a SPI-compatible serial digital
Figure 7-1 shows the connection diagram with the host
device and Figure 7-2 shows the SPI-compatible serial
interface timing diagram.
CS
DVIO
DVIO
CNVST
The SDI pin can be tied to the digital I/O interface
supply voltage (DVIO) or just maintain logic “High” level
by the host. The CNVST pin is used for both chip select
(CS) and conversion-start control.
SDI
SDO
SCLK
SDI
10 k
(Note 1)
A rising edge on CNVST initiates the conversion
process. Once the conversion is initiated, the device
will complete the conversion regardless of the state of
CNVST. This means the CNVST pin can be used for
other purposes during tCNV.
SCLK
(b) Host Device (Master)
(a) MCP33131D/21D/11D-XX
Note 1: Adding this pull-up is needed when monitoring
status of Recalibrate.
When the conversion is complete, the output is
available at SDO by lowering CNVST. Data is sent
MSB-first and changes on the falling edge of SCLK.
FIGURE 7-1:
Digital Interface Connection
Diagram.
Output data can be sampled on either edge of SCLK.
However, a digital host capturing data on the falling
edge of SCLK can achieve a faster read out rate.
tCYC
= 1/fS
SDI = DVIO
(Note 1)
t
CNVH
(a) Exit input acquisition mode and
(b) Enter new conversion mode
t
SU_SDIH_CNV
CNVST
t
SCLK
(Note 2)
4
14
1
16
3
15
2
SCLK
t
t
DO
QUIET
t
t
(Note 5)
SCLK_L
SCLK_H
t
DIS
Hi-Z
(MAX)
D15
(MSB)
Hi-Z
D2
SDO
D12
D1
D0
D14
D13
t
CNV
t
EN
(Note 3)
t
EN
(Note 4)
ADC State
Input Acquisition
Conversion
Input Acquisition
(t
)
(t
)
(t
)
ACQ
CNV
ACQ
Note 1: SDI must maintain “High” during the entire tCYC
2: Any SCLK toggling events (dummy clocks) before CNVST is changed to “Low” are ignored.
3: t when CNVST is lowered after t (Max).
.
EN
CNV
4: t when CNVST is lowered before t
(Max).
CNV
EN
5: Recommended data detection: Detect SDO on the falling edge of SCLK.
TM
FIGURE 7-2:
SPI Compatible Serial Interface Timing Diagram (16-bit device).
2018 Microchip Technology Inc.
DS20005947B-page 41
MCP33131D/MCP33121D/MCP33111D-XX
A self-calibration is initiated by sending the recalibrate
command. The host device sends a recalibrate
command by transmitting 1024 SCLK pulses (including
the clocks for data bits) while the device is in the
acquisition phase (Standby).
7.1
Recalibrate Command
The user may use the recalibrate command in the
following cases:
• When the reference voltage was not fully settled
during the first-power sequence.
The device drives SDO low during the recalibration
procedure, and returns to high-Z once completed. The
status of the recalibration procedure can be monitored
by placing a pull-up on SDO, so that SDO goes high
when the recalibration is complete.
• During operation, to ensure optimum performance
across varying environment conditions, such as
reference voltage and temperature.
Figure 7-3 shows the recalibrate command timing
diagram. The calibration takes approximately 500 ms
(tCAL).
(Note 1)
SDI = DVIO
Start recalibration
Finish recalibration
Complete data reading
Device Recalibration
CNVST
1024 clocks
(SPI Recalibrate command)
TM
1024
1
2
3
15 16
t
CAL
SCLK
SDO
(Note 2)
“High” with Pull-up
Hi-Z
“High” with Pull-up
Hi-Z
“Low”
ADC Output Data Stream
Hi-Z
(Note 3)
ADC State
(Note 4)
t
CNV
Note
1: SDI must remain “High” during the entire recalibration cycle.
2: The 1024 clocks include the clocks for data bits.
3: SDO outputs “Low” during calibration, and Hi-Z when exiting the calibration.
4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately.
FIGURE 7-3:
Note:
Recalibrate Command Timing Diagram.
When the device performs a self-calibration, it is important to note that both AVDD and the reference voltage
(VREF) must be stabilized for a correct calibration. This is also true when the device is first powered-up, the
reference voltage (VREF) must be stabilized before self-calibration begins. This means the VREF must be
provided prior to supplying AVDD or within about 64 ms after supplying AVDD
.
DS20005947B-page 42
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Figure 8-1 and Figure 8-2 show this evaluation tool.
This evaluation platform allows users to quickly
evaluate the ADC's performance for their specific
application requirements.
8.0
8.1
DEVELOPMENT SUPPORT
Device Evaluation Board
Microchip offers a high speed/high precision SAR ADC
evaluation platform which can be used to evaluate
Microchip’s latest high speed/high resolution SAR ADC
products. The platform consists of an MCP331x1D-XX
evaluation board, a data capture board (PIC32MZ EF
Curiosity Board), and a PC-based Graphical User
Interface (GUI) software.
Note:
Contact Microchip Technology Inc. for the
PIC32 MCU firmware and the
MCP331x1D-XX Evaluation Kit.
(a) MCP331x1D-XX Evaluation Board
(b) PIC32 MZ EF Curiosity Board
FIGURE 8-1:
MCP331x1D-XX Evaluation Kit.
FIGURE 8-2:
PC-Based Graphical User Interface Software.
2018 Microchip Technology Inc.
DS20005947B-page 43
MCP33131D/MCP33121D/MCP33111D-XX
ers are recommended:
8.2
PCB Layout Guidelines:
(a) Top Layer: Most of the noise-sensitive ana-
log components are populated on the top layer.
Use all unused surface area as ground planes:
analog ground plane in analog circuit section
and digital ground in digital circuit section. These
ground planes need to be tied to the corre-
sponding ground planes in the second and bot-
tom layers using multiple vias.
Microchip provides the schematics and PCB layout of
the MCP331x1D-XX Evaluation Board. It is strongly
recommended that the user references the example
circuits and PCB layouts.
A good schematic with low noise PCB layout is critical
for high performing ADC application system designs. A
few guidelines are listed below:
• Use low noise supplies (AVDD, DVIO, and VREF).
(b) 2nd Layer: Use this layer as the ground
plane: Analog ground plane under the analog
circuit section of the top layer and digital ground
plane under the digital circuit section on the top
layer. Each ground plane is tied to its corre-
sponding ground plane of top and bottom layers
using multiple vias.
• All supply voltage pins, including reference volt-
age, need decoupling capacitors. Decoupling
capacitor requirements for each supply pin are
shown in Table 5-1.
• Use NPO or COG type capacitor for the RC anti-
aliasing filters in the analog input network.
• Keep the analog circuit section (analog input
driver amplifiers, filters, voltage reference, ADC,
etc.) with an analog ground plane, and the digital
circuit section (MCU, digital I/O interface) with a
digital ground plane. Keep these sections as
much apart as possible. This will minimize any
digital switching noise coupling into the analog
section.
(c) 3rd Layer: This layer is used to distribute
various power supplies of the circuits. Use sep-
arate trace paths for the power supplies of ana-
log and digital sections. Do not use the same
power supply source for both analog and digital
circuits.
(d) Bottom Layer: This layer is mostly used as
a solid ground plane: Analog ground plane
under the analog circuit section of the top layer
and digital ground plane under the digital circuit
section on the top layer. Each ground plane is
tied to its corresponding ground plane of all lay-
ers using multiple vias.
• Connect the analog and digital ground planes at a
single point (away from the sensitive analog sec-
tions) with a 0 resistor or with a ferrite bead.
See Figure 8-3 as an example of separated
ground planes.
• Keep the clock and digital output data lines short
and away from the sensitive analog sections as
much as possible.
Figure 8-3 and Figure 8-4 show brief examples
of the PCB layout. See more details of the sche-
matics and PCB layout in the MCP331x1D-XX
Evaluation Board User’s Guide.
• PCB material and Layers: Low loss FR-4 mate-
rial is most commonly used. The following 4 lay-
Analog Ground Plane
(GND)
MCP331x1D-XX
Analog Ground Plane
(GND)
Note: Analog and digital
ground planes are
SCLK
SDO
connected via R56.
R56
Digital Interface
Connectors for MCU
Digital Ground Plane
(DGND)
(DGND)
Digital Ground Plane
FIGURE 8-3:
PCB Layout Example: Analog and Digital Ground Planes
DS20005947B-page 44
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
SDI
VREF
VIO
SCLK
SDO
AVDD
AIN+
-
AIN
GND
MCP331x1D-XX
CNVST
(a) PCB layout example
VREF
C6
10uF
(Tantalum)
R3
C7
VIN
+
C35
22R
100pF
1.7nF
(NPO)
MCP331x1D-XX
R8
VIN
-
22R
C37
1.7nF
(NPO)
33R
CNVST
SDI
33R
33R
SCLK
SDO
33R
R24 = 0 for Single-Ended
Configuration
(b) Schematic example from the MCP331x1D-XX Evaluation Board
PCB Layout Example: See more details in the MCP331x1D-XX EV Kit User’s Guide.
FIGURE 8-4:
2018 Microchip Technology Inc.
DS20005947B-page 45
MCP33131D/MCP33121D/MCP33111D-XX
NOTES:
DS20005947B-page 46
2018 Microchip Technology Inc.
–---------
-
–------------
MCP33131D/MCP33121D/MCP33111D-XX
EQUATION 9-2:
9.0
TERMINOLOGY
P
S
---------------------
SINAD = 10log
Analog Input Bandwidth (Full-Power
Bandwidth)
P
+ P
D
N
SNR
10
THD
10
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
= –10log 10
– 10
SINAD is either given in units of dBc (dB to carrier),
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale), when the
power of the fundamental is extrapolated to the
converter full-scale range.
Aperture Delay or Sampling Delay
This is the time delay between the rising edge of the
CNVST input and when the input signal is held for a
conversion.
Effective Number of Bits (ENOB)
Differential Nonlinearity
(DNL, No Missing Codes)
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
An ideal ADC exhibits code transitions that are exactly
1 LSB apart. DNL is the deviation from this ideal value.
No missing codes to 16-bit resolution indicates that all
65,536 codes (16,384 codes for 14-bit, 4096 codes for
12-bit) must be present over all the operating
conditions.
EQUATION 9-3:
SINAD – 1.76
ENOB = ----------------------------------
6.02
Gain Error
Integral Nonlinearity (INL)
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale
range. Gain error is usually expressed in LSB or as a
percentage of full-scale range (%FSR).
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to
the noise floor power (PN), below the Nyquist frequency
and excluding the power at DC and the first nine
harmonics.
Offset Error
The major carry transition should occur for an analog
value of ½ LSB below AIN+ = AIN−. Offset error is
defined as the deviation of the actual transition from
that point.
EQUATION 9-1:
P
S
Temperature Drift
-------
SNR = 10log
P
N
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value at across the TMIN to TMAX range.
The value is normalized by the reference voltage and
expressed in V/oC or ppm/oC.
SNR is either given in units of dBc (dB to carrier), when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale), when the power
of the fundamental is extrapolated to the converter
full-scale range.
Maximum Conversion Rate
Signal-to-Noise and Distortion (SINAD)
The maximum clock rate at which parametric testing is
performed.
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
2018 Microchip Technology Inc.
DS20005947B-page 47
MCP33131D/MCP33121D/MCP33111D-XX
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
EQUATION 9-4:
P
S
-------
THD = 10log
P
D
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 9-5:
2
2
2
3
2
4
2
n
V + V + V + + V
THD = –20log-----------------------------------------------------------------
2
V
1
Where:
V1 = RMS amplitude of the
fundamental frequency
V1 through Vn = Amplitudes of the second
through nth harmonics
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential input pair. The common-mode signal can be
an AC or DC signal or a combination of the two. CMRR
is measured using the ratio of the differential signal
gain to the common-mode signal gain and expressed in
dB with the following equation:
EQUATION 9-6:
A
DIFF
------------------
CMRR = 20log
A
CM
Where:
ADIFF = Output Code/Differential Voltage
ADIFF = Output Code/Common-Mode Voltage
DS20005947B-page 48
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
Example
10-Lead MSOP (3x3 mm)
Corresponding Part Number:
31D-10 = MCP33131D-10
31D-05 = MCP33131D-05
21D-10 = MCP33121D-10
21D-05 = MCP33121D-05
11D-10 = MCP33111D-10
11D-05 = MCP33111D-05
31D-10
839256
10-Lead TDFN (3x3x0.9 mm)
Example
Corresponding Part Number:
31D1 = MCP33131D-10
31D0 = MCP33131D-05
21D1 = MCP33121D-10
21D0 = MCP33121D-05
11D1 = MCP33111D-10
11D0 = MCP33111D-05
31D1
1839
256
XXXX
YYWW
NNN
PIN 1
PIN 1
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2018 Microchip Technology Inc.
DS20005947B-page 49
MCP33131D/MCP33121D/MCP33111D-XX
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 H
D
D
2
A
N
E
2
E1
2
E1
E
0.20 H
0.25 C
1
2
e
B
8X b
0.13
C A B
TOP VIEW
H
C
A2
A
SEATING
PLANE
8X
0.10 C
A1
SEE DETAIL A
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-021D Sheet 1 of 2
DS20005947B-page 50
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
4X Ĭ1
c
C
SEATING
PLANE
Ĭ
L
(L1)
4X Ĭ1
DETAIL A
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
10
0.50 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
A
-
-
1.10
0.95
0.15
A2
A1
E
E1
D
0.75
0.00
0.85
-
4.90 BSC
3.00 BSC
3.00 BSC
0.60
L
0.40
0.80
Footprint
L1
0.95 REF
Mold Draft Angle
Foot Angle
Lead Thickness
Lead Width
0°
5°
0.08
0.15
-
-
-
-
8°
15°
0.23
0.33
Ĭ
Ĭ1
c
b
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-021D Sheet 2 of 2
2018 Microchip Technology Inc.
DS20005947B-page 51
MCP33131D/MCP33121D/MCP33111D-XX
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
SILK SCREEN
Z
C
G1
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.50 BSC
4.40
MAX
Contact Pitch
E
C
Contact Pad Spacing
Overall Width
Contact Pad Width (X10)
Contact Pad Length (X10)
Distance Between Pads (X5)
Distance Between Pads (X8)
Z
X1
Y1
G1
G
5.80
0.30
1.40
3.00
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2021B
DS20005947B-page 52
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc.
DS20005947B-page 53
MCP33131D/MCP33121D/MCP33111D-XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005947B-page 54
2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
APPENDIX A: REVISION HISTORY
Revision B (November 2018)
• Added TDFN-10 package release
• Added AEC-Q100 qualification
• Added 500 kSPS family devices (MCP33131D/
MCP33121D/MCP33111D-05)
• Minor typographical corrections
Revision A (March 2018)
• Original release of this document
2018 Microchip Technology Inc.
DS20005947B-page 55
MCP33131D/MCP33121D/MCP33111D-XX
NOTES:
2018 Microchip Technology Inc.
DS20005947B-page 56
MCP33131D/MCP33121D/MCP33111D-XX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
─X
/XX
─XX
PART NO.
Device
X
Examples:
a)
MCP33131D-10-I/MS: 1 Msps, 10LD MSOP,
Input Type
Tape
and
Reel
Temperature Package
Range
Sample Rate
16-bit device
b)
MCP33131D-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
16-bit device
Device:
MCP33131D-10: 1 Msps 16-Bit Differential Input SAR ADC
MCP33121D-10: 1 Msps 14-Bit Differential Input SAR ADC
MCP33111D-10: 1 Msps 12-Bit Differential Input SAR ADC
c)
d)
MCP33131D-10-I/MN: 1 Msps, 10LD TDFN,
16-bit device
MCP33131D-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
MCP33131D-05: 500 kSPS 16-Bit Differential Input SAR ADC
MCP33121D-05: 500 kSPS 14-Bit Differential Input SAR ADC
MCP33111D-05: 500 kSPS 12-Bit Differential Input SAR ADC
16-bit device
e)
f)
MCP33121D-10-I/MS: 1 Msps, 10LD MSOP,
14-bit device
MCP33121D-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
Input Type
D: Differential Input
14-bit device
g)
h)
MCP33121D-10-I/MN: 1 Msps, 10LD TDFN,
14-bit device
Sample Rate: 10
= 1 Msps
= 500 kSPS
MCP33121D-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
05
14-bit device
i)
j)
MCP33111D-10-I/MS: 1 Msps, 10LD MSOP,
12-bit device
Tape and
Reel Option:
Blank
=
=
Standard packaging (tube or tray)
Tape and Reel
T
MCP33111D-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
Temperature
Range:
E
I
= -40C to +125C (Extended)
= -40C to +85C (Industrial)
12-bit device
k)
l)
MCP33111D-10-I/MN: 1 Msps, 10LD TDFN,
12-bit device
Package:
MS
MN
=
=
Plastic Micro Small Outline Package (MSOP), 10-Lead
MCP33111D-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
Thin Plastic Dual Flat No Lead Package (TDFN),
10-Lead
12-bit device
m) MCP33131D-05-I/MS: 500 kSPS, 10LD MSOP,
16-bit device
n)
MCP33131D-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
16-bit device
Note:
Tape and Reel identifier appears only in the catalog part number
description. This identifier is used for ordering purposes and is not
printed on the device package. Check with your Microchip Sales Office
for package availability with the Tape and Reel option.
o)
p)
MCP33131D-05-I/MN: 500 kSPS, 10LD TDFN,
16-bit device
MCP33131D-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
16-bit device
q)
r)
MCP33121D-05-I/MS: 500 kSPS, 10LD MSOP,
14-bit device
MCP33121D-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
14-bit device
s)
t)
MCP33121D-05-I/MN: 500 kSPS, 10LD TDFN,
14-bit device
MCP33121D-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
14-bit device
u)
v)
MCP33111D-10-I/MS: 500 kSPS, 10LD MSOP,
12-bit device
MCP33111D-10T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
12-bit device
w)
x)
MCP33111D-10-I/MN: 500 kSPS, 10LD TDFN,
12-bit device
MCP33111D-10T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
12-bit device
DS20005947B-page 57
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
CERTIFIEDꢀBYꢀDNVꢀ
© 2018, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-3863-2
== ISO/TSꢀ16949ꢀ==
2018 Microchip Technology Inc.
DS20005947B-page 58
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
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India - New Delhi
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Denmark - Copenhagen
Tel: 45-4450-2828
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China - Chengdu
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Finland - Espoo
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Atlanta
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Korea - Daegu
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China - Hangzhou
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Korea - Seoul
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Germany - Haan
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Detroit
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Thailand - Bangkok
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Italy - Padova
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Houston, TX
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Vietnam - Ho Chi Minh
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Netherlands - Drunen
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Fax: 31-416-690340
Indianapolis
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Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
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China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
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Tel: 951-273-7800
Romania - Bucharest
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Spain - Madrid
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Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20005947B-page 59
2018 Microchip Technology Inc.
08/15/18
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