MCP3464R-E/ST_技术文档

MCP3461/2/4R

Two/Four/Eight-Channel, 153.6 ksps, Low-Noise,

16-Bit Delta-Sigma ADCs with Internal Voltage Reference

Features

General Description

• One/Two/Four Differential or Two/Four/Eight

Single-Ended Input Channels

The MCP3461/2/4R devices are 2/4/8-channel, 16-bit,

Delta-Sigma Analog-to-Digital Converters (ADCs) with

programmable data rate of up to 153.6 ksps. They offer

integrated features, such as internal voltage reference,

internal oscillator, temperature sensor and burnout

sensor detection, in order to reduce system component

count and total solution cost.

• 16-Bit Resolution

• Programmable Data Rate: Up to 153.6 ksps

• Programmable Gain: 0.33x to 64x

• 97.2 dB SINAD, -116 dBc THD, 120 dBc SFDR

(Gain = 1x, 4800 SPS)

The MCP3461/2/4R ADCs are fully configurable with

Oversampling Ratio (OSR) from 32 to 98304, and gain

from 1/3x to 64x. These devices include an internal

sequencer (Scan mode) with multiple monitor channels

and a 16-bit timer to be able to automatically create

conversion loop sequences without needing MCU

communications. Advanced security features, such as

CRC and register map lock, can ensure configuration

locking and integrity, as well as communication data

integrity for secure environments.

• Low-Temperature Drift:

- Offset error drift: 4/Gain nV/°C (AZ_MUX = 1)

- Gain error drift: 0.5 ppm/°C (Gain = 1x)

• Low Noise: 2.3 µV_RMS(Gain = 16x, 9600 SPS)

• RMS Effective Resolution: 15.4 Bits Minimum (All

Gains, All OSR Combinations)

• Wide Input Voltage Range: 0V to AV_DD

• Selectable Internal 2.4V Voltage Reference with

15 ppm/°C Drift

These devices come with a 20 MHz SPI-compatible

serial interface. Communication is largely simplified

with 8-bit commands, including various Continuous

Read/Write modes and 16/32-bit multiple data formats

that can be accessed by the Direct Memory Access

(DMA) of an 8-bit, 16-bit or 32-bit MCU.

• Differential Voltage Reference Inputs

• Internal Oscillator or External Clock Selection

• Ultra-Low Full Shutdown Current Consumption

(< 2.4 µA)

• Internal Temperature Sensor

• Burnout Current Sources for Sensor Open/Short

Detection

The MCP3461/2/4R devices are available in a leaded

20-lead TSSOP package, as well as in an ultra-small,

3 mm x 3 mm x 0.55 mm 20-lead UQFN package and

are specified over an extended temperature range from

-40°C to +125°C.

• 16-Bit Digital Offset and Gain Error Calibration

Registers

• Internal Conversions Sequencer (Scan Mode) for

Automatic Multiplexing

Applications

• Dedicated IRQ Pin for Easy Synchronization

• Advanced Security Features:

• Precision Sensor Transducers and Transmitters:

Pressure, Strain, Flow and Force Measurement

- 16-bit CRC for secure SPI communications

- 16-bit CRC and IRQ for securing

configuration

• Factory Automation and Process Controls

• Portable Instrumentation

- Register map lock with 8-bit secure key

- Monitor controls for system diagnostics

• Temperature Measurements

• 20 MHz SPI-Compatible Interface with Mode 0,0

and 1,1

• AV_DD: 2.7V-3.6V

• DV_DD: 1.8V-3.6V

• Extended Temperature Range: -40°C to +125°C

• Packages: 3 mm x 3 mm x 0.55 mm 20-Lead

UQFN and 6.5 mm x 4.4 mm x 1 mm 20-Lead

TSSOP

 2020-2021 Microchip Technology Inc.

DS20006404C-page 1

MCP3461/2/4R

Package Types – 20-Lead UQFN

Package Type for All Devices: 20-Lead UQFN* (3 mm x 3 mm x 0.55 mm)

A. MCP3461R: Single Channel Device

20 19 18 17 16

REFIN-

1

2

3

4

15 IRQ/MDAT

REFIN+/OUT

CH0

SDO

SDI

14

13

EP

21

CH1

12 SCK

NC

5

11

CS

6

7

8

9

10

B. MCP3462R: Dual Channel Device

20 19 18 17 16

REFIN-

REFIN+/OUT

CH0

1

2

3

4

IRQ/MDAT

SDO

15

14

EP

21

13 SDI

SCK

CH1

12

11 CS

CH2

5

6

7

8

9

10

C. MCP3464R: Quad Channel Device

20 19 18 17 16

REFIN-

1

2

3

4

IRQ/MDAT

15

REFIN+/OUT

14 SDO

13 SDI

12 SCK

11 CS

EP

21

CH0

CH1

CH2

5

6

7

8

9 10

*Includes Exposed Thermal Pad (EP); see Table 3-1.

DS20006404C-page 2

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Package Types – 20-Lead TSSOP

Package Type for All Devices: 20-Lead TSSOP (6.5 mm x 4.4 mm x 1 mm)

A. MCP3461R: Single Channel Device

AV_DD

A_GND

1

2

3

4

DV_DD

20

19

18

17

16

D_GND

REFIN-

MCLK

IRQ/MDAT

SDO

REFIN+/OUT

CH0

CH1

NC

5

6

7

8

9

SDI

15

14

13

12

11

SCK

NC

CS

NC

10

NC

B. MCP3462R: Dual Channel Device

AV_DD

A_GND

1

2

3

4

DV_DD

D_GND

20

19

18

17

16

REFIN-

MCLK

REFIN+/OUT

CH0

IRQ/MDAT

5

SDO

SDI

CH1

6

7

8

9

15

14

13

12

11

CH2

CH3

NC

SCK

CS

NC

10

NC

C. MCP3464R: Quad Channel Device

AV_DD

A_GND

1

2

3

4

20

19

18

17

DV_DD

D_GND

REFIN-

MCLK

IRQ/MDAT

SDO

REFIN+/OUT

CH0

CH1

CH2

5

16

6

7

8

9

15

14

13

12

SDI

SCK

CS

CH3

CH4

CH7

CH6

10

CH5

11

Note:

The NC is a Not Connected pin. It is recommended for the NC pin to be tied to A_GNDfor a better

susceptibility to electromagnetic fields.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 3

MCP3461/2/4R

Functional Block Diagram

REFIN+/OUT

AV_DD

DV_DD

AMCLK

VREF_SEL

MCLK

+

-

Voltage

Reference

Clock

2.4V

Generation

(RC Oscillator)

IRQ/MDAT

DMCLK/DRCLK

REFIN-

V_REF-V_REF+

OSR[3:0]

PRE[1:0]

DMCLK

CH0

CH1

CHꢁ

CH3

CH4

CH5

V_IN

+

-

ꢀ

+

x

SDO

SDI

SCK

CS

SINC³Filter

with Digital

Gain

SINC¹

Filter

ꢁ^ndOrder

Digital SPI

Interface

V_IN

-

Offset/Gain

Δ±Ȉ

ꢀ

MCP346ꢁ/4R

Calibration

Modulator

with Analog

Gain

Analog

Differential

Multiplexer

only

and control

'±Ȉꢀꢀꢀ$ꢂ' Converter

MCP3464R

only

CH6

CH7

Burnout

Current

Sources

POR

AV_DD

POR

DV_DD

Monitoring

TEMP

Diodes

A_GNDAV_DD

A_GND

D_GND

ANALOG DIGITAL

DS20006404C-page 4

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

1.0

ELECTRICAL CHARACTERISTICS

†

Absolute Maximum Ratings

DV_DD,AV_DD......................................................................................................................................................-0.3 to 4.0V

Digital Inputs and Outputs w.r.t. D_GND............................................................................................ -0.3V to DV_DD+ 0.3V

Analog Inputs w.r.t. A_GND.................................................................................................................-0.3V to AV_DD+ 0.3V

Current at Input Pins...............................................................................................................................................±5 mA

Current at Output and Supply Pins ......................................................................................................................±20 mA

Storage Temperature ..............................................................................................................................-65°C to +150°C

Ambient Temperature with Power Applied ..............................................................................................-65°C to +125°C

Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C

Maximum Junction Temperature (T_J)........................................................................................... .........................+150°C

ESD on All Pins (HBM)  6.0 kV

†

Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions, above

those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 5

MCP3461/2/4R

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV = 2.7V to 3.6V, DV = 1.8V to AV + 0.1V,

DD

MCLK = 4.9152 MHz, V

= AV , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

REF

DD

T

= -40°C to +125°C, V = -0.5 dBFS at 50 Hz.

IN

A

Parameters

Supply Requirements

Sym.

Min.

Typ.

Max.

Units

Conditions

Analog Operating Voltage

Digital Operating Voltage

Analog Operating Current

AV

2.7

1.8

—

3.6

V

DD

DV

AV + 0.1

V

DV ≤ 3.6V

DD

AI

0.56

0.69

0.93

1.65

—

0.81

0.96

1.3

mA

BOOST[1:0] = 00, 0.5x

DD

—

BOOST[1:0] = 01, 0.66x

BOOST[1:0] = 10, 1x

BOOST[1:0] = 11, 2x

BOOST[1:0] = 00, 0.5x,

—

2.2

Analog Operating Current

AI

—

0.96

DD

V

= 2.4V internal

REF

—

1.2

1.6

2.5

mA

BOOST[1:0] = 01, 0.66x,

= 2.4V internal

V

REF

BOOST[1:0] = 10, 1x,

= 2.4V internal

V

REF

BOOST[1:0] = 11, 2x,

= 2.4V internal

V

REF

Digital Operating Current

DI

—

0.25

—

0.37

22

mA

µA

Note 8

DD

Analog Partial Shutdown

Current

AI

DI

AI

DI

CONFIG0 = 0x00

DDS_PS

DDS_FS

Digital Partial Shutdown

Current

—

17

0.4

2

µA

CONFIG0 = 0x00

Analog Full-Shutdown

Current

CONFIG0 = 0x00 with

Full-Shutdown Fast-CMD

Digital Full-Shutdown

Current

CONFIG0 = 0x00 with

Full-Shutdown Fast-CMD

Power-on Reset (POR)

Threshold Voltage

V

—

1.75

1.2

150

1

—

V

For analog circuits

For digital circuits

POR_A

POR_D

POR Hysteresis

POR Reset Time

V

mV

µs

POR_HYS

t

POR

Note 1: This parameter is ensured by design and not 100% tested.

2: This parameter is ensured by characterization and not 100% tested.

3: REFIN- must be connected to ground for single-ended measurements.

4: Full-Scale Range (FSR) = 2 x V

/Gain.

REF

5: This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between

the two input pins of the channel selected with the input multiplexer.

6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”.

7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.

8: DI is measured while no transfer is present on the SPI bus.

DD

9: An external buffer is recommended for external use.

10: Start-up time is the reaction time to the SPI command.

11: Settling time depends on bypass caps on REFIN+/OUT pin.

DS20006404C-page 6

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV = 2.7V to 3.6V, DV = 1.8V to AV + 0.1V,

DD

MCLK = 4.9152 MHz, V

= AV , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

REF

DD

T

= -40°C to +125°C, V = -0.5 dBFS at 50 Hz.

IN

A

Parameters

Analog Inputs

Sym.

Min.

Typ.

Max.

Units

Conditions

Input Voltage at Input Pin

CH

A

– 0.1

—

AV + 0.1

V

Analog inputs are measured

N

GND

DD

with respect to A

GND

Differential Input Range

V

Z

-V

/Gain

—

+V /Gain

REF

V

IN

REF

Differential Input Impedance

—

510

—

k

GAIN = 0.33x, proportional to

1/AMCLK

IN

(Note 5)

—

260

150

80

—

k

nA

GAIN = 1x, proportional to

1/AMCLK

GAIN = 2x, proportional to

1/AMCLK

GAIN = 4x, proportional to

1/AMCLK

40

GAIN = 8x, proportional to

1/AMCLK

20

GAIN ≥ 16x, proportional to

1/AMCLK

Analog Input Leakage

Current During ADC

Shutdown

I

±10

LI_A

Internal Voltage Reference

Internal V_REFAbsolute Voltage

I

-2%

—

2.4

15

+2%

40

V

VREF_SEL = 1,

VREF

T

= +25°C only

A

Internal V

Temperature

T

ppm/°C

T

= -40°C to +125°C,

REF

CREFE

A

Coefficient

extended temperature range

(Note 2)

Internal V

T

—

9

40

ppm/°C T = -40°C to +85°C,

A

REF

CREFI

Temperature Coefficient

industrial temperature range

(Note 2)

Voltage Reference Buffer

Short-Circuit Current

I

—

8

mA

ms

REFIN+/OUT shorted to A

VREF_SEL = 1(Note 9)

,

REF_SC

GND

Internal Reference

Settling Time

t

12

—

Settling to 10 ppm from final

value, bypass capacitor 1 µF

(Notes 2, 11)

VREF_SET

Internal V

Output Noise

VREF_Noise

—

14.3

—

µV

VREF_SEL = 1, AZ_VREF = 1

REF

(chopper on), T = +25°C only

A

(Note 2)

Note 1: This parameter is ensured by design and not 100% tested.

2: This parameter is ensured by characterization and not 100% tested.

3: REFIN- must be connected to ground for single-ended measurements.

4: Full-Scale Range (FSR) = 2 x V /Gain.

REF

5: This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between

the two input pins of the channel selected with the input multiplexer.

6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”.

7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.

8: DI is measured while no transfer is present on the SPI bus.

DD

9: An external buffer is recommended for external use.

10: Start-up time is the reaction time to the SPI command.

11: Settling time depends on bypass caps on REFIN+/OUT pin.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 7

MCP3461/2/4R

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV = 2.7V to 3.6V, DV = 1.8V to AV + 0.1V,

DD

MCLK = 4.9152 MHz, V

= AV , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

REF

DD

T

= -40°C to +125°C, V = -0.5 dBFS at 50 Hz.

IN

A

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

External Voltage Reference Input

Reference Voltage Range

V

0.6

—

AV

V

VREF_SEL = 0

REF

DD

(V

+ – V

-)

REF

External Noninverting Input

Voltage Reference

V

+

V

- + 0.6

REF

External Inverting Input

Voltage Reference

V

-

A

V

+ – 0.6

REF

GND

REF

DC Performance

No Missing Code Resolution

Offset Error

Resolution

16

—

Bits

µV

OSR ≥ 256 (Note 1)

V

-900/Gain

900/Gain

AZ_MUX = 0(Note 6)

AZ_MUX = 1(Notes 2, 6)

OS

-(0.05 + 0.8/

Gain)

0.05 + 0.8/

Gain

Offset Error Temperature

Coefficient

V

—

-3

—

70/Gain

300/Gain

nV/°C AZ_MUX = 0(Notes 2, 6)

AZ_MUX = 1(Notes 2, 6)

OS_DRIFT

4/Gain

—

16/Gain

+3

Gain Error

G

%

Note 6

E

Gain Error Temperature

Coefficient

G

0.5

1

2

ppm/°C Gain: 1x, 2x, 4x (Note 2)

Gain: 8x (Note 2)

E_DRIFT

4

2

8

Gain: 0.33x, 16x (Note 2)

Integral Nonlinearity

(Note 7)

INL

-10

-7

—

+10

+7

ppm

FSR

Gain = 0.33x (Note 2)

Gain = 1x (Note 2)

Gain = 2x (Note 2)

Gain = 4x (Note 2)

Gain = 8x (Note 2)

Gain = 16x (Note 2)

—

-7

—

+7

-10

-20

-32

—

+10

+20

+32

—

AV Power Supply

DC PSRR

DC CMRR

-76 – 20 x LOG

(Gain)

dB

AV varies from 2.7V to 3.6V,

DD

Rejection Ratio

V

= 0V

IN

DV Power Supply

—

-110

—

DV varies from 1.8V to 3.6V,

DD

Rejection Ratio

V

= 0V

IN

DC Common-Mode

Rejection Ratio

-126

V

varies from 0V to AV

= 0V

,

DD

INCOM

IN

Note 1: This parameter is ensured by design and not 100% tested.

2: This parameter is ensured by characterization and not 100% tested.

3: REFIN- must be connected to ground for single-ended measurements.

4: Full-Scale Range (FSR) = 2 x V

/Gain.

REF

5: This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between

the two input pins of the channel selected with the input multiplexer.

6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”.

7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.

8: DI is measured while no transfer is present on the SPI bus.

DD

9: An external buffer is recommended for external use.

10: Start-up time is the reaction time to the SPI command.

11: Settling time depends on bypass caps on REFIN+/OUT pin.

DS20006404C-page 8

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV = 2.7V to 3.6V, DV = 1.8V to AV + 0.1V,

DD

MCLK = 4.9152 MHz, V

= AV , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

REF

DD

T

= -40°C to +125°C, V = -0.5 dBFS at 50 Hz.

IN

A

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

AC Performance

Signal-to-Noise and

Distortion Ratio

SINAD

96.9

95.4

97.2

95.8

—

dB

AV = DV = V

= 3.3V

DD

REF

and T = +25°C (Note 2)

A

AV = DV = 3.3V,

DD

V

= 2.4V internal, bypass

REF

capacitor 0.1 µF and

= +25°C (Note 2)

T

A

Signal-to-Noise Ratio

SNR

THD

97

97.3

96

—

dBc

AV = DV = V

= 3.3V

DD

REF

and T = +25°C (Note 2)

A

95.7

AV = DV = 3.3V,

DD DD

V

= 2.4V internal, bypass

REF

capacitor 0.1 µF and

= +25°C (Note 2)

T

A

Total Harmonic Distortion

—

-116

-110

-105

dB

AV = DV = V

= 3.3V

DD

REF

and T = +25°C, includes the

A

first 10 harmonics (Note 2)

AV = DV = 3.3V,

DD

V

= 2.4V internal, bypass

REF

capacitor 0.1 µF and

= +25°C, includes the first

T

A

10 harmonics (Note 2)

Spurious-Free Dynamic

Range

SFDR

110

107

120

—

dBc

AV = DV = V = 3.3V

DD

REF

and T = +25°C (Note 2)

A

112.5

AV = DV = 3.3V,

DD DD

V

= 2.4V internal, bypass

REF

capacitor 0.1 µF and

T

= +25°C (Note 2)

A

Input Channel Crosstalk

CTALK

—

-130

—

dB

V

= 0V, Perturbation = 0 dB at

IN

50 Hz, applies to all

perturbation channels and all

input channels

AC Power Supply Rejection

Ratio

AC PSRR

AC CMRR

—

-75 – 20 x LOG

(Gain)

—

dB

V

= 0V, DV = 3.3V,

IN DD

AV = 3.3V + 0.3V , 50 Hz

DD

P

AC Common-Mode

Rejection Ratio

-122

V

= 0 dB at 50 Hz,

INCOM

= 0V

IN

Note 1: This parameter is ensured by design and not 100% tested.

2: This parameter is ensured by characterization and not 100% tested.

3: REFIN- must be connected to ground for single-ended measurements.

4: Full-Scale Range (FSR) = 2 x V /Gain.

REF

5: This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between

the two input pins of the channel selected with the input multiplexer.

6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”.

7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.

8: DI is measured while no transfer is present on the SPI bus.

DD

9: An external buffer is recommended for external use.

10: Start-up time is the reaction time to the SPI command.

11: Settling time depends on bypass caps on REFIN+/OUT pin.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 9

MCP3461/2/4R

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV = 2.7V to 3.6V, DV = 1.8V to AV + 0.1V,

DD

MCLK = 4.9152 MHz, V

= AV , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

REF

DD

T

= -40°C to +125°C, V = -0.5 dBFS at 50 Hz.

IN

A

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

ADC Timing Parameters

Sampling Frequency

Output Data Rate

DMCLK

DRCLK

See Table 5-6

256

MHz

ksps

ms

See Figure 4-1

Data Conversion Time

ADC Start-up Delay

T

CONV

ADC_SETUP

T

—

0

—

DMCLK ADC_MODE[1:0] bits change

periods from ‘0x’ to ‘1x’

0

DMCLK ADC_MODE[1:0] bits change

periods from ‘10’ to ‘11’

Conversion Start Pulse Low

Time

T

1

—

DMCLK

periods

STP

Scan Mode Time Delays

T

—

512

DMCLK Time delay between sampling

periods channels

DLY_SCAN

T

0

16777215

OSR-16

—

DMCLK Time interval between Scan

periods cycles

TIMER_SCAN

Data Ready Pulse Low Time

Data Ready Pulse High Time

T

—

16

—

DMCLK See Figure 5-16

periods

DRL

DRH

T

DMCLK See Figure 5-16

periods

Data Transfer Time to DR

(Data Ready)

t

50

ns

DODR

Modulator Output Valid from

AMCLK High

t

100

200

ns

2.7V ≤ DV ≤ 3.6V

DD

DOMDAT

1.8V ≤ DV ≤ 2.7V

DD

External Master Clock Input (CLK_SEL[1] = 0)

Master Clock Input

Frequency Range

f

1

—

20

10

55

MHz

%

DV ≥ 2.7V

DD

MCLK_EXT

DV < 2.7V

DD

Master Clock Input Duty Cycle

f

45

MCLK_DUTY

Internal Clock Oscillator

Internal Master Clock

Frequency

f

3.3

—

6.6

—

MHz

µs

CLK_SEL[1] = 1

MCLK_INT

Internal Oscillator Start-up

Time

t

10

CLK_SEL[1] changes from ‘0’

to ‘1’, time to stabilize the clock

frequency to ±1 kHz of the final

value (Note 10)

OSC_STARTUP

Internal Oscillator Current

Consumption

IDD

—

30

±5

—

µA

°C

Should be added to DI when

CLK_SEL[1:0] = 1x

OSC

DD

Internal Temperature Sensor

Temperature Measurement

Accuracy

T

See Section 5.1.2 “Internal

Temperature Sensor”

Acc

Note 1: This parameter is ensured by design and not 100% tested.

2: This parameter is ensured by characterization and not 100% tested.

3: REFIN- must be connected to ground for single-ended measurements.

4: Full-Scale Range (FSR) = 2 x V

/Gain.

REF

5: This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between

the two input pins of the channel selected with the input multiplexer.

6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”.

7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.

8: DI is measured while no transfer is present on the SPI bus.

DD

9: An external buffer is recommended for external use.

10: Start-up time is the reaction time to the SPI command.

11: Settling time depends on bypass caps on REFIN+/OUT pin.

DS20006404C-page 10

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

TEMPERATURE SPECIFICATIONS

Electrical Specifications: Unless otherwise specified, all parameters apply for T_A= -40°C to +125°C,

AV_DD= 2.7V to 3.6V, DV_DD= 1.8V to AV_DD+ 0.1V, D_GND= A_GND= 0V.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistance

Thermal Resistance, 20-Lead TSSOP

Thermal Resistance, 20-Lead UQFN

T_A

-40

-65

—

+125

+150

°C

_JA

—

44

50

—

°C/W

Note 1: The internal Junction Temperature (T_J) must not exceed the absolute maximum specification of +150°C.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 11

MCP3461/2/4R

TABLE 1-1:

SPI SERIAL INTERFACE TIMING SPECIFICATIONS FOR DV_DD= 2.7V TO 3.6V

Electrical Specifications: DV_DD= 2.7V to 3.6V, T_A= -40°C to +125°C, C_LOAD= 30 pF. See Figure 1-1.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Serial Clock Frequency

CS Setup Time

f_SCK

t_CSS

t_CSH

t_CSD

t_SU

—

25

50

5

—

20

—

25

—

25

MHz

ns

CS Hold Time

CS Disable Time

Data Setup Time

Data Hold Time

t_HD

10

20

50

—

0

Serial Clock High Time

Serial Clock Low Time

Serial Clock Delay Time

Serial Clock Enable Time

Output Valid from SCK Low

Output Hold Time

t_HI

t_LO

t_CLD

t_CLE

t_DO

t_HO

Output Disable Time

t_DIS

—

Measured with a 1.5 mA

pull-up current source on

SDO pin

POR IRQ Disable Time

t_CSIRQ

—

52

25

ns

Measured with a 1.5 mA

pull-up current source on

IRQ pin

Output Valid from CS Low

t_CSSDO

SDO toggles to logic low at

each communication start (CS

falling edge)

DS20006404C-page 12

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

TABLE 1-2:

SPI SERIAL INTERFACE TIMING SPECIFICATIONS FOR DV_DD= 1.8V TO 2.7V

(10 MHz MAXIMUM SCK FREQUENCY)

Electrical Specifications: DV_DD= 1.8V to 2.7V, T_A= -40°C to +125°C, C_LOAD= 30 pF. See Figure 1-1.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Serial Clock Frequency

CS Setup Time

f_SCK

t_CSS

t_CSH

t_CSD

t_SU

—

50

—

10

—

50

—

50

MHz

ns

CS Hold Time

100

10

CS Disable Time

Data Setup Time

Data Hold Time

t_HD

20

Serial Clock High Time

Serial Clock Low Time

Serial Clock Delay Time

Serial Clock Enable Time

Output Valid from SCK Low

Output Hold Time

t_HI

40

t_LO

40

t_CLD

t_CLE

t_DO

100

—

t_HO

0

Output Disable Time

t_DIS

—

Measured with a 1.5 mA

pull-up current source on

SDO pin

POR IRQ Disable Time

t_CSIRQ

—

60

50

ns

Measured with a 1.5 mA

pull-up current source on

IRQ pin

Output Valid from CS Low

t_CSSDO

SDO toggles to logic low at

each communication start (CS

falling edge)

TABLE 1-3:

DIGITAL I/O DC SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, all parameters apply at DV_DD= 1.8V to 3.6V,

T_A= -40°C to +125°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Schmitt Trigger High-Level

Input Voltage

V_IH

0.7 x DV_DD

—

V

Schmitt Trigger Low-Level

Input Voltage

V_IL

—

0.3 x DV_DD

—

V

Hysteresis of Schmitt Trigger

Inputs

V_HYS

200

mV

Low-Level Output Voltage

High-Level Output Voltage

Input Leakage Current

V_OL

V_OH

I_{LI_D}

—

0.8 x DV_DD

—

0.2 x DV_DD

V

I_OL= +1.5 mA

—

1

I_OH= -1.5 mA

µA

Pins configured as inputs

or high-impedance outputs

 2020-2021 Microchip Technology Inc.

DS20006404C-page 13

MCP3461/2/4R

t_{CS D}

CS

t_SCK

t_HI

t_LO

t_CLE

t_{CS S}

t_CSH

t_CLD

SPI mode 1,1

SPI mode 0,0

SCK

SDI

SPI mode 0,0

Device Latches SDI

on SCK Rising Edge

Device Latches SDO

on SCK Falling Edge

t_HD

t_SU

t_DO

t_HO

t_DIS

SDO

t_CSSDO

High-Z

0 (for first two bits on SDO)

0

FIGURE 1-1:

Serial Output Timing Diagram.

DS20006404C-page 14

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

0

-20

-40

0

-20

-40

V_IN= -0.5 dBFS @ 50 Hz

V_IN= -0.5 dBFS @ 1 kHz

FFT 16384 samples

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

-180

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

Frequency (Hz)

FIGURE 2-1:

FFT Output Spectrum,

FIGURE 2-4:

FFT Output Spectrum,

f_in= 50 Hz Input.

f_in= 1 kHz (Internal V_REF).

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

70000

V_IN= -0.5 dBFS @ 1 kHz

FFT 16384 samples

V_IN^ꢀ= 0V

CONV_MODE[1:0] = 11ꢀ

60000

64000 samples

Bin size = 1 LSE

50000

Histograms may show up

40000

to 2 bins equally

distributed if offset is close

to a round LSE value

30000

(Intrinsic noise << 16-bit

quantization noise)

20000

10000

0

-10 -9 -8 -7 -6 -5 -4 -3 -2 -1

ADC Output Code (LSE)

0

500

1000

1500

2000

2500

Frequency (Hz)

FIGURE 2-2:

FFT Output Spectrum,

FIGURE 2-5:

Output Noise Histogram.

f_in= 1 kHz Input.

70000

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

V_IN= -0.5 dBFS @ 50 Hz

FFT 16384 samples

V_IN= 0V

CONV_MODE[1:0] = 11

64000 samples

60000

50000

40000

30000

20000

10000

0

Bin size = 1 LSB

Histograms may show

up to 2 bins equally

distributed if offset is

close to a round LSB

value

(Intrinsic noise << 16-bit

quantization noise)

-12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2

ADC Output Code (LSB)

0

500

1000

1500

2000

2500

Frequency (Hz)

FIGURE 2-3:

FFT Output Spectrum,

FIGURE 2-6:

Output Noise Histogram

f_in= 50 Hz (Internal V_REF).

(Internal V_REF).

 2020-2021 Microchip Technology Inc.

DS20006404C-page 15

MCP3461/2/4R

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

6

4

120

AVDD = VREF = 2.7V, -40°C

AVDD = VREF = 2.7V, +125°C

AVDD = VREF = 3.6V, -40°C

AVDD = VREF = 3.6V, +125°C

100

80

2

Gain = 1x

60

GAIN = 0.33

0

GAIN = 1

40

GAIN = 2

-2

-4

-6

GAIN = 4

20

GAIN = 8

GAIN = 16

0

-100

-50

0

50

100

Oversampling Ratio (OSR)

Differential Input Voltage (% of V_REF

)

FIGURE 2-7:

INL vs. Input Voltage.

FIGURE 2-10:

SINAD vs. OSR.

5

4.5

4

3.5

3

2.5

2

1.5

1

120

100

80

60

40

20

0

AVDD = VREF = 2.7V, -40°C

AVDD = VREF = 2.7V, +125°C

AVDD = VREF = 3.6V, -40°C

AVDD = VREF = 3.6V, +125°C

Gain = 1x

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

0.5

0

-100

-50

0

50

100

Oversampling Ratio (OSR)

Differential Input Voltage (% of V_REF

)

FIGURE 2-11:

SNR vs. OSR.

FIGURE 2-8:

Output Noise vs. Input

Voltage.

20

0

-20

AV_DD= V_REF= 2.7V, -40°C

AV_DD= V_REF= 2.7V, +125°C

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

18

16

14

12

10

8

6

4

2

0

AV_DD= V_REF= 3.6V, -40°C

AV_DD= V_REF= 3.6V, +125°C

-40

-60

-80

-100

-120

-140

0.25

0.5

1

2

4

8

16

Analog Gain

Oversampling Ratio (OSR)

FIGURE 2-12:

THD vs. OSR.

FIGURE 2-9:

Maximum INL vs. Gain.

DS20006404C-page 16

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

0

140

120

100

80

GAIN = 0.33

-20

-40

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

-60

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

-80

60

-100

-120

-140

40

20

0

Oversampling Ratio (OSR)

FIGURE 2-13:

SFDR vs. OSR, External

FIGURE 2-16:

SFDR vs. OSR.

V_REF

.

140

120

100

80

120

100

80

60

40

20

0

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

60

40

20

0

Oversampling Ratio (OSR)

FIGURE 2-17:

SFDR vs. OSR, Internal

FIGURE 2-14:

SINAD vs. OSR, Internal

V_REF

.

V_REF

.

50

45

40

35

30

25

20

15

10

5

120

100

80

60

40

20

0

33 devices x 3 lots

Bin Size: 0.05 dB

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

0

Oversampling Ratio (OSR)

Signal-to-Noise Ratio (dB)

FIGURE 2-18:

SNR Distribution Histogram.

FIGURE 2-15:

SNR vs. OSR, Internal V_REF.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 17

MCP3461/2/4R

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

45

40

35

30

25

20

15

10

5

40

33 devices x 3 lots

Bin Size: 0.05 dB

33 devices x 3 lots

Bin Size: 0.05 dB

35

30

25

20

15

10

5

0

Signal-to-Noise Ratio (dB)

Signal-to-Noise-and-Distortion Ratio (dB)

FIGURE 2-19:

SINAD Distribution

FIGURE 2-22:

SNR Distribution Histogram,

Histogram.

Internal V_REF.

20

18

16

14

12

10

8

6

4

2

0

40

35

30

25

20

15

10

5

33 devices x 3 lots

Bin Size: 0.5 dB

33 devices x 3 lots

Bin Size: 0.05 dB

0

Signal-to-Noise-and-Distortion Ratio (dB)

Total Harmonic Distortion (dBc)

FIGURE 2-20:

THD Distribution Histogram.

FIGURE 2-23:

SINAD Distribution

Histogram, Internal V_REF

.

25

20

15

10

5

35

30

25

20

15

10

5

33 devices x 3 lots

Bin Size: 1.0 dB

33 devices x 3 lots

Bin Size: 0.5 dB

0

Total Harmonic Distortion (dBc)

Spurious-Free Dynamic Range (dBc)

FIGURE 2-21:

SFDR Distribution

FIGURE 2-24:

THD Distribution Histogram,

Histogram.

Internal V_REF.

DS20006404C-page 18

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

0

50

45

40

35

30

25

20

15

10

5

GAIN=0.33

33 devices x 3 lots

GAIN=1

GAIN=2

GAIN=4

GAIN=8

GAIN=16

Bin Size: 1.0 dB

-20

-40

-60

-80

-100

-120

0

-50

-25

0

25

50

75

100

125

Spurious-Free Dynamic Range (dBc)

Temperature (°C)

FIGURE 2-25:

SFDR Distribution

FIGURE 2-28:

THD vs. Temperature.

Histogram, Internal V_REF

.

120

100

80

60

40

20

0

140

120

100

80

GAIN=0.33

60

GAIN=1

GAIN=2

GAIN=4

GAIN=8

GAIN=16

GAIN=1

GAIN=2

GAIN=4

GAIN=8

GAIN=16

40

20

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (°C)

FIGURE 2-26:

SINAD vs. Temperature.

FIGURE 2-29:

SFDR vs. Temperature.

120

100

80

60

40

20

0

120

100

80

60

40

20

0

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

GAIN=0.33

GAIN=1

GAIN=2

GAIN=4

GAIN=8

GAIN=16

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (°C)

FIGURE 2-27:

SNR vs. Temperature.

FIGURE 2-30:

SINAD vs. Temperature,

Internal V_REF

.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 19

MCP3461/2/4R

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

140

120

100

120

100

80

60

40

20

0

80

GAIN = 0.33

60

40

20

0

SINAD (dB)

SNR (dB)

-THD (dBc)

SFDR (dBc)

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

V_REF= 2.7V

AV_DD= 3.3V

-50

-25

0

25

50

75

100

125

-8

-6

-4

-2

0

2

20

Temperature (°C)

Analog Input Signal Amplitude (dBFS)

FIGURE 2-31:

SNR vs. Temperature,

FIGURE 2-34:

Input Signal Amplitude.

Dynamic Performance vs.

Internal V_REF

.

100

95

90

85

80

75

70

0

-20

GAIN=0.33

GAIN=1

GAIN=2

GAIN=4

GAIN=8

GAIN=16

BOOST = 0.5x

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

-40

-60

-80

-100

-120

-50

-25

0

25

50

75

100

125

0

5ꢀ

10ꢀ

15

Temperature (°C)

$MCLK Frequency (MHz)

FIGURE 2-32:

THD vs. Temperature,

FIGURE 2-35:

(Boost = 0.5x, External V_REF).

SINAD vs. AMCLK

Internal V_REF

.

100

95

90

85

80

75

70

GAIN=0.33

GAIN=1

140

120

100

80

GAIN=2

GAIN=4

GAIN=8

GAIN=16

BOOST = 0.66x

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

60

40

20

0

-50

-25

0

25

50

75

100

125

0

5ꢀ

10

15

Temperature (°C)

$MCLK Frequency (MHz)

FIGURE 2-33:

Internal V_REF

SFDR vs. Temperature,

FIGURE 2-36:

(Boost = 0.66x, External V_REF).

SINAD vs. AMCLK

.

DS20006404C-page 20

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

100

95

90

85

80

75

70

100

GAIN = 0.33

GAIN = 1

95

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

BOOST = 0.66x

90

85

80

75

70

GAIN=0.33

GAIN=1

GAIN=2

GAIN=4

GAIN=8

GAIN=16

BOOST = 1x

0

5

10

15

20

0

5ꢀ

10ꢀ

15

20

AMCLK Frequency (MHz)

$MCLK Frequency (MHz)

FIGURE 2-37:

SINAD vs. AMCLK

FIGURE 2-40:

SINAD vs. AMCLK

(Boost = 1x, External V_REF).

(Boost = 0.66x, Internal V_REF).

100

95

120

115

110

105

100

95

GAIN=0.33

GAIN=1

GAIN=2

GAIN=4

GAIN=8

GAIN=16

BOOST = 2x

90

85

90

85

80

75

GAIN = 0.33

80

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

75

70

BOOST = 1x

10

70

0

5

15

20

0

5ꢀ

10ꢀ

15

20

AMCLK Frequency (MHz)

$MCLK Frequency (MHz)

FIGURE 2-38:

SINAD vs. AMCLK

FIGURE 2-41:

SINAD vs. AMCLK

(Boost = 2x, External V_REF).

(Boost = 1x, Internal V_REF).

100

95

90

85

80

75

70

120

115

110

105

100

95

90

85

80

75

GAIN = 0.33

GAIN = 1

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

BOOST = 0.5x

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

BOOST = 2x

70

0

5

10

15

20

0

5

10

15

20

AMCLK Frequency (MHz)

FIGURE 2-39:

SINAD vs. AMCLK

FIGURE 2-42:

SINAD vs. AMCLK

(Boost = 0.5x, Internal V_REF).

(Boost = 2x, Internal V_REF).

 2020-2021 Microchip Technology Inc.

DS20006404C-page 21

MCP3461/2/4R

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

1000

800

600

400

200

100

95

90

85

80

75

70

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

AV_DD= 3.3V

AZ_MUX = 0

0

BOOST=1x,

AVDD=2.7V

BOOST=1x,

AVDD=3.3V

BOOST=1x,

AVDD=3.6V

-200

-400

-600

-800

-1000

GAIN = 1x

-50

-25

0

25

50

75

100

125

0

5ꢀ

10ꢀ

15

20

$MCLK Frequency (MHz)

Temperature (°C)

FIGURE 2-43:

SINAD vs. AMCLK vs. AV_DD

.

FIGURE 2-46:

Offset Error vs. Temperature

(AZ_MUX = 0).

1,200

120

100

80

60

40

20

0

GAIN = 0.33

T_A= 25°C,

AZ_MUX = 1

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

1,000

800

600

400

200

0

OSR = 32

OSR = 64

OSR = 128

OSR = 256

2.7

3

3.3

3.6

Analog Input Signal Frequency (Hz)

AV_DDSupply Voltage (V)

FIGURE 2-44:

SINAD vs. Input Signal

FIGURE 2-47:

Offset Error vs. AV_DD

Frequency.

(AZ_MUX = 1).

0

-200

-400

-600

-800

-1000

1,000

800

600

400

200

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

0

-200

-400

-600

-800

-1,000

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

-1200

-1400

T_A= 25°C,

AV_DD= 3.3V

AZ_MUX = 1

AZ_MUX = 0

2.7

3

3.3

3.6

-50

-25

0

25

50

75

100 125

AV_DDSupply Voltage (V)

Temperature (°C)

FIGURE 2-45:

Offset Error vs. AV_DD

FIGURE 2-48:

Offset Error vs. Temperature

(AZ_MUX = 0).

(AZ_MUX = 1).

DS20006404C-page 22

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

10K

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

1K

100

10

GAIN = 8

GAIN = 16

T_A= 25°C

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

1

2.7

3

3.3

3.6

1

5

25

AV_DDSupply Voltage (V)

MCLK Frequency (MHz)

FIGURE 2-49:

Gain Error vs. AV_DD

.

FIGURE 2-52:

Differential Input Impedance

vs. MCLK.

2

1.8

1.6

1.4

1.2

1

10K

1K

0.8

0.6

0.4

0.2

0

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

100

CS_SEL = 01

CS_SEL = 10

CS_SEL = 11

AV_DD= 3.3V

10

1

100

10K

1M

100M

-50

-25

0

25

50

75

100

125

Differential Input Impedance (Ω)

Temperature (°C)

FIGURE 2-50:

Gain Error vs. Temperature.

FIGURE 2-53:

ADC Output Code vs.

Differential Input Impedance, Burnout Current

Sources Enabled.

2

5

4

3

2

1

61 Devices

1.8

1.6

1.4

1.2

1

AI_DDBOOST = 2x

AI_DDBOOST = 1x

0

-1

-2

-3

-4

-5

0.8

0.6

0.4

0.2

0

AI_DDBOOST = 0.66x

AI_DDBOOST = 0.5x

DI_DD

-50

-25

0

25

50

75

100

125

0

5

10

15

20

Temperature (°C)

MCLK Frequency (MHz)

FIGURE 2-54:

DI_DDand AI_DDvs. MCLK.

FIGURE 2-51:

Temperature Sensor

Accuracy vs. Temperature (First-Order Best Fit).

 2020-2021 Microchip Technology Inc.

DS20006404C-page 23

MCP3461/2/4R

Note:

Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, MCLK = 4.9152 MHz, V_IN= -0.5 dBFS

at 50 Hz, V_REF= AV_DD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks

are centered at their bin center.

2.5

2

2.41186

AI_DDBOOST = 2x

2.41185

2.41184

2.41183

1.5

1

AI_DDBOOST = 1x

2.41182

AI_DDBOOST = 0.66x

2.41181

AI_DDBOOST = 0.5x

2.4118

0.5

0

2.41179

2.41178

DI_DD

Output Noise = 14.3 ȝV_RMS

100 Samples (100 ms per sample)

0

2

4

6

8

10

1.8

2.1

2.4

2.7

3

3.3

3.6

Time (s)

AV_DD/DV_DD(V)

FIGURE 2-55:

DI_DDand AI_DDvs. DV_DD

FIGURE 2-58:

V_REFOutput vs. Time

and AV_DD

.

(T = +25°C, AV_DD= 3.3V).

2.5

2.415

11 Devices x 3 Lots

AI_DDBOOST = 2x

2.41

2.405

2.4

2

1.5

1

AI_DDBOOST = 1x

2.395

2.39

AI_DDBOOST = 0.66x

AI_DDBOOST = 0.5x

0.5

0

2.385

2.38

0

5

10

15

20

-50

-25

0

25

50

75

100

125

Temperature (°C)

MCLK Frequency (MHz)

FIGURE 2-56:

AI_DDvs. MCLK (Internal

FIGURE 2-59:

V_REFOutput Voltage vs.

V_REF).

Temperature (AV_DD= 3.3V).

2.5

2

2.3988

2.3987

2.3986

2.3985

2.3984

2.3983

2.3982

2.3981

2.398

AI_DDBOOST = 2x

1.5

1

AI_DDBOOST = 1x

AI_DDBOOST = 0.66x

AI_DDBOOST = 0.5x

0.5

0

2.3979

2.3978

2.7 2.8 2.9

3

3.1 3.2 3.3 3.4 3.5 3.6

-50

-25

0

25

50

75

100

125

AV_DD(V)

Temperature (^ƕC)

FIGURE 2-57:

Temperature.

DI_DDand AI_DDvs.

FIGURE 2-60:

Voltage vs. AV_DD

Internal V_REFOutput

.

DS20006404C-page 24

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

EQUATION 2-1:

2.1

Noise Specifications

2  V

Table 2-1 and Table 2-2 summarize the noise

performance of the MCP3461/2/4R devices. The noise

performance is an analog gain function of the ADC

(digital gain does not change the noise performance

significantly) and the OSR, chosen through the user

interface. With a higher gain, the input referred noise is

reduced. With a higher OSR setting, the noise is also

reduced as the oversampling diminishes both thermal

noise and quantization noise induced by the

Delta-Sigma modulator loop.

REF







ln ----------------------------------------------------



GAIN  RMS (Noise)

ER

= ----------------------------------------------------------------

RMS

ln2

EQUATION 2-2:

2  V

REF







ln ----------------------------------------------------------------------



GAIN  Peak-to-Peak Noise

ER

= ---------------------------------------------------------------------------------

pk – pk

ln2

The noise value generally increases when temperature

is higher as thermal noise is dominant for all OSR

larger than 32. For high OSR settings (> 512), the

thermal noise is largely dominant and increases

proportionally to the square root of the absolute

temperature. The performance in the following tables

has been measured with the device placed in Continu-

ous Conversion mode, with the differential input

voltage equal to V_IN= 0V, default conditions for the

register map and MCLK = 4.9152 MHz.

Due to the nature of the noise, the performance

detailed in the noise tables can vary significantly from

one measurement to another. They present an averag-

ing of the performance over a large distribution of parts

over multiple lots. They give the typical expectation of

the noise performance, but performance can be better

or worse if a limited number of measurements is

performed. For large gain and OSR combinations, if the

noise performance is comparable to the quantization

step (1 LSb), the performance is limited to 0.5 LSb for

the RMS noise and 1 LSb for the peak-to-peak noise

(same limits for Effective Resolution values).

The noise performance is also a function of the

measurement duration. For short duration measure-

ments (low number of consecutive samples), the

peak-to-peak noise is usually reduced because the

crest factor (ratio between the RMS noise and

peak-to-peak noise) is reduced. This is only a conse-

quence of the noise distribution being Gaussian by

nature (see Figure 2-5 for noise histogram example

and fitting with an ideal Gaussian distribution). The

noise specifications have been measured with a

sample size of 16384 samples for low OSR values and

have been capped to approximately 80 seconds for the

16384 samples leading to a larger duration. The noise

specifications are expressed in two different values,

which lead to the same quantity. It may be more practi-

cal to choose one of these representations depending

on the desired application.

These figures correspond to the resolution limit of the

device as peak-to-peak noise cannot be better than

1 LSb. Similarly, if the intrinsic RMS noise of the device

is much smaller than 0.5 LSb, it may lead to histogram

with either one or two bins, depending on the relative

position of the input voltage versus the possible

quantized outputs of the ADC. If the position is exactly

in between two quantization steps, the histogram of

output noise will have two bins with exactly 50% occur-

rence on each. This case gives an RMS noise of a

0.5 LSb value, which is therefore, used as a cap of the

performance for the sake of clarity and a better

representation on the noise tables.

The noise specifications are improved by a ratio of

approximately √2 (or 0.5-bit Effective Resolution) when

the AZ_MUX setting is enabled. However, the output

data rate is significantly reduced (see Figure 5-5 and

Table 5-6).

In Table 2-1, the RMS (Root Mean Square) noise is the

variance of the ADC output code, expressed in µV_RMS

,

and input referred with Equation 5-5. The peak-to-peak

noise values are in parentheses. The peak-to-peak

noise is the difference between the maximum and

minimum code observed during the complete time of

the measurement (see Equation 5-5).

The digital gain added for Gain = 32x and 64x settings

is not significant for the noise performance, and there-

fore, the noise values can be extracted from the

Gain = 16x columns. Effective Resolution performance

is degraded by one bit for Gain = 32x and two bits for

Gain = 64x, compared to Gain = 16x performance.

In Table 2-2, the noise is expressed in Effective

Resolution (ER). The Effective Resolution is a ratio of

the full-scale range of the ADC (that depends on V_REF

and gain) and the noise performance of the device. The

Effective Resolution can be determined from the RMS

or peak-to-peak noise with the following equations.

Note:

All Output Noise performance-related

tables and figures are with reference to

the input (i.e., Input Referred).

 2020-2021 Microchip Technology Inc.

DS20006404C-page 25

MCP3461/2/4R

TABLE 2-1:

NOISE RMS LEVEL VS. GAIN VS. OSR (AV_DD= DV_DD= V_REF= 3.3V, T_A= +25°C)

RMS (Peak-to-Peak) Noise (µV)

TOTAL

OSR

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

32

388.9 (2829.9)

151.1 (564)

130.2 (950)

50.4 (184.6)

50.4 (107.4)

50.4 (100.7)

65.7 (481.7)

25.2 (102.4)

25.2 (57.1)

25.2 (50.4)

33.2 (240.9)

12.6 (56.2)

12.6 (33.6)

12.6 (25.2)

17 (125.5)

6.3 (34.8)

6.3 (21.4)

6.3 (15.9)

6.3 (12.6)

8.9 (66.9)

3.4 (22.5)

3.2 (14.3)

3.2 (10.5)

3.2 (6.9)

3.2 (6.3)

64

128

151.1 (302.1)

256

512

1024

2048

4096

8192

16384

20480

24576

40960

49152

81920

98304

TABLE 2-2:

EFFECTIVE RESOLUTION VS. GAIN VS. OSR (AV_DD= DV_DD= V_REF= 3.3V,

T_A= +25°C)

Effective Resolution RMS (Peak-to-Peak) (bits)

TOTAL

OSR

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

32

15.6 (12.8)

17 (15.2)

17 (16)

15.6 (12.8)

17 (15.2)

17 (15.9)

17 (16)

15.6 (12.7)

17 (15)

17 (15.9)

17 (16)

15.6 (12.7)

17 (14.9)

17 (15.6)

17 (16)

15.6 (12.7)

17 (14.5)

17 (15.3)

17 (15.7)

17 (16)

15.5 (12.6)

16.9 (14.2)

17 (14.9)

17 (15.4)

17 (15.9)

17 (16)

64

128

256

512

1024

2048

4096

8192

16384

20480

24576

40960

49152

81920

98304

17 (16)

Note:

To calculate noise RMS level and Effective Resolution (Bits) for a given gain and data rate, refer to the OSR

setting and associated data rate relationship shown in Table 5-6.

DS20006404C-page 26

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

TABLE 2-3:

OUTPUT NOISE VS. GAIN VS. OSR (AV_DD= DV_DD= 3.3V, V_REF= 2.4V INTERNAL,

T_A= +25°C)

RMS (Peak-to-Peak) Noise (µV)

TOTAL

OSR

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

32

281.5 (2167.7)

111.0 (525.3)

111.0 (325.5)

111.0 (222.0)

93.7 (739.7)

36.6 (178.2)

36.6 (112.3)

36.6 (80.6)

36.6 (73.2)

47.5 (372.3)

18.3 (92.8)

18.3 (65.9)

18.3 (41.5)

18.3 (36.6)

24.2 (191.7)

9.2 (53.1)

9.2 (34.2)

9.2 (27.5)

9.2 (18.9)

9.2 (18.3)

12.6 (96.4)

4.8 (33.6)

4.6 (21.7)

4.6 (14.7)

4.6 (10.1)

4.6 (9.2)

6.8 (52.9)

3.0 (22.1)

2.3 (14.2)

2.3 (10.8)

2.3 (6.7)

2.3 (5.3)

2.3 (4.6)

64

128

256

512

1024

2048

4096

8192

16384

20480

24576

40960

49152

81920

98304

TABLE 2-4:

EFFECTIVE RESOLUTION VS. GAIN VS. OSR (AV_DD= DV_DD= 3.3V, V_REF= 2.4V

INTERNAL, T_A= +25°C)

Effective Resolution RMS (Peak-to-Peak) (bits)

TOTAL

OSR

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

32

15.7 (12.7)

17.0 (14.8)

17.0 (15.5)

17.0 (16.0)

15.7 (12.7)

17.0 (14.7)

17.0 (15.5)

17.0 (15.9)

17.0 (16.0)

15.6 (12.7)

17.0 (14.7)

17.0 (15.2)

17.0 (15.9)

17.0 (16.0)

15.6 (12.6)

17.0 (14.5)

17.0 (15.1)

17.0 (15.5)

17.0 (16.0)

15.5 (12.6)

16.9 (14.1)

17.0 (14.8)

17.0 (15.4)

17.0 (15.9)

17.0 (16.0)

15.4 (12.5)

16.6 (13.8)

17.0 (14.4)

17.0 (14.8)

17.0 (15.5)

17.0 (15.8)

17.0 (16.0)

64

128

256

512

1024

2048

4096

8192

16384

20480

24576

40960

49152

81920

98304

Note:

To calculate noise RMS level and Effective Resolution (Bits) for a given GAIN and data rate, refer to the

OSR setting and associated data rate relationship shown in Table 5-6.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 27

MCP3461/2/4R

NOTES:

DS20006404C-page 28

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

3.0

PIN DESCRIPTIONS

TABLE 3-1:

PIN FUNCTION TABLE

MCP3461R MCP3462R MCP3464R MCP3461R MCP3462R MCP3464R

Symbol

Description

20-Lead UQFN

20-Lead TSSOP

1

2

3

4

REFIN-

Inverting Reference Input Pin

REFIN+/OUT Noninverting Reference Input Pin

or Internal Voltage Reference

Output

3

4

5

6

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CS

Analog Input 0 Pin

Analog Input 1 Pin

Analog Input 2 Pin

Analog Input 3 Pin

Analog Input 4 Pin

Analog Input 5 Pin

Analog Input 6 Pin

Analog Input 7 Pin

—

5

6

—

7

8

6

8

—

11

7

—

13

9

8

10

11

12

9

10

Serial Interface Chip Select

Digital Input Pin

12

13

14

15

16

14

15

16

17

18

SCK

SDI

Serial Interface Digital Clock Input

Serial Interface Digital Data Input

SDO

Serial Interface Digital Data

Output Pin

IRQ/MDAT Interrupt Output Pin or Modulator

Output Pin

MCLK

Master Clock Input or Analog

Master Clock Output Pin

17

18

19

20

19

20

1

D

Digital Ground Pin

GND

DV

Digital Supply Voltage Pin

Analog Supply Voltage Pin

Analog Ground Pin

Not Connected

DD

AV

DD

2

A

GND

5, 6, 7, 8, 9, 7, 8, 9, 10

10

—

7, 8, 9, 10,

11, 12

9, 10, 11,

12

—

NC

21

—

EP

Exposed Thermal Pad, Internally

Connected to A

GND

 2020-2021 Microchip Technology Inc.

DS20006404C-page 29

MCP3461/2/4R

The input signal level is multiplied by the internal

programmable analog gain at the front end of the

Delta-Sigma modulator. For single-ended input

measurements, the user can select V_IN- to be internally

3.1

Differential Reference Voltage

Inputs: REFIN+/OUT, REFIN-

The REFIN+/OUT pin is the noninverting differential

reference input (V_REF+) when VREF_SEL = 0. When

VREF_SEL = 1, it is the internal voltage reference out-

put voltage as well as the ADC voltage noninverting

reference pin.

connected to A_GND

.

The differential input voltage should not exceed an

absolute of ±V_REF/Gain for accurate measurement. If

the input is out of range, the converter output code will

be saturated or overloaded depending on how the out-

put data format (DATA_FORMAT[1:0]) is selected. See

Section 5.6 “ADC Output Data Format” for further

information on the ADC output coding.

The REFIN- pin is the inverting differential reference

input (V_REF-).

For single-ended reference applications, the REFIN-

pin should be directly connected to A_GND

.

The absolute voltage on each of the analog signal

input pins can range from A_GND– 0.1V to V_DD+ 0.1V.

Any voltage above or below this range will cause leak-

age currents through the Electrostatic Discharge

(ESD) diodes at the input pins. This ESD current can

cause unexpected performance of the device. The

Common-mode of the analog inputs should be chosen

such that both the differential analog input range and

the absolute voltage range on each pin are within the

specified operating range defined in the Electrical

Characteristics table.

The differential reference voltage pins must respect

this condition at all times: 0.6V ≤ V_REF≤ AV_DD. The

differential reference voltage input is given by the

following equation:

EQUATION 3-1:

V

= V

– V

REF

REF+

REF-

For optimal ADC accuracy, appropriate bypass

capacitors should be placed between REFIN+/OUT

and A_GNDat all times. Using a 0.1 µF and a 10 µF

ceramic capacitor can help to decouple the reference

voltage around the sampling frequency (which would

lead to aliasing noise in the baseband). These bypass

capacitors are not mandatory for correct ADC opera-

tion, but removing these capacitors may degrade the

accuracy of the ADC.

3.3

SPI Serial Interface

Communication Pins

The SPI interface is compatible with both SPI Mode 0,0

and 1,1.

3.3.1

CHIP SELECT (CS)

3.2

Analog Inputs (CHn): Differential

or Single-Ended

This is the SPI Chip Select pin that enables/disables

the SPI serial communication. The CS falling edge

initiates the serial communication and the rising edge

terminates the communication. No communication can

take place when this pin is in a Logic High state. This

input is Schmitt Triggered.

The CHn pins are the analog input signal pins for the

ADC. Two analog multiplexers are used to connect the

CHn pins to the V_IN+/V_IN- analog inputs of the ADC.

Each multiplexer independently selects one input to be

connected to an ADC input (V_IN+ or V_IN-). Each CHn

pin can either be connected to the V_IN+ or V_IN- inputs

of the ADC. This multiplexer selection is controlled by

either the MUX register in MUX mode or the SCAN

register in Scan mode. See Figure 5-1 for more details

on the multiplexer structure.

3.3.2

SERIAL DATA CLOCK (SCK)

This is the serial clock input pin for SPI communication.

This input has a Schmitt Trigger structure. The maxi-

mum SPI clock speed is 20 MHz. Data are clocked into

the device on the rising edge of SCK. Data are clocked

out of the device on the falling edge of SCK. The device

interface is compatible with both SPI Mode 0,0 and 1,1.

SPI modes can be changed when CS is in Logic High

status.

When the input is selected by the multiplexer, the

differential (V_IN) and Common-Mode Voltage (V_INCOM

at the ADC inputs are defined by:

)

EQUATION 3-2:

SCK and MCLK are two different and asynchronous

clocks. SCK is only required during a communication,

while MCLK is continuously required when the part

converts analog inputs.

V

= V

– V

IN

IN+

V

IN-

+ V

IN+

IN-

V

= ---------------------------------

INCOM

2

DS20006404C-page 30

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

3.3.3

SERIAL DATA OUTPUT PIN (SDO)

3.5

MCLK

This pin is used for the SPI Data Output (SDO). The

SDO data are clocked out on the falling edge of SCK.

This pin stays high-impedance under the following

conditions:

This pin is either the MCLK digital input pin for the ADC

or the AMCLK digital output pin, depending on the

CLK_SEL[1:0] bits setting in the CONFIG0 register.

The typical clock frequency specified is 4.9152 MHz.

To optimize the ADC for accuracy and ensure proper

operation, AMCLK should be limited to a certain range

depending on the Boost and Gain settings. The higher

Gain settings require higher BOOST settings to main-

tain high bandwidth, as the input sampling capacitors

• When CS pin is logic high.

• During the entire SPI Write or Fast command

communication period after the SPI COMMAND

byte has been transmitted.

• After the two device address bits in the command

are transmitted if the device address in the com-

mand does not match the internal chip device

address.

have

a

larger value. Figure 2-35, Figure 2-36,

Figure 2-37, Figure 2-38 and Figure 2-43 represent the

typical accuracy (SINAD) expected with the different

combinations of Boost and Gain settings, and can be

used to determine an optimal set for the application

depending on the sampling speed (AMCLK) chosen.

MCLK can take larger values as long as the prescaler

settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in

the range shown in Section 2.0 “Typical Performance

Curves”.

3.3.4

SERIAL DATA INPUT PIN (SDI)

This is the SPI Data Input (SDI) pin and it uses a

Schmitt Trigger structure. When CS is logic low, this

pin is used to send a COMMAND byte just after the CS

falling edge, which can be followed by data words of

various lengths. Data are clocked into the device on

the rising edge of SCK. Toggling SDI while reading a

register has no effect.

3.6

Digital Ground (D

)

GND

D_GNDis the ground connection to internal digital

circuitry. To ensure accuracy and noise cancellation,

D_GNDmust be connected to the same ground as

A_GND, preferably with a star connection. If a digital

ground plane is available, it is recommended that this

pin be tied to this plane of the Printed Circuit Board

(PCB). This plane should also reference all other

digital circuitry in the system. D_GNDis not internally

connected to A_GNDand must be connected externally.

3.4

IRQ/MDAT

This is the digital output pin. This pin can be configured for

Interrupt (IRQ) or Modulator Data (MDAT) output using

the IRQ_MODE[1] bit setting. When IRQ_MODE[1] = 0

(default), this pin can output all four possible interrupts

(see Section 6.8 “Interrupts Description”). The

Inactive state of the pin is selectable through the

IRQ_MODE[0] bit setting (high-Z or logic high).

When IRQ_MODE[1] = 1, this pin outputs the modulator

output synchronously with AMCLK (that can be

selected as an output on the MCLK pin). In this mode,

the POR and CRC interrupts can still be generated as

they are high-level interrupts, and will lock the

IRQ/MDAT pin to logic low until they are cleared.

3.7

Digital Power Supply (DV

)

DD

DV_DDis the power supply pin for the digital circuitry

within the device. The voltage on this pin must be

maintained in the range specified by the Electrical

Characteristics table. For optimal performance, it is

recommended to connect appropriate bypass capaci-

tors (typically a 10 µF ceramic in parallel with a 0.1 µF

ceramic). DV_DDis monitored by the DV_DDPOR

monitoring circuit for the digital section.

When the IRQ pin is in High-Z mode, an external

pull-up resistor must be connected between DV_DDand

the IRQ pin. The device needs to be able to detect a

Logic High state when no interrupt occurs in order to

function properly (the pad has an input Schmitt Trigger

to detect the state of the IRQ pin just like the user sees

it). The pull-up value can be equal to 100-200 k for a

weak pull-up using the typical clock frequency. The

pull-up resistor value must be selected in relation with

the load capacitance of the IRQ output, the MCLK

frequency and the DV_DDsupply voltage, so that all

interrupts can be correctly detected by the SPI host

device.

3.8

Analog Power Supply (AV

)

DD

AV_DDis the power supply pin for the analog circuitry

within the device. The voltage on this pin must be

maintained in the range specified by the Electrical

Characteristics table. For optimal performance, it is

recommended to connect appropriate bypass capaci-

tors (typically a 10 µF ceramic in parallel with a 0.1 µF

ceramic). AV_DDis monitored by the AV_DDPOR

monitoring circuit for the analog section.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 31

MCP3461/2/4R

3.9

Analog Ground (A

)

3.10

Exposed Pad (EP)

GND

A_GNDis the ground connection to internal analog

circuitry. To ensure accuracy and noise cancellation,

this pin must be connected to the same ground as

D_GND, preferably with a star connection. If an analog

ground plane is available, it is recommended that this

pin be tied to this plane of the PCB. This plane should

also reference all other analog circuitry in the system.

A_GNDis the biasing voltage for the substrate of the die

This pad is only available on the UQFN package. The

pad is internally connected to A_GND. It must be con-

nected to the analog ground of the PCB for optimal

accuracy and thermal performance. This pad can also

be left floating if necessary.

and is not internally connected to D_GND

.

DS20006404C-page 32

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

• Offset Error

4.0

TERMINOLOGY AND

FORMULAS

• Gain Error

• Integral Nonlinearity Error (INL)

• Signal-to-Noise Ratio (SNR)

This section defines the terms and formulas used

throughout this document. The following terms are

defined:

• Signal-to-Noise and Distortion Ratio (SINAD)

• Total Harmonic Distortion (THD)

• Spurious-Free Dynamic Range (SFDR)

• MCP3461/2/4R Delta-Sigma Architecture

• Power Supply Rejection Ratio (PSRR)

• Common-Mode Rejection Ratio (CMRR)

• Digital Pins Output Current Consumption

• MCLK – Master Clock

• AMCLK – Analog Master Clock

• DMCLK – Digital Master Clock

• DRCLK – Data Rate Clock

• OSR – Oversampling Ratio

PRE[1:0]

OSR[3:0]

CLK_SEL[1]

CLK_SEL[1] = 0

MCLK

0

Pad

DRCLK

MCLK

AMCLK

DMCLK

1/

OUT

1/4

1/OSR

PRESCALE

1

Multiplexer

Internal Oscillator

Clock Divider

CLK_SEL[1:0] = 11

AMCLKOUT

FIGURE 4-1:

System Clock Details.

EQUATION 4-2:

DIGITAL MASTER CLOCK

4.1 MCLK – Master Clock

This is the master clock frequency at the MCLK input pin

when an external clock source is selected or internal

clock frequency when the internal clock is selected.

AMCLK

DMCLK = -------------------- = --------------------------------

4  Prescale

MCLK

4

4.2

AMCLK – Analog Master Clock

4.4

DRCLK – Data Rate Clock

This is the clock frequency that is present on the analog

portion of the device after prescaling has occurred via

the PRE[1:0] bits.

This is the output data rate in Continuous mode or the

rate at which the ADC outputs new data. Any new data

are signaled by a data ready pulse on the IRQ pin.

This data rate depends on the OSR and the prescaler,

as shown in Equation 4-3.

EQUATION 4-1:

ANALOG MASTER

CLOCK

EQUATION 4-3:

DATA RATE

MCLK

Prescale

AMCLK = ----------------------

DMCLK

AMCLK

MCLK

DRCLK = --------------------- = --------------------- = ---------------------------------------------------

OSR

4  OSR

4  OSR  Prescale

4.3

DMCLK – Digital Master Clock

Since this is the output data rate, and since the

decimation filter is a sinc (or notch) filter, there is a

notch in the filter transfer function at each integer

multiple of this rate.

This is the clock frequency that is present on the digital

portion of the device. This is also the sampling frequency

or the rate at which the modulator outputs are refreshed.

Each period of this clock corresponds to one sample and

one modulator output. See Equation 4-2.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 33

MCP3461/2/4R

EQUATION 4-5:

SINAD EQUATION

4.5

OSR – Oversampling Ratio

SignalPower

Noise + HarmonicsPower

The ratio of the sampling frequency to the output data

rate. OSR = DMCLK/DRCLK in Continuous mode. See

Table 5-6 for the OSR setting effect on sinc filter

parameters.







SINADdB = 10log --------------------------------------------------------------------



The calculated combination of SNR and THD per the

following formula also yields SINAD:

4.6

Offset Error

EQUATION 4-6:

SINAD, THD AND SNR

RELATIONSHIP

This is the error induced by the ADC when the inputs

are shorted together (V_IN= 0V). This error varies based

on gain settings, OSR settings and from chip to chip. It

can easily be calibrated out by an MCU with a

subtraction.

SNR

10

THD

------------

10













SINADdB = 10log 10^^-----------+ 10^

4.7

Gain Error

4.11 Total Harmonic Distortion (THD)

This is the error induced by the ADC on the slope of the

transfer function. It is the deviation expressed in per-

centage compared to the ideal transfer function defined

by Equation 5-5. The specification incorporates ADC

gain error contributions, but not the V_REFcontribution.

This error varies with GAIN and OSR settings. The gain

error of this device has a low-temperature coefficient.

The THD is the ratio of the output harmonics power to

the fundamental signal power for a sine wave input and

is defined by the following equation.

EQUATION 4-7:

HarmonicsPower

FundamentalPower







THDdB = 10log ----------------------------------------------------



4.8

Integral Nonlinearity Error (INL)

The THD is usually measured only with respect to the

first ten harmonics. THD is sometimes expressed in

percentage (%). This formula converts the THD from

dB to percentage:

Integral Nonlinearity Error is the maximum deviation of

an ADC transition point from the corresponding point of

an ideal transfer function, with the offset and gain

errors removed, or with the end points equal to zero. It

is the maximum remaining static error after offset and

gain errors calibration for a DC input signal.

EQUATION 4-8:

THDdB

THD% = 100  10^{------------------------}

20

4.9

Signal-to-Noise Ratio (SNR)

For this device family, the Signal-to-Noise Ratio is a

ratio of the output fundamental signal power to the

noise power (not including the harmonics of the signal)

when the input is a sine wave at a predetermined

frequency. It is measured in dB. Usually, only the

maximum Signal-to-Noise Ratio is specified. The SNR

figure depends mainly on the OSR and GAIN settings

of the device, as well as the temperature (due to

thermal noise being dominant for high OSR).

4.12 Spurious-Free Dynamic Range

(SFDR)

SFDR is the ratio between the output power of the

fundamental and the highest spur in the frequency

spectrum. The spur frequency is not necessarily a har-

monic of the fundamental, even though that is usually

the case. This figure represents the dynamic range of

the ADC when a full-scale signal is used at the input.

This specification depends mainly on the OSR and

GAIN settings.

EQUATION 4-4:

SIGNAL-TO-NOISE RATIO

SignalPower

NoisePower







SNRdB = 10log ---------------------------------



EQUATION 4-9:

FundamentalPower

HighestSpurPower







SFDRdB = 10log ----------------------------------------------------

4.10 Signal-to-Noise and Distortion

Ratio (SINAD)



Signal-to-Noise and Distortion Ratio is similar to

Signal-to-Noise Ratio, with the exception that you must

include the harmonics power in the noise power calcu-

lation. The SINAD specification depends mainly on the

OSR and GAIN settings.

DS20006404C-page 34

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

4.13 MCP3461/2/4R Delta-Sigma

Architecture

4.15 Common-Mode Rejection Ratio

(CMRR)

A Delta-Sigma ADC is an oversampling converter that

incorporates a built-in modulator, which digitizes the

quantity of charge integrated by the modulator loop.

The quantizer is the block that performs the

Analog-to-Digital conversion. The quantizer is typically

one bit or a simple comparator, which helps to maintain

the linearity performance of the ADC (the DAC

structure is in this case, inherently linear).

This is the ratio between a change in the

Common-mode input voltage and the change in the

ADC output codes. It measures the influence of the

Common-mode input voltage on the ADC outputs.

The CMRR specification can be DC (the Common-mode

input voltage takes multiple DC values) or AC (the

Common-mode input voltage is a sine wave at a certain

frequency with a certain Common-mode). In AC, the

amplitude of the sine wave represents the change in

the Common-mode input voltage. CMRR is defined in

Equation 4-11.

Multibit quantizers help to lower the quantization error

(the error fed back in the loop can be very large with

1-bit quantizers) without changing the order of the

modulator or the OSR, which leads to better SNR

figures. However, typically the linearity of such archi-

tectures is more difficult to achieve since the DAC is no

more simple to realize and its linearity limits the THD of

such ADC.

EQUATION 4-11:

V_OUT







CMRRdB = 20log -----------------------



V_INCOM

The modulator 5-level quantizer is a Flash ADC

composed of four comparators arranged with equally

spaced thresholds and a thermometer coding. The

device also includes proprietary 5-level DAC

architecture that is inherently linear for improved THD

figures.

Where V_INCOM= (V_IN+ + V_IN-)/2 is the Common-mode

input voltage and V_OUTis the equivalent input voltage

that the output code translates to with the ADC transfer

function.

4.16 Digital Pins Output Current

Consumption

4.14 Power Supply Rejection Ratio

(PSRR)

The digital current consumption shown in the Electri-

cal Characteristics table does not take into account

the current consumption generated by the digital output

pins and the charge of their capacitive loading. The

specification is intended with all output pins left floating

and no communication.

This is the ratio between a change in the power supply

voltage and the change in the ADC output codes. It

measures the influence of the power supply voltage on

the ADC outputs. PSRR is defined in Equation 4-10.

The PSRR specification can be DC (the power supply

is taking multiple DC values) or AC (the power supply

is a sine wave at a certain frequency with a certain

Common-mode). In AC, the amplitude of the sine wave

represents the change in the power supply.

In order to estimate the additional current consumption

due to the output pins, see Equation 4-12. This equa-

tion specifies the amount of additional current due to

each pin when its output is connected to a C_load

capacitance, with respect to D_GND, and submitted to an

output signal toggling at an f_outfrequency.

EQUATION 4-10:

If a typical 10 MHz SPI frequency is used, with a 30 pF

load and DV_DD= 3.3V, the SDO output generates an

additional maximum current consumption of 500 µA

(the maximum toggling frequency of SDO is 5 MHz,

since f_SCK= 10 MHz, and this is reached when the ADC

output code is a succession of ‘1’s and ‘0’s). The C_load

value includes internal digital output driver capaci-

tance, but this can generally be neglected with respect

to the external loading capacitance.

V_OUT







PSRRdB = 20log ------------------



AV_DD

Where V_OUTis the equivalent input voltage that the

output code translates to with the ADC transfer

function.

EQUATION 4-12:

DIDD

= C

 DV

 f

SPI

load

DD

out

Where:

C_load= Capacitance on the Output Pin

DV_DD= Digital Supply Voltage

f_out= Output Frequency on the Output Pin

 2020-2021 Microchip Technology Inc.

DS20006404C-page 35

MCP3461/2/4R

NOTES:

DS20006404C-page 36

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Each of these multiplexers includes the same

possibilities for the input selection, so that any required

combination of input voltages can be converted by the

ADC. The analog multiplexer is composed of parallel

low-resistance input switches, turned on or off, depend-

ing on the input channel selection. Their resistance is

negligible compared to the input impedance of the ADC

(caused by the charge and discharge of the input

sampling capacitors on the V_IN+/V_IN- ADC inputs). The

block diagram of the analog multiplexer is shown in

Figure 5-1.

5.0

5.1

DEVICE OVERVIEW

Analog Input Multiplexer

The device includes a fully configurable analog input

dual multiplexer that can select which input is con-

nected to each of the two differential input pins

(V_IN+/V_IN-) of the Delta-Sigma ADC.

The dual multiplexer is divided into two single-ended

multiplexers that are totally independent.

MUX[7:4]

CH0

CH1

A_GND

AV_DD

REFIN+/OUT

REFIN-

CS_SEL[1:0]

TEMP Diode P

TEMP Diode M

V_CM

I_SOURCE

I_TEMP

+

I_TEMP-

MUX[7:4]

= 1101

MUX[3:0]

= 1101

MUX[7:4]

= 1110

MUX[3:0]

= 1110

V_IN+ Analog Multiplexer

V_IN+

V_IN-

A_GND

MUX[3:0]

CH0

CH1

A_GND

Sigma-Delta ADC

CS_SEL[1:0]

I_SINK

AV_DD

REFIN+/OUT

REFIN-

A_GND

TEMP Diode P

TEMP Diode M

V_CM

V_IN- Analog Multiplexer

A_GND

Analog Input Dual Multiplexer

FIGURE 5-1:

Simplified Analog Input Multiplexer Schematic.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 37

MCP3461/2/4R

The possible selections are described in Table 5-1 and

can be set with the MUX[7:0] register bits during the

MUX mode. The MUX[7:4] bits define the selection for

the V_IN+ (noninverting analog input of the ADC). The

MUX[3:0] bits define the selection for the V_IN- (inverting

analog input of the ADC).

TABLE 5-1:

MUX[7:4] (V_IN+) or

MUX[3:0] (V_IN-) Code

ANALOG INPUT MUX DECODING

Selected

Channel

Comment

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

CH0

CH1

CH2

Not Connected (NC) for MCP3461R

CH3

Not Connected (NC) for MCP3461R

CH4

Not Connected (NC) for MCP3461R/MCP3462R

CH5

CH6

CH7

A_GND

AV_DD

Reserved

REFIN+/OUT

REFIN-

TEMP Diode P

TEMP Diode M

Internal V_CM

Do not use

Internal Common-mode voltage for modulator biasing

During Scan mode, the two single-ended input

multiplexers are automatically set to a certain position,

depending on the Scan sequence and which channel

has been selected by the user. The Scan sequence

channels’ configuration corresponds to a certain code

in the MUX[7:0] register bits, as defined in Table 5-15.

The possible inputs of the analog multiplexer include

not only the analog input channels, but also REFIN+/-

inputs, AV_DDand A_GND, as well as temperature sensor

outputs and the V_CMinternal Common-mode. This

large selection offers many possibilities for measuring

internal or external data resources of the system and

can serve as diagnostic purposes to increase the

security of the applications. Some monitor channels

are already predefined in Scan mode to further help

users to integrate diagnostics to their applications (for

example, the analog power supply or the temperature

can be constantly monitored in Scan mode; see

Section 5.15.3 “Scan Mode Internal Resource

Channels” for more details of the different resources

that can be monitored in Scan mode).

In order to monitor the Digital Power Supply (DV_DD), it

is necessary to connect DV_DDexternally to one of the

CHn analog inputs, since DV_DDis not one of the pos-

sible selections of the analog multiplexer. A similar

setup can be implemented to monitor D_GNDif D_GNDis

not connected externally to A_GND

.

For MCP3461R and MCP3462R, some codes are not

available in the selection since the pins are not bonded

out on these devices. These codes should then be

avoided in the application, as the input they connect to

is effectively a high-impedance node.

Note:

When VREF_SEL = 0(external V_REF) and

REFIN+/OUT and REFIN- are selected as

analog inputs for the ADC, the same

REFIN+/OUT and REF- pin voltages are

used as the reference for the ADC. This

diagnostic mode is useful for determining

the full-scale Gain error of the ADC when

a Gain setting of 1/3x or 1x is used.

The TEMP Diodes P and M are two internal diodes that

are biased by a current source, and that can be used to

perform a temperature measurement. If TEMP Diode P

is connected to V_IN+ and TEMP Diode M to V_IN-, then

the ADC output code is a function of the temperature

using Equation 5-1 (see Section 5.1.2, Internal Tem-

perature Sensor for more details). The V_CMselection

measures the internal Common-mode voltage source

that biases the Delta-Sigma modulator (this voltage is

not provided at any output of the part).

DS20006404C-page 38

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

This relatively low accuracy on the current is generally

sufficient for open/short-detection applications.

Figure 2-53 shows how the ADC output code varies

when the burnout current sources are enabled (with

Gain = 1x) and the input sensor impedance is swept

with a large dynamic range. This allows the use of the

ADC as an open/short-detection circuit, which is

practical when manufacturing complex remote sensor

systems.

5.1.1

BURNOUT CURRENT SOURCES

FOR SENSOR OPEN/SHORT

DETECTION

The ADC inputs, V_IN-/V_IN+, feature a selectable

burnout current source, which enables open or

short-circuit detection, as well as biasing very low-

current external sensors. The bias current is sourced

on the V_IN+ pin of the ADC (noninverting output of the

analog multiplexer) and sunk on the V_IN- pin of the ADC

(inverting output of the analog multiplexer). Since the

same current flows at the V_IN-/V_IN+ pins of the ADC, it

can sense the impedance of an externally connected

sensor that would be connected between the selected

inputs of the multiplexer. When the sensor is in short

circuit, the ADC converts signals that are close to 0V.

When the sensor is an open circuit, the ADC converts

signals that are close to the AV_DDvoltage.

5.1.2

INTERNAL TEMPERATURE

SENSOR

The device includes an on-board temperature sensor,

which is made of two typical P-N junction diodes biased

by fixed current sources (TEMP Diodes P and M). The

TEMP Diode P has a current density of 4x of the TEMP

Diode M.

The difference in the current densities of the diodes yields

a voltage that is a function of the absolute temperature.

The current source is an independent peripheral of the

ADC. It does not need the ADC to be in Conversion

mode to be present. Once enabled, the source pro-

vides current even when the ADC is in Reset or ADC

Shutdown mode. The current source can be configured

at any time through programming the CS_SEL[1:0] bits

in the CONFIG0 register (see Table 5-2).

Once the ADC inputs (V_IN-/V_IN+) are connected to the

temperature sensor diodes (MUX[7:0] = 0xDE), the

ADC will see a V_INdifferential input that is the function

of the temperature. The transfer function of the

temperature sensor can be approximated by a linear

equation or a third-order equation for more accuracy.

Since the amount of current selected can be very small,

it may be necessary to diminish the MCLK master clock

frequency to be able to reach the full desired accuracy

during conversions (the settling time of the input struc-

ture, including the sensor, can be large if the sensor is

very resistive, which will limit the bandwidth of the

Sample-and-Hold input circuit).

When the internal temperature sensor is selected for

the MUX or Scan input, the input sink/source current

source, controlled by the CS_SEL[1:0] bits (see

Section 5.1, Analog Input Multiplexer), is disabled

internally (even though the CS_SEL[1:0] bits are not

modified by the temperature sensor selection). In this

case, the input current source is replaced by a specific

internal current source that will only be sourced to the

diode temperature sensor (see Figure 5-1).

TABLE 5-2:

BURNOUT CURRENT

SOURCE SETTINGS

CS_SEL[1:0]

(Source/Sink)

Burnout Current

The bias current of the diodes is not calibrated internally

and can lead to a relatively large gain and offset error in

the transfer function of the temperature sensor. Typical

graphs showing the typical error in the temperature

measurement are provided in Section 2.0, Typical

Performance Curves (see Figure 2-51 for first order).

Amplitude

00

01

10

11

0 µA

0.9 µA

3.7 µA

15 µA

The accuracy can also be optimized by using proper

digital gain and offset error calibration schemes.

The accuracy of the current sources is on the order of

magnitude of ±20% and not very well controlled inter-

nally. However, the mismatch between sink and source

is typically around ±1%.

EQUATION 5-1:

TEMPERATURE SENSOR TRANSFER FUNCTION

First-Order (Linear) Fitting: Gain = 1, MCLK = 4.9152 MHz

where V

= V

+ – V

-

REF

TEMPC = 0.102646  ADCDATALSb  VREF (V) – 269.13,

REF

V

mV = 0.2973  TEMP (C) + 80

IN

 2020-2021 Microchip Technology Inc.

DS20006404C-page 39

MCP3461/2/4R

When AZ_MUX = 1, the algorithm is enabled. When the

offset cancellation algorithm is enabled, ADC takes two

conversions, one with the differential input as V_IN+/V_IN-,

one with V_IN+/V_IN- inverted. Equation 5-2 calculates the

ADC output code. When AZ_MUX = 1, the Conversion

Time, T_CONV, is multiplied by two, compared to the

default case where AZ_MUX = 0.

5.1.3

ADC OFFSET CANCELLATION

ALGORITHM

The input multiplexer and the ADC include an offset

cancellation algorithm that cancels the offset contribution

of the ADC. This offset cancellation algorithm is con-

trolled by the AZ_MUX bit in the CONFIG2 register.

When AZ_MUX = 0(default), the offset cancellation algo-

rithm is disabled and the conversions are not affected by

this setting.

EQUATION 5-2:

AZ_MUX CONVERSION RESULT

ADC Output at +V  – ADC Output at -V



IN

ADC Output Code (AZ_MUX = 1) = -----------------------------------------------------------------------------------------------------------------------

2

This technique allows the cancellation of the ADC

offset error and the achievement of ultra-low offset

without any digital calibration. The resulting offset is the

residue of the difference between the two conversions,

which is on the order of magnitude of the noise floor.

This offset is effectively canceled at every conversion,

so the residual offset error temperature drift is

extremely low.

For One-Shot mode, the conversion time is simply

multiplied by two. Enabling the AZ_MUX bit is not

compatible with the Continuous Conversion mode

(because it effectively multiplexes the inputs in

between each conversion). If AZ_MUX = 1 and

CONV_MODE = 11 (Continuous Conversion mode),

the device will reset the digital filter in between each

conversion, and will therefore, have an output data rate

of 1/(2 * T_CONV). The Continuous mode is replaced by

a series of One-Shot mode conversions with no delay

in between each conversion (see Section 5.14 “Con-

version Modes” and Figure 5-5 for more details about

the Conversion modes).

DS20006404C-page 40

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MCP3461/2/4R

This anti-aliasing filter can be a simple first-order RC

network with low time constant, which will provide a

high rejection at the DMCLK frequency (see Figure 5-6

for more details). The RC network usually uses small R

and large C to avoid additional offset due to IR drop in

the signal path. This anti-aliasing filter will induce a

small systematic gain error on the AC input signals that

can be compensated in the digital section with the

Digital Gain Error Calibration (GAINCAL) register.

5.2

Input Impedance

The ADC inputs (V_IN+/V_IN-) are directly tied to the

analog multiplexer outputs and are not routed to exter-

nal pins. The multiplexer input stage contribution to the

input impedance is negligible.

The conversion accuracy can be affected by the input

signal source impedance when any external circuit is

connected to the input pins. The source impedance

adds to the internal impedance and directly affects the

time required to charge the internal sampling capacitor.

Therefore, a large input source impedance connected

to the input pins can increase the system performance

errors, such as offset, gain and Integral Nonlinearity

(INL). Ideally, the input source impedance should be

near zero. This can be achieved by using an opera-

tional amplifier with a closed-loop output impedance of

tens of ohms.

5.3

ADC Programmable Gain

The gain of the converter is programmable and

controlled by the GAIN[2:0] bits in the CONFIG2 register.

The ADC programmable gain is divided in two gain

stages: one in the analog domain, one in the digital

domain, as per Table 5-3.

After the multiplexer, the analog input signals are

routed to the Delta-Sigma ADC inputs and are

amplified by the analog gain stage (see Section 5.3.1

“Analog Gain” for more details). The digital gain stage

is placed inside the digital decimation filter (see

Section 5.3.2 “Digital Gain” for more details).

A proper anti-aliasing filter must be placed at the ADC

inputs. This will attenuate the frequency contents

around DMCLK and keep the desired accuracy over

the baseband (DRCLK) of the converter.

TABLE 5-3:

DELTA-SIGMA ADC GAIN SETTINGS

Total Gain

Analog Gain Digital Gain

Total Gain

(dB)

GAIN[2:0]

V_INRange (V)

(V/V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.333

1

0.333

1

2

4

-9.5

0

±Min (AV_DD, 3 * V_REF

±V_REF

)

2

6

±V_REF/2

4

12

18

24

30

36

±V_REF/4

8

±V_REF/8

16

32

64

16

±V_REF/16

±V_REF/32

±V_REF/64

 2020-2021 Microchip Technology Inc.

DS20006404C-page 41

MCP3461/2/4R

Figure 5-2 represents a simplified block diagram of the

Delta-Sigma modulator.

5.3.1

ANALOG GAIN

The gain settings, from 0.33x to 16x, are done in the

analog domain. This analog gain is placed on each ADC

differential input. Each doubling of the gain improves the

thermal noise due to sampling by approximately 3 dB,

which means the lowest noise configuration is obtained

when using the highest analog gain. The SNR, however,

is degraded, since doubling the gain factor reduces

the maximum allowable input signal amplitude by

approximately 6 dB.

Delta-Sigma 2^ndOrder 5-Level Modulator

Quantizer

Differential Input

Voltage

(from Analog Mux)

Analog

2^ndOrder

Loop

Output

Bitstream

Thermometer Coding

(to Digital Filter)

4

5-Level Flash

ADC

Filter

5-Level DAC

Analog

Digital

If the gain is set to 0.33x, the differential input range

theoretically becomes ±3 * V_REF. However, the device

does not support input voltages outside of the power

supply voltage range. If large reference voltages are

used with this gain, the input voltage range will be

clipped between A_GNDand AV_DD, and therefore, the

output code span will be limited. This gain is useful

when the reference voltage is small and when the

input signal voltage is large.

FIGURE 5-2:

Block Diagram.

Simplified Delta-Sigma ADC

5.4.2

MODULATOR OUTPUT BLOCK

The modulator output option enables users to apply

their own digital filtering on the output bit stream. By

setting IRQ_MODE[1] = 1in the IRQ register, the mod-

ulator output is available at the IRQ/MDAT pin, at

AMCLK rate and also through the ADCDATA register

(0x0) with DMCLK rate. With this configuration, the

digital decimation filter is disabled in order to reduce

the current consumption and no data ready interrupt is

generated on any of the IRQ mechanisms. The

IRQ/MDAT pin is never placed in high-impedance

during the Modulator Output mode.

The analog gain stage can be used to amplify very low

signals, but the differential input range of the

Delta-Sigma modulator must not be exceeded.

5.3.2

DIGITAL GAIN

When the gain setting is chosen from 16x to 64x, the

analog gain stays constant at 16x, and the additional

gain is done in the digital domain by a simple shift and

round of the output code. The digital gain range is

between 1x and 4x.

Since the Delta-Sigma modulator has a 5-level output

given by the state of four comparators with thermo-

meter coding, the output is represented using four bits,

each bit representing the state of the corresponding

comparator (see Table 5-4).

The output noise is approximately unchanged (except

for the quantization noise, which is slightly decreased).

The SNR is thus degraded by 6 dB per octave from 16x

to 64x settings.

The comparator output bits are arranged serially at the

AMCLK rate on the IRQ/MDAT output pin (see

Figure 5-3).

This digital gain is useful for scaling up the signals with-

out using the host device (MCU) operations, but they

degrade the SNR and resolution (one bit per octave),

and do not significantly improve the noise performance,

except for very large OSR settings.

This 1-bit serial bit stream is considered to be the same

one as is produced by a 1-bit DAC modulator with a

sampling frequency of AMCLK. The modulator can

either be considered as a 5-level output at DMCLK rate

or as 1-bit output at AMCLK rate. These two represen-

tations are interchangeable. The MDAT outputs can,

therefore, be used in any application that requires 1-bit

modulator outputs. This application can be integrated

with an external sinc filter or more advanced decima-

tion filters that are computed in the MCU or DSP

device.

5.4

Delta-Sigma Modulator

5.4.1

ARCHITECTURE

The Delta-Sigma ADC includes

a

second-order

modulator with a multibit DAC architecture. Its 5-level

quantizer is a Flash ADC composed of four comparators

with equally spaced thresholds and a thermometer out-

put coding. The proprietary 5-level architecture ensures

minimum quantization noise at the outputs of the

modulators without disturbing the linearity or inducing

additional distortion.

When CLK_SEL[1:0] = 11 (internal oscillator with

external clock output), the AMCLK clock is present on

the MCLK pin. This configuration allows a correct

synchronization of the bit stream when the internal

oscillator is used as the master clock source.

Unlike most multibit DAC architectures, the 5-level

DAC used in this architecture is inherently linear, and

therefore, does not degrade the ADC linearity and THD

performance.

When CLK_SEL[1:0] = 00, the modulator outputs are

also synchronized with the MCLK input, but the ratio

between MCLK and AMCLK must to be taken into

account in the user applications to correctly retrieve the

desired bit stream.

The sampling frequency is DMCLK; therefore, the

modulator outputs are refreshed at a DMCLK rate.

DS20006404C-page 42

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MCP3461/2/4R

The default value of the bit stream after a Reset or a

power-up is ‘0011’; it is equivalent to a 0V input for the

ADC. After each ADC Reset and Restart (see

Section 5.16 “A/D Conversion Automatic Reset and

Restart Feature”), the bit stream output is also reset

and restarted, and the IRQ/MDAT is kept equal to logic

high during the two MCLK clock periods needed for the

synchronization. After these two clock periods, the bit

stream will be provided on the IRQ/MDAT pin and the

first value will be the default value.

5.4.3

BOOST MODES

The Delta-Sigma modulator includes a programmable

biasing circuit in order to further adjust the power

consumption to the sampling speed applied through the

MCLK. This can be programmed through the

BOOST[1:0] bits in the CONFIG2 register. The different

BOOST settings are applied to the entire modulator

circuit, including the voltage reference buffers. The

settings of the BOOST[1:0] bits are described in

Table 5-5.

TABLE 5-4:

DELTA-SIGMA MODULATOR

OUTPUT BIT STREAM CODING

TABLE 5-5:

BOOST SETTINGS

DESCRIPTION

Modulator

Output Code

(Decimal)

MDAT Equivalent

BOOST[1:0]

Bias Current

COMP[3:0]

Code

Serial

V_REF

Stream

Voltage

00

01

10

11

x0.5

x0.66

1111

0111

0011

0001

0000

+2

+1

0

1111

0111

0011

0001

0000

+V_REF

+V_REF/2

0

x1 (default)

x2

-1

-2

-V_REF/2

-V_REF

The maximum achievable Analog Master Clock

(AMCLK) speed, the maximum sampling frequency

(DMCLK) and the maximum achievable data rate

(DRCLK) are highly dependent on the BOOST[1:0] and

GAIN[2:0] bits setting. A higher BOOST setting allows

the circuit’s bandwidth to be increased and allows a

higher analog master clock rate, which will then

increase the baseband of the input signals to be

converted. The digital gain (which is enabled at 32x

and 64x gains) has no influence on the achievable

bandwidth.

t_DOMDATt_DOMDATt_DOMDATt_DOMDATt_DOMDAT

AMCLK

MDAT

(code = +2)

A typical dependency of the bandwidth depending on

the gain for each BOOST setting combination is shown

from Figure 2-35 to Figure 2-38. Typically, a larger gain

setting requires a higher BOOST setting in order to

achieve the same bandwidth performance.

MDAT

(code = +1)

Figure 2-43 shows the behavior of the achievable

bandwidth at BOOST = 1x with AV_DDcorner cases.

Since the BOOST settings vary, the internal slew rate

of the modulator components, using a lower V_REF

value, will improve the bandwidth if low BOOST

settings are used and show a bandwidth behavior that

is too limited.

MDAT

(code = 0)

MDAT

(code = -1)

MDAT

(code = -2)

COMP[3]

COMP[2]

COMP[1]

COMP[0]

FIGURE 5-3:

MDAT Serial Outputs

Depending on the Modulator Output Code.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 43

MCP3461/2/4R

The transfer function of this filter has a unity gain at

each multiple of DMCLK. A proper anti-aliasing filter

must be placed at the ADC inputs. This will attenuate

the frequency contents around each multiple of

DMCLK and keep the desired accuracy over the base-

band of the converter. This anti-aliasing filter can be a

simple first-order RC network with low time constant to

provide a high rejection at DMCLK frequency.

5.5

Digital Decimation Filter

The decimation filter decimates the output bit stream of

the modulator to produce 16-bit ADC output data. The

decimation filter present in the device is a cascade of

two filters: a third-order sinc filter with a decimation

ratio of OSR₃(third-order moving an average of

3 x OSR₃values), followed by a first-order sinc filter

with a decimation ratio of OSR₁, moving an average of

OSR values (third-order moving average of 3 x OSR₃

values).

The conversion time is a function of the OSR settings

and the DMCLK frequency.

Figure 5-4 represents the decimation filter architecture.

EQUATION 5-4:

CONVERSION TIME FOR

OSR = OSR3 x OSR1

OSR₁= 1

Modulator

Output

T_CONV= 3  OSR₃ + OSR₁– 1  OSR₃  DMCLK

Decimation

Filter

SINC³

(Thermometer

Coding)

SINC¹

Output

In One-Shot mode, each conversion is launched

individually, so the maximum data rate is effectively

1/T_CONVif each conversion is launched with no delay.

The digital filter is reset in between each conversion.

4

ADC

Resolution

OSR₃

OSR₁

Decimation Filter

However, due to the nature of the digital filter (which

memorizes the sum of the incoming bit stream), the

data rate at the filter output can be maximized if the

filter is never reset. Because of the internal resampling

of the digital filter, the output data rate can be equal to

DMCLK/OSR = DRCLK; this is the case in Continuous

mode. In this case, the first conversion still happens in

the T_CONVtime, as this is the settling time of the filter.

The subsequent conversions are pipelined and give

their output at a data rate of DRCLK. The Continuous

Conversion mode can optimize the data rate, while

consuming the same power as One-Shot mode, which

is advantageous in applications that require a continu-

ous sampling of the analog inputs. The Continuous

mode is not compatible with multiplexing the inputs

(see Section 5.15 “Scan Mode” for more details

about the Conversion mode settings in MUX and Scan

modes).

FIGURE 5-4:

Diagram.

Decimation Filter Block

The following equation is the transfer function of the

decimation filter:

EQUATION 5-3:

FILTER TRANSFER

FUNCTION

3

-OSR

-OSR  OSR

1 3













3

1 – z





Hz = --------------------------------------------  -----------------------------------------------------

3

–1

–OSR

OSR₃1 – z 



3

OSR₁ 1 – z





Where:

2fj

DMCLK







z = exp ---------------------



Figure 5-5 shows the fundamental difference between

One-Shot mode and Continuous mode in a simplified

diagram.

The resolution (number of possible output codes

expressed in powers of two or in bits) of the digital

filter is 16-bit maximum for any OSR = OSR₃x OSR₁

and data format choice. The resolution only depends

on the OSR through the OSR[3:0] bits setting in the

CONFIG1 register per Table 5-6. Once the OSR is

chosen, the resolution is fixed and the output code of

the ADC is encoded with the data format defined by

the DATA_FORMAT[1:0] bits setting in the CONFIG3

register.

DS20006404C-page 44

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MCP3461/2/4R

Analog Input

Signal

One-Shot mode

Conversions are Serialized,

Filter is Reset After Each

Conversion

IRQ

ADC

Status

Conversion1

Conversion2

Conversion3

Group Delay: T_CONV

T_CONV

Data Rate: 1/(T_CONV

)

IRQ

ADC

Status

Conversion1

Continuous mode

Conversions are Pipelined,

Filter is Never Reset

Group Delay: T_CONV

T_CONV= Settling Time

1/DRCLK

Conversion2

T_CONV

Data Rate: DRCLK

Conversion3

T_CONV

FIGURE 5-5:

One-Shot Mode vs. Continuous Mode.

Since the converter is effectively doing two conversions

when the AZ_MUX bit is enabled, the conversion time

is equal to 2 * T_CONVin this mode. As described in

Section 5.1.3 “ADC Offset Cancellation Algorithm”,

this selection is not compatible with the Continuous

Conversion mode, and therefore, the output data rate

is equal to 1/(2 * T_CONV) in this mode.

When OSR is larger than 20480 for typical master clock

frequency, MCLK = 4.9152 MHz, the device includes

an additional 50/60 Hz rejection by aligning decimation

filter notches with a multiple of 50/60 Hz depending on

the OSR setting. The rejection band strongly depends

on the master clock accuracy and corresponds to a

first-order decimation filter rejection rate.

Table 5-6 summarizes the possible filter settings and

their associated Conversion Time, T_CONV, as well as

their output data rate (DRCLK) in Continuous mode.

The high OSR settings can be used for applications

requiring very low noise and slow data rates.

Figure 5-6 shows the frequency response of the

decimation filter with default settings. Figure 5-7

represents the frequency response of the filter with the

highest OSR settings and a line rejection at 60 Hz.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 45

MCP3461/2/4R

TABLE 5-6:

OVERSAMPLING RATIO AND SINC FILTER RELATIONSHIP

Data Rate in Continuous

Conversion Mode

ADC Resolution

in Bits

(No Missing

Codes)

Conversion

Time

Total

OSR

OSR[3:0] OSR

OSR

3

1

Data Rate (Hz) with

Fastest Data Rate (Hz)

(T

)

CONV

MCLK = 4.9152 MHz

with MCLK = 19.6608 MHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32

1

32

16

96/DMCLK

192/DMCLK

38400

19200

9600

4800

2400

1200

600

300

150

75

153600

76800

38400

19200

9600

4800

2400

1200

600

64

128

256

512

1

128

384/DMCLK

1

256

768/DMCLK

1

512

1536/DMCLK

2048/DMCLK

3072/DMCLK

5120/DMCLK

9216/DMCLK

17408/DMCLK

21504/DMCLK

25600/DMCLK

41984/DMCLK

50176/DMCLK

82944/DMCLK

99328/DMCLK

2

1024

2048

4096

8192

16384

20480

24576

40960

49152

4

8

16

32

40

48

80

96

300

60

240

50

200

30

120

25

100

160 81920

192 98304

15

60

12.5

50

DS20006404C-page 46

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

FIGURE 5-6:

Decimation Filter Frequency Response (OSR = 256, PRE = 1:1, MCLK = 4.9152 MHz).

FIGURE 5-7:

Decimation Filter Frequency Response (OSR = 81920, PRE = 1:1,

MCLK = 4.9152 MHz).

 2020-2021 Microchip Technology Inc.

DS20006404C-page 47

MCP3461/2/4R

The rounding ensures a maximum 1/2 LSb error

instead of a simple truncation that ensures a 1 LSb

maximum error.

5.6

ADC Output Data Format

The ADC Output Data (ADCDATA) register is located at

the address: 0x0. The default length of the register is

16-bit (15-bit + sign).

Equation 5-5 calculates the ADC output code as a

function of the input and reference signals for DC

inputs.

Output data are calculated in the digital decimation

filter with a much larger resolution and rounded to the

closest LSb value.

EQUATION 5-5:

ADC OUTPUT CODE FOR DC INPUT (DATA_FORMAT[1:0] = 00)

– V

V





IN+

IN-

ADC_OUTPUT(LSb) = -----------------------------------------  32768  GAIN





V

– V





REF+

REF-

For AC sine wave inputs, the decimation filter transfer

function (see Equation 5-3) induces an additional gain

on the ADC output code, which depends on the input

frequency (roll-off of the decimation filter).

ADC output format is set by the DATA_FORMAT[1:0]

bits in the CONFIG3 register. These bits define four

different possible formats for the ADC Data Output

register: three 32-bit formats and one 16-bit format for

the MCP3461/2/4R.

For any inputs, the V_IN+/V_IN- voltages are averaged out

during the whole conversion time as the ADC is an

oversampling converter.

Figure 5-8 describes all possible data formats.

DATA_FORMAT[1:0]

00

SGN + DATA[14:0]

01

10

SGN + DATA[14:0]

SGN ext (16-bit)

0x0000

DATA[15:0]

11

CH_ID[3:0]

SGN ext (12-bit)

FIGURE 5-8:

ADC Output Format Selection.

When DATA_FORMAT[1:0] = 0x, the ADC data are

represented on 16 bits (15-bit plus sign). The ADC out-

put code is represented with MSb first signed two’s

complement coding. With these two data formats, the

coding does not allow overrange; the equivalent

analog input range is [-V_REF; +V_REF– 1 LSb]. When

V_IN* Gain > V_REF– 1 LSb, the 16-bit ADC code

(SGN + DATA[22:0]) will saturate and be locked at

0x7FFF. When V_IN* Gain < -V_REF, the 16-bit ADC code

will saturate and be locked at 0x8000. Using these data

formats does not permit correctly evaluating full-scale

errors in case of a positive full-scale error.

When DATA_FORMAT[1:0] = 00, the output register

shows

only

the

16-bit

value.

When

DATA_FORMAT[1:0] = 01, the output register is 32 bits

long and the output code is padded with additional

zeros on the last byte. The output code is left justified

in this case. This format is useful for 32-bit MCU

applications.

DS20006404C-page 48

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

When DATA_FORMAT[1:0] = 1x, the ADC data are

represented on 17 bits. For these two data formats, the

output register is 32 bits long. With these two data

formats, the coding allows overrange; the equivalent

analog input range is [-2 x V_REF, +2 x V_REF– 1 LSb].

When V_IN* Gain > 2V_REF– 1 LSb, the 17-bit ADC code

(SGN + DATA[15:0]) will saturate and be locked at

0x0FFFF. When V_IN* Gain < -2V_REF, the 16-bit ADC

code will saturate and be locked at 0x10000. Using

these data formats allows a correct evaluation of the

full-scale errors in case of a positive full-scale error,

since they allow inputs that can be greater than V_REFor

16-bit codes for the [-V_REF; +V_REF– 1 LSb] range and

the MSb on the 17-bit coding can be considered as a

simple Sign bit extension.

When DATA_FORMAT[1:0] = 10, the 17-bit

(16-bit + SGN) value is right justified. The first byte of

the 32-bit ADC output code will repeat the Sign bit

(SGN).

In DATA_FORMAT[1:0] = 11, the output code is similar

to the one in DATA_FORMAT[1:0] = 10. The only differ-

ence resides in the four MSbs of the first byte, which

are no longer repeats of the Sign bit (SGN). They are

the Channel ID data (CH_ID[3:0]) that are defined in

Table 5-15. This CH_ID[3:0] word can be used to verify

that the right channel has been converted to Scan

mode and can serve easy data retrieval and logging

(see Section 5.15 “Scan Mode” for more details

about the Scan mode). In MUX mode, this 4-bit word is

defaulted to ‘0000’ and does not vary with the

MUX[7:0] selection. This format is useful for 32-bit

MCU applications.

less than -V_REF

.

The ADC accuracy is not maintained on the full

extended [-2 x V_REF, +2 x V_REF– 1 LSb] range, but only

on a smaller range, which is approximately equal to

±1.05 x V_REF. This overrange can be useful in high-side

measurements and gain error cancellation algorithms.

The overrange-capable formatting on 17 bits is fully

compatible with the standard code locked formatting on

16 bits; both coding formats will produce the same

TABLE 5-7:

DATA_FORMAT[1:0] = 0x (16-BIT CODING)

ADC Output Code

(SGN + DATA[14:0])

Equivalent Input Voltage

Hexadecimal

Decimal

> V_REF– 1 LSb

V_REF– 2 LSbs

1 LSb

0111111111111111

0111111111111110

0000000000000001

0000000000000000

1111111111111111

1000000000000001

1000000000000000

0x7FFF

0x7FFE

0x0001

0x0000

0xFFFF

0x8000

+32767

+32766

+1

0

-1 LSb

-1

-V_REF+ 1 LSb

< -V_REF

-32767

-32768

TABLE 5-8:

DATA_FORMAT[1:0] = 1x (17-BIT CODING)

ADC Output Code

(SGN + DATA[15:0])

Equivalent Input Voltage

Hexadecimal

Decimal

> 2 V_REF– 1 LSb

2 V_REF– 2 LSbs

V_REF+ 1 LSb

V_REF

01111111111111111

01111111111111110

01000000000000001

01000000000000000

00111111111111111

00111111111111110

00000000000000001

00000000000000000

11111111111111111

11000000000000001

11000000000000000

10111111111111111

10000000000000001

10000000000000000

0x0FFFF

0x0FFFE

0x08001

0x08000

0x07FFF

0x07FFE

0x00001

0x00000

0x1FFFF

0x18001

0x18000

0x17FFF

0x10001

0x10000

+65535

+65534

+32769

+32768

+32767

+32766

+1

V_REF– 1 LSb

V_REF– 2 LSbs

1 LSb

0

-1 LSb

-1

-V_REF+ 1 LSb

-V_REF

-32767

-32768

-32769

-65535

-65536

-V_REF– 1 LSb

-2 V_REF+ 1 LSb

< -2 V_REF

 2020-2021 Microchip Technology Inc.

DS20006404C-page 49

MCP3461/2/4R

The REFIN- pin is set as an input, directly connected to

the V_REF- input of theADC. For a better noise immunity,

it is recommended to connect this pin to A_GNDexter-

nally when a single-ended voltage reference is used.

Figure 6-10 shows more details of the reference

selection and reference pins connections.

5.7

Internal/External Voltage

Reference

5.7.1

VOLTAGE REFERENCE

SELECTION

The voltage reference selection for the ADC is

controlled by the VREF_SEL bit in the CONFIG0

register, as shown in Table 5-9.

TABLE 5-9:

VREF_SEL

ADC VOLTAGE REFERENCE SELECTION

Reference Input/Output Pins

Description

REFIN- Pin

_REF- Input

REFIN+/OUT Pin

0

External reference selected.

Internal reference buffer is shut

down. Internal reference is only

generating the internal 1.2V

Common-mode voltage for the

ADC.

V

V_REF+ Input

1

Internal reference selected with

2.4V buffered output.

V_REF- Input

(should be tied to A_GND

Internal Reference with 2.4V

Buffered Output

)

REFIN-

PAD

ADC V_REF

-

Input

REFIN+/OUT

PAD

ADC V_REF

+

Input

Chopped at DMCLK Rate if AZ_VREF = 1

VREF_SEL = 0 Off

VREF_SEL = 1 On

VREF_SEL

–

2x

+

V

_REFBuffer

–

ADC Internal

_CMVoltage

1x

V

+

Internal

Band Gap

Voltage

+

-

V_CMBuffer

1.2V

FIGURE 5-9:

Voltage Reference Selection Schematic.

DS20006404C-page 50

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

When VREF_SEL = 0, the reference voltage is set to

External mode. The REFIN+/OUT pin becomes an

input. In this case, the REFIN+/OUT pad is directly tied

to the V_REF+ input of the ADC. There is no input buffer

in the differential input voltage reference path in this

mode, so the external voltage reference should include

a buffer to be able to charge the internal voltage

reference sampling capacitors.

The offset induced by the buffer may slightly vary between

the two possible gain selections, as well as its tempera-

ture dependency and bandwidth; therefore, it has to be

characterized separately. The buffer injects a certain

quantity of 1/f noise into the system that can be modulated

with the incoming input signals and can limit the SNR

performance at higher OSR values (OSR > 256).

To overcome this limitation, the buffer includes an

auto-zeroing algorithm that greatly reduces (cancels

out) the 1/f noise and cancels the offset value of the

reference buffer. As a result, the SNR of the system is

not affected by this 1/f noise component of the refer-

ence buffer, even at maximum OSR values. This

auto-zeroing algorithm is performed synchronously

with the DMCLK and can be enabled or disabled with

the AZ_VREF bit setting in the CONFIG2 register.

When VREF_SEL = 1, the REFIN+/OUT is internally

buffered to produce a 2.4V buffered reference voltage

at the V_REF+ input of the ADC. Section 5.7.2 “Internal

Voltage Reference Buffer” details the architecture of

the voltage reference buffer.

In this mode, the REFIN+/OUT pin becomes an output

and the reference voltage is generated internally.

The structure of the internal voltage reference is based

on a band gap voltage reference source, giving a 1.2V

output directly connected to a low-noise chopper buffer,

configured with a gain of 2x, to give a 2.4V output on

the REFIN+/OUT pad. The internal reference has a

very low typical temperature coefficient of 15 ppm/°C

for extended temperature range and 9 ppm/°C for

industrial temperature range, allowing the ADC output

codes to have the least variation corresponding to the

temperature ranges, since they are proportional to

(1/V_REF).

When AZ_VREF = 1 (default), the auto-zeroing is

enabled, which cancels out the 1/f noise and improves

the SNR while not impacting the THD performance.

This mode is recommended for higher OSR values

(OSR 256).

When AZ_VREF = 0, the reference auto-zeroing algo-

rithm is disabled. This setting should be reserved to

lower OSR values, where higher ADC speed is more

important than accuracy.

If the application is susceptible to high-frequency noise,

using AZ_VREF = 0 or a proper low-pass filter at the

V_REFoutput pin (to filter out the chopper frequency

5.7.2

INTERNAL VOLTAGE REFERENCE

BUFFER

components

from

the

buffered

output)

is

When VREF_SEL = 1, the voltage reference buffer is

enabled. It is only powered on when the ADC state is in

Reset or in Conversion mode and is powered off in

Shutdown mode.

recommended.

The buffer is designed to be able to drive the ADC

reference input that is sampling the reference voltage.

The REFIN- pin is not buffered and is connected

directly to the ADC inverting voltage reference input

(V_REF-).

 2020-2021 Microchip Technology Inc.

DS20006404C-page 51

MCP3461/2/4R

If the CS pin is kept logic low during a POR state, a

logic high pulse is necessary to start the first communi-

cation sequence after power-up. The CS rising edge

will reset the SPI interface properly and the falling edge

will clear the POR interrupt on the IRQ pin (see

Figure 6-15).

5.8

Power-on Reset

The analog and digital power supplies are monitored

separately by two Power-on Reset (POR) monitoring

circuits at all times, except during Full Shutdown mode

(see Section 5.10 “Low-Power Shutdown Modes”).

Each POR circuit has two separate thresholds, one for

the rising voltage supply and one for the falling voltage

supply. They both include hysteresis (the rising thresh-

old is superior), so that the device is tolerant to a certain

degree of transient noise on each power supply.

The DV_DDand AV_DDmonitoring thresholds are different

since their respective voltage ranges are different. The

AV_DDrising threshold is approximately 1.75V ±10% and

the DV_DDis 1.2V ±10%. The hysteresis is approximately

150 mV (typical).

If any of the two power supply voltages is below its

respective threshold, the POR state is forced internally.

In this state, the SPI interface is disabled, no command

can be executed by the chip. All registers are cleared

and set to their default values.

Proper decoupling ceramic capacitors (0.1 µF and

10 µF ceramic) should be placed as close as possible

to the power supply pins (AV_DD, DV_DD) to provide

additional transient immunity.

During Full Shutdown mode, the power supply voltages

are not monitored to be able to reach ultra-low power

consumption. The device cannot generate a POR event

interrupt in this mode, except for cases of extremely

low-power supply voltages. See Section 5.10.1 “Full

Shutdown Mode”.

At power-up, when both power supply voltages are

above the rising thresholds, the device powers up and

the SPI interface is enabled and can handle communi-

cations. Since both thresholds need to be crossed for

the power-up, the power-up sequence is not important

and any power supply voltage can ramp up first. The

detection time for the monitoring circuits (t_POR) is about

1 µs for relatively fast power-up ramp rates. The normal

operation stops when any of the falling thresholds of

the two POR monitoring circuits is crossed. Figure 5-10

illustrates the power-up and power-down sequences.

In order to ensure a proper power-up sequence, the

ramp rate of DV_DDmust not exceed 3 V/µs when

coming out of the POR state.

Voltage

(AV_DD, DV_DD

)

POR Threshold Up

POR Threshold Down

t_POR

Time

POR State

Normal Operation

POR State

FIGURE 5-10:

Power-on Reset Timing Diagram.

DS20006404C-page 52

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MCP3461/2/4R

In MUX mode, overwriting the ADC_MODE[1:0] bits to

‘11’ when the ADC is already in conversion resets and

restarts the current conversion immediately. The

conversion start pulse will also be regenerated if the

EN_STP bit is enabled.

5.9

ADC Operating Modes

The ADC can be placed into three different operating

modes: ADC Shutdown, Standby and Conversion. The

ADC operating mode is controlled by the user through

the ADC_MODE[1:0] bits in the CONFIG0 register. The

user can directly launch conversions or place the ADC

into ADC Shutdown or Standby mode by writing these

bits. Additional Fast commands are available for each

of the three possible states of these bits to allow faster

programming in case of time-sensitive applications

(see Section 6.2.4 “Command-Type Bits (CMD[1:0])”).

Table 5-10 describes the available ADC_MODE[1:0]

bits setting.

In Scan mode (see Section 5.15 “Scan Mode”),

writing the ADC_MODE[1:0] bits to ‘11’ starts the

conversion Scan cycle. During the complete cycle,

even when the scan timer is enabled, reading the

ADC_MODE[1:0] bits gives a ‘11’ code output, mean-

ing that the Scan cycle is ongoing. Rewriting

ADC_MODE[1:0] = 11during Scan mode will immedi-

ately reset and restart the entire Scan sequence from

the beginning of the sequence. The conversion start

pulse will also be regenerated if the EN_STP bit is

enabled. The restart of the Scan sequence may induce

a T_{ADC_SETUP}additional delay if the ADC is in ADC

Shutdown mode when the ADC_MODE bits are over-

written (this can happen if the ADC_MODE bits are

overwritten during the timer delay period, where the

ADC is placed into ADC Shutdown mode in between

two Scan cycles).

The ADC_MODE[1:0] bits do not give an instantaneous

representation of the ADC state. Writing the

ADC_MODE[1:0] bits sets the desired state of the ADC,

but this state is only attained after a start-up time depend-

ing on the current state of the ADC (see Section 5.11

“ADC Start-up Timer” for details about the start-up

timer). Typically, the device starts in ADC Shutdown

mode after a POR (ADC_MODE[1:0] = 00by default). To

launch conversions in the desired configuration, the user

should program the part in the desired configuration and

then set the ADC_MODE[1:0] bits to ‘11’. In this case, the

first conversion will start after T_{ADC_SETUP}= 256 DMCLK

periods. This time is necessary for the part to adjust to the

new programmed settings and settle in to its operating

point to accurately convert the input signals.

The ADCDATA register is always updated with the last

conversion results. The ADCDATA register cannot

provide incomplete conversion results. The A/D con-

version must be completed to be able to provide a

result in the ADCDATA register. Each end of conver-

sion generates a data ready interrupt on all three IRQ

mechanisms (see Section 6.8.1 “Conversion Data

Ready Interrupt”). The ADCDATA register is never

cleared when the device transitions from one mode to

another. The only way to clear the ADCDATA register is

a POR event or a Full Reset Fast command (see

Section 6.2.5 “Fast Commands Description”).

Internally, the device tracks the current state of the

ADC, as well as the start-up timer counter, to be able to

optimize the start-up time depending on the desired

transitions and internal configurations required, and set

by the user.

TABLE 5-10: ADC OPERATING MODES DESCRIPTION

ADC_MODE[1:0]

ADC Mode

Description

11

Conversion

The ADC is placed into Conversion mode and consumes the specified

current. A/D conversions can be reset and restarted immediately once this

mode is effectively reached. This mode may be reached after a maximum of

T_{ADC_SETUP}time, depending of the current state of the ADC.

10

0x

Standby

Conversions are stopped. ADC is placed into Reset but consumes almost

as much current as in Conversion mode. A/D conversions can start immedi-

ately once this mode is effectively reached. This mode may be reached after

a maximum of T_{ADC_SETUP}time, depending of the current state of the ADC.

ADC Shutdown Conversions are stopped. ADC is placed into ADC Shutdown mode and

does not consume any current. A/D conversions can only start after

T_{ADC_SETUP}start-up time. This mode is effective immediately after being

programmed.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 53

MCP3461/2/4R

The part can still be accessed through the SPI interface

during this mode and will accept incoming SPI

commands. The ADCDATA register is not cleared

during Full Shutdown mode and still holds previous

conversion results. The other register settings are not

modified or reset due to entering Full Shutdown mode.

5.10 Low-Power Shutdown Modes

The device incorporates two low-power modes that can

be activated in order to limit power consumption of the

device when ADC is not used. These two modes are

called Partial Shutdown and Full Shutdown modes.

The Full Shutdown mode stops all internal timers and

resets them. Sending a Fast CMD to change the

operating mode exits the Full Shutdown mode.

5.10.1

FULL SHUTDOWN MODE

The Full Shutdown mode can only be enabled by

sending a Fast Command Full Shutdown (Fast com-

mand code: ‘1101’). Note that the execution of this

Fast command forces the CONFIG0 to be set to 0x00

(no active block is enabled).

The user should place all digital inputs to a static value

(logic low or high) in order to optimize power consumption

during Full Shutdown mode. The current consumption

specifications during Full Shutdown mode are intended

without any digital pin toggling during the measurement.

In this case, only leakage current is consumed throughout

the device and this current varies exponentially with

respect to absolute temperature.

Full Shutdown mode is the lowest power mode of the

device. None of the circuits consuming static power are

active in this mode.

As stated in Section 5.8 “Power-on Reset”, the

AV_DD/DV_DDPOR monitoring circuits are not active

while in Full Shutdown mode.

5.10.2

PARTIAL SHUTDOWN MODE

Partial Shutdown mode is achieved when CONFIG0 is

set to ‘0000000x’. In this mode, most of the internal

circuits are shut down, with the exception of the POR

monitoring and internal biasing circuits. During the

Partial Shutdown mode, the power supply is continu-

ously monitored, whereas in Full Shutdown mode, the

POR monitoring circuits are powered down. The power

consumption is also much higher in Partial Shutdown

mode due to the POR monitoring circuits being active.

Partial Shutdown mode allows the device to be

restarted and put back in Conversion mode faster than

Full Shutdown mode. Table 5-11 describes the differ-

ences between Partial and Full Shutdown modes. If the

current consumption of Partial Shutdown mode is

acceptable for the application, it is recommended that

it is used as an alternative to Full Shutdown mode,

where the POR monitoring circuits are shut down and

no longer monitoring the AV_DDand DV_DDpower

supplies.

Note:

If the digital power supply resides for a long

period of time below the POR threshold

and to a sufficiently low voltage (typically

below 0.6V), some bits previously set to ‘1’

can toggle to ‘0’ and not be set properly.

In order to ensure a safe operation after

the Full Shutdown mode, follow the

sequence of commands:

- Write LOCK register to 0xA5

- Write IRQ register to 0x03

- Send a Fast CMD Full Reset (1110)

- Reconfigure the chip as desired

This sequence ensures a recovery with

the desired settings in any loss-of-power

scenario.

TABLE 5-11: LOW-POWER MODES⁽¹⁾

Device

Low-Power Mode

VREF_SEL CONFIG0[6] CLK_SEL[1:0] CS_SEL[1:0] ADC_MODE[1:0]

Description

Partial Shutdown

0

00

0x

All peripherals, except the POR

monitoring circuits and clock bias-

ing circuits, are shut down and

consume no static current.The SPI

interface remains active in this

mode and consumes no current

while the bus is Idle.

Full Shutdown

0

00

All analog and digital circuits are

shut down and consume no static

current. The SPI interface remains

active in this mode and consumes

no current while the bus is Idle.

Note 1: x= Don’t Care

DS20006404C-page 54

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

The transition from Standby to Conversion mode and

vice versa is immediate once the timer has reached 0 (if

ADC_MODE[1:0] = 11). If the transition from Standby to

Conversion mode occurs, and if the timer has not yet

reached 0, the timer will continue to decrement to 0

before effectively starting the conversion. The timer

cannot decrement faster than 256 DMCLK periods when

the ADC transitions from ADC Shutdown mode to Con-

version mode (from ADC Shutdown mode, the ADC is

allowed 256 DMCLK periods to power-up and settle to

its desired operating point before starting conversions).

The start-up time has been sized at 256 DMCLK clock

periods for the part to be able to settle in all conditions

and with all possible clock frequencies as specified.

5.11 ADC Start-up Timer

The device includes an intelligent start-up timer circuit

for the ADC, which ensures that the ADC is properly

biased and that internal nodes are properly settled

before each conversion. This timer ensures the proper

conditions for the ADC to convert with its full accuracy

for each conversion.

The ADC can operate in three different modes: ADC

Shutdown, Standby and Conversion, as described in

Section 5.9 “ADC Operating Modes”. The ADC

start-up timer manages the time for the transitions

between each mode. These transitions can be instan-

taneous or can take a maximum of 256 DMCLK

periods, depending on the type of transition, and the

current status of the ADC and of the internal start-up

timer.

Table 5-12 summarizes the behavior of the internal

start-up timer as a function of the ADC_MODE[1:0] bits

setting.

The timer will always try to reduce the transition time

from one state to another, but will also allow enough

time for the internal circuitry to settle to the proper

internal operating points.

Rewriting ADC_MODE[1:0] bits without changing the

bit settings does not modify the internal timer and

cannot shorten the start-up delay necessary to start

accurate conversions. A synchronization delay of two

MCLK periods occurs after each rewrite if

ADC_MODE[1:0] = 1x.

The transitions from Standby or Conversion mode to

ADC Shutdown mode are always immediate. They

reset the internal start-up timer to 256 DMCLK periods

(T_{ADC_SETUP}).

In Scan mode, when CONV_MODE[1:0] = 11

(Continuous mode), the ADC may be placed in ADC

Shutdown mode and restarted in between each Scan

cycle depending on the TIMER[23:0] bits setting (see

Section 5.15.5 “Delay Between Scan Cycles

(TIMER[23:0])”). If the TIMER register is programmed

with a decimal code greater than T_{ADC_SETUP}= 256,

the internal timer will automatically place the part in

ADC Shutdown mode at the end of the cycle and will

start to transition to the next cycle 256 DMCLK periods

before the end of the TIMER delay.

The transitions from ADC Shutdown to Standby or

Conversion mode start the internal start-up timer that

decrements from 256 to 0. The timer only decrements

after a small delay of two MCLK periods in case of a

transition caused by an SPI command. This small delay

is necessary to overcome any possible synchronization

issue between the two asynchronous clocks: MCLK

and SCK. The timer will immediately decrement

(without the synchronization delay) if the transitions are

generated by the internal state machine (for example,

when the transitions are generated by the Scan

sequence). Once the timer reaches 0 (when the user

has clocked 256 DMCLK periods), the device reaches

its internal proper operating points and will either stay

in Standby mode (if ADC_MODE[1:0] = 10) or start the

Conversion mode (if ADC_MODE[1:0] = 11).

This lowers the power consumed during the TIMER

delay as much as possible. If the value of the TIMER

delay is less than 256 DMCLK periods, the part will not

enter ADC Shutdown mode and stay in Standby during

the TIMER delay (in this case, the power consumed is

equivalent to the Conversion mode power consumption).

In order to catch the start of the conversion in case of

complex sequences of transitions, it can be useful to

enable the EN_STP bit so that the part will generate a

pulse on the IRQ pin to indicate a conversion start.

Figure 5-11 shows different cases of transitions

between modes and shows the internal state of the

start-up timer for each step.

TABLE 5-12: ADC START-UP TIMER BEHAVIOR AS A FUNCTION OF ADC_MODE[1:0] SETTINGS

ADC_MODE[1:0]

ADC State

ADC Start-up Timer Behavior

11

Conversion

The ADC start-up timer decrements to 0. The conversion

starts when it reaches 0.

10

0x

Standby

The ADC start-up timer decrements to 0. The ADC is ready to

convert when it reaches 0.

ADC Shutdown

ADC start-up timer is reset to T_{ADC_SETUP}= 256.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 55

MCP3461/2/4R

DMCLK

Continuous Clocking

Write

ADC_M ODE =

SPI

1X

1x

ADC_M ODE =

1x

0x

1x

0x

1x

ADC_MODE

Timer Reset

Timer

Countdown

Timer Reset

Switching Between ADC_MODE = 10and 11

has no Effect on the Timer

256

ADC Start-up

Timer Decimal

Code

ADC Ready to Convert

0

FIGURE 5-11:

ADC Start-up Timer Timing Diagram.

5.12.1

EXTERNAL MASTER CLOCK MODE

(CLK_SEL[1:0] = 0x)

5.12 Master Clock Selection/Internal

Oscillator

The External Clock mode is used to input the MCLK

clock necessary for the ADC conversions and can

accept duty cycles with a large range since the clock is

redivided internally to generate the different internal

phases.

The device includes three possible clock modes for the

master clock generation. The Master Clock (MCLK) is

used by the ADC to perform conversions and is also used

by the digital portion to generate the different digital

timers. The clock mode selection is made through the

CLK_SEL[1:0] bits located in the CONFIG0 register. The

possible selections are described in Table 5-13.

The external clock can be provided on the MCLK pin for

the MCP3461/2/4R devices.

The master clock is not propagated in the chip when the

chip enters the Full Shutdown mode (see Section 5.10

“Low-Power Shutdown Modes”). Any change to the

CLK_SEL bits creates a Reset and Restart for the

currently running conversions, and a Restart of the ADC

setup timer. Each Reset and Restart resets all internal

phases to their default values and can lead to a possible

temporary duty cycle change at the clock output pin.

5.12.2

INTERNAL OSCILLATOR

The device includes an internal RC-type oscillator

powered by the digital power supply (DV_DD/D_GND). The

frequency of this internal oscillator ranges from

3.3 MHz to 6.6 MHz. The oscillator is not trimmed in

production, therefore, the precision of the center

frequency is approximately ±30% from chip to chip.

The duty cycle of the internal oscillator is centered

around 50% and varies very slightly from chip to chip.

The internal oscillator has no Reset feature and keeps

running once selected.

TABLE 5-13: CLOCK SELECTION BITS

CLK_SEL[1:0]

Clock Mode

MCLK Pin

00or 01

External Clock MCLK digital input

10

Internal RC

Oscillator,

High-Z

no clock output

11

Internal RC

Oscillator with

clock output

AMCLK digital

output

DS20006404C-page 56

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

The calculations are performed internally with proper

management of overloading, so that the overload

detection is done on the output result only and not on

the intermediate results. A sufficient number of addi-

tional overload bits are maintained and propagated

internally to overcome all possible overload and/or

overload recovery situations.

5.12.3

INTERNAL MASTER CLOCK

MODES (CLK_SEL[1:0] = 1x)

When CLK_SEL[1] = 1, the internal oscillator is selected

and the master clock is generated internally. The internal

oscillator has no Reset feature and continues to run

once selected. The master clock generation is indepen-

dent of the ADC as the clock can still be generated, even

if the ADC is in ADC Shutdown mode. The internal

oscillator is only disabled when CLK_SEL[1:0] = 0x. The

clock can be distributed to the dedicated output pin

depending on the CLK_SEL[0] bit. When the clock

output is selected (CLK_SEL[0] = 1), the AMCLK clock

derived from the MCLK (AMCLK = MCLK/PRESCALE)

is available on the output pin. The AMCLK output can

serve as the clock pin to synchronize the modulator out-

put or other MCP3461/2/4R devices that are configured

with CLK_SEL[1:0] = 00or 01.

For example, if ADCDATA (pre-calibration) + OFFSETCAL

is out of bounds, but (ADCDATA (pre-calibration) +

OFFSETCAL) x GAINCAL is still in the right range

(possible with 0 < GAINCAL < 1), the result is not

saturated.

5.13.1

DIGITAL OFFSET ERROR

CALIBRATION

The Offset Calibration register (OFFSETCAL,

address: 0x9) is a signed MSb first, two’s complement

coding, 24-bit register that holds the digital offset

calibration value, OFFSETCAL. The OFFSETCAL

equivalent input voltage value is calculated with

Equation 5-7.

The AMCLK output is available on the MCLK clock

output pin as soon as the Write command

(CLK_SEL[1:0] = 11) is finished.

5.13 Digital System Offset and Gain

Calibrations

EQUATION 5-7:

OFFSETCAL

CALIBRATION VALUE

(EQUIVALENT INPUT

VOLTAGE)

The MCP3461/2/4R devices include

a

digital

calibration feature for offset and gain errors. The cali-

bration scheme for offset error consists of the addition

of a fixed offset value to the ADC output code

(ADCDATA at address: 0x0). The offset value added

(OFFSETCAL) is determined in the OFFSETCAL

register (address: 0x9). The calibration scheme for gain

error consists of the multiplication of a fixed gain value

to the ADCDATA code. The gain value (GAINCAL)

multiplied is determined in the GAINCAL register

(address: 0xA).

OFFSETCAL (V) = V_REFx (OFFSETCAL[23:8]

signed decimal code)/(32768 x GAIN)

For the MCP3461/2/4R devices, the offset calibration

is done by adding the OFFSETCAL[23:8] calibration

value to the ADCDATA output code, bit by bit. The last

byte of the OFFSETCAL register (OFFSETCAL[7:0])

is ignored and internally reset to 0x00 during the cali-

bration; therefore, the addition just takes into account

the OFFSETCAL[23:8] bits and is done bit-by-bit with

the ADC output code.

The digital offset and gain calibration schemes are

enabled or disabled via the EN_OFFCAL and

EN_GAINCAL control bits of the CONFIG3 register.

When both calibration control bits are enabled

(EN_OFFCAL = EN_GAINCAL = 1), the ADCDATA

register is modified with the digital offset and gain cali-

bration schemes, as described in Equation 5-6. When a

calibration enable bit is off, its corresponding register

becomes a Don’t Care register and the corresponding

calibration is not performed.

The offset calibration value range in equivalent voltage

is [-V_REF/GAIN; (+V_REF– 1 LSb)/GAIN], which can

cancel any possible offset in the ADC but also in the

system. The offset calibration is realized with a simple

24-bit signed adder and is instantaneous (no pipeline

delay). Enabling the offset calibration will affect the

next conversion result; the conversion result already

held in the ADCDATA register (0x0) is not modified

when the EN_OFFCAL is set to ‘1’, but the next one

will take the offset calibration into account. Changing

the OFFSETCAL register to a new value will not affect

the current ADCDATA value, but the next one (after a

data ready interrupt) will take the new OFFSETCAL

value into account. Figure 5-12 presents the different

cases and their impact on the ADCDATA register and

the IRQ output.

EQUATION 5-6:

ADCDATA OUTPUT

AFTER DIGITAL GAIN

AND OFFSET ERROR

CALIBRATION

ADCDATA (post-calibration) =

[ADCDATA (pre-calibration) + OFFSETCAL] x GAINCAL

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DS20006404C-page 57

MCP3461/2/4R

Write

EN_OFFCAL

Write

SPI

OFFSEꢀTCAꢀL[23:ꢁ] = OFFSEꢀTCAꢀL1

=

1

OFFSEꢀTCAꢀL[23:ꢁ] = OFFSEꢀTCAꢀL2

ADC

STATUS

Data 1 Conversion

Data 2 Conversion

Data 3 Conversion

Data 4 Conversion

IRQ

ADC DATA

REGISTER

VALUE

DATA0

DATA1

DATA2 + OFFSETCAL1

DATA3 + OFFSETCAL2

FIGURE 5-12:

ADC Output and IRQ Behavior with Digital Offset Calibration Enabled.

error calibration is made with a simple add-and-shift

5.13.2

DIGITAL GAIN ERROR

CALIBRATION

circuit clocked on DMCLK and induces a pipeline

delay of T_GCAL= 15 DMCLK periods. This pipeline

delay acts as a delay on the data ready interrupt

position that is shifted by T_GCAL= 15 DMCLK periods.

The Gain Error Calibration register (GAINCAL,

address: 0xA) is an unsigned 24-bit register that holds

the digital gain error calibration value, GAINCAL.

Equation 5-8 calculates the GAINCAL multiplier.

During this delay, the converter can process the next

conversion, the delay does not shift the next conver-

sion and does not change the Conversion Time,

T_CONV. Enabling the gain error calibration will affect

the next conversion result. The conversion result

already held in the ADCDATA register (0x0) is not

modified when the EN_GAINCAL is set to ‘1’, but the

next one will take the offset calibration into account.

Changing the GAINCAL register to a new value will

not affect the current ADCDATA value, but the next

one (after a data ready interrupt) will take the new

GAINCAL value into account. Figure 5-13 shows the

different cases and their associated effects on the

ADCDATA register and the IRQ output.

EQUATION 5-8:

GAINCAL CALIBRATION

VALUE (MULTIPLIER

VALUE)

GAINCAL (V/V) = (GAINCAL[23:8] unsigned decimal

code)/32768

For the MCP3461/2/4R devices, the gain error

calibration is done by multiplying the GAINCAL value to

the ADC output code. The last byte of the GAINCAL

register (GAINCAL[7:0]) is ignored and internally reset to

0x00 during the calibration; therefore, the multiplication

just takes into account the GAINCAL[23:8] bits.

The gain error calibration value range in equivalent

voltage is [0; 2-2^-15], which can cancel any possible

gain error in the ADC and in the system. The gain

Write

EN_GAINCAL

Write

SPI

GAINCAL[23:ꢁ] = GAINCAL1

=

1

GAINCAL[23:ꢁ] = GAINCAL2

ADC

Data 1 Conversion

DATA0

Data 2 Conversion

DATA1

Data 3 Conversion

Data 4 Conversion

STATUS

IRQ

DATA2 x GAINCAL1

T_GCAL

DATA3 x GAINCAL2

ADCDATA

T_GCAL

FIGURE 5-13:

ADC Output and IRQ Behavior with Digital Gain Error Calibration Enabled.

DS20006404C-page 58

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

5.14 Conversion Modes

The ADC includes several Conversion modes that can

be selected through the CONV_MODE[1:0] bits located

in the CONFIG3 register. The ADC behavior, with

respect to these bits, depends on whether the ADC is

in MUX or Scan mode. Table 5-14 summarizes the

possible configurations.

TABLE 5-14: ADC CONVERSION MODES IN MUX OR SCAN MODES

ADC Behavior

CONV_MODE[1:0]

ADC Behavior (MUX Mode)

ADC_MODE[1:0] Bits Setting

(Scan Mode)

0x

Performs a one-shot conversion Performs one complete

Returns to ‘0x’ after one

and automatically returns to

ADC Shutdown mode.

Scan cycle and

automatically returns to

ADC Shutdown mode.

conversion (MUX mode) or one

Scan cycle (Scan mode).

10

11

Performs a one-shot conversion Performs one complete

Returns to ‘10’ after one

conversion (MUX mode) or one

Scan cycle (Scan mode).

and automatically returns to

Standby mode.

Scan cycle and

automatically returns to

Standby mode.

Performs continuous

conversions.

Performs continuous Scan Stays at ‘11’.

cycles with TIMER[23:0]

delay between each cycle.

In Continuous Conversion mode, the ADC is never

placed in Standby or ADC Shutdown mode and con-

verts continuously without any internal Reset. In this

mode, the output data rate of the ADC is defined by

DRCLK (see Figure 5-5). The digital decimation filter

induces a pipeline or group delay of T_CONVfor the first

data ready and is structured to give a continuous

stream of data at the DRCLK rate after these first data

(the internal registers of the filter are never reset in this

mode, thus the decimation filter acts as a moving aver-

age). Each data ready interrupt corresponds to a valid

and complete conversion that was processed through

the digital filter (the digital filter has no latency in this

respect). This mode allows a faster data rate than the

One-Shot mode, and is therefore, recommended for

higher bandwidth applications. The pipeline delay

should be carefully determined and adapted to the user

needs, especially in closed-loop, low-latency applica-

tions. This mode is recommended for applications

requiring continuous sampling/averaging of the input

signals. If AZ_MUX = 1, the Continuous Conversion

mode is replaced by a series of subsequent One-Shot

mode conversions with a reset in between each

conversion. This makes the group delay equal to

2 x T_CONVand the data rate equal to 1/(2 x T_CONV).

5.14.1

CONVERSION MODES IN MUX

MODE

In MUX mode, the user can choose between one-shot

and continuous conversions.

A one-shot conversion is a single conversion and takes

a certain Conversion Time, T_CONV(or 2 x T_CONVwhen

AZ_MUX = 1, see Section 5.1.3 “ADC Offset Cancel-

lation Algorithm”). Once this conversion is

performed, the part automatically returns to a Standby

or ADC Shutdown state, depending on the

CONV_MODE[1:0] bits setting. The Conversion mode

determined by the CONV_MODE[1:0] bits setting will

also affect the state of the ADC_MODE[1:0] as

described in Table 5-14.

The conversion can be preceded by a start-up time that

depends on the ADC state (see Section 5.11 “ADC

Start-up Timer”). In One-Shot mode, the ADC data

have to be read completely with the SPI interface for

the interrupt to be cleared on the IRQ pin (the IRQ pin

cannot be automatically cleared like in the Continuous

Conversion mode).

This mode is recommended for low-power, low

bandwidth applications, requiring a once in a while A/D

conversion.

Figure 5-14 and Figure 5-15 detail One-Shot and

Continuous Conversion modes for MUX mode.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 59

MCP3461/2/4R

ADC Data Read can be

Performed During this Time

t_DODR

Write

CONV_MODE =

Write

ADC_MODE =

Read ADC Data

SPI

or

10

0x

11

Don’t Care

Continuous Clocking

Don’t Care

MCLK

‘

’ or ‘ ’

0x 10

00

11

ADC_MODE

Depending on CONV_MODE[1:0]

ADC

STATUS

Partial Shutdown or Reset

Depending on CONV_MODE[1:0]

Partial Shutdown

Start-up

Conversion

T_CONV

T_{ADC_SETU P}

T_STP

IRQ

Conversion

Start

(Generates

Pulse if

EN_STP = 1)

IRQ is Cleared

at First SCK Falling Edge

After ADC Read Start

FIGURE 5-14:

MUX One-Shot Conversion Mode Timing Diagram.

Write

ODE =

Read A DC

Data 1

Read A DC

Data 2

Write

ADC_MODE =

11

SPI

CONV_M

11

Don’t Care

Continuous Clocking

MCLK

ADC_MODE

00

11

ADC

STATUS

Data 2

Conversion

Data 3

Conversion

Partial Shutdown

Start-up

Data 1 Conversion

T_CONV

T_{ADC_SETUP}

1/DRCLK

IRQ

T_DRH

FIGURE 5-15:

MUX Continuous Conversion Mode Timing Diagram.

DS20006404C-page 60

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

If CONV_MODE[1:0] = 11, the ADC runs in a Scan

Cycle mode with a TIMER[23:0] delay between cycles.

5.14.2

CONVERSION MODES IN SCAN

MODE

Writing the CONV_MODE[1:0] bits with the SPI inter-

face within a conversion does not create an internal

Reset. It is recommended not to wait for the end of a

conversion to change the CONV_MODE[1:0] bits to the

desired value, but to change to the desired value just

after the data are ready to avoid possible glitches.

Figure 5-16 and Figure 5-17, respectively, detail the

ADC timing behavior in One-Shot and Continuous

Conversion modes, when configured for Scan mode,

with N channels chosen among 16 Scan possibilities.

In Scan mode, the device takes one conversion per

channel and multiplexes the input to the next channel in

the Scan sequence. Therefore, all conversions are

One-Shot mode conversions, no matter how the

CONV_MODE[1:0] bits are set. Each conversion takes

the same time, T_CONV(or 2 x T_CONVwhen AZ_MUX = 1,

see Section 5.1.3 “ADC Offset Cancellation Algo-

rithm”), to be performed. If CONV_MODE[1:0] = 00, 01

or 10, the Scan cycle is executed once and then the

ADC is placed into Standby or ADC Shutdown mode.

Write

Read ADC Data 1

Read ADC Data N-1

Read ADC Data N

SPI

MCLK

CONV_MODE = 0x/10 ADC_MODE = 11

Don’t Care

Continuous Clocking

‘0x’ or ‘10’

00

11

ADC_MODE

Depending on CONV_MODE

ADC

Channel N Conversion

(Last in Cycle)

ADC Shutdown or Reset

Depending on CONV_MODE

ADC Shutdown

Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset

STATUS

T_{ADC_SETUP}

T_{DLY_SCAN}

T_DRH

T_CONV

T_DRH

IRQ

FIGURE 5-16:

Scan One-Shot Conversion Mode Timing Diagram.

Read ADC Data1

(New Cycle)

SPI

Write

CONV_MODE

Write

ADC_MODE = 11

Read ADC Data 1

Read ADC Data N-1

Read ADC Data N

=

11

MCLK

Don’t Care

Continuous Clocking

ADC_MODE

00

11

T_{ADC_SETUP}

ADC

Channel N Conversion

(Last in Cycle)

ADC Shutdown or Reset

Channel 1 Conversion Channel 2 Conversion

Reset

(New Cycle) (New Cycle)

ADC Shutdown

Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset

Start-up

STATUS

Depending on TIMER[23:0] Settings

T_{ADC_SETUP}

T_{DLY_SCAN}

T_DRH

T_{DLY_SCAN}

T_{TIMER_SCAN}

T_CONV

T_DRH

IRQ

T_DRH

Start-up Time is Reduced to 0

if T_{TIMER_SCAN}< 256 DMCLK

Periods

FIGURE 5-17:

Scan Continuous Conversion Mode Timing Diagram.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 61

MCP3461/2/4R

5.15.2

SCAN MODE ENABLE AND SCAN

CHANNEL SELECTION

5.15 Scan Mode

5.15.1

SCAN MODE PRINCIPLE

The ADC is, by default, in MUX mode at power-up. The

ADC enters Scan mode as soon as one of the

SCAN[15:0] bits in the SCAN register is set to ‘1’. MUX

mode and Scan mode cannot be enabled at the same

time. When SCAN[15:0] = 0x0000, Scan mode is dis-

abled and the part returns to MUX mode, where the

input channel selection is defined by the MUX[7:0] bits.

In Scan mode, the device sequentially and

automatically converts a list of predefined differential

inputs (also referred to as input channels) in a defined

order. After this series of conversions, the ADC can be

placed in Standby or ADC Shutdown mode, or it can

wait a certain time in order to perform the same

sequence of conversions periodically.

The Scan cycle conversions are effectively started as

soon as the ADC_MODE[1:0] bits are programmed

through the SPI interface to ‘11’ (direct Write or Fast

command, ADC Reset and Restart). After the

ADC_MODE[1:0] bits are set to ‘11’, they keep the same

value until the Scan mode is completed or aborted.

This mode is useful for applications that require

constant monitoring of defined channels or internal

resources (like AV_DDor VCM), and allow a minimal and

simplified communication.

When in Scan mode, the MUX register (address: 0x6)

becomes a Don’t Care register.

Each SCAN[15:0] bit defines a possible input channel for

the Scan cycle, which corresponds to a certain selection

of the analog multiplexer input channel and possibly a

certain predefined gain of the ADC. The Scan cycle will

process and convert each channel that has been enabled

(SCAN[n] = 1) with a defined order of priority, from MSb to

LSb (SCAN[15] to SCAN[0]). The list of channels with

their corresponding inputs is defined in Table 5-15.

Scan mode includes a configurable delay between

each Scan cycle, as well as a configurable delay

between each conversion within a Scan cycle.

Each conversion within the Scan cycle leads to a data

ready interrupt and to an update of the ADCDATA

register as soon as the current conversion is finished.

The device does not include additional memory to

retain all Scan cycle A/D conversion results. Therefore,

each result has to be read when it is available and

before it is overwritten by the next conversion result.

When using DATA_FORMAT[1:0] = 11, each channel

conversion result in the Scan sequence can be identi-

fied with a Channel ID (CH_ID[3:0]) code that will

appear in the four MSbs of the ADCDATA register out-

put value (Section 5.6 “ADC Output Data Format”).

The Channel ID indicates the channel that sends the

output data. Table 5-15 shows each possible Channel

ID value and its associated channel.

TABLE 5-15: ADC CHANNEL SELECTION

SCAN[n]

MUX[7:0]

Channel Name

Channel ID

Specific ADC Gain

Corresponding Setting

Bit⁽¹⁾

15

14

13

12

11

10

9

OFFSET

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

0x88

0xF8

0x98

0xDE

0x67

0x45

0x23

0x01

0x78

0x68

0x58

0x48

0x38

0x28

0x18

0x08

None

1x

V_CM

AV_DD

0.33x

1x

TEMP

Differential Channel D (CH6-CH7)

Differential Channel C (CH4-CH5)

Differential Channel B (CH2-CH3)

Differential Channel A (CH0-CH1)

Single-Ended Channel CH7

Single-Ended Channel CH6

Single-Ended Channel CH5

Single-Ended Channel CH4

Single-Ended Channel CH3

Single-Ended Channel CH2

Single-Ended Channel CH1

Single-Ended Channel CH0

None

8

7

6

5

4

3

2

1

0

Note 1: SCAN[11:9] and SCAN[7:2] are not available for MCP3461R. Writing these bits has no effect.

SCAN[11:10] and SCAN[7:4] are not available for MCP3462R. Writing these bits has no effect.

DS20006404C-page 62

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

The V_CMreading is susceptible to the gain and offset

errors of the ADC, which should be calibrated to obtain

a precise internal Common-mode measurement.

5.15.3

SCAN MODE INTERNAL

RESOURCE CHANNELS

5.15.3.1

Analog Supply Voltage Reading

(AV_DD

)

5.15.4

DELAY BETWEEN CONVERSIONS

WITHIN A SCAN CYCLE (DLY[2:0])

During the conversion that reads AV_DDin Scan mode,

the multiplexer selection becomes 0x98 (AV_DD– A_GND),

which is equal to the analog power supply voltage.

Since AV_DDis the highest voltage available in the chip,

when reading AV_DDin Scan mode, the gain of the ADC

is automatically set to 1/3x, which maximizes the input

full-scale range regardless of the GAIN[2:0] bits setting.

This temporary internal configuration does not change

the register settings, it only impacts the gain of the

device during this conversion.

While the ADC and multiplexer are optimized to switch

from one channel to another instantaneously, it may not

be the case of an application that requires additional

settling time to overcome the transition. The device can

insert an additional delay between each conversion of

the Scan cycle.

The delay value is controlled by the DLY[2:0] bits

located in the SCAN register (SCAN[23:20]). See

Table 5-16.

With this fixed 1/3x gain, the ADC can measure the

maximum specified analog supply voltage (AV_DD= 3.6V)

with a reference voltage as low as 1.2V.

TABLE 5-16: DELAY BETWEEN

CONVERSIONS WITHIN A

SCAN CYCLE

5.15.3.2

Temperature Reading (TEMP)

Delay Value

DLY[2:0]

During the conversion that reads TEMP in Scan mode,

the multiplexer selection becomes 0xDE, which

enables the two temperature diode sensors at each

input of the ADC. During the temperature reading, the

ADC gain is automatically set to 1x regardless of the

GAIN[2:0] bits setting. This temporary internal configu-

ration does not change the register setting, it only

impacts the gain of the device during this conversion.

(DMCLK Periods)

111

110

101

100

011

010

001

000

512

256

128

64

32

16

8

5.15.3.3

Offset Reading (OFFSET)

During the conversion that reads OFFSET in Scan

mode, the differential MUX output is shorted to A_GND

(internally). The offset reading varies from part to part,

and over AV_DDand temperature. The reading of this

offset value can be used for the device offset calibration

or tracking of the offset value in applications.

0

The delay is only added in between two conversions of

the same Scan cycle. There is no delay added at the

end or the beginning of each Scan cycle due to the

DLY[2:0] bits setting.

There is no automatic offset calibration in the device,

so the user has to manually write the opposite (signed

value) of the offset measured into the OFFSETCAL

register to effectively cancel the offset on the

subsequent outputs.

During this delay, the ADC is internally kept in Standby

mode (ADC_MODE[1:0] = 10 internally, but the

ADC_MODE[1:0] bits are always read as ‘11’ through

the SPI interface).

The analog multiplexer switches to the next selected

input at the end of each conversion (i.e., at the begin-

ning of the added delay, so that the application has

additional time to settle properly).

5.15.3.4

V_CMReading (V_CM)

During the conversion that reads V_CM, the device

monitors the internal Common-mode voltage of the

device in order to ensure proper operation.

The V_CMvoltage of the device should be located at

1.2V ± 2% to ensure proper accuracy. With this setting,

the internal multiplexer setting becomes 0xF8

(V_CM– A_GND). In order to properly measure V_CM, the

reference voltage must be larger than 1.2V.

During the V_CMreading, the gain of the ADC is set to 1x

regardless of the GAIN[2:0] bits setting. This temporary

internal configuration does not change the register

setting, it impacts the gain of the device during this

conversion.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 63

MCP3461/2/4R

The device incorporates an automatic Reset and

Restart feature for the A/D conversions to avoid these

invalid data. Some register writes with the SPI interface

during a conversion will automatically reset and restart

the A/D conversion with the new settings.

5.15.5

DELAY BETWEEN SCAN CYCLES

(TIMER[23:0])

During Continuous mode, Scan cycles are processed

continuously, one after another, separated by a time

delay (T_{TIMER_SCAN}), which is defined by the TIMER

register (address: 0x8) value. During this delay, the

ADC is automatically placed into a power-saving mode

(Standby or ADC Shutdown). The T_{TIMER_SCAN}delay

offers better power efficiency for applications which run

a scan sequence periodically. Since the delay can be

very long, it allows synchronous applications with very

slow update rates without having to use an external

timer. The TIMER register defines the time,

T_{TIMER_SCAN}, between cycles with a 24-bit unsigned

value going from 0 to 16777215 DMCLK periods.

Table 5-17 details the TIMER values with respect to the

TIMER[23:0] code.

The automatic Reset and Restart feature behavior

depends on the register bits that are written by the SPI

interface.

5.16.1

REGISTER BIT MODIFICATIONS

NOT CAUSING RESET/RESTART

The first group of bits will not generate any Reset and

Restart. This group is composed of all the unused bits,

all the read-only bits and some digital settings, such

as the CONV_MODE[1:0], DATA_FORMAT[1:0],

CRC_FORMAT, EN_CRCCOM, IRQ_MODE[0],

EN_FASTCMD, EN_STP and LOCK[7:0] bits.

TABLE 5-17: TIMER DELAY VALUE

BETWEEN SCAN CYCLES

5.16.2

REGISTER BIT MODIFICATIONS

CAUSING IMMEDIATE

RESET/RESTART

T_{TIMER_SCAN}Delay

TIMER[23:0]

Value

(DMCLK Periods)

The second group of bits generates a Reset and a

Restart. The Reset is immediate, the Restart is only

valid after a period of two MCLK periods (necessary to

handle the Reset and ensures that the Restart is

synchronous with the master clock). This group is

composed of settings that do not induce an analog

operating point change. This group includes:

ADC_MODE[1:0], PRE[1:0], OSR[3:0], GAIN[2:0],

AZ_MUX, EN_OFFCAL, EN_GAINCAL, IRQ_MODE[1:0],

MUX[7:0] and DLY[2:0] bits. The EN_OFFCAL,

EN_GAINCAL and IRQ_MODE[1:0] bits generate the

Reset and Restart only if they are changed to a new

value. An overwrite of the same value has no effect. In

Scan mode, the Reset and Restart feature will just

restart the current conversion for this group of bits; the

Scan cycle is not modified and not restarted. The

MUX[7:0] bits can be changed within Scan mode

without generating a Reset and a Restart, since this reg-

ister is a Don’t Care during Scan mode. The DLY[2:0] bits

can be changed during the MUX mode without generat-

ing a Reset and Restart since these bits are Don’t Care

during the MUX mode. The OFFSETCAL[23:0] and

GAINCAL[23:0] bits only generate a Reset and a Restart

when written if their corresponding enable bit

(EN_OFFCAL, EN_GAINCAL) is enabled.

111111111111111111111111

111111111111111111111110

100000000000000000000000

000000000000000000000001

000000000000000000000000

16777215

16777214

8388608

1

0

The internal TIMER counter will decrement from the

T_{TIMER_SCAN}value to 0 and launch the new Scan cycle.

If the T_{TIMER_SCAN}value is greater than T_{ADC_SETUP}

(256 DMCLK periods), the device will enter ADC

Shutdown mode (ADC_MODE is set to ‘00’ internally)

at each end of a Scan cycle. When the internal TIMER

counter reaches 256, the device will start the ADC

during a T_{ADC_SETUP}time to be ready to convert when

the internal counter reaches 0.

If the T_{TIMER_SCAN}value is less than T_{ADC_SETUP}, the

part will be placed in Standby mode between Scan

cycles (ADC_MODE is set to ‘10’ internally).

ADC_MODE[1:0] bits in the CONFIG0 register can only

be read as ‘11’ by the SPI interface during the entire

Scan cycle and between Scan cycles.

The ADC_MODE[1:0] bits generate an immediate

Reset and Restart, but only if they are overwritten with

‘11’ (in any other case, the conversions are stopped).

Depending on the part being in MUX or Scan mode,

the Reset and Restart feature will reset the conversion

or the complete Scan cycle.

5.16 A/D Conversion Automatic Reset

and Restart Feature

When the A/D conversions are running, the user can

change the device configuration through the SPI inter-

face by writing any register. Some register settings

directly impact the conversion results and lead to

invalid ADC data if they are changed within a

conversion.

DS20006404C-page 64

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Depending on the phase between the AMCLK and the

SPI commands, the 2-MCLK delay can turn into a

4-MCLK delay to ensure the proper synchronization of

the device. If very precise synchronization is required,

it is recommended to not change the register configu-

rations (i.e., not during conversions) or to use the

EN_STP = 1setting so that the start of the conversions

can be clearly determined.

5.16.3

REGISTER BIT MODIFICATIONS

CAUSING DELAYED

RESET/RESTART

A third group of bits will generate a Reset and a Restart

that induce a new start-up delay (T_{ADC_SETUP}), so that

the internal analog operating points can be settled with

the new settings before the new conversion is started.

The Reset is immediate; the start-up timer is only

restarted after a period of two MCLK periods (necessary

to handle the Reset and to ensure that the Restart is

synchronous with the master clock). Overall, the delay

from the Reset to the actual Restart of the conversion

In MUX mode, the TIMER and SCAN registers do not

generate a Reset and Restart when written, except if

the SCAN register is modified to effectively enter into

Scan mode. In this case, the MUX mode is superseded

by the Scan mode immediately.

with the new settings is then 2 MCLK + T_{ADC_SETUP}

.

This group includes: CONFIG0 and the RESERVED

registers at addresses: 0xB and 0xC. The CONFIG0

bits induce a start-up timer delay only if they are

changed to a new value. If they are overwritten with the

same value, they will generate an immediate Reset and

Restart. In Scan mode, the Reset and Restart feature

will just restart the current conversion for this group of

bits, the Scan cycle is not modified and not restarted.

In Scan mode, a write access of the SCAN register,

during or between conversions within the Scan cycle,

will create a Reset and Restart of the whole Scan

sequence. Within the same conditions, a write access

on the TIMER register will not create a Reset and

Restart of the entire Scan sequence. However, during

the T_{TIMER_SCAN}delay between Scan cycles, a write

on the SCAN register does not generate a Reset and a

Restart of the entire sequence. Within the same condi-

tions, a write on the TIMER register generates a Reset

and a Restart of the entire sequence.

This third group of bits will induce a start-up timer delay,

even when ADC_MODE[1:0] = 10 or if the ADC is in

Standby mode.

During the Reset and Restart sequence, the Reset is

immediate and resets the internal phases to the original

state, which can lead to a discontinuity in the clock out-

put frequency if the AMCLK clock output is enabled. The

Restart is synchronous with the AMCLK generation and

is effective only after two MCLK periods. The Restart

also generates a conversion start pulse (only after the

two MCLK periods or the two MCLK + T_{ADC_SETUP}

necessary for the Restart) if enabled, for the user to be

able to align the system with the exact start of the new

conversion.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 65

MCP3461/2/4R

NOTES:

DS20006404C-page 66

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Once the part is locked (write-protected), an additional

checksum calculation also runs continuously in the

background to ensure the integrity of the full register

map. All writable registers of the register map are

processed through a CRC-16 calculation engine and

give a CRC-16 checksum that depends on the con-

figuration. This checksum is readable from the CRC

register and updated when MCLK is running. If there is

a change in the checksum, a CRC interrupt generates

a flag to warn the user that the configuration has been

corrupted.

6.0

6.1

SPI SERIAL INTERFACE AND

DEVICE OPERATION

Overview

The MCP3461/2/4R devices use an SPI interface to

read and write the internal registers. The device

includes a four-wire (CS, SCK, SDI, SDO) serial SPI

interface that is compatible with SPI Modes 0,0 and

1,1. Data are clocked out of the device on the falling

edge of SCK and data are clocked into the device on

the rising edge of SCK. In these modes, the SCK clock

can Idle either high (1,1) or low (0,0). The digital inter-

face is asynchronous with the MCLK clock that controls

the ADC sampling and digital filtering. All digital input

pins are Schmitt Triggered to avoid system noise

perturbations on the communications. The SPI interface

is maintained in a Reset state during POR.

The MCP3461/2/4R devices also include additional

digital signal pins, such as a dedicated IRQ interrupt

output pin and a Master Clock (MCLK) input/output pin,

which allow easier synchronization and faster interrupt

handling, facilitating the implementation of the device in

many different applications.

6.2

SPI Communication Structure

Each SPI communication starts with a CS falling edge

and stops with the CS rising edge. Each SPI communi-

cation is independent. When CS is logic high, SDO is

in high-impedance, the transitions on SCK and SDI

have no effect. Changing from SPI Mode 1,1 to an SPI

Mode 0,0 and vice versa is possible and must be done

while the CS pin is logic high. Any CS rising edge clears

the communication and resets the SPI digital interface.

See Figure 1-1 for the SPI timing details.

The MCP3461/2/4R devices’ interface has a simple

communication structure. Every communication starts

with a CS falling edge and stops with a CS rising edge.

The communication is always started by the

COMMAND byte (8 bits) clocking on the SDI input. The

COMMAND byte defines the command that will be

executed by the digital interface. It includes the device

address, the register address bits and the

command-type bits.

The MCP3461/2/4R digital interface is capable of

handling various Continuous Read and Write modes,

which allows for ADC data streaming or full register

map writing within only one communication (and there-

fore, with only one unique COMMAND byte). It also

includes single byte Fast commands. The device does

not include a Host Reset pin, but it includes an SPI Fast

command to be able to fully reset the part at any time

and place it back in a default configuration.

The COMMAND byte is typically followed by data bytes

clocked on SDI if the command type is a write and on

SDO if the command type is a read. The COMMAND

byte can also define a Fast command, and in this case,

it is not followed by any other byte. The following sub-

sections detail the COMMAND byte structure and all

possible commands.

During the COMMAND byte clocking on SDI, a

STATUS byte is also propagated on the SDO output to

enable easy polling of the device status. During this time,

the interface is full-duplex, but the part can still be used

by MCUs handling only half-duplex communications if

the STATUS byte is ignored.

The device family also includes advanced security

features to secure communication and alert users of

unwanted Write commands that change the desired

configuration. To secure the entire configuration, the

device includes an 8-bit lock code (LOCK[7:0]), which

blocks all Write commands to the full register map if the

value of the lock code is not equal to a defined pass-

word (0xA5). The user can protect its configuration by

changing the LOCK[7:0] value to 0x00 after full

programming, so that any unwanted Write command

will not result in a change in the configuration. Each SPI

read communication can be secured through a select-

able CRC-16 checksum provided on the SDO pin at the

end of every communication sequence. This checksum

computation is compatible with the DMA CRC hard-

ware of the PIC24 and PIC32 MCUs, as well as many

other MCU references, resulting in no additional

overhead for the added security.

6.2.1

COMMAND BYTE STRUCTURE

The COMMAND byte fully defines the command that

will be executed by the part. This byte is divided into

three parts: the device address bits (CMD[7:6]), the

command address bits (CMD[5:2]) and the

command-type bits (CMD[1:0]). See Table 6-1.

TABLE 6-1:

COMMAND BYTE

CMD[7] CMD[6] CMD[5] CMD[4] CMD[3] CMD[2] CMD[1] CMD[0]

Device Address

Bits

Register Address/Fast Command

Bits

Command Type

Bits

 2020-2021 Microchip Technology Inc.

DS20006404C-page 67

MCP3461/2/4R

6.2.2

DEVICE ADDRESS BITS (CMD[7:6])

6.2.3

COMMAND ADDRESS BITS

(CMD[5:2])

The SPI interface of the MCP3461/2/4R devices is

addressable, which means that multiple devices can

communicate on the same SPI bus with only one Chip

Select line for all devices. Each device communication

starts by a CS falling edge, followed by the clocking of

the device address (CMD[7:6]). Each device contains

an internal device address which the device can

respond to.

The COMMAND byte contains four address bits

(CMD[5:2]) that can serve two purposes. In case of a

register write or read access, they define at which

register address the first read/write is performed. In

case of a Fast command, they determine which Fast

command is executed by the device.

In case of a Write command on a read-only register, the

command is not executed and the communication

should be aborted (CS rising edge) to place another

command. All registers can be read; there is no

undefined address in the register map.

This address is coded on two bits, so four possible

addresses are available. Device address is hard-coded

within the device and should be determined when

ordering the device. The device address is part of the

device markings to avoid potential confusion (see

Sections 9.1 “Package Marking Information⁽¹⁾”).

6.2.4

COMMAND-TYPE BITS (CMD[1:0])

When the CMD[7:6] bits match the device address, the

communication will proceed and the part will execute

the commands defined in the control byte and its

subsequent data bytes.

The last two bits of the COMMAND register byte define

the command type. These bits are an extension of the

typical read/write bits present in most SPI communica-

tion protocols. The two bits define four possible

command types: Incremental Write, Incremental Read,

Static Read and Fast command. Changing the com-

mand type within the same communication (while CS is

logic low) is not possible. The communication has to be

stopped (CS rising edge) and restarted (CS falling

edge) to change its command type. The list of possible

commands, their type and their possible command

addresses are described in Table 6-2.

When the CMD[7:6] bits do not correspond to the

address hard-coded in the device, the command is

ignored. In this case, the SDO output will become

high-impedance, which prevents bus contention errors

when multiple devices are connected on the same SPI

bus (see Figure 6-2). The user has to exit from this

communication through a CS rising edge to be able to

launch another command.

TABLE 6-2:

CMD[5:2]

COMMAND TYPES TABLE

CMD[1:0]

Command Description

0xxx

100x

1010

1011

1100

1101

00

Don’t Care

ADC Conversion Start/Restart Fast Command (overwrites ADC_MODE[1:0] = 11)

ADC Standby Mode Fast Command (overwrites ADC_MODE[1:0] = 10)

ADC Shutdown Mode Fast Command (overwrites ADC_MODE[1:0] = 00)

Full Shutdown Mode Fast Command (overwrites CONFIG0[7:0] = 0x00 and

places the part in Full Shutdown mode)

1110

1111

00

01

10

11

Device Full Reset Fast Command (resets the entire register map to default value)

Don’t Care

ADDR

Static Read of Register Address, ADDR

Incremental Write Starting at Register Address, ADDR

Incremental Read Starting at Register Address, ADDR

DS20006404C-page 68

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MCP3461/2/4R

The STATUS byte structure is described in Figure 6-1.

6.2.5

FAST COMMANDS DESCRIPTION

There are five possible Fast commands available for

the MCP3461/2/4R devices. For each command, only

the COMMAND byte has to be provided on the SPI port

and the command is executed right after the

COMMAND byte has been clocked. The Fast com-

mand codes are detailed in Table 6-2. All undefined

command address codes for Fast commands will be

ignored and will have no effect. SDO will stay in

high-impedance after the COMMAND byte for a Fast

command until a CS rising edge is provided. The Fast

commands can be enabled or disabled by placing the

EN_FASTCMD bit in the IRQ register to ‘1’ (default).

Disabling Fast commands can increase the security of

the device because it can avoid the execution of

unwanted Fast commands, which can be useful in

harsh environments.

STAT[7] STAT[6] STAT[5] STAT[4] STAT[3] STAT[2] STAT[1] STAT[0]

DEV_ADDR

[1]

DEV_ADDR

[0]

DEV_ADDR

[0]

DR_STATUS

CRCCFG_ PO R_ST ATUS

ST ATUS

0

Device Address

Acknowledge bits

Interrupt Status bits

FIGURE 6-1:

STATUS Byte.

The first two bits are always equal to ‘0’ and SDO

toggles to ‘0’ as soon as a CS pin falling edge is per-

formed. This allows having an application with multiple

devices, with different device addresses, sharing one

common SPI bus and avoiding bus contention during

STATUS byte clocking.

The next three bits of the STATUS byte give a

confirmation (Acknowledge) of the hard-coded device

address. If the device address of the COMMAND byte

and the internal device address of the chip match, these

three bits will be transmitted and they are equal to:

The ADC Start/Restart command (command address:

‘1010’) overwrites the ADC_MODE[1:0] bits to ‘11’,

creating a conversion start (or a restart if the

conversion was already running).

• STAT[5:4] = DEV_ADDR[1:0]

• STAT[3] = DEV_ADDR[0]

The ADC Standby mode command (command

address: ‘1011’) overwrites the ADC_MODE[1:0] bits

to ‘10’ and places the ADC in Standby mode.

The STAT[3] bit allows the user to distinguish the SDO

output from a High-Impedance state (device address

not matched), as the bits, STAT[4] and STAT[3], are

complementary and will induce a deterministic toggle

on the SDO output.

The ADC Shutdown mode command (command

address: ‘1100’) overwrites the ADC_MODE[1:0] bits

to ‘00’ and places the ADC in ADC Shutdown mode.

The Full Shutdown mode command (command

address: ‘1101’) overwrites the CONFIG0 register to

0x00 and places the device in Full Shutdown mode

(see Section 5.10 “Low-Power Shutdown Modes”

for a full description of this mode).

If the two device address bits are not matched with the

internally hard-coded device address bits, SDO is

maintained in a High-Impedance state during the rest

of the communication and the command is ignored.

This behavior avoids potential bus contention errors if

multiple devices with different device addresses share

the same SPI bus. After the transmission of the first two

bits, only one device responds to the command (all

other devices with non-matching device addresses

keep the SDO in high-impedance). In this case, the

user needs to abort the communication (CS rising

edge) in order to perform another command.

The Full Reset command (command address: ‘1110’)

resets the device and places the entire register map

into its default state condition, including the non-

writable registers. The only difference with a POR

event is that the POR_STATUS bit in the IRQ register

is set to ‘1’ after a Full Reset and is reset to ‘0’ after a

POR event. The user can only clear the ADC Data

Output register to its default value by using the Full

Reset command.

The three LSbs of the STATUS byte are the three

Interrupt Status bits:

• STAT[2] = DR_STATUS (ADC data ready interrupt

status)

6.2.6

DEVICE ADDRESS AND STATUS

BYTE DURING CONTROL BYTE

• STAT[1] = CRCCFG_STATUS (CRC checksum

error on the register map interrupt status)

During the COMMAND byte clocking on the SDI pin,

the SDO pin displays a STATUS byte to help the user

retrieve quick interrupt status information.

• STAT[0] = POR_STATUS (POR interrupt status)

The STATUS byte allows fast polling of the different

interrupts without having to read the IRQ register. How-

ever, it requires an MCU that can communicate in

Full-Duplex mode (SDI and SDO are clocked at the

same time). For MCUs that are only half-duplex, and

for devices that do not incorporate a separate IRQ pin,

or for applications that do not connect the existing IRQ

pin, the polling of the IRQ status can still be done by

reading the IRQ register continuously.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 69

MCP3461/2/4R

These three Interrupt Status bits are independent of the

two other interrupt mechanisms (IRQ pin and IRQ

register) and are cleared each time the STATUS byte is

fully clocked. This enables the polling on the STATUS

byte as a possible interrupt management solution with-

out requiring to connect the IRQ pin in the system. All

Status bit values are latched together just after the

device address has been correctly recognized by the

chip. Any interrupt happening after the two first Status

bits have been clocked out will appear in the STATUS

byte of the subsequent communication sequence.

Figure 6-2 represents the beginning of each

communication with both COMMAND and STATUS

bytes depicted. After the STATUS byte is propagated,

the SDO pin will be placed in high-impedance for Fast

commands or Write commands and will transfer data

bytes for Read commands as long as the CS pin stays

logic low.

Device Latches SDI on Rising Edge

Device Latches SDO on Falling Edge

CS

SPI Mode 1,1

SCK

SPI Mode 0,0

Don’t Care

SDI

Device

Address

Command

Type

Register

Address

High-Z

SDO

0

Device Address

Matches CMD[7:6]

Device

Address ACK

Interrupts

Status

High-Z

SDO

0

Device Address

does not Match

CMD[7:6]

FIGURE 6-2:

SPI Communication Start (COMMAND Byte on SDI and STATUS Byte on SDO) when

the Device Address Matches/Does Not Match CMD[7:6].

DS20006404C-page 70

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MCP3461/2/4R

6.3

Writing to the Device

When the command type is Incremental Write

(CMD[1:0] = 10), the device enters Write mode and

starts writing the first data byte to the address given in

the CMD[5:2] bits.

CONFIG0 (0x1)

CONFIG1 (0x2)

CONFIG2 (0x3)

CONFIG3 (0x4)

IRQ (0x5)

After the STATUS byte has been transferred, SDO

stays in a High-Impedance state during an Incremental

Write communication. Writing to a read-only address

(such as addresses: 0x0 or 0xF) has no effect and does

not increment the Address Pointer. The user must stop

the communication and restart a communication with a

COMMAND byte pointing to a writable address (0x1

to 0xD).

MUX (0x6)

SCAN (0x7)

TIMER (0x8)

Each register is effectively written after receiving the

last bit for the register (SCK last rising edge). Any CS

rising edge during a write communication aborts the

current writing. In this case, the register being written

will not be updated and will keep its old value.

OFFSETCAL (0x9)

GAINCAL (0xA)

Reserved (0xB)

Reserved (0xC)

LOCK (0xD)

The registers may need 8, 16 or 24 bits to be effectively

written, depending on their address (see Table 8-1).

After each register is written, the Address Pointer is

automatically incremented as long as CS stays logic

low. When the Address Pointer reaches 0xD, the next

register to be written is the 0x1 register (see Figure 6-3

for a graphical representation of the address looping).

Reserved (0xE)

Internal registers located at addresses, 0xB, 0xC and

0xE, should be kept to their default state at all times for

proper operation. These are reserved registers and

should not be modified.

FIGURE 6-3:

Incremental Write Loop.

The Incremental Write feature can be used in order to

fully configure the part using a unique communication

which can save time in the application. This unique

communication can end at address 0xD so that the

user can also lock the configuration when written,

providing additional security in the application (see

Section 6.6 “Locking/Unlocking Register Map

Write Access”).

Figure 6-4 shows an example of a write communication

in detail with a single register write. Figure 6-5 shows an

example of an Incremental Write communication.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 71

MCP3461/2/4R

CS

Device Latches SDI on Rising Edge

SCK

Don’t care

DATA<23>

Don’t care

SDI

High-Z

0

SDO

0

SPI Mode 0,0; Example with a 24-Bit Wide Register Located at Address CMD<5:2>

CS

SCK

SDI

Device Latches SDI on Rising Edge

Don’t

care

Don’t care

0

DATA<0>

High-Z

0

A<6>

SDO

0

SPI Mode 1,1; Example with a 24-Bit Wide Register Located at Address CMD<5:2>

FIGURE 6-4:

Single Register Write Communication (CMD[1:0] = 10) Timing Diagram.

CS

ADDRESS SET

0x1

Depends on

ADDR

Depends on

ADDR + 1

8x

...

8x

...

8x

...

ADDR

...

SCK

Complete

WRITE

Sequence

COMMAND

BYTE

Don’t care

ADDR

ADDR + 1

ADDR = 0xD

ADDR = 0x1

ADDR = 0x2

ADDR = 0xD

SDI

CMD<7:6> + ADDR +10

Complete WRITE Sequence

0xD

Roll-over

Hi-Z

00xxxxxx

SDO

0

Depends on IRQ Status

and Device Address

FIGURE 6-5:

Multiple Register Write Within One Communication Using Incremental Write Feature.

DS20006404C-page 72

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

6.4

Reading from the Device

When the Command bit, CMD[0], is equal to ‘1’, the

command is a read communication. After the STATUS

byte has been transferred, the first register to be read

on the SDO pin is the one with the address defined by

the Command Address bits (CMD[5:2]).

ADCDATA (0x0)

CONFIG0 (0x1)

CONFIG1 (0x2)

CONFIG2 (0x3)

CONFIG3 (0x4)

IRQ (0x5)

Any CS rising edge during a read communication

aborts the current reading.

The registers may need 4, 8, 16, 24 or 32 bits to be fully

read depending on their address (see Table 8-1).

If the CMD[1:0] bits are equal to ‘11’, the command

type is Incremental Read. In this case, after each

register is read, the Address Pointer is automatically

incremented as long as CS stays logic low. The

following data bytes are read from the next address

sequentially defined in the register map. When the

Address Pointer reaches 0xF (last register in the register

map for reading), the next register to read is register 0x0

(see Figure 6-6 for a graphical representation of the

address looping).

MUX (0x6)

SCAN (0x7)

TIMER (0x8)

OFFSETCAL (0x9)

GAINCAL (0xA)

Reserved (0xB)

Reserved (0xC)

LOCK (0xD)

Reserved (0xE)

CRCREG (0xF)

FIGURE 6-6:

Incremental Read Loop.

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DS20006404C-page 73

MCP3461/2/4R

If the CMD[1:0] bits are equal to ‘01’, the command

type is Static Read. In this case, the register address

defined in the COMMAND byte is read continuously.

The Address Pointer is automatically incremented.

Continuously clocking SCK while CS stays logic low

will continuously read the same register. Reading

another register is only possible by aborting the current

communication sequence by raising CS and issuing

another command.

In both Static and Incremental modes, the registers

are updated after each register read is fully performed.

If the value of the register changes internally during

the read, it will only be updated after the end of the

read. The value of each register is latched in the SDO

Output Shift register at the first rising edge of SCK of

each individual register reading. Figure 6-7 shows the

bit by bit details of a single register Read communica-

tion. Figure 6-8 shows the examples of Static and

Incremental Read communications.

CS

Device Latches SDI on Rising Edge

Device Latches SDO on Falling Edge

SCK

SDI

Don’t Care

1

High-Z

DATA<23>

Don’t Care

0

SDO

0

SPI Mode 0,0 ; Example with a 24-Bit Wide Register Located at Address CMD<5:2>

CS

Device Latches SDI on Rising Edge

Device Latches SDO on Falling Edge

SCK

SDI

Don’t Care

1

High-Z

DATA<0>

0

A<6>

SDO

0

SPI Mode 1,1; Example with a 24-Bit Wide Register Located at Address CMD<5:2>

FIGURE 6-7:

Single Read SPI Communication (Static or Incremental Read).

DS20006404C-page 74

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

CS

Depends on

ADDR

Depends on

ADDR

Depends on

ADDR

8x

...

SCK

SDI

COMMAND

BYTE

Don’t Care

CMD[7:6] + ADDR + 01

High-Z

00XXXXXX

ADDR

...

ADDR

SDO

0

Depends on IRQ status

and device address

Complete READ

sequence

Static Read Sequence

CS

ADDRESS SET

0x0

Depends on

ADDR

Depends on

ADDR+1

Depends on

Data Format

8x

...

16x

8x

...

16x

...

ADDR

...

SCK

SDI

Complete

READ

sequence

COMMAND

BYTE

Don’t Care

CMD[7:6] + ADDR + 11

0xF

Roll-over

High-Z

00XXXXXX

ADDR

ADDR + 1

...

ADDR = 0xF

ADDR = 0x0

ADDR = 0x1

...

ADDR = 0xF

SDO

0

Depends on IRQ status

and device address

Complete READ sequence

Incremental Read Sequence

Static and Incremental Read SPI Communications.

FIGURE 6-8:

 2020-2021 Microchip Technology Inc.

DS20006404C-page 75

MCP3461/2/4R

If the COMMAND byte defines a Static Read of the

ADCDATA register (address: 0x0), the ADC data will be

present on SDO and will be updated continuously at

each read. In this case, when a data ready interrupt

occurs within a read, the data are not corrupted and will

be updated to a new value after the old value has been

completely read.

The ADC register contains a double buffer that

prevents data from being corrupted while reading it.

The part is able to stream output data continuously with

no additional command if the communication is not

stopped with a CS rising edge. Figure 6-9 represents

the continuous streaming of incoming ADCDATA

through the SPI port with both SPI Modes 0,0 and 1,1.

CS

The falling edge after Read Start

clears the DR interrupt on IRQ pin

The falling edge after Read Start

clears the DR interrupt on IRQ pin

Device latches SDI on rising edge

Device latches SDO on falling edge

SCK

SDI

Don’t care

Read Start

DATA0<31>

Hi-Z

DATA0<31>

DATA1<31>

SDO

IRQ

SDO changessynchronously with the IRQ

falling edge (DR interrupt flag)

only when MSB is present on SDO

DR Interrupt

(DATA1 is ready)

SPI Mode 0,0; ADC Data Format: 32-Bit

CS

SCK

SDI

The falling edge after Read Start

clears the DR interrupt on IRQ pin

The falling edge after Read Start

clears the DR interrupt on IRQ pin

Device latches SDI on rising edge

Device latches SDO on falling edge

Don’t care

R/W

Don’t care

Read Start

Hi-Z

DATA0<0>

SDO

IRQ

DR Interrupt

(DATA1 is ready)

SPI Mode 1,1; ADC Data Format: 32-Bit

Continuous ADC Read (Data Streaming) with SPI Mode 0,0 and 1,1.

FIGURE 6-9:

DS20006404C-page 76

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

For continuous reading of ADCDATA in SPI Mode 0,0,

once the data have been completely read after a data

ready interrupt, the SDO pin takes the MSb value of the

previous data at the end of the reading (falling edge of

the last SCK clock). If SCK stays Idle at logic low (by

definition of Mode 0,0), the SDO pin will be updated at

the falling edge of the next data ready pulse (synchro-

nously with the IRQ pin falling edge with an output

timing of t_DODR) with the new MSb of the data corre-

sponding to the data ready pulse. This mechanism

allows the device to continuously read ADC data

outputs seamlessly, even in SPI Mode (0,0).

When enabled, the CRC checksum (CRCCOM[15:0])

is propagated on SDO after each read communication

sequence.

In case of a Static Read command, the checksum is

propagated after each register read. In case of an

Incremental Read command, the checksum is propa-

gated after the last register read in the register map

(address: 0xF). Figure 6-11 and Figure 6-12 show

typical read communications in Static Read and

Incremental Read modes, respectively, when the

EN_CRCCOM bit is enabled. Since the STATUS byte

is propagated on SDO, it is part of the first message,

and therefore, it is included in the calculation of the first

checksum. For subsequent checksum calculations, the

message only contains the registers that are effectively

read in between two checksums.

In SPI Mode (1,1), the SDO pin stays in the last state

(LSb of previous data) after a complete reading, which

also allows seamless Continuous Read mode.

The ADC output data can only be properly read after a

t_DODRtime, after the data ready interrupt comes on the

IRQ pin. The t_DODRtiming is shorter than the time

necessary to input a command on the SDI pin, which

ensures proper reading when a new Read command is

triggered by the data ready interrupt. In case of contin-

uous reading (with CS pin kept logic low), the t_DODR

timing must be carefully handled by the MCU, but in

general, the interrupt service time is much longer than

the t_DODRtiming. Retrieving a data ready interrupt by

reading the STATUS byte or reading the IRQ register

automatically ensures that the t_DODRtiming is

respected.

The CRC-16 format displayed on the SDO pin depends

on the CRC_FORMAT bit in the CONFIG3 register (see

Figure 6-10). It can have a 16-bit or 32-bit format to be

compatible with both 16-bit and 32-bit MCUs. The

CRCCOM[15:0] bits calculated by the device do not

depend on the format (the device always calculates a

16-bit only CRC checksum).

CRC_FORMAT = 0: 16-Bit

CRCCOM[15:0]

(Default)

0x0000

CRC_FORMAT = 1: 32-Bit

FIGURE 6-10:

Communications.

CRC Format Table for Read

6.5

Securing Read Communications

through CRC-16 Checksum

Since some applications can generate or receive large

EMI/EMC interferences and large transient spikes, it is

helpful to secure SPI communications as much as

possible, to maintain data integrity and desired

configurations during the application’s lifetime.

The CRC calculation computed by the device is fully

compatible with the CRC hardware contained in the

Direct Memory Access (DMA) of the PIC24 and PIC32

MCU product lines. The CRC message that should be

considered in the PIC^®device DMA is the concatena-

tion of the read sequence and its associated

checksum. When the DMA CRC hardware computes

this extended message, the resulted checksum should

The communication data on the SDO pin can be

secured through the insertion of a Cyclic Redundancy

Check (CRC) checksum at the end of each read

sequence. The CRC checksum on communications

can be enabled or disabled through the EN_CRCCOM

bit in the CONFIG3 register. The CRC message

ensures the integrity of the read sequence bits

transmitted on the SDO pin.

be 0x0000. Any other result indicates that

a

miscommunication has occurred and that the current

communication sequence should be stopped and

restarted.

The CRC checksum in the MCP3461/2/4R devices

uses the 16-bit CRC-16 ANSI polynomial as defined in

the IEEE 802.3 Standard: x¹⁶+ x¹⁵+ x²+ 1.

This polynomial can also be noted as 0x8005. CRC-16

detects all single and double-bit errors, all errors with

an odd number of bits, all burst errors of 16 bits in

length or less and most errors for longer bursts. This

allows an excellent coverage of the SPI communication

errors that can occur in the system, and heavily

reduces the risk of a miscommunication, even under

noisy environments.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 77

MCP3461/2/4R

CS

16x or 32x

Depending on

CRC format

16x or 32x

Depending on

CRC format

Depends on

ADDR

Depends on

ADDR

8x

...

SCK

ADDRESS SET

ADDR

Roll-over

COMMAND

BYTE

Don’t Care

SDI

CRC Checksum

CMD[7:6] + ADDR + 01

High-Z

STATUS

ADDR

CRC Checksum

First checksum

ADDR

CRC Checksum

New checksum

...

SDO

BYTE

0

Complete READ sequence including STATUS Byte

= First Message for CRC Calculation

New message

FIGURE 6-11:

SPI Static Read with Communication CRC Enabled.

CS

ADDRESS SET

0x0

16x or 32x

Depending on

CRC format

Depends on Depending on

Depends on

Data Format

8x

...

16x

Depending on

CRC format

8x

...

24x

...

ADDR

...

SCK

ADDR

ADDR+1

Complete

READ

sequence

COMMAND

BYTE

Don’t Care

SDI

CMD[7:6] + ADDR + 11

0xF

Roll-over

High-Z

STATUS

BYTE

(not part of register map)

ADDR

ADDR + 1

...

ADDR = 0xF CRC Checksum ADDR = 0x0

First Checksum

ADDR = 0x1

...

ADDR = 0xF CRC Checksum

New Checksum

CRC Checksum

SDO

0

Complete READ sequence including STATUS Byte

= First Message for CRC Calculation

New Message

FIGURE 6-12:

SPI Incremental Read with Communication CRC Enabled.

DS20006404C-page 78

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Since this feature is intended to protect the

configuration of the device, this calculation is run

continuously only when the register map is locked

(LOCK[7:0]), which is different than 0xA5 (see

Section 6.6 “Locking/Unlocking Register Map

Write Access”). If the register map is unlocked (for

example, after POR), the CRCCFG[15:0] bits are

cleared and no CRC is calculated.

6.6

Locking/Unlocking Register Map

Write Access

The MCP3461/2/4R digital interface includes an

advanced security feature that allows locking or unlock-

ing the register map write access. This feature prevents

the miscommunication that can corrupt the desired

configuration of the device, especially an SPI read

becoming an SPI write because of the noisy

environment.

The

DR_STATUS,

CRCCFG_STATUS

and

POR_STATUS bits are set to ‘1’ (default) and the

CRCCFG[15:0] bits are set to ‘0’ (default) for this calcu-

lation, as they could vary and lead to unwanted CRC

errors.

The last register address of the incremental write loop

(0xD: LOCK) contains the LOCK[7:0] bits. If these bits

are equal to the password value (0xA5), the register

map write access is not locked. Any write can take

place and the communications are not protected. The

devices are, by default after POR, in an unlocked state

(LOCK[7:0] = 0xA5).

After the DR_STATUS, CRCCFG_STATUS and

POR_STATUS bits are cleared (with a read on the IRQ

register), the CRC checksum on the register map can

be verified by reading all registers in an Incremental

Read sequence and by using the CRC communication.

At the second incremental read loop, the checksum

provided by the CRC communication must be equal to

all zeros if the checksum on the register map is correct.

When the LOCK[7:0] bits are not equal to 0xA5, the

register map write access is locked. The register map,

and therefore, the full device configuration is write-

protected. Any write to an address other than 0xD will

yield no result. All the register addresses, except the

address 0xD, become read-only. In this case, if the user

wants to change the configuration, the LOCK[7:0] bits

have to be reprogrammed back to 0xA5 before sending

the desired Write command.

The checksum will be calculated for the first time in

11 DMCLK periods. This first value will then be the

reference checksum value and will be latched internally

until an unlocking of the register map occurs. The

checksum will then be calculated continuously every

11 DMCLK periods and checked against the reference

checksum.

The LOCK[7:0] bits are located in the last register of the

Incremental Write address loop, so the user can pro-

gram the entire register map, starting from 0x1 to 0xD,

within one continuous write sequence and then lock the

configuration at the end of the sequence by writing all

zeros (for example) in the 0xD address.

If the checksum is different than the reference, an

interrupt flag will be generated on the CRCCFG_STATUS

bit within the STATUS byte on SDO, on the

CRCCFG_STATUS bit in the IRQ register and on the

IRQ output pin. The interrupt flag is maintained on all

three mechanisms until the register map write access

is unlocked.

6.7

Detecting a Configuration Change

through CRC-16 Checksum on the

Register Map and its Associated

Interrupt Flag

When the part write access is unlocked, the interrupt on

the IRQ pin clears immediately and the two other inter-

rupt mechanisms are cleared when the interrupt is read

(read STATUS byte or read IRQ register). The CRC

interrupt can occur even if the IRQ pin is configured as

the MDAT modulator output. In this case, the interrupt

stays present and forces a logic low output on this pin

as long as the LOCK[7:0] register is locked (LOCK[7:0]

0xA5).

In order to prevent internal corruption and to provide

additional security on the register map configuration,

the MCP3461/2/4R devices include an automatic and

continuous CRC checksum calculation on the full

register map Configuration bits. This calculation is not

the same as the communication CRC checksum

described in Section 6.5 “Securing Read

Communications through CRC-16 Checksum”.

At power-up, the interrupt is not present and the

register map is unlocked. As soon as the user finishes

writing its configuration, the user needs to lock the

register map (for example, by writing 0x00 in the LOCK

bits) to be able to use the interrupt flag and to calculate

the checksum of the register map.

This calculation takes the contents of the register map,

from addresses 0x1 to 0xF, and produces a checksum

which is held in the CRCCFG[15:0] bits located in the

CRCCFG register (address: 0xF). The CRC checksum

for the register map uses the 16-bit CRC-16 ANSI poly-

nomial as defined in the IEEE 802.3 Standard:

x

¹⁶+ x¹⁵+ x²+ 1.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 79

MCP3461/2/4R

Additionally, there are three independent interrupt

mechanisms that allow the devices to be implemented

in many different applications and configurations. A

summary of the different mechanisms is available in

Table 6-3.

6.8

Interrupts Description

The MCP3461/2/4R devices incorporate multiple

interrupt mechanisms to be able to synchronize the

device with an MCU and to warn against external per-

turbations. There are four events that can generate

interrupt flags:

• Conversion Start

• Data Ready

• POR

• CRC Error on the Register Map Configuration

TABLE 6-3:

INTERRUPT DESCRIPTION SUMMARY TABLE

Interrupt Flag Type

Description

Clearing Procedure

STATUS Byte

Three Status bits (DR_STATUS,

Cleared when STATUS byte clocking is finished

(on the last SCK falling edge).

CRCCFG_STATUS, POR_STATUS) are

latched together after device address

detection and clocked out during each

command on the SDO STATUS byte.

IRQ Register Status

Bits

IRQ register Status bits can be read when Cleared when the IRQ register reading is

reading the address 0x5 (IRQ register).

The IRQ latching occurs at the beginning

of the IRQ register reading.

finished (on the last SCK falling edge).

IRQ Pin State

• When IRQ_MODE[1] = 0, the IRQ pin

can be asserted to logic low by any of

the interrupts.

• Conversion start interrupt is automatically

cleared at the beginning of a new

conversion cycle after a T_STPtiming.

• When IRQ_MODE[1] = 1, only POR

and CRC interrupts can assert the

IRQ pin to logic low.

• DR interrupt is cleared by the first SCK

falling edge of an ADC read, or

automatically 16 DMCLKs before a new

data ready in Continuous Conversion mode

or in Scan mode.

• POR interrupt is cleared on the first CS

falling edge when both AV_DDand DV_DD

monitoring circuits detect that their power

supply is over their respective thresholds.

• CRCCFG interrupt is cleared when the

device is unlocked (writing 0xA5 to LOCK

register) or when a Fast command ADC

start/restart conversion is performed.

DS20006404C-page 80

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

3. IRQ pin state. The interrupt generates an IRQ

pin falling edge (transition to logic low) as soon

as it happens.

6.8.1

CONVERSION DATA READY

INTERRUPT

The data ready interrupt happens when a new

conversion is ready to be read on theADCDATAregister.

This event happens synchronously with DMCLK and at

each end of conversion. This interrupt is implemented

with three different and independent mechanisms:

STATUS byte on SDO, IRQ register Status bit and IRQ

pin state.

The data ready interrupt is cleared by the first of the

following two events:

• First falling edge of SCK during an ADC Output

Data register read

• 16 DMCLK clock periods before current

conversion ends

1. STATUS byte on SDO. When the interrupt

occurs on the next STATUS byte transmitted on

SDO, the DR_STATUS bit will be logic low. Once

the STATUS byte has been transmitted, the

DR_STATUS bit appears as ‘1’ until a new

interrupt is present. If the interrupt occurs

between two STATUS byte transmissions, the

DR_STATUS bit on SDO will appear as equal to

‘0’ on the second reading.

If the user does not read the ADCDATA register in time

in Continuous Conversion mode or in Scan mode, the

IRQ pin will automatically reset to its Inactive state

16 DMCLKs prior to the new data ready interrupt. This

feature is designed in order to avoid the case where the

IRQ pin is logic low if the reading of ADC data is not

performed. The user can then determine exactly when

to expect the new data and can respect the t_DODR

timing in all cases to ensure a proper reading of the

ADC data. See Figure 6-13 for more details.

2. IRQ register Status bit. When the interrupt

occurs, the DR_STATUS bit in the IRQ register

is set to ‘0’. Once the IRQ register has been fully

read, this DR_STATUS bit is reset to ‘1’. If the

interrupt occurs between two readings of the

IRQ register, the IRQ register Status bit appears

as equal to ‘0’ on the second reading.

Transitiontime

t_DOD

R

DATA1 can be readduringthis time

DATA2 can be readduringthis time

COMMAND Byte

Read ADCDATA

COMMAND Byte

Read ADC DATA2

SPI

Read ADC DATA1

Read ADCDATA

ADCDATA

REGISTER

DATA0

DATA1

1/DRCLK

DATA2

1/DRCLK

T_CON

V

T_DRH

IRQ

Data Ready Interrupt

Interrupt is cleared

automatically if ADCDATA

has not been read in time

at first SCK falling edge

after ADCDATA read start

FIGURE 6-13:

Data Ready Interrupt IRQ Pin Timing Diagram.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 81

MCP3461/2/4R

This interrupt marks the beginning of a conversion

cycle. In case of a One-Shot mode or Continuous mode

conversion in MUX mode, it marks the start of the

sampling in the first conversion (after the ADC start-up

delay of 256 DMCLK periods). In case of a Scan mode,

it marks the start of the sampling in the first conversion

of the first Scan mode cycle. The host MCU can utilize

this interrupt to synchronize the start of the ADC con-

version and manage synchronous events together with

the conversion process (see Figure 6-14 for more

details).

6.8.2

CONVERSION CYCLE START

INTERRUPT

This interrupt is the only selectable one and the only

one not present in the STATUS byte on the SDO and

IRQ registers. It is only available on the IRQ pin. The

user can enable or disable this output by using:

• [EN_STP] = 1: The conversion start interrupt

output is enabled (default).

• [EN_STP] = 0: The conversion start interrupt

output is disabled.

00

11

ADC_MODE

1st Conversion in

Start-up

Shutdown

ADC STATUS

either MUX or SCAN mode

T_{ADC_ SETUP}

T_{CON V}

T_STP

IRQ

Conversion

Start IRQ

(EN_STP = 1)

Data Ready

IRQ

FIGURE 6-14:

Conversion Start IRQ Timing Diagram.

This interrupt output generates a falling edge on the

IRQ pin and is automatically cleared after a short

period of time, T_STP.

6.8.3.2

IRQ Register Status Bit

When the device has just powered up, the

POR_STATUS bit in the IRQ register is set to ‘0’. Once

the IRQ register has been fully read, this

POR_STATUS bit is once again reset to ‘1’. If a POR

event occurs between two readings of the IRQ register,

the IRQ register Status bit will appear as equal to ‘0’ on

the second reading. This mechanism can only work

when the power supplies are back above the POR

thresholds on the analog and digital cores.

6.8.3

POR INTERRUPT

The POR interrupt informs the user if a POR event has

happened or if the part is in a POR state when the IRQ

pin is used.

This interrupt is implemented with three different and

independent mechanisms: STATUS byte on SDO, IRQ

register Status bit and IRQ pin state.

6.8.3.3

IRQ Pin State

6.8.3.1

STATUS Byte on SDO

A Logic Low state is generated on the IRQ pin as soon

as the AV_DDor DV_DDmonitoring circuits detect a power

supply drop below their specified threshold.

When the device has just powered up, on the first

STATUS byte transmitted on SDO (first communica-

tion), the POR_STATUS bit is logic low. Once the

STATUS byte has been transmitted, the POR_STATUS

bit appears as ‘1’ until the part is powered down. If a

POR event occurs between two STATUS byte trans-

missions, and if the part is properly repowered up, the

POR_STATUS bit on SDO will appear as equal to ‘0’ on

the latter reading. This mechanism can only work when

the power supplies are back above the POR thresholds

on the analog and digital cores, as retrieving data from

the SPI port is not possible when the device is in a POR

state.

This POR interrupt can only be cleared when both

AV_DDand DV_DDare above their monitoring voltage

thresholds. When this condition is met, the POR

threshold is cleared by the CS falling edge. Therefore,

it means that if a CS falling edge does not clear the IRQ

pin state, the POR event is still in effect.

DS20006404C-page 82

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

This feature helps the user to know exactly when the

chip has powered up by polling with the CS pin and

checking the IRQ pin state at power-up (see

Figure 6-15 for more details).

Since this is a high-level priority interrupt, the POR

interrupt can happen at all times, even when MDAT is

enabled. In this case, having a constant logic low bit-

stream can indicate a probable POR event (or a fully

negative ADC saturation output code induced by a

large negative input voltage).

V_{POR_A}, V_{POR_D}

DV_DD

AV_DD

t_POR

POR

Internal State

High-Z

IRQ

CS

0

t_CSIRQ

Don’t Care

Chip Select

Starts Low

Clears POR interrupt

FIGURE 6-15:

POR IRQ Timing Diagram.

6.8.4 CRCCFG ERROR INTERRUPT

6.8.4.3

IRQ Pin State

The CRCCFG interrupt happens when an error in the

CRC-16 checksum has been detected in the register

map CRC calculation.

The CRCCFG error generates a Logic Low state on the

IRQ pin until it is cleared. The clearing of the CRCCFG

error can only be made by “unlocking” the device (write

0xA5 in the LOCK[7:0] register) or by sending a Fast

command start/restart ADC conversion. Unlocking the

device stops the CRC calculation, and therefore, clears

the associated interrupt. Sending an ADC start/restart

conversion Fast command resets the CRC calculation

and clears the interrupt.

This interrupt is implemented with three different and

independent mechanisms: STATUS byte on SDO, IRQ

register Status bit and IRQ pin state.

6.8.4.1

STATUS Byte on SDO

In case of a CRCCFG error on the next STATUS byte

transmitted on SDO, the CRCCFG_STATUS bit is logic

low. Once the STATUS byte has been transmitted, the

CRCCFG_STATUS bit appears as ‘1’ until a new inter-

rupt occurs. If the error is detected again between two

STATUS byte transmissions, the CRCCFG_STATUS

bit on SDO will appear as equal to ‘0’ on the second

reading.

This CRCCFG error can only occur in case of an

external perturbation (for example, EMI induced) that

causes the continuous calculation of the CRC on the

register map to be erroneous or in case the chip

integrity has been altered. Since both causes are

high-priority issues, the CRCCFG error has priority

over all other interrupts (except POR) and over the

MDAT output on the IRQ pin.

6.8.4.2

IRQ Register Status Bit

Note:

If MCLK starts running before the device is

locked, an interrupt can momentarily occur,

even if registers have not been corrupted. In

such a case, the user must send a

start/restart conversion Fast command,

which will clear the unwanted interrupt and

correctly restart the CRC calculations.

In case of a CRCCFG error, the CRCCFG_STATUS bit

in the IRQ register is set to ‘0’. Once the IRQ register is

fully read, the CRCCFG_STATUS bit is reset to ‘1’. If

the CRCCFG error happens again between two read-

ings of the IRQ register, the IRQ register Status bit will

appear as ‘0’ on the second reading.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 83

MCP3461/2/4R

NOTES:

DS20006404C-page 84

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

7.1

Typical Application for Absolute

Voltage Measurement

7.0

BASIC APPLICATION

CONFIGURATION

The MCP3461/2/4R devices are able to measure the

signal provided by sensors with absolute voltage out-

put. For such applications, the MCP3461/2/4R family

typically uses its internal voltage reference. For the

best performance, an external capacitor is recom-

mended on the REFIN+/OUT pin for noise filtering and

to provide more stability for the internal voltage

reference (See Section 3.1 “Differential Reference

Voltage Inputs: REFIN+/OUT, REFIN-”).

The MCP3461/2/4R devices can be used for various

precision Analog-to-Digital Converter applications. The

flexibility of its usage is given by the possibility of

configuring the ADC to fit the required application.

Anti-Aliasing Filters

R12

5%

100

0603

C6

J1

J3

J5

J7

0.1 μF

16V

CH0

CH1

0603

GNDA

C9

0.1 μF

16V

ADC

R6

5%

100

0603

3.3A

3.3D

0603

IRQ Pull-up

R5

100

5%

0603

R14

R17

10R

5%

10R

5%

C3

0.1 μF

16V

0603

3.3D

CH2

CH3

0.1 μF

0603

C11

C13 0.1 μF

0603

16V

C4

0.1 μF

C12

16V

0.1 μF

0603

C14 0.1 μF

16V

R8

100

0603

5%

0603

16V

R22

10k

GNDA

GND

5%

R7

100

0603

5%

0603

19

18

C2

AV_DD

DV_DD

0.1 μF

16V

RA14/ADC_IRQ

3

4

CH4

CH5

CH0

0603

CH1

CH2

CH3

CH4

CH5

CH6

CH7

C5

0.1 μF

16V

5

10R 5%

R10

0603

5%

16

15

0603 R18

0603

MCLK

RD3/ADC_CLKIN

RA14/ADC_IRQ

100

6

0603

R19

IRQ/MDAT

R9

100

5%

7

13

0603 R21

10R 5%

SDI

SDO

SCK

CS

RG8/ADC_MOSI2

RG7/ADC_MISO2

RG6/ADC_SCK2

RG9/ADC_CS2

14 R16

12 0603

11 R15

0603

10R5%

0603

C7

8

10R 5%

0603

R20

10R

5%

0.1 μF

16V

CH6

CH7

0603

9

C8

10

0.1 μF

16V

R11

100

5%

0603

2

1

21

REFIN+/OUT

REFIN-

EP

GNDA

GND

0603

20

17

AGND

DGND

MCP3464R

GNDA

C10

10uF

10V

0603

GNDA

FIGURE 7-1:

MCP3464R Application Example.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 85

MCP3461/2/4R

The ADC can be used in Differential or Single-Ended

mode due to the internal dual multiplexer (Figure 5-1).

The user can select the input connection settings from

the MUX register (Section 8.7 “Multiplexer (MUX)

Register”) by using the different settings available on

the positive and negative inputs of the ADC. The

single-ended configuration is achieved by selecting

A_GNDfor the V_IN- input of the ADC (MUX[3:0] = 1000)

or by selecting any CHn input channel for V_IN- and

connecting the corresponding CHn input channel to

The connection of the thermocouple to the ADC

requires minimal extra components. A differential input

structure is recommended. The cold junction can be

measured by using a digital temperature sensor, such

as MCP9804, connected to the MCU. If high accuracy

is not required, the cold junction temperature can be

estimated directly with the internal temperature sensor

of the ADC (see Figure 7-2).

7.2

Typical Application for

A_GND

.

Ratiometric Voltage Measurement

7.1.1

HIGH-SIDE AND LOW-SIDE

CURRENT SENSING

A wide range of sensors provides an output voltage

directly related to the power supply of the sensors.

These sensors are known as ratiometric output. These

sensors often have a Wheatstone bridge structure,

such as pressure sensors or load cells (Figure 7-3).

The ADC has the ability to perform differential

measurements with an analog input Common-mode

equal to or slightly larger than AV_DD, or equal to or slightly

lower than A_GND(see the Electrical Characteristics

table).

A differential input structure and a Kelvin connection

are required in order to achieve the most accurate

measurements. An anti-aliasing filter is required to

avoid aliasing of the oversampling frequency (DMCLK)

back into the baseband of the input signal and possible

corruption of the output data. Figure 7-1 provides an

example of an anti-aliasing filter.

R₁

V_IN

+

REFIN+/OUT

Input

Signal

RTD

MCP3461R

REFIN-

V_IN

-

For the measurement of voltages that can reach AV_DD

or a few mV higher, a gain setting of 0.33x is useful

since it increases the input range to a 3 x V_REFvalue,

so a 1.2V V_REFwill allow a theoretical input range of

3.6V. However, the maximum voltage that can be

measured is always bounded by AV_DD+ 0.1V in order

to limit excess leakage current at the input pins created

by the ESD structures. Therefore, in order to properly

measure 3.6V with a 1.2V voltage reference, it is

recommended to use an AV_DDsupply voltage as close

as possible to 3.6V.

FIGURE 7-3:

Ratiometric Connection.

Wheatstone Bridge

Others act as a single resistor with a value dependent

on temperature (pure metal resistance thermometer

RTD and negative temperature coefficient resistor

NTC). To accurately measure the signal from these

sensors, REFIN+/OUT is usually connected to the

same power supply of the sensor (Figure 7-4), as long

as this respects the specified voltage range on the

REFIN+/OUT pin (see the Electrical Characteristics

table.

7.1.2

THERMOCOUPLE CONNECTION

One of the most used temperature transducers in the

industry is the thermocouple. Thermocouples provide a

voltage dependent on the temperature difference

between cold junction and hot junction. This voltage is

in the order of magnitude of tens of µV/°C, which

requires amplification that can be provided by the

internal gain stage of the ADC.

R₂

Sensor

REFIN+/OUT

V_IN

+

Anti-aliasing

Filter

MCP3461R

V_IN-

REFIN-

R₁

C₁

C₂

A_GND

D_GND

FIGURE 7-4:

RTD Ratiometric Connection.

FIGURE 7-2:

Thermocouple Connection

to MCP3461R.

DS20006404C-page 86

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Another possibility, sometimes easier to implement in

terms of PCB layout, is to consider the MCP3461/2/4R

as an analog component, and therefore, connect AV_DD

to DV_DDand A_GNDto D_GNDwith a star connection. In

this scheme, the decoupling capacitors may be larger,

due to the ripple on the digital power supply (caused by

the digital filters and the SPI interface of the

MCP3461/2/4R) now causing glitches on the analog

power supply.

7.3

Power Supply Design and

Bypassing

In any system, the analog ICs (such as references or

operational amplifiers) are always connected to the

analog ground plane. The MCP3461/2/4R devices

should also be considered sensitive analog components

and connected to the analog ground plane. The ADC

features two pairs of power supply voltage pins: A_GND

and AV_DD, D_GNDand DV_DD. For best performance, it is

recommended to keep the two pairs of pins connected to

two different networks (see Figure 7-5), so that the

design will feature two ground traces and two power

supplies (see Figure 7-6).

Figure 7-6 shows an example of a power supply

schematic with separate DV_DDand AV_DD. A high-current

LDO (MCP1825) was used for the DV_DDline to be able

to power the MCU and other peripherals attached to the

MCU. A high PSRR LDO (MCP1754) is used for the

AV_DDthat goes to the ADC and a few other components

sensitive to noise. The Net tie is used to separate D_GND

The analog circuitry (including MCP3461/2/4R) and the

digital circuitry (MCU) should have separate power

supplies and return paths to the external ground refer-

ence, as described in Figure 7-5. An example of a

typical power supply circuit, with different paths for

analog and digital return currents, is shown in

Figure 7-6. A possible split example is shown in

Figure 7-7, where the ground star connection can be

located underneath the device with the exposed pad.

The split between analog and digital can be done under

the device, and AV_DDand DV_DDcan be connected with

lines coming under the ground plane. The two separate

return paths will eventually share a unique connection

point (star connection) in order to minimize coupling

between the two power supply domains.

from A_GND

.

I

D

I

A

C

0.1 ȝF

DV_DD

MCP3ꢁ6ꢂ5

V

D

AV_DD

A

MCU

A

D

GND

I

A

I

D

“Star” Point

D =

A =

-

FIGURE 7-5:

Separating Digital and

Analog Ground by Using a Star Connection.

5V

U2

MCP1825S-3.3V

1

3

VIN

VOUT

3.3D

C45

C11

0.1 μF

0603

C44

10 μF

TANT-B

5V_USB

C10

10 μF

TANT-B

0.1 μF

0603

9V

GND

U4

J9

LM1117-5V

J10

U3

+5V USB

+9V IN

D1

1

3

2

3

2

MCP1754-3.3V

VIN

VOUT

1

3

MRA4005

VIN

VOUT

3.3A

C15

Power Jack 2.5 mm

10 μF

TANT-B

C13

C14

C12

GND

10 μF

TANT-B

0.1 μF

0603

0.1 μF

0603

GND

Net Tie

GND

GNDA

FIGURE 7-6:

Power Supply with Separate Lines for Analog and Digital Sections (the “Net Tie”

Object Represents the Star Ground Connection).

 2020-2021 Microchip Technology Inc.

DS20006404C-page 87

MCP3461/2/4R

7.4

SPI Interface Digital Crosstalk

The MCP3461/2/4R devices incorporate a high-speed

20 MHz SPI digital interface. This interface can induce

crosstalk, especially with the outer channels closer to

the SPI digital pins (for example, CH7), if it is run at full

speed without any precautions. The crosstalk is caused

by the switching noise created by the digital SPI

signals. This crosstalk would negatively impact the

SNR in this case. The noise is attenuated if proper

separation between the analog and the digital power

supplies is put in place (see Sections 7.3 “Power

Supply Design and Bypassing”).

In order to further remove the influence of the SPI

communication on measurement accuracy, it is recom-

mended to add series resistors on the SPI lines to

reduce the current spikes caused by the digital switch-

ing noise (see Figure 7-1 where these resistors have

been implemented). The resistors also help to keep the

level of electromagnetic emissions low.

FIGURE 7-7:

Digital Circuits on the Layout (Shown on the

UQFN Package).

Separation of Analog and

The switching noise is also a linear function of the

DV_DDsupply voltage. In order to further reduce the

influence of the switching noise caused by SPI trans-

missions, the DV_DDdigital power supply voltage should

be kept as low a value as possible.

When remote sensors are used to reduce the sensitivity

to external influences, such as EMI, the wires that

connect the sensor to the ADC should form a twisted

pair. Ferrite beads can be used between the digital and

analog ground planes to keep high-frequency noise

from entering the device. A low-resistance ferrite bead

is recommended.

The measurement graphs provided in this

“MCP3461/2/4R Data Sheet” have been performed

with 10 series resistors connected on each SPI I/O

pin. Measurement accuracy disturbances have not

been observed, even at 20 MHz interfacing.

DS20006404C-page 88

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

8.0

INTERNAL REGISTERS

The MCP3461/2/4R devices have a total of 16 internal

registers made of volatile memory. Table 8-1 includes a

summary of the registers. These registers are

sequentially accessible.

TABLE 8-1:

INTERNAL REGISTERS SUMMARY

No. of

Address Register Name

R/W

Description

Bits

0x0

ADCDATA

CONFIG0

4/16/32

R

Latest A/D conversion data output value (16 or 32 bits depending on

DATA_FORMAT[1:0]) or modulator output stream (4-bit wide) in MDAT

Output mode

0x1

8

R/W ADC Operating mode, Master Clock mode and Input Bias Current

Source mode

0x2

0x3

CONFIG1

CONFIG2

8

R/W Prescale and OSR settings

R/W ADC boost and gain settings, auto-zeroing settings for analog

multiplexer, voltage reference and ADC

0x4

0x5

CONFIG3

IRQ

8

R/W Conversion mode, data and CRC format settings; enable for CRC on

communications, enable for digital offset and gain error calibrations

R/W IRQ Status bits and IRQ mode settings; enable for Fast commands and

for conversion start pulse

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

MUX

SCAN

8

R/W Analog multiplexer input selection (MUX mode only)

24

8

R/W Scan mode settings

TIMER

R/W Delay value for TIMER between Scan cycles

OFFSETCAL

GAINCAL

RESERVED

LOCK

R/W ADC digital offset calibration value

R/W ADC digital gain calibration value

R/W

8

R/W Password value for SPI Write mode locking

R/W

RESERVED

CRCCFG

16

R

CRC checksum for device configuration

 2020-2021 Microchip Technology Inc.

DS20006404C-page 89

MCP3461/2/4R

8.1

ADCDATA REGISTER

Name

ADCDATA

Bits

Address

0x0

Cof

R

4/16/32

REGISTER 8-1:

ADCDATA: ADC CHANNEL DATA OUTPUT REGISTER

R-0

ADCDATA[15:0]

bit 15

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

ADCDATA[15:0]: ADC Output Code

The data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. The data can be

formatted in 16/32-bit modes depending on the DATA_FORMAT[1:0] bits setting (see Section 5.6

“ADC Output Data Format”).

The ADC Channel Data Output registers always contain the most recent A/D conversion data. The

register is updated at each data ready internal signal (it depends on the OSR and CONV_MODE

settings). The register is latched at the start of each SPI Read command. The register is double

buffered to avoid data loss. There is a small time delay, t_DODR, after each data ready, where the user

has to wait for the data to be available. Otherwise, data corruption can occur (when the internal data

are refreshed).

When IRQ_MODE[1:0] = 1x, this register becomes a 4-bit wide register containing the MDAT output

codes, which are the outputs of the modulator that are represented by four comparator outputs

(COMP[3:0], see Section 5.4.2 “Modulator Output Block”).

DS20006404C-page 90

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

8.2

CONFIG0 REGISTER

Name

CONFIG0

Bits

8

Address

0x1

Cof

R/W

REGISTER 8-2:

CONFIG0 REGISTER

R/W-1 R/W-0

CLK_SEL[1:0]

R/W-1

R/W-0

VREF_SEL CONFIG0[6]

bit 7

CS_SEL[1:0]

ADC_MODE[1:0]

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

VREF_SEL: Internal Voltage Reference

1= Internal voltage reference is selected and buffered internally; REFIN+/OUT pin voltage is set at

2.4V (default)

0= External voltage reference is selected and not buffered internally; the internal voltage reference

buffer is shut down

bit 6

CONFIG0[6]:

If CONFIG0 = 0x0, the device goes into Partial Shutdown mode. This bit does not have any other function.

bit 5-4

CLK_SEL[1:0]: Clock Selection

11= Internal clock is selected and AMCLK is present on the analog master clock output pin

10= Internal clock is selected and no clock output is present on the CLK pin

01= External digital clock

00= External digital clock (default)

bit 3-2

bit 1-0

CS_SEL[1:0]: Current Source/Sink Selection Bits for Sensor Bias (source on V_IN+/sink on V_IN-)

11= 15 µA is applied to the ADC inputs

10= 3.7 µA is applied to the ADC inputs

01= 0.9 µA is applied to the ADC inputs

00= No current source is applied to the ADC inputs (default)

ADC_MODE[1:0]: ADC Operating Mode Selection

11= ADC Conversion mode

10= ADC Standby mode

01= ADC Shutdown mode

00= ADC Shutdown mode (default)

 2020-2021 Microchip Technology Inc.

DS20006404C-page 91

MCP3461/2/4R

8.3

CONFIG1 REGISTER

Name

CONFIG1

Bits

8

Address

0x2

Cof

R/W

REGISTER 8-3:

CONFIG1: CONFIGURATION REGISTER 1

R/W-0

PRE[1:0]

bit 7

R/W-0

R/W-1

R/W-0

OSR[3:0]

RESERVED[1:0]

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-2

PRE[1:0]: Prescaler Value Selection for AMCLK

11= AMCLK = MCLK/8

10= AMCLK = MCLK/4

01= AMCLK = MCLK/2

00= AMCLK = MCLK (default)

OSR[3:0]: Oversampling Ratio for Delta-Sigma A/D Conversion

1111= OSR: 98304

1110= OSR: 81920

1101= OSR: 49152

1100= OSR: 40960

1011= OSR: 24576

1010= OSR: 20480

1001= OSR: 16384

1000= OSR: 8192

0111= OSR: 4096

0110= OSR: 2048

0101= OSR: 1024

0100= OSR: 512

0011= OSR: 256 (default)

0010= OSR: 128

0001= OSR: 64

0000= OSR: 32

bit 1-0

RESERVED[1:0]: Should always be set to ‘00’

DS20006404C-page 92

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

8.4

CONFIG2 REGISTER

Name

CONFIG2

Bits

8

Address

0x3

Cof

R/W

REGISTER 8-4:

CONFIG2: CONFIGURATION REGISTER 2

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

RESERVED

bit 0

BOOST[1:0]

GAIN[2:0]

AZ_MUX

AZ_REF

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-3

BOOST[1:0]: ADC Bias Current Selection

11= ADC channel has current x 2

10= ADC channel has current x 1 (default)

01= ADC channel has current x 0.66

00= ADC channel has current x 0.5

GAIN[2:0]: ADC Gain Selection

111= Gain is x64 (x16 analog, x4 digital)

110= Gain is x32 (x16 analog, x2 digital)

101= Gain is x16

100= Gain is x8

011= Gain is x4

010= Gain is x2

001= Gain is x1 (default)

000= Gain is x1/3

bit 2

AZ_MUX: Auto-Zeroing MUX Setting

1= ADC auto-zeroing algorithm is enabled; this setting multiplies the conversion time by two and

does not allow Continuous Conversion mode operation (which is then replaced by a series of

consecutive One-Shot mode conversions)

0= Analog input multiplexer auto-zeroing algorithm is disabled (default).

bit 1

bit 0

AZ_REF: Auto-Zeroing Reference Buffer Setting

1= Internal voltage reference buffer chopping algorithm is enabled; this setting has no effect when

external voltage reference is selected (VREF_SEL = 0) (default)

0= Internal voltage reference buffer chopping auto-zeroing algorithm is disabled

RESERVED: Should always be equal to ‘1’

 2020-2021 Microchip Technology Inc.

DS20006404C-page 93

MCP3461/2/4R

8.5

CONFIG3 REGISTER

Name

CONFIG3

Bits

8

Address

0x4

Cof

R/W

REGISTER 8-5:

CONFIG3: CONFIGURATION REGISTER 3

R/W-0 R/W-0 R/W-0 R/W-0

DATA_FORMAT[1:0] CRC_FORMAT EN_CRCCOM

R/W-0

CONV_MODE[1:0]

EN_OFFCAL EN_GAINCAL

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

CONV_MODE[1:0]: Conversion Mode Selection

11= Continuous Conversion mode or continuous conversion cycle in Scan mode

10= One-shot conversion or one-shot cycle in Scan mode; it sets ADC_MODE[1:0] to ‘10’ (standby) at

the end of the conversion or at the end of the conversion cycle in Scan mode

0x= One-shot conversion or one-shot cycle in Scan mode’ it sets ADC_MODE[1:0] to ‘0x’ (ADC

shutdown) at the end of the conversion or at the end of the conversion cycle in Scan mode (default)

DATA_FORMAT[1:0]: ADC Output Data Format Selection

11= 32-bit (17-bit right justified data + Channel ID): CHID[3:0] + SGN extension (12 bits) + 16-bit ADC

data; it allows overrange with the SGN extension

10= 32-bit (17-bit right justified data): SGN extension (8-bit) + 16-bit ADC data; it allows overrange with

the SGN extension

01= 32-bit (16-bit left justified data): 16-bit ADC data + 0x0000 (16 bit); it does not allow overrange (ADC

code locked to 0xFFFF or 0x8000)

00= 16-bit (default ADC coding): 16-bit ADC data; it does not allow overrange (ADC code locked to

0xFFFF or 0x8000)

bit 3

bit 2

CRC_FORMAT: CRC Checksum Format Selection on Read Communications

(it does not affect CRCCFG coding)

1= 32-bit wide (CRC-16 followed by 16 zeros)

0= 16-bit wide (CRC-16 only) (default)

EN_CRCCOM: CRC Checksum Selection on Read Communications

(it does not affect CRCCFG calculations)

1= CRC on communications enabled

0= CRC on communications disabled (default)

bit 1

bit 0

EN_OFFCAL: Enable Digital Offset Calibration

1= Enabled

0= Disabled (default)

EN_GAINCAL: Enable Digital Gain Calibration

1= Enabled

0= Disabled (default)

DS20006404C-page 94

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

8.6

IRQ REGISTER

Name

IRQ

Bits

8

Address

0x5

Cof

R/W

REGISTER 8-6:

IRQ: INTERRUPT REQUEST REGISTER

R-1 R-1 R/W-0

DR_STATUS CRCCFG_STATUS POR_STATUS IRQ_MODE[1:0]⁽¹⁾EN_FASTCMD

U-0

—

R-1

R/W-0

R/W-1

EN_STP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

DR_STATUS: Data Ready Status Flag

1= ADCDATA has not been updated since last reading or last Reset (default)

0= New ADCDATA ready for reading

bit 5

CRCCFG_STATUS: CRC Error Status Flag Bit for Internal Registers

1= CRC error has not occurred for the Configuration registers (default)

0= CRC error has occurred for the Configuration registers

bit 4

POR_STATUS: POR Status Flag

1= POR has not occurred since the last reading (default)

0= POR has occurred since the last reading

bit 3-2

IRQ_MODE[1:0]: Configuration for the IRQ/MDAT Pin⁽¹⁾

IRQ_MODE[1]: IRQ/MDAT Selection

1= MDAT output is selected. Only POR and CRC interrupts can be present on this pin and take priority

over the MDAT output

0= IRQ output is selected. All interrupts can appear on the IRQ/MDAT pin

IRQ_MODE[0]: IRQ Pin Inactive State Selection

1= The Inactive state is logic high (does not require a pull-up resistor to DV_DD

0= The Inactive state is High-Z (requires a pull-up resistor to DV_DD) (default)

)

bit 1

bit 0

EN_FASTCMD: Enable Fast Commands in the COMMAND Byte

1= Fast commands are enabled (default)

0= Fast commands are disabled

EN_STP: Enable Conversion Start Interrupt Output

1= Enabled (default)

0= Disabled

Note 1: When IRQ_MODE[1:0] = 10or 11, the modulator output codes (MDAT stream) are available at both the

MDAT pin and ADCDATA register (0x0).

 2020-2021 Microchip Technology Inc.

DS20006404C-page 95

MCP3461/2/4R

8.7

MULTIPLEXER (MUX) REGISTER

Name

MUX

Bits

8

Address

0x6

Cof

R/W

REGISTER 8-7:

MUX: MULTIPLEXER REGISTER

R/W-0 R/W-0 R/W-0

MUX_VIN+[3:0]^(2,3)

R/W-0

MUX_VIN-[3:0]^(2,3)

R/W-0

R/W-1

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Bit 7-4

MUX_VIN+[3:0]: Input Selection^(2,3)

1111= Internal V_CM

1110= Internal Temperature Sensor Diode M (Temp Diode M)⁽¹⁾

1101= Internal Temperature Sensor Diode P (Temp Diode P)⁽¹⁾

1100= REFIN-

1011= REFIN+/OUT

1010= Reserved (do not use)

1001= AV_DD

1000= A_GND

0111= CH7

0110= CH6

0101= CH5

0100= CH4

0011= CH3

0010= CH2

0001= CH1

0000= CH0 (default)

Bit 3-0

MUX_VIN-[3:0]: Input Selection^(2,3)

1111= Internal V_CM

1110= Internal Temperature Sensor Diode M (Temp Diode M)⁽¹⁾

1101= Internal Temperature Sensor Diode P (Temp Diode P)⁽¹⁾

1100= REFIN-

1011= REFIN+/OUT

1010= Reserved (do not use)

1001= AV_DD

1000= A_GND

0111= CH7

0110= CH6

0101= CH5

0100= CH4

0011= CH3

0010= CH2

0001= CH1 (default)

0000= CH0

Note 1: Selects the internal temperature sensor diode and forces a fixed current through it. For a correct

temperature reading, the MUX[7:0] selection should be equal to 0xDE.

2: For MCP3462R, the codes, ‘0111/0110/0101/0100’, correspond to a floating input and should be

avoided.

3: For MCP3461R, the codes, ‘0111/0110/0101/0100/0011/0010’, correspond to a floating input and

should be avoided.

DS20006404C-page 96

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

8.8

SCAN REGISTER

Name

SCAN

Bits

24

Address

0x7

Cof

R/W

REGISTER 8-8:

SCAN: SCAN MODE SETTINGS REGISTER

R/W-0

U-0

—

DLY[2:0]

RESERVED

bit 23

bit 16

R/W-0

OFFSET

bit 15

R/W-0

VCM

R/W-0

AV_DD

R/W-0

TEMP

R/W-0

bit 8

SCAN_DIFF_CH[D:A]

R/W-0

bit 7

R/W-0

bit 0

SCAN_SE_CH[7:0]

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

Bit 23-21

DLY[2:0]: Delay Time (T_{DLY_SCAN}) Between Each Conversion During a Scan Cycle

111= 512 * DMCLK

110= 256 * DMCLK

101= 128 * DMCLK

100= 64 * DMCLK

011= 32 * DMCLK

010= 16 * DMCLK

001= 8 * DMCLK

000= 0: No delay (default)

Bit 20

RESERVED: Should be set to ‘0’

Bit 19-16

Bit 15-0

Unimplemented: Read as ‘0’

SCAN Channel Selection (see Table 5-15 for a complete description)

 2020-2021 Microchip Technology Inc.

DS20006404C-page 97

MCP3461/2/4R

8.9

TIMER REGISTER

Name

TIMER

Bits

24

Address

0x8

Cof

R/W

REGISTER 8-9:

TIMER: TIMER DELAY VALUE REGISTER

R/W-0

TIMER[23:0]

bit 23

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Bit 23-0

TIMER[23:0]: Selection Bits for the Time Interval (T_{TIMER_SCAN}) Between Two Consecutive Scan Cycles

(when CONV_MODE[1:0] = 11)

0xFFFF: T_{TIMER_SCAN}= 16777215 * DMCLK periods

0xFFFFFE: T_{TIMER_SCAN}= 16777214 * DMCLK periods

•

0x000002: T_{TIMER_SCAN}= 2 * DMCLK periods

0x000001: T_{TIMER_SCAN}= 1 * DMCLK periods

0x000000: T_{TIMER_SCAN}= 0 (no delay) – default

DS20006404C-page 98

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

8.10 OFFSETCAL REGISTER

Name

Bits

24

Address

0x9

Cof

OFFSETCAL

R/W

REGISTER 8-10: OFFSETCAL: OFFSET CALIBRATION REGISTER

R/W-0

OFFSETCAL[23:16]

bit 23

bit 16

bit 8

bit 0

R/W-0

OFFSETCAL[15:8]

bit 15

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Bit 23-8

Bit 7-0

OFFSETCAL[23:8]: Offset Error Digital Calibration Code (two’s complement, MSb first coding)

See Section 5.13 “Digital System Offset and Gain Calibrations”.

Unimplemented[7:0]: 0x00

 2020-2021 Microchip Technology Inc.

DS20006404C-page 99

MCP3461/2/4R

8.11 GAINCAL REGISTER

Name

Bits

24

Address

0xA

Cof

GAINCAL

R/W

REGISTER 8-11: GAINCAL: GAIN CALIBRATION REGISTER

R/W-0

GAINCAL[23:16]

bit 23

bit 16

bit 8

bit 0

R/W-0

GAINCAL[15:8]

bit 15

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Bit 23-8

Bit 7-0

GAINCAL[23:8]: Gain Error Digital Calibration Code (unsigned, MSb first coding)

The GAINCAL default value is 800000, which provides a gain of 1x. See Section 5.13 “Digital

System Offset and Gain Calibrations”.

Unimplemented[7:0]: 0x00

DS20006404C-page 100

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

8.12 RESERVED REGISTER

Name

Bits

24

Address

0xB

Cof

RESERVED

R/W

REGISTER 8-12: RESERVED REGISTER

R/W-0x900000

RESERVED[23:0]

bit 23

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Bit 23-0

RESERVED[23:0]: Should be set to 0x900000

8.13 RESERVED REGISTER

Name

Bits

8

Address

0xC

Cof

RESERVED

R/W

REGISTER 8-13: RESERVED REGISTER

R/W-0x30

RESERVED[7:0]

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Bit 7-0

RESERVED[7:0]: Should be set to 0x30

 2020-2021 Microchip Technology Inc.

DS20006404C-page 101

MCP3461/2/4R

8.14 LOCK REGISTER

Name

LOCK

Bits

8

Address

0xD

Cof

R/W

REGISTER 8-14: LOCK: SPI WRITE MODE LOCKING PASSWORD VALUE REGISTER

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

bit 0

LOCK[7:0]

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Bit 7-0

LOCK[7:0]: Write Access Password Entry Code

0xA5 = Write access is allowed on the full register map. CRC on register map values is not calculated

(CRCCFG[15:0] = 0x0000) – default.

Any code, except 0xA5 = Write access, is not allowed on the full register map. Only the LOCK register

is writable. CRC on register map is calculated continuously only when DMCLK is running.

8.15 RESERVED REGISTER

Name

Bits

16

Address

0xE

Cof

RESERVED

R/W

REGISTER 8-15: RESERVED REGISTER

R/W (default depends on product denomination)

RESERVED[15:0]

bit 15

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Bit 15-0

RESERVED[15:0]: Should be set to

MCP3461R: 0x0008

MCP3462R: 0x0009

MCP3464R: 0x000B

DS20006404C-page 102

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

8.16 CRCCFG REGISTER

Name

Bits

16

Address

0xF

Cof

R

CRCCFG

REGISTER 8-16: CRCCFG: CRC CONFIGURATION REGISTER

R-0

CRCCFG[15:0]

bit 15

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Bit 15-0

CRCCFG[15:0]: CRC-16 Checksum Value

CRC-16 checksum is continuously calculated internally based on the register map configuration

settings when the device is locked (LOCK[7:0] ≠ 0xA5).

 2020-2021 Microchip Technology Inc.

DS20006404C-page 103

MCP3461/2/4R

NOTES:

DS20006404C-page 104

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

9.0

9.1

PACKAGING INFORMATION

(1)

Package Marking Information

20-Lead UQFN (3 x 3 x 0.55 mm)

Example

PIN 1

XXX

AAM

2112

256

YYWW

NNN

Part Number

Code

SPI Device Address

(2)

MCP3461RT-E/NC

MCP3462RT-E/NC

MCP3464RT-E/NC

AAM

AAN

AAP

01

(2)

01

(2)

01

20-Lead TSSOP (6.5 x 4.4 x 1 mm)⁽³⁾

Example

XXXXXXXX

XXXXXNNN

MCP464R

3

e

EST 256

YYWW

2112

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note 1: In the event the full Microchip part number cannot be marked on one line, it

will be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

2: Denotes the device default SPI address option. The device only responds to

SPI commands if CMD[7:6] matches the SPI device address for each com-

mand (see Section 6.2.2 “Device Address Bits (CMD[7:6])”). Contact

Microchip Sales for other device address option ordering procedure.

3: The 20-Lead TSSOP package allows up to 8 characters per line as shown

here. Currently only 7 characters are being used as shown in the example.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 105

MCP3461/2/4R

20-Lead Ultra Thin Plastic Quad Flat, No Lead Package ꢃ1&ꢄꢀ- 3x3 mm Body [UQFN]

(Formerly Q3DE; SST Legacy Package)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

NOTE 1

N

1

2

(DATUM B)

(DATUM A)

2X

0.075 C

2X

TOP VIEW

0.075 C

A1

0.10 C

C

A

SEATING

PLANE

20X

(A3)

SIDE VIEW

0.08 C

C A B

0.10

D2

See

Detail A

0.10

C A B

e

2

E2

2

1

NOTE 1

K

N

20X b

0.10

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing C04-264A Sheet 1 of 2

DS20006404C-page 106

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

20-Lead Ultra Thin Plastic Quad Flat, No Lead Packageꢀꢃ1&ꢄꢀ- 3x3 mm Body [UQFN]

(Formerly Q3DE; SST Legacy Package)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

(b)

b1

L

DETAIL A

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Terminals

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Length

Exposed Pad Length

Overall Width

Exposed Pad Width

Terminal Width (Inner)

Terminal Width (Outer)

Terminal Length

N

20

0.40 BSC

0.55

e

A

A1

A3

D

D2

E

E2

b

b1

L

0.50

0.00

0.60

0.05

0.02

0.15 REF

3.00 BSC

1.70

3.00 BSC

1.70

0.15 REF

0.20

0.40

1.60

1.80

0.15

0.35

0.20

0.25

0.45

-

Terminal-to-Exposed-Pad

K

-

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-264A Sheet 2 of 2

 2020-2021 Microchip Technology Inc.

DS20006404C-page 107

MCP3461/2/4R

20-Lead Ultra Thin Plastic Quad Flat, No Lead Packageꢀꢃ1&ꢄꢀ- 3x3 mm Body [UQFN]

(Formerly Q3DE; SST Legacy Package)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

X2

EV

20

ØV

Y1

1

2

C2 Y2

EV

G1

X1

E

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.40 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

X2

Y2

C1

C2

X1

Y1

G1

V

1.80

3.00

Contact Pad Spacing

Contact Pad Width (X20)

Contact Pad Length (X20)

Contact Pad to Center Pad (X20)

Thermal Via Diameter

0.20

0.80

0.20

0.30

1.00

Thermal Via Pitch

EV

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

Microchip Technology Drawing C04-2264A

DS20006404C-page 108

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

 2020-2021 Microchip Technology Inc.

DS20006404C-page 109

MCP3461/2/4R

DS20006404C-page 110

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2020-2021 Microchip Technology Inc.

DS20006404C-page 111

MCP3461/2/4R

NOTES:

DS20006404C-page 112

 2020-2021 Microchip Technology Inc.

MCP3461/2/4R

APPENDIX A: REVISION HISTORY

Revision C (April 2021)

• Updated size for 20-Lead TSSOP package

throughout the document

• Updated Features

• Updated Section 2.1, Noise Specifications

• Updated Equation 2-1 and Equation 2-2

• Updated Table 2-2 and Table 2-4

• Updated Section 9.0, Packaging Information

Revision B (December 2020)

The following is the list of modifications:

• Corrected Table 5-11

• Corrected Register 8-2

Note:

The SPI standard uses the terminology

“Master” and “Slave”. The equivalent

Microchip terminology used in this

document is “Host” and “Client”,

respectively.

Revision A (August 2020)

• Initial release of this document.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 113

MCP3461/2/4R

NOTES:

 2020-2021 Microchip Technology Inc.

DS20006404C-page 114

MCP3461/2/4R

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

(1)

PART NO.

Device

X

/XX

a) MCP3461RT-E/NC: Single Channel ADC,

Tape and Reel,

Tape and

Reel

Temperature

Range

Package

Extended Temperature,

20-Lead UQFN.

b) MCP3462RT-E/NC: Dual Channel ADC,

Tape and Reel,

Device:

MCP3461/2/4R: Two/Four/Eight Differential Channel,

16-bit Delta-Sigma ADCs with Internal

Voltage Reference.

Extended Temperature,

20-Lead UQFN.

c) MCP3464RT-E/NC: Quad Channel ADC,

Tape and Reel,

Tape and Reel:

T

= Tape and Reel

Extended Temperature,

20-Lead UQFN.

Blank = Standard packaging (tube or tray)

d) MCP3461RT-E/ST: Single Channel ADC,

Tape and Reel,

Temperature

Range:

E

= -40°C to +125°C (Extended)

Extended Temperature,

20-Lead TSSOP.

e) MCP3462R-E/ST: Dual Channel ADC,

Standard Packaging,

Package:

NC = Ultra Small, No Lead Package (UQFN),

3 x 3 x 0.55 mm, 20-Lead

Extended Temperature,

20-Lead TSSOP.

ST

= Plastic Thin Shrink Small Outline (TSSOP),

6.5 x 4.4 x 1 mm, 20-Lead

f) MCP3464R-E/ST: Quad Channel ADC,

Standard Packaging,

Extended Temperature,

20-Lead TSSOP.

Note 1: Tape and Reel identifier only appears in the

catalog part number description. This identi-

fier is used for ordering purposes and is not

printed on the device package. Check with

your Microchip Sales Office for package

availability with the Tape and Reel option.

2: Device SPI Address ‘01’ is the default

address option. Contact Microchip Sales for

other device address option ordering

procedure.

 2020-2021 Microchip Technology Inc.

DS20006404C-page 115

MCP3461/2/4R

NOTES:

DS20006404C-page 116

 2020-2021 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specifications contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip

devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications

contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished

without violating Microchip's intellectual property rights.

•

Microchip is willing to work with any customer who is concerned about the integrity of its code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not

mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are

committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection

feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or

other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication is provided for the sole

purpose of designing with and using Microchip products. Infor-

mation regarding device applications and the like is provided

only for your convenience and may be superseded by updates.

It is your responsibility to ensure that your application meets

with your specifications.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec,

AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,

chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,

flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,

LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,

Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,

PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,

Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,

SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered

trademarks of Microchip Technology Incorporated in the U.S.A. and

other countries.

THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS".

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION INCLUDING BUT NOT

LIMITED TO ANY IMPLIED WARRANTIES OF NON-

INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A

PARTICULAR PURPOSE OR WARRANTIES RELATED TO

ITS CONDITION, QUALITY, OR PERFORMANCE.

AgileSwitch, APT, ClockWorks, The Embedded Control Solutions

Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight

Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,

Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-

Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,

TimePictra, TimeProvider, WinPath, and ZL are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI-

RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN-

TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND

WHATSOEVER RELATED TO THE INFORMATION OR ITS

USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS

BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES

ARE FORESEEABLE. TO THE FULLEST EXTENT

ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON

ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION

OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF

ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP

FOR THE INFORMATION. Use of Microchip devices in life sup-

port and/or safety applications is entirely at the buyer's risk, and

the buyer agrees to defend, indemnify and hold harmless

Microchip from any and all damages, claims, suits, or expenses

resulting from such use. No licenses are conveyed, implicitly or

otherwise, under any Microchip intellectual property rights

unless otherwise stated.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky,

BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive,

CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,

Dynamic Average Matching, DAM, ECAN, Espresso T1S,

EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP,

INICnet, Intelligent Paralleling, Inter-Chip Connectivity,

JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi,

MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,

NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,

PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,

Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O,

simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI,

SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total

Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,

ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks

of Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage

Technology, and Symmcom are registered trademarks of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany

II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their

respective companies.

Reserved.

For information regarding Microchip’s Quality Management Systems,

please visit www.microchip.com/quality.

ISBN: 978-1-5224-7999-4

 2020-2021 Microchip Technology Inc.

DS20006404C-page 117

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

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Poland - Warsaw

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Fax: 949-462-9608

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Raleigh, NC

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Tel: 905-695-1980

Fax: 905-695-2078

DS20006404C-page 118

 2020-2021 Microchip Technology Inc.

02/28/20


型号：	MCP3464R-E/ST
厂家：	MICROCHIP
描述：	Two/Four/Eight-Channel, 153.6 ksps, Low-Noise, 16-Bit Delta-Sigma ADCs with Internal Voltage Reference
文件：	总118页 (文件大小：2859K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP3464R-E/ST [MICROCHIP]

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