MCP3901_技术文档

MCP3901

Two-Channel Analog Front End

Features

Description

The MCP3901 is a dual channel Analog Front End

(AFE) containing two synchronous sampling Delta-

Sigma Analog-to-Digital Converters (ADC), two PGAs,

phase delay compensation block internal voltage

reference, modulator output block, and high-speed

20 MHz SPI compatible serial interface. The converters

contain a proprietary dithering algorithm for reduced

Idle tones and improved THD.

• Two Synchronous Sampling 16/24-bit Resolution

Delta-Sigma A/D Converters with Proprietary

Multi-Bit Architecture

• 91 dB SINAD, -104 dBc Total Harmonic Distortion

(THD) (up to 35^thharmonic), 109 dB Spurious-free

Dynamic Range (SFDR) for Each Channel

• Programmable Data Rate up to 64 ksps

• Ultra Low-Power Shutdown mode with <2 µA

• -133 dB Crosstalk Between the Two Channels

• Low Drift Internal Voltage Reference: 12 ppm/°C

• Differential Voltage Reference Input Pins

• High Gain PGA on Each Channel (up to 32 V/V)

The internal register map contains 24-bit wide ADC

data words, a modulator output byte, as well as six

writable control registers to program gain,

oversampling ratio, phase, resolution, dithering,

shutdown, Reset and several communication features.

The communication is largely simplified with various

Continuous Read modes that can be accessed by the

Direct Memory Access (DMA) of an MCU and with a

separate data ready pin that can be connected directly

to an Interrupt Request (IRQ) input of an MCU.

• Phase Delay Compensation Between the Two

Channels with 1 µs time Resolution

• Separate Modulator Outputs for Each Channel

• High-Speed, Addressable 20 MHz SPI Interface

with Mode 0,0 and 1,1 Compatibility

The MCP3901 is capable of interfacing to a large

variety of voltage and current sensors, including

shunts, current transformers, Rogowski coils and Hall-

effect sensors.

• Independent Analog and Digital Power Supplies:

4.5V-5.5V AV_DD, 2.7V-5.5V DV_DD

• Low-Power Consumption: (14 mW typical at 5V)

• Available in Small 20-lead SSOP and QFN

Packages

Package Type

20-Lead

SSOP

• Industrial Temperature Ranges:

RESET

SDI

1

2

3

4

5

6

7

8

20

19

18

17

16

DV_DD

AV_DD

CH0+

CH0-

CH1-

CH1+

AGND

SDO

SCK

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

CS

OSC2

OSC1/CLKI

Applications

15

14

13

DR

• Energy Metering and Power Measurement

• Automotive

MDAT0

MDAT1

REFIN/OUT+

9

12

11

REFIN- 10

DGND

• Portable Instrumentation

• Medical and Power Monitoring

20-Lead QFN

20 19 18 17 16

CH0+

SCK

1

15

14

13

CH0-

CH1-

CH1+

2

3

4

5

CS

EP

21

OSC2

12 OSC1/CLKI

11 DR

AGND

10

9

6

7

8

* Includes Exposed Thermal Pad (EP); see Table 3-1.

DS22192D-page 1

MCP3901

Functional Block Diagram

AV_DD

DV_DD

REFIN/OUT+

Xtal Oscillator

MCLK

Voltage

Reference

+

VREFEXT

AMCLK

OSC1

OSC2

Clock

Generation

V_REF

DMCLK/DRCLK

-

REFIN -

ANALOG DIGITAL

V_REF- V_REF+

OSR<1:0>

PRE<1:0>

DMCLK

SINC³

DATA_CH0<23:0>

CH0+

CH0-

+

-

PGA

DR

SDO

Δ -Σ

Modulator

Phase

Shifter

PHASE <7:0>

Digital SPI

Interface

Φ

RESET

SDI

DATA_CH1<23:0>

CH1+

CH1-

+

-

PGA

SCK

CS

SINC³

Δ -Σ

Modulator

MODOUT<1:0>

DUAL DS ADC

SDN<1:0>, RESET<1:0>, GAIN<7:0>

POR

Modulator

Output Block

MOD<7:0>

POR

MDAT0

MDAT1

AV_DD

Monitoring

AGND

DGND

DS22192D-page 2

MCP3901

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at those or any other conditions, above those indi-

cated in the operational listings of this specification, is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V_DD...................................................................................7.0V

Digital inputs and outputs w.r.t. A

........ -0.6V to V_DD+0.6V

GND

Analog input w.r.t. A

.........................................-6V to +6V

GND

V

input w.r.t. A

............................... -0.6V to V_DD+0.6V

REF

GND

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................-65°C to +125°C

Soldering temperature of leads (10 seconds).............+300°C

ESD on the analog inputs (HBM,MM).................7.0 kV, 400V

ESD on all other pins (HBM,MM)........................7.0 kV, 400V

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, AV_DD= 4.5 to 5.5V, DV_DD= 2.7 to 5.5V; -40°C < T_A< +85°C,

MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V_IN= -0.5dBFS = 333 mV_RMS@ 50/60 Hz

Parameters

Symbol

Min

Typical

Max

Units

Conditions

Internal Voltage Reference

Tolerance

V_REF

-2%

2.37

+2%

V

VREFEXT = 0

Temperature Coefficient

Output Impedance

TC_REF

—

12

7

—

ppm/°C VREFEXT = 0

ZOUT_REF

kΩ

AV_DD= 5V,

VREFEXT = 0

Voltage Reference Input

Input Capacitance

—

10

pF

V

Differential Input Voltage Range

V_REF

2.2

2.6

V_REF= (V_REF+– V_REF-),

(V_REF+– V_REF-

)

VREFEXT = 1

Absolute Voltage on REFIN+ Pin

Absolute Voltage on REFIN- Pin

ADC Performance

V_REF+

V_REF-

1.9

—

2.9

0.3

V

VREFEXT = 1

-0.3

Resolution (No Missing Codes)

24

—

bits

OSR = 256

(See Table 5-3)

Sampling Frequency

f_S

See Table 4-2

kHz

f_S= DMCLK = MCLK/

(4 x PRESCALE)

Note 1: This specification implies that the ADC output is valid over this entire differential range and that there is no

distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the

maximum signal range, V_IN= -0.5 dBFS @ 50/60 Hz = 353 mV_RMS,V_REF= 2.4V.

2: See terminology section for definition.

3: This parameter is established by characterization and not 100% tested.

4: For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00,

VREFEXT = 0, CLKEXT = 0.

5: For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11,

VREFEXT = 1, CLKEXT = 1.

6: Applies to all gains. Offset error is dependant on PGA gain setting (see Figure 2-19 for typical values).

7: Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied

continuously to the part with no risk for damage.

8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with

BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz,

AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to ‘0’.

DS22192D-page 3

MCP3901

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, AV_DD= 4.5 to 5.5V, DV_DD= 2.7 to 5.5V; -40°C < T_A< +85°C,

MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V_IN= -0.5dBFS = 333 mV_RMS@ 50/60 Hz

Parameters

Output Data Rate

Symbol

Min

Typical

Max

Units

Conditions

f_D

See Table 4-2

ksps

f_D= DRCLK = DMCLK/

OSR = MCLK/

(4 x PRESCALE x OSR)

Analog Input Absolute Voltage

on CH0+, CH0-, CH1+,

CH1- Pins

CHn+

A_IN

-1

—

+1

V

All analog input

channels, measured to

AGND (Note 7)

Analog Input Leakage Current

—

-3

1

2

—

nA

(Note 4)

-40°C < T_A< 125°C

(Note 1)

Differential Input Voltage Range (CHn+ – CHn-)

—

3

500/GAIN

mV

Offset Error (Note 2)

Offset Error Drift

V_OS

+3

—

(Note 6)

—

-2.5

—

µV/°C From -40°C to +125°C

Gain Error (Note 2)

GE

-0.4

—

1

—

%

G = 1

+2.5

—

All Gains

Gain Error Drift

ppm/°C From -40°C to +125°C

Integral Nonlinearity (Note 2)

INL

Z_IN

15

—

ppm

GAIN = 1,

DITHER = On

Input Impedance

350

89

—

kΩ

Proportional to

1/AMCLK

Signal-to-Noise and Distortion

SINAD

91

dB

OSR = 256,

Ratio (Notes 2, 3)

DITHER = On

78

—

79

—

dB

Total Harmonic Distortion

(Notes 2, 3)

THD

SNR

-104

-102

OSR = 256,

DITHER = On

—

89

-85

91

-84

—

dB

Signal-to-Noise Ratio

OSR = 256,

(Notes 2, 3)

DITHER = On

80

—

81

—

dB

Spurious Free Dynamic Range

(Note 2)

SFDR

CTALK

109

OSR = 256,

DITHER = On

—

87

—

dB

Crosstalk (50/60 Hz) (Note 2)

-133

OSR = 256,

DITHER = On

Note 1: This specification implies that the ADC output is valid over this entire differential range and that there is no

distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the

maximum signal range, V_IN= -0.5 dBFS @ 50/60 Hz = 353 mV_RMS,V_REF= 2.4V.

2: See terminology section for definition.

3: This parameter is established by characterization and not 100% tested.

4: For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00,

VREFEXT = 0, CLKEXT = 0.

5: For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11,

VREFEXT = 1, CLKEXT = 1.

6: Applies to all gains. Offset error is dependant on PGA gain setting (see Figure 2-19 for typical values).

7: Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied

continuously to the part with no risk for damage.

8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with

BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz,

AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to ‘0’.

DS22192D-page 4

MCP3901

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, AV_DD= 4.5 to 5.5V, DV_DD= 2.7 to 5.5V; -40°C < T_A< +85°C,

MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; V_IN= -0.5dBFS = 333 mV_RMS@ 50/60 Hz

Parameters

Symbol

Min

Typical

Max

Units

Conditions

AC Power Supply Rejection

AC PSRR

—

-77

—

dB

AV_DDand DV_DD= 5V +

1 V_PP@ 50/60 Hz

DC Power Supply Rejection

DC PSRR

CMRR

—

-77

-72

—

dB

AV_DDand DV_DD= 4.5 to

5.5V

DC Common-Mode Rejection

Ratio (Note 2)

V_CMvaries from -1V to

+1V

Oscillator Input

Master Clock Frequency Range

Power Specifications

MCLK

1

—

16.384

MHz

(Note 8)

Operating Voltage, Analog

Operating Voltage, Digital

Power On Reset Threshold

AV_DD

DV_DD

POR

4.5

2.7

—

5.5

—

V

3.6

4.2

4.6

(Note 3)

—

-40°C < T_A< 125°C,

(Note 3)

Operating Current, Analog

(Note 4)

AI_DD

—

2.1

2.8

3.3

mA

BOOST<1:0> = 00

-40°C < T_A< 125°C,

BOOST<1:0> = 00

—

3.8

5.6

7

mA

BOOST<1:0> = 11

-40°C < T_A< 125°C,

BOOST<1:0> = 11

Operating Current, Digital

DI_DD

—

0.45

0.25

1.2

1.0

0.45

1.6

mA

DV_DD= 5V,

MCLK = 4 MHz

DV_DD= 2.7V,

MCLK = 4 MHz

DV_DD= 5V,

MCLK = 8.192 MHz

Shutdown Current, Analog

Shutdown Current, Digital

I_DDS,A

I_DDS,D

—

1

µA

AV_DDpin only (Note 5)

DV_DDpin only (Note 5)

Note 1: This specification implies that the ADC output is valid over this entire differential range and that there is no

distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the

maximum signal range, V_IN= -0.5 dBFS @ 50/60 Hz = 353 mV_RMS,V_REF= 2.4V.

2: See terminology section for definition.

3: This parameter is established by characterization and not 100% tested.

4: For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00,

VREFEXT = 0, CLKEXT = 0.

5: For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11,

VREFEXT = 1, CLKEXT = 1.

6: Applies to all gains. Offset error is dependant on PGA gain setting (see Figure 2-19 for typical values).

7: Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied

continuously to the part with no risk for damage.

8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with

BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz,

AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to ‘0’.

DS22192D-page 5

MCP3901

SERIAL INTERFACE SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, all parameters apply: AV = 4.5 to 5.5V, DV = 2.7 to 5.5V,

DD

-40°C < T < +85°C, C

= 30 pF

LOAD

A

Parameters

Serial Clock Frequency

Sym

Min

Typ

Max

Units

Conditions

f

—

20

10

MHz 4.5 ≤ DV ≤ 5.5

MHz 2.7 ≤ DV < 5.5

SCK

DD

CS Setup Time

CS Hold Time

t

25

50

—

ns

4.5 ≤ DV ≤ 5.5

CSS

DD

2.7 ≤ DV ≤ 5.5

DD

t

50

100

—

ns

4.5 ≤ DV ≤ 5.5

CSH

DD

2.7 ≤ DV < 5.5

DD

CS Disable Time

Data Setup Time

t

50

—

ns

CSD

t

5

10

—

ns

4.5 ≤ DV ≤ 5.5

SU

DD

2.7 ≤ DV < 5.5

DD

Data Hold Time

t_HD

t_HI

10

20

—

ns

4.5 ≤ DV ≤ 5.5

DD

2.7 ≤ DV < 5.5

DD

Serial Clock High Time

Serial Clock Low Time

20

50

—

ns

4.5 ≤ DV ≤ 5.5

DD

2.7 ≤ DV < 5.5

DD

t_LO

20

50

—

ns

4.5 ≤ DV ≤ 5.5

DD

2.7 ≤ DV < 5.5

DD

Serial Clock Delay Time

Serial Clock Enable Time

Output Valid from SCK Low

t_CLD

t_CLE

50

—

ns

s

—

50

t_DO

2.7 ≤ DV < 5.5

DD

Modulator Output Valid from AMCLK

High

t_DOMDAT

1/2 * AMCLK

Output Hold Time

t_HO

t_DIS

0

—

ns

(Note 1)

Output Disable Time

—

25

50

ns

4.5 ≤ DV ≤ 5.5

2.7 ≤ DV < 5.5 (Note 1)

DD

Reset Pulse Width (RESET)

t

100

—

50

—

ns

µs

V

2.7 ≤ DV < 5.5

MCLR

DD

Data Transfer Time to DR (data ready)

Data Ready Pulse Low Time

t

—

2.7 ≤ DV < 5.5

DODR

DD

t

—

1/DMCLK

2.7 ≤ DV < 5.5

DRP

DD

Schmitt Trigger High-Level Input Voltage

Schmitt Trigger Low-Level Input Voltage

V

.7 DV

—

DV + 1

DD

IH1

DD

V

-0.3

300

0.2 DV

—

V

IL1

DD

Hysteresis of Schmitt Trigger Inputs

(all digital inputs)

V

mV

HYS

Low-Level Output Voltage, SDO Pin

V

—

0.4

—

V

SDO pin only,

OL

I

= +2.0 mA, V = 5.0V

DD

OL

Low-level output voltage, DR and

MDAT Pins

V

DR and MDAT pins only,

= +800 mA, V = 5.0V

OL

I

OL

DD

High-level output voltage, SDO pin

V

DV – 0.5

V

SDO pin only,

= -2.0 mA, V = 5.0V

OH

DD

I

OH

DD

High-level output voltage, DR and

MDAT pins

DV – 0.5

—

V

DR and MDAT pins only,

= -800 µA, V = 5.0V

OH

DD

I

OH

DD

Input leakage current

I

—

±1

µA

CS = DV

,

DD

LI

V

= DGND or DV

DD

IN

Output leakage current

I

—

±1

7

µA

pF

CS = DV

,

DD

LO

V

= DGND or DV

OUT

DD

Internal capacitance (all inputs and

outputs)

C

T = 25°C,

INT

A

SCK = 1.0 MHz,

DV = 5.0V (Note 1)

DD

Note 1: This parameter is periodically sampled and not 100% tested.

DS22192D-page 6

MCP3901

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV_DD= 4.5 to 5.5V,

DV_DD= 2.7 to 5.5V

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 20L SSOP

Thermal Resistance, 20L QFN

T_A

-40

-65

—

+125

+150

°C

(Note 1)

θ_JA

—

89.3

43

—

°C/W

Note 1: The internal junction temperature (T_J) must not exceed the absolute maximum specification of +150°C.

CS

f_SCK

t_CSH

t_HI

t_LO

Mode 1,1

Mode 0,0

SCK

t_DO

t_DIS

t_HO

MSB Out

LSB Out

SDO

Don’t Care

SDI

FIGURE 1-1:

Serial Output Timing Diagram.

t

CSD

CS

t_CLE

t_CLD

f

t_CSS

SCK

t_CSH

t_HI

t_LO

Mode 1,1

Mode 0,0

SCK

t_HD

t_SU

SDI

MSB In

LSB In

HI-Z

SDO

FIGURE 1-2:

Serial Input Timing Diagram.

DS22192D-page 7

MCP3901

1/DRCLK

DR

t

DRP

t

DODR

SCK

SDO

FIGURE 1-3:

Data Ready Pulse Timing Diagram.

H

Timing Waveform for t_DIS

Timing Waveform for t_DO

V

SCK

SDO

IH

CS

t_DO

90%

t_DIS

HI-Z

SDO

10%

Timing Waveform for MDAT0/1

Modulator Output

OSC1/CLKI

t_DOMDAT

MDAT0/1

FIGURE 1-4:

Specific Timing Diagrams.

CLKEXT

PRESCALE<1:0>

OSR<1:0>

Digital Buffer

f_DADC

Output

Data Rate

f_SADC

Sampling

Rate

1

1/

1/4

1/OSR

1/Prescale

OSC1

OSC2

DMCLK

DRCLK

AMCLK

MCLK

0

Multiplexer

Clock Divider

Crystal

Oscillator

FIGURE 1-5:

MCP3901 Clock Detail.

DS22192D-page 8

MCP3901

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

Note:

Unless otherwise indicated, AV_DD= 5.0V, DV_DD= 5.0V; T_A= +25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 64; GAIN = 1; Dithering OFF; V_IN= -0.5 dBFS @ 60 Hz.

0

-20

-40

-60

-80

0

-20

-40

-60

-80

f_IN= -60dBFS @ 60 Hz

f_D= 3.9 ksps

16384 Point FFT

OSR = 256

f_IN= -0.5dBFS @ 60 Hz

_D= 3.9 ksps

16384 Point FFT

OSR = 256

f

Dithering OFF

Dithering ON

-100

-120

-140

-160

-180

-200

-100

-120

-140

-160

-180

-200

0

500

1000

1500

2000

0

500

1000

1500

2000

Frequency (Hz)

FIGURE 2-1:

Spectral Response.

FIGURE 2-4:

Spectral Response.

0

-20

-40

-60

-80

0

-20

f_IN= -0.5dBFS @ 60 Hz

f_IN= -60dBFS @ 60 Hz

_D= 3.9 ksps

16384 Point FFT

OSR = 256

f_D= 15.6 ksps

16384 Point FFT

OSR = 64

f

-40

-60

Dithering OFF

Dithering ON

-80

-100

-120

-140

-160

-180

-200

0

-100

-120

-140

-160

-180

0

2000

4000

6000

8000

1000

1500

2000

Frequency (Hz)

FIGURE 2-2:

Spectral Response.

FIGURE 2-5:

Spectral Response.

0

-20

-40

-60

-80

0

-20

f_IN= -0.5dBFS @ 60 Hz

f_IN= -60dBFS @ 60 Hz

f_D= 3.9 ksps

OSR = 256

16384 points

Dithering OFF

f_D= 15.6 ksps

16384 Point FFT

OSR = 64

-40

-60

Dithering OFF

-100

-120

-140

-160

-180

-200

0

-80

-100

-120

-140

-160

0

1000

1500

2000

4000

6000

8000

Frequency (Hz)

FIGURE 2-3:

Spectral Response.

FIGURE 2-6:

Spectral Response.

DS22192D-page 9

MCP3901

Note:

Unless otherwise indicated, AV_DD= 5.0V, DV_DD= 5.0V; T_A= +25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 64; GAIN = 1; Dithering OFF; V_IN= -0.5 dBFS @ 60 Hz.

0

120

110

Dithering ON

Dithering OFF

f_IN= -0.5dBFS @ 60 Hz

-20

-40

f_D= 15.6 ksps

100

90

80

70

60

50

40

30

20

10

0

16384 Point FFT

OSR = 64

Dithering ON

-60

-80

-100

-120

-140

-160

-180

32

64

128

256

0

2000

4000

6000

8000

Oversampling Ratio (OSR)

Frequency (Hz)

FIGURE 2-7:

Spectral Response.

FIGURE 2-10:

Spurious Free Dynamic

Range vs. Oversampling Ratio.

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

0

100

95

90

85

80

75

70

65

60

55

50

16

15

14

13

12

11

10

9

f_IN= -60dBFS @ 60 Hz

f_D= 15.6 ksps

16384 Point FFT

OSR = 64

Dithering ON

Dithering OFF

Dithering ON

8

32

64

128

256

2000

4000

6000

8000

Oversampling Ratio (OSR)

Frequency (Hz)

FIGURE 2-8:

Spectral Response.

FIGURE 2-11:

Signal-to-Noise and

Distortion and Effective Number of Bits vs.

Oversampling Ratio.

12

10

8

6

4

95

90

85

80

75

70

65

f_IN= 60 Hz

MCLK = 4 MHz

OSR = 256

OSR = 256 (Dithering ON)

OSR = 128 (Dithering ON)

Dithering On

OSR = 32

60

55

50

45

40

OSR = 64

2

0

107 107.5 108 108.5 109 109.5 110 110.5 111

Spurious Free Dynamic Range (dB)

1

2

4

8

16

32

Gain (V/V)

FIGURE 2-9:

Range Histogram.

Spurious Free Dynamic

FIGURE 2-12:

Distortion vs. Gain.

Signal-to-Noise and

DS22192D-page 10

MCP3901

Note:

Unless otherwise indicated, AV_DD= 5.0V, DV_DD= 5.0V; T_A= +25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 64; GAIN = 1; Dithering OFF; V_IN= -0.5 dBFS @ 60 Hz.

95

90

85

80

75

70

65

60

55

50

45

40

14

f_IN= 60 Hz

MCLK = 4 MHz

OSR = 256

Dithering On

OSR = 256

OSR = 128

12

10

8

OSR = 64

6

OSR = 32

4

2

0

1

2

4

8

16

32

-105.0 -104.5 -104.0 -103.5 -103.0 -102.5 -102.0

Total Harmonic Distortion (dBc)

Gain (V/V)

FIGURE 2-13:

Signal-to-Noise and

FIGURE 2-16:

Total Harmonic Distortion

Distortion vs. Gain (Dithering On).

Histogram (Dithering On).

0

-20

0

-20

-40

-60

-40

-60

Dithering OFF

-80

-100

-120

-100

Dithering ON

-120

-50 -25

0

25

50

75 100 125 150

32

64

128

256

Temperature (ºC)

Oversampling Ratio (OSR)

FIGURE 2-14:

Total Harmonic Distortion

FIGURE 2-17:

Total Harmonic Distortion

vs. Oversampling Ratio.

vs. Temperature.

100

90

80

70

60

50

40

30

20

10

0

f_D= 15.625 ksps

80

f_D= 15.625 ksps

60

40

20

0

-20

-40

-60

-80

SINC filter notch at 15.625 Hz

1000 10000

SINC filter notch at 15.625 Hz

10

100

10

100

1000

10000

Input Signal Frequency (Hz)

FIGURE 2-15:

Total Harmonic Distortion

FIGURE 2-18:

Signal-to-Noise and

vs. Input Signal Frequency.

Distortion vs. Input Frequency.

DS22192D-page 11

MCP3901

Note:

Unless otherwise indicated, AV_DD= 5.0V, DV_DD= 5.0V; T_A= +25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 64; GAIN = 1; Dithering OFF; V_IN= -0.5 dBFS @ 60 Hz.

1

2

0

8

6

4

0.6

0.5

0.4

0.3

0.2

0.1

0

f_IN= 60 Hz

MCLK = 4 MHz

OSR = 64

G=8

1

Dithering OFF

G=16

G=2

G=1

G=32

2

-0.1

-0.2

-0.3

G=4

0

78.9 79 79.1 79.2 79.3 79.4 79.5 79.6 79.7 79.8

SINAD (dB)

-50

-25

0

25

50

75

100 125 150

Temperature (ºC)

FIGURE 2-19:

Signal-to-Noise and

FIGURE 2-22:

Channel 0 Offset vs.

Distortion Histogram.

Temperature.

100

90

80

70

60

50

40

30

20

10

0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

G=8

G=1

G=16

G=32

25

G=2

G=4

-50 -25

0

25

50

75 100 125 150

0

50

75 100 125 150

Temperature (ºC)

Temperature (°C)

FIGURE 2-20:

Signal-to-Noise and

FIGURE 2-23:

Channel 1 Offset vs.

Distortion vs. Temperature.

Temperature.

100

80

60

40

20

0

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

Channel 0

-20

-40

Channel 1

0.05

0

-

80

0

20

40

60

-50 -25

0

25

50

75 100 125 150

Input Amplitude (dBFS)

Temperature (°C)

FIGURE 2-21:

Signal-to-Noise and

FIGURE 2-24:

Channel-to-Channel Offset

Distortion vs. Input Signal Amplitude.

Match vs. Temperature.

DS22192D-page 12

MCP3901

Note:

Unless otherwise indicated, AV_DD= 5.0V, DV_DD= 5.0V; T_A= +25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 64; GAIN = 1; Dithering OFF; V_IN= -0.5 dBFS @ 60 Hz.

0

2.37165

-0.2

-0.4

-0.6

-0.8

-1

-1.2

-1.4

-1.6

-1.8

-2

2.3716

G=1

G=2

G=8

2.37155

2.3715

2.37145

2.3714

G=16

G=4

G=32

2.37135

2.3713

-50 -25

0

25

50

75 100 125 150

4.5

4.8

5.0

5.3

5.5

Temperature (°C)

Power Supply (V)

FIGURE 2-25:

Positive Gain Error vs.

FIGURE 2-28:

Internal Voltage Reference

Temperature.

vs. Supply Voltage.

0

-0.2

-0.4

-0.6

-0.8

-1

-1.2

-1.4

-1.6

-1.8

-2

100

90

80

70

60

50

40

30

20

10

0

G=1

G=2

G=8

G=16

G=4

G=32

-50 -25

0

25

50

75 100 125 150

3

5

7

9

11

Temperature (°C)

MCLK Frequency (MHz)

FIGURE 2-26:

Negative Gain Error vs.

FIGURE 2-29:

Signal-to-Noise and

Temperature

Distortion vs. Master Clock (MCLK), BOOST ON.

2.4

2.39

2.38

2.37

2.36

8000

Channel 0

7000

6000

5000

4000

3000

2000

1000

0

V_IN= 0V

_A= +25°C

T

16384 Consecutive

Readings

24-bit Mode

2.35

-3000 -2000 -1000

0

1000 2000 3000

-50 -25

0

25

50

75 100 125 150

Output Code (LSB)

Temperature (°C)

FIGURE 2-27:

Internal Voltage Reference

FIGURE 2-30:

Noise Histogram.

vs. Temperature.

DS22192D-page 13

MCP3901

Note:

Unless otherwise indicated, AV_DD= 5.0V, DV_DD= 5.0 V; T_A= 25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 64; GAIN = 1; Dithering OFF; V_IN= -0.5 dBFS @ 60 Hz.

100

80

60

2.5

2

OSR = 256

Dithering OFF

SCK = 8 MHz

AI_DDBOOST OFF

40

20

0

1.5

1

Channel 0

Channel 1

-20

-40

-60

-80

-100

DI_DD

0.5

0

-0.5

-0.25

0

0.25

0.5

0

1

2

3

4

5

6

Input Voltage (V)

MCLK (MHz)

FIGURE 2-31:

Integral Nonlinearity

FIGURE 2-33:

Operating Current vs.

(Dithering Off).

Master Clock (MCLK).

50

40

OSR = 256

Dithering ON

SCK = 8 MHz

30

20

Channel 0

10

0

Channel 1

-10

-20

-30

-40

-50

-0.5

-0.25

0

0.25

0.5

Input Voltage (V)

FIGURE 2-32:

Integral Nonlinearity

(Dithering On).

DS22192D-page 14

MCP3901

3.0

PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

Symbol

PIN FUNCTION TABLE

Pin No.

Function

SSOP

QFN

RESET

DV_DD

AV_DD

1

2

18

19

20

1

Master Reset Logic Input Pin

Digital Power Supply Pin

Analog Power Supply Pin

3

CH0+

CH0-

4

Non-Inverting Analog Input Pin for Channel 0

Inverting Analog Input Pin for Channel 0

Inverting Analog Input Pin for Channel 1

Non-Inverting Analog Input Pin for Channel 1

5

2

CH1-

6

3

CH1+

A_GND

7

4

8

5

Analog Ground Pin, Return Path for Internal Analog Circuitry

Non-Inverting Voltage Reference Input and Internal Reference Output Pin

Inverting Voltage Reference Input Pin

REFIN+/OUT

REFIN-

D_GND

9

6

10

11

12

13

14

15

16

17

18

19

20

—

7

8

Digital Ground Pin, Return Path for Internal Digital Circuitry

Modulator Data Output Pin for Channel 1

Modulator Data Output Pin for Channel 0

Data Ready Signal Output Pin

MDAT1

MDAT0

DR

9

10

11

12

13

14

15

16

17

21

OSC1/CLKI

OSC2

CS

Oscillator Crystal Connection Pin or External Clock Input Pin

Oscillator Crystal Connection Pin

Serial Interface Chip Select Pin

SCK

Serial Interface Clock Pin

SDO

Serial Interface Data Output Pin

SDI

Serial Interface Data Input Pin

EP

Exposed Thermal Pad. Must be connected to AGND.

3.1

RESET

3.2

Digital V (DV

)

DD

This pin is active low and places the entire chip in a

Reset state when active.

DV_DDis the power supply pin for the digital circuitry

within the MCP3901. This pin requires appropriate

bypass capacitors and should be maintained between

2.7V and 5.5V for specified operation.

When RESET = 0, all registers are reset to their default

value, no communication can take place and no clock

is distributed inside the part. This state is equivalent to

a POR state.

3.3

Analog V (AV

)

DD

Since the default state of the ADCs is on, the analog

power consumption when RESET = 0is equivalent to

when RESET = 1. Only the digital power consumption

is largely reduced because this current consumption is

essentially dynamic and is reduced drastically when

there is no clock running.

AV_DDis the power supply pin for the analog circuitry

within the MCP3901.

This pin requires appropriate bypass capacitors and

should be maintained to 5V ±10% for specified

operation.

All the analog biases are enabled during a Reset so

that the part is fully operational just after a RESET

rising edge.

This input is Schmitt triggered.

DS22192D-page 15

MCP3901

3.4

ADC Differential Analog inputs

(CHn+/CHn-)

3.7

Inverting Reference Input (REFIN-)

This pin is the inverting side of the differential voltage

reference input for both ADCs. When using an external

differential voltage reference, it should be connected to

its V_REF-pin. When using an external, single-ended

voltage reference, or when VREFEXT = 0(default) and

using the internal voltage reference, this pin should be

directly connected to AGND.

CH0- and CH0+, and CH1- and CH1+, are the two fully

differential analog voltage inputs for the Delta-Sigma

ADCs.

The linear and specified region of the channels are

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±500 mV/GAIN with

V_REF= 2.4V.

3.8

Digital Ground Connection

(DGND)

The maximum absolute voltage, with respect to AGND,

for each CHn+/- input pin is ±1V with no distortion and

±6V with no breaking after continuous voltage.

DGND is the ground connection to internal digital

circuitry (SINC filters, oscillator, serial interface). To

ensure accuracy and noise cancellation, DGND must be

connected to the same ground as AGND, preferably with

a star connection. If a digital ground plane is available, it

is recommended that this pin be tied to this plane of the

Printed Circuit Board (PCB). This plane should also

reference all other digital circuitry in the system.

3.5

Analog Ground (AGND)

AGND is the ground connection to internal analog

circuitry (ADCs, PGA, voltage reference, POR). To

ensure accuracy and noise cancellation, this pin must

be connected to the same ground as DGND, preferably

with a star connection. If an analog ground plane is

available, it is recommended that this pin be tied to this

plane of the PCB. This plane should also reference all

other analog circuitry in the system.

3.9

Modulator Data Output Pin for

Channel 1 and Channel 0

(MDAT1/MDAT0)

3.6

Non-Inverting Reference Input,

Internal Reference Output

(REFIN+/OUT)

MDAT0 and MDAT1 are the output pins for the

modulator serial bitstreams of ADC Channels 0 and 1,

respectively. These pins are high-impedance by

default. When the MODOUT<1:0> are enabled, the

modulator bitstream of the corresponding channel is

present on the pin and updated at the AMCLK

frequency. (See Section 5.4 “Modulator Output

Block” for a complete description of the modulator

outputs.) These pins can be directly connected to a

MCU or DSP when a specific digital filtering is needed.

This pin is the non-inverting side of the differential

voltage reference input for both ADCs or the internal

voltage reference output.

When VREFEXT = 1, and an external voltage

reference source can be used, the internal voltage ref-

erence is disabled. When using an external differential

voltage reference, it should be connected to its V_REF

+

pin. When using an external single-ended reference, it

should be connected to this pin.

3.10 DR (Data Ready Pin)

The data ready pin indicates if a new conversion result

is ready to be read. The default state of this pin is high

when DR_HIZN = 1 and is high-impedance when

DR_HIZN = 0 (default). After each conversion is

finished, a low pulse will take place on the data ready

pin to indicate the conversion result is ready as an

interrupt. This pulse is synchronous with the master

clock and has a defined and constant width.

When VREFEXT = 0, the internal voltage reference is

enabled and connected to this pin through a switch.

This voltage reference has minimal drive capability, and

thus, needs proper buffering and bypass capacitances

(10 µF tantalum in parallel with 0.1 µF ceramic) if used

as a voltage source.

For optimal performance, bypass capacitances should

be connected between this pin and AGND at all times,

even when the internal voltage reference is used.

However, these capacitors are not mandatory to

ensure proper operation.

The data ready pin is independent of the SPI interface

and acts like an interrupt output. The data ready pin state

is not latched and the pulse width (and period) are both

determined by the MCLK frequency, over-sampling rate

and internal clock prescale settings. The DR pulse width

is equal to one DMCLK period and the frequency of the

pulses is equal to DRCLK (see Figure 1-3).

Note:

This pin should not be left floating when the

DR_HIZN bit is low; a 100 kΩ pull-up

resistor

connected

to

D_VDD

is

recommended.

DS22192D-page 16

MCP3901

3.11 Oscillator and Master Clock Input

Pins (OSC1/CLKI, OSC2)

3.14 SDO (Serial Data Output)

This is the SPI data output pin. Data is clocked out of

the device on the falling edge of SCK.

OSC1/CLKI and OSC2 provide the master clock for the

device. When CLKEXT = 0(default), a resonant crystal

or clock source with a similar sinusoidal waveform must

be placed across these pins to ensure proper

operation. The typical clock frequency specified is

4 MHz. However, the clock frequency can be 1 MHz to

5 MHz without disturbing ADC accuracy. With the

current boost circuit enabled, the master clock can be

used up to 8.192 MHz without disturbing ADC

accuracy. Appropriate load capacitance should be

connected to these pins for proper operation.

This pin stays high-impedance during the first

command byte. It also stays high-impedance during the

whole communication for write commands, and when

the CS pin is high or when the RESET pin is low. This

pin is active only when a read command is processed.

Each read is processed by a packet of 8 bits.

3.15 SDI (Serial Data Input)

This is the SPI data input pin. Data is clocked into the

device on the rising edge of SCK.

Note:

When CLKEXT = 1, the crystal oscillator is

disabled, as well as the OSC2 input. The

OSC1 becomes the master clock input,

CLKI, the direct path for an external clock

source; for example, a clock source

generated by an MCU.

When CS is low, this pin is used to communicate with a

series of 8-bit commands.

The interface is half-duplex (inputs and outputs do not

happen at the same time).

Each communication starts with a chip select falling

edge, followed by an 8-bit command word entered

through the SDI pin. Each command is either a read or

a write command. Toggling SDI during a read

command has no effect.

3.12 CS (Chip Select)

This pin is the SPI chip select that enables the serial

communication. When this pin is high, no

communication can take place. A chip select falling

edge initiates the serial communication and a chip

select rising edge terminates the communication. No

communication can take place, even when CS is low

and when RESET is low.

This input is Schmitt triggered.

3.13 SCK (Serial Data Clock)

This is the serial clock pin for SPI communication.

Data is clocked into the device on the rising edge of

SCK. Data is clocked out of the device on the falling

edge of SCK.

The MCP3901 interface is compatible with both SPI 0,0

and 1,1 modes. SPI modes can only be changed during

a Reset.

The maximum clock speed specified is 20 MHz when

DV_DD> 4.5V and 10 MHz otherwise.

This input is Schmitt triggered.

DS22192D-page 17

MCP3901

NOTES:

DS22192D-page 18

MCP3901

4.2

AMCLK – Analog Master Clock

4.0

TERMINOLOGY AND

FORMULAS

This is the clock frequency that is present on the analog

portion of the device, after prescaling has occurred via

the CONFIG1 PRESCALE<1:0> register bits. The

analog portion includes the PGAs and the two

Sigma-Delta modulators.

This section defines the terms and formulas used

throughout this data sheet. The following terms are

defined:

MCLK – Master Clock

AMCLK – Analog Master Clock

DMCLK – Digital Master Clock

DRCLK – Data Rate Clock

Oversampling Ratio (OSR)

Offset Error

EQUATION 4-1:

MCLK

AMCLK = ------------------------------

PRESCALE

TABLE 4-1:

MCP3901 OVERSAMPLING

RATIO SETTINGS

Gain Error

Integral Nonlinearity Error

Signal-to-Noise Ratio (SNR)

Signal-to-Noise Ratio And Distortion (SINAD)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

MCP3901 Delta-Sigma Architecture

Idle Tones

Config

Analog Master Clock

Prescale

PRE<1:0>

0

1

0

1

0

1

AMCLK = MCLK/1 (default)

AMCLK = MCLK/2

AMCLK = MCLK/4

AMCLK = MCLK/8

4.3

DMCLK – Digital Master Clock

Dithering

Crosstalk

This is the clock frequency that is present on the digital

portion of the device, after prescaling and division by 4.

This is also the sampling frequency, which is the rate

when the modulator outputs are refreshed. Each period

of this clock corresponds to one sample and one

modulator output (see Figure 1-5).

PSRR

CMRR

ADC Reset Mode

Hardware Reset Mode (RESET = 0)

ADC Shutdown Mode

Full Shutdown Mode

EQUATION 4-2:

AMCLK

DMCLK = -------------------- = ---------------------------------------

4 × PRESCALE

MCLK

4

4.1

MCLK – Master Clock

This is the fastest clock present in the device. This is

the frequency of the crystal placed at the OSC1/OSC2

inputs when CLKEXT = 0or the frequency of the clock

input at the OSC1/CLKI when CLKEXT = 1 (see

Figure 1-5).

4.4

DRCLK – Data Rate Clock

This is the output data rate (i.e., the rate at which the

ADCs output new data). Each new data is signaled by

a Data Ready pulse on the DR pin.

This data rate is depending on the OSR and the

prescaler with the following formula:

EQUATION 4-3:

DMCLK

OSR

AMCLK

4 × OSR

MCLK

4 × OSR × PRESCALE

DRCLK = --------------------- = --------------------- = ----------------------------------------------------------

DS22192D-page 19

MCP3901

Since this is the output data rate, and since the

decimation filter is a SINC (or notch) filter, there is a

notch in the filter transfer function at each integer

multiple of this rate.

The following table describes the various combinations

of OSR and PRESCALE, and their associated AMCLK,

DMCLK and DRCLK rates.

TABLE 4-2:

DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE

PRE

<1:0>

DRCLK

(ksps)

SINAD

(dB)

ENOB

(bits)

OSR <1:0> OSR

AMCLK

DMCLK

DRCLK

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

256

128

64

MCLK/8

MCLK/4

MCLK/2

MCLK

MCLK/32

MCLK/16

MCLK/8

MCLK/4

MCLK/8192

MCLK/4096

MCLK/2048

MCLK/1024

MCLK/4096

MCLK/2048

MCLK/1024

MCLK/512

MCLK/2048

MCLK/1024

MCLK/512

MCLK/256

MCLK/1024

MCLK/512

MCLK/256

MCLK/128

0.4882

0.976

1.95

91.4

86.6

78.7

68.2

91.4

86.6

78.7

68.2

91.4

86.6

78.7

68.2

91.4

86.6

78.7

68.2

14.89

14.10

12.78

11.04

14.89

14.10

12.78

11.04

14.89

14.10

12.78

11.04

14.89

14.10

12.78

11.04

1

32

3.9

1

256

128

64

0.976

1.95

1

3.9

1

32

7.8125

1.95

0

256

128

64

0

3.9

0

7.8125

15.625

3.9

0

32

0

256

128

64

0

MCLK

7.8125

15.625

31.25

0

MCLK

0

32

MCLK

Note:

For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1.

4.5

Oversampling Ratio (OSR)

4.6

Offset Error

The ratio of the sampling frequency to the output data

rate is OSR = DMCLK/DRCLK. The default OSR is 64

or with MCLK = 4 MHz and PRESCALE = 1,

AMCLK = 4 MHz, f_S= 1 MHz, f_D= 15.625 ksps. The

following bits in the CONFIG1 register are used to

change the Oversampling Ratio (OSR).

This is the error induced by the ADC when the inputs

are shorted together (V_IN= 0V). The specification

incorporates both PGA and ADC offset contributions.

This error varies with PGA and OSR settings. The

offset is different on each channel and varies from chip

to chip. This offset error can easily be calibrated out by

a MCU with a subtraction. The offset is specified in mV.

TABLE 4-3:

MCP3901 OVERSAMPLING

RATIO SETTINGS

The offset on the MCP3901 has a low temperature

coefficient; see Section 2.0 “Typical Performance

Curves”.

CONFIG

OVERSAMPLING RATIO

OSR

OSR<1:0>

4.7

Gain Error

0

1

0

1

0

1

32

64 (default)

128

This is the error induced by the ADC on the slope of the

transfer function. It is the deviation expressed in percent

(%) compared to the ideal transfer function defined by

Equation 5-3. The specification incorporates both PGA

and ADC gain error contributions, but not the V_REF

contribution (it is measured with an external V_REF). This

error varies with PGA and OSR settings.

256

The gain error on the MCP3901 has a low temperature

coefficient; see the typical performance curves for

more information, Figure 2-24 and Figure 2-25.

DS22192D-page 20

MCP3901

4.8

Integral Nonlinearity Error

4.11 Total Harmonic Distortion (THD)

Integral nonlinearity error is the maximum deviation of

an ADC transition point from the corresponding point of

an ideal transfer function, with the offset and gain

errors removed, or with the end points equal to zero.

The total harmonic distortion is the ratio of the output

harmonic’s power to the fundamental signal power for

a sinewave input and is defined by Equation 4-7:

It is the maximum remaining error after calibration of

offset and gain errors for a DC input signal.

EQUATION 4-7:

HarmonicsPower

FundamentalPower

⎛

⎞

THD(dB) = 10log ----------------------------------------------------

4.9

Signal-to-Noise Ratio (SNR)

⎝

⎠

For the MCP3901 ADC, the Signal-to-Noise ratio is a

ratio of the output fundamental signal power to the

noise power (not including the harmonics of the signal),

when the input is a sinewave at a predetermined

frequency. It is measured in dB. Usually, only the

maximum Signal-to-Noise ratio is specified. The SNR

calculation mainly depends on the OSR and DITHER

settings of the device.

The THD calculation includes the first 35 harmonics for

the MCP3901 specifications. The THD is usually only

measured with respect to the 10 first harmonics. THD

is sometimes expressed in %. For converting the THD

in %, here is the formula:

EQUATION 4-8:

EQUATION 4-4:

SIGNAL-TO-NOISE RATIO

THD(dB)

THD(%) = 100 × 10^{------------------------}

20

SignalPower

⎛

⎞

⎠

SNR(dB) = 10log ----------------------------------

⎝

NoisePower

This specification depends mainly on the DITHER

setting.

4.10 Signal-to-Noise Ratio And

Distortion (SINAD)

4.12 Spurious-Free Dynamic Range

(SFDR)

The most important figure of merit, for the analog

performance of the ADCs present on the MCP3901, is

the

Signal-to-Noise

and

Distortion

(SINAD)

SFDR is the ratio between the output power of the

fundamental and the highest spur in the frequency

spectrum. The spur frequency is not necessarily a

harmonic of the fundamental, even though it is usually

the case. This figure represents the dynamic range of

the ADC when a full-scale signal is used at the input.

This specification depends mainly on the DITHER

setting.

specification.

Signal-to-Noise and distortion ratio are similar to the

Signal-to-Noise ratio, with the exception that you must

include the harmonics power in the noise power

calculation. The SINAD specification mainly depends

on the OSR and DITHER settings.

EQUATION 4-5:

SINAD EQUATION

EQUATION 4-9:

SignalPower

Noise + HarmonicsPower

⎛

⎞

⎠

SINAD(dB) = 10log --------------------------------------------------------------------

⎝

FundamentalPower

⎛

⎞

SFDR(dB) = 10log ----------------------------------------------------

⎝

⎠

HighestSpurPower

The calculated combination of SNR and THD per the

following formula also yields SINAD:

EQUATION 4-6:

SINAD, THD AND SNR

RELATIONSHIP

SNR

10

–THD

---------------

10

⎛

⎞

⎠

⎛

⎞

⎠

SINAD(dB) = 10log 10^⎝^-----------+ 10^⎝

DS22192D-page 21

MCP3901

These Idle tones are residues that are inherent to the

quantization process and the fact that the converter is

integrating at all times without being reset. They are

residues of the finite resolution of the conversion

process. They are very difficult to attenuate and they are

heavily signal dependent. They can degrade both the

SFDR and THD of the converter, even for DC inputs.

They can be localized in the baseband of the converter,

and thus, difficult to filter from the actual input signal.

4.13 MCP3901 Delta-Sigma

Architecture

The MCP3901 incorporates two Delta-Sigma ADCs

with a multi-bit architecture. A Delta-Sigma ADC is an

oversampling converter that incorporates a built-in

modulator, which is digitizing the quantity of charge

integrated by the modulator loop (see Figure 5-1). The

quantizer is the block that is performing the

Analog-to-Digital conversion. The quantizer is typically

1 bit, or a simple comparator which helps to maintain

the linearity performance of the ADC (the DAC

structure, is in this case, inherently linear).

For power metering applications, Idle tones can be very

disturbing because energy can be detected even at the

50 or 60 Hz frequency, depending on the DC offset of

the ADCs, while no power is really present at the

inputs. The only practical way to suppress or attenuate

the Idle tones phenomenon is to apply dithering to the

ADC. The Idle tone amplitudes are a function of the

order of the modulator, the OSR and the number of

levels in the quantizer of the modulator. A higher order,

a higher OSR or a higher number of levels for the

quantizer will attenuate the Idle tones amplitude.

Multi-bit quantizers help to lower the quantization error

(the error fed back in the loop can be very large with

1-bit quantizers) without changing the order of the

modulator or the OSR, which leads to better SNR

figures. Typically, however, the linearity of such

architectures is more difficult to achieve, since the DAC

is no more simple to realize, and its linearity limits the

THD of such ADCs.

4.15 Dithering

The MCP3901’s 5-level quantizer is a Flash ADC,

composed of 4 comparators arranged with equally

spaced thresholds and a thermometer coding. The

MCP3901 also includes proprietary 5-level DAC

architecture that is inherently linear for improved THD

figures.

In order to suppress or attenuate the Idle tones present

in any Delta-Sigma ADCs, dithering can be applied to

the ADC. Dithering is the process of adding an error to

the ADC feedback loop in order to “decorrelate” the

outputs and “break” the Idle tones behavior. Usually, a

random or pseudo-random generator adds an analog

or digital error to the feedback loop of the Delta-Sigma

ADC in order to ensure that no tonal behavior can

happen at its outputs. This error is filtered by the

feedback loop, and typically, has a zero average value

so that the converter static transfer function is not

disturbed by the dithering process. However, the

dithering process slightly increases the noise floor (it

adds noise to the part) while reducing its tonal behavior,

and thus, improving SFDR and THD (see Figure 2-10

and Figure 2-14). The dithering process scrambles the

Idle tones into baseband white noise and ensures that

dynamic specs (SNR, SINAD, THD, SFDR) are less

signal dependent. The MCP3901 incorporates a

proprietary dithering algorithm on both ADCs in order to

remove Idle tones and improve THD, which is crucial

for power metering applications.

4.14 Idle Tones

A Delta-Sigma Converter is an integrating converter. It

also has a finite quantization step (LSB) which can be

detected by its quantizer. A DC input voltage that is

below the quantization step should only provide an all

zeros result, since the input is not large enough to be

detected. As an integrating device, any Delta-Sigma

will show, in this case, Idle tones. This means that the

output will have spurs in the frequency content that are

depending on the ratio between quantization step

voltage and the input voltage. These spurs are the

result of the integrated sub-quantization step inputs

that will eventually cross the quantization steps after a

long enough integration. This will induce an AC

frequency at the output of the ADC and can be shown

in the ADC output spectrum.

DS22192D-page 22

MCP3901

It is defined as:

4.16 Crosstalk

The crosstalk is defined as the perturbation caused by

one ADC channel on the other ADC channel. It is a

measurement of the isolation between the two ADCs

present in the chip.

EQUATION 4-11:

ΔV_OUT

⎛

⎞

⎠

PSRR(dB) = 20log ------------------

⎝

ΔAV_DD

This measurement is a two-step procedure:

Where V_OUTis the equivalent input voltage that the

output code translates to with the ADC transfer

function. In the MCP3901 specification, AV_DDvaries

from 4.5V to 5.5V, and for AC PSRR, a 50/60 Hz

sinewave is chosen, centered around 5V with a

maximum 500 mV amplitude. The PSRR specification

1. Measure one ADC input with no perturbation on

the other ADC (ADC inputs shorted).

2. Measure the same ADC input with

a

perturbation sine wave signal on the other ADC

at a certain predefined frequency.

The crosstalk is then the ratio between the output

power of the ADC when the perturbation is present and

when it is not divided by the power of the perturbation

signal.

is measured with AV_DD= DV_DD

.

4.18 CMRR

This is the ratio between

a

change in the

A lower crosstalk value implies more independence

and isolation between the two channels.

common-mode input voltage and the ADC output

codes. It measures the influence of the common-mode

input voltage on the ADC outputs.

The measurement of this signal is performed under the

following conditions:

The CMRR specification can be DC (the

common-mode input voltage is taking multiple DC

values) or AC (the common-mode input voltage is a

sinewave at a certain frequency with a certain

common-mode). In AC, the amplitude of the sinewave

is representing the change in the power supply.

• GAIN = 1,

• PRESCALE = 1,

• OSR = 256,

• MCLK = 4 MHz

It is defined as:

Step 1

• CH0+ = CH0- = AGND

• CH1+ = CH1- = AGND

EQUATION 4-12:

ΔV_OUT

⎛

⎞

CMRR(dB) = 20log -----------------

⎝

⎠

ΔV_CM

Step 2

• CH0+ = CH0- = AGND

Where V_CM= (CHn+ + CHn-)/2 is the common-mode

input voltage and V_OUTis the equivalent input voltage,

the output code is translated to the ADC transfer

function. In the MCP3901 specification, VCM varies

from -1V to +1V, and for the AC specification, a 50/

60 Hz sinewave is chosen, centered around 0V, with a

500 mV amplitude.

• CH1+ – CH1- = 1 V_P-P@ 50/60 Hz (full-scale

sine wave)

The crosstalk is then calculated with the following

formula:

EQUATION 4-10:

ΔCH0Power

ΔCH1Power

⎛

⎞

⎠

CTalk(dB) = 10log --------------------------------

4.19 ADC Reset Mode

⎝

ADC Reset mode (also called Soft Reset mode) can

only be entered through setting the RESET<1:0> bits

high in the Configuration register. This mode is defined

as the condition where the converters are active, but

their output is forced to ‘0’.

4.17 PSRR

This is the ratio between a change in the power supply

voltage and the ADC output codes. It measures the

influence of the power supply voltage on the ADC

outputs.

The registers are not affected in this Reset mode and

retain their values.

The ADCs can immediately output meaningful codes

after leaving Reset mode (and after the sinc filter

settling time of 3/DRCLK). This mode is both entered

and exited through the setting of bits in the

Configuration register.

The PSRR specification can be DC (the power supply

is taking multiple DC values) or AC (the power supply

is a sinewave at a certain frequency with a certain

common-mode). In AC, the amplitude of the sinewave

is representing the change in the power supply.

DS22192D-page 23

MCP3901

Each converter can be placed in Soft Reset mode

independently. The Configuration registers are not

modified by the Soft Reset mode.

Each converter can be placed in Shutdown mode,

independently. The CONFIG registers are not modified

by the Shutdown mode. This mode is only available

through programming the SHUTDOWN<1:0> bits in

the CONFIG2 register.

A data ready pulse will not be generated by any ADC

while in Reset mode.

The output data is flushed to all zeros while in ADC

shutdown. No data ready pulses are generated by any

ADC while in ADC Shutdown mode.

Reset mode also effects the modulator output block

(i.e., the MDAT pin, corresponding to the channel in

Reset). If enabled, it provides

a

bitstream

corresponding to a zero output (a series of ‘0011’ bits

continuously repeated).

ADC Shutdown mode also effects the modulator output

block (i.e., if MDAT of the channel in Shutdown mode is

enabled). This pin will provide a bitstream correspond-

ing to a zero output (series of ‘0011’ bits continuously

repeated).

When an ADC exits ADC Reset mode, any phase delay

present, before Reset was entered, will still be present.

If one ADC was not in Reset, the ADC leaving Reset

mode will automatically resynchronize the phase delay.

The resynchronization is relative to the other ADC

channel per the Phase Delay register block and gives

DR pulses accordingly.

When an ADC exits ADC Shutdown mode, any phase

delay present before shutdown was entered will still be

present. If one ADC was not in shutdown, the ADC

leaving Shutdown mode will automatically resynchro-

nize the phase delay relative to the other ADC channel,

per the Phase Delay register block, and give DR pulses

accordingly.

If an ADC is placed in Reset mode while the other is

converting, it is not shutting down the internal clock.

When going back out of Reset, it will be resynchronized

automatically with the clock that did not stop during

Reset.

If an ADC is placed in Shutdown mode while the other

is converting, it is not shutting down the internal clock.

When going back out of shutdown, it will be

resynchronized automatically with the clock that did not

stop during Reset.

If both ADCs are in Soft Reset or Shutdown modes, the

clock is no longer distributed to the digital core for low-

power operation. Once any of the ADC is back to normal

operation, the clock is automatically distributed again.

If both ADCs are in ADC Reset or ADC Shutdown

modes, there is no more distribution of the clock to the

digital core for low-power operation. Once any of the

ADC is back to normal operation, the clock is

automatically distributed again.

4.20 Hard Reset Mode (RESET = 0)

This mode is only available during a Power-on-Reset

(POR) or when the RESET pin is pulled low. The RESET

pin low state places the device in a Hard Reset mode.

4.22 Full Shutdown Mode

In this mode, all internal registers are reset to their

default state.

The lowest power consumption can be achieved when

SHUTDOWN<1:0> = 11and VREFEXT = CLKEXT = 1.

This mode is called “Full Shutdown mode” and no

analog circuitry is enabled. In this mode, the POR AV_DD

monitoring circuit is also disabled. When the clock is Idle

(CLKI = 0 or 1 continuously), no clock is propagated

throughout the chip. Both ADCs are in shutdown, the

internal voltage reference is disabled and the internal

oscillator is disabled.

The DC biases for the analog blocks are still active (i.e.,

the MCP3901 is ready to convert). However, this pin

clears all conversion data in the ADCs. In this mode,

the MDAT outputs are in high-impedance. The

comparator outputs of both ADCs are forced to their

Reset state (‘0011’). The SINC filters are all reset, as

well as their double output buffers. See serial timing for

minimum pulse low time in Section 1.0 “Electrical

Characteristics”.

The only circuit that remains active is the SPI interface,

but this circuit does not induce any static power

consumption. If SCK is Idle, the only current

consumption comes from the leakage currents induced

by the transistors and is less than 1 µA on each power

supply.

During a Hard Reset, no communication with the part is

possible. The digital interface is maintained in a Reset

state.

4.21 ADC Shutdown Mode

This mode can be used to power down the chip

completely and avoid power consumption when there

is no data to convert at the analog inputs. Any SCK or

MCLK edge coming while on this mode, will induce

dynamic power consumption.

ADC Shutdown mode is defined as a state where the

converters and their biases are off, consuming only

leakage current. After this is removed, start-up delay

time (SINC filter settling time) will occur before outputting

meaningful codes. The start-up delay is needed to

power-up all DC biases in the channel that was in

shutdown. This delay is the same as t_PORand any DR

pulse coming within this delay should be discarded.

Once any of the SHUTDOWN, CLKEXT and VREFEXT

bits returns to ‘0’, the POR AV_DDmonitoring block is

back to operation and AV_DDmonitoring can take place.

DS22192D-page 24

MCP3901

5.3

Delta-Sigma Modulator

5.0

5.1

DEVICE OVERVIEW

Analog Inputs (CHn+/-)

5.3.1

ARCHITECTURE

Both ADCs are identical in the MCP3901 and they

include a second-order modulator with a multi-bit DAC

architecture (see Figure 5-1). The quantizer is a Flash

ADC composed of 4 comparators with equally spaced

thresholds and a thermometer output coding. The

proprietary 5-level architecture ensures minimum

quantization noise at the outputs of the modulators

without disturbing linearity or inducing additional

distortion. The sampling frequency is DMCLK (typically

1 MHz with MCLK = 4 MHz) so the modulator outputs

are refreshed at a DMCLK rate. The modulator outputs

are available in the MOD register or serially transferred

on each MDAT pin.

The MCP3901 analog inputs can be connected directly

to current and voltage transducers (such as shunts,

current transformers, or Rogowski coils). Each input

pin is protected by specialized ESD structures that are

certified to pass 7 kV HBM and 400V MM contact

charge. These structures allow bipolar ±6V continuous

voltage, with respect to AGND, to be present at their

inputs without the risk of permanent damage.

Both channels have fully differential voltage inputs for

better noise performance. The absolute voltage at each

pin, relative to AGND, should be maintained in the ±1V

range during operation in order to ensure the specified

ADC accuracy. The common-mode signals should be

adapted to respect both the previous conditions and

the differential input voltage range. For best

performance, the common-mode signals should be

maintained to AGND.

Both modulators also include a dithering algorithm that

can be enabled through the DITHER<1:0> bits in the

Configuration register. This dithering process improves

THD and SFDR (for high OSR settings) while slightly

increasing the noise floor of the ADCs. For power

metering applications and applications that are

distortion-sensitive, it is recommended to keep DITHER

enabled for both ADCs. In the case of power metering

applications, THD and SFDR are critical specifications to

optimize SNR (noise floor). This is not really problematic

due to a large averaging factor at the output of the ADCs;

therefore, even for low OSR settings, the dithering

algorithm will show a positive impact on the performance

of the application.

5.2

Programmable Gain Amplifiers

(PGA)

The two Programmable Gain Amplifiers (PGAs) reside

at the front end of each Delta-Sigma ADC. They have

two functions: translate the common-mode of the input

from AGND to an internal level between AGND and

AV_DD, and amplify the input differential signal. The

translation of the common-mode does not change the

differential signal, but recenters the common-mode so

that the input signal can be properly amplified.

Figure 5-1 represents a simplified block diagram of the

Delta-Sigma ADC present on MCP3901.

The PGA block can be used to amplify very low signals,

but the differential input range of the Delta-Sigma

modulator must not be exceeded. The PGA is

controlled by the PGA_CHn<2:0> bits in the GAIN

register. The following table represents the gain

settings for the PGA:

Quantizer

Loop

Filter

Output

Differential

Second-

Order

Integrator

Voltage Input

Bitstream

5-Level

Flash ADC

TABLE 5-1:

PGA CONFIGURATION

SETTING

Gain

(dB)

V_INRange

(V)

PGA_CHn<2:0> (V/V)

DAC

0

1

0

1

0

1

0

1

0

1

2

0

±0.5

MCP3901 Delta-Sigma Modulator

6

±0.25

4

12

18

24

30

±0.125

FIGURE 5-1:

Block Diagram.

Simplified Delta-Sigma ADC

8

±0.0625

±0.03125

±0.015625

16

32

DS22192D-page 25

MCP3901

5.3.2

MODULATOR INPUT RANGE AND

SATURATION POINT

TABLE 5-2:

DELTA-SIGMA MODULATOR

CODING

For a specified voltage reference value of 2.4V, the

modulators’ specified differential input range is

±500 mV. The input range is proportional to V_REFand

scales according to the V_REFvoltage. This range

ensures the stability of the modulator over amplitude

and frequency. Outside of this range, the modulator is

still functional, however, its stability is no longer

ensured, and therefore, it is not recommended to

exceed this limit. The saturation point for the modulator

is V_REF/3, since the transfer function of the ADC

includes a gain of 3 by default (independent from

the PGA setting). See Section 5.6 “ADC Output

Coding”.

Comp<3:0>

Code

Modulator

Output Code

MDAT Serial

Stream

1111

0111

0011

0001

0000

+2

+1

0

1111

0111

0011

0001

0000

-1

-2

COMP

<0>

COMP

COMP COMP

<3> <2>

<1>

5.3.3

BOOST MODE

AMCLK

DMCLK

The Delta-Sigma modulators also include an

independent BOOST mode for each channel. If the

corresponding BOOST<1:0> bits are enabled, the

power consumption of the modulator is multiplied by 2.

Its bandwidth is increased to be able to sustain AMCLK

clock frequencies up to 8.192 MHz, while keeping the

ADC accuracy. When disabled, the power consumption

is back to normal and the AMCLK clock frequencies

can only reach up to 5 MHz without affecting ADC

accuracy.

MDAT+2

MDAT+1

MDAT+0

5.4

Modulator Output Block

If the user wishes to use the modulator output of the

device, the appropriate bits to enable the modulator

output must be set in the Configuration register.

MDAT-1

When MODOUT<1:0> are enabled, the modulator

output of the corresponding channel is present at the

corresponding MDAT output pin as soon as the

command is placed.

MDAT-2

Since the Delta-Sigma modulators have a 5-level

output given by the state of 4 comparators with

thermometer coding, their outputs can be represented

on 4 bits. Each bit gives the state of the corresponding

comparator (see Table 5-2). These bits are present on

the MOD register and are updated at the DMCLK rate.

FIGURE 5-2:

Function of the Modulator Output Code.

MDAT Serial Outputs in

Since the Reset and shutdown SPI commands are

asynchronous, the MDAT pins are resynchronized with

DMCLK after each time the part goes out of Reset and

shutdown.

In order to output the comparators result on a separate

pin (MDAT0 and MDAT1), these comparator output bits

have been arranged to be serially output at the AMCLK

rate (see Figure 5-2).

This means that the first output of MDAT after Reset is

always ‘0011’ after the first DMCLK rising edge.

This 1-bit serial bitstream is the same as what would be

produced by a 1-bit DAC modulator with a sampling

frequency of AMCLK. The modulator can either be

considered as a 5 level-output at DMCLK rate or a 1-bit

output at AMCLK rate. These two representations are

interchangeable. The MDAT outputs can, therefore, be

used in any application that requires 1-bit modulator

outputs. These applications will often integrate and

filter the 1-bit output with SINC or more complex

decimation filters computed by an MCU or a DSP.

DS22192D-page 26

MCP3901

3

The Normal Mode Rejection Ratio (NMRR) or gain of

the transfer function is given by the following equation:

5.5

SINC Filter

Both ADCs present in the MCP3901 include a

decimation filter that is a third-order sinc (or notch)

filter. This filter processes the multi-bit bitstream into

16 or 24-bit words (depending on the WIDTH

Configuration bit). The settling time of the filter is

3 DMCLK periods. It is recommended that unsettled

data be discarded to avoid data corruption, which can

be done easily by setting the DR_LTY bit high in the

STATUS/COM register.

EQUATION 5-2:

MAGNITUDE OF

FREQUENCY RESPONSE

H(f)

3

f

⎛

⎞

⎠

sinc π ⋅ ---------------------

⎝

DMCLK

NMRR(f) =

---------------------------------------------

f

⎛

⎞

sinc π ⋅ --------------------

⎝

⎠

DRCLK

The resolution achievable at the output of the sinc filter

(the output of the ADC) is dependant on the OSR and

is summarized with the following table:

or:

TABLE 5-3:

OSR<1:0>

ADC RESOLUTION vs. OSR

3

f

f_S

⎛

⎞

⎠

sinc π ⋅ ---

⎝

ADC Resolution (bits)

OSR

NMRR(f) =

-----------------------------

No Missing Codes

f

⎛

⎞

⎠

sinc π ⋅ ----

⎝

f_D

0

1

0

1

0

1

32

64

17

20

23

24

where:

128

256

sin(x)

sinc(x) = --------------

x

For 24-Bit Output mode (WIDTH = 1), the output of the

sinc filter is padded with least significant zeros for any

resolution less than 24 bits.

Figure 5-3 shows the sinc filter frequency response:

For 16-Bit Output modes, the output of the sinc filter is

rounded to the closest 16-bit number in order to

conserve only 16-bit words and to minimize truncation

error.

20

0

The gain of the transfer function of this filter is 1 at each

multiple of DMCLK (typically 1 MHz) so a proper

anti-aliasing filter must be placed at the inputs. This will

attenuate the frequency content around DMCLK and

keep the desired accuracy over the baseband of the

converter. This anti-aliasing filter can be a simple,

first-order RC network with a sufficiently low time

constant to generate high rejection at DMCLK

frequency.

-20

-40

-60

-80

-100

-120

1

10

100

1000

10000 100000 1000000

Input Frequency (Hz)

FIGURE 5-3:

MCLK = 4 MHz, OSR = 64, PRESCALE = 1.

SINC Filter Response with

EQUATION 5-1:

SINC FILTER TRANSFER

FUNCTION H(Z)

3

1 – z^–OSR

H(z) = --------------------------------

⎛

⎞

⎟

⎠

⎜

–1

⎝

OSR(1 – z

)

Where:

2πfj

DMCLK

⎛

⎞

⎠

z = exp ---------------------

⎝

DS22192D-page 27

MCP3901

In case of positive saturation (CHn+ – CHn- > V_REF/3),

the output is locked to 7FFFFF for 24-bit mode (7FFF

for 16-bit mode). In case of negative saturation

(CHn+ – CHn- < -V_REF/3), the output code is locked to

800000 for 24-bit mode (8000 for 16-bit mode).

5.6

ADC Output Coding

The second-order modulator, SINC³filter, PGA, V_REF

and analog input structure all work together to produce

the device transfer function for the Analog-to-Digital

conversion (see Equation 5-3).

Equation 5-3 is only true for DC inputs. For AC inputs,

this transfer function needs to be multiplied by the

transfer function of the SINC³filter (see Equation 5-1

and Equation 5-2).

The channel data is either a 16-bit or 24-bit word,

presented in a 23-bit or 15-bit plus sign, two’s

complement format, and is MSB (left) justified.

The ADC data is two or three bytes wide depending on

the WIDTH bit of the associated channel. The 16-bit

mode includes a round to the closest 16-bit word

(instead of truncation) in order to improve the accuracy

of the ADC data.

EQUATION 5-3:

(CH_n+– CH_n-)

⎛

⎞

(For 24-Bit Mode or WIDTH = 1)

DATA_CHn = ------------------------------------- × 8,388,608 × G × 3

⎝

⎠

V_REF+– V_REF-

(CH_n+– CH_n-)

⎛

⎞

(For 16-Bit Mode or WIDTH = 0)

DATA_CHn = ------------------------------------- × 32, 768 × G × 3

⎝

⎠

_REF+– V_REF-

V

5.6.1

ADC RESOLUTION AS A FUNCTION

OF OSR

The ADC resolution is a function of the OSR

(Section 5.5 “SINC3 Filter”). The resolution is the

same for both channels. No matter what the resolution

is, the ADC output data is always presented in 24-bit

words, with added zeros at the end if the OSR is not

large enough to produce 24-bit resolution (left

justification).

TABLE 5-4:

OSR = 256 OUTPUT CODE EXAMPLES

ADC Output Code (MSB First)

Hexadecimal

Decimal

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x7FFFFF

0x7FFFFE

0x000000

0xFFFFFF

0x800001

0x800000

+ 8,388,607

+ 8,388,606

0

-1

- 8,388,607

- 8,388,608

TABLE 5-5:

OSR = 128 OUTPUT CODE EXAMPLES

ADC Output Code (MSB First)

Decimal

23-Bit Resolution

Hexadecimal

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x7FFFFE

0x7FFFFC

0x000000

0xFFFFFE

0x800002

0x800000

+ 4,194,303

+ 4,194,302

0

-1

- 4,194,303

- 4,194,304

DS22192D-page 28

MCP3901

TABLE 5-6:

OSR = 64 OUTPUT CODE EXAMPLES

ADC Output code (MSB First)

Decimal

20-Bit Resolution

Hexadecimal

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x7FFFF0

0x7FFFE0

0x000000

0xFFFFF0

0x800010

0x800000

+ 524, 287

+ 524, 286

0

-1

- 524,287

- 524, 288

TABLE 5-7:

OSR = 32 OUTPUT CODE EXAMPLES

ADC Output code (MSB First)

Decimal

17-Bit Resolution

Hexadecimal

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x7FFF80

0x7FFF00

0x000000

0xFFFF80

0x800080

0x800000

+ 65, 535

+ 65, 534

0

-1

- 65,535

- 65, 536

These bypass capacitors are not mandatory for correct

ADC operation, but removing these capacitors may

degrade the accuracy of the ADC. The bypass

capacitors also help the applications where the voltage

reference output is connected to other circuits. In this

case, additional buffering may be needed as the output

drive capability of this output is low.

5.7

Voltage Reference

5.7.1

INTERNAL VOLTAGE REFERENCE

The MCP3901 contains an internal voltage reference

source, specially designed to minimize drift over

temperature. In order to enable the internal voltage

reference, the VREFEXT bit in the Configuration

register must be set to ‘0’ (Default mode). This internal

V_REFsupplies reference voltage to both channels. The

typical value of this voltage reference is 2.37V ±2%.

5.7.2

DIFFERENTIAL EXTERNAL

VOLTAGE INPUTS

The internal reference has

a very low typical

When the VREFEXT bit is high, the two reference pins

(REFIN+/OUT, REFIN-) become a differential voltage

reference input. The voltage at the REFIN+/OUT pin is

noted as V_REF+ and the voltage at the REFIN- pin is

noted as V_REF-. The differential voltage input value is

given by the following equation:

temperature coefficient of ±12 ppm/°C, allowing the

output codes to have minimal variation with respect to

temperature, since they are proportional to (1/V_REF).

The noise of the internal voltage reference is low

enough not to significantly degrade the SNR of the

ADC if compared to a precision, external low noise

voltage reference.

EQUATION 5-4:

The output pin for the internal voltage reference is

REFIN+/OUT.

V_REF= V_REF+ – V_REF

-

When the internal voltage reference is enabled, the

REFIN- pin should always be connected to AGND.

The specified V_REFrange is from 2.2V to 2.6V. The

REFIN- pin voltage (V_REF-) should be limited to ±0.3V.

Typically, for single-ended reference applications, the

REFIN- pin should be directly connected to AGND.

For optimal ADC accuracy, appropriate bypass

capacitors should be placed between REFIN+/OUT

and AGND. Decoupling at the sampling frequency,

around 1 MHz, is important for any noise around this

frequency will be aliased back into the conversion data

(0.1 µF ceramic and 10 µF tantalum capacitors are

recommended).

DS22192D-page 29

MCP3901

5.8

Power-on Reset

5.9

RESET Effect on Delta-Sigma

Modulator/SINC Filter

The MCP3901 contains an internal POR circuit that

monitors analog supply voltage AV_DDduring operation.

The typical threshold for a power-up event detection is

4.2V ±5%. The POR circuit has a built-in hysteresis for

improved transient spikes immunity that has a typical

value of 200 mV. Proper decoupling capacitors (0.1 µF

ceramic and 10 µF tantalum) should be mounted as

close as possible to the AV_DDpin, providing additional

transient immunity.

When the RESET pin is low, both ADCs will be in Reset

and output code, 0x0000h. The RESET pin performs a

Hard Reset (DC biases still on, part ready to convert)

and clears all charges contained in the Delta-Sigma

modulators. The comparators’ output is ‘0011’ for each

ADC.

The SINC filters are all reset, as well as their double

output buffers. This pin is independent of the serial

interface. It brings the CONFIG registers to the default

state. When RESET is low, any write with the SPI

interface will be disabled and will have no effect. All

output pins (SDO, DR, MDAT0/1) are high-impedance,

and no clock is propagated through the chip.

Figure 5-4 illustrates the different conditions at

power-up and a power-down event in the typical

conditions. All internal DC biases are not settled until at

least 50 µs after system POR. Any DR pulses during

this time, after a system Reset, should be ignored. After

POR, DR pulses are present at the pin with all the

default conditions in the Configuration registers.

5.10 Phase Delay Block

Both AV_DDand DV_DDpower supplies are independent.

Since AV_DDis the only power supply that is monitored,

it is highly recommended to power up DV_DDfirst as a

power-up sequence. If AV_DDis powered up first, it is

highly recommended to keep the RESET pin low during

the whole power-up sequence.

The MCP3901 incorporates a phase delay generator

which ensures that the two ADCs are converting the

inputs with a fixed delay between them. The two ADCs

are synchronously sampling but the averaging of

modulator outputs is delayed. Therefore, the SINC filter

outputs (thus, the ADC outputs) show a fixed phase

delay, as determined by the PHASE register setting.

AV

DD

The PHASE register (PHASE<7:0>) is a 7 bit + sign,

MSB first, two’s complement register that indicates how

much phase delay there is to be between Channel 0

and Channel 1. The reference channel for the delay is

Channel 1 (typically the voltage channel for power

metering applications). When PHASE<7:0> are

positive, Channel 0 is lagging versus Channel 1. When

PHASE<7:0> are negative, Channel 0 is leading

versus Channel 1. The amount of delay between two

ADC conversions is given by the following formula:

5V

4.2V

4V

50 µs

t

POR

Time

0V

Device

Mode

Proper

Operation

EQUATION 5-5:

Reset

Phase Register Code

Delay = -------------------------------------------------

DMCLK

FIGURE 5-4:

Power-on Reset Operation.

The timing resolution of the phase delay is 1/DMCLK or

1 µs in the default configuration with MCLK = 4 MHz.

The data ready signals are affected by the phase delay

settings. Typically, the time difference between the data

ready pulses of Channel 0 and Channel 1 is equal to

the phase delay setting.

Note:

A detailed explanation of the Data Ready

pin (DR) with phase delay is present in

Section 6.10 “Data Ready Latches and

Data Ready Modes (DRMODE<1:0>)”.

DS22192D-page 30

MCP3901

5.10.1

PHASE DELAY LIMITS

5.11 Crystal Oscillator

The phase delay can only go from -OSR/2 to

+OSR/2 – 1. This sets the fine phase resolution. The

PHASE register is coded with two’s complement.

The MCP3901 includes a Pierce-type crystal oscillator

with very high stability and ensures very low

temperature and jitter for the clock generation. This

oscillator can handle up to 16.384 MHz crystal

frequencies provided that proper load capacitances

and the quartz quality factor are used.

If larger delays between the two channels are needed,

they can be implemented externally to the chip with an

MCU. A FIFO in the MCU can save incoming data from

the leading channel for a number N of DRCLK clocks.

In this case, DRCLK would represent the coarse timing

resolution, and DMCLK, the fine timing resolution. The

total delay will then be equal to:

For keeping specified ADC accuracy, AMCLK should

be kept between 1 and 5 MHz with BOOST off or 1 and

8.192 MHz with BOOST on. Larger MCLK frequencies

can be used provided the prescaler clock settings allow

the AMCLK to respect these ranges.

Delay = N/DRCLK + PHASE/DMCLK

For a proper start-up, the load capacitors of the crystal

should be connected between OSC1 and DGND, and

between OSC2 and DGND. They should also respect

the following equation:

The Phase Delay register can be programmed once

with the OSR = 256 setting and will adjust to the OSR

automatically afterwards, without the need to change

the value of the PHASE register.

• OSR = 256: The delay can go from -128 to +127.

PHASE<7> is the sign bit, PHASE<6> is the MSB

and PHASE<0> is the LSB.

EQUATION 5-6:

2

6

1

⎛

⎞

R_M< 1.6 × 10 × ------------------------

• OSR = 128: The delay can go from -64 to +63.

PHASE<6> is the sign bit, PHASE<5> is the MSB

and PHASE<0> is the LSB.

⎝

⎠

f × C_LOAD

Where:

• OSR = 64: The delay can go from -32 to +31.

PHASE<5> is the sign bit, PHASE<4> is the MSB

and PHASE<0> is the LSB.

f

=

Crystal frequency in MHz

C_LOAD

Load capacitance in pF including

parasitics from the PCB

• OSR = 32: The delay can go from -16 to +15.

PHASE<4> is the sign bit, PHASE<3> is the MSB

and PHASE<0> is the LSB.

R_M

=

Motional resistance in ohms of

the quartz

When CLKEXT = 1, the crystal oscillator is bypassed

by a digital buffer to allow direct clock input for an

external clock (see Figure 1-5).

TABLE 5-8:

PHASE VALUES WITH

MCLK = 4 MHZ, OSR = 256

Hex

Delay

(CH0 relative

to CH1)

PHASE

Register Value

0 1 1 1 1 1 1 1

0 1 1 1 1 1 1 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0x7F

0x7E

0x01

0x00

0xFF

0x81

0x80

+127 µs

+126 µs

+1 µs

0 µs

-1 µs

-127 µs

-128 µs

DS22192D-page 31

MCP3901

NOTES:

DS22192D-page 32

MCP3901

6.0

6.1

SERIAL INTERFACE

DESCRIPTION

A6

A5

A4 A3

A2 A1

A0 R/W

Overview

Read/

Write Bit

Device

Address

Bits

Register

The MCP3901 device is compatible with SPI Modes 0,0

and 1,1. Data is clocked out of the MCP3901 on the

falling edge of SCK and data is clocked into the

MCP3901 on the rising edge of SCK. In these modes,

SCK can Idle either high or low.

Address Bits

FIGURE 6-1:

Control Byte.

The default device address bits are ‘00’. Contact the

Microchip factory for additional device address bits. For

more information, please see the Product Identification

System section.

Each SPI communication starts with a CS falling edge

and stops with the CS rising edge. Each SPI

communication is independent. When CS is high, SDO

is in high-impedance, and transitions on SCK and SDI

have no effect. Additional controls: RESET, DR and

MDAT0/1 are also provided on separate pins for

advanced communication.

A read on undefined addresses will give an all zeros

output on the first, and all subsequent transmitted

bytes. A write on an undefined address will have no

effect and also, will not increment the address counter.

The MCP3901 interface has a simple command

structure. The first byte transmitted is always the

CONTROL byte and is followed by data bytes that are

8-bit wide. Both ADCs are continuously converting data

by default and can be reset or shut down through a

CONFIG2 register setting.

The register map is defined in Section 7.1 “ADC

Channel Data Output Registers”.

6.3

Reading from the Device

The first data byte read is the one defined by the

address given in the CONTROL byte. After this first

byte is transmitted, if the CS pin is maintained low, the

communication continues and the address of the next

transmitted byte is determined by the status of the

READ bits in the STATUS/COM register. Multiple

looping configurations can be defined through the

READ<1:0> bits for the address increment (see

Section 6.6 “SPI MODE 0,0 – Clock Idle Low, Read/

Write Examples”).

Since each ADC data is either 16 or 24 bits (depending

on the WIDTH bits), the internal registers can be

grouped together with various configurations (through

the READ bits) in order to allow easy data retrieval within

only one communication. For device reads, the internal

address counter can be automatically incremented in

order to loop through groups of data within the register

map. The SDO will then output the data located at the

ADDRESS (A<4:0>) defined in the control byte and then

ADDRESS + 1 depending on the READ<1:0> bits,

which select the groups of registers. These groups are

defined in Section 7.1 “ADC Channel Data Output

Registers” (Register Map).

6.4

Writing to the Device

The first data byte written is the one defined by the

address given in the control byte. The write

communication automatically increments the address

for subsequent bytes.

The Data Ready pin (DR) can be used as an interrupt

for an MCU and outputs pulses when new ADC

channel data is available. The RESET pin acts like a

Hard Reset and can reset the part to its default power-

up configuration. The MDAT0/1 pins give the modulator

outputs (see Section 5.4 “Modulator Output Block”).

The address of the next transmitted byte within the

same communication (CS stays low) is the next

address defined on the register map. At the end of the

register map, the address loops to the beginning of the

register map. Writing a non-writable register has no

effect.

6.2

Control Byte

The SDO pin stays in high-impedance during a write

communication.

The control byte of the MCP3901 contains two device

Address bits, A<6:5>, 5 register Address bits, A<4:0>,

and a Read/Write bit (R/W). The first byte transmitted

to the MCP3901 is always the control byte.

6.5

SPI MODE 1,1 – Clock Idle High,

Read/Write Examples

The MCP3901 interface is device addressable

(through A<6:5>) so that multiple MCP3901 chips can

be present on the same SPI bus with no data bus

contention. This functionality enables three-phase

power metering systems, containing three MCP3901

chips, controlled by a single SPI bus (single CS, SCK,

SDI and SDO pins).

In this SPI mode, the clock Idles high. For the

MCP3901, this means that there will be a falling edge

before there is a rising edge.

Note:

Changing from an SPI Mode 1,1 to an SPI

Mode 0,0 is possible, but needs a Reset

pulse in-between to ensure correct

communication.

DS22192D-page 33

MCP3901

:

CS

Data Transitions on

the Falling Edge

MCU and MCP3901 Latch

Bits on the Rising Edge

SCK

SDI

A6 A5 A4 A3 A2 A1 A0 R/W

HI-Z

D0

D7 D6 D5 D4 D3 D2 D1

D0

SDO

(ADDRESS) DATA

(ADDRESS + 1) DATA

FIGURE 6-2:

Device Read (SPI Mode 1,1 – Clock Idles High).

CS

Data Transitions on

the Falling Edge

MCU and MCP3901 Latch

Bits on the Rising Edge

SCK

A6 A5 A4 A3 A2 A1 A0

R/W

D7 D6 D5 D4 D3 D2

D1

D7 D6 D5 D4 D3 D2 D1

D0

SDI

(ADDRESS) DATA

HI-Z

(ADDRESS + 1) DATA

HI-Z

SDO

FIGURE 6-3:

Device Write (SPI Mode 1,1 – Clock Idles High).

DS22192D-page 34

MCP3901

6.6

SPI MODE 0,0 – Clock Idle Low,

Read/Write Examples

In this SPI mode, the clock Idles low. For the MCP3901,

this means that there will be a rising edge before there

is a falling edge.

CS

Data Transitions on

the Falling Edge

MCU and MCP3901 Latch

Bits on the Rising Edge

SCK

A6

A5 A4 A3 A2 A1 A0 R/W

SDI

HI-Z

D6 D5 D4 D3 D2 D1 D0

D7

D7 OF (ADDRESS + 2) DATA

D7

D6 D5 D4 D3 D2 D1 D0

SDO

(ADDRESS) DATA

(ADDRESS + 1) DATA

FIGURE 6-4:

Device Read (SPI Mode 0,0 – Clock Idles Low).

CS

Data Transitions on

the Falling Edge

MCU and MCP3901 Latch

Bits on the Rising Edge

SCK

D7

A6

A5 A4 A3 A2 A1 A0 R/W

D7 OF (ADDRESS + 2) DATA

D7

D6 D5 D4 D3 D2 D1 D0

SDI

(ADDRESS) DATA

HI-Z

(ADDRESS + 1) DATA

HI-Z

SDO

FIGURE 6-5:

Device Write (SPI Mode 0,0 – Clock Idles Low).

DS22192D-page 35

MCP3901

The STATUS/COM register contains the loop settings

for the internal address counter (READ<1:0>). The

internal address counter can either stay constant

(READ<1:0> = 00) and continuously read the same

byte, or it can auto-increment and loop through the

register groups defined below (READ<1:0> = 01),

register types (READ<1:0> = 10) or the entire register

map (READ<1:0> = 11).

6.7

Continuous Communication,

Looping on Address Sets

If the user wishes to read back either of the ADC

channels continuously, or both channels continuously,

the internal address counter of the MCP3901 can be

set to loop on specific register sets. In this case, there

is only one control byte on SDI to start the

communication. The part stays within the same loop

until CS returns high.

Each channel is configured independently as either a

16-bit or 24-bit data word, depending on the setting of

the corresponding WIDTH bit in the CONFIG1 register.

This internal address counter allows the following

functionality:

For continuous reading, in the case of WIDTH = 0

(16-bit), the lower byte of the ADC data is not accessed

and the part jumps automatically to the following

address (the user does not have to clock out the lower

byte since it becomes undefined for WIDTH = 0).

• Read one ADC channel’s data continuously

• Read both ADC channel’s data continuously (both

ADC data can be independent or linked with

DRMODE settings)

• Continuously read the entire register map

• Continuously read each separate register

• Continuously read all Configuration registers

Figure 6-6 represents

a typical, continuous read

communication with the default settings (DRMODE<1:0>

= 00, READ<1:0> = 10) for both WIDTH settings. This

configuration is typically used for power metering

applications.

• Write all Configuration registers in one

communication (see Figure 6-7)

CS

SCK

CH0 ADC

ADDR/R

SDI

CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC

Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte

CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC

Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte

SDO

DR

These bytes are not present when WIDTH=0 (16-bit mode)

FIGURE 6-6:

Typical Continuous Read Communication.

DS22192D-page 36

MCP3901

The following register sets are defined as types:

6.7.1

CONTINUOUS WRITE

Both ADCs are powered up with their default

configurations, and begin to output DR pulses

immediately (RESET<1:0> and SHUTDOWN<1:0>

bits are off by default).

TABLE 6-2:

Type

REGISTER TYPES

Addresses

ADC DATA

0x00-0x05

The default output codes for both ADCs are all zeros.

The default modulator output for both ADCs is ‘0011’

(corresponding to a theoretical zero voltage at the

inputs). The default phase is zero between the two

channels.

(both channels)

CONFIGURATION

0x06-0x0B

6.8

Situations that Reset ADC Data

It is recommended to enter into ADC Reset mode for

both ADCs, just after power-up, because the desired

MCP3901 register configuration may not be the default

one, and in this case, the ADC would output undesired

data. Within the ADC Reset mode (RESET<1:0> = 11),

the user can configure the whole part with a single

communication. The write commands automatically

increment the address so that the user can start writing

the PHASE register and finish with the CONFIG2

register in only one communication (see Figure 6-7).

The RESET<1:0> bits are in the CONFIG2 register to

allow exiting the Soft Reset mode, and have the whole

part configured and ready to run in only one command.

Immediately after the following actions, the ADCs are

temporarily reset in order to provide proper operation:

1. Change in PHASE register.

2. Change in the OSR setting.

3. Change in the PRESCALE setting.

4. Overwrite of the same PHASE register value.

5. Change in the CLKEXT bit in the CONFIG2

register, modifying internal oscillator state.

After these temporary Resets, the ADCs go back to the

normal operation with no need for an additional

command. These are also the settings where the DR

position is affected. The PHASE register can be used

to serially Soft Reset the ADCs, without using the

RESET bits in the Configuration register, if the same

value is written in the PHASE register.

The following register sets are defined as groups:

TABLE 6-1:

Group

REGISTER GROUPS

Addresses

ADC DATA CH0

0x00-0x02

0x03-0x05

0x06-0x08

0x09-0x0B

ADC DATA CH1

MOD, PHASE, GAIN

CONFIG, STATUS

AV_DD

CS

SCK

SDI

00011000

11XXXXXX

00001110

xxxxxxxx

CONFIG2 ADDR/W CONFIG2

PHASE ADDR/W PHASE

GAIN

STATUS/COM CONFIG1

CONFIG2

Optional Reset of Both ADCs

One Command for Writing Complete Configuration

FIGURE 6-7:

Recommended Configuration Sequence at Power-up.

DS22192D-page 37

MCP3901

6.9

Data Ready Pin (DR)

6.10 Data Ready Latches and Data

Ready Modes (DRMODE<1:0>)

To signify when channel data is ready for transmission,

the data ready signal is available on the Data Ready pin

(DR) through an active-low pulse at the end of a

channel conversion.

To ensure that both channels’ ADC data is present at

the same time for SPI read, regardless of phase delay

settings for either or both channels, there are two sets

of latches in series with both the data ready and the

‘read start’ triggers.

The data ready pin outputs an active-low pulse with a

period that is equal to the DRCLK clock period, and

with a width equal to one DMCLK period.

The first set of latches holds each output when the data

is ready and latches both outputs together when

DRMODE<1:0> = 00. When this mode is on, both

ADCs work together and produce one set of available

data after each data ready pulse (that corresponds to

the lagging ADC data ready). The second set of latches

ensures that when reading starts on an ADC output, the

corresponding data is latched so that no data

corruption can occur.

When not active-low, this pin can either be in high-

impedance (when DR_HIZN = 0) or in a defined logic

high state (when DR_HIZN = 1). This is controlled

through the Configuration registers. This allows

multiple devices to share the same data ready pin (with

a pull-up resistor connected between DR and DV_DD) in

3-phase, energy meter designs to reduce pin count. A

single device on the bus does not require a pull-up

resistor.

If an ADC read has started, in order to read the

following ADC output, the current reading needs to be

completed (all bits must be read from the ADC Output

Data registers).

After a data ready pulse has occurred, the ADC output

data can be read through SPI communication. Two sets

of latches at the output of the ADC prevent the

communication from outputting corrupted data (see

Section 6.10 “Data Ready Latches and Data Ready

Modes (DRMODE<1:0>)”).

6.10.1

DATA READY PIN (DR) CONTROL

USING DRMODE BITS

There are four modes that control the data ready

pulses and these modes are set with the

DRMODE<1:0> bits in the STATUS/COM register. For

power metering applications, DRMODE<1:0> = 00 is

recommended (Default mode).

The CS pin has no effect on the DR pin, which means

even if CS is high, data ready pulses will be provided

(except when the configuration prevents them from

outputting data ready pulses). The DR pin can be used

as an interrupt when connected to an MCU or DSP.

While the RESET pin is low, the DR pin is not active.

DS22192D-page 38

MCP3901

The position of the DR pulses vary, with respect to this

mode, to the OSR and to the PHASE settings:

6.10.2

DR PULSES WITH SHUTDOWN OR

RESET CONDITIONS

• DRMODE<1:0> = 11: Both data ready pulses

from ADC Channel 0 and ADC Channel 1 are

output on the DR pin.

There will be no DR pulses if DRMODE<1:0> = 00

when either one or both of the ADCs are in Reset or

shutdown. In Mode 0,0, a DR pulse only happens when

both ADCs are ready. Any DR pulse will correspond to

one data on both ADCs. The two ADCs are linked

together and act as if there was only one channel with

the combined data of both ADCs. This mode is very

practical when both ADC channels’ data retrieval and

processing need to be synchronized, as in power

metering applications.

• DRMODE<1:0> = 10: Data ready pulses from

ADC Channel 1 are output on the DR pin. The DR

from ADC Channel 0 is not present on the pin.

• DRMODE<1:0> = 01: Data ready pulses from

ADC Channel 0 are output on the DR pin. The DR

from ADC Channel 1 is not present on the pin.

• DRMODE<1:0> = 00 (Recommended and

Default mode): Data ready pulses from the

lagging ADC between the two are output on the

DR pin. The lagging ADC depends on the PHASE

register and on the OSR. In this mode, the two

ADCs are linked together so their data is latched

together when the lagging ADC output is ready.

Note:

If DRMODE<1:0> = 11, the user will still

be able to retrieve the DR pulse for the

ADC not in shutdown or Reset (i.e., only

1 ADC channel needs to be awake).

Figure 6-8 represents the behavior of the data ready

pin with the different DRMODE and DR_LTY

configurations, while shutdown or Resets are applied.

DS22192D-page 39

MCP3901

PHASE < 0

PHASE = 0

PHASE > 0

FIGURE 6-8:

Data Ready Behavior.

DS22192D-page 40

MCP3901

7.0

INTERNAL REGISTERS

The addresses associated with the internal registers

are listed below. A detailed description of the registers

follows. All registers are 8-bit long and can be

addressed separately. Read modes define the groups

and types of registers for continuous read

communication or looping on address sets.

.

TABLE 7-1:

Address

REGISTER MAP

Name

Bits R/W

Description

0x00

0x03

0x06

0x07

0x08

0x09

0x0A

0x0B

DATA_CH0

DATA_CH1

MOD

24

8

R

Channel 0 ADC Data <23:0>, MSB First

Channel 1 ADC Data <23:0>, MSB First

R/W Delta-Sigma Modulators Output Register

R/W Phase Delay Configuration Register

R/W Gain Configuration Register

R/W Status/Communication Register

R/W Configuration Register 1

PHASE

8

GAIN

8

STATUS/COM

CONFIG1

CONFIG2

8

R/W Configuration Register 2

TABLE 7-2:

REGISTER MAP GROUPING

FOR CONTINUOUS READ

MODES

READ<1:0>

Function Address

= 01

= 10

= 11

0x00

DATA_CH0

DATA_CH1

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

MOD

PHASE

GAIN

STATUS/

COM

CONFIG1

CONFIG2

0x0A

0x0B

DS22192D-page 41

MCP3901

ADC read communication occurs. When a data ready

event occurs during a read communication, the most

current ADC data is also latched to avoid data

corruption issues. The three bytes of each channel are

updated synchronously at a DRCLK rate. The three

bytes can be accessed separately, if needed, but are

refreshed synchronously.

7.1

ADC Channel Data Output

Registers

The ADC Channel Data Output registers always

contain the most recent A/D conversion data for each

channel. These registers are read-only. They can be

accessed independently or linked together (with

READ<1:0> bits). These registers are latched when an

REGISTER 7-1:

CHANNEL OUTPUT REGISTERS: ADDRESS 0x00-0x02: CH0; 0x03-0x05; CH1

R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA_CHn DATA_CHn DATA_CHn DATA_CHn DATA_CHn DATA_CHn DATA_CHn

R-0

DATA_CHn

<23>

<22>

<21>

<20>

<19>

<18>

<17>

<16>

bit 23

bit 16

R-0

DATA_CHn

<15>

DATA_CHn DATA_CHn DATA_CHn DATA_CHn DATA_CHn

DATA_CHn DATA_CHn

<14>

<13>

<12>

<11>

<10>

<9>

<8>

bit 15

bit 8

R-0

DATA_CHn

<7>

DATA_CHn DATA_CHn DATA_CHn DATA_CHn DATA_CHn

DATA_CHn DATA_CHn

<1> <0>

<6>

<5>

<4>

<3>

<2>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 23-0

DATA_CHn<23:0>

DS22192D-page 42

MCP3901

This register should be used as a read-only register.

(Note 1).

7.2

Modulator Output Register

The MOD register contains the most recent modulator

data output. The default value corresponds to an

equivalent input of 0V on both ADCs. Each bit in this

register corresponds to one comparator output on one

of the channels.

This register is updated at the refresh rate of DMCLK

(typically, 1 MHz with MCLK = 4 MHz).

See Section 5.4 “Modulator Output Block” for more

details.

.

REGISTER 7-2:

MODULATOR OUTPUT REGISTER (MOD): ADDRESS 0x06

R/W-0 R/W-1 R/W-1 R/W-0 R/W-0

R/W-0

R/W-1

COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

COMPn_CH1: Comparator Outputs from Channel 1 Modulator bits

COMPn_CH0: Comparator Outputs from Channel 0 Modulator bits

Note 1: This register can be written in order to overwrite modulator output data, but any writing here will corrupt the

ADC_DATA on the next three data ready pulses.

DS22192D-page 43

MCP3901

7.3.1

PHASE RESOLUTION FROM OSR

7.3

PHASE Register

The timing resolution of the phase delay is 1/DMCLK,

or 1 µs, in the default configuration (MCLK = 4 MHz).

The PHASE register coding depends on the OSR

setting:

The PHASE register (PHASE<7:0>) is a 7 bits + sign,

MSB first, two’s complement register that indicates how

much phase delay there should be between Channel 0

and Channel 1.

• OSR = 256: The delay can go from -128 to +127.

PHASE<7> is the sign bit. Phase<6> is the MSB

and PHASE<0> the LSB.

The reference channel for the delay is Channel 1,

which typically, is the voltage channel when used in

energy metering applications (i.e., when PHASE regis-

ter code is positive, Channel 0 is lagging Channel 1).

• OSR = 128: The delay can go from -64 to +63.

PHASE<6> is the sign bit. Phase<5> is the MSB

and PHASE<0> the LSB.

When PHASE register code is negative, Channel 0 is

leading versus Channel 1.

• OSR = 64: The delay can go from -32 to +31.

PHASE<5> is the sign bit. Phase<4> is the MSB

and PHASE<0> the LSB.

The delay is given by the following formula:

EQUATION 7-1:

• OSR = 32: The delay can go from -16 to +15.

PHASE<4> is the sign bit. Phase<3> is the MSB

and PHASE<0> the LSB.

Phase Register Code

Delay = -------------------------------------------------

DMCLK

REGISTER 7-3:

PHASE REGISTER (PHASE): ADDRESS 0x07

R/W-0 R/W-0 R/W-0 R/W-0

PHASE<6> PHASE<5> PHASE<4> PHASE<3> PHASE<2>

R/W-0

PHASE<7>

bit 7

PHASE<1> PHASE<0>

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

PHASE<7:0>: CH0 Relative to CH1 Phase Delay bits

Delay = PHASE Register’s two’s complement code/DMCLK (Default PHASE = 0).

DS22192D-page 44

MCP3901

7.4

Gain Configuration Register

This register contains the settings for the PGA gains for

each channel as well as the BOOST options for each

channel.

REGISTER 7-4:

GAIN CONFIGURATION REGISTER (GAIN): ADDRESS 0x08

R/W-0

PGA_CH1

<2>

PGA_CH1

<1>

PGA_CH1

<0>

BOOST_

CH1

BOOST_

CH0

PGA_CH0

<2>

PGA_CH0

<1>

PGA_CH0

<0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

PGA_CH1<2:0>: PGA Setting for Channel 1 bits

111= Reserved (Gain = 1)

110= Reserved (Gain = 1)

101= Gain is 32

100= Gain is 16

011= Gain is 8

010= Gain is 4

001= Gain is 2

000= Gain is 1

bit 4-3

bit 2-0

BOOST_CH<1:0> Current Scaling for High-Speed Operation bits

11= Both channels have current x 2

10= Channel 1 has current x 2

01= Channel 0 has current x 2

00= Neither channel has current x 2

PGA_CH0<2:0>: PGA Setting for Channel 0 bits

111= Reserved (Gain = 1)

110= Reserved (Gain = 1)

101= Gain is 32

100= Gain is 16

011= Gain is 8

010= Gain is 4

001= Gain is 2

000= Gain is 1

DS22192D-page 45

MCP3901

This mode is very useful for power metering

applications because the data from both ADCs can be

retrieved, using this single data ready event, and

processed synchronously even in case of a large

phase difference. This mode works as if there was one

ADC channel and its data would be 48 bits long and

contain both channel data. As a consequence, if one

channel is in Reset or shutdown when DRMODE = 00,

no data ready pulse will be present at the outputs (if

both channels are not ready in this mode, the data is

not considered ready).

7.5

Status and Communication

Register

This register contains all settings related to the

communication, including data ready settings and

status, and Read mode settings.

7.5.1

DATA READY (DR) LATENCY

CONTROL – DR_LTY

This bit determines if the first data ready pulses

correspond to settled data or unsettled data from each

SINC³filter. Unsettled data will provide DR pulses

every DRCLK period. If this bit is set, unsettled data will

wait for 3 DRCLK periods before giving DR pulses and

will then give DR pulses every DRCLK period.

See Section 6.9 “Data Ready Pin (DR)” for more

details about data ready pin behavior.

7.5.4

DR STATUS FLAG –

DRSTATUS<1:0>

7.5.2

DATA READY (DR) PIN HIGH Z –

DR_HIZN

These bits indicate the DR status of both channels,

respectively. These flags are set to logic high after each

read of the STATUS/COM register. These bits are

cleared when a DR event has happened on its

respective ADC channel. Writing these bits has no

effect.

This bit defines the non-active state of the data ready

pin (logic 1 or high-impedance). Using this bit, the user

can connect multiple chips with the same DR pin with a

pull-up resistor (DR_HIZN = 0) or a single chip with no

external component (DR_HIZN = 1).

Note:

These bits are useful if multiple devices

share the same DR output pin

(DR_HIZN = 0), in order to understand

what DR event happened. This configura-

tion can be used for three-phase power

metering systems, where all three phases

share the same data ready pin. In case

the DRMODE = 00 (linked ADCs), these

data ready status bits will be updated syn-

chronously upon the same event (lagging

ADC is ready). These bits are also useful

in systems where the DR pin is not used

to save MCU I/O.

7.5.3

DATA READY MODE –

DRMODE<1:0>

If one of the channels is in Reset or shutdown, only one

of the data ready pulses is present and the situation is

similar to DRMODE = 01or 10. In the ‘01’, ‘10’ and ‘11’

modes, the ADC channel data to be read is latched at

the beginning of a reading in order to prevent the case

of erroneous data when a DR pulse happens during a

read. In these modes, the two channels are

independent.

When these bits are equal to ‘11’,’10’ or ‘01’, they

control which ADC’s data ready is present on the DR

pin. When DRMODE = 00, the data ready pin output is

synchronized with the lagging ADC channel (defined by

the PHASE register) and the ADCs are linked together.

In this mode, the output of the two ADCs is latched

synchronously at the moment of the DR event. This

prevents bad synchronization between the two ADCs.

The output is also latched at the beginning of a reading

in order not to be updated during a read and not to give

erroneous data.

DS22192D-page 46

MCP3901

REGISTER 7-5:

R/W-1 R/W-0

READ<1> READ<0> DR_LTY DR_HIZN DRMODE<1> DRMODE<0> DRSTATUS_CH1 DRSTATUS_CH0

STATUS AND COMMUNICATION REGISTER: ADDRESS 0x09

R/W-1 R/W-0 R/W-0 R/W-0 R-1

R-1

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

READ<1:0>: Address Loop Setting bits

11= Address counter loops on entire register map

10= Address counter loops on register types (default)

01= Address counter loops on register groups

00= Address not incremented, continually read same single register

bit 5

DR_LTY: Data Ready Latency Control bit

1= “No Latency” Conversion, DR pulses after 3 DRCLK periods (default)

0= Unsettled Data is available after every DRCLK period

bit 4

DR_HIZN: Data Ready Pin Inactive State Control bit

1= The data ready pin default state is a logic high when data is NOT ready

0= The data ready pin default state is high-impedance when data is NOT ready (default)

bit 3-2

DRMODE<1:0>: Data Ready Pin (DR) Control bits

11= Both Data Ready pulses from ADC0 and ADC Channel 1 are output on the DR pin.

10= Data Ready pulses from ADC Channel 1 are output on the DR pin. DR from ADC Channel 0 are not

present on the pin.

01= Data Ready pulses from ADC Channel 0 are output on the DR pin. DR from ADC Channel 1 are not

present on the pin.

00= Data Ready pulses from the lagging ADC between the two are output on the DR pin. The lagging

ADC selection depends on the PHASE register and on the OSR (default).

bit 1-0

DRSTATUS_CH<1:0>: Data Ready Status bits

11= ADC Channel 1 and Channel 0 data is not ready (default)

10= ADC Channel 1 data is not ready, ADC Channel 0 data is ready

01= ADC Channel 0 data is not ready, ADC Channel 1 data is ready

00= ADC Channel 1 and Channel 0 data is ready

DS22192D-page 47

MCP3901

24 bits, the modulator output control settings, the state

of the channel Resets and shutdowns, the dithering

algorithm control (for Idle tones suppression), and the

control bits for the external VREF and external CLK.

7.6

Configuration Registers

The Configuration registers contain settings for the

internal clock prescaler, the oversampling ratio, the

Channel 0 and Channel 1 width settings of 16 or

REGISTER 7-6:

CONFIGURATION REGISTERS:

CONFIG1: ADDRESS 0x0A, CONFIG2: ADDRESS 0x0B

R/W-0

R/W-1

R/W-0

PRESCALE PRESCALE

OSR<1>

OSR<0>

WIDTH

_CH1

WIDTH

_CH0

MODOUT

_CH1

MODOUT

_CH0

<1>

<0>

bit 15

bit 8

R/W-0

R/W-1

R/W-0

RESET

_CH1

RESET

_CH0

SHUTDOWN SHUTDOWN

DITHER

_CH1

DITHER

_CH0

VREFEXT

CLKEXT

_CH1

_CH0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-12

PRESCALE<1:0>: Internal Master Clock (AMCLK) Prescaler Value bits

11= AMCLK = MCLK/8

10= AMCLK = MCLK/4

01= AMCLK = MCLK/2

00= AMCLK = MCLK (default)

OSR<1:0>: Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, DMCLK/DRCLK)

11= 256

10= 128

01= 64 (default)

00= 32

bit 11-10

bit 9-8

WIDTH_CH<1:0>: ADC Channel Output Data Word Width bits

1= 24-bit mode

0= 16-bit mode (default)

MODOUT_CH<1:0>: Modulator Output Setting for MDAT Pins bits

11 = Both CH0 and CH1 modulator outputs present on MDAT1 and MDAT0 pins

10 = CH1 ADC modulator output present on MDAT1 pin

01 = CH0 ADC modulator output present on MDAT0 pin

00 = No modulator output is enabled (default)

bit 7-6

bit 5-4

bit 3-2

RESET_CH<1:0>: Reset Mode Setting for ADCs bits

11= Both CH0 and CH1 ADC are in Reset mode

10= CH1 ADC in Reset mode

01= CH0 ADC in Reset mode

00= Neither Channel in Reset mode (default)

SHUTDOWN_CH<1:0>: Shutdown Mode Setting for ADCs bits

11= Both CH0 and CH1 ADC are in Shutdown

10= CH1ADC is in shutdown

01= CH0 ADC is in shutdown

00= Neither Channel is in shutdown (default)

DITHER_CH<1:0>: Control for Dithering Circuit bits

11= Both CH0 and CH1 ADC have dithering circuit applied (default)

10= Only CH1 ADC has dithering circuit applied

01= Only CH0 ADC has dithering circuit applied

00= Neither Channel has dithering circuit applied

DS22192D-page 48

MCP3901

REGISTER 7-6:

CONFIGURATION REGISTERS:

CONFIG1: ADDRESS 0x0A, CONFIG2: ADDRESS 0x0B (CONTINUED)

bit 1

VREFEXT: Internal Voltage Reference Shutdown Control bit

1= Internal voltage reference disabled, an external voltage reference must be placed between

REFIN+/OUT and REFIN-

0= Internal voltage reference enabled (default)

bit 0

CLKEXT: Clock Mode bit

1= External Clock mode (internal oscillator disabled and bypassed – lower power)

0= XT mode – A crystal must be placed between OSC1/OSC2 (default)

DS22192D-page 49

MCP3901

NOTES:

DS22192D-page 50

MCP3901

8.0

8.1

PACKAGING INFORMATION

Package Marking Information

20-Lead SSOP (SS)

Example:

XXXXXXXX

YYWWNNN

MCP3901A0

E/SS^

e

^

3

I/SS^^

e3

1049256

20-Lead QFN

Examples:

XXXXXXX

39010

I/ML

39010

E/ML

e

3

e

3

1049256

YYWWNNN

1049256

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22192D-page 51

MCP3901

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DS22192D-page 52

MCP3901

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22192D-page 53

MCP3901

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DS22192D-page 54

MCP3901

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DS22192D-page 55

MCP3901

NOTES:

DS22192D-page 56

MCP3901

APPENDIX A: REVISION HISTORY

Revision D (April 2011)

The following is the list of modifications:

1. Added the 20-lead QFN package and related

information throughout the document.

2. Added the E Temperature package option.

Revision C (August 2010)

The following is the list of modifications:

1. Corrected symbols inside the Functional Block

Diagram figure.

2. Typographical revisions throughout document.

Revision B (November 2009)

The following is the list of modifications:

1. Removed the QFN package and all references

to it.

Revision A (September 2009)

• Original Release of this Document.

DS22192D-page 57

MCP3901

NOTES:

DS22192D-page 58

MCP3901

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

XX

X

/XX

Examples:

a)

MCP3901A0-I/SS:

Two-Channel ΔΣ A/D

Converter,

SSOP-20 package,

Address Option = A0

Industrial Temperature

Range

Address

Options

Tape and Temperature Package

Reel

Range

Device:

MCP3901: Two-Channel ΔΣ A/D Converter

b)

MCP3901A0T-I/SS: Tape and Reel,

Two-Channel ΔΣ A/D

Converter,

Address Options:

XX

A0*

A1

A6

0

A5

0

SSOP-20 package,

Address Option = A0

Industrial Temperature

Range

Two-Channel ΔΣ A/D

Converter,

SSOP-20 package,

Address Option = A1

Industrial Temperature

Range

=

0

1

A2

1

0

c)

d)

MCP3901A1-I/SS:

A3

1

* Default option. Contact Microchip factory for other

address options

MCP3901A1T-I/SS: Tape and Reel,

Tape and Reel:

T

=

Tape and Reel

Two-Channel ΔΣ A/D

Converter,

SSOP-20 package,

Address Option = A1

Industrial Temperature

Range

Temperature Range:

I

=

-40°C to +85°C

-40°C to +125°C

E

e)

MCP3901A0-E/ML:

Two-Channel ΔΣ A/D

Converter,

QFN-20 package,

Address Option = A0

Extended Temperature

Range.

Package:

SS

ML

=

Plastic Shrink Small Outline (SSOP), 20-lead

Plastic Quad Flat No-lead (4x4 QFN), 20-lead

DS22192D-page 59

MCP3901

NOTES:

DS22192D-page 60

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-078-3

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22192D-page 61

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Fax: 886-7-330-9305

Los Angeles

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Toronto

Mississauga, Ontario,

Canada

China - Zhuhai

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-756-3210040

Fax: 86-756-3210049

02/18/11

DS22192D-page 62


型号：	MCP3901
厂家：	MICROCHIP
描述：	Two-Channel Analog Front End Portable Instrumentation 双通道模拟前端便携式仪表仪表便携式
文件：	总62页 (文件大小：1790K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP3901 [MICROCHIP]

相关型号：

MCP3901A0-E/ML

MCP3901A0-E/SS

MCP3901A0-I/ML

MCP3901A0-I/SS

MCP3901A0T-I/ML

MCP3901A0T-I/SS

MCP3901A1-I/ML

MCP3901A1-I/SS

MCP3901A1T-I/ML

MCP3901A1T-I/SS

MCP3901A2-I/ML

MCP3901A2-I/SS