MCP39F521-E/MQ [MICROCHIP]
I2C Power Monitor with Calculation and Energy Accumulation;型号: | MCP39F521-E/MQ |
厂家: | MICROCHIP |
描述: | I2C Power Monitor with Calculation and Energy Accumulation |
文件: | 总52页 (文件大小:1001K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MCP39F521
2
I C Power Monitor with Calculation and Energy Accumulation
Features
Description
• Power Monitoring Accuracy Capable of 0.1%
Error Across 4000:1 Dynamic Range
The MCP39F521 is a highly integrated, complete
single-phase power-monitoring device, designed for
real-time measurement of input power for AC/DC
power supplies, power distribution units, consumer and
industrial applications. It includes dual-channel
• Built-In Calculations on Fast 16-bit Processing
Core
- Active, Reactive, Apparent Power
delta-sigma ADCs,
a 16-bit calculation engine,
- True Root Mean Square (RMS) Current,
RMS Voltage
EEPROM and a flexible two-wire I2C interface.
An integrated low-drift voltage reference with
10 ppm/°C in addition to 94.5 dB of signal-to-noise and
distortion ratio (SINAD) performance on each
measurement channel allows for better than 0.1%
accurate designs across a 4000:1 dynamic range.
- Line Frequency, Power Factor
• 64-bit Wide Import and Export Active Energy
Accumulation Registers
• 64-bit Four Quadrant Reactive Energy
Accumulation Registers
Package Types
• Signed Active and Reactive Power Outputs
MCP39F521
5x5 QFN*
• Dedicated Zero Crossing Detection (ZCD) Pin
Output with Less than 100 µs Latency
• Automatic Event Pin Control through Fast Voltage
Surge Detection, Less than 5 ms Delay
• I2C Interface, up to 400 kHz Clock Rate
• Two Independent Registers for Minimum and
Maximum Output Quantity Tracking
28 27 26 25 24 23 22
• Fast Calibration Routines and Simplified
Command Protocol
A
1
2
3
4
EVENT
NC
21
GND
20 AN_IN
19 V1+
• 512 Bytes User-Accessible EEPROM through
Page Read/Write Commands
NC
EP
29
COMMON
18
V1-
B
• Low-Drift Internal Voltage Reference,
10 ppm/°C Typical
COMMON
5
6
7
A
17 I1-
I1+
A1
16
15
OSCI
• 28-lead 5 x 5 mm QFN Package
OSCO
• Extended Temperature Range -40°C to +125°C
8
9 10 11 12 13 14
Applications
• Power Monitoring for Home Automation
• Industrial Lighting Power Monitoring
• Real-Time Measurement of Input Power for
AC/DC Supplies
*Includes Exposed Thermal Pad (EP); see Table 3-1.
• Intelligent Power Distribution Units
2015 Microchip Technology Inc.
DS20005442A-page 1
MCP39F521
Functional Block Diagram
A
AV
D
DV
DD
GND
DD
GND
Timing
OSCI
Generation
A1
A0
OSCO
Internal
Oscillator
2
I C
Serial
Interface
SCL
SDA
24-bit Delta-Sigma
Multi-Level
Modulator ADC
I1+
I1-
+
-
PGA
16-BIT
CORE
FLASH
24-bit Delta-Sigma
Multi-Level
Modulator ADC
V1+
V1-
+
-
PGA
EVENT
ZCD
Calculation
Engine
(CE)
Digital Outputs
10-bit SAR
ADC
AN_IN
DS20005442A-page 2
2015 Microchip Technology Inc.
MCP39F521
MCP39F521 Typical Application – Single-Phase, Two-Wire Application Schematic
+3.3V
10
0.1 µF
1 µF
LOAD
0.1 µF
AV
DV
RESET
DD
DD
1 k
REFIN/OUT+
I1+
0.1 µF
+
-
33 nF
2 m
1 k
A1
A0
To DV or GND, do not float
DD
I1-
33 nF
To DV or GND,
do not float
DD
MCP39F521
3.3 DV
1 k
DD
V1-
V1+
33 nF
2 k
SCL
SDA
499 k
499 k
1 k
to MCU SCL
3.3 DV
DD
2 k
33 nF
NC
NC
NC
NC
DR
to MCU SDA
N.C.
Leave Floating
(OPTIONAL)
Connect on PCB
COMMON
A,B
+3.3V
EVENT
ZCD
AN_IN
MCP9700A
OSCO
D
4 MHz
A
GND
GND
OSCI
22 pF
22 pF
(OPTIONAL)
+3.3V
0.47µF
470
MCP1754
0.01 µF
470 µF
N
L
A
GND
D
GND
Note:
The external sensing components shown here, a 2 mΩ shunt, two 499 kΩ and 1 kΩ resistors for the
1000:1 voltage divider, are specifically chosen to match the default values for the calibration registers
defined in Section 6.0, Register Descriptions. By choosing low-tolerance components of these
values (e.g. 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero
calibration. See Section 8.0, MCP39F521 Calibration for more information.
2015 Microchip Technology Inc.
DS20005442A-page 3
MCP39F521
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operation listings of this specification is
not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
DV .................................................................. -0.3 to +4.5V
DD
AV .................................................................. -0.3 to +4.0V
DD
Digital inputs and outputs w.r.t. A
...............-0.3V to +4.0V
GND
Analog Inputs (I+,I-,V+,V-) w.r.t. A
...................-2V to +2V
GND
V
input w.r.t. A
........................ ....-0.6V to AV +0.6V
REF
GND DD
Maximum Current out of D
pin..............................300 mA
GND
Maximum Current into DV pin.................................250 mA
DD
Maximum Output Current Sunk by Digital IO................25 mA
Maximum Current Sourced by Digital IO.......................25 mA
Storage temperature .....................................-65°C to +150°C
Ambient temperature with power applied......-40°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD on the analog inputs (HBM,MM).................4.0 kV, 200V
ESD on all other pins (HBM,MM)........................4.0 kV, 200V
1.1
Specifications
ELECTRICAL CHARACTERISTICS
TABLE 1-1:
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C
to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Power Measurement
Active Power (Note 1)
P
Q
—
—
—
—
—
±0.1
±0.1
±0.1
±0.1
±0.1
—
—
—
—
—
%
%
%
%
%
4000:1 Dynamic Range on
Current Channel (Note 2)
Reactive Power (Note 1)
Apparent Power (Note 1)
Current RMS (Note 1)
Voltage RMS (Note 1)
4000:1 Dynamic Range on
Current Channel (Note 2)
S
4000:1 Dynamic Range on
Current Channel (Note 2)
IRMS
VRMS
4000:1 Dynamic Range on
Current Channel (Note 2)
4000:1 Dynamic Range on
Voltage Channel (Note 2)
Power Factor (Note 1)
Line Frequency (Note 1)
—
—
±0.1
±0.1
—
—
%
%
LF
Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 4 line cycles.
2: Specification by design and characterization; not production tested.
3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or
TCAL = 80 ms for 50 Hz line.
4: Applies to Voltage Sag and Voltage Surge events only.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical
Performance Curves for typical performance.
6:
VIN = 1VPP = 353 mVRMS @ 50/60 Hz.
7: Variation applies to internal clock and I2C only. All calculated output quantities are temperature
compensated to the performance listed in the respective specification.
DS20005442A-page 4
2015 Microchip Technology Inc.
MCP39F521
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C
to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Calibration, Calculation and Event Detection Times
2N x (1/fLINE
see
)
Auto-Calibration Time
tCAL
—
—
—
—
ms
ms
Note 3
Note 4
Minimum Time
for Voltage Surge/Sag
Detection
tAC_SASU
Section 7.0
24-Bit Delta-Sigma ADC Performance
Analog Input
Absolute Voltage
VIN
-1
—
1
+1
—
V
Analog Input
Leakage Current
AIN
—
nA
mV
Differential Input
Voltage Range
(I1+ – I1-), -600/GAIN
(V1+ – V1-)
—
+600/GAIN
VREF = 1.2V,
proportional to VREF
Offset Error
VOS
GE
ZIN
-1
—
—
0.5
—
+1
—
+4
—
—
—
—
—
—
—
—
mV
µV/°C
%
Offset Error Drift
Gain Error
-4
Note 5
Gain Error Drift
—
1
ppm/°C
k
Differential Input
Impedance
232
142
72
38
36
33
92
—
G = 1
G = 2
G = 4
G = 8
G = 16
G = 32
Note 6
—
k
—
k
—
k
—
k
—
k
Signal-to-Noise
SINAD
94.5
dB
and Distortion Ratio
Total Harmonic Distortion
Signal-to-Noise Ratio
THD
SNR
—
92
—
-106.5
95
-103
—
dBc
dB
Note 6
Note 6
Note 6
Spurious Free
SFDR
111
—
dB
Dynamic Range
Crosstalk
CTALK
—
—
-122
-73
—
—
dB
dB
AC Power
AC PSRR
AVDD and
Supply Rejection Ratio
DVDD = 3.3V + 0.6VPP
,
100 Hz, 120 Hz, 1 kHz
DC Power
Supply Rejection Ratio
DC PSRR
DC CMRR
—
—
-73
—
—
dB
dB
AVDD and DVDD = 3 to
3.6V
DC Common
-105
V
CM varies
Mode Rejection Ratio
from -1V to +1V
Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 4 line cycles.
2: Specification by design and characterization; not production tested.
3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or
TCAL = 80 ms for 50 Hz line.
4: Applies to Voltage Sag and Voltage Surge events only.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical
Performance Curves for typical performance.
6: VIN = 1VPP = 353 mVRMS @ 50/60 Hz.
7: Variation applies to internal clock and I2C only. All calculated output quantities are temperature
compensated to the performance listed in the respective specification.
2015 Microchip Technology Inc.
DS20005442A-page 5
MCP39F521
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C
to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
10-Bit SAR ADC Performance for Temperature Measurement
Resolution
NR
VIN
RIN
—
DGND - 0.3
—
10
—
—
—
DVDD + 0.3
2.5
bits
V
Absolute Input Voltage
Recommended
k
Impedance of
Analog Voltage Source
Integral Nonlinearity
Differential Nonlinearity
Gain Error
INL
—
—
—
—
—
±1
±1
±2
±1.5
±3
LSb
LSb
LSb
LSb
sps
DNL
GERR
EOFF
±1
Offset Error
±1
fLINE/2N
±2
Temperature
—
Note 3
Measurement Rate
Clock and Timings
I2C Clock Frequency
fSCL
—
-2%
—
—
4
400
+2%
15
kHz 100 kHz and 400 kHz
I2C modes supported
Master Clock
and Crystal Frequency
fMCLK
MHz
Capacitive Loading
on OSCO pin
COSC2
fINT_OSC
—
2
pF
%
When an external clock is
used to drive the device
Internal Oscillator
Tolerance
—
—
-40 to +85°C only (Note 7)
Internal Voltage Reference
Internal Voltage
Reference Tolerance
VREF
-2%
—
1.2
10
+2%
—
V
Temperature Coefficient
TCVREF
ppm/°C TA = -40°C to +85°C,
VREFEXT = 0
Output Impedance
Current, VREF
ZOUTVREF
AIDDVREF
—
—
2
—
—
k
40
µA
Voltage Reference Input
Input Capacitance
—
—
—
10
pF
V
A
+ 1.1V
A
+ 1.3V
Absolute Voltage on
VREF+ Pin
VREF+
GND
GND
Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 4 line cycles.
2: Specification by design and characterization; not production tested.
3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or
TCAL = 80 ms for 50 Hz line.
4: Applies to Voltage Sag and Voltage Surge events only.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical
Performance Curves for typical performance.
6:
VIN = 1VPP = 353 mVRMS @ 50/60 Hz.
7: Variation applies to internal clock and I2C only. All calculated output quantities are temperature
compensated to the performance listed in the respective specification.
DS20005442A-page 6
2015 Microchip Technology Inc.
MCP39F521
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C
to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Power Specifications
Operating Voltage
AVDD
DVDD
,
2.7
—
—
3.6
0.7
V
V
DVDD Start Voltage
to Ensure Internal
Power-On Reset Signal
VPOR
SDVDD
VPOR
SAVDD
IDD
DGND
DVDD Rise Rate to
Ensure Internal
Power-On Reset Signal
0.05
AGND
0.042
—
—
—
—
13
—
2.1
—
V/ms 0 – 3.3V in 0.1s,
0 – 2.5V in 60 ms
AVDD Start Voltage to
Ensure Internal
Power-On Reset Signal
V
AVDD Rise Rate to
Ensure Internal Power
On Reset Signal
V/ms 0 – 2.4V in 50 ms
Operating Current
Data EEPROM Memory
Cell Endurance
—
mA
EPS
TIWD
100,000
—
—
4
—
—
E/W
ms
Self-Timed
Write Cycle Time
10,000,000
Number of Total
Write/Erase Cycles
Before Refresh
RREF
—
—
E/W
Characteristic Retention
TRETDD
IDDPD
40
—
—
7
—
—
Years Provided no other
specifications are violated
Supply Current during
Programming
mA
Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 4 line cycles.
2: Specification by design and characterization; not production tested.
3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or
TCAL = 80 ms for 50 Hz line.
4: Applies to Voltage Sag and Voltage Surge events only.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical
Performance Curves for typical performance.
6: VIN = 1VPP = 353 mVRMS @ 50/60 Hz.
7: Variation applies to internal clock and I2C only. All calculated output quantities are temperature
compensated to the performance listed in the respective specification.
2015 Microchip Technology Inc.
DS20005442A-page 7
MCP39F521
TABLE 1-2:
SERIAL DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V,
TA = -40°C to +125°C, MCLK = 4 MHz
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
VIH
VIL
0.8 DVDD
—
—
DVDD
0.2 DVDD
—
V
V
0
VOH
VOL
ILI
3
—
V
IOH = -3.0 mA, VDD = 3.6V
IOL = 4.0 mA, VDD = 3.6V
—
—
—
—
0.4
V
—
1
µA
µA
0.050
0.100
Digital Output pins only
(ZCD, EVENT)
TABLE 1-3:
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Operating Temperature Range
Storage Temperature Range
TA
TA
-40
-65
—
—
+125
+150
°C
°C
Thermal Package Resistances
Thermal Resistance, 28LD 5x5 QFN
JA
—
36.9
—
°C/W
DS20005442A-page 8
2015 Microchip Technology Inc.
MCP39F521
2.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz.
0.50%
0.40%
0.30%
0.20%
0.10%
0.00%
-0.10%
-0.20%
-0.30%
-0.40%
-0.50%
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
fIN = -60 dBFS @ 60 Hz
f
D = 3.9 ksps
16384 pt FFT
OSR = 256
0.01
0.1
1
10
100
1000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
Current Channel Input Amplitude (mVPEAK
)
FIGURE 2-1:
Active Power, Gain = 1.
FIGURE 2-4:
Spectral Response.
0.100%
0.050%
0.000%
-0.050%
-0.100%
0.1
1
10
100
1000
Input Voltage RMS (mVPP
)
Total Harmonic Distortion (-dBc)
FIGURE 2-2:
RMS Current, Gain = 1.
FIGURE 2-5:
THD Histogram.
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
0
-10
G = 1
G = 8
G = 2
G = 4
G = 16
G = 32
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-1
-50
-25
0
25
50
75
100 125 150
1
10
100
1000
10000 100000
Temperature (°C)
Energy Accumulation (Watt-Hours)
FIGURE 2-3:
Energy, Gain = 8.
FIGURE 2-6:
THD vs. Temperature.
2015 Microchip Technology Inc.
DS20005442A-page 9
MCP39F521
Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz.
1.2008
1.2007
1.2006
1.2005
1.2004
1.2003
1.2002
1.2001
1.2000
1.1999
94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5
Signal-to-Noise and Distortion Ratio (dB)
-50
0
50
100
150
Temperature (C)
FIGURE 2-7:
SNR Histogram.
FIGURE 2-10:
Internal Voltage Reference
vs. Temperature.
100
90
80
70
60
50
40
30
20
10
0
G = 1
G = 8
G = 2
G = 4
G = 16
G = 32
-50 -25
0
25
50
75 100 125 150
Temperature (°C)
FIGURE 2-8:
SINAD vs. Temperature.
5
4
3
2
1
0
-1
-2
-3
-4
G = 1
G = 2
G = 4
G = 8
G = 16
G = 32
-5
-50 -25
0
25
50
75
100 125 150
Temperature (°C)
FIGURE 2-9:
Gain Error vs. Temperature.
DS20005442A-page 10
2015 Microchip Technology Inc.
MCP39F521
3.0
PIN DESCRIPTION
The description of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Symbol
MCP39F521
5x5 QFN
Function
1
EVENT
NC
Event Output Pin
No Connect (must be left floating)
2, 3, 8, 9
4
5
6
7
COMMONB
COMMONA
OSCI
Common pin B, to be connected to COMMONA
Common pin A, to be connected to COMMONB
Oscillator Crystal Connection Pin or External Clock Input Pin
Oscillator Crystal Connection Pin
OSCO
10
11
RESET
AVDD
A0
Reset Pin for Delta Sigma ADCs
Analog Power Supply Pin
I2C Address Select Pin A0
12
13
SCL
I2C Serial Clock
14
SDA
I2C Serial Data
15
A1
I2C Address Select Pin A1
16
I1+
Noninverting Current Channel Input for 24-bit ADC
Inverting Current Channel Input for 24-bit ADC
Inverting Voltage Channel Input for 24-bit ADC
Noninverting Voltage Channel Input for 24-bit ADC
Analog Input for SAR ADC
17
I1-
18
V1-
19
V1+
20
AN_IN
AGND
ZCD
21
Analog Ground Pin, Return Path for internal analog circuitry
Zero Crossing Detection Output
22
23
REFIN+/OUT
Noninverting Voltage Reference Input and Internal Reference Output Pin
24, 27
DGND
DVDD
Digital Ground Pin, Return Path for internal digital circuitry
Digital Power Supply Pin
25
26
Master Clear for Device
MCLR
28
29
DR
EP
Data Ready (must be left floating)
Exposed Thermal Pad (to be connected to DGND
)
3.1
Event Output Pin (EVENT)
3.3
Oscillator Pins (OSCI/OSCO)
This digital output pin can be configured to act as an
output flag based on various internal raise conditions.
Control is modified through the Event Configuration
register.
OSCI and OSCO provide the master clock for the
device. Appropriate load capacitance should be
connected to these pins for proper operation. An
optional 4 MHz crystal can be connected to these pins.
If a crystal of external clock source is not detected, the
device will clock from the internal 4 MHz oscillator.
3.2
Common Pins (COMMON and
A
COMMON )
B
3.4
Reset Pin (RESET)
The COMMONA and COMMONB pins are internal
connections for the MCP39F521. These two pins
should be connected together in the application.
This pin is active-low and places the delta-sigma
ADCs, PGA, internal VREF and other blocks associated
with the analog front-end in a Reset state when pulled
low. This input is Schmitt-triggered.
2015 Microchip Technology Inc.
DS20005442A-page 11
MCP39F521
3.5
Analog Power Supply Pin (AV
)
3.10 24-Bit Delta Sigma ADC
Differential Voltage Channel
Inputs (V1-/V1+)
DD
AVDD is the power supply pin for the analog circuitry
within the MCP39F521.
This pin requires appropriate bypass capacitors and
should be maintained to 2.7V and 3.6V for specified
operation. It is recommended to use 0.1 µF ceramic
capacitors.
V1- and V1+ are the two fully-differential voltage
channel inputs for the Delta-Sigma ADCs.
The linear and specified region of the channels are
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±600 mVPEAK/GAIN
with VREF = 1.2V.
3.6
Chip Address Inputs (A0, A1)
The A0 and A1 inputs are used by the MCP39F521 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
The maximum absolute voltage, with respect to AGND
for each VN+/- input pin is ±1V with no distortion and
±2V, with no breaking after continuous voltage.
,
3.11 Analog Input (AN_IN)
Up to four devices may be connected to the same bus
by using different combinations. These inputs must be
connected to VDD or GND and cannot be left floating.
This is the input to the analog-to-digital converter that
can be used for temperature measurement and
compensation. If temperature compensation is
required in the application, it is advised to connect the
low-power active thermistor IC MCP9700A to this pin.
If temperature compensation is not required, this can
be used as a general purpose analog-to-digital
converter input.
In most applications, the chip address inputs are
hardwired to logic 0 or logic 1. For applications in which
these pins are controlled by a microcontroller or other
programmable device, the chip address pins must be
driven to logic 0 or logic 1 before normal device
operation can proceed.
2
3.7
I C Serial Clock (SCL)
3.12 Analog Ground Pin (A
)
GND
This input is used to synchronize the data transfer to
and from the device.
AGND is the ground connection to internal analog
circuitry (ADCs, PGA, voltage reference, POR). If an
analog ground pin is available on the PCB, it is
recommended that this pin be tied to that plane.
2
3.8
I C Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to DVDD (typical 10k for 100kHz, 2k for
400kHz).
3.13 Zero Crossing Detection (ZCD)
This digital output pin is the output of the Zero Crossing
Detection circuit of the IC. The output here will be a
logic output with edges that transition at each zero
crossing of the voltage channel input. For more
information see Section 5.13, Zero Crossing
Detection (ZCD).
For normal data transfer, SDA is allowed to change
only during SCL low. Change during SCL high is
reserved for indicating the Start and Stop conditions.
3.14 Noninverting Reference
Input/Internal Reference Output
Pin (REFIN+/OUT)
3.9
24-Bit Delta Sigma ADC
Differential Current Channel
Input Pins (I1+/I1-)
This pin is the noninverting side of the differential
voltage reference input for the delta sigma ADCs or the
internal voltage reference output.
I1- and I1+ are the two fully-differential current channel
inputs for the Delta-Sigma ADCs.
The linear and specified region of the channels are
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±600 mVPEAK/GAIN
with VREF = 1.2V.
For optimal performance, bypass capacitances should
be connected between this pin and AGND at all times,
even when the internal voltage reference is used.
However, these capacitors are not mandatory to
ensure proper operation.
The maximum absolute voltage, with respect to AGND
,
for each In+/- input pin is ±1V with no distortion and
±6V with no breaking after continuous voltage.
DS20005442A-page 12
2015 Microchip Technology Inc.
MCP39F521
3.15 Digital Ground Connection Pins
(D
)
GND
DGND is the ground connection to internal digital
circuitry (SINC filters, oscillator, serial interface). If a
digital ground plane is available, it is recommended to
tie this pin to the digital plane of the PCB. This plane
should also reference all other digital circuitry in the
system.
3.16 Digital Power Supply Pin (DV
)
DD
DVDD is the power supply pin for the digital circuitry
within the MCP39F521. This pin requires appropriate
bypass capacitors and should be maintained between
2.7V and 3.6V for specified operation. It is
recommended to use 0.1 µF ceramic capacitors.
3.17 Data Ready Pin (DR)
The data ready pin indicates if a new delta-sigma A/D
conversion result is ready to be processed. This pin is
for indication only and should be left floating. After each
conversion is finished, a low pulse will take place on the
Data Ready pin to indicate that the conversion result is
ready and an interrupt is generated in the calculation
engine (CE). This pulse is synchronous with the line
frequency to ensure an integer number of samples for
each line cycle.
Note:
This pin is internally connected to the IRQ
of the calculation engine and should be
left floating.
3.18 Exposed Thermal Pad (EP)
This pin is the exposed thermal pad. It must be
connected to DGND
.
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DS20005442A-page 13
MCP39F521
NOTES:
DS20005442A-page 14
2015 Microchip Technology Inc.
MCP39F521
Each command frame consists of a header byte, the
number of bytes in the frame, command packet (or
command packets) and a checksum.
4.0
COMMUNICATION PROTOCOL
The I2C communication protocol is a frame-based
protocol, with
a complete communication frame
Each response frame consists of either a ACK, NAK,
CSFAIL, or ACK+Data with checksum.
occurring between the I2C start and stop bits.
A command frame is a write transmission from the I2C
master to the MCP39F521 device.
Note:
If a custom communication protocol is
desired, please contact a Microchip sales
office.
A read response frame is read transmission from the
I2C master to the MCP39F521.
4.1
COMMUNICATION FRAMES
The following two figures represent the command frames and read request frames.
Command Frame
...
Frame Byte 3
Frame Byte N
Checksum
Frame Byte 1
Frame Byte 2
Header Byte (0xA5) Number of Bytes Command Packet1 Command Packet2 Command Packet n
..
Command
BYTE0
BYTE N
BYTE N
BYTE1 BYTE2
FIGURE 4-1: MCP39F521 Command Write Frame.
Read Response Frame
Frame Byte 3
...
Frame Byte N
Checksum
Frame Byte 1
ACK (0x06)
Frame Byte 2
Frame Byte 4
Data Byte 2
Frame Byte N-1
Data Byte N
Number of Bytes Data Byte 1
..
FIGURE 4-2: MCP39F521 Read Response Frame (ACK with Data).
The following two figures represent I2C command frame writes and read frame responses.
S
S
Bus Activity
Master
Command
Frame Byte 2
Command
Frame Byte 3
Command
Frame Byte 1
Command
Frame Byte N
T
A
R
T
T
O
P
Control Byte
A A
SDA Line
S 1 1 1 0 1
0 0
0
0
0
P
0
1 0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
FIGURE 4-3: I2C Command Write Frame.
S
Response
Frame Byte 2
Response
Frame Byte 1
S
T
Bus Activity
Master
T
A
R
T
Control Byte
A A
Frame Byte 3
Frame Byte N
O
P
SDA Line
S 1 1 1 0 1
1 0
0
0
0
P
1
N
O
A
C
K
1 0
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
FIGURE 4-4: I2C Read Response Frame.
2015 Microchip Technology Inc.
DS20005442A-page 15
MCP39F521
2
This approach allows for single, secure transmission
from the host processor to the MCP39F521 with either
4.3
I C Time Out and Clock Stretching
Time out is when an I2C slave resets its interface if the
I2C clock is low for longer than a specified time. The
MCP39F521 offers a set 2 ms I2C time out that can be
disabled through the Time-out Disable bit in the System
Configuration Register (Register 6-2).
a
single command, or multiple commands.
No command in a frame is processed until the frame is
complete and the checksum and number of bytes are
validated after the stop bit.
The number of bytes in an individual command packet
depends on the specific command. For example, to set
the instruction pointer, three bytes are needed in the
packet: the command byte and two bytes for the
address you want to set to the pointer. The first byte in
a command packet is always the command byte.
In addition, the device includes a clock stretching
feature which allows the master to know when a frame
has been processed. Clock stretching is when a slave
device can not cooperate with the clock speed or needs
to slow down the bus. In the case of the MCP39F521,
after a frame is received, the device will hold the clock
low until the frame has been processed. The maximum
clock stretching duration is less than 10 milliseconds.
2
4.2
I C CONTROL BYTE
A Control byte is the first byte received following the
Start condition from the master device. The Control
byte consists of a 4-bit control code. For the
MCP39F521 the control code is ‘1110’ for all read and
write operations. The following three bits are
chip-select address bits, A2, A1, and A0. For the
MCP39F521, A2 is always set to binary ‘1’. A1 and A0
are controlled by the logic pins A1 and A0, which
allows up to 4 different devices on the I2C bus.
4.4
Checksum
The checksum is generated using simple byte addition
and taking the modulus to find the remainder after
dividing the sum of the entire frame by 256. This
operation is done to obtain an 8-bit checksum. All the
bytes of the frame are included in the checksum,
including the header byte and number of bytes. If a
frame includes multiple command packets, none of the
commands will be issued if the frame checksum fails.
In this instance, the MCP39F521 will respond with a
CSFAIL response of 0x51.
The last bit of the Control byte defines the operation to
be performed. When set to ‘1’, a read operation is
selected. When set to ‘0’, a write operation is selected.
Following a Start condition, the MCP39F521 monitors
the SDA bus checking for the 4-bit control code
(‘1110’) and proper address bits. Upon receiving the
correct control code and address bits, the slave
(MCP39F521) outputs an acknowledge signal on the
SDA line, and depending on the state of the R/W bit,
will either respond with data or wait to receive
additional bytes prior to the Stop condition. The
Control byte is defined in the following figure.
On commands that are requesting data back from the
MCP39F521, the frame and checksum are created in
the same way, with the header byte becoming an
acknowledge (0x06). Communication examples are
given in Section 4.6, Example Communication
Frames and MCP39F521 Responses.
Read/Write Bit
Chip Select
Control Code
Bits
S
1
1
1
0
1
A1 A0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
FIGURE 4-5: MCP39F521 Control Byte Format.
DS20005442A-page 16
2015 Microchip Technology Inc.
MCP39F521
4.5
Command List
The following table is a list of all accepted command
bytes for the MCP39F521. There are 10 possible
accepted commands for the MCP39F521.
TABLE 4-1:
MCP39F521 INSTRUCTION SET
Command
#
Command
Instruction
Parameter
Number
ofBytes
Successful
Response
Command
ID
1
Register Read, N bytes
0x4E
Number of Bytes
2
ACK, Data,
Checksum
2
3
4
5
Register Write, N bytes
Set Address Pointer
Save Registers To Flash
Page Read EEPROM
0x4D
0x41
0x53
0x42
Number of Bytes
ADDRESS
None
1+N
3
ACK
ACK
ACK
2
PAGE
2
ACK, Data,
Checksum
6
7
Page Write EEPROM
0x50
0x4F
0x5A
0x7A
0x76
PAGE
None
None
None
None
18
2
ACK
ACK
Bulk Erase EEPROM
8
Auto-Calibrate Gain
Note 1
9
Auto-Calibrate Reactive Gain
Auto-Calibrate Frequency
Note 1
Note 1
10
Note 1: See Section 8.0, MCP39F521 Calibration for more information on calibration.
4.6
Example Communication Frames
and MCP39F521 Responses
Tables 4-2 to 4-11 show exact hexadecimal
communication frames as they should be sent to the
MCP39F521 from the system MCU. The values here
can be used as direct examples for writing your code to
communicate to the MCP39F521.
TABLE 4-2:
REGISTER READ, N BYTES COMMAND (Note 1)
Byte # Value
Byte Description
Response from MCP39F521
1
2
3
4
5
6
7
8
0xA5 Header Byte
0x08 Number of Bytes in Frame
0x41 Command (Set Address Pointer)
0x00 Address High
0x02 Address Low
0x4E Command (Register Read, N bytes)
0x20 Number of Bytes to Read (32)
0x5E Checksum
ACK + Number of Bytes (35) + 32 bytes, + Checksum
Note 1: This example Register Read, N bytesframe, as written here, can be used to poll a subset of the
output data, starting at the top, address 0x02, and reading 32 data bytes back or 35 bytes total in the
frame.
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DS20005442A-page 17
MCP39F521
TABLE 4-3:
Byte #
REGISTER WRITE, N- BYTES COMMAND (Note 1)
Value
Byte Description
Response from MCP39F521
1
2
0xA5
0x25
0x41
0x00
0x48
0x4D
0x1C
*Data*
Header Byte
Number of Bytes in Frame
Command (Set Address Pointer)
Address High
3
4
5
Address Low
6
Command (Register Write, N Bytes)
Number of Bytes to Write (28)
Data Bytes (28 total data bytes)
Checksum ACK
7
8-36
37
Checksum
Note 1: This Register Write, N Bytes frame, as written here, can be used to write the entire set of
calibration target data, starting at the top, address 0x7A, and continuing to write until the end of this set of
registers, 28 bytes later, register 0x94. Note these are not the calibration registers, but the calibration
targets which need to be written prior to issuing the auto-calibration target commands. See Section 8.0,
MCP39F521 Calibration for more information.
TABLE 4-4:
Byte #
SET ADDRESS POINTER COMMAND (Note 1)
Value
Byte Description
Response from MCP39F521
1
2
3
4
5
6
0xA5
0x06
0x41
0x00
0x02
0xEE
Header Byte
Number of Bytes in Frame
Command (Set Address Pointer)
Address High
Address Low
Checksum
ACK
Note 1: The Set Address Pointercommand is typically included inside of a frame that includes a read or write
command, as shown in Table 4-2 and Table 4-3. There is typically no reason for this command to have its
own frame, but is shown here as an example.
TABLE 4-5:
Byte #
SAVE TO FLASH COMMAND
Value
Byte Description
Response from MCP39F521
1
2
3
4
0xA5
0x04
0x53
0xFC
Header Byte
Number of Bytes in Frame
Command (Save To Flash)
Checksum
ACK
TABLE 4-6:
Byte #
PAGE READ EEPROM COMMAND
Value Byte Description
Header Byte
Response from MCP39F521
1
2
3
4
5
0xA5
0x05
0x42
0x01
0xED
Number of Bytes in Frame
Command (Page Read EEPROM)
Page Number (e.g. 1)
Checksum
ACK + EEPROM Page Data + Checksum
DS20005442A-page 18
2015 Microchip Technology Inc.
MCP39F521
TABLE 4-7:
Byte #
PAGE WRITE EEPROM COMMAND
Value
Byte Description
Response from MCP39F521
1
2
0xA5
0x15
Header Byte
Number of Bytes in Frame
Command (Page Write EEPROM)
Page Number (e.g. 1)
EEPROM Data (16 bytes/Page)
Checksum
3
0x50
4
0x01
5-20
21
*Data*
Checksum
ACK
TABLE 4-8:
Byte #
BULK ERASE EEPROM COMMAND
Value
Byte Description
Response from MCP39F521
1
2
3
4
0xA5
0x04
0x4F
0xF8
Header Byte
Number of Bytes in Frame
Command (Bulk Erase EEPROM)
Checksum
ACK
TABLE 4-9:
AUTO-CALIBRATE GAIN COMMAND
Byte Description
Byte # Value
Response from MCP39F521
1
2
3
4
0xA5 Header Byte
0x04 Number of Bytes in Frame
0x5A Command (Auto-Calibrate Gain)
0x03 Checksum
ACK (or NAK if unable to calibrate), see Section 8.0,
MCP39F521 Calibration for more information.
TABLE 4-10: AUTO-CALIBRATE REACTIVE GAIN COMMAND
Byte # Value Byte Description
Response from MCP39F521
1
2
3
4
0xA5 Header Byte
0x04 Number of Bytes in Frame
0x7A Command (Auto-Calibrate Reactive Gain)
0x23 Checksum
ACK (or NAK if unable to calibrate), see
Section 8.0, MCP39F521 Calibration for more
information.
TABLE 4-11: AUTO-CALIBRATE FREQUENCY COMMAND
Byte # Value Byte Description
Response from MCP39F521
1
2
3
4
0xA5 Header Byte
0x04 Number of Bytes in Frame
0x76 Command (Auto-Calibrate Frequency)
0x1F Checksum
ACK (or NAK if unable to calibrate), see Section 8.0,
MCP39F521 Calibration for more information.
2015 Microchip Technology Inc.
DS20005442A-page 19
MCP39F521
4.7.6
PAGE WRITE EEPROM (0x50)
4.7
Command Descriptions
The Page Write EEPROM command is expecting
17 additional bytes in the command parameters, which
are the EEPROM page plus 16 bytes of data. A more
complete description of the memory organization of the
EEPROM can be found in Section 9.0, EEPROM The
response to this command is an acknowledge.
4.7.1
REGISTER READ, N BYTES (0x4E)
The Register Read, N bytescommand returns
the N bytes that follow whatever the current address
pointer is set to. It should typically follow
a
Set Address Pointercommand and can be used
in conjunction with other read commands. An
acknowledge, data and checksum is the response for
this command. The maximum number of bytes that can
be read with this command is 32. If there are other read
commands within a frame, the maximum number of
bytes that can be read is 32 minus the number of bytes
being read in the frame. With this command, the data is
returned LSB first.
4.7.7
BULK ERASE EEPROM (0x4F)
The Bulk Erase EEPROM command will erase the
entire EEPROM array and return it to a state of 0xFFFF
for each memory location of EEPROM. A more
complete description of the memory organization of the
EEPROM can be found in Section 9.0, EEPROM. The
response to this command is acknowledge.
4.7.2
REGISTER WRITE, N BYTES (0x4D)
bytes command is
4.7.8
AUTO-CALIBRATE GAIN (0x5A)
The Register Write,
N
The Auto-Calibrate Gain command initiates the
single-point calibration that is all that is typically
required for the system. This command calibrates the
RMS current, RMS voltage and active power based on
the target values written in the corresponding registers.
See Section 8.0, MCP39F521 Calibration for more
information on device calibration. The response to this
command is acknowledge.
followed by N bytes that will be written to whatever the
current address pointer is set to. It should typically
follow a Set Address Pointercommand and can
be used in conjunction with other write commands. An
acknowledge is the response for this command. The
maximum number of bytes that can be written with this
command is 32. If there are other write commands
within a frame, the maximum number of bytes that can
be written is 32 minus the number of bytes being
written in the frame. With this command, the data is
written LSB first.
4.7.9
AUTO-CALIBRATE REACTIVE GAIN
(0X7A)
The Auto-Calibrate Reactive Gaincommand
initiates single-point calibration to match the
measured reactive power to the target reactive power.
This is typically done at PF = 0.5. See section
Section 8.0, MCP39F521 Calibration for more
information on device calibration.
a
4.7.3
SET ADDRESS POINTER (0x41)
This command is used to set the address pointer for all
read and write commands. This command is expecting
the address pointer as the command parameter in the
following two bytes, address high byte followed by
address low byte. The address pointer is two bytes in
length. If the address pointer is within the acceptable
addresses of the device, an acknowledge will be
returned.
4.7.10
AUTO-CALIBRATE FREQUENCY
(0x76)
For applications not using an external crystal and
running the MCP39F521 off the internal oscillator, a
gain calibration to the line frequency indication is
required. The Gain Line Frequency (0x00AE) register
is set such that the frequency indication matches what
is set in the Line Frequency Reference (0x0094)
register. See Section 8.0, MCP39F521 Calibration for
more information on device calibration.
4.7.4
SAVE REGISTERS TO FLASH (0x53)
The Save Registers To Flashcommand makes
a copy of all the calibration and configuration registers
to flash. This includes all R/W registers in the register
set. The response to this command is an acknowledge.
4.7.5
PAGE READ EEPROM (0x42)
The Read Page EEPROMcommand returns 16 bytes
of data that are stored in an individual page on the
MCP39F521. A more complete description of the
memory organization of the EEPROM can be found in
Section 9.0, EEPROM. This command is expecting
the EEPROM page as the command parameter or the
following byte. The response to this command is an
acknowledge, 16-bytes of data and CRC checksum.
DS20005442A-page 20
2015 Microchip Technology Inc.
MCP39F521
4.8
Notation for Register Types
The following notation has been adopted for describing
the various registers used in the MCP39F521:
TABLE 4-12: SHORT-HAND NOTATION
FOR REGISTER TYPES
Notation
Description
u64
u32
s32
u16
s16
b32
Unsigned, 64-bit register
Unsigned, 32-bit register
Signed, 32-bit register
Unsigned, 16-bit register
Signed, 16-bit register
32-bit register containing discrete
Boolean bit settings
2015 Microchip Technology Inc.
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MCP39F521
5.3
Raw Voltage and Currents Signal
Conditioning
5.0
CALCULATION ENGINE (CE)
DESCRIPTION
The first set of signal conditioning that occurs inside the
MCP39F521 is shown in Figure 5-1. All conditions set
in this diagram effect all of the output registers
(RMS current, RMS voltage, active power, reactive
power, apparent power, etc.). The gain of the PGA, the
Shutdown and Reset status of the 24-bit ADCs are all
controlled through the System Configuration register
(Register 6-2).
5.1
Computation Cycle Overview
The MCP39F521 uses a coherent sampling algorithm
to phase lock the sampling rate to the line frequency
with an integer number of samples per line cycle, and
reports all power output quantities at a 2N number of
line cycles. This is defined as a computation cycle and
is dependent on the line frequency, so any change in
the line frequency will change the update rate of the
output power quantities.
For DC applications, offset can be removed by using
the DC Offset Current register. To compensate for any
external phase error between the current and voltage
channels, the Phase Compensation register can be
used.
5.2
Accumulation Interval Parameter
The accumulation interval is defined as an 2N number
of line cycles, where N is the value in the Accumulation
Interval Parameter register.
See Section 8.0, MCP39F521 Calibration for more
information on device calibration.
24-bit ADC
Multi-Level
Modulator
I1+
+
-
PGA
i
I1-
HPF 1
+
+
CHANNEL I1
DC Offset Current:s16
SystemConfiguration:b32
PhaseCompensation:s16
24-bit ADC
Multi-Level
Modulator
V1+
V1-
+
-
PGA
v
HPF 1
CHANNEL V1
Note 1: High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel.
FIGURE 5-1:
Channel I1 and V1 Signal Flow.
5.4 RMS Current and RMS Voltage
The MCP39F521 device provides true RMS
measurements. The MCP39F521 device has two
simultaneous sampling 24-bit A/D converters for the
current and voltage measurements. The root mean
square calculations are performed on 2N current and
voltage samples, where N is defined by the register
Accumulation Interval Parameter.
EQUATION 5-1:
RMS CURRENT AND
VOLTAGE
N
N
2
– 1
2
– 1
2
2
i
v
n
n
n = 0
n = 0
I
=
-----------------------------
V
=
------------------------------
RMS
RMS
N
N
2
2
DS20005442A-page 22
2015 Microchip Technology Inc.
MCP39F521
Range:b32
2N-1
N
÷ 2
÷2RANGE
CurrentRMS:u32
i
X
X
0
+
ACCU
+
GainCurrentRMS:u16
OffsetCurrentRMS:s32
ApparentPower:u32
X
GainVoltageRMS:u16
2
N-1
N
÷ 2
÷2RANGE
v
VoltageRMS:u16
X
X
0
ACCU
FIGURE 5-2:
RMS Current and Voltage Calculation Signal Flow.
5.5
Power and Energy
The MCP39F521 offers signed power numbers for
active and reactive power, import and export registers
for active energy, and four-quadrant reactive power
measurement. For this device, import power or energy
is considered positive (power or energy being
consumed by the load), and export power or energy is
considered negative (power or energy being delivered
by the load). The following figure represents the
measurements obtained by the MCP39F521.
Import Reactive Power
Consume, Inductive
+P, +Q
Generate, Inductive
Quadrant I
Quadrant II
-P, +Q
S
Q
P
Import Active Power
Export Active Power
Quadrant III
Quadrant IV
Consume, Capacitive
+P, -Q
Generate, Capacitive
-P, -Q
Export Reactive Power
The Power Circle and Triangle (S = Apparent, P = Active, Q = Reactive).
FIGURE 5-3:
2015 Microchip Technology Inc.
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MCP39F521
5.6
Energy Accumulation
5.8
Active Power (P)
Energy accumulation for all four energy registers
(import/export, active/reactive) occurs at the end of
each computation cycle, if the energy accumulation
has been turned on. See Section 6.3, System Status
The MCP39F521 has two simultaneous sampling A/D
converters. For the active power calculation, the
instantaneous current and instantaneous voltages are
multiplied together to create instantaneous power.
This instantaneous power is then converted to active
power by averaging or calculating the DC component.
Register on the Energy Control register.
A
no-load threshold test is done to make sure the
measured energy is not below the no-load threshold; if
it is above the no-load threshold, the accumulation
occurs with a default energy resolution of 1mWh for all
of the energy registers.
Equation 5-4 controls the number of samples used in
this accumulation prior to updating the Active Power
output register.
Please note that although this register is unsigned, the
direction of the active power (import or export) can be
determined by the Active Power Sign bit (SIGN_PA)
located in the System Status register (Register 6-1).
5.6.1
NO-LOAD THRESHOLD
The no-load threshold is set by modifying the value in
the No-Load Threshold register. The unit for this
register is power with a default resolution of 0.01W. The
default value is 100 or 1.00W. Any power that is below
1W will not be accumulated into any of the energy
registers.
EQUATION 5-4:
ACTIVE POWER
N
k = 2 – 1
1
N
2
P = ------
V I
k
k
k = 0
5.7
Apparent Power (S)
This 32-bit register is the output register for the final
apparent power indication. It is the product of RMS
current and RMS voltage as shown in Equation 5-2.
EQUATION 5-2:
APPARENT POWER (S)
S = I
V
RMS
RMS
For scaling of the apparent power indication, the
calculation engine uses the register Apparent Power
Divisor. This is described in the following register
operations, per Equation 5-3.
EQUATION 5-3:
APPARENT POWER (S)
CurrentRMS VoltageRMS
S = --------------------------------------------------------------------
ApparentPowerDivisor
10
GainActivePower:u16
i
Range:b32
N
2
-1
÷ 2N
÷2RANGE
ActivePower:u32
X
X
0
+
ACCU
+
OffsetActivePower:s32
v
FIGURE 5-4:
Active Power Calculation Signal Flow.
DS20005442A-page 24
2015 Microchip Technology Inc.
MCP39F521
5.9
Power Factor (PF)
Power factor is calculated by the ratio of P to S or active
power divided by apparent power.
EQUATION 5-5:
POWER FACTOR
P
PF = ---
S
The Power Factor Reading is stored in a signed 16-bit
register (Power Factor). This register is a signed, two's
complement register with the MSB representing the
polarity of the power factor. Positive means inductive
load, negative means capacitive load. Each LSB is
then equivalent to a weight of 2-15. A maximum register
value of 0x7FFF corresponds to a power factor of 1.
The minimum register value of 0x8000 corresponds to
a power factor of -1.
5.10 Reactive Power (Q)
In the MCP39F521, Reactive Power is calculated using
a 90 degree phase shift in the voltage channel. The
same accumulation principles apply as with active
power where ACCU acts as an accumulator. Any light
load or residual power can be removed by using the
Offset Reactive Power register. Gain is corrected by
the Gain Reactive Power register. The final output is an
unsigned 32-bit value located in the Reactive Power
register.
Please note that although this register is unsigned, the
direction of the power can be determined by the
Reactive Power Sign bit (SIGN_PR) in the System
Status register (Register 6-1).
GainReactivePower:u16
i
HPF
Range:b32
N
2
-1
÷ 2N
÷2RANGE
X
X
0
+
ACCU1
ReactivePower:u32
-
OffsetReactivePower:s32
v
HPF (+90deg.)
FIGURE 5-5:
Reactive Power Calculation Signal Flow.
2015 Microchip Technology Inc.
DS20005442A-page 25
MCP39F521
5.11 10-Bit Analog Input
5.13 Zero Crossing Detection (ZCD)
The least 10 significant bits of the 16-bit Analog Input
register contain the output of the 10-bit ADC. The
conversion rate of the analog input occurs once every
computation cycle.
The Zero Crossing Detection block generates a logic
pulse output on the ZCD pin that is coherent with the
zero crossing of the input AC signal present on voltage
input pins (V1+, V1-). The ZCD pin can be enabled and
disabled
by
the
corresponding
bit
The Thermistor Voltage can be used for temperature
compensation of the calculation engine. See
Section 8.7, Temperature Compensation for more
information.
(ZCD_OUTPUT_DIS) in the System Configuration
register (Register 6-2). When enabled, this produces a
square wave with a frequency that is twice that of the
AC signal present on the voltage input. Figure 5-7
represents the signal on the ZCD pin superimposed
with the AC signal present on the voltage input in this
mode.
AnalogInput:u16
10-bit
MCP9700
ADC
<100 µs
FIGURE 5-6:
Using an Analog
Out-Temperature Sensor for Automatic
Temperature Compensation.
5.12 Minimum and Maximum
Recordings
FIGURE 5-7:
Operation (Noninverted, Non-Pulsed).
Zero Crossing Detection
The MCP39F521 has the ability to record minimum and
maximum outputs and keep them in a total of four
registers (two minimum and two maximum) based on
the value of address pointers located in the four
registers listed below.
A
second mode is available that produces a
100 µs pulse (ZCD_PULS) at each zero crossing,
shown in Figure 5-8.
A minimum and maximum test is done after each
calculation interval. If the current measurement value
of the value directed to by the pointer is smaller or
larger than the value in the Minimum or Maximum
register, the record is updated appropriately.
<100 µs
The registers are listed as follows:
• MinMaxPointer1 → MinimumRecord1,
MaximumRecord1
• MinMaxPointer2 → MinimumRecord2,
MaximumRecord2
FIGURE 5-8:
Zero Crossing Detection
Operation (Noninverted, Pulsed).
Only the output quantity register addresses can be
tracked by the Min/Max pointers. Output quantity
registers are defined as those from Voltage RMS to
Apparent Power (addresses 0x0006 to 0x001A). All
other addresses will be ignored by the calculation
engine.
Switching modes is done by setting the corresponding
bit in the System Configuration register (Register 6-2).
In addition, either the toggling of this pin, or the pulse,
can be inverted. The ZCD Inversion bit (ZCD_INV) is
also in the System Configuration register
(Register 6-2).
Please note that the 64-bit energy registers can not be
tracked through the Minimum and Maximum recording
registers.
There are two bits in the System Configuration register
that can be used to modify the zero crossing. The zero
crossing output can be inverted by setting the Inversion
bit, or the zero crossing can be a 100 µs pulse at each
zero crossing, by setting the Pulse Bit.
Note that a low-pass filter is included in the signal path
that allows the zero crossing detection circuit to filter
out the fundamental frequency. An internal
compensation circuit is then used to gain back the
phase delay introduced by the low-pass filter resulting
in a latency of less than 100 µs.
DS20005442A-page 26
2015 Microchip Technology Inc.
MCP39F521
6.0
6.1
REGISTER DESCRIPTIONS
Complete Register Map
The following table describes the registers for the MCP39F521 device.
TABLE 6-1:
Address
MCP39F521 REGISTER MAP
Section Read/ Data
Number Write Type
Register Name
Description
Output Registers
0x0000 Instruction Pointer
0x0002 System Status
0x0004 System Version
6.2
6.3
6.4
R
R
R
u16 Address pointer for read or write commands
b16 System Status Register
u16 System version date code information for
MCP39F521, set at Microchip factory;
format YMDD
0x0006 Voltage RMS
5.4
8.6
R
R
R
R
R
R
R
R
R
R
R
R
R
u16 RMS Voltage output
0x0008 Line Frequency
u16 Line Frequency output
0x000A Analog Input Voltage
0x000C Power Factor
5.11
5.9
u16 Output of the 10-bit SAR ADC
s16 Power Factor output
0x000E Current RMS
5.4
u32 RMS Current output
0x0012 Active Power (Note 1)
0x0016 Reactive Power (Note 1)
0x001A Apparent Power
5.8
u32 Active Power output
5.10
5.7
u32 Reactive Power output
u32 Apparent Power output
0x001E Import Active Energy Counter
0x0026 Export Active Energy Counter
0x002E Import Reactive Energy Counter
0x0036 Export Reactive Energy Counter
0x003E Minimum Record 1
5.6
u64 Accumulator for Active Energy, Import
u64 Accumulator for Active Energy, Export
u64 Accumulator for Reactive Energy, Import
u64 Accumulator for Reactive Energy, Export
5.6
5.6
5.6
5.12
u32 Minimum Value of the Output Quantity
Address in Min/Max Pointer 1 Register
0x0042 Minimum Record 2
5.12
R
u32 Minimum Value of the Output Quantity
Address in Min/Max Pointer 2 Register
0x0046 Reserved
—
—
R
R
R
u32 Reserved
u32 Reserved
0x004A Reserved
0x004E Maximum Record 1
5.12
u32 Maximum Value of the Output Quantity
Address in Min/Max Pointer 1 Register
0x0052 Maximum Record 2
5.12
R
u32 Maximum Value of the Output Quantity
Address in Min/Max Pointer 2 Register
0x0056 Reserved
0x005A Reserved
—
—
R
R
u32 Reserved
u32 Reserved
Note 1: The registers are unsigned, however their sign is kept as a separate bit in the System Status Register
(Register 6-1).
2: These registers are reserved for EMI filter compensation when necessary for power supply monitoring.
They may require specific adjustment depending on PSU parameters; please contact the local Microchip
office for further support.
2015 Microchip Technology Inc.
DS20005442A-page 27
MCP39F521
TABLE 6-1:
Address
MCP39F521 REGISTER MAP (CONTINUED)
Section Read/ Data
Number Write Type
Register Name
Description
Calibration Registers
0x005E Calibration Register
Delimiter
8.8
R/W u16 May be used to initiate loading of the default
calibration coefficients at start-up
0x0060 Gain Current RMS
0x0062 Gain Voltage RMS
0x0064 Gain Active Power
0x0066 Gain Reactive Power
0x0068 Offset Current RMS
0x006C Offset Active Power
0x0070 Offset Reactive Power
0x0074 DC Offset Current
0x0076 Phase Compensation
0x0078 Apparent Power Divisor
8.3
8.3
R/W u16 Gain Calibration Factor for RMS Current
R/W u16 Gain Calibration Factor for RMS Voltage
R/W u16 Gain Calibration Factor for Active Power
R/W u16 Gain Calibration Factor for Reactive Power
R/W s32 Offset Calibration Factor for RMS Current
R/W s32 Offset Calibration Factor for Active Power
R/W s32 Offset Calibration Factor for Reactive Power
R/W s16 Offset Calibration Factor for DC Current
R/W s16 Phase Compensation
8.3
8.3
8.5.1
8.5.1
8.5.1
8.5.2
8.5
5.7
R/W u16 Number of Digits for apparent power divisor to
match IRMS and VRMS resolution
Design Configuration Registers
0x007A System Configuration
6.5
R/W b32 Control for device configuration, including
ADC configuration
0x007E Event Configuration
0x0082 Range
7.0
6.6
R/W b16 Settings for the Event pin
R/W b32 Scaling factor for Outputs
0x0086 Calibration Current
8.3.1
R/W u32 Target Current to be used during
single-point calibration
0x008A Calibration Voltage
8.3.1
8.3.1
8.3.1
8.6.1
R/W u16 Target Voltage to be used during
single-point calibration
0x008C Calibration Power Active
0x0090 Calibration Power Reactive
0x0094 Line Frequency Reference
R/W u32 Target Active Power to be used during
single-point calibration
R/W u32 Target Reactive Power to be used during
single-point calibration
R/W u16 Reference Value for the nominal line
frequency
0x0096 Reserved
—
—
R/W u32 Reserved
R/W u32 Reserved
0x009A Reserved
0x009E Accumulation Interval Parameter
5.2
R/W u16 N for 2N number of line cycles to be used
during a single computation cycle
0x00A0 Voltage Sag Limit
0x00A2 Voltage Surge Limit
0x00A4 Over Current Limit
0x00A8 Over Power Limit
7.2
7.2
7.2
7.2
R/W u16 RMS Voltage threshold at which an event flag
is recorded
R/W u16 RMS Voltage threshold at which an event flag
is recorded
R/W u32 RMS Current threshold at which an event flag
is recorded
R/W u32 Active Power Limit at which an event flag is
recorded
Note 1: The registers are unsigned, however their sign is kept as a separate bit in the System Status Register
(Register 6-1).
2: These registers are reserved for EMI filter compensation when necessary for power supply monitoring.
They may require specific adjustment depending on PSU parameters; please contact the local Microchip
office for further support.
DS20005442A-page 28
2015 Microchip Technology Inc.
MCP39F521
TABLE 6-1:
Address
MCP39F521 REGISTER MAP (CONTINUED)
Section Read/ Data
Register Name
Description
Number Write Type
EMI Filter Compensation Registers (Note 2)
0x00AC Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
R
R
R
R
R
R
R
R
R
R
R
R
R
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
u16 Reserved
0x00AE Reserved
0x00B0 Reserved
0x00B2 Reserved
0x00B4 Reserved
0x00B6 Reserved
0x00B8 Reserved
0x00BA Reserved
0x00BC Reserved
0x00BE Reserved
0x00C0 Reserved
0x00C2 Reserved
0x00C4 Reserved
Temperature Compensation Registers
0x00C6 Temperature Compensation for
Frequency
8.7
8.7
8.7
8.7
R/W u16 Correction factor for compensating the line
frequency indication over temperature
0x00C8 Temperature Compensation for
Current
R/W u16 Correction factor for compensating the Current
RMS indication over temperature
0x00CA Temperature Compensation for
Power
R/W u16 Correction factor for compensating the active
power indication over temperature
0x00CC Ambient Temperature
Reference Voltage
R/W u16 Register for storing the reference temperature
during calibration
Control Registers for Peripherals
0x00CE Reserved
—
—
R/W u16 Reserved
0x00D0 Reserved
R/W u16 Reserved
0x00D2 Reserved
—
R/W u16 Reserved
0x00D4 MinMaxPointer1
0x00D6 MinMaxPointer2
0x00D8 Reserved
5.12
5.12
—
R/W u16 Address Pointer for Min/Max 1 Outputs
R/W u16 Address Pointer for Min/Max 2 Outputs
R/W u16 Reserved
0x00DA Reserved
—
R/W u16 Reserved
0x00DC Energy Control
5.6
R/W u16 Input register for reset/start of Energy
Accumulation
0x00DE Reserved
—
R/W u16 Reserved
0x00E0 No-Load Threshold
5.6.1
R/W u16 No-Load Threshold for Energy Counting
Note 1: The registers are unsigned, however their sign is kept as a separate bit in the System Status Register
(Register 6-1).
2: These registers are reserved for EMI filter compensation when necessary for power supply monitoring.
They may require specific adjustment depending on PSU parameters; please contact the local Microchip
office for further support.
2015 Microchip Technology Inc.
DS20005442A-page 29
MCP39F521
6.2
Address Pointer Register
This unsigned 16-bit register contains the address to
which all read and write instructions occur. This register
is only written through the Set Address Pointer
command and is otherwise outside the writable range
of register addresses.
6.3
System Status Register
The System Status register is a read-only register and
can be used to detect the various states of pin levels as
defined below.
REGISTER 6-1:
SYSTEM STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-x
U-0
—
U-0
—
EVENT
bit 15
bit 8
U-0
—
U-0
—
R-x
R-x
R-x
R-x
R-x
R-x
SIGN_PR
SIGN_PA OVERPOW
OVERCUR
VSURGE
VSAG
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
bit 10
EVENT: State of Event Detection algorithm. This bit is latched and must be cleared.
1= Event has occurred
0= Event has not occurred
bit 9-8
bit 7-6
bit 5
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
SIGN_PR: Sign of Reactive Power
1= Reactive Power is positive, inductive and is in quadrants 1,2
0= Reactive Power is negative, is capacitive and is in quadrants 3,4
bit 4
bit 3
bit 2
bit 1
bit 0
SIGN_PA: Sign of Active Power (import/export sign of active power)
1= Active Power is positive (import) and is in quadrants 1,4
0= Active Power is negative (export) and is in quadrants 2,3
OVERPOW: State of Over Power detection algorithm
1= Over Power threshold has been broken
0= Over Power threshold has not been broken
OVERCUR: State of the Over Current detection algorithm
1= Over Current threshold has been broken
0= Over Current threshold has not been broken
VSURGE: State of Voltage Surge Detection algorithm. This bit is latched and must be cleared.
1= Surge threshold has been broken
0= Surge threshold has not been broken
VSAG: State of Voltage Sag Detection algorithm. This bit is latched and must be cleared.
1= Sag threshold has been broken
0= Sag threshold has not been broken
DS20005442A-page 30
2015 Microchip Technology Inc.
MCP39F521
6.5.2
24-BIT ADC RESET MODE
(SOFT RESET MODE)
6.4
System Version Register
The System Version register is hard-coded by
Microchip Technology Inc. and contains calculation
engine date code information. The System Version
register is a date code in the YMDD format, with year
and month in hex, day in decimal (e.g. 0xF316 = 2015,
Feb. 16th).
24-bit ADC Reset mode (also called Soft Reset) can
only be entered through setting high the RESET<1:0>
bits in the System Configuration register (Register 6-2).
This mode is defined as the condition where the
converters are active but their output is forced to ‘0’.
6.5.3
ADC SHUTDOWN MODE
6.5
System Configuration
ADC Shutdown mode is defined as a state where the
converters and their biases are OFF, consuming only
leakage current. When the Shutdown bit (SHUTDOWN
<1:0>) is reset to ‘0’, the analog biases will be enabled,
as well as the clock and the digital circuitry.
The System Configuration register (Register 6-2)
contains bits for controlling the following:
• PGA setting
• ADC Reset State
Each converter can be placed in Shutdown mode
independently. This mode is only available through
programming of the SHUTDOWN<1:0> bits in the
System Configuration register (Register 6-2).
• ADC Shutdown State
• Voltage Reference Trim
• Single Wire Auto-Transmission
These options are described in the following sections.
6.5.4
VREF TEMPERATURE
COMPENSATION
6.5.1
PROGRAMMABLE GAIN
AMPLIFIERS (PGA)
If desired, the user can calibrate out the temperature
drift for ultra-low VREF drift.
The two Programmable Gain Amplifiers (PGAs) reside
at the front-end of each 24-bit Delta-Sigma ADC. They
have two functions:
The internal voltage reference comprises a proprietary
circuit and algorithm to compensate first-order and
• Translate the Common mode of the input from
AGND to an internal level between AGND and AVDD
second-order
temperature
coefficients.
The
compensation allows very low temperature coefficients
(typically 10 ppm/°C) on the entire range of
temperatures from -40°C to +125°C. This temperature
coefficient varies from part to part.
• Amplify the input differential signal
The translation of the Common mode does not change
the differential signal but enters the Common mode so
that the input signal can be properly amplified.
The temperature coefficient can be adjusted on each
part through the System Configuration register
(0x0042) (Register 6-2). The default value of this
register is set to 0x42. The typical variation of the
temperature coefficient of the internal voltage
reference, with respect to VREFCAL register code, is
shown in Figure 6-1.
The PGA block can be used to amplify very low signals,
but the differential input range of the delta-sigma
modulator must not be exceeded. The PGA is
controlled by the PGA_CHn<2:0> bits in Register 6-2
the System Configuration register. Table 6-2
represents the gain settings for the PGAs.
60
50
40
30
20
10
0
TABLE 6-2:
PGA CONFIGURATION
SETTING (Note 1)
Gain
Gain
Gain
(dB)
VIN Range
(V)
PGA_CHn<2:0> (V/V)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
2
0
±0.5
±0.25
6
4
12
18
24
30
±0.125
8
±0.0625
±0.03125
±0.015625
16
32
0
64
128
192
256
VREFCAL Register Trim Code (decimal)
Note 1: The two undefined settings (110, 111)
FIGURE 6-1:
Trimcode Chart.
VREF Tempco vs. VREFCAL
are G = 1.
2015 Microchip Technology Inc.
DS20005442A-page 31
MCP39F521
REGISTER 6-2:
SYSTEM CONFIGURATION REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
PGA_CH1<2:0>
PGA_CH0<2:0>
bit 31
bit 24
R/W-0
bit 23
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
VREFCAL<7:0>
bit 16
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
ZCD_INV
ZCD_PULS
ZCD_OUTPUT_
DIS
TIMEOUT_DIS
bit 15
bit 8
R/W-0
TEMPCOMP
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
RESET<1:0>
SHUTDOWN<1:0>
VREFEXT
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-30
bit 29-27
Unimplemented: Read as ‘0’
PGA_CH1 <2:0>: PGA Setting for Channel 1
111= Reserved (Gain = 1)
110= Reserved (Gain = 1)
101= Gain is 32
100= Gain is 16
011= Gain is 8
010= Gain is 4
001= Gain is 2
000= Gain is 1 (DEFAULT)
bit 26-24
PGA_CH0 <2:0>: PGA Setting for Channel 0
111= Reserved (Gain = 1)
110= Reserved (Gain = 1)
101= Gain is 32
100= Gain is 16
011= Gain is 8 (Default)
010= Gain is 4
001= Gain is 2
000= Gain is 1
bit 23-16
bit 15
VREFCAL<n>: Internal voltage reference temperature coefficient register value (See Section 6.5.4,
VREF Temperature Compensation for complete description)
TIMEOUT_DIS: Time Out Disable
1= I2C Time Out is Disabled
0= I2C Time Out is Enabled (DEFAULT)
bit 14-13
bit 12
Unimplemented: Read as ‘0’
ZCD_INV: Zero Crossing Detection Output Inverse
1= ZCD is inverted
0= ZCD is not inverted (DEFAULT)
DS20005442A-page 32
2015 Microchip Technology Inc.
MCP39F521
REGISTER 6-2:
SYSTEM CONFIGURATION REGISTER (CONTINUED)
bit 11
ZCD_PULS: Zero Crossing Detection Pulse mode
1= ZCD output is 100 µs pulses on zero crossings
0= ZCD Output changes logic state on zero crossings (DEFAULT)
bit 10
ZCD_OUTPUT_DIS: Disable the Zero Crossing output pin
1= ZCD output is disabled
0= ZCD output is enabled (Default)
bit 9-8
bit 7
Unimplemented: Read as ‘0’
TEMPCOMP: temperaure compensation enable bit
1= Temperature compensation is enabled
0= Temperature compensation is disabled (DEFAULT)
bit 6-5
bit 4-3
RESET <1:0>: Reset mode setting for ADCs
11= Both I1 and V1 are in Reset mode
10= V1 ADC is in Reset mode
01= I1 ADC is in Reset mode
00= Neither ADC is in Reset mode (DEFAULT)
SHUTDOWN <1:0>: Shutdown mode setting for ADCs
11= Both I1 and V1 are in Shutdown
10= V1 ADC is in Shutdown
01= I1 ADC is in Shutdown
00= Neither ADC is in Shutdown (DEFAULT)
bit 2
VREFEXT: Internal Voltage Reference Shutdown Control
1= Internal Voltage Reference Disabled
0= Internal Voltage Reference Enabled (DEFAULT)
bit 1-0
Unimplemented: Read as ‘0’
REGISTER 6-3:
ENERGY ACCUMULATION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
ENRG_CNTRL
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bits 15-1
bit 0
Unimplemented: Read as ‘0‘
ENRG_CNTRL: Energy Accumulation Control bit
1= Energy Accumulation is tuned on and all registers are accumulating
0= Energy Accumulation is turned off and all energy accumulation registers are reset to 0 (DEFAULT)
2015 Microchip Technology Inc.
DS20005442A-page 33
MCP39F521
The purpose of this register is two-fold: the number of
6.6
Range Register
right-bit shifting (division by 2RANGE) must be high
enough to prevent overflow in the output register, and
low enough to allow for the desired output resolution. It
is the user’s responsibility to set this register correctly
to ensure proper output operation for a given meter
design.
The Range register (Register 6-4) is a 32-bit register
that contains the number of right-bit shifts for the
following outputs, divided into separate bytes as
defined below:
• RMS Current
• RMS Voltage
For further information and example usage, see
Section 8.3, Single-Point Gain Calibrations at Unity
Power Factor.
• Power (Active, Reactive, Apparent)
Note that the power range byte operates across both
the active and reactive output registers and sets the
same scale.
.
REGISTER 6-4:
RANGE REGISTER
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
bit 31
bit 24
R/W-0
bit 23
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
POWER<7:0>
bit 16
R/W-0
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-1
CURRENT<7:0>
bit 8
R/W-0
R/W-0
bit 7
R/W-1
R/W-0
VOLTAGE<7:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-24
bit 23-16
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
POWER<7:0>: Sets the number of right-bit shifts for the Active and Reactive Power output registers
CURRENT<7:0>: Sets the number of right-bit shifts for the Current RMS output register
VOLTAGE<7:0>: Sets the number of right-bit shifts for the Voltage RMS output register
DS20005442A-page 34
2015 Microchip Technology Inc.
MCP39F521
7.2
Voltage Sag and Voltage Surge
Detection
7.0
7.1
EVENT OUTPUT PIN/EVENT
CONFIGURATION REGISTER
The event alarms for Voltage Sag and Voltage Surge
work differently compared to the Over Current and
Over Power events, which are tested against every
computation cycle. These two event alarms are
designed to provide a much faster interrupt if the
condition occurs. Note that neither of these two events
have a respective Hold register associated with them,
since the detection time is less than one line cycle.
Event Pin
The MCP39F521 device has one Event pin that can be
configured in three possible configurations. These
configurations are:
1. No event is mapped to the pin
2. Voltage Surge, Voltage Sag, Over Current, or
Over Power event is mapped to the pin. More
than one event can be mapped to the Event pin.
The calculation engine keeps track of a trailing
mean square of the input voltage, as defined by the
following equation:
3. Manual control of the Event pin.
These three configurations allow for the control of
external interrupts or hardware that is dependent on
the measured power, current or voltage. The Event
configuration register (Register 7-1) below describes
how these events and pins can be configured.
EQUATION 7-1:
2
2 f
0
LINE
V
= -------------------------
V
SA
n
f
SAMPLE
f
SAMPLE
n = – ------------------------- – 1
2 f
LINE
Therefore, at each data-ready occurrence, the value of
SA is compared to the programmable threshold set in
V
the Voltage Sag Limit register and Voltage Surge Limit
register to determine if a flag should be set. If either of
these events are masked to either the Event pin, a
logic-high interrupt will be given on these pins.
The Sag or Surge events can be used to quickly
determine if a power failure has occurred in the system.
2015 Microchip Technology Inc.
DS20005442A-page 35
MCP39F521
REGISTER 7-1:
EVENT CONFIGURATION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 31
bit 24
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
OVERPOW_PIN OVERCUR_PIN
VSURGE_PIN
VSAG_PIN
bit 16
bit 23
U-0
R/W-0
U-0
—
U-0
—
R/W
R/W
R/W-0
R/W-0
—
EVENT_MANU
OVERCUR_CL
OVERPOW_CL
VSUR_CL
VSAG_CL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VSUR_LA
VSAG_LA
OVERPOW_LA OVERCUR_LA
VSUR_TST
VSAG_TST
OVERPOW_TST OVERCUR_TST
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-24
bit 23
bit 22
bit 21
bit 20
bit 19
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
OVERPOW_PIN: Pin Operation for the Over Power event
1= Event mapped to Event pin only
0= Event not mapped to a pin (Default)
bit 18
bit 17
bit 16
OVERCUR_PIN: Pin Operation for the Over Current event
1= Event mapped to Event pin only
0= Event not mapped to a pin (Default)
VSURGE_PIN: Pin Operation for the Voltage Surge event
1= Event mapped to Event pin only
0= Event not mapped to a pin (Default)
VSAG_PIN: Pin Operation for the Voltage Sag event
1= Event mapped to Event pin only
0= Event not mapped to a pin (Default)
bit 15
bit 14
Unimplemented: Read as ‘0’
EVENT_MANU: Manual Control of the Event pin
1= Pin is logic high
0= Pin is logic low (Default)
bit 13-12
bit 11
Unimplemented: Read as ‘0’
OVERCUR_CL: Reset or clear bit for the Over Current event
1= Event is cleared
0= Event is not cleared (Default)
bit 10
bit 9
OVERPOW_CL: Reset or clear bit for the Over Power event
1= Event is cleared
0= Event is not cleared (Default)
VSUR_CL: Reset or clear bit for the Voltage Surge event
1= Event is cleared
0= Event is not cleared (Default)
DS20005442A-page 36
2015 Microchip Technology Inc.
MCP39F521
REGISTER 7-1:
EVENT CONFIGURATION REGISTER (CONTINUED)
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
VSAG_CL: Reset or clear bit for the Voltage Sag event
1= Event is cleared
0= Event is not cleared (Default)
VSUR_LA: Latching control of the Voltage Surge event
1= Event is latched and needs to be cleared
0= Event does not latch
VSAG_LA: Latching control of the Voltage Sag event
1= Event is latched and needs to be cleared
0= Event does not latch
OVERPOW_LA: Latching control of the Over Power event
1= Event is latched and needs to be cleared
0= Event does not latch
OVERCUR_LA: Latching control of the Over Current event
1= Event is latched and needs to be cleared
0= Event does not latch
VSUR_TST: Test control of the Voltage Surge event
1= Simulated event is turned on
0= Simulated Event is turned off
VSAG_TST: Test control of the Voltage Sag event
1= Simulated event is turned on
0= Simulated Event is turned off
OVERPOW_TST: Test control of the Over Power event
1= Simulated Event is turned on
0= Simulated Event is turned off
OVERCUR_TST: Test control of the Over Current event
1= Simulated Event is turned on
0= Simulated Event is turned off
Note:
Writing a 1to the Clear bit, clears the event, either real or simulated through test bits, and then returns to
a state of 0.
2015 Microchip Technology Inc.
DS20005442A-page 37
MCP39F521
8.3.1
USING THE AUTO-CALIBRATION
GAIN COMMAND
8.0
8.1
MCP39F521 CALIBRATION
Overview
By applying stable reference voltages and currents that
are equivalent to the values that reside in the target
Calibration Current, Calibration Voltage and Calibration
Active Power registers, the Auto-Calibration
Gaincommand can then be issued to the device.
Calibration compensates for ADC gain error,
component tolerances and overall noise in the system.
The device provides an on-chip calibration algorithm
that allows simple system calibration to be performed
quickly. The excellent analog performance of the
A/D converters on the MCP39F521 allows for a
After a successful calibration (response = ACK), a
Save Registers to Flashcommand can then be
issued to save the calibration constants calculated by
the device.
single point calibration and
command to achieve accurate measurements.
a
single calibration
The following registers are set when the
Auto-Calibration Gaincommand is issued:
Calibration can be done by either using the predefined
auto-calibration commands, or by writing directly to the
calibration registers. If additional calibration points are
required (AC offset, Phase Compensation, DC offset),
the corresponding calibration registers are available to
the user and will be described separately in this
section.
• Gain Current RMS
• Gain Voltage RMS
• Gain Active Power
When this command is issued, the MCP39F521
attempts to match the expected values to the
measured values for all three output quantities by
changing the gain register based on the following
formula:
8.2
Calibration Order
The proper steps for calibration need to be observed.
If the device has an external temperature sensor
attached, temperature calibration should be done first
by reading the value from the Thermistor Voltage
register and copying the value by writing to the Ambient
Temperature Reference Voltage register.
EQUATION 8-1:
Expected
Measured
GAIN
= GAIN
-------------------------
NEW
OLD
The same formula applies for voltage RMS, current
RMS and active power. Since the gain registers for all
three quantities are 16-bit numbers, the ratio of the
expected value to the measured value (which can be
modified by changing the Range register) and the
previous gain must be such that the equation yields a
valid number. Here the limits are set to be from 25,000
to 65,535. A new gain within this range for all three
limits will return an ACK for a successful calibration,
otherwise the command returns a NAK for a failed
calibration attempt.
If the device runs on the internal oscillator, the line
frequency must be calibrated next using the
Auto-Calibration Frequency command.
The single-point gain calibration at unity power factor
should be performed next.
If non-unity displacement power factor measurements
are a concern, then the next step should be phase
calibration, followed by reactive power gain calibration.
To summarize the order of calibration:
1. Temperature Calibration (optional)
2. Line Frequency Calibration (optional)
3. Gain Calibration at PF = 1
It is the user’s responsibility to ensure that the proper
range settings, PGA settings and hardware design
settings are correct to allow for successful calibration
using this command.
4. Phase Calibration at PF 1 (optional)
5. Reactive Gain Calibration at PF 1(optional)
8.3.2
EXAMPLE OF RANGE SELECTION
FOR VALID CALIBRATION
8.3
Single-Point Gain Calibrations at
Unity Power Factor
In this example, the user applies a calibration current
of 1A to an uncalibrated system. The indicated value
in the Current RMS register is 2300 with the system's
specific shunt value, PGA gain, etc. The user expects
to see a value of 1000 in the Current RMS register
when 1A current is applied, meaning 1.000A with
1 mA resolution. Other given values are:
When using the device in AC mode with the high-pass
filters turned on, most offset errors are removed and
only a single-point gain calibration is required.
Setting the gain registers to properly produce the
desired outputs can be done manually by writing to the
appropriate register. The alternative method is to use
the auto-calibration commands described in this
section.
• The existing value for Gain Current RMS is 33480
• The existing value for Range is 12
DS20005442A-page 38
2015 Microchip Technology Inc.
MCP39F521
By using Equation 8-2, the calculation for GainNEW
yields:
The GainNEW is much larger than the 16-bit limit of
65535, so fewer right-bit shifts must be introduced to
get the measured value closer to the expected value.
The user needs to compute the number of bit shifts
that will give a value lower than 65535. To estimate
this number:
EQUATION 8-2:
Expected
Measured
1000
2300
GAIN
= GAIN
--------------------------= 33480 -----------= 14556
NEW
OLD
14556 25 000
EQUATION 8-5:
145565
When using
the
Auto-Calibration Gain
----------------- = 2.2
65535
command, the result would be a failed calibration or a
NAK returned form the MCP39F521, because the
resulting GainNEW is less than 25,000.
2.2 rounds to the closest integer value of 2. The range
value changes to 12 – 2 = 10; there are 2 less right-bit
shifts.
The new measured value will be 2300 x 22 = 9200.
The solution is to use the Range register to bring the
measured value closer to the expected value, such
that a new gain value can be calculated within the
limits specified above.
EQUATION 8-6:
The Range register specifies the number of right-bit
shifts (equivalent to divisions by 2) after the
multiplication with the Gain Current RMS register.
Refer to Section 5.0, Calculation Engine (CE)
Description for information on the Range register.
Expected
--------------------------= 33480 --------------= 36391
OLD
10000
9200
GAIN
= GAIN
NEW
Measured
25 000 36391 65535
Incrementing the Range register by 1 unit, an
additional right-bit shift or ÷2 is included in the
calculation. Increasing the current range from 12 to 13
yields the new measured Current RMS register value
of 2300/2 = 1150. The expected (1000) and measured
(1150) are much closer now, so the expected new gain
should be within the limits:
The resulting new gain is within the limits and the
device successfully calibrates Current RMS and
returns an ACK.
8.4
Calibrating the Phase
Compensation Register
Phase compensation is provided to adjust for any
phase delay between the current and voltage path.
This procedure requires sinusoidal current and voltage
waveforms, with a significant phase shift between
them, and significant amplitudes. The recommended
displacement power factor for calibration is 0.5. The
procedure for calculating the phase compensation
register is as follows:
EQUATION 8-3:
Expected
Measured
1000
1150
GAIN
= GAIN
--------------------------= 33480 -----------= 29113
NEW
OLD
25 000 29113 65535
The resulting new gain is within the limits and the
device successfully calibrates Current RMS and
returns an ACK.
1. Determine what the difference is between the
angle corresponding to the measured power
factor (PFMEAS) and the angle corresponding to
the expected power factor (PFEXP), in degrees.
It can be observed that the range can be set to 14 and
the resulting new gain will still be within limits
(GainNEW = 58226). However, since this gain value is
close to the limit of the 16-bit Gain register, variations
from system to system (component tolerances, etc.)
might create a scenario where the calibration is not
successful on some units and there would be a yield
issue. The best approach is to choose a range value
that places the new gain in the middle of the bounds of
the gain registers described above.
EQUATION 8-7:
Value in PowerFactor Register
PFMEAS = --------------------------------------------------------------------------
32768
180
ANGLEMEAS = acosPFMEAS --------
180
ANGLEEXP = acosPFEXP --------
In a second example, when applying 1A, the user
expects an output of 1.0000A with 0.1 mA resolution.
The example is starting with the same initial values:
2. Convert this from degrees to the resolution
provided in Equation 8-8:
EQUATION 8-4:
EQUATION 8-8:
Expected
--------------------------= 33480 --------------= 145565
OLD
10000
2300
GAIN
= GAIN
= ANGLE
– ANGLE
40
NEW
145565 65535
Measured
MEAS
EXP
2015 Microchip Technology Inc.
DS20005442A-page 39
MCP39F521
3. Combine this additional phase compensation to
whatever value is currently in the phase
compensation, and update the register.
Equation 8-9 should be computed in terms of an
8-bit two's complement signed value. The 8-bit
result is placed in the least significant byte of the
16-bit Phase Compensation register.
8.6
Calibrating the Line Frequency
Register
The Line Frequency register contains a 16-bit number
with a value equivalent to the input line frequency as it
is measured on the voltage channel. When in
DC mode, this calculation is turned off and the register
will be equal to zero.
EQUATION 8-9:
The measurement of the line frequency is only valid
from 45 to 65 Hz.
PhaseCompensation
= PhaseCompensation
+
OLD
NEW
8.6.1
USING THE AUTO-CALIBRATION
FREQUENCY COMMAND
Based on Equation 8-9, the maximum angle in degrees
that can be compensated is ±3.2 degrees. If a larger
phase shift is required, contact your local Microchip
sales office.
By applying a stable reference voltage with a constant
line frequency that is equivalent to the value that
resides in the Line Frequency Ref, the
Auto-Calibration Frequency command can
then be issued to the device.
8.5
Offset/No-Load Calibrations
After a successful calibration (response = ACK), a
Save Registers to Flashcommand can then be
issued to save the calibration constants calculated by
the device.
During offset calibrations, no line voltage or current
should be applied to the system. The system should be
in a No-Load condition.
The
following
register
is
set
when
command is
the
8.5.1
AC OFFSET CALIBRATION
Auto-Calibration
Frequency
issued:
There are three registers associated with the AC Offset
Calibration:
• Gain Line Frequency
• Offset Current RMS
• Offset Active Power
• Offset Reactive Power
Note that the command is only required when running
off the internal oscillator. The formula used to calculate
the new gain is shown in Equation 8-1.
When computing the AC offset values, the respective
Gain and Range registers should be taken into
consideration according to the block diagrams in
Figures 5-2 and 5-4.
After
a
successful
offset
calibration,
a
Save Registers to Flash command can then be
issued to save the calibration constants calculated by
the device.
8.5.2
DC OFFSET CALIBRATION
In DC applications, the high-pass filter on the current
and voltage channels is turned off. To remove any
residual DC value on the current, the DC Offset Current
register adds to the A/D conversion immediately after
the ADC and prior to any other function.
DS20005442A-page 40
2015 Microchip Technology Inc.
MCP39F521
8.7
Temperature Compensation
8.8
Retrieving Factory Default
Calibration Values
The MCP39F521 measures the indication of the
temperature sensor and uses the value to compensate
the temperature variation of the shunt resistance and
the frequency of the internal RC oscillator.
After user calibration and a Save to Flashcommand
has been issued, it is possible to retrieve the factory
default calibration values. This can be done by writing
0xA5A5 to the Calibration Register Delimiter, issuing a
Save to Flash, and then resetting the part. This
procedure will retrieve all factory default calibration
values and will remain in this state until calibration has
been performed again, and a Save to Flash
command has been issued.
The same formula applies for Line Frequency, Current
RMS, Active Power and Reactive Power. The
temperature compensation coefficient depends on the
16-bit signed integer value of the corresponding
compensation register.
EQUATION 8-10:
y = x 1 + c T – T
CAL
TemperatureCompensation Register
c = ----------------------------------------------------------------------------------------------
M
2
Where:
x
=
Uncompensated Output (corresponding to
Line Frequency, Current RMS, Active Power
and Reactive Power)
y
c
=
=
Compensated Output
Temperature Compensation Coefficient
(depending on the shunt's Temperature
Coefficient of Resistance or on the internal RC
oscillator temperature frequency drift). There
are three registers: one for Line Frequency
compensation, one for Current compensation,
and one for power compensation (Active and
Reactive)
T
=
=
Thermistor Voltage (in 10-bit ADC units)
T
Ambient Temperature Reference Voltage. It
should be set at the beginning of the
calibration procedure, by reading the
thermistor voltage and writing its value to the
ambient temperature reference voltage
register.
CAL
M
=
=
26 (for Line Frequency compensation)
27 (for Current, Active Power and Reactive
Power)
When calibrating the temperature, the effect of the
compensation coefficients is minimal. The coefficients
need to be tuned when the difference between the
calibration temperature and the device temperature is
significant. It is recommended to use the default values
as starting points.
2015 Microchip Technology Inc.
DS20005442A-page 41
MCP39F521
There are three commands that support access to the
EEPROM array.
9.0
EEPROM
The data EEPROM is organized as 16-bit wide
memory. Each word is directly addressable, and is
readable and writable across the entire VDD range. The
MCP39F521 has 256 16-bit words of EEPROM that is
organized in 32 pages for a total of 512 bytes.
• EEPROM Page Read(0x42)
• EEPROM Page Write(0x50)
• EEPROM Bulk Erase(0x4F)
TABLE 9-1:
Command
EXAMPLE EEPROM COMMANDS AND DEVICE RESPONSE
Command ID BYTE 0
BYTE 1-N
# Bytes Successful Response
Page Read EEPROM
Page Write EEPROM
Bulk Erase EEPROM
0x42
0x50
0x4F
PAGE
PAGE + 16 BYTES OF DATA
---------
2
18
1
ACK, Data, Checksum
ACK
ACK
TABLE 9-2:
MCP39F521 EEPROM ORGANIZATION
Page
00
02
04
06
08
0A
0C
0E
0
0000
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
0010
0020
0030
0040
0050
0060
0070
0080
0090
00A0
00B0
00C0
00D0
00E0
00F0
0100
0110
0120
0130
0140
0150
0160
0170
0180
0190
01A0
01B0
01C0
01D0
01E0
01F0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DS20005442A-page 42
2015 Microchip Technology Inc.
MCP39F521
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
28-Lead QFN (5x5x0.9 mm)
Example
39F521
-E/MQ
1539256
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
e
3
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2015 Microchip Technology Inc.
DS20005442A-page 43
MCP39F521
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
NOTE 1
1
2
(DATUM B)
(DATUM A)
2X
0.10 C
2X
TOP VIEW
0.10 C
0.10 C
A1
C
A
SEATING
PLANE
28X
A3
0.08 C
0.10
SIDE VIEW
C A B
0.10
D2
C A B
E2
28X K
2
1
NOTE 1
28X L
N
28X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-140C Sheet 1 of 2
DS20005442A-page 44
2015 Microchip Technology Inc.
MCP39F521
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
N
28
0.50 BSC
0.90
e
A
A1
A3
E
E2
D
D2
b
L
0.80
0.00
1.00
0.05
0.02
0.20 REF
5.00 BSC
3.25
5.00 BSC
3.25
0.25
0.40
-
3.15
3.35
3.15
0.18
0.35
0.20
3.35
0.30
0.45
-
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-140C Sheet 2 of 2
2015 Microchip Technology Inc.
DS20005442A-page 45
MCP39F521
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern
With 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-2140A
DS20005442A-page 46
2015 Microchip Technology Inc.
MCP39F521
APPENDIX A: REVISION HISTORY
Revision A (September 2015)
• Original Release of this Document.
2015 Microchip Technology Inc.
DS20005442A-page 47
MCP39F521
NOTES:
DS20005442A-page 48
2015 Microchip Technology Inc.
MCP39F521
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
PART NO.
Device
[X]
X
/XX
Examples:
a) MCP39F521-E/MQ:
Extended temperature,
28LD 5x5 QFN package
Tape and Temperature Package
Reel
Range
b) MCP39F521T-E/MQ: Tape and Reel,
Extended temperature,
MCP39F521: I2C Power-Monitor with Calculation and
Energy Accumulation
28LD 5x5 QFN package
Device:
Tape and Reel Option: Blank
=
=
Standard packaging (tube or tray)
Tape and Reel(1)
T
Note 1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes
and is not printed on the device package.
Check with your Microchip sales office for
package availability for the Tape and Reel
option.
Temperature Range:
Package:
E
=
=
-40°C to +125°C (Extended)
MQ
Plastic Quad Flat, No Lead Package – 5x5x0.9 mm
body (QFN), 28-lead
2015 Microchip Technology Inc.
DS20005442A-page 49
MCP39F521
NOTES:
2015 Microchip Technology Inc.
DS20005442A-page 50
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-819-2
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2015 Microchip Technology Inc.
DS20005442A-page 51
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
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Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
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Atlanta
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Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Austin, TX
Tel: 512-257-3370
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
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Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Dongguan
Tel: 86-769-8702-9880
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
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Tel: 82-53-744-4301
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Tel: 86-571-8792-8115
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Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
Cleveland
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Poland - Warsaw
Tel: 48-22-3325737
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Fax: 216-447-0643
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Tel: 34-91-708-08-90
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Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
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Tel: 46-8-5090-4654
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Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Detroit
Novi, MI
UK - Wokingham
Tel: 44-118-921-5800
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
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Tel: 63-2-634-9065
Fax: 63-2-634-9069
Tel: 248-848-4000
Fax: 44-118-921-5820
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Tel: 281-894-5983
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Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
New York, NY
Tel: 631-435-6000
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
San Jose, CA
Tel: 408-735-9110
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
07/14/15
DS20005442A-page 52
2015 Microchip Technology Inc.
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