MCP4017T-103E/LT_技术文档

MCP4017/18/19

7-Bit Single I²C™ Digital POT with Volatile Memory in

SC70

Package Types

Features

Potentiometer

MCP4018

SC70-6

Rheostat

• Potentiometer or Rheostat configuration options

MCP4017

SC70-6

• 7-bit: Resistor Network Resolution

-

127 Resistors (128 Steps)

W

V

1

2

3

6

5

4

DD

A

V

A

1

2

3

6

5

4

DD

• Zero Scale to Full Scale Wiper operation

• R_ABResistances: 5 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ

• Low Wiper Resistance: 100Ω (typical)

• Low Tempco:

W

A

V

B

SS

V

W

SS

B

W

B

SCL

SDA

SCL

SDA

MCP4019

- Absolute (Rheostat): 50 ppm typical

(0°C to 70°C)

SC70-5

W

V

1

2

3

5

DD

W

- Ratiometric (Potentiometer): 10 ppm typical

• Simple I²C Protocol with read & write commands

• Brown-out reset protection (1.5V typical)

• Power-on Default Wiper Setting (Mid-scale)

• Low-Power Operation:

V

SS

B

A

SCL

SDA

4

• Wide Bandwidth (-3 dB) Operation:

- 2 MHz (typical) for 5.0 kΩ device

- 2.5 µA Static Current (typical)

• Extended temperature range (-40°C to +125°C)

• Very small package (SC70)

• Wide Operating Voltage Range:

- 2.7V to 5.5V - Device Characteristics

Specified

• Lead free (Pb-free) package

- 1.8V to 5.5V - Device Operation

Device Features

Resistance (typical)

VDD

Wiper

Configuration

Wiper Operating

(Ω)

Device

Options (kΩ)

Range ⁽¹⁾

Package

MCP4017

MCP4018

MCP4019

I²C 128

I²C 128 Potentiometer RAM

I²C 128

Rheostat RAM

Rheostat

RAM

5.0, 10.0, 50.0, 100.0

75

1.8V to 5.5V SC70-6

1.8V to 5.5V SC70-5

Note 1: Analog characteristics only tested from 2.7V to 5.5V

DS22147A-page 1

MCP4017/18/19

Device Block Diagram

A ⁽²⁾

V_DD

V_SS

Power-up/

Brown-out

Control

W

I²C Serial

Interface

Module,

Control

Logic, &

Memory

SCL

SDA

Resistor

Network 0

(Pot 0)

B ^{(1, 2)}

Note 1: Some configurations will have this

signal internally connected to ground.

2: In some configurations, this signal

may not be connected externally

Note 1

(internally floating or grounded).

Comparison of Similar Microchip Devices ⁽¹⁾

Resistance (typical)

V_DD

Wiper

Configuration

Operating

Device

Options (kΩ)

Range ⁽²⁾

Package

MCP4017

MCP4012

MCP4022

MCP4132

MCP4142

MCP4152

MCP4162

MCP4532

MCP4542

MCP4552

MCP4562

MCP4018

MCP4013

MCP4023

MCP4019

MCP4014

MCP4024

I²C 128

U/D 64

SPI 129

SPI 257

I²C 129

I²C 257

Rheostat

RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V

No

No SC70-6

No SOT-23-6

Yes SOT-23-6

No PDIP-8,

RAM

EE

2.1, 5.0, 10.0, 50.0

1.8V to 5.5V Yes

2.7V to 5.5V Yes

RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes

EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes

RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes

EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes

RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes

EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes

RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes

EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes

SOIC-8,

Yes

MSOP-8,

No

DFN-8

Yes

No MSOP-8,

DFN-8

Yes

No

Yes

I²C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V

No

No SC70-6

No SOT-23-6

Yes SOT-23-6

No SC70-5

No SOT-23-5

Yes SOT-23-5

U/D 64 Potentiometer RAM

U/D 64 Potentiometer EE

I²C 128

U/D 64

2.1, 5.0, 10.0, 50.0

1.8V to 5.5V Yes

2.7V to 5.5V Yes

Rheostat

RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V

No

RAM

EE

2.1, 5.0, 10.0, 50.0

1.8V to 5.5V Yes

2.7V to 5.5V Yes

Note 1: This table is broken into three groups by a thick line (and color coding). The unshaded devices in this table

are the devices described in this data sheet, while the shaded devices offer a comparable resistor network

configuration.

2: Analog characteristics only tested from 2.7V to 5.5V

DS22147A-page 2

MCP4017/18/19

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification

is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

Voltage on V_DDwith respect to V_SS..... -0.6V to +7.0V

Voltage on SCL, and SDA with respect to V_SS

-0.6V to 12.5V

.............................................................................

Voltage on all other pins (A, W, and B)

with respect to V_{SS ............................}-0.3V to V_DD+ 0.3V

Input clamp current, I_IK

(V_I< 0, V_I> V_DD, V_I> V_PPON HV pins)...........±20 mA

Output clamp current, I_OK

(V_O< 0 or V_O> V_DD) .......................................±20 mA

Maximum output current sunk by any Output pin

...........................................................................25 mA

Maximum output current sourced by any Output pin

...........................................................................25 mA

Maximum current out of V_SSpin ......................100 mA

Maximum current into V_DDpin .........................100 mA

Maximum current into A, W and B pins...........±2.5 mA

Package power dissipation (T_A= +50°C, T_J= +150°C)

SC70-5............................................................302 mW

SC70-6.................................................................. TBD

Storage temperature ..........................-65°C to +150°C

Ambient temperature with power applied

...........................................................-40°C to +125°C

ESD protection on all pins ........................≥ 4 kV (HBM)

........................................................................≥ 400V (MM)

Maximum Junction Temperature (T_J) .............. +150°C

DS22147A-page 3

MCP4017/18/19

AC/DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

–40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Supply Voltage

V_DD

2.7

1.8

—

5.5

V

Analog Characteristics specified

Digital Characteristics specified

RAM retention voltage (V_RAM) < V_BOR

V_DDStart Voltage

to ensure Wiper

Reset

V_BOR

V_DDRR

T_BORD

1.65

V_DDRise Rate to

ensure Power-on

Reset

(Note 7)

V/ms

µS

Delay after device

exits the reset

state

—

10

20

(V_DD> V_BOR

)

Supply Current

(Note 8)

I_DD

—

45

80

5

µA

Serial Interface Active,

Write all 0’s to Volatile Wiper

V_DD= 5.5V, F_SCL= 400 kHz

2.5

Serial Interface Inactive,

(Stop condition, SCL = SDA = V_IH),

Wiper = 0, V_DD= 5.5V

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

3: MCP4018 device only, includes V_WZSEand V_WFSE

.

4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

5: This specification by design.

6: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

7: POR/BOR is not rate dependent.

8: Supply current is independent of current through the resistor network

DS22147A-page 4

MCP4017/18/19

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

-502 devices (Note 1)

Resistance

(± 20%)

R_AB

4.0

8.0

5

10

6.0

12.0

60.0

120.0

kΩ

-103 devices (Note 1)

-503 devices (Note 1)

-104 devices (Note 1)

40.0

80.0

50

100

128

R_AB

Resolution

N

Taps No Missing Codes

Step Resistance

R_S

—

/

—

Ω

Note 5

(127)

100

155

50

Wiper Resistance

R_W

—

170

325

—

Ω

V_DD= 5.5 V, I_W= 2.0 mA, code = 00h

V_DD= 2.7 V, I_W= 2.0 mA, code = 00h

Nominal

Resistance

Tempco

ΔR_AB/ΔT

ppm/°C T_A= -20°C to +70°C

ppm/°C T_A= -40°C to +85°C

ppm/°C T_A= -40°C to +125°C

ppm/°C Code = Midscale (3Fh)

100

150

15

—

Ratiometeric

Tempco

ΔV_WB/ΔT

—

Resistor Terminal

Input Voltage

V_A,V_W,V_B

Vss

—

V_DD

V

Note 4, Note 5

Range (Terminals

A, B and W)

I_AW, W = Full Scale (FS)

I_BW, W = Zero Scale (ZS)

I_AWor I_BW, W = FS or ZS

I_AB, V_B= 0V, V_A= 5.5V,

Maximum current

through Terminal

(A, W or B)

I_T

—

2.5

mA

Terminal A

Terminal B

Terminal W

2.5

Note 5

1.38

R

_AB(MIN)= 4000

I_AB, V_B= 0V, V_A= 5.5V,

_AB(MIN)= 8000

I_AB, V_B= 0V, V_A= 5.5V,

_AB(MIN)= 40000

I_AB, V_B= 0V, V_A= 5.5V,

_AB(MIN)= 80000

—

0.688

0.138

0.069

mA

Terminal A

and

Terminal B

R

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

3: MCP4018 device only, includes V_WZSEand V_WFSE

.

4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

5: This specification by design.

6: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

7: POR/BOR is not rate dependent.

8: Supply current is independent of current through the resistor network

DS22147A-page 5

MCP4017/18/19

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Full Scale Error

(MCP4018 only)

(code = 7Fh)

V_WFSE

-3.0

-2.0

-0.5

—

-0.1

—

LSb

5 kΩ

2.7V ≤ V_DD≤ 5.5V

10 kΩ 2.7V ≤ V_DD≤ 5.5V

50 kΩ 2.7V ≤ V_DD≤ 5.5V

100 kΩ 2.7V ≤ V_DD≤ 5.5V

-0.1

—

-0.1

—

Zero Scale Error

(MCP4018 only)

(code = 00h)

V_WZSE

+0.1

±0.25

+3.0

+2.0

+0.5

5 kΩ

2.7V ≤ V_DD≤ 5.5V

—

10 kΩ 2.7V ≤ V_DD≤ 5.5V

50 kΩ 2.7V ≤ V_DD≤ 5.5V

100 kΩ 2.7V ≤ V_DD≤ 5.5V

—

Potentiometer

Integral

Non-linearity

INL

DNL

BW

-0.5

2.7V ≤ V_DD≤ 5.5V

MCP4018 device only (Note 2)

Potentiometer

Differential Non-

linearity

-0.25

±0.125 +0.25

LSb

2.7V ≤ V_DD≤ 5.5V

MCP4018 device only (Note 2)

Bandwidth -3 dB

(See Figure 2-83,

load = 30 pF)

—

2

—

MHz 5 kΩ

Code = 3Fh

1

MHz 10 kΩ Code = 3Fh

260

100

kHz

50 kΩ Code = 3Fh

100 kΩ Code = 3Fh

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

3: MCP4018 device only, includes V_WZSEand V_WFSE

.

4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

5: This specification by design.

6: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

7: POR/BOR is not rate dependent.

8: Supply current is independent of current through the resistor network

DS22147A-page 6

MCP4017/18/19

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Rheostat Integral

Non-linearity

MCP4018

R-INL

-2.0

-5.0

±0.5

+3.5

+2.0

+5.0

LSb

pF

5 kΩ

5.5V, I_W= 900 µA

2.7V, I_W= 430 µA (Note 6)

1.8V (Note 6)

See Section 2.0

(Note 3)

-2.0

-4.0

±0.5

+2.5

+2.0

+4.0

10 kΩ 5.5V, I_W= 450 µA

2.7V, I_W= 215 µA (Note 6)

MCP4017 and

MCP4019 devices

only (Note 3)

See Section 2.0

1.8V (Note 6)

-1.125

-1.5

±0.5

+1

+1.125

+1.5

50 kΩ 5.5V, I_W= 90 µA

2.7V, I_W= 43 µA (Note 6)

See Section 2.0

1.8V (Note 6)

-0.8

-1.125

±0.5

+0.8

100 kΩ 5.5V, I_W= 45 µA

+0.25 +1.125

2.7V, I_W= 21.5 µA (Note 6)

See Section 2.0

1.8V (Note 6)

Rheostat

Differential Non-

linearity

MCP4018

(Note 3)

MCP4017 and

MCP4019 devices

only (Note 3)

R-DNL

-0.5

±0.25

+0.5

5 kΩ

5.5V, I_W= 900 mA

2.7V, I_W= 430 µA (Note 6)

1.8V (Note 6)

-0.75

+0.75

See Section 2.0

-0.5

-0.75

±0.25

+0.5

+0.75

10 kΩ 5.5V, I_W= 450 µA

2.7V, I_W= 215 µA (Note 6)

See Section 2.0

1.8V (Note 6)

-0.375

±0.25 +0.375

50 kΩ 5.5V, I_W= 90 µA

-0.375

2.7V, I_W= 43 µA (Note 6)

See Section 2.0

1.8V (Note 6)

-0.375

±0.25 +0.375

100 kΩ 5.5V, I_W= 45 µA

2.7V, I_W= 21.5 µA (Note 6)

See Section 2.0

1.8V (Note 6)

Capacitance (P_A)

Capacitance (P_w)

Capacitance (P_B)

C_AW

C_W

—

75

120

75

—

f =1 MHz, Code = Full Scale

pF

C_BW

pF

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

3: MCP4018 device only, includes V_WZSEand V_WFSE

.

4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

5: This specification by design.

6: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

7: POR/BOR is not rate dependent.

8: Supply current is independent of current through the resistor network

DS22147A-page 7

MCP4017/18/19

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Digital Inputs/Outputs (SDA, SCK)

Schmitt Trigger

High Input

V_IH

0.7 V_DD

—

V

1.8V ≤ V_DD≤ 5.5V

Threshold

Schmitt Trigger

Low Input

V_IL

-0.5

—

0.3V_DD

V

Threshold

Hysteresis of

Schmitt Trigger

Inputs (Note 5)

V_HYS

—

N.A.

0.1V_DD

—

V

All inputs except SDA and SCL

V

_DD< 2.0V

100 kHz

400 kHz

SDA

and

SCL

N.A.

—

V

V_DD≥ 2.0V

V_DD< 2.0V

V_DD≥ 2.0V

0.1 V_DD

0.05 V_DD

V_SS

—

V

—

V

Output Low

Voltage (SDA)

V_OL

—

0.2V_DD

0.4

1

V

V_DD< 2.0V, I_OL= 1 mA

V_DD≥ 2.0V, I_OL= 3 mA

V_IN= V_DDand V_IN= V_SS

V_SS

—

V

Input Leakage

Current

I_IL

-1

—

µA

Pin Capacitance

RAM (Wiper) Value

Value Range

C_IN, C_OUT

—

10

—

pF

f_C= 400 kHz

N

0h

—

7Fh

hex

Wiper POR/BOR

Value

N_POR/BOR

3Fh

Power Requirements

Power Supply

Sensitivity

PSS

—

0.0005 0.0035

%/%

V_DD= 2.7V to 5.5V,

V_A= 2.7V, Code = 3Fh

(MCP4018 only)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

3: MCP4018 device only, includes V_WZSEand V_WFSE

.

4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

5: This specification by design.

6: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

7: POR/BOR is not rate dependent.

8: Supply current is independent of current through the resistor network

DS22147A-page 8

MCP4017/18/19

1.1

I²C Mode Timing Waveforms and Requirements

SCL

93

91

90

92

SDA

STOP

Condition

START

Condition

2

FIGURE 1-1:

I C Bus Start/Stop Bits Timing Waveforms.

2

TABLE 1-1:

I C BUS START/STOP BITS REQUIREMENTS

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage V_DDrange is described in Section 2.0 “Typical

Performance Curves”

Param.

Symbol

No.

Characteristic

Standard Mode

Min

Max

Units

Conditions

F_SCL

0

100

400

—

kHz C_b= 400 pF, 1.8V - 5.5V

Fast Mode

0

kHz C_b= 400 pF, 2.7V - 5.5V

D102

90

Cb

Bus capacitive

loading

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

—

pF

—

TSU:STA START condition

Setup time

4700

600

4000

600

4000

600

4000

600

ns

Only relevant for repeated

START condition

—

91

THD:STA START condition

Hold time

—

After this period the first

clock pulse is generated

—

92

TSU:STO STOP condition

Setup time

—

93

THD:STO STOP condition

Hold time

—

103

102

100

106

101

109

SCL

90

91

92

107

SDA

In

110

109

SDA

Out

Note 1: Refer to specification D102 (Cb) for load conditions.

2

FIGURE 1-2:

I C Bus Data Timing.

DS22147A-page 9

MCP4017/18/19

2

TABLE 1-2:

I C BUS DATA REQUIREMENTS (SLAVE MODE)

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in AC/DC characteristics

Parame-

ter No.

Sym

Characteristic

Min

Max Units

Conditions

100

T_HIGH

Clockhightime 100 kHz mode

400 kHz mode

4000

—

ns

1.8V-5.5V

600

—

ns

2.7V-5.5V

101

T_LOW

Clock low time

100 kHz mode

4700

1.8V-5.5V

2.7V-5.5V

400 kHz mode

100 kHz mode

1300

—

ns

102A ⁽⁵⁾

102B ⁽⁵⁾

103A ⁽⁵⁾

103B ⁽⁵⁾

106

T_RSCLSCL rise time

T_RSDASDA rise time

T_FSCLSCL fall time

T_FSDASDA fall time

1000

Cb is specified to be from

10 to 400 pF

400 kHz mode

100 kHz mode

20 + 0.1Cb

—

300

ns

1000

Cb is specified to be from

10 to 400 pF

400 kHz mode

100 kHz mode

20 + 0.1Cb

—

300

ns

Cb is specified to be from

10 to 400 pF

400 kHz mode

100 kHz mode

20 + 0.1Cb

—

40

ns

300

Cb is specified to be from

10 to 400 pF

20 + 0.1Cb ⁽⁴⁾

0

400 kHz mode

300

—

ns

THD:DAT Data input hold 100 kHz mode

1.8V-5.5V, Note 6

2.7V-5.5V, Note 6

(2)

time

400 kHz mode

0

—

ns

107

TSU:DAT Data input

setup time

100 kHz mode

250

400 kHz mode

100 kHz mode

100

—

ns

(1)

109

T_AA

Output valid

from clock

3450

400 kHz mode

100 kHz mode

—

900

—

ns

110

T_BUF

Bus free time

4700

Time the bus must be free

before a new transmission

can start

400 kHz mode

1300

—

ns

T_SP

Input filter spike 100 kHz mode

—

50

ns

Philips Spec states N.A.

suppression

400 kHz mode

(SDA and SCL)

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the

requirement tsu; DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it

must output the next data bit to the SDA line

TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before

the SCL line is released.

3: The MCP4018/MCP4019 device must provide a data hold time to bridge the undefined part between VIH

and VIL of the falling edge of the SCL signal. This specification is not a part of the I²C specification, but must

be tested in order to guarantee that the output data will meet the setup and hold specifications for the receiv-

ing device.

4: Use Cb in pF for the calculations.

5: Not Tested.

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not

unintentionally create a Start or Stop condition.

DS22147A-page 10

MCP4017/18/19

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +1.8V to +5.5V, V_SS= GND.

Parameters

Temperature Ranges

Sym

Min

Typ

Max

Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

T_A

-40

-65

—

+125

+150

°C

Thermal Resistance, 5L-SC70

(Note 1)

θ_JA

—

331

—

°C/W

Thermal Resistance, 6L-SC70

TBD

Note 1: Package Power Dissipation (PDIS) is calculated as follows:

_DIS= (T_J- T_A) / θ_JA

where: T_J= Junction Temperature, T_A= Ambient Temperature.

P

,

DS22147A-page 11

MCP4017/18/19

NOTES:

DS22147A-page 12

MCP4017/18/19

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

2

1.8

1.6

1.4

1.2

1

60

50

5.5V

40

400 kHz, 5.5V

30

0.8

0.6

0.4

0.2

0

20

100 kHz, 5.5V

100 kHz, 2.7V

400 kHz, 2.7V

2.7V

10

0

-40

0

40

Temperature (°C)

80

120

-40

0

40

Temperature (°C)

80

120

FIGURE 2-1:

Interface Active Current

) and Temperature

FIGURE 2-2:

(I ) vs. Temperature and V .

DD

Interface Inactive Current

(I ) vs. SCL Frequency (f

DD

SCL

SHDN

(V = 1.8V, 2.7V and 5.5V).

DD

DS22147A-page 13

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

85°C

DNL

125°C

85°C

125°C

INL

60

25°C

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

R_W

DNL

25°C

32

-40°C

R_W

-40°C

40

INL

20

0

64

96

0

32

64

96

Wiper Setting (decimal)

FIGURE 2-3:

5.0 kΩ : Pot Mode – R (Ω),

FIGURE 2-6:

5.0 kΩ : Rheo Mode – R

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 5.5V). (A = V , B = V ).

Temperature (V = 5.5V).(I = 1.4mA, B = V

)

DD

SS

DD

W

SS

300

260

220

180

140

100

60

3

-40C Rw

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

260

220

180

140

100

60

0.3

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

-40C INL

125C INL

-40C DNL

125C DNL

0.2

0.1

0

INL

125°C

2

125°C

85°C

25°C

85°

INL

1

R_W

-0.1

-0.2

-0.3

R_W

0

25°C

-40°C

DNL

-40°C

20

-1

0

32

64

96

0

32

64

96

Wiper Setting (decimal)

FIGURE 2-4:

5.0 kΩ : Pot Mode – R (Ω),

FIGURE 2-7:

5.0 kΩ : Rheo Mode – R

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 2.7V). (A = V , B = V

)

Temperature (V = 2.7V).(I = 450uA, B = V

)

SS

DD

SS

DD

W

2500

2000

1500

1000

500

44

39

34

29

24

19

14

9

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.35

2500

2000

1500

1000

500

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

INL

RW

INL

DNL

RW

4

0

-1

0

32

64

96

0

32

64

96

Wiper Setting (decimal)

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

FIGURE 2-5:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 1.8V). (A = V , B = V

5.0 kΩ : Pot Mode – R (Ω),

FIGURE 2-8:

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 1.8V). (I = TBD, B = V

5.0 kΩ : Rheo Mode – R

W

)

SS

DD

SS

DD

W

DS22147A-page 14

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

0.0

-0.2

-0.4

-0.6

-0.8

200

180

160

140

120

100

80

2.7V

5.5V

-1.0

-1.2

2.7

60

-1.4

40

5.5V

1.8V

-1.6

20

-1.8

0

-40

0

40

80

120

0

32

64

96

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-9:

5.0 kΩ : Full Scale Error

FIGURE 2-12:

5.0 kΩ : R

Tempco

BW

(FSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V).

ΔR / ΔT vs. Code.

DD

WB

1.8

1.6

1.4

1.2

1.8V

1.0

2.7

0.8

0.6

0.4

5.5V

0.2

0.0

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-10:

5.0 kΩ : Zero Scale Error

FIGURE 2-13:

5.0 kΩ : Power-Up Wiper

(ZSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V).

Response Time.

DD

5200

5180

5160

5140

5120

5100

Wiper

V_DD

1.8V

5080

2.7V

5060

5040

5020

5.5V

5000

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-11:

5.0 kΩ : Nominal Resistance

FIGURE 2-14:

5.0 kΩ : Digital Feedthrough

(Ω) vs. Temperature and V

.

(SCL signal coupling to Wiper pin).

DD

DS22147A-page 15

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-15:

5.0 kΩ : Write Wiper (40h →

FIGURE 2-18:

5.0 kΩ : Write Wiper (FFh →

3Fh) Settling Time (V =5.5V).

00h) Settling Time (V =5.5V).

DD

FIGURE 2-16:

5.0 kΩ : Write Wiper (40h

FIGURE 2-19:

5.0 kΩ : Write Wiper (FFh →

→ 3Fh) Settling Time (V =2.7V).

00h) Settling Time (V =2.7V).

DD

FIGURE 2-17:

5.0 kΩ : Write Wiper (40h →

FIGURE 2-20:

5.0 kΩ : Write Wiper (FFh →

3Fh) Settling Time (V =1.8V).

00h) Settling Time (V =1.8V).

DD

DS22147A-page 16

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

0.3

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.2

0.1

0

DNL

125°C

85°C

125°C

85°C

60

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

-40°C

R_W

-40°C

DNL

25°C

64

INL

40

INL

20

0

32

96

0

32

64

96

Wiper Setting (decimal)

FIGURE 2-21:

10 kΩ Pot Mode : R (Ω),

FIGURE 2-24:

10 kΩ Rheo Mode : R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 5.5V). (A = V , B = V

)

Temperature (V = 5.5V).(I = 450uA, B = V

)

SS

DD

SS

DD

W

300

260

220

180

140

100

60

3

-40C Rw

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

260

220

180

140

100

60

0.3

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

-40C INL

125C INL

-40C DNL

125C DNL

0.2

0.1

0

85°C

INL

2

125°C

R_W

85°

25°C

1

-0.1

-0.2

-0.3

DNL

R_W

0

25°C

32

INL

-40°C

DNL

20

-1

0

64

96

0

32

64

96

Wiper Setting (decimal)

FIGURE 2-22:

10 kΩ Pot Mode : R (Ω),

FIGURE 2-25:

10 kΩ Rheo Mode : R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 2.7V). (A = V , B = V

)

Temperature (V = 2.7V).(I = 210uA, B = V

)

SS

DD

SS

DD

W

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

39

34

29

24

19

14

9

0.35

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

3000

2000

1000

0

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

3000

2000

1000

0

DNL

INL

RW

DNL

4

-1

0

32

64

96

0

32

64

96

Wiper Setting (decimal)

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

FIGURE 2-23:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 1.8V). (A = V , B = V

10 kΩ Pot Mode : R (Ω),

FIGURE 2-26:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 1.8V). (I = TBD, B = V

10 kΩ Rheo Mode : R (Ω),

W

)

SS

DD

SS

DD

W

DS22147A-page 17

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

0.0

-0.1

-0.2

-0.3

-0.4

100

80

60

40

20

0

2.7V

-0.5

-0.6

-0.7

-0.8

-0.9

-1.0

5.5V

2.7

5.5V

64

1.8V

0

32

96

-40

0

40

80

120

Wiper Setting (decimal)

Ambient Temperature (°C)

FIGURE 2-30:

10 kΩ : R

Tempco

BW

FIGURE 2-27:

(FSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V).

10 kΩ : Full Scale Error

ΔR / ΔT vs. Code.

WB

DD

0.9

0.8

0.7

0.6

1.8V

0.5

2.7

0.4

0.3

0.2

0.1

0.0

5.5V

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-31:

Response Time.

10 kΩ : Power-Up Wiper

FIGURE 2-28:

(ZSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V).

10 kΩ : Zero Scale Error

DD

10200

10150

10100

Wiper

V_DD

1.8V

10050

10000

2.7

9950

5.5V

9900

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-32:

(SCL signal coupling to Wiper pin).

10 kΩ : Digital Feedthrough

FIGURE 2-29:

(Ω) vs. Temperature and V

10 kΩ : Nominal Resistance

.

DD

DS22147A-page 18

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-33:

10 kΩ : Write Wiper (40h →

FIGURE 2-36:

10 kΩ : Write Wiper (FFh →

3Fh) Settling Time (V =5.5V).

00h) Settling Time (V =5.5V).

DD

FIGURE 2-34:

10 kΩ : Write Wiper (40h →

FIGURE 2-37:

10 kΩ : Write Wiper (FFh →

3Fh) Settling Time (V =2.7V).

00h) Settling Time (V =2.7V).

DD

FIGURE 2-35:

10 kΩ : Write Wiper (40h →

FIGURE 2-38:

10 kΩ : Write Wiper (FFh →

3Fh) Settling Time (V =1.8V).

00h) Settling Time (V =1.8V).

DD

DS22147A-page 19

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

85°C

125°C

85°C

125°C

60

INL

DNL

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

INL

-40°C

R_W

-40°C

R_W

25°C

40

25°C

20

0

32

64

96

0

32

64

96

Wiper Setting (decimal)

FIGURE 2-39:

50 kΩ Pot Mode : R (Ω),

FIGURE 2-42:

50 kΩ Rheo Mode : R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 5.5V).

Temperature (V = 5.5V).(I = 90uA, B = V

)

SS

DD

W

300

260

220

180

140

100

60

0.3

0.2

0.1

0

-40C Rw

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C INL

-40C DNL

260

220

180

140

100

60

125°C

85°C

INL

125°C

85°

25°C

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

INL

DNL

R_W

DNL

R_W

25°C

-40°C

20

0

32

64

96

0

32

64

96

Wiper Setting (decimal)

FIGURE 2-40:

50 kΩ Pot Mode : R (Ω),

FIGURE 2-43:

50 kΩ Rheo Mode : R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 2.7V).

Temperature (V = 2.7V).(I = 45uA, B = V

)

SS

DD

W

10000

8000

6000

4000

2000

0

23

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

10000

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

125C INL 21

125C DNL

19

17

15

13

11

9

7

5

3

1

8000

6000

4000

2000

0

RW

DNL

INL

DNL

RW

-1

0

32

64

96

0

32

64

96

Wiper Setting (decimal)

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

FIGURE 2-41:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 1.8V).

50 kΩ Pot Mode : R (Ω),

FIGURE 2-44:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 1.8V). (I = TBD, B = V )

SS

50 kΩ Rheo Mode : R (Ω),

W

DD

W

DS22147A-page 20

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

0.00

-0.04

-0.08

100

80

60

40

20

0

2.7V

2.7

5.5V

-0.12

-0.16

1.8V

0

-40

40

80

120

0

32

64

96

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-45:

50 kΩ : Full Scale Error

FIGURE 2-48:

50 kΩ : R

Tempco

BW

(FSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V).

ΔR / ΔT vs. Code.

DD

WB

0.20

0.16

1.8V

0.12

2.7

0.08

0.04

5.5V

0.00

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-46:

50 kΩ : Zero Scale Error

FIGURE 2-49:

50 kΩ : Power-Up Wiper

(ZSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V).

Response Time.

DD

49800

49600

49400

Wiper

V_DD

49200

49000

48800

1.8V

2.7V

5.5V

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-47:

50 kΩ : Nominal Resistance

FIGURE 2-50:

50 kΩ : Digital Feedthrough

(Ω) vs. Temperature and V

.

(SCL signal coupling to Wiper pin).

DD

DS22147A-page 21

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-51:

50 kΩ : Write Wiper (40h →

FIGURE 2-54:

50 kΩ : Write Wiper (FFh →

3Fh) Settling Time (V =5.5V).

00h) Settling Time (V =5.5V).

DD

FIGURE 2-52:

50 kΩ : Write Wiper (40h →

FIGURE 2-55:

50 kΩ : Write Wiper (FFh →

3Fh) Settling Time (V =2.7V).

00h) Settling Time (V =2.7V).

DD

FIGURE 2-53:

50 kΩ : Write Wiper (40h →

FIGURE 2-56:

50 kΩ : Write Wiper (FFh →

3Fh) Settling Time (V =1.8V).

00h) Settling Time (V =1.8V).

DD

DS22147A-page 22

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

0.3

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.2

0.1

0

DNL

125°C

DNL

85°C

60

INL

25°C

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

R_W

-40°C

R_W

-40°C

40

25°C

INL

20

0

32

64

96

0

32

64

96

Wiper Setting (decimal)

FIGURE 2-57:

100 kΩ Pot Mode : R (Ω),

FIGURE 2-60:

100 kΩ Rheo Mode : R

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 5.5V).

Temperature (V = 5.5V). (I = 45uA, B = V

)

SS

DD

W

300

260

220

180

140

100

60

0.3

0.2

0.1

0

-40C Rw

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C INL

-40C DNL

260

220

180

140

100

60

125°C

85°C

DNL

INL

85°

125°C

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

DNL

R_W

INL

25°C

32

25°C

-40°C

20

0

64

96

0

32

64

96

Wiper Setting (decimal)

FIGURE 2-58:

100 kΩ Pot Mode : R (Ω),

FIGURE 2-61:

100 kΩ Rheo Mode : R

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 2.7V).

Temperature (V = 2.7V). (I = 21uA, B = V

)

SS

DD

W

15000

12500

10000

7500

5000

2500

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

15000

19

17

15

13

11

9

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

12500

10000

7500

5000

2500

0

RW

DNL

INL

7

5

DNL

3

INL

RW

1

-1

0

32

64

96

0

32

64

96

Wiper Setting (decimal)

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

FIGURE 2-59:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 1.8V).

100 kΩ Pot Mode : R (Ω),

FIGURE 2-62:

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Temperature (V = 1.8V). (I = TBD, B = V

100 kΩ Rheo Mode : R

W

)

SS

DD

W

DS22147A-page 23

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

0.00

100

80

60

40

20

0

-0.02

5.5V

-0.04

2.7V

2.7

-0.06

5.5V

1.8V

-0.08

-40

0

40

80

120

0

32

64

96

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-63:

100 kΩ : Full Scale Error

FIGURE 2-66:

100 kΩ : R

Tempco

BW

(FSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V).

ΔR / ΔT vs. Code.

DD

WB

0.12

0.08

1.8V

2.7

0.04

5.5V

0.00

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-64:

100 kΩ : Zero Scale Error

FIGURE 2-67:

100 kΩ : Power-Up Wiper

(ZSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V).

Response Time.

DD

99800

99600

99400

99200

99000

Wiper

V_DD

1.8V

98800

2.7V

98600

98400

98200

98000

97800

5.5V

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-65:

100 kΩ : Nominal

FIGURE 2-68:

100 kΩ : Digital

Resistance (Ω) vs. Temperature and V

.

Feedthrough (SCL signal coupling to Wiper pin).

DD

DS22147A-page 24

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-69:

100 kΩ : Write Wiper (40h

FIGURE 2-72:

100 kΩ : Write Wiper (FFh

→ 3Fh) Settling Time (V = 5.5V).

→ 00h) Settling Time (V = 5.5V).

DD

FIGURE 2-70:

100 kΩ : Write Wiper (40h

FIGURE 2-73:

100 kΩ : Write Wiper (FFh

→ 3Fh) Settling Time (V = 2.7V).

→ 00h) Settling Time (V = 2.7V).

DD

FIGURE 2-71:

100 kΩ : Write Wiper (40h

FIGURE 2-74:

100 kΩ : Write Wiper (FFh

→ 3Fh) Settling Time (V = 1.8V).

→ 00h) Settling Time (V = 1.8V).

DD

DS22147A-page 25

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

4

0.3

0.25

0.2

3.5

5.5V

3

2.7V (@ 3mA)

5.5V (@ 3mA)

2.5

2.7V

2

0.15

0.1

1.5

1

1.8V (@ 1mA)

0.05

0

0.5

1.8V

0

-40

0

40

80

120

-40

0

40

80

120

Temperature (°C)

FIGURE 2-75:

V

(SCL, SDA) vs. V and

FIGURE 2-77:

V

(SDA) vs. V and

IH

DD

OL

DD

Temperature.

2

1.5

1

1.2

1

5.5

5.5V

2.7V

0.8

0.6

0.4

0.2

2.7V

0.5

1.8V

0

-40

0

40

Temperature (°C)

80

120

-40

0

40

Temperature (°C)

80

120

FIGURE 2-76:

V

(SCL, SDA) vs. V and

FIGURE 2-78:

POR/BOR Trip point vs. V

DD

IL

DD

Temperature.

and Temperature.

DS22147A-page 26

MCP4017/18/19

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

10

0

Code = 7Fh

0

Code = 3Fh

Code = 1Fh

-10

-20

-30

-40

-50

-60

-10

-20

Code = 0Fh

Code = 1Fh

Code = 01h

-30

Code = 01h

-40

-50

100

1,000

10,000

100

1,000

10,000

Frequency (kHz)

FIGURE 2-79:

5 kΩ – Gain vs. Frequency

FIGURE 2-82:

100 kΩ – Gain vs.

(-3dB).

Frequency (-3dB).

2.1

Test Circuits

10

0

Code = 7Fh

Code = 3Fh

+5V

-10

-20

-30

+5V

Code = 0Fh

Code = 01h

A

B

Code = 1Fh

V

IN

W

V

+

-

OUT

-40

-50

-60

100

1,000

10,000

Frequency (kHz)

FIGURE 2-80:

10 kΩ – Gain vs. Frequency

(-3dB).

FIGURE 2-83:

Gain vs. Frequency Test

(-3dB).

10

0

Code = 7Fh

Code = 3Fh

Code = 1Fh

-10

-20

-30

-40

-50

Code = 0Fh

Code = 01h

-60

100

1,000

Frequency (kHz)

10,000

FIGURE 2-81:

50 kΩ – Gain vs. Frequency

(-3dB).

DS22147A-page 27

MCP4017/18/19

NOTES:

DS22147A-page 28

MCP4017/18/19

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

Additional descriptions of the device pins follow.

TABLE 3-1:

PINOUT DESCRIPTION FOR THE MCP4017/18/19

Pin Number

Name

Type

Buffer

Type

Function

MCP4017 MCP4018 MCP4019

(SC70-6) (SC70-6) (SC70-5)

V_DD

V_SS

SCL

SDA

B

1

2

1

2

1

2

P

—

Positive Power Supply Input

Ground

P

3

I/O

ST (OD) I²C Serial Clock pin

ST (OD) I²C Serial Data pin

4

5

—

5

—

5

A

Potentiometer Terminal B

Potentiometer Wiper Terminal

Potentiometer Terminal A

W

6

A

—

6

—

Legend: A = Analog input

ST (OD) = Schmitt Trigger with Open Drain

O = Output I/O = Input/Output

I = Input

P = Power

DS22147A-page 29

MCP4017/18/19

W pin can support both positive and negative current.

The voltage on terminal W must be between V_SSand

3.1

Positive Power Supply Input (V_DD)

The V_DDpin is the device’s positive power supply input.

The input power supply is relative to V_SSand can range

from 1.8V to 5.5V. A de-coupling capacitor on V_DD(to

V_DD

.

3.7

Potentiometer Terminal A

V_SS

)

is recommended to achieve maximum

performance.

The terminal A pin (available on some devices) is

connected to the internal potentiometer’s terminal A.

While the device’s voltage is in the range of 1.8V ≤ V_DD

< 2.7V, the Resistor Network’s electrical performance

of the device may not meet the data sheet

specifications.

The potentiometer’s terminal A is the fixed connection

to the Full Scale (0x7F tap) wiper value of the digital

potentiometer.

The terminal A pin is available on the MCP4018

devices. The terminal A pin does not have a polarity

relative to the terminal W pin. The terminal A pin can

support both positive and negative current. The voltage

3.2

Ground (V_SS)

The V_SSpin is the device ground reference.

on Terminal A must be between V_SSand V_DD

.

3.3

I²C Serial Clock (SCL)

The terminal A pin is not available on the MCP4017

and MCP4019 devices. For these devices, the

potentiometer’s terminal A is internally floating.

The SCL pin is the serial clock pin of the I²C interface.

The MCP401X acts only as a slave and the SCL pin

accepts only external serial clocks. The SCL pin is an

open-drain output. Refer to Section 5.0 “Serial

Interface - I²C Module” for more details of I²C Serial

Interface communication.

3.4

I²C Serial Data (SDA)

The SDA pin is the serial data pin of the I²C interface.

The SDA pin has a Schmitt trigger input and an

open-drain output. Refer to Section 5.0 “Serial

Interface - I²C Module” for more details of I²C Serial

Interface communication.

3.5

Potentiometer Terminal B

The terminal B pin (available on some devices) is

connected to the internal potentiometer’s terminal B.

The potentiometer’s terminal B is the fixed connection

to the Zero Scale (0x00 tap) wiper value of the digital

potentiometer.

The terminal B pin is available on the MCP4017 device.

The terminal B pin does not have a polarity relative to

the terminal W pin. The terminal B pin can support both

positive and negative current. The voltage on terminal

B must be between V_SSand V_DD

.

The terminal B pin is not available on the MCP4018

and MCP4019 devices. For these devices, the

potentiometer’s terminal B is internally connected to

V_SS

.

3.6

Potentiometer Wiper (W) Terminal

The terminal W pin is connected to the internal

potentiometer’s terminal W (the wiper). The wiper

terminal is the adjustable terminal of the digital

potentiometer. The terminal W pin does not have a

polarity relative to terminals A or B pins. The terminal

DS22147A-page 30

MCP4017/18/19

4.1.2

BROWN-OUT RESET

4.0

GENERAL OVERVIEW

When the device powers down, the device V_DDwill

cross the V_POR/V_BORvoltage. Once the V_DDvoltage

decreases below the V_POR/V_BORvoltage the following

happens:

The MCP4017/18/19 devices are general purpose

digital potentiometers intended to be used in

applications where a programmable resistance with

moderate bandwidth is desired.

• Serial Interface is disabled

This Data Sheet covers a family of three Digital

Potentiometer and Rheostat devices. The MCP4018

device is the Potentiometer configuration, while the

MCP4017 and MCP4019 devices are the Rheostat

configuration.

If the V_DDvoltage decreases below the V_RAMvoltage

the following happens:

• Volatile wiper registers may become corrupted

As the voltage recovers above the V_POR/V_BORvoltage

see Section 4.1.1 “Power-on Reset”.

Applications generally suited for the MCP401X devices

include:

Serial commands not completed due to a Brown-out

condition may cause the memory location to become

corrupted.

• Set point or offset trimming

• Sensor calibration

• Selectable gain and offset amplifier designs

• Cost-sensitive mechanical trim pot replacement

4.1.3

WIPER REGISTER (RAM)

The Wiper Register is volatile memory that starts

functioning at the RAM retention voltage (V_RAM). The

Wiper Register will be loaded with the default wiper

value when V_DDwill rise above the V_POR/V_BORvoltage.

As the Device Block Diagram shows, there are four

main functional blocks. These are:

• POR/BOR Operation

• Serial Interface - I²C Module

• Resistor Network

4.1.4

DEVICE CURRENTS

The current of the device can be classified into two

modes of the device operation. These are:

The POR/BOR operation and the Memory Map are

discussed in this section and the I²C and Resistor

Network operation are described in their own sections.

The Serial Commands commands are discussed in

Section 5.4.

• Serial Interface Inactive (Static Operation)

• Serial Interface Active

Static Operation occurs when a Stop condition is

received. Static Operation is exited when a Start

condition is received.

4.1

POR/BOR Operation

The Power-on Reset is the case where the device is

having power applied to it from V_SS. The Brown-out

Reset occurs when a device had power applied to it,

and that power (voltage) drops below the specified

range.

The devices RAM retention voltage (V_RAM) is lower

than the POR/BOR voltage trip point (V_POR/V_BOR). The

maximum V_POR/V_BORvoltage is less then 1.8V.

When V_POR/V_BOR< V_DD< 2.7V, the Resistor Network’s

electrical performance may not meet the data sheet

specifications. In this region, the device is capable of

reading and writing to its volatile memory if the proper

serial command is executed.

Table 4-1 shows the digital pot’s level of functionality

across the entire V_DDrange, while Figure 4-1 illustrates

the Power-up and Brown-out functionality.

4.1.1

POWER-ON RESET

When the device powers up, the device V_DDwill cross

the V_POR/V_BORvoltage. Once the V_DDvoltage crosses

the V_POR/V_BORvoltage, the following happens:

• Volatile wiper register is loaded with the default

wiper value (3Fh)

• The device is capable of digital operation

DS22147A-page 31

MCP4017/18/19

TABLE 4-1:

V_DDLevel

DEVICE FUNCTIONALITY AT EACH V REGION (NOTE 1)

DD

Serial

Potentiometer

Terminals

Wiper Setting

Comment

Interface

V_DD< V_BOR< 1.8V Ignored

“unknown”

Unknown

V_BOR≤ V_DD< 1.8V “Unknown” Operational with

Wiper Register loaded

with POR/BOR value

reduced electrical

specs

1.8V ≤ V_DD< 2.7V Accepted Operational with

Wiper Register

determines Wiper

Setting

Electrical performance may not

meet the data sheet specifications.

reduced electrical

specs

2.7V ≤ V_DD≤ 5.5V Accepted Operational

Wiper Register

determines Wiper

Setting

Meets the data sheet specifications

Note 1: For system voltages below the minimum operating voltage, the customer will be recommended to use a

voltage supervisor to hold the system in reset. This will ensure that MCP4017/18/19 commands are not

attempted out of the operating range of the device.

Normal Operation Range

Outside Specified

V_DD

AC/DC Range

2.7V

1.8V

V_POR/BOR

V_RAM

V_SS

Analog

Characteristics

not specified

Characteristics not specified

Device’s Serial

Interface is

V_BORDelay

“Not Operational”

Wiper Forced to Default POR/BOR setting

FIGURE 4-1:

Power-up and Brown-out.

DS22147A-page 32

MCP4017/18/19

5.1

I²C I/O Considerations

5.0

SERIAL INTERFACE -

I C MODULE

2

I²C specifications require active low, passive high

functionality on devices interfacing to the bus. Since

devices may be operating on separate power supply

sources, ESD clamping diodes are not permitted. The

specification recommends using open drain transistors

tied to V_SS(common) with a pull-up resistor. The

specification makes some general recommendations

on the size of this pull-up, but does not specify the

exact value since bus speeds and bus capacitance

impacts the pull-up value for optimum system

performance.

A 2-wire I²C serial protocol is used to write or read the

digital potentiometer’s wiper register. The I²C protocol

utilizes the SCL input pin and SDA input/output pin.

The I²C serial interface supports the following features.

• Slave mode of operation

• 7-bit addressing

• The following clock rate modes are supported:

- Standard mode, bit rates up to 100 kb/s

- Fast mode, bit rates up to 400 kb/s

• Support Multi-Master Applications

Common pull-up values range from 1 kΩ to a max of

~10 kΩ. Power sensitive applications tend to choose

higher values to minimize current losses during

communication but these applications also typically

The serial clock is generated by the Master.

The I²C Module is compatible with the Phillips I²C

specification. Phillips only defines the field types, field

lengths, timings, etc. of a frame. The frame content

defines the behavior of the device. The frame content

for the MCP4017, MCP4018, and MCP4019 devices

are defined in this section of the Data Sheet.

utilize lower V_DD

.

The SDA and SCL float (are not driving) when the

device is powered down.

A "glitch" filter is on the SCL and SDA pins when the pin

is an input. When these pins are an output, there is a

slew rate control of the pin that is independent of device

frequency.

Figure 5-1 shows a typical I²C bus configurations.

Single I²C Bus Configuration

5.1.1

SLOPE CONTROL

The device implements slope control on the SDA

output. The slope control is defined by the fast mode

specifications.

Device 1

Device 2

Device n

Device 3

Host

Controller

For Fast (FS) mode, the device has spike suppression

and Schmidt trigger inputs on the SDA and SCL pins.

Device 4

2

FIGURE 5-1:

Typical Application I C Bus

Configurations.

Refer to Section 2.0 “Typical Performance Curves”,

AC/DC Electrical Characteristics table for detailed input

threshold and timing specifications.

DS22147A-page 33

MCP4017/18/19

I²C Bit Definitions

If the Slave Address is not valid, the Slave Device will

issue a Not A (A). The A bit will have the SDA signal

high.

5.2

I²C bit definitions include:

• Start Bit

If an error condition occurs (such as an A instead of A)

then an START bit must be issued to reset the

command state machine.

• Data Bit

• Acknowledge (A) Bit

• Repeated Start Bit

• Stop Bit

TABLE 5-1:

MCP4017/18/19 A / A

RESPONSES

• Clock Stretching

Acknowledge

Bit Response

Figure 5-8 shows the waveform for these states.

Event

Comment

5.2.1

START BIT

General Call

A

The Start bit (see Figure 5-2) indicates the beginning of

a data transfer sequence. The Start bit is defined as the

SDA signal falling when the SCL signal is “High”.

SlaveAddress A

valid

SlaveAddress A

not valid

I²C Module Resets,

or a “Don’t Care” if

the collision occurs

on the Masters

“Start bit”.

2nd Bit

1st Bit

Bus Collision N.A.

SDA

SCL

S

FIGURE 5-2:

Start Bit.

5.2.2 DATA BIT

5.2.4

REPEATED START BIT

The SDA signal may change state while the SCL signal

is Low. While the SCL signal is High, the SDA signal

MUST be stable (see Figure 5-3).

The Repeated Start bit (see Figure 5-5) indicates the

current Master Device wishes to continue

communicating with the current Slave Device without

releasing the I²C bus. The Repeated Start condition is

the same as the Start condition, except that the

Repeated Start bit follows a Start bit (with the Data bits

+ A bit) and not a Stop bit.

2nd Bit

1st Bit

SDA

SCL

The Start bit is the beginning of a data transfer

sequence and is defined as the SDA signal falling when

the SCL signal is “High”.

S

FIGURE 5-3:

Data Bit.

Note 1: A bus collision during the Repeated Start

5.2.3 ACKNOWLEDGE (A) BIT

condition occurs if:

The A bit (see Figure 5-4) is a response from the Slave

device to the Master device. Depending on the context

of the transfer sequence, the A bit may indicate

different things. Typically the Slave device will supply

an A response after the Start bit and 8 “data” bits have

been received. The A bit will have the SDA signal low.

• SDA is sampled low when SCL goes

from low to high.

• SCL goes low before SDA is asserted

low. This may indicate that another mas-

ter is attempting to transmit a data "1".

SDA

SCL

D0

A

1st Bit

SDA

SCL

8

9

FIGURE 5-4:

Acknowledge Waveform.

Sr = Repeated Start

FIGURE 5-5:

Repeat Start Condition

Waveform.

DS22147A-page 34

MCP4017/18/19

5.2.5

STOP BIT

5.2.7

ABORTING A TRANSMISSION

The Stop bit (see Figure 5-6) Indicates the end of the

I²C Data Transfer Sequence. The Stop bit is defined as

the SDA signal rising when the SCL signal is “High”.

A Stop bit resets the I²C interface of the other devices.

If any part of the I²C transmission does not meet the

command format, it is aborted. This can be intentionally

accomplished with a START or STOP condition. This is

done so that noisy transmissions (usually an extra

START or STOP condition) are aborted before they

corrupt the device.

A / A

SDA

SCL

2

5.2.8

IGNORING AN I C TRANSMISSION

AND “FALLING OFF” THE BUS

The MCP4017/18/19 expects to receive entire, valid

I²C commands and will assume any command not

defined as a valid command is due to a bus corruption

and will enter a passive high condition on the SDA

signal. All signals will be ignored until the next valid

START condition and CONTROL BYTE are received.

P

FIGURE 5-6:

Transmit Mode.

Stop Condition Receive or

5.2.6

CLOCK STRETCHING

“Clock Stretching” is something that the Secondary

Device can do, to allow additional time to “respond” to

the “data” that has been received.

The MCP4017/18/19 will not strech the clock signal

(SCL) since memory read accesses occur fast enough.

SDA

SCL

S

1st 2nd 3rd 4th 5th 6th 7th 8th A/A 1st 2nd 3rd 4th 5th 6th 7th 8th A/A

P

Bit Bit Bit Bit Bit Bit Bit Bit

2

FIGURE 5-7:

Typical 16-bit I C Waveform Format.

SDA

SCL

Data allowed

to change

Data or

A valid

STOP

Condition

START

Condition

2

FIGURE 5-8:

I C Data States and Bit Sequence.

DS22147A-page 35

MCP4017/18/19

2

5.2.9

I C COMMAND PROTOCOL

TABLE 5-2:

Device

DEVICE I C ADDRESS

I²C Address

Comment

The MCP4017/18/19 is a slave I²C device which

supports 7-bit slave addressing. The slave address

contains seven fixed bits. Figure 5-9 shows the control

byte format.

MCP4017

MCP4018

MCP4019

‘0101111’

5.2.9.1

Control Byte (Slave Address)

The Control Byte is always preceded by a START

condition. The Control Byte contains the slave address

consisting of seven fixed bits and the R/W bit. Figure 5-

9 shows the control byte format and Table 5-2 shows

the I²C address for the devices.

5.2.9.2

Hardware Address Pins

The MCP4017/MCP4018/MCP4019 does not support

hardware address bits.

5.2.10

GENERAL CALL

The General Call is a method that the Master device

can communicate with all other Slave devices.

Slave Address

S

A6 A5 A4 A3 A2 A1 A0 R/W

“0” “1” “0” “1” “1” “1” “1”

A/A

The MCP4017/18/19 devices do not respond to

General Call address and commands, and therefore

the communications are Not Acknowledged.

Start

bit

R/W bit

R/W = 0 = write

R/W = 1 = read

A bit (controlled by slave device)

A = 0 = Slave Device Acknowledges byte

A = 1 = Slave Device does not Acknowledge byte

FIGURE 5-9:

I C Control Byte.

Slave Address Bits in the

2

Second Byte

S

0

A

x

X

x

0

A

P

General Call Address

“7-bit Command”

Reserved 7-bit Commands (By I²C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000)

‘0000 011’b - Reset and write programmable part of slave address by hardware.

‘0000 010’b - Write programmable part of slave address by hardware.

‘0000 000’b - NOT Allowed

The Following is a “Hardware General Call” Format

Second Byte

n occurrences of (Data + A / A)

A x X A P

S

0

A

x

X

x

1

x

X

x

General Call Address

“7-bit Command”

This indicates a “Hardware General Call”

MCP4016/7/8/9 will ignore this byte and

all following bytes (and A), until

a Stop bit (P) is encountered.

FIGURE 5-10:

General Call Formats.

DS22147A-page 36

MCP4017/18/19

The Stop bit terminates the current I²C bus activity. The

MCP4017/18/19 wait to detect the next Start condition.

This sequence does not effect any other I²C devices

which may be on the bus, as they should disregard this

as an invalid command.

5.3

Software Reset Sequence

Note:

This technique should be supported by

any I²C compliant device. The 24xxxx I²C

Serial EEPROM devices support this tech-

nique, which is documented in AN1028.

At times it may become necessary to perform a

Software Reset Sequence to ensure the MCP4017/18/

19 device is in a correct and known I²C Interface state.

This only resets the I²C state machine.

5.4

Serial Commands

The MCP4017/18/19 devices support

commands. These commands are:

2

serial

• Write Operation

• Read Operations

This is useful if the MCP4017/18/19 device powers up

in an incorrect state (due to excessive bus noise, etc),

or if the Master Device is reset during communication.

Figure 5-11 shows the communication sequence to

software reset the device.

S

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’

S

P

Nine bits of ‘1’

Start bit

Start

bit

Stop bit

FIGURE 5-11:

Software Reset Sequence

Format.

The 1st Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

Master Device.In this mode, the device is monitoring

the data bus in Receive mode and can detect the Start

bit forces an internal Reset.

The nine bits of ‘1’ are used to force a Reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP4017/18/19 is driving an A

on the I²C bus, or is in output mode (from a Read

command) and is driving a data bit of ‘0’ onto the I²C

bus. In both of these cases, the previous Start bit could

not be generated due to the MCP4017/18/19 holding

the bus low. By sending out nine ‘1’ bits, it is ensured

that the device will see a A (the Master Device does not

drive the I²C bus low to acknowledge the data sent by

the MCP4017/18/19), which also forces the MCP4017/

18/19 to reset.

The 2nd Start bit is sent to address the rare possibility

of an erroneous write. This could occur if the Master

Device was reset while sending a Write command to

the MCP4017/18/19, AND then as the Master Device

returns to normal operation and issues a Start condition

while the MCP4017/18/19 is issuing an A. In this case

if the 2nd Start bit is not sent (and the Stop bit was sent)

the MCP4017/18/19 could initiate a write cycle.

Note:

The potential for this erroneous write

ONLY occurs if the Master Device is reset

while sending a Write command to the

MCP4017/18/19.

DS22147A-page 37

MCP4017/18/19

5.4.1

WRITE OPERATION

5.4.2

READ OPERATIONS

The read operation requires the START condition,

Control Byte, Acknowledge, Data Byte, the master

generating the A and STOP condition. The Control

Byte requires the R/W bit equal to a logic one (R/W =

1) to generate a read sequence. The MCP4017/18/19

will A the Slave Address Byte and A all the Data Bytes.

The I²C Master will A the Slave Address Byte and the

last Data Byte. If there are multiple Data Bytes, the I²C

Master will A all Data Bytes except the last Data Byte

(which it will A).

The write operation requires the START condition,

Control Byte, Acknowledge, Data Byte, Acknowledge

and STOP (or RESTART) condition. The Control (Slave

Address) Byte requires the R/W bit equal to a logic zero

(R/W = “0”) to generate a write sequence. The

MCP4017/18/19 is responsible for generating the

Acknowledge (A) bits.

Data is written to the MCP4017/18/19 after every byte

transfer (during the A bit). If a STOP or RESTART

condition is generated during a data transfer (before

the A bit), the data will not be written to MCP4017/18/

19.

The MCP4017/18/19 maintains control of the SDA

signal until all data bits have been clocked out.

The command is terminated once a Stop (P) condition

occurs. Refer to Figure 5-13 for the read command

sequence. For a single read, the master sends a STOP

or RESTART condition after the 1st data byte (and A

bit) is sent from the slave.

Data bytes may be written after each Acknowledge.

The command is terminated once a Stop (P) condition

occurs. Refer to Figure 5-12 for the write sequence.

For a single byte write, the master sends a STOP or

RESTART condition after the 1st data byte is sent.

Figure 5-14 shows the I²C communication behavior of

the Master Device and the MCP4017/18/19 device and

the resultant I²C bus values.

The MSb of each Data Byte is a don’t care, since the

wiper register is only 7-bits wide.

Figure 5-14 shows the I²C communication behavior of

the Master Device and the MCP4017/18/19 device and

the resultant I²C bus values.

Fixed

Address

Read/Write bit (“0” = Write)

x D6 D5 D4

S

0

1

0

1

1 1 0 A

D3 D2 D1 D0 A x D6 D5 D4 D3 D2 D1 D0 A

Data Byte

STOP bit

Slave Address Byte

x D6 D5 D4

P

D3 D2 D1 D0 A x D6 D5 D4 D3 D2 D1 D0 A

Data Byte

Legend

S = Start Condition

P = Stop Condition

A = Acknowledge

X = Don’t Care

R/W = Read/Write bit

D6, D5, D4, D3, D2, D1, D0 = Data bits

2

FIGURE 5-12:

I C Write Command Format.

DS22147A-page 38

MCP4017/18/19

Fixed

Address

Read/Write bit (“1” = Read)

0 D6 D5 D4

S

0

1

0

1

1 1 1 A

D3 D2 D1 D0 A(1)0 D6 D5 D4 D3 D2 D1 D0 A(1)

Data Byte

STOP bit

(2)

Slave Address Byte

0 D6 D5 D4

P

D3 D2 D1 D0 A(1)0 D6 D5 D4 D3 D2 D1 D0 A

Data Byte

Legend

S = Start Condition

P = Stop Condition

A = Acknowledge

X = Don’t Care

R/W = Read/Write bit

Note 1 = Data bits

Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP4017/18/19

will abort this transfer and release the bus.

2: The Master Device will A, and the MCP4017/18/19 will release the bus so the Master Device can

generate a Stop or Repeated Start condition.

2

FIGURE 5-13:

I C Read Command Format.

DS22147A-page 39

MCP4017/18/19

Write 1 Byte

R

/

S Slave Address

W A Data Byte ⁽¹⁾

A P

Master

S 0 1 0 1 1 1 1 0 1 x d d d d d d d 1 P

MCP4017/18/19

0

I²C Bus

S 0 1 0 1 1 1 1 0 0 x d d d d d d d 0 P

Write 2 Bytes

R

/

S Slave Address

S 0 1 0 1 1 1 1 0 1 x d d d d d d d 1 x d d d d d d d 1 P

W A Data Byte ⁽¹⁾

A Data Byte ⁽¹⁾

A P

Master

MCP4017/18/19

0

I²C Bus

S 0 1 0 1 1 1 1 0 0 x d d d d d d d 0 x d d d d d d d 1 P

Read 1 Byte

R

/

S Slave Address

W A Data Byte

A P

1 P

Master

S 0 1 0 1 1 1 1 1 1

MCP4017/18/19

0 0 d d d d d d d 1

I²C Bus

S 0 1 0 1 1 1 1 1 0 0 d d d d d d d 1 P

Read 2 Bytes

R

/

S Slave Address

W A Data Byte

A Data Byte

A P

Master

S 0 1 0 1 1 1 1 1 1

0

1 P

MCP4017/18/19

I²C Bus

0 0 d d d d d d d 1 0 d d d d d d d 1

S 0 1 0 1 1 1 1 1 0 0 d d d d d d d 0 0 d d d d d d d 1 P

Note 1: For Write Commands, the MSb of the Data Byte is a don’t care since the wiper register is only 7-bits wide.

2

FIGURE 5-14:

I C Communication Behavior.

DS22147A-page 40

MCP4017/18/19

6.0

RESISTOR NETWORK

A

The Resistor Network is made up of two parts. These

are:

7Fh

RW ⁽¹⁾

N = 127

• Resistor Ladder

• Wiper

R_S

N = 126

N = 125

7Eh

RW ⁽¹⁾

7Dh

RW ⁽¹⁾

Figure 6-1 shows a block diagram for the resistive

network.

Digital potentiometer applications can be divided into

two resistor network categories:

• Rheostat configuration

• Potentiometer (or voltage divider) configuration

W

The MCP4017 is a true rheostat, with terminal B and

the wiper (W) of the variable resistor available on pins.

N = 1

01h

RW ⁽¹⁾

The MCP4018 device offers

a voltage divider

(potentiometer) with terminal B internally connected to

ground.

R_S

N = 0

00h

RW ⁽¹⁾

The MCP4019 device is a Rheostat device with

terminal A of the resistor floating, terminal B internally

connected to ground, and the wiper (W) available on

pin.

B

Analog

Mux

Note 1: The wiper resistance is tap dependent.

That is, each tap selection resistance

has a small variation. This variation has

more effect on devices with smaller R_AB

resistance (5.0 kΩ).

6.1

Resistor Ladder Module

The resistor ladder is a series of equal value resistors

(R_S) with a connection point (tap) between the two

resistors. The total number of resistors in the series

(ladder) determines the R_ABresistance (see Figure 6-

1). The end points of the resistor ladder are connected

to the device Terminal A and Terminal B pins. The R_AB

(and R_S) resistance has small variations over voltage

and temperature.

FIGURE 6-1:

Resistor Network Block

Diagram.

TABLE 6-1:

WIPER SETTING MAP

Wiper Setting Properties

The Resistor Network has 127 resistors in a string

between terminal A and terminal B. This gives 7-bits of

resolution.

07Fh

07Eh - 040h

03Fh

Full Scale (W = A)

W = N

The wiper can be set to tap onto any of these 127

resistors thus providing 128 possible settings

(including terminal A and terminal B). This allows zero

scale to full scale connections.

W = N (Mid Scale)

W = N

03Eh - 001h

000h

Zero Scale (W = B)

A wiper setting of 00h connects the Terminal W (wiper)

to Terminal B (Zero Scale). A wiper setting of 3Fh is the

Mid scale setting. A wiper setting of 7Fh connects the

Terminal W (wiper) to Terminal A (Full Scale). Table 6-

1 illustrates the full wiper setting map.

Terminal A and B as well as the wiper W do not have a

polarity. These terminals can support both positive and

negative current.

DS22147A-page 41

MCP4017/18/19

Step resistance (R_S) is the resistance from one tap

setting to the next. This value will be dependent on the

A POR/BOR event will load the Volatile Wiper register

value with the default value. Table 6-3 shows the

default values offered.

R_ABvalue that has been selected. Equation 6-1 shows

the calculation for the step resistance while Table 6-2

shows the typical step resistances for each device.

TABLE 6-3:

DEFAULT FACTORY

SETTINGS SELECTION

EQUATION 6-1:

R CALCULATION

S

Default POR Wiper

Resistance Typical

R_AB

Code ⁽¹⁾

Code

R_ABValue

R_S= ---------

Setting

127

-502

5.0 kΩ

10.0 kΩ

50.0 kΩ

100.0 kΩ

Mid-scale

3Fh

Equation 6-2 illustrates the calculation used to

determine the resistance between the wiper and

terminal B.

-103

-503

-104

Note 1: Custom POR/BOR Wiper Setting options

are available, contact the local Microchip

Sales Office for additional information.

Custom options have minimum volume

requirements.

EQUATION 6-2:

R

CALCULATION

WB

R_AB

R_WB= ------------- + R_W

127

N

N = 0 to 127 (decimal)

The digital potentiometer is available in four nominal

resistances (R_AB) where the nominal resistance is

defined as the resistance between terminal A and

terminal B. The four nominal resistances are 5 kΩ,

10 kΩ, 50 kΩ, and 100 kΩ.

The total resistance of the device has minimal variation

due to operating voltage (see Figure 2-11, Figure 2-29,

Figure 2-47, or Figure 2-65).

TABLE 6-2:

STEP RESISTANCES

Resistance (Ω)

Part Number

Total

(R_AB

Case

Step (R_S)

)

Min.

4000

31.496

39.370

47.244

62.992

78.740

94.488

314.961

393.701

472.441

629.921

MCP4017/18/19-502E Typical 5000

Max.

Min.

6000

8000

MCP4017/18/19-103E Typical 10000

Max.

Min.

12000

40000

MCP4017/18/19-503E Typical 50000

Max.

Min.

60000

80000

MCP4017/18/19-104E Typical 100000 787.402

Max. 120000 944.882

DS22147A-page 42

MCP4017/18/19

6.2.2

POTENTIOMETER

CONFIGURATION

6.2

Resistor Configurations

6.2.1

RHEOSTAT CONFIGURATION

When used as a potentiometer, all three terminals of

the device are tied to different nodes in the circuit. This

allows the potentiometer to output

proportional to the input voltage. This configuration is

sometimes called voltage divider mode. The

potentiometer is used to provide a variable voltage by

adjusting the wiper position between the two endpoints

as shown in Figure 6-3. Reversing the polarity of the A

and B terminals will not affect operation.

When used as a rheostat, two of the three digital

potentiometer’s terminals are used as a resistive

element in the circuit. With terminal W (wiper) and

either terminal A or terminal B, a variable resistor is

created. The resistance will depend on the tap setting

of the wiper (and the wiper’s resistance). The

resistance is controlled by changing the wiper setting

a

voltage

The unused terminal (B or A) should be left floating.

Figure 6-2 shows the two possible resistors that can be

used. Reversing the polarity of the A and B terminals

will not affect operation.

V₁

A

V₃

W

A

B

R_AW

or

R_BW

W

V₂

B

FIGURE 6-3:

Potentiometer

Configuration.

Resistor

Rheostat Configuration.

The temperature coefficient of the R_ABresistors is

minimal by design. In this configuration, the resistors all

change uniformly, so minimal variation should be seen.

FIGURE 6-2:

This allows the control of the total resistance between

the two nodes. The total resistance depends on the

“starting” terminal to the Wiper terminal. So at the code

00h, the R_BWresistance is minimal (R_W), but the R_AW

resistance in maximized (R_AB+ R_W). Conversely, at the

code 3Fh, the R_AWresistance is minimal (R_W), but the

R_BWresistance in maximized (R_AB+ R_W).

The Wiper resistor temperature coefficient is different

to the R_ABtemperature coefficient. The voltage at node

V3 (Figure 6-3) is not dependent on this Wiper

resistance, just the ratio of the R_ABresistors, so this

temperature coefficient in most cases can be ignored.

Note:

To avoid damage to the internal wiper

circuitry in this configuration, care should

be taken to insure the current flow never

exceeds 2.5 mA.

The resistance Step size (R_S) equates to one LSb of

the resistor.

Note:

To avoid damage to the internal wiper

circuitry in this configuration, care should

be taken to insure the current flow never

exceeds 2.5 mA.

The pinout for the rheostat devices is such that as the

wiper register is incremented, the resistance of the

resistor will increase (as measured from Terminal B to

the W Terminal).

DS22147A-page 43

MCP4017/18/19

In a potentiometer configuration, the wiper resistance

variation does not effect the output voltage seen on the

W pin.

6.3

Wiper Resistance

Wiper resistance is the series resistance of the analog

switch that connects the selected resistor ladder node

to the Wiper Terminal common signal (see Figure 6-1).

The slope of the resistance has a linear area (at the

higher voltages) and a non-linear area (at the lower

voltages). In where resistance increases faster then the

voltage drop (at low voltages).

A value in the volatile wiper register selects which

analog switch to close, connecting the W terminal to

the selected node of the resistor ladder.

The resistance is dependent on the voltages on the

analog switch source, gate, and drain nodes, as well as

the device’s wiper code, temperature, and the current

through the switch. As the device voltage decreases,

the wiper resistance increases (see Figure 6-4 and

Table 6-4).

R_W

The wiper can connect directly to Terminal B or to

Terminal A. A zero scale connections, connects the

Terminal W (wiper) to Terminal B (wiper setting of

000h). A full scale connections, connects the Terminal

W (wiper) to Terminal A (wiper setting of 7Fh). In these

configurations the only resistance between the

Terminal W and the other Terminal (A or B) is that of the

analog switches.

V_DD

Note: The slope of the resistance has a linear

area (at the higher voltages) and a

non-linear area (at the lower voltages).

The wiper resistance is typically measured when the

wiper is positioned at either zero scale (00h) or full

scale (3Fh).

FIGURE 6-4:

Resistance (R ) to Voltage.

Relationship of Wiper

W

Since there is minimal variation of the total device

resistance over voltage, at a constant temperature (see

Figure 2-11, Figure 2-29, Figure 2-47, or Figure 2-65),

the change in wiper resistance over voltage can have a

significant impact on the INL and DNL error.

The wiper resistance in potentiometer-generated

voltage divider applications is not a significant source

of error.

The wiper resistance in rheostat applications can

create significant nonlinearity as the wiper is moved

toward zero scale (00h). The lower the nominal

resistance, the greater the possible error.

In a rheostat configuration, this change in voltage

needs to be taken into account. Particularly for the

lower resistance devices. For the 5.0 kΩ device the

maximum wiper resistance at 5.5V is approximately

3.2% of the total resistance, while at 2.7V it is

approximately 6.5% of the total resistance.

TABLE 6-4:

Typical

TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE

Resistance (Ω)

Wiper (R_W)

Step Max @ Max @

R_W/ R_S(%) ⁽¹⁾

R_W/ R_AB(%) ⁽²⁾

R_W

Typical

=

R_W= Max R_W= Max

@ 5.5V

R_W

=

R_W= Max R_W= Max

Total

@ 2.7V

Typical

@ 5.5V

@ 2.7V

Typical

(R_AB

)

(R_S)

5.5V

2.7V

5000

39.37

78.74

100

170

325

254.00% 431.80%

825.5%

2.00%

1.00%

0.20%

0.10%

3.40%

1.70%

0.34%

0.17%

6.50%

3.25%

0.65%

0.325%

10000

50000

127.00% 215.90% 412.75%

393.70

25.40%

12.70%

43.18%

21.59%

82.55%

41.28%

100000 787.40

Note 1: R_Sis the typical value. The variation of this resistance is minimal over voltage.

2: R_ABis the typical value. The variation of this resistance is minimal over voltage.

DS22147A-page 44

MCP4017/18/19

6.4.1.2

Differential Non-linearity (DNL)

6.4

Operational Characteristics

DNL error is the measure of variations in code widths

from the ideal code width. A DNL error of zero would

imply that every code is exactly 1 LSb wide.

Understanding the operational characteristics of the

device’s resistor components is important to the system

design.

6.4.1

ACCURACY

111

6.4.1.1

Integral Non-linearity (INL)

INL error for these devices is the maximum deviation

between an actual code transition point and its

corresponding ideal transition point after offset and

gain errors have been removed. These endpoints are

from 0x00 to 0x7F. Refer to Figure 6-5.

110

Actual

transfer

101

function

Digital

Input

Code

100

011

010

001

000

Ideal transfer

function

Positive INL means higher resistance than ideal.

Negative INL means lower resistance than ideal.

Wide code, > 1 LSb

INL < 0

111

Narrow code < 1 LSb

Actual

transfer

function

110

101

100

Digital Pot Output

FIGURE 6-6:

DNL Accuracy.

Digital

Input

6.4.1.3 Ratiometric temperature coefficient

Code

011

010

001

000

The ratiometric temperature coefficient quantifies the

error in the ratio R_AW/R_WBdue to temperature drift.

This is typically the critical error when using a

potentiometer device (MCP4018) in a voltage divider

configuration.

Ideal transfer

function

6.4.1.4

Absolute temperature coefficient

INL < 0

The absolute temperature coefficient quantifies the

error in the end-to-end resistance (Nominal resistance

R_AB) due to temperature drift. This is typically the

critical error when using a rheostat device (MCP4017

and MCP4019) in an adjustable resistor configuration.

Digital Pot Output

FIGURE 6-5:

INL Accuracy.

DS22147A-page 45

MCP4017/18/19

6.4.2

MONOTONIC OPERATION

Monotonic operation means that the device’s

resistance increases with every step change (from

terminal A to terminal B or terminal B to terminal A).

The wiper resistances difference at each tap location.

When changing from one tap position to the next (either

increasing or decreasing), the ΔR_Wis less then the

ΔR_S. When this change occurs, the device voltage and

temperature are “the same” for the two tap positions.

R_S63

0x3F

0x3E

R_S62

0x3D

R_S3

0x03

R_S1

0x02

R_S0

0x01

0x00

R_W

n = ?

(@ tap)

R_BW

=

R_Sn+ R_{W(@ Tap n)}

n = 0

Resistance (R_BW

)

FIGURE 6-7:

R

.

BW

DS22147A-page 46

MCP4017/18/19

7.2

Layout Considerations

7.0

DESIGN CONSIDERATIONS

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

In the design of a system with the MCP4017/18/19

devices, the following considerations should be taken

into account. These are:

potentially

masking

the

MCP4017/18/19’s

performance. Careful board layout will minimize these

effects and increase the Signal-to-Noise Ratio (SNR).

Bench testing has shown that a multi-layer board

utilizing a low-inductance ground plane, isolated inputs,

isolated outputs and proper decoupling are critical to

achieving the performance that the silicon is capable of

providing. Particularly harsh environments may require

shielding of critical signals.

• The Power Supply

• The Layout

In the design of a system with the MCP4017/18/19

devices, the following considerations should be taken

into account:

• Power Supply Considerations

• Layout Considerations

If low noise is desired, breadboards and wire-wrapped

boards are not recommended.

7.1

Power Supply Considerations

7.2.1

RESISTOR TEMPCO

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 7-1 illustrates an

appropriate bypass strategy.

Characterization curves of the resistor temperature

coefficient (Tempco) are shown in Figure 2-11,

Figure 2-29, Figure 2-47, and Figure 2-65.

These curves show that the resistor network is

designed to correct for the change in resistance as

temperature increases. This technique reduces the

end to end change is R_ABresistance.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close to the device power pin (V_DD) as possible (within

4 mm).

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, V_DDand

V_SSshould reside on the analog plane.

V_DD

0.1 µF

V_DD

0.1 µF

A

W

SCL

SDA

B

V_SS

FIGURE 7-1:

Typical Microcontroller

Connections.

DS22147A-page 47

MCP4017/18/19

NOTES:

DS22147A-page 48

MCP4017/18/19

8.0

APPLICATIONS EXAMPLES

V_DD

R₁

Digital potentiometers have a multitude of practical

uses in modern electronic circuits. The most popular

uses include precision calibration of set point

thresholds, sensor trimming, LCD bias trimming, audio

attenuation, adjustable power supplies, motor control

overcurrent trip setting, adjustable gain amplifiers and

offset trimming. The MCP4017/18/19 devices can be

used to replace the common mechanical trim pot in

applications where the operating and terminal voltages

are within CMOS process limitations (V_DD= 2.7V to

5.5V).

MCP4018

A

SDA

SCL

W

V_OUT

B

FIGURE 8-1:

Using the Digital

Potentiometer to Set a Precise Output Voltage.

8.1

Set Point Threshold Trimming

8.1.1

TRIMMING A THRESHOLD FOR AN

OPTICAL SENSOR

Applications that need accurate detection of an input

threshold event often need several sources of error

eliminated. Use of comparators and operational

amplifiers (op amps) with low offset and gain error can

help achieve the desired accuracy, but in many

applications, the input source variation is beyond the

designer’s control. If the entire system can be

calibrated after assembly in a controlled environment

(like factory test), these sources of error are minimized

if not entirely eliminated.

If the application has to calibrate the threshold of a

diode, transistor or resistor, a variation range of 0.1V is

common. Often, the desired a resolution of 2 mV or

better is adequate to accurately detect the presence of

a precise signal. A “windowed” voltage divider, utilizing

the MCP4018, would be a potential solution. Figure 8-

2 illustrates this example application.

Figure 8-1 illustrates a common digital potentiometer

configuration. This configuration is often referred to as

a “windowed voltage divider”. Note that R₁is not

necessary to create the voltage divider, but its

presence is useful when the desired threshold has

limited range. It is “windowed” because R₁can narrow

the adjustable range of V_TRIPto a value much less than

V_DD– V_SS. If the output range is reduced, the

magnitude of each output step is reduced. This

effectively increases the trimming resolution for a fixed

digital potentiometer resolution. This technique may

allow a lower-cost digital potentiometer to be utilized

(64 steps instead of 256 steps).

V_DD

V_CC+

R_sense

R₁

MCP4018

Comparator

A

B

V_TRIP

SDA

SCL

W

MCP6021

V_CC–

The MCP4018’s low DNL performance is critical to

meeting calibration accuracy in production without

having to use a higher precision digital potentiometer.

0.1 µF

EQUATION 8-1:

CALCULATING THE

WIPER SETTING FROM

FIGURE 8-2:

Calibration.

Set Point or Threshold

THE DESIRED V

TRIP

R_WB

⎛

⎝

⎞

⎠

------------------

V_TRIP= V_DD

R₁+ R₂

R

_AB= R_Nominal

D

127

R_WB= R_AB

•

V_TRIP

V_DD

D =

• (R₁+ R_AB

)

• 127

D = Digital Potentiometer Wiper Setting (0-127)

DS22147A-page 49

MCP4017/18/19

8.2

Operational Amplifier

Applications

Figure 8-3 and Figure 8-4 illustrate typical amplifier

circuits that could replace fixed resistors with the

MCP4017/18/19 to achieve digitally-adjustable analog

solutions.

MCP6291

V_IN

+

Op Amp

–

V_DD

V_OUT

R₁

R₃

A

B

W

MCP4017

MCP4018

FIGURE 8-3:

Trimming Offset and Gain in

a Non-Inverting Amplifier.

MCP4018

R₄

A

B

W

V_DD

–

Op Amp

+

R₁

V_OUT

V_IN

MCP6021

A

B

W

1

f_c= -----------------------------

2π ⋅ R ⋅ C

Eq

MCP4018

Thevenin

Equivalent

||

R_Eq= (R₁+ R_AB– R_WB

)

(R₂+ R_WB) + R_w

FIGURE 8-4:

Programmable Filter.

DS22147A-page 50

MCP4017/18/19

The circuit illustrated by Figure 8-6 utilizes a digital

potentiometer for trimming the offset error. This

solution removes R_Wfrom the trimming equation along

with the error associated with R_W. R₂is not required,

but can be utilized to reduce the trimming “window” and

reduce variation due to the digital pot’s R_ABpart-to-part

variability.

8.3

Temperature Sensor Applications

Thermistors are resistors with very predictable

variation with temperature. Thermistors are a popular

sensor choice when a low-cost temperature-sensing

solution is desired. Unfortunately, thermistors have

non-linear characteristics that are undesirable, typically

requiring trimming in an application to achieve greater

accuracy. There are several common solutions to trim

& linearize thermistors. Figure 8-5 and Figure 8-6 are

simple methods for linearizing a 3-terminal NTC

thermistor. Both are simple voltage dividers using a

Positive Temperature Coefficient (PTC) resistor (R₁)

with a transfer function capable of compensating for the

linearity error in the Negative Temperature Coefficient

(NTC) thermistor.

V_DD

R₁

NTC

Thermistor

The circuit, illustrated by Figure 8-5, utilizes a digital

rheostat for trimming the offset error caused by the

thermistor’s part-to-part variation. This solution puts the

digital potentiometer’s R_Winto the voltage divider

calculation. The MCP4017/18/19’s R_ABtemperature

coefficient is a low 50 ppm (-20°C to +70°C). R_W’s error

is substantially greater than R_AB’s error because R_W

varies with V_DD, wiper setting and temperature. For the

50 kΩ devices, the error introduced by R_Wis, in most

cases, insignificant as long as the wiper setting is > 6.

For the 2 kΩ devices, the error introduced by R_Wis

V_OUT

MCP4018

FIGURE 8-6:

Thermistor Calibration using

a Digital Potentiometer in a Potentiometer

Configuration.

significant because it is a higher percentage of R_WB

.

For these reasons, the circuit illustrated in Figure 8-5 is

not the most optimum method for “exciting” and

linearizing a thermistor.

V_DD

R₁

NTC

Thermistor

V_OUT

R₂

MCP4017

FIGURE 8-5:

Thermistor Calibration using

a Digital Potentiometer in a Rheostat

Configuration.

DS22147A-page 51

MCP4017/18/19

8.4

Wheatstone Bridge Trimming

Another common configuration to “excite” a sensor

(such as a strain gauge, pressure sensor or thermistor)

is the wheatstone bridge configuration. The

wheatstone bridge provides

a differential output

instead of a single-ended output. Figure 8-7 illustrates

a wheatstone bridge utilizing one to three digital

potentiometers. The digital potentiometers in this

example are used to trim the offset and gain of the

wheatstone bridge.

V_DD

5 kΩ

MCP4017

V_OUT

MCP4017

50 kΩ

FIGURE 8-7:

Wheatstone Bridge

Trimming.

DS22147A-page 52

MCP4017/18/19

9.2

Technical Documentation

9.0

9.1

DEVELOPMENT SUPPORT

Development Tools

Several additional technical documents are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs, and Design Guides. Table 9-1 shows

some of these documents.

To assist in your design and evaluation of the

MCP4017/18/19 devices, a Demo board using the

MCP4017 device is in development. Please check the

Microchip web site for the release of this board. The

board part number is tentatively MCP4XXXDM-PGA,

and is expected to be available in the summer of 2009.

TABLE 9-1:

TECHNICAL DOCUMENTATION

Title

Application

Literature #

Note Number

AN1080

AN737

AN692

AN691

AN219

—

Understanding Digital Potentiometers Resistor Variations

Using Digital Potentiometers to Design Low Pass Adjustable Filters

Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect

Optimizing the Digital Potentiometer in Precision Circuits

Comparing Digital Potentiometers to Mechanical Potentiometers

Digital Potentiometer Design Guide

DS01080

DS00737

DS00692

DS00691

DS00219

DS22017

DS21825

—

Signal Chain Design Guide

DS22147A-page 53

MCP4017/18/19

NOTES:

DS22147A-page 54

MCP4017/18/19

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

Example:

5-Lead SC70

Part Number

Code

MCP4019T-502E/LT

MCP4019T-103E/LT

BENN

BFNN

XXNN

BENN

MCP4019T-503E/LT BGNN

MCP4019T-104E/LT

BHNN

6-Lead SC70

Example:

Part Number

Code

Part Number

Code

MCP4017T-502E/LT

MCP4017T-103E/LT

AENN

AFNN

MCP4018T-502E/LT

MCP4018T-103E/LT

AANN

ABNN

ACNN

ADNN

XXNN

AANN

MCP4017T-503E/LT AGNN MCP4018T-503E/LT

MCP4017T-104E/LT AHNN MCP4018T-104E/LT

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22147A-page 55

MCP4017/18/19

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢂꢒꢖꢆꢗꢍꢘꢙꢚꢛ

ꢜꢔꢊꢃꢝ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ

ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ

D

b

1

3

2

E1

E

4

5

e

A

A2

c

A1

L

3ꢆꢃ#

ꢏꢙ44ꢙꢏ"ꢗ"ꢚꢕ

ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#

ꢏꢙ5

56ꢏ

ꢏꢔ7

5$ꢄ8ꢅꢍꢈꢇ%ꢈ1ꢃꢆ

1ꢃ#ꢊꢌ

5

ꢅ

(

ꢐꢁ9(ꢈ)ꢕ*

6,ꢅꢍꢉꢋꢋꢈ:ꢅꢃꢓꢌ#

ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈꢗꢌꢃꢊ/ꢆꢅ

ꢕ#ꢉꢆ!ꢇ%%

ꢔ

ꢐꢁ;ꢐ

ꢐꢁꢐꢐ

ꢀꢁ;ꢐ

ꢀꢁꢀ(

ꢀꢁ;ꢐ

ꢐꢁꢀꢐ

ꢐꢁꢐ;

ꢐꢁꢀ(

M

ꢑꢁꢀꢐ

ꢀꢁꢑ(

ꢑꢁꢐꢐ

ꢐꢁꢑꢐ

M

ꢀꢁꢀꢐ

ꢀꢁꢐꢐ

ꢐꢁꢀꢐ

ꢑꢁꢖꢐ

ꢀꢁꢛ(

ꢑꢁꢑ(

ꢐꢁꢖ9

ꢐꢁꢑ9

ꢐꢁꢖꢐ

ꢔꢑ

ꢔꢀ

"

"ꢀ

ꢂ

4

ꢊ

8

6,ꢅꢍꢉꢋꢋꢈ=ꢃ!#ꢌ

ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ=ꢃ!#ꢌ

6,ꢅꢍꢉꢋꢋꢈ4ꢅꢆꢓ#ꢌ

.ꢇꢇ#ꢈ4ꢅꢆꢓ#ꢌ

4ꢅꢉ!ꢈꢗꢌꢃꢊ/ꢆꢅ

4ꢅꢉ!ꢈ=ꢃ!#ꢌ

M

ꢜꢔꢊꢃꢉꢝ

ꢀꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀꢑꢒꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ

ꢑꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ

)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ

ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢜꢐ9ꢀ)

DS22147A-page 56

MCP4017/18/19

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22147A-page 57

MCP4017/18/19

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22147A-page 58

MCP4017/18/19

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22147A-page 59

MCP4017/18/19

NOTES:

DS22147A-page 60

MCP4017/18/19

APPENDIX A: REVISION HISTORY

Revision A (March 2009)

• Original Release of this Document.

DS22147A-page 61

MCP4017/18/19

NOTES:

DS22147A-page 62

MCP4017/18/19

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

XXX

X

/XX

a) MCP4017T-502E/LT: 5 kΩ,

Resistance Temperature Package

Version Range

6-LD SC-70.

b) MCP4017T-103E/LT: 10 kΩ, 6-LD

SC-70.

c) MCP4017T-503E/LT: 50 kΩ,

6-LD SC-70.

d) MCP4017T-104E/LT: 100 kΩ,

6-LD SC-70.

Device:

MCP4017: Single Rheostat with I²C

interface

MCP4017T: Single Rheostat with I²C

interface (Tape and Reel)

MCP4018: Single Potentiometer to GND

with I²C Interface

a) MCP4018T-502E/LT: 5 kΩ,

6-LD SC-70.

b) MCP4018T-103E/LT: 10 kΩ,

6-LD SC-70.

c) MCP4018T-503E/LT: 50 kΩ,

6-LD SC-70.

d) MCP4018T-104E/LT: 100 kΩ,

6-LD SC-70.

MCP4018T: Single Potentiometer to GND

with I²C Interface (Tape and

Reel)

MCP4019: Single Rheostat to GND with

I²C Interface

MCP4019T: Single Rheostat to GND with

I²C Interface (Tape and Reel)

Resistance

Version:

502 = 5 kΩ

a) MCP4019T-502E/LT: 5 kΩ,

5-LD SC-70.

b) MCP4019T-103E/LT: 10 kΩ,

5-LD SC-70.

103 = 10 kΩ

503 = 50 kΩ

104 = 100 kΩ

c) MCP4019T-503E/LT: 50 kΩ,

5-LD SC-70.

d) MCP4019T-104E/LT: 100 kΩ,

5-LD SC-70.

Temperature

Range:

E

= -40°C to +125°C

Package:

LT = Plastic Small Outline Transistor

(SC70), 5-lead, 6-lead

DS22147A-page 63

MCP4017/18/19

NOTES:

DS22147A-page 64

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,

PICkit, PICDEM, PICDEM.net, PICtail, PIC³²logo, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Total Endurance, TSHARC, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22147A-page 65

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

03/26/09

DS22147A-page 66


型号：	MCP4017T-103E/LT
厂家：	MICROCHIP
描述：	7-Bit Single I2C? Digital POT with Volatile Memory in SC70 7位单I2C ？数字电位器在SC70易失性存储器电位器存储
文件：	总66页 (文件大小：2760K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP4017T-103E/LT [MICROCHIP]

相关型号：

MCP4017T-103E/LTVAO

MCP4017T-104E/LT

MCP4017T-502E/LT

MCP4017T-503E/LT

MCP4018

MCP4018-103E/LT

MCP4018-104E/LT

MCP4018-502E/LT

MCP4018-503E/LT

MCP4018T

MCP4018T-103E/LT

MCP4018T-103E/LTVAO