MCP4021T-503E/MCVAO [MICROCHIP]
Digital Potentiometer, 1 Func, 50000ohm, Increment/decrement Control Interface, 64 Positions, PDSO8;
| 型号： | MCP4021T-503E/MCVAO |
| 厂家： | 
MICROCHIP |
| 描述： | Digital Potentiometer, 1 Func, 50000ohm, Increment/decrement Control Interface, 64 Positions, PDSO8 光电二极管 |
| 文件： | 总74页 (文件大小：4411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP4021/2/3/4
Low-Cost NV Digital POT with WiperLock™ Technology
Package Types
Features
MCP4021
MCP4022
• Nonvolatile Digital Potentiometer in SOT-23,
SOIC, MSOP and DFN Packages
SOIC, MSOP, DFN
Potentiometer
SOT-23-6
Rheostat
• 64 Taps: 63 Resistors with Taps to Terminal A and
Terminal B
V
V
A
8
7
6
5
U/D
1
2
3
4
1
2
3
6
5
4
DD
DD
A
W
• Simple Up/Down (U/D) Protocol
V
V
W
CS
NC
B
SS
A
SS
• Power-on Recall of Saved Wiper Setting
• Resistance Values: 2.1 k, 5 k, 10 k or 50 k
• Low Tempco:
A
B
U/D
B
W
W
CS
- Absolute (Rheostat): 50 ppm (0°C to 70°C Typ.)
- Ratiometric (Potentiometer): 10 ppm (Typ.)
• Low Wiper Resistance: 75 (Typ.)
MCP4023
MCP4024
SOT-23-6
Potentiometer
SOT-23-5
Rheostat
A
V
W
5
V
• WiperLock™ Technology to Secure the wiper
setting in nonvolatile memory (EEPROM)
A
1
2
3
6
5
4
1
2
3
DD
DD
W
V
W
CS
V
SS
SS
W
B
B
A
• High-Voltage Tolerant Digital Inputs: up to 12.5V
• Low-Power Operation: 1 µA Max Static Current
• Wide Operating Voltage: 2.7V to 5.5V
• Extended Temperature Range: –40°C to +125°C
• Wide Bandwidth (-3 dB) Operation:
U/D
U/D
CS
4
Block Diagram
A
- 4 MHz (Typ.) for 2.1 k Device
VDD
Power-Up
and
Brown-Out
Control
Description
VSS
The MCP4021/2/3/4 devices are nonvolatile, 6-bit
digital potentiometers that can be configured as either a
potentiometer or rheostat. The wiper setting is
controlled through a simple Up/Down (U/D) serial
interface.
2-Wire
Interface
and
Control
Logic
W
CS
U/D
These device’s implement Microchip’s WiperLock
technology,
which
allows
application-specific
calibration settings to be secured in the EEPROM
without requiring the use of an additional write-protect
pin.
EEPROM and
WiperLock
Technology
B
Device Features
Resistance (typical)
VDD
Operating
Range
Wiper
Configuration
Memory
Type
# of
Steps
Control WiperLock
Interface Technology
Device
Options (k)
Wiper ()
MCP4021 Potentiometer (1)
EE
EE
EE
EE
2.1, 5.0, 10.0, 50.0
2.1, 5.0, 10.0, 50.0
2.1, 5.0, 10.0, 50.0
2.1, 5.0, 10.0, 50.0
75
75
75
75
64 2.7V - 5.5V
64 2.7V- 5.5V
U/D
U/D
U/D
U/D
Yes
Yes
Yes
Yes
MCP4022
MCP4023
MCP4024
Rheostat
Potentiometer
Rheostat
64 2.7V - 5.5V
64 2.7V - 5.5V
Note 1: Floating either terminal (A or B) allows the device to be used in Rheostat mode.
.
2006-2017 Microchip Technology Inc.
DS20001945F-page 1
MCP4021/2/3/4
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD............................................................................................................. 6.5V
CS and U/D inputs w.r.t VSS................................... –0.3V to 12.5V
A, B and W terminals w.r.t VSS................... –0.3V to VDD + 0.3V
Current at Input Pins ..................................................±10 mA
Current at Supply Pins ...............................................±10 mA
Current at Potentiometer Pins ...................................±2.5 mA
Storage temperature ....................................–65°C to +150°C
Ambient temp. with power applied ...............–55°C to +125°C
ESD protection on all pins 4 kV (HBM), 400V (MM)
Maximum Junction Temperature (TJ)..........................+150°C
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = –40°C to +125°C, 2.1 k5 k10 kand50 kdevicesTypical specifications represent values for VDD = 5.5V, VSS = 0V,
TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Operating Voltage Range
CS Input Voltage
VDD
VCS
2.7
—
—
5.5
V
V
VSS
12.5
The CS pin will be at one of
three input levels (VIL, VIH or
V
IHH). (Note 6)
Supply Current
IDD
—
—
—
45
15
—
—
1
µA
µA
µA
5.5V, CS = VSS, fU/D = 1 MHz
2.7V, CS = VSS, fU/D = 1 MHz
Serial Interface Inactive
0.3
(CS = VIH, U/D = VIH
)
—
0.6
2.1
5
3
mA
k
k
k
k
Taps
EE Write cycle, TA = +25°C
-202 devices(Note 1)
-502 devices(Note 1)
-103 devices(Note 1)
-503 devices(Note 1)
No Missing Codes
Note 6
Resistance
(± 20%)
RAB
1.68
4.0
2.52
6.0
8.0
10
50
12.0
60.0
40.0
Resolution
N
64
RAB / 63
Step Resistance
RS
—
—
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS. (–202 devices VA = 4V).
3: MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h.
4: MCP4022/24 only, test conditions are:
Current at Voltage
Comments
Device
Resistance
5.5V
2.7V
2.1 k
5 k
2.25 mA
1.4 mA
450 µA
90 µA
1.1 mA
450 µA
210 µA
40 µA
MCP4022 includes VWZSE
MCP4024 includes VWFSE
10 k
50 k
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0, "Resistor" for additional information.
8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
9: This parameter is not tested, but specified by characterization.
DS20001945F-page 2
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = –40°C to +125°C, 2.1 k5 k10 kand50 kdevicesTypical specifications represent values for VDD = 5.5V, VSS = 0V,
TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Wiper Resistance (Note 3, Note 4)
RW
—
—
—
—
—
—
70
70
125
325
—
5.5V
2.7V
Nominal Resistance Tempco
Ratiometeric Tempco
R/T
50
ppm/°C TA = –20°C to +70°C
ppm/°C TA = –40°C to +85°C
ppm/°C TA = –40°C to +125°C
100
150
10
—
—
VWA/T
—
ppm/°C MCP4021 and MCP4023 only,
code = 1Fh
Full-Scale Error
VWFSE
VWZSE
N
-0.5
-0.5
-0.1
+0.5
+0.5
LSb
LSb
Bits
LSb
LSb
Code 3Fh (MCP4021/23 only)
Code 00h (MCP4021/23 only)
Zero-Scale Error
+0.1
Monotonicity
Yes
Potentiometer Integral Non-linearity
INL
-0.5
-0.5
±0.25
±0.25
+0.5
+0.5
MCP4021/23 only (Note 2)
MCP4021/23 only (Note 2)
Potentiometer Differential
Nonlinearity
DNL
Resistor Terminal Input Voltage Range
(Terminals A, B and W)
VA,VW,VB
Vss
—
VDD
V
Note 5, Note 6
Maximum current through A, W or B
Leakage current into A, W or B
IW
—
—
—
—
—
—
—
—
—
100
100
100
75
2.5
—
—
—
—
—
—
—
mA
nA
Note 6
IWL
MCP4021 A = W = B = VSS
MCP4022/23 A = W = VSS
MCP4024 W = VSS
f =1 MHz, code = 1Fh
f =1 MHz, code = 1Fh
f =1 MHz, code = 1Fh
nA
nA
Capacitance (PA)
Capacitance (Pw)
Capacitance (PB)
Bandwidth -3 dB
CAW
CW
pF
120
75
pF
CBW
BW
pF
4
MHz
-202
Code = 1F,
devices
output load = 30 pF
—
—
—
2
1
—
—
—
MHz
MHz
kHz
-502
devices
-103
devices
200
-503
devices
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS. (–202 devices VA = 4V).
3: MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h.
4: MCP4022/24 only, test conditions are:
Current at Voltage
Comments
Device
Resistance
5.5V
2.7V
2.1 k
5 k
2.25 mA
1.4 mA
450 µA
90 µA
1.1 mA
450 µA
210 µA
40 µA
MCP4022 includes VWZSE
MCP4024 includes VWFSE
10 k
50 k
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0, "Resistor" for additional information.
8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
9: This parameter is not tested, but specified by characterization.
2006-2017 Microchip Technology Inc.
DS20001945F-page 3
MCP4021/2/3/4
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = –40°C to +125°C, 2.1 k5 k10 kand50 kdevicesTypical specifications represent values for VDD = 5.5V, VSS = 0V,
TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Rheostat Integral Non-linearity
MCP4021 (Note 4, Note 8)
MCP4022 and MCP4024 (Note 4)
R-INL
-0.5
-8.5
±0.25
+4.5
+0.5
+8.5
LSb
LSb
-202
devices
(2.1 k
5.5V
2.7V (Note 7)
-0.5
-5.5
±0.25
+2.5
+0.5
+5.5
LSb
LSb
-502
devices
(5 k
5.5V
2.7V (Note 7)
-0.5
-3
±0.25
+1
+0.5
+3
LSb
LSb
-103
devices
(10 k
5.5V
2.7V (Note 7)
-0.5
-1
±0.25
+0.25
+0.5
+1
LSb
LSb
-503
devices
(50 k
5.5V
2.7V (Note 7)
Rheostat Differential Non-linearity
MCP4021 (Note 4, Note 8)
MCP4022 and MCP4024 (Note 4)
R-DNL
-0.5
-1
±0.25
+0.5
+0.5
+2
LSb
LSb
-202
devices
(2.1 k
5.5V
2.7V (Note 7)
-0.5
-1
±0.25
+0.25
+0.5
LSb
LSb
-502
devices
(5 k
5.5V
+1.25
2.7V (Note 7)
-0.5
-1
±0.25
0
+0.5
+1
LSb
LSb
-103
devices
(10 k
5.5V
2.7V (Note 7)
-0.5
-0.5
±0.25
0
+0.5
+0.5
LSb
LSb
-503
devices
(50 k
5.5V
2.7V (Note 7)
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS. (–202 devices VA = 4V).
3: MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h.
4: MCP4022/24 only, test conditions are:
Current at Voltage
Comments
Device
Resistance
5.5V
2.7V
2.1 k
5 k
2.25 mA
1.4 mA
450 µA
90 µA
1.1 mA
450 µA
210 µA
40 µA
MCP4022 includes VWZSE
MCP4024 includes VWFSE
10 k
50 k
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0, "Resistor" for additional information.
8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
9: This parameter is not tested, but specified by characterization.
DS20001945F-page 4
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = –40°C to +125°C, 2.1 k5 k10 kand50 kdevicesTypical specifications represent values for VDD = 5.5V, VSS = 0V,
TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Digital Inputs/Outputs (CS, U/D)
Input High Voltage
VIH
VIL
0.7 VDD
—
—
—
—
0.3 VDD
12.5(6)
12.5(6)
VDD+0.8(6)
—
V
V
Input Low Voltage
High-Voltage Input Entry Voltage
(Threshold for WiperLock Technology)
VIHH
8.5(9)
9.0
—
—
V
+7°C to +125°C
—
V
–40°C to +125°C
High-Voltage Input Exit Voltage
CS Pull-up/Pull-down Resistance
CS Weak Pull-up/Pull-down Current
Input Leakage Current
CS and U/D Pin Capacitance
RAM (Wiper) Value
VIHH
RCS
—
V
—
16
170
—
k
µA
µA
pF
VDD = 5.5V, VCS = 3V
VDD = 5.5V, VCS = 3V
VIN = VDD
IPU
—
—
IIL
–1
1
CIN, COUT
—
10
—
fC = 1 MHz
Value Range
N
0h
—
3Fh
hex
EEPROM
Endurance
Endurance
—
1M
—
—
Cycles
hex
EEPROM Range
N
N
0h
3Fh
Initial Factory Setting
Power Requirements
1Fh
hex
WiperLock Technology = Off
Power Supply Sensitivity
(MCP4021 and MCP4023 only)
PSS
—
—
0.0015
0.0015
0.0035
0.0035
%/%
%/%
VDD = 4.5V to 5.5V, VA = 4.5V,
Code = 1Fh
VDD = 2.7V to 4.5V, VA = 2.7V,
Code = 1Fh
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS. (–202 devices VA = 4V).
3: MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h.
4: MCP4022/24 only, test conditions are:
Current at Voltage
Comments
Device
Resistance
5.5V
2.7V
2.1 k
5 k
2.25 mA
1.4 mA
450 µA
90 µA
1.1 mA
450 µA
210 µA
40 µA
MCP4022 includes VWZSE
MCP4024 includes VWFSE
10 k
50 k
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0, "Resistor" for additional information.
8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
9: This parameter is not tested, but specified by characterization.
2006-2017 Microchip Technology Inc.
DS20001945F-page 5
MCP4021/2/3/4
tCSHI
tCSLO
CS
1/fUD
tLUC
tLCUF
tLUC
tLO
tLCUF
U/D
tHI
tLCUR
tS
tS
W
FIGURE 1-1:
Increment Timing Waveform.
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C.
Parameters
CS Low Time
Sym
Min
Typ
Max
Units
Conditions
tCSLO
tCSHI
tLUC
tLCUF
tLCUR
tHI
5
500
500
500
3
—
—
—
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
1
µs
ns
CS High Time
U/D to CS Hold Time
CS to U/D Low Setup Time
CS to U/D High Setup Time
U/D High Time
ns
ns
µs
500
500
—
ns
U/D Low Time
tLO
ns
Up/Down Toggle Frequency
Wiper Settling Time
fUD
MHz
µs
tS
0.5
1
—
—
—
—
—
5
2.1 k CL = 100 pF
µs
5 k CL = 100 pF
10 k CL = 100 pF
50 k CL = 100 pF
2
µs
10
—
µs
Wiper Response on Power-Up
Internal EEPROM Write Time
tPU
twc
200
—
—
ns
—
ms
ms
@25°C
—
10
-40°C to +125°C
DS20001945F-page 6
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
tCSHI
tCSLO
CS
1/fUD
tLUC
tLCUF
tLUC
tHI
U/D
tLO
tLCUR
tS
tS
W
FIGURE 1-2:
Decrement Timing Waveform.
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +2.7V to 5.5V, TA = –40°C to +125°C.
Parameters
CS Low Time
Sym
Min
Typ
Max
Units
Conditions
tCSLO
tCSHI
tLUC
tLCUF
tLCUR
tHI
5
500
500
500
3
—
—
—
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
1
µs
ns
CS High Time
U/D to CS Hold Time
CS to U/D Low Setup Time
CS to U/D High Setup Time
U/D High Time
ns
ns
µs
500
500
—
ns
U/D Low Time
tLO
ns
Up/Down Toggle Frequency
Wiper Settling Time
fUD
MHz
µs
tS
0.5
1
—
—
—
—
—
5
2.1 k CL = 100 pF
µs
5 k CL = 100 pF
10 k CL = 100 pF
50 k CL = 100 pF
2
µs
10
—
µs
Wiper Response on Power-Up
Internal EEPROM Write Time
tPU
twc
200
—
—
ns
—
ms
ms
@25°C
—
10
-40°C to +125°C
2006-2017 Microchip Technology Inc.
DS20001945F-page 7
MCP4021/2/3/4
tCSHI
tCSLO
12V
CS
5V
1/fUD
tHUC tHCUF
tHUC
tLO
tHCUF
U/D
tHCUR
W
tHI
tS
tS
FIGURE 1-3:
High-Voltage Increment Timing Waveform.
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C.
Parameters
CS Low Time
Sym
Min
Typ
Max
Units
Conditions
tCSLO
tCSHI
tHI
5
500
500
500
—
—
—
—
—
—
—
—
—
—
—
—
5
—
—
—
—
1
µs
ns
CS High Time
U/D High Time
ns
U/D Low Time
tLO
ns
Up/Down Toggle Frequency
HV U/D to CS Hold Time
HV CS to U/D Low Setup Time
HV CS to U/D High Setup Time
Wiper Settling Time
fUD
MHz
µs
tHUC
tHCUF
tHCUR
tS
1.5
8
—
—
—
—
—
—
—
—
5
µs
4.5
0.5
1
µs
µs
2.1 k CL = 100 pF
µs
5 k CL = 100 pF
10 k CL = 100 pF
50 k CL = 100 pF
2
µs
10
—
µs
Wiper Response on Power-Up
Internal EEPROM Write Time
tPU
twc
200
—
—
ns
—
ms
ms
@25°C
—
10
–40°C to +125°C
DS20001945F-page 8
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
tCSHI
tCSLO
12V
5V
CS
1/fUD
tHUC
tHCUF
tHUC
tHI
U/D
tLO
tHCUR
tS
tS
W
FIGURE 1-4:
High-Voltage Decrement Timing Waveform.
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C.
Parameters
CS Low Time
Sym
Min
Typ
Max
Units
Conditions
tCSLO
tCSHI
tHI
5
500
500
500
—
—
—
—
—
—
—
—
—
—
—
—
5
—
—
—
—
1
µs
ns
CS High Time
U/D High Time
ns
U/D Low Time
tLO
ns
Up/Down Toggle Frequency
HV U/D to CS Hold Time
HV CS to U/D Low Setup Time
HV CS to U/D High Setup Time
Wiper Settling Time
fUD
MHz
µs
tHUC
tHCUF
tHCUR
tS
1.5
8
—
—
—
—
—
—
—
—
5
µs
4.5
0.5
1
µs
µs
2.1 k CL = 100 pF
µs
5 k CL = 100 pF
10 k CL = 100 pF
50 k CL = 100 pF
2
µs
10
—
µs
Wiper Response on Power-Up
Internal EEPROM Write Time
tPU
twc
200
—
—
ns
—
ms
ms
@25°C
—
10
–40°C to +125°C
2006-2017 Microchip Technology Inc.
DS20001945F-page 9
MCP4021/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 6L-SOT-23
Thermal Resistance, 8L-DFN (2x3)
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-SOIC
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
JA
JA
JA
JA
JA
—
—
—
—
—
255
230
85
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
206
117
DS20001945F-page 10
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
80
250
200
150
100
50
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
2.7V -40°C
70
60
50
40
30
20
10
0
2.7V 25°C
2.7V 85°C
2.7V 125°C
5.5V -40°C
5.5V 25°C
5.5V 85°C
5.5V 125°C
ICS
RCS
0
0.20
0.40
0.60
U/D (MHz)
0.80
1.00
9
8
7
6
5
4
3
2
1
f
VCS (V)
FIGURE 2-1:
Device Current (I ) vs. U/D
FIGURE 2-4:
CS Pull-up/Pull-down
DD
Frequency (f ) and Ambient Temperature
Resistance (R ) and Current (I ) vs. CS Input
U/D
CS
CS
(V = 2.7V and 5.5V).
Voltage (V ) (V = 5.5V).
DD
CS DD
600.0
500.0
400.0
300.0
200.0
100.0
0.0
12
10
8
1.8V Entry
2.7V Entry
5.5V Entry
1.8V Exit
2.7V Exit
5.5V Exit
V
DD = 5.5V
6
4
VDD = 2.7V
2
0
-40
25
85
125
-40 -20
0
20
40
60
80 100 120
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-2:
Write Current (I
) vs.
FIGURE 2-5:
CS High Input Entry/Exit
WRITE
Ambient Temperature and V
.
Threshold vs. Ambient Temperature and V
.
DD
DD
0.8
0.7
VDD = 5.5V
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VDD = 2.7V
-40
25
85
125
Ambient Temperature (°C)
FIGURE 2-3:
Device Current (I
) vs.
SHDN
Ambient Temperature and V . (CS = V ).
DD
DD
2006-2017 Microchip Technology Inc.
DS20001945F-page 11
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
140
120
100
80
0.075
0.05
120
100
80
60
40
20
0
0.8
0.6
0.4
0.2
0
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
0.025
0
INL
DNL
60
-0.025
-0.05
-0.075
-0.1
40
DNL
RW
-0.2
-0.4
RW
20
0
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-6:
2.1 k Pot Mode – R (),
FIGURE 2-8:
2.1 k Rheo Mode – R
W
W
INL (LSb), DNL (LSb) vs. Wiper Setting and
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 5.5V).
Ambient Temperature (V = 5.5V).
DD
DD
500
10
8
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
400
0.1
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
400
300
200
100
0
300
200
100
0
0.05
0
INL
6
INL
4
DNL
RW
2
-0.05
-0.1
0
DNL
RW
-2
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-7:
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 2.7V).
2.1 k Pot Mode – R (),
FIGURE 2-9:
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 2.7V).
2.1 k Rheo Mode – R
W
W
DD
DD
DS20001945F-page 12
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2080
2060
2500
2000
1500
1000
500
-40°C
25°C
85°C
125°C
VDD = 5.5V
2040
2020
VDD = 2.7V
2000
0
-40
0
40
80
120
0
8
16
24
32
40
48
56
64
Ambient Temperature (°C)
Wiper Setting (decimal)
FIGURE 2-10:
2.1 k – Nominal
FIGURE 2-11:
2.1 k – R
() vs. Wiper
WB
Resistance () vs. Ambient Temperature and
Setting and Ambient Temperature.
V
.
DD
2006-2017 Microchip Technology Inc.
DS20001945F-page 13
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
WIPER
WIPER
U/D
U/D
FIGURE 2-12:
2.1 k – Low-Voltage
FIGURE 2-15:
2.1 k – Low-Voltage
Decrement Wiper Settling Time (V = 2.7V).
Increment Wiper Settling Time (V = 2.7V).
DD
DD
WIPER
U/D
WIPER
U/D
FIGURE 2-13:
2.1 k – Low-Voltage
FIGURE 2-16:
2.1 k – Low-Voltage
Decrement Wiper Settling Time (V = 5.5V).
Increment Wiper Settling Time (V = 5.5V).
DD
DD
WIPER
VDD
FIGURE 2-14:
2.1 k – Power-Up Wiper
Response Time.
DS20001945F-page 14
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
140
120
100
80
0.075
0.05
120
100
80
60
40
20
0
0.6
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0.4
0.2
0
0.025
0
INL
INL
DNL
DNL
60
-0.025
-0.05
-0.075
-0.1
-0.2
-0.4
-0.6
40
RW
RW
20
0
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-17:
5 k Pot Mode – R (),
FIGURE 2-19:
5 k Rheo Mode – R (),
W
W
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 5.5V).
Ambient Temperature (V = 5.5V).
DD
DD
450
0.1
600
5
4
3
2
1
0
-1
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
400
350
300
250
200
150
100
50
0.075
0.05
0.025
0
500
400
300
200
100
0
INL
INL
DNL
-0.025
-0.05
-0.075
-0.1
RW
RW
DNL
0
-0.125
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-18:
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 2.7V).
5 k Pot Mode – R (),
FIGURE 2-20:
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 2.7V).
5 k Rheo Mode – R (),
W
W
DD
DD
2006-2017 Microchip Technology Inc.
DS20001945F-page 15
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
4950
6000
5000
4000
3000
2000
1000
0
2.7V Vdd
5.5V Vdd
-40°C
25°C
85°C
125°C
4925
4900
4875
VDD = 5.5V
4850
4825
VDD = 2.7V
4800
-40 -20
0
20 40 60 80 100 120
0
8
16
24
32
40
48
56
64
Ambient Temperature (°C)
Wiper Setting (decimal)
FIGURE 2-21:
5 k – Nominal Resistance
FIGURE 2-22:
5 k – R
() vs. Wiper
WB
() vs. Ambient Temperature and V
.
Setting and Ambient Temperature.
DD
DS20001945F-page 16
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
WIPER
WIPER
U/D
U/D
FIGURE 2-23:
5 k – Low-Voltage
FIGURE 2-25:
5 k – Low-Voltage
Decrement Wiper Settling Time (V = 2.7V).
Increment Wiper Settling Time (V = 2.7V).
DD
DD
WIPER
U/D
WIPER
U/D
FIGURE 2-24:
5 k – Low-Voltage
FIGURE 2-26:
5 k – Low-Voltage
Decrement Wiper Settling Time (V = 5.5V).
Increment Wiper Settling Time (V = 5.5V).
DD
DD
2006-2017 Microchip Technology Inc.
DS20001945F-page 17
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
120
100
80
60
40
20
0
0.05
0.025
0
120
100
80
60
40
20
0
0.15
0.1
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
DNL
INL
0.05
0
DNL
INL
-0.025
-0.05
-0.075
-0.1
-0.05
-0.1
-0.15
RW
RW
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-27:
10 k Pot Mode – R (),
FIGURE 2-29:
10 k Rheo Mode – R (),
W
W
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 5.5V).
Ambient Temperature (V = 5.5V).
DD
DD
450
0.05
500
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
DNL
2.5
400
350
300
250
200
150
100
50
0.025
0
400
300
200
100
0
INL
1.5
INL
-0.025
-0.05
-0.075
-0.1
0.5
DNL
-0.5
-1.5
-2.5
RW
RW
0
-0.125
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-28:
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 2.7V).
10 k Pot Mode – R (),
FIGURE 2-30:
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 2.7V).
10 k Rheo Mode – R (),
W
W
DD
DD
DS20001945F-page 18
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
10250
10230
10210
10190
10170
10150
10130
10110
10090
10070
10050
12000
10000
8000
6000
4000
2000
0
-40°C
25°C
85°C
125°C
VDD = 5.5V
VDD = 2.7V
-40 -20
0
20 40 60 80 100 120
Ambient Temperature (°C)
0
8
16
24
32
40
48
56
64
Wiper Setting (decimal)
FIGURE 2-31:
10 k – Nominal Resistance
FIGURE 2-32:
10 k – R
() vs. Wiper
WB
() vs. Ambient Temperature and V
.
Setting and Ambient Temperature.
DD
2006-2017 Microchip Technology Inc.
DS20001945F-page 19
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
WIPER
WIPER
U/D
U/D
FIGURE 2-33:
10 k – Low-Voltage
FIGURE 2-35:
10 k – Low-Voltage
Decrement Wiper Settling Time (V = 2.7V).
Increment Wiper Settling Time (V = 2.7V).
DD
DD
WIPER
U/D
WIPER
U/D
FIGURE 2-34:
10 k – Low-Voltage
FIGURE 2-36:
10 k – Low-Voltage
Decrement Wiper Settling Time (V = 5.5V).
Increment Wiper Settling Time (V = 5.5V).
DD
DD
DS20001945F-page 20
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
200
160
120
80
0.1
200
150
100
50
0.15
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0.05
0
0.1
INL
DNL
0.05
0
INL
-0.05
-0.1
-0.15
RW
RW
40
-0.05
-0.1
DNL
0
0
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-37:
50 k Pot Mode – R (),
FIGURE 2-39:
50 k Rheo Mode – R (),
W
W
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 5.5V).
Ambient Temperature (V = 5.5V).
DD
DD
600
0.05
0.025
0
600
1.5
1
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
500
400
300
200
100
0
500
400
300
200
100
0
RW
DNL
0.5
0
INL
DNL
-0.025
-0.05
-0.075
-0.1
INL
-0.5
-1
RW
-1.5
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-38:
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 2.7V).
50 k Pot Mode – R (),
FIGURE 2-40:
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (V = 2.7V).
50 k Rheo Mode – R (),
W
W
DD
DD
2006-2017 Microchip Technology Inc.
DS20001945F-page 21
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
60000
50000
40000
30000
20000
10000
0
49800
49600
49400
49200
49000
48800
48600
48400
48200
48000
-40C
25C
85C
125C
VDD = 5.5V
VDD = 2.7V
-40 -20
0
20 40 60 80 100 120
Ambient Temperature (°C)
0
8
16
24
32
40
48
56
64
Wiper Setting (decimal)
FIGURE 2-41:
50 k – Nominal Resistance
FIGURE 2-42:
50 k – R
() vs. Wiper
WB
() vs. Ambient Temperature and V
.
Setting and Ambient Temperature.
DD
DS20001945F-page 22
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
U/D
U/D
WIPER
WIPER
FIGURE 2-43:
50 k – Low-Voltage
FIGURE 2-46:
50 k – Low-Voltage
Decrement Wiper Settling Time (V = 2.7V).
Increment Wiper Settling Time (V = 2.7V).
DD
DD
U/D
U/D
WIPER
WIPER
FIGURE 2-44:
50 k – Low-Voltage
FIGURE 2-47:
50 k - Low-Voltage
Decrement Wiper Settling Time (V = 5.5V).
Increment Wiper Settling Time (V = 5.5V).
DD
DD
WIPER
VDD
FIGURE 2-45:
50 k – Power-Up Wiper
Response Time.
2006-2017 Microchip Technology Inc.
DS20001945F-page 23
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
4.5
A
2.1 k:
4
3.5
3
2.5
2
1.5
1
0.5
0
+5V
W
VIN
VOUT
+
~
5 k:
-
OFFSET
GND
DUT
10 k:
50 k:
B
2.5V DC
-40
25
125
Temperature (°C)
FIGURE 2-49:
-3 dB Bandwidth Test
FIGURE 2-48:
-3 dB Bandwidth vs.
Circuit.
Temperature.
DS20001945F-page 24
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin
Type
Buffer
Type
MCP4022
MCP4023
(SOT-23-6)
Symbol
Function
MCP4021
(SOIC-8)
MCP4024
(SOT-23-5)
1
2
3
4
5
6
7
8
1
2
1
2
VDD
VSS
A
P
P
—
—
Positive Power Supply Input
Ground
6
—
5
I/O
I/O
I
A
Potentiometer Terminal A
Potentiometer Wiper Terminal
Chip Select Input
5
W
A
4
4
CS
B
TTL
A
—
—
3
—
—
3
I/O
—
I
Potentiometer Terminal B
No Connection
NC
U/D
—
TTL
Increment/Decrement Input
Legend: TTL = TTL compatible input
A = Analog input
O = Output
I = Input
P = Power
3.1
Positive Power Supply Input (VDD
)
3.4
Potentiometer Wiper (W) Terminal
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS and can range
from 2.7V to 5.5V. A decoupling capacitor on VDD (to
The terminal W pin is connected to the internal potenti-
ometer’s terminal W (the wiper). The wiper terminal is
the adjustable terminal of the digital potentiometer. The
terminal W pin does not have a polarity relative to
terminals A or B pins. The terminal W pin can support
both positive and negative current. The voltage on
VSS
)
is recommended to achieve maximum
performance.
terminal W must be between VSS and VDD
.
3.2
Ground (VSS)
The VSS pin is the device ground reference.
3.5
Potentiometer Terminal B
The terminal B pin is connected to the internal potenti-
ometer’s terminal B (available on some devices). The
potentiometer’s terminal B is the fixed connection to the
0x00 terminal of the digital potentiometer.
3.3
Potentiometer Terminal A
The terminal A pin is connected to the internal potenti-
ometer’s terminal A (available on some devices). The
potentiometer’s terminal A is the fixed connection to the
0x3F terminal of the digital potentiometer.
The terminal B pin is available on the MCP4021 device.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
The terminal A pin is available on the MCP4021,
MCP4022 and MCP4023 devices. The terminal A pin
does not have a polarity relative to the terminal W or B
pins. The terminal A pin can support both positive and
negative current. The voltage on terminal A must be
on terminal B must be between VSS and VDD
.
The terminal B pin is not available on the MCP4022,
MCP4023 and MCP4024 devices.
between VSS and VDD
.
For the MCP4023 and MCP4024, the internal potenti-
The terminal A pin is not available on the MCP4024.
The potentiometer’s terminal A is internally floating.
ometer’s terminal B is internally connected to VSS
.
Terminal B does not have a polarity relative to terminals
W or A. Terminal B can support both positive and
negative current.
For the MCP4022, terminal B is internally floating.
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MCP4021/2/3/4
3.6
Chip Select (CS)
3.7
Increment/Decrement (U/D)
The CS pin is the chip select input. Forcing the CS pin
to VIL enables the serial commands. These commands
can increment and decrement the wiper. Depending on
the command, the wiper may (or may not) be saved to
nonvolatile memory (EEPROM). Forcing the CS pin to
VIHH enables the high-voltage serial commands. These
commands can increment and decrement the wiper
and enable or disable the WiperLock technology. The
wiper is saved to nonvolatile memory (EEPROM).
The U/D pin input is used to increment or decrement
the wiper on the digital potentiometer. An increment
moves the wiper one step toward terminal A, while a
decrement moves the wiper one step toward
terminal B.
The CS pin has an internal pull-up resistor. The resistor
will become “disabled” when the voltage on the CS pin
is below the VIH level. This means that when the CS pin
is “floating”, the CS pin will be pulled to the VIH level
(serial communication (the U/D pin) is ignored). And
when the CS pin is driven low (VIL), the resistance
becomes very large to reduce the device current
consumption when serial commands are occurring.
See Figure 2-4 for additional information.
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MCP4021/2/3/4
EQUATION 4-1:
R CALCULATION
4.0
GENERAL OVERVIEW
S
RAB
The MCP402X devices are general purpose digital
potentiometers intended to be used in applications
where a programmable resistance with moderate
bandwidth is desired.
RS = ---------
63
EQUATION 4-2:
R
CALCULATION
WB
Applications generally suited for the MCP402X devices
include:
RAB
RWB = ------------- + RW
63
N
• Set point or offset trimming
N = 0 to 63 (decimal)
• Sensor calibration
• Selectable gain and offset amplifier designs
• Cost-sensitive mechanical trim pot replacement
1 LSb is the ideal resistance difference between two
successive codes. If we use N = 1 and RW = 0 in
Equation 4-2, we can calculate the step size for each
increment or decrement command.
The digital potentiometer is available in four nominal
resistances (RAB), where the nominal resistance is
defined as the resistance between terminal A and
terminal B. The four nominal resistances are 2.1 k,
5 k, 10 k and 50 k
The MCP4021 device offers
a voltage divider
(potentiometer) with all terminals available on pins.
The MCP4022 is a true rheostat, with terminal A and
the wiper (W) of the variable resistor available on pins.
There are 63 resistors in a string between terminal A
and terminal B. The wiper can be set to tap onto any of
these 63 resistors thus providing 64 possible settings
(including terminal A and terminal B).
The MCP4023 device offers a voltage divider (potenti-
ometer) with terminal B connected to ground.
The MCP4024 device is a rheostat device with terminal
A of the resistor floating, terminal B connected to
ground, and the wiper (W) available on pin.
Figure 4-1 shows a block diagram for the resistive
network of the device. Equation 4-1 shows the
calculation for the step resistance, while Equation 4-2
illustrates the calculation used to determine the
resistance between the wiper and terminal B.
The MCP4021 can be externally configured to
implement any of the MCP4022, MCP4023 or
MCP4024 configurations.
A
4.1
Serial Interface
3Fh
N = 63
(1)
A 2-wire synchronous serial protocol is used to
increment or decrement the digital potentiometer’s
wiper terminal. The Increment/Decrement (U/D)
protocol utilizes the CS and U/D input pins. Both inputs
are tolerant of signals up to 12.5V without damaging
the device. The CS pin can differentiate between two
high-voltage levels, VIH and VIHH. This enables
additional commands without requiring additional input
pins. The high-voltage commands (VIHH on the CS pin)
are similar to the standard commands, except that they
control (enable, disable, ...) the state of the nonvolatile
WiperLock technology feature.
RW
RS
RS
RS
N = 62
N = 61
3Eh
3Dh
(1)
(1)
RW
RW
W
N = 1
N = 0
01h
00h
The simple U/D protocol uses the state of the U/D pin
at the falling edge of the CS pin to determine if
Increment or Decrement mode is desired. Subsequent
rising edges of the U/D pin move the wiper.
(1)
(1)
RW
RW
RS
The wiper value will not underflow or overflow. The new
wiper setting can be saved to EEPROM, if desired, by
selecting the state of the U/D pin during the rising edge
of the CS pin.
B
Analog
Mux
Note 1: The wiper resistance is tap dependent.
That is, each tap selection resistance
has a small variation. This variation
effects the smaller resistance devices
(2.1 k) more.
The nonvolatile wiper enables the MCP4021/2/3/4 to
operate stand alone (without microcontroller control).
FIGURE 4-1:
Resistor Block Diagram.
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MCP4021/2/3/4
The default settings of the MCP4021/2/3/4 device’s
from the factory are shown in Table 4-1.
4.2
The WiperLock Technology
The MCP4021/2/3/4 device’s WiperLock technology
allows application-specific calibration settings to be
secured in the EEPROM without requiring the use of an
additional write-protect pin.
TABLE 4-1:
DEFAULT FACTORY
SETTINGS SELECTION
The WiperLock technology prevents the serial
commands from doing the following:
• Incrementing or decrementing the wiper setting
• Writing the wiper setting to the nonvolatile
memory
–202 Mid-scale
–502 Mid-scale
–103 Mid-scale
–503 Mid-scale
1Fh
1Fh
1Fh
1Fh
Disabled
Disabled
Disabled
Disabled
2.1 k
5.0 k
Enabling and disabling the WiperLock technology
feature requires high-voltage serial commands
(CS = VIHH). Incrementing and decrementing the wiper
requires high-voltage commands when the feature is
enabled. The high-voltage threshold (VIHH) is intended
to prevent the wiper setting from being altered by noise
or intentional transitions on the U/D and CS pins, while
still providing flexibility for production or calibration
environments.
10.0 k
50.0 k
It is good practice in your manufacturing flow to
configure the device to your desired settings.
4.4
Brown-Out
Both the CS and U/D input pins are tolerant of signals
up to 12V. This allows the flexibility to multiplex the
digital pot’s control signals onto application signals for
manufacturing/calibration.
If the device VDD is below the specified minimum
voltage, care must be taken to ensure that the CS and
U/D pins do not “create” any of the serial commands.
When the device VDD drops below Vmin (2.7V), the
electrical performance may not meet the data sheet
specifications (see Figure 4-2). The wiper may be
unknown or initialized to the value stored in the
EEPROM. Also the device may be capable of
incrementing, decrementing and writing to its EEPROM
if a valid command is detected on the CS and U/D pins.
4.3
Power-up
When the device powers up, the last saved wiper
setting is restored.
While VDD < Vmin (2.7V), the electrical performance
may not meet the data sheet specifications (see
Figure 4-2). The wiper may be unknown or initialized to
the value stored in the EEPROM. Also the device may
be capable of incrementing, decrementing and writing
to its EEPROM, if a valid command is detected on the
CS and U/D pins.
4.5
Serial Interface Inactive
The serial interface is inactive any time the CS pin is at
VIH and all write cycles are completed.
EEPROM
Write
Protect
Outside
Specified AC/DC
Range
VDD
2.7V
VWP
VSS
FIGURE 4-2:
Power-up and Brown-out.
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MCP4021/2/3/4
5.2
Serial Commands
5.0
5.1
SERIAL INTERFACE
Overview
The MCP402X devices support 10 serial commands.
The commands can be grouped into the following
types:
The MCP4021/2/3/4 utilizes a simple 2-wire interface to
increment or decrement the digital potentiometer’s
wiper terminal (W), store the wiper setting in nonvolatile
memory and turn the WiperLock technology feature on
or off. This interface uses the Chip Select (CS) pin,
while the U/D pin is the Up/Down input.
• Serial Commands
• High-voltage Serial Commands
All the commands are shown in Table 5-1.
The command type is determined by the voltage level
on the CS pin. The initial state that the CS pin must be
driven is VIH. From VIH, the two levels that the CS pin
can be driven are:
The Increment/Decrement protocol enables the
device to move one step at a time through the range
of possible resistance values. The wiper value is
initialized with the value stored in the internal
EEPROM upon power-up. A wiper value of 00h con-
nects the wiper to terminal B. A wiper value of 3Fh
connects the wiper to terminal A. Increment com-
mands move the wiper toward terminal A, but will not
increment to a value greater than 3Fh. Decrement
commands move the wiper toward terminal B, but
will not decrement below 00h.
• VIL
• VIHH
If the CS pin is driven from VIH to VIL, a serial
command is selected. If the CS pin is driven from VIH to
VIHH, a high-voltage serial command is selected.
High-voltage serial commands control the state of the
WiperLock technology. This is a unique feature, where
the user can determine whether or not to “lock” or
“unlock” the wiper state.
Refer to Section 1.0 “Electrical Characteristics”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.
High-voltage serial commands increment/decrement
the wiper regardless of the status of the WiperLock
technology.
Communication is unidirectional. Therefore, the value
of the current wiper setting cannot be read out of the
MCP402X device.
TABLE 5-1:
COMMANDS
After
Command
Wiper is
“locked”/
”unlocked”
Saves
Wiper
Value in
EEPROM
High
Voltage
on CS
pin?
Works
when
Wiper is
“locked”?
Command Name
Increment without Writing Wiper Setting to EEPROM
Increment with Writing Wiper Setting to EEPROM
Decrement without Writing Wiper Setting to EEPROM
Decrement with Writing Wiper Setting to EEPROM
Write Wiper Setting to EEPROM
—
—
—
unlocked
unlocked
unlocked
unlocked
unlocked
unlocked
locked
Note 1
Note 1
Note 1
Note 1
Note 1
Yes
Yes
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
High-Voltage Increment and Disable WiperLock Technology
High-Voltage Increment and Enable WiperLock Technology
High-Voltage Decrement and Disable WiperLock Technology
High-Voltage Decrement and Enable WiperLock Technology
Yes
Yes
Yes
Yes
Yes
Yes
unlocked
locked
Yes
Yes
Write Wiper Setting to EEPROM and Disable WiperLock
Technology
unlocked
Yes
Write Wiper Setting to EEPROM and Enable WiperLock
Technology
Yes
Yes
locked
Yes
Note 1: This command will only complete if wiper is “unlocked” (WiperLock Technology is Disabled).
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MCP4021/2/3/4
The EEPROM value has not been updated to this new
wiper value, so if the device voltage is lowered below
the RAM retention voltage of the device, once the
device returns to the operating range, the wiper will be
loaded with the wiper setting in the EEPROM.
5.2.1
INCREMENT WITHOUT WRITING
WIPER SETTING TO EEPROM
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to achieving a low state (VIL) on the
CS pin. Subsequent rising edges of the U/D pin
increment the wiper setting toward terminal A. This is
shown in Figure 5-1.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered. This is
since an EEPROM write cycle (twc) is not active.
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
“unexpected” transitions (on the U/D pin do not cause
the wiper setting to increment. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
Note:
The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
VIH
VIL
CS
VIH
6
5
1
2
3
4
U/D
VIL
X
X
X
X
X
EEPROM
X+1 X+2
X+3 X+4
X
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
Note: If WiperLock technology enabled, wiper will not move.
Increment without Writing Wiper Setting to EEPROM.
FIGURE 5-1:
DS20001945F-page 30
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MCP4021/2/3/4
To ensure that “unexpected” transitions on the U/D pin
do not cause the wiper setting to increment, the U/D pin
should be driven low and the CS pin forced to VIH as
soon as possible (within device specifications) after the
last desired increment occurs.
5.2.2
INCREMENT WITH WRITING WIPER
SETTING TO EEPROM
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to achieving a low state (VIL) on the
CS pin. Subsequent rising edges of the U/D pin
increment the wiper setting toward terminal A. This is
shown in Figure 5-2.
After the CS pin is driven to VIH (from VIL), all other
serial commands are ignored until the EEPROM write
cycle (twc) completes.
After the wiper is incremented to the desired position,
the U/D pin should be driven low (VIL). Then when the
CS pin is forced to VIH, the wiper value is written to the
EEPROM. Therefore, if the device voltage is lowered
below the RAM retention voltage of the device, once
the device returns to the operating range, the wiper will
be loaded with this wiper setting (stored in the
EEPROM).
Note:
The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
VIH
VIH
VIL
CS
tWC
VIH
6
1
2
3
4
5
VIL
U/D
X
X
X
X
X
X+4
EEPROM
X+1 X+2
X+3 X+4
X
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
Note: If WiperLock technology enabled, wiper will not move.
Increment with Writing Wiper Setting to EEPROM.
FIGURE 5-2:
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MCP4021/2/3/4
The EEPROM value has not been updated to this new
wiper value, so, if the device voltage is lowered below
the RAM retention voltage of the device, once the
device returns to the operating range, the wiper will be
loaded with the wiper setting in the EEPROM.
5.2.3
DECREMENT WITHOUT WRITING
WIPER SETTING TO EEPROM
This mode is achieved by initializing the U/D pin to a low
state (VIL) prior to achieving a low state (VIL) on the CS
pin. Subsequent rising edges of the U/D pin will
decrement the wiper setting toward terminal B. This is
shown in Figure 5-3.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered, since an
EEPROM write cycle (tWC) is not started.
After the wiper is decremented to the desired position,
the U/D pin should be forced low (VIL) and the CS pin
should be forced to VIH. This will ensure that
“unexpected” transitions on the U/D pin do not cause
the wiper setting to decrement. Driving the CS pin to
VIH should occur as soon as possible (within device
specifications) after the last desired increment occurs.
Note:
The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
VIH
VIL
CS
6
5
VIH
1
2
3
4
VIL
VIL
U/D
X
X
X
X
X
EEPROM
X
X-1
X-2
X-3
X-4
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
Note: If WiperLock technology enabled, wiper will not change.
FIGURE 5-3:
Decrement without Writing Wiper Setting to EEPROM.
DS20001945F-page 32
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MCP4021/2/3/4
To ensure that “unexpected” transitions on the U/D pin
do not cause the wiper setting to decrement, the U/D
pin should be driven low (VIL) and the CS pin forced to
VIH as soon as possible (within device specifications)
after the last desired increment occurs.
5.2.4
DECREMENT WITH WRITING
WIPER SETTING TO EEPROM
This mode is achieved by initializing the U/D pin to a
low state (VIL) prior to achieving a low state (VIL) on the
CS pin. Subsequent rising edges of the U/D pin
decrement the wiper setting (toward terminal B). This is
shown in Figure 5-4.
After the CS pin is driven to VIH (from VIL), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
After the wiper is decremented to the desired position,
the U/D pin should remain high (VIH). Then when the
CS pin is raised to VIH, the wiper value is written to the
EEPROM. Therefore, if the device voltage is lowered
below the RAM retention voltage of the device, once
the device returns to the operating range, the wiper will
be loaded with this wiper setting (stored in the
EEPROM).
Note:
The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
VIH
VIL
CS
tWC
VIH
1
2
3
4
5
6
VIL
U/D
X
X
X
X
X
EEPROM
X-4
X-1
X-2
X-3
X-4
X
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
Note: If WiperLock technology enabled, wiper will not change.
FIGURE 5-4:
Decrement with Writing Wiper Setting to EEPROM.
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DS20001945F-page 33
MCP4021/2/3/4
When the CS pin is forced to VIH, the wiper value is
written to the EEPROM. Therefore, if the device
voltage is lowered below the RAM retention voltage of
the device, once the device returns to the operating
range, the wiper will be loaded with this wiper setting
(stored in the EEPROM).
5.2.5
WRITE WIPER SETTING TO
EEPROM
To write the current wiper setting to EEPROM, force
both the CS pin and U/D pin to VIH. Then force the CS
pin to VIL. Before there is a rising edge on the U/D pin,
force the CS pin to VIH. This causes the wiper setting
value to be written to EEPROM.
To ensure that “unexpected” transitions on the U/D pin
do not cause the wiper setting to increment, force the
CS pin to VIH as soon as possible (within device
specifications) after the U/D pin is forced to VIL.
Note:
After the U/D pin is forced to VIL, each rising
edge on the U/D pin will cause the wiper to
increment.
This is the same command as the “Incre-
ment with Writing Wiper Setting to
EEPROM“command, but the U/D pin is held
at VIL, so the wiper is not incremented.
After the CS pin is driven to VIH (from VIL), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
VIH
VIH
VIL
CS
tWC
VIH
6
5
VIL
U/D
X
EEPROM
X+4
X+4
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
FIGURE 5-5:
Write Wiper Setting to EEPROM.
DS20001945F-page 34
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MCP4021/2/3/4
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
5.2.6
HIGH-VOLTAGE INCREMENT AND
DISABLE WiperLock TECHNOLOGY
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to the CS pin being driven to VIHH
.
Note:
The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
Subsequent rising edges of the U/D pin increment the
wiper setting toward terminal A. Set the U/D pin to the
high state (VIH) prior to forcing the CS pin to VIH. This
begins a write cycle and disables the WiperLock
technology feature (See Figure 5-6).
VIHH
VIH
VIH
CS
tWC
VIH
VIH
6
1
2
3
4
5
U/D
VIL
X
X
X
X
X
X+4
EEPROM
X+1 X+2
X+3 X+4
X
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
FIGURE 5-6:
High-Voltage Increment and Disable WiperLock Technology.
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DS20001945F-page 35
MCP4021/2/3/4
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
5.2.7
HIGH-VOLTAGE INCREMENT AND
ENABLE WiperLock TECHNOLOGY
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to the CS pin being driven to VIHH
.
Note:
The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
Subsequent rising edges of the U/D pin increment the
wiper setting toward terminal A. Set the U/D pin to the
low state (VIL) prior to forcing the CS pin to VIH. This
begins a write cycle and enables the WiperLock
technology feature (See Figure 5-7).
VIHH
VIH
VIH
CS
tWC
VIH
6
1
2
3
4
5
VIL
U/D
VIL
X
X
X
X
X
X+4
EEPROM
X+1 X+2
X+3 X+4
X
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
FIGURE 5-7:
High-Voltage Increment and Enable WiperLock Technology.
DS20001945F-page 36
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MCP4021/2/3/4
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
5.2.8
HIGH-VOLTAGE DECREMENT AND
DISABLE WiperLock TECHNOLOGY
This mode is achieved by initializing the U/D pin to a
low state (VIL) prior to the CS pin being driven to VIHH
.
Note:
The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
Subsequent rising edges of the U/D pin decrement the
wiper setting toward terminal B. Set the U/D pin to the
low state (VIL) prior to forcing the CS pin to VIH. This
begins a write cycle and disables the WiperLock
Technology feature (See Figure 5-8).
VIHH
VIH
VIH
CS
tWC
1
2
3
4
6 VIH
5
VIL
VIL
U/D
X
X
X
X
X
X-4
EEPROM
X-1
X-2
X-3
X-4
X
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
FIGURE 5-8:
High-Voltage Decrement and Disable WiperLock Technology.
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DS20001945F-page 37
MCP4021/2/3/4
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
5.2.9
HIGH-VOLTAGE DECREMENT AND
ENABLE WiperLock TECHNOLOGY
This mode is achieved by initializing the U/D pin to the
low state (VIL) prior to driving the CS pin to VIHH
.
Note:
The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
Subsequent rising edges of the U/D pin decrement the
wiper setting toward terminal B. Set the U/D pin to a
high state (VIH) prior to forcing the CS pin to VIH. This
begins a write cycle and enables the WiperLock
technology feature (See Figure 5-9).
VIHH
VIH
VIH
CS
tWC
VDD
VIH
6
5
1
2
3
4
U/D
VIL
X
X
X
X
X
X-4
EEPROM
X-1
X-2
X-3
X-4
X
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
FIGURE 5-9:
High-Voltage Decrement and Enable WiperLock Technology.
DS20001945F-page 38
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MCP4021/2/3/4
To ensure that unexpected transitions on the U/D pin
do not cause the wiper setting to change, force the CS
pin to VIH as soon as possible (within device
5.2.10
WRITE WIPER SETTING TO
EEPROM AND DISABLE WiperLock
TECHNOLOGY
specifications) after the CS pin is forced to VIHH
.
This mode is achieved by keeping the U/D pin static
(either at VIL or at VIH), while the CS pin is driven from
VIH to VIHH and then returned to VIH. When the falling
edge of the CS pin occurs (from VIHH to VIH), the wiper
value is written to EEPROM and the WiperLock
technology is disabled (See Figure 5-10).
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
VIHH
VIH
CS
VIH
tWC
VIH
U/D
VIL
X
EEPROM
X+4
X+4
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
FIGURE 5-10:
Write Wiper Setting to EEPROM and Disable WiperLock Technology.
2006-2017 Microchip Technology Inc.
DS20001945F-page 39
MCP4021/2/3/4
To ensure that “unexpected” transitions on the U/D pin
do not cause the wiper setting to increment, force the
CS pin to VIH as soon as possible (within device
specifications) after the U/D pin is forced to VIL.
5.2.11
WRITE WIPER SETTING TO
EEPROM AND ENABLE WiperLock
TECHNOLOGY
This mode is achieved by initializing the U/D and CS
pins to a high state (VIH) prior to the CS pin being driven
to VIHH (from VIH). Set the U/D pin to a low state (VIL)
prior to forcing the CS pin to VIH (from VIHH). This
begins a write cycle and enables the WiperLock
technology feature (See Figure 5-11).
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
VIHH
VIH
VIH
CS
tWC
VIH
U/D
VIL
X
EEPROM
X+4
X+4
Wiper
WiperLock Technology Enable
WiperLock Technology Disable
WiperLock Technology
FIGURE 5-11:
Write Wiper Setting to EEPROM and Enable WiperLock Technology.
DS20001945F-page 40
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
The circuit in Figure 5-13 shows the method used on
the MCP402X Nonvolatile Digital Potentiometer
Evaluation Board. This method requires that the
system voltage be approximately 5V. This ensures that
when the PIC10F206 enters a brown-out condition,
there is an insufficient voltage level on the CS pin to
change the stored value of the wiper. The MCP402X
Non-volatile Digital Potentiometer Evaluation Board
5.3
CS High Voltage
Depending on the requirements of the system, the use
of high voltage (VIHH) on the CS pin, may or may not be
required during system operation. Table 5-2 shows
possible system applications, and whether a high
voltage (VIHH) is required on the system.
The MCP402X supports six high-voltage commands
(the CS input voltage must meet the VIHH
specification).
User’s Guide (DS51546) contains
schematic.
a
complete
GP0 is a general purpose I/O pin, while GP2 can either
be a general purpose I/O pin or it can output the internal
clock.
TABLE 5-2:
HIGH-VOLTAGE
APPLICATIONS
For the serial commands, configure the GP2 pin as an
input (high impedance). The output state of the GP0 pin
will determine the voltage on the CS pin (VIL or VIH).
High
Voltage
System Operation
Production calibration only - system
should not update wiper setting
From
Calibration
Unit
For high-voltage serial commands, force the GP0
output pin to output a high level (VOH) and configure the
GP2 pin to output the internal clock. This will form a
charge pump and increase the voltage on the CS pin
(when the system voltage is approximately 5V).
WiperLock Technology disabled during
system operation
Not
Required
Wiper setting can be updated and
“locked” during system operation
Required
PIC10F206
R1
5.3.1
TECHNIQUES TO FORCE THE CS
PIN TO V
GP0
IHH
MCP402X
The circuit in Figure 5-12 shows a method using the
TC1240A doubling charge pump. When the SHDN pin
is high, the TC1240A is off, and the level on the CS pin
is controlled by the PIC® microcontrollers (MCUs) IO2
pin.
GP2
CS
C2
C1
When the SHDN pin is low, the TC1240A is on and the
VOUT voltage is 2 * VDD. The resistor R1 allows the CS
pin to go higher than the voltage such that the PIC
MCU’s IO2 pin “clamps” at approximately VDD.
FIGURE 5-13:
Digital Potentiometer Evaluation Board
MCP402X Non-volatile
(MCP402XEV) implementation to Generate the
V
Voltage.
IHH
TC1240A
VIN
C+
PIC® MCU
C1
C-
SHDN
VOUT
IO1
MCP402X
R1
CS
IO2
C2
FIGURE 5-12:
Generate the V
Using the TC1240A to
Voltage.
IHH
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MCP4021/2/3/4
Step resistance (RS) is the resistance from one tap
setting to the next. This value will be dependent on the
6.0
RESISTOR
Digital potentiometer applications can be divided into
two categories:
RAB value that has been selected. Table 6-1 shows the
typical step resistances for each device.
• Rheostat configuration
The total resistance of the device has minimal variation
due to operating voltage (see Figure 2-6, Figure 2-17,
Figure 2-27 or Figure 2-37).
• Potentiometer (or voltage divider) configuration
Figure 6-1 shows a block diagram for the MCP402X
resistors.
TABLE 6-1:
Part Number
TYPICALSTEPRESISTANCES
Typical Resistance ()
A
3Fh
N = 63
Total (RAB
)
Step (RS)
(1)
RW
MCP402X-202E
MCP402X-502E
MCP402X-103E
MCP402X-503E
2100
5000
33.33
79.37
RS
RS
RS
N = 62
N = 61
3Eh
3Dh
10000
50000
158.73
793.65
(1)
(1)
RW
RW
Terminal A and B, as well as the wiper W, do not have
a polarity. These terminals can support both positive
and negative current.
W
N = 1
N = 0
01h
00h
(1)
(1)
RW
RW
RS
B
Analog
Mux
Note 1: The wiper resistance is tap dependent.
That is, each tap selection resistance
has a small variation. This variation
effects the smaller resistance devices
(2.1 k) more.
FIGURE 6-1:
Resistor Block Diagram.
DS20001945F-page 42
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MCP4021/2/3/4
6.1.2
POTENTIOMETER
CONFIGURATION
6.1
Resistor Configurations
6.1.1
RHEOSTAT CONFIGURATION
When used as a potentiometer, all three terminals are
tied to different nodes in the circuit. This allows the
potentiometer to output a voltage proportional to the
input voltage. This configuration is sometimes called
voltage divider mode. The potentiometer is used to
provide a variable voltage by adjusting the wiper
position between the two endpoints as shown in
Figure 6-3. Reversing the polarity of the A and B
terminals will not affect operation.
When used as a rheostat, two of the three digital
potentiometer’s terminals are used as a resistive
element in the circuit. With terminal W (wiper) and
either terminal A or terminal B, a variable resistor is
created. The resistance will depend on the tap setting
of the wiper and the wiper’s resistance. The resistance
is controlled by changing the wiper setting.
The unused terminal (B or A) should be left floating.
Figure 6-2 shows the two possible resistors that can be
used. Reversing the polarity of the A and B terminals
will not affect operation.
V1
A
V3
W
A
B
RAW
or
RBW
V2
W
B
FIGURE 6-3:
Potentiometer Configuration.
The temperature coefficient of the RAB resistors is
minimal by design. In this configuration, the resistors all
change uniformly, so minimal variation should be seen.
Resistor
Rheostat Configuration.
FIGURE 6-2:
The wiper resistor temperature coefficient is different
from the RAB temperature coefficient. The voltage at
node V3 (Figure 6-3) is not dependent on this wiper
resistance, just the ratio of the RAB resistors, so this
temperature coefficient in most cases can be
ignored.
This allows the control of the total resistance between
the two nodes. The total resistance depends on the
“starting” terminal to the wiper terminal. At the code
00h, the RBW resistance is minimal (RW), but the RAW
resistance in maximized (RAB + RW). Conversely, at the
code 3Fh, the RAW resistance is minimal (RW), but the
RBW resistance in maximized (RAB + RW).
Note:
To avoid damage to the internal wiper
circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
The resistance step size (RS) equates to one LSb of the
resistor.
Note:
To avoid damage to the internal wiper
circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
The change in wiper-to-end terminal resistance over
temperature is shown in Figure 2-6, Figure 2-17,
Figure 2-27 and Figure 2-37. The most variation over
temperature will occur in the first few codes due to the
wiper resistance coefficient affecting the total
resistance. The remaining codes are dominated by the
total resistance tempco RAB
.
2006-2017 Microchip Technology Inc.
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MCP4021/2/3/4
The slope of the resistance has a linear area (at the
higher voltages) and a nonlinear area (at the lower volt-
ages), where resistance increases faster than the volt-
age drop (at low voltages).
6.2
Wiper Resistance
Wiper resistance is the series resistance of the wiper.
This resistance is typically measured when the wiper is
positioned at either zero-scale (00h) or full-scale (3Fh).
The wiper resistance in potentiometer-generated
voltage divider applications is not a significant source
of error.
The wiper resistance in rheostat applications can
create significant nonlinearity as the wiper is moved
toward zero-scale (00h). The lower the nominal
resistance, the greater the possible error.
RW
Wiper resistance is significant depending on the
devices operating voltage. As the device voltage
decreases, the wiper resistance increases (see
Figure 6-4 and Table 6-2).
VDD
Note:
The slope of the resistance has a linear
area (at the higher voltages) and a non-
linear area (at the lower voltages).
In a rheostat configuration, this change in voltage
needs to be taken into account, particularly for the
lower resistance devices. For the 2.1 k device, the
maximum wiper resistance at 5.5V is approximately 6%
of the total resistance, while at 2.7V, it is approximately
15.5% of the total resistance.
FIGURE 6-4:
Relationship of Wiper
Resistance (R ) to Voltage.
W
Since there is minimal variation of the total device
resistance over voltage, at a constant temperature (see
Figure 2-6, Figure 2-17, Figure 2-27 or Figure 2-37),
the change in wiper resistance over voltage can have a
significant impact on the INL and DNL error.
In a potentiometer configuration, the wiper resistance
variation does not effect the output voltage seen on the
terminal W pin.
TABLE 6-2:
Typical
TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE
Resistance ()
Wiper (RW)
Step Max @ Max @
RW / RS (%) (1)
RW / RAB (%) (2)
RW
Typical
=
RW = Max RW = Max
@ 5.5V
RW
=
RW = Max RW = Max
Total
@ 2.7V
Typical
@ 5.5V
@ 2.7V
Typical
(RAB
)
(RS)
5.5V
2.7V
2100
5000
33.33
79.37
75
75
75
75
125
125
125
125
325
325
325
325
225.0%
94.5%
47.25%
9.45%
375.0%
157.5%
78.75%
15.75%
975.0%
409.5%
204.75%
40.95%
3.57%
1.5%
5.95%
2.50%
1.25%
0.25%
15.48%
6.50%
3.25%
0.65%
10000 158.73
50000 793.65
0.75%
0.15%
Note 1: RS is the typical value. The variation of this resistance is minimal over voltage.
2: RAB is the typical value. The variation of this resistance is minimal over voltage.
DS20001945F-page 44
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
6.3.1.2
Differential Non-Linearity (DNL)
6.3
Operational Characteristics
DNL error is the measure of variations in code widths
from the ideal code width. A DNL error of zero would
imply that every code is exactly 1 LSb wide.
Understanding the operational characteristics of the
device’s resistor components is important to the system
design.
6.3.1
ACCURACY
6.3.1.1
Integral Nonlinearity (INL)
111
INL error for these devices is the maximum deviation
between an actual code transition point and its
corresponding ideal transition point after offset and
gain errors have been removed. These endpoints are
from 0x00 to 0x3F. Refer to Figure 6-5.
110
Actual
Transfer
Function
101
Digital
Input
Code
100
011
010
001
000
Ideal Transfer
Function
Positive INL means higher resistance than ideal.
Negative INL means lower resistance than ideal.
Wide Code, > 1 LSb
INL < 0
111
Narrow Code < 1 LSb
Actual
Transfer
Function
110
101
100
Digital Pot Output
FIGURE 6-6:
DNL Accuracy.
Digital
Input
6.3.1.3 Ratiometric Temperature Coefficient
Code
011
010
001
000
The ratiometric temperature coefficient quantifies the
error in the ratio RAW/RWB due to temperature drift.
This is typically the critical error when using a
potentiometer device (MCP4021 and MCP4023) in a
voltage divider configuration.
Ideal Transfer
Function
6.3.1.4
Absolute Temperature Coefficient
INL < 0
The absolute temperature coefficient quantifies the
error in the end-to-end resistance (nominal resistance
RAB) due to temperature drift. This is typically the
critical error when using a rheostat device (MCP4022
and MCP4024) in an adjustable resistor configuration.
Digital Pot Output
FIGURE 6-5:
INL Accuracy.
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MCP4021/2/3/4
6.3.2
MONOTONIC OPERATION
Monotonic operation means that the device’s
resistance increases with every step change (from
terminal A to terminal B or terminal B to terminal A).
The wiper resistance is different at each tap location.
When changing from one tap position to the next (either
increasing or decreasing), the RW is less than the
RS. When this change occurs, the device voltage and
temperature are the same for the two tap positions.
RS63
0x3F
0x3E
RS62
0x3D
RS3
0x03
RS1
0x02
RS0
0x01
0x00
RW
n = ?
(@ tap)
RBW
=
RSn + RW(@ Tap n
)
n = 0
Resistance (RBW
)
FIGURE 6-7:
Resistance, R
.
BW
DS20001945F-page 46
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MCP4021/2/3/4
7.2
Layout Considerations
7.0
DESIGN CONSIDERATIONS
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP402X’s performance.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs, isolated
outputs and proper decoupling are critical to achieving
the performance that the silicon is capable of providing.
Particularly harsh environments may require shielding
of critical signals.
In the design of a system with the MCP402X devices,
the following considerations should be taken into
account:
• The power supply
• The layout
7.1
Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 7-1 illustrates an
appropriate bypass strategy.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
VDD
0.1 µF
VDD
0.1 µF
A
W
U/D
CS
B
VSS
VSS
FIGURE 7-1:
Typical Microcontroller
Connections.
2006-2017 Microchip Technology Inc.
DS20001945F-page 47
MCP4021/2/3/4
8.0
APPLICATIONS EXAMPLES
VDD
R1
Nonvolatile digital potentiometers have a multitude of
practical uses in modern electronic circuits. The most
popular uses include precision calibration of set point
thresholds, sensor trimming, LCD bias trimming, audio
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP4021/2/3/4 devices can be
used to replace the common mechanical trim pot in
applications where the operating and terminal voltages
are within CMOS process limitations (VDD = 2.7V to
5.5V).
MCP4021
A
CS
W
VOUT
U/D
B
R2
8.1
Set Point Threshold Trimming
FIGURE 8-1:
Potentiometer to Set a Precise Output Voltage.
Using the Digital
Applications that need accurate detection of an input
threshold event often need several sources of error
eliminated. Use of comparators and operational
amplifiers (op amps) with low offset and gain error can
help achieve the desired accuracy, but in many applica-
tions, the input source variation is beyond the
designer’s control. If the entire system can be
calibrated after assembly in a controlled environment
(like factory test), these sources of error are minimized,
if not entirely eliminated.
8.1.1
TRIMMING A THRESHOLD FOR AN
OPTICAL SENSOR
If the application has to calibrate the threshold of a
diode, transistor or resistor, a variation range of 0.1V is
common. Often, the desired resolution of 2 mV or
better is adequate to accurately detect the presence of
a precise signal. A “windowed” voltage divider, utilizing
the MCP4021 or MCP4023, would be a potential
solution, as shown in Figure 8-2.
Figure 8-1 illustrates a common digital potentiometer
configuration. This configuration is often referred to as
a “windowed voltage divider”. Note that R1 and R2 are
not necessary to create the voltage divider, but their
presence is useful when the desired threshold has
limited range. It is “windowed” because R1 and R2 can
narrow the adjustable range of VTRIP to a value much
less than VDD – VSS. If the output range is reduced, the
magnitude of each output step is reduced. This
effectively increases the trimming resolution for a fixed
digital potentiometer resolution. This technique may
allow a lower-cost digital potentiometer to be utilized
(64 steps instead of 256 steps).
VDD
VDD
VCC+
Rsense
R1
Comparator
MCP4021
CS
A
B
The MCP4021’s and
MCP4023’s low DNL
VTRIP
W
performance is critical to meeting calibration accuracy
in production without having to use a higher precision
digital potentiometer.
MCP6021
VCC–
U/D
0.1 µF
R2
EQUATION 8-1:
CALCULATING THE
WIPER SETTING FROM
THE DESIRED V
TRIP
FIGURE 8-2:
Calibration.
Set Point or Threshold
R2 + RWB
----------------------------------
VTRIP = VDD
R1 + RAB + R2
RAB = RNominal
D
63
-----
RWB = RAB
VTRIP
--------------
D =
R1 + RAB + R2 – R2 63
VDD
Where:
D = Digital Potentiometer Wiper Setting (0-63)
DS20001945F-page 48
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
8.2
Operational Amplifier
Applications
VDD
MCP6291
VIN
+
Figure 8-3, Figure 8-4 and Figure 8-5 illustrate typical
amplifier circuits that could replace fixed resistors with
the MCP4021/2/3/4 to achieve digitally-adjustable
analog solutions.
Op Amp
–
VDD
VW
VOUT
R1
Figure 8-4 shows a circuit that allows a non-inverting
amplifier to have its’ offset and gain to be independently
trimmed. The MCP4021 is used along with resistors R1
and R2 to set the offset voltage. The sum of R1 + R2
resistance should be significantly greater (> 100 times)
the resistance value of the MCP4021. This allows each
increment or decrement in the MCP4021 to be a fine
adjustment of the offset voltage. The input voltage of
the op amp (VIN) should be centered at the op amps VW
voltage. The gain is adjusted by the MCP4022. If the
resistance value of the MCP4022 is small compared to
the resistance value of R3, then this is a fine
adjustment of the gain. If the resistance value of the
MCP4022 is equal (or large) compared to the
resistance value of R3, then this is a course adjustment
of the gain. In general, trim the course adjustments first
and then trim the fine adjustments.
R3
W
A
B
A
W
MCP4022
R2
FIGURE 8-4:
a Noninverting Amplifier.
Trimming Offset and Gain in
MCP4021
R3
R4
B
A
W
Pot2
VDD
–
Op Amp
+
R1
VOUT
MCP4021
VIN
R3
R4
MCP6021
B
A
A
B
VIN
W
W
1
fc = -----------------------------
Pot1
MCP4022
2 R C
Eq
VDD
–
R2
Op Amp
+
R1
VOUT
Thevenin
Equivalent
MCP6001
REq = R1 + RAB – RWB
R2 + RWB + Rw
A
B
W
FIGURE 8-5:
Programmable Filter.
R2
FIGURE 8-3:
Trimming Offset and Gain in
an Inverting Amplifier.
2006-2017 Microchip Technology Inc.
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MCP4021/2/3/4
8.3
Temperature Sensor Applications
VDD
Thermistors are resistors with very predictable
variation with temperature. Thermistors are a popular
sensor choice when a low-cost, temperature-sensing
solution is desired. Unfortunately, thermistors have
nonlinear characteristics that are undesirable, typically
requiring trimming in an application to achieve greater
accuracy. There are several common solutions to trim
and linearize thermistors. Figure 8-6 and Figure 8-7
are simple methods for linearizing a 3-terminal NTC
thermistor. Both are simple voltage dividers using a
Positive Temperature Coefficient (PTC) resistor (R1)
with a transfer function capable of compensating for the
linearity error in the Negative Temperature Coefficient
(NTC) thermistor.
R1
NTC
Thermistor
MCP4021
VOUT
R2
The circuit, illustrated by Figure 8-6, utilizes a digital
rheostat for trimming the offset error caused by the
thermistor’s part-to-part variation. This solution puts the
digital potentiometer’s RW into the voltage divider
calculation. The MCP4021/2/3/4’s RAB temperature
coefficient is 50 ppm (-20°C to +70°C). RW’s error is
substantially greater than RAB’s error because RW
varies with VDD, wiper setting and temperature. For the
50 k devices, the error introduced by RW is, in most
cases, insignificant as long as the wiper setting is > 6.
For the 2 k devices, the error introduced by RW is
FIGURE 8-7:
a Digital Potentiometer in a Potentiometer
Configuration.
Thermistor Calibration using
8.4
Wheatstone Bridge Trimming
Another common configuration to “excite” a sensor
(such as a strain gauge, pressure sensor or thermistor)
is the wheatstone bridge configuration. The wheat-
stone bridge provides a differential output instead of a
significant because it is a higher percentage of RWB
.
single-ended output. Figure 8-8 illustrates
a
For these reasons, the circuit illustrated in Figure 8-6 is
not the most optimum method for “exciting” and
linearizing a thermistor.
wheatstone bridge utilizing one to three digital
potentiometers. The digital potentiometers in this
example are used to trim the offset and gain of the
wheatstone bridge.
VDD
VDD
R1
NTC
Thermistor
VOUT
R2
2.1 k
MCP4022
A
MCP4022
VOUT
W
MCP4022
50 k
MCP4022
50 k
FIGURE 8-6:
a Digital Potentiometer in a Rheostat
Configuration.
Thermistor Calibration using
The circuit illustrated by Figure 8-7 utilizes a digital
potentiometer for trimming the offset error. This
solution removes RW from the trimming equation along
with the error associated with RW. R2 is not required,
but can be utilized to reduce the trimming “window” and
reduce variation due to the digital potentiometer’s RAB
part-to-part variability.
FIGURE 8-8:
Trimming.
Wheatstone Bridge
DS20001945F-page 50
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MCP4021/2/3/4
9.0
9.1
DEVELOPMENT SUPPORT
Evaluation/Demonstration Boards
Currently there are three boards that are available that
can be used to evaluate the MCP4021/2/3/4 family of
devices.
1. The MCP402X Digital Potentiometer Evaluation
Board kit (MCP402XEV) contains a simple
demonstration board utilizing a PIC10F206, the
MCP4021 and a blank PCB, which can be
populated with any desired MCP4021/2/3/4
device in a SOT-23-5, SOT-23-6 or 150 mil
SOIC 8-pin package.
This board has two push buttons to control when
the PIC® microcontroller generates MCP402X
serial commands. The example firmware
demonstrates the following commands:
• Increment
• Decrement
• High-Voltage Increment and Enable
WiperLock Technology
• High-Voltage Decrement and Enable
WiperLock Technology
• High-Voltage Increment and Disable
WiperLock Technology
• High-Voltage Decrement and Disable
WiperLock Technology
The populated board (with the MCP4021) can
be used to evaluate the other MCP402X devices
by appropriately jumpering the PCB pads.
2. The SOT-23-5/6 Evaluation Board (VSUPEV2)
can be used to evaluate the characteristics of
the MCP4022, MCP4023 and MCP4024
devices.
3. The 8-pin SOIC/MSOP/TSSOP/DIP Evaluation
Board (SOIC8EV) can be used to evaluate the
characteristics of the MCP4021 device in either
the SOIC or MSOP package.
4. The MCP4XXX Digital Potentiometer Daughter
Board allows the system designer to quickly
evaluate the operation of Microchip Technol-
ogy's MCP42XXX and MCP402X Digital Poten-
tiometers. The board supports two MCP42XXX
devices and an MCP402X device, which can be
replaced with an MCP401X device.
The board also has a voltage doubler device
(TC1240A), which can be used to show the
WiperLock Technology feature of the MCP4021.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
2006-2017 Microchip Technology Inc.
DS20001945F-page 51
MCP4021/2/3/4
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
Example:
5-Lead SOT-23 (MCP4024)
DP25
XXNN
Part Number
Code
MCP4024T-202E/OT
MCP4024T-502E/OT
MCP4024T-103E/OT
MCP4024T-503E/OT
DPNN
DQNN
DRNN
DSNN
Note: Applies to 5-Lead SOT-23
Example:
6-Lead SOT-23 (MCP4022 / MCP4023)
XXNN
BA25
Code
MCP4022 MCP4023
Part Number
MCP402xT-202E/CH
MCP402xT-502E/CH
MCP402xT-103E/CH
MCP402xT-503E/CH
BANN
BBNN
BCNN
BDNN
BENN
BFNN
BGNN
BHNN
Note: Applies to 6-Lead SOT-23
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20001945F-page 52
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
Package Marking Information
8-Lead DFN (2x3) (MCP4021)
Example:
AAA
640
25
Part Number
Code
MCP4021T-202E/MC
MCP4021T-502E/MC
MCP4021T-103E/MC
MCP4021T-503E/MC
AAA
AAB
AAC
AAD
Note: Applies to 8-Lead DFN
8-Lead MSOP (MCP4021)
Example:
402122
640256
8-Lead SOIC (150 mil) (MCP4021)
Example:
402153E
e
3
SN^1640
256
NNN
Part Numbers
8L-MSOP 8L-SOIC
Code
MCP4021-202E/MS MCP4021-202E/SN
MCP4021-502E/MS MCP4021-502E/SN
MCP4021-103E/MS MCP4021-103E/SN
MCP4021-503E/MS MCP4021-503E/SN
22
52
13
53
2006-2017 Microchip Technology Inc.
DS20001945F-page 53
MCP4021/2/3/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A2
A1
A
0.20 C
SEATING PLANE
A
SEE SHEET 2
C
SIDE VIEW
Microchip Technology Drawing C04-028D [OT] Sheet 1 ofꢀꢁ
DS20001945F-page 54
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
6
0.95 BSC
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
-
-
-
-
1.45
1.30
0.15
2.80 BSC
1.60 BSC
2.90 BSC
0.30
-
0.60
Footprint
Foot Angle
Lead Thickness
Lead Width
L1
0.60 REF
I
0°
0.08
0.20
-
-
-
10°
0.26
0.51
c
b
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091D [OT] Sheet 2 ofꢀꢁ
2006-2017 Microchip Technology Inc.
DS20001945F-page 55
MCP4021/2/3/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
C
X
0.95 BSC
2.80
Contact Pad Spacing
Contact Pad Width (X5)
Contact Pad Length (X5)
Distance Between Pads
Distance Between Pads
Overall Width
0.60
1.10
Y
G
GX
Z
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091A [OT]
DS20001945F-page 56
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.15 C A-B
D
e1
A
D
E
2
E1
E
E1
2
2X
0.15 C D
2X
0.20 C A-B
e
B
6X b
0.20
C A-B D
TOP VIEW
A2
A
C
SEATING PLANE
6X
A1
c
0.10 C
SIDE VIEW
R1
R
L2
GAUGE PLANE
Ĭ
L
(L1)
END VIEW
Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2
2006-2017 Microchip Technology Inc.
DS20001945F-page 57
MCP4021/2/3/4
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Leads
Pitch
N
e
6
0.95 BSC
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
0.00
-
1.45
1.30
0.15
1.15
-
2.80 BSC
1.60 BSC
2.90 BSC
0.45
Overall Width
Molded Package Width
Overall Length
Foot Length
0.30
0.60
Footprint
Seating Plane to Gauge Plane
Foot Angle
Lead Thickness
Lead Width
L1
L1
φ
c
b
0.60 REF
0.25 BSC
-
0°
0.08
0.20
10°
0.26
0.51
-
-
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2
DS20001945F-page 58
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
GX
Y
Z
C
G
G
SILK SCREEN
X
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.95 BSC
2.80
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width (X3)
Contact Pad Length (X3)
Distance Between Pads
Distance Between Pads
Overall Width
X
Y
G
GX
Z
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2028B (CH)
2006-2017 Microchip Technology Inc.
DS20001945F-page 59
MCP4021/2/3/4
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DS20001945F-page 60
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2006-2017 Microchip Technology Inc.
DS20001945F-page 61
MCP4021/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001945F-page 62
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2006-2017 Microchip Technology Inc.
DS20001945F-page 63
MCP4021/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001945F-page 64
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
1
2
NOTE 1
e
NX b
0.25
C A–B D
B
NOTE 5
TOP VIEW
0.10 C
0.10 C
C
A2
A
SEATING
PLANE
8X
SIDE VIEW
A1
h
R0.13
R0.13
h
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
2006-2017 Microchip Technology Inc.
DS20001945F-page 65
MCP4021/2/3/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
8
1.27 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
A
-
-
-
-
1.75
-
0.25
A2
A1
E
1.25
0.10
§
6.00 BSC
Molded Package Width
Overall Length
E1
D
3.90 BSC
4.90 BSC
Chamfer (Optional)
Foot Length
h
L
0.25
0.40
-
-
0.50
1.27
Footprint
L1
1.04 REF
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0°
0.17
0.31
5°
-
-
-
-
-
8°
c
b
0.25
0.51
15°
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
DS20001945F-page 66
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
C
X1
Y1
1.27 BSC
5.40
Contact Pad Spacing
Contact Pad Width (X8)
Contact Pad Length (X8)
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev B
2006-2017 Microchip Technology Inc.
DS20001945F-page 67
MCP4021/2/3/4
NOTES:
DS20001945F-page 68
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
APPENDIX A: REVISION HISTORY
Revision F (December 2017)
The following is the list of modifications:
1. Updated the High-Voltage Input Entry Voltage
entry in the “AC/DC Characteristics” table.
2. Updated Table6-1“TypicalStepResistances”.
Revision E (December 2006)
The following is the list of modifications:
1. Added device designators in conditions column
to associate units (MHz) in Bandwidth –3 dB
parameter in the table “AC/DC Characteris-
tics” table.
2. Added device designations in conditions column
for R-INL and R-DNL specifications.
3. Added disclaimers to package outline drawings.
Revision D (October 2006)
The following is the list of modifications:
1. Changed the EEPROM write cycle time (TWC
)
from a maximum of 5 ms to a maximum of
10 ms (overvoltage and temperature) with a typ-
ical of 5 ms.
2. For the 10 k device, the rheostat differential
nonlinearity specification at 2.7V was changed
from ±0.5 LSb to ±1.0 LSb.
3. Figure 2-9 in Section 2.0 “Typical Perfor-
mance Curves” was updated with the correct
data.
4. Added Figure 2-48 for –3 db Bandwidth
information.
5. Updated available Development Tools.
6. Added disclaimer to package outline drawings.
Revision C (November 2005)
The following is the list of modifications:
1. Enhanced Descriptions.
2. Reordered Sections.
3. Added 8-lead MSOP and DFN packages.
Revision B (April 2005)
The following is the list of modifications:
1. Updated part numbers in Product Identifcation
Section (PIS).
2. Added Appendix A: Revision History.
Revision A (April 2005)
• Original release of this document.
2006-2017 Microchip Technology Inc.
DS20001945F-page 69
MCP4021/2/3/4
NOTES:
DS20001945F-page 70
2006-2017 Microchip Technology Inc.
MCP4021/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
XXX
X
/XX
a)
b)
c)
d)
e)
f)
g)
h)
i)
MCP4021-103E/MS: 10 k, 8-LD MSOP
Resistance Temperature Package
Version Range
MCP4021-103E/SN: 10 k, 8-LD SOIC
MCP4021T-103E/MC: T/R, 10 k, 8-LD DFN
MCP4021T-103E/MS: T/R, 10 k, 8-LD MSOP
MCP4021T-103E/SN: T/R, 10 k, 8-LD SOIC
MCP4021-202E/MS: 2.1 k, 8-LD MSOP
MCP4021-202E/SN: 2.1 k, 8-LD SOIC
MCP4021T-202E/MC: T/R, 2.1 k, 8-LD DFN
MCP4021T-202E/MS: T/R, 2.1 k, 8-LD MSOP
MCP4021T-202E/SN: T/R, 2.1 k, 8-LD SOIC
MCP4021-502E/MS: 5 k, 8-LD MSOP
MCP4021-502E/SN: 5 k, 8-LD SOIC
Device:
MCP4021:
MCP4021T:
Single Potentiometer with U/D Interface
Single Potentiometer with U/D Interface
(Tape and Reel) (SOIC, MSOP)
Single Rheostat with U/D interface
Single Rheostat with U/D interface
(Tape and Reel) (SOT-23-6)
Single Potentiometer to GND with U/D
Interface
Single Potentiometer to GND with U/D
Interface (Tape and Reel) (SOT-23-6)
Single Rheostat to GND with U/D
Interface
MCP4022:
MCP4022T:
j)
k)
l)
MCP4023:
MCP4023T:
MCP4024:
MCP4024T:
m) MCP4021T-502E/MC: T/R, 5 k, 8-LD DFN
n)
o)
p)
q)
r)
MCP4021T-502E/MS: T/R, 5 k, 8-LD MSOP
MCP4021T-502E/SN: T/R, 5 k, 8-LD SOIC
MCP4021-503E/MS: 50 k, 8-LD MSOP
MCP4021-503E/SN: 50 k, 8-LD SOIC
MCP4021T-503E/MC: T/R, 50 k, 8-LD DFN
MCP4021T-503E/MS: T/R, 50 k, 8-LD MSOP
MCP4021T-503E/SN: T/R, 50 k, 8-LD SOIC
Single Rheostat to GND with U/D
Interface (Tape and Reel)(SOT-23-5)
s)
t)
a)
b)
c)
d)
MCP4022T-202E/CH 2.1 k, 6-LD SOT-23
MCP4022T-502E/CH 5 k, 6-LD SOT-23
MCP4022T-103E/CH 10 k, 6-LD SOT-23
MCP4022T-503E/CH 50 k, 6-LD SOT-23
Resistance Version:
202 = 2.1 k
502 = 5 k
103 = 10 k
503 = 50 k
a)
b)
c)
d)
MCP4023T-202E/CH 2.1 k, 6-LD SOT-23
MCP4023T-502E/CH 5 k, 6-LD SOT-23
MCP4023T-103E/CH 10 k, 6-LD SOT-23
MCP4023T-503E/CH 50 k, 6-LD SOT-23
Temperature Range:
Package:
E
=
-40°C to +125°C
CH
MC
MS
SN
OT
=
=
=
=
=
Plastic Small Outline Transistor, 6-lead
Plastic Dual Flat No Lead (2x3x0.9 mm), 8-lead
Plastic MSOP, 8-lead
Plastic SOIC, (150 mil Body), 8-lead
Plastic Small Outline Transistor, 5-lead
a)
b)
c)
d)
MCP4024T-202E/OT 2.1 k, 5-LD SOT-23
MCP4024T-502E/OT 5 k, 5-LD SOT-23
MCP4024T-103E/OT 10 k, 5-LD SOT-23
MCP4024T-503E/OT 50 k, 5-LD SOT-23
2006-2017 Microchip Technology Inc.
DS20001945F-page 71
MCP4021/2/3/4
NOTES:
DS20001945F-page 72
2006-2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
CERTIFIEDꢀBYꢀDNVꢀ
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2436-9
== ISO/TSꢀ16949ꢀ==ꢀ
2006-2017 Microchip Technology Inc.
DS20001945F-page 73
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DS20001945F-page 74
2006-2017 Microchip Technology Inc.
10/25/17
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