MCP41HV51 [MICROCHIP]
7/8-Bit Single, 36V (±18V) Digital POT with SPI Serial Interface and Volatile Memory;
| 型号： | MCP41HV51 |
| 厂家： | 
MICROCHIP |
| 描述： | 7/8-Bit Single, 36V (±18V) Digital POT with SPI Serial Interface and Volatile Memory |
| 文件： | 总90页 (文件大小：2625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP41HVX1
7/8-Bit Single, +36V (±18V) Digital POT
with SPI Serial Interface and Volatile Memory
Package Types (Top View)
Features
• High-Voltage Analog Support:
MCP41HVX1 Single Potentiometer
TSSOP (ST)
- +36V Terminal Voltage Range (DGND = V-)
- ±18V Terminal Voltage Range
(DGND = V- + 18V)
V+
V
SCK
CS
SDI
SDO
WLAT
14
13
12
11
10
9
1
2
3
4
5
6
7
L
P0A
P0W
P0B
V-
DGND
NC
• Wide Operating Voltage:
- Analog: 10V to 36V (specified performance)
- Digital: 2.7V to 5.5V
(2)
8
SHDN
1.8V to 5.5V (DGND V- + 0.9V)
• Single Resistor Network
5x5 QFN (MQ)
• Potentiometer Configuration Options
• Resistor Network Resolution
- 7-bit: 127 Resistors (128 Taps)
- 8-bit: 255 Resistors (256 Taps)
• RAB Resistance Options:
17 16
18
19
20
15
14 P0W
P0A
V
1
2
3
4
5
L
SCK
CS
21 EP(1)
- 5 k
10 k
P0B
V-
13
12
- 50 k
100 k
SDI
• High Terminal/Wiper Current (IW) Support:
- 25 mA (for 5 k)
DGND
11
SDO
- 12.5 mA (for 10 k)
8
9 10
6
7
- 6.5 mA (for 50 k and 100 k)
• Zero-Scale to Full-Scale Wiper Operation
• Low Wiper Resistance: 75 (Typical)
• Low Tempco:
Note 1: Exposed Pad (EP)
2: NC = Not Internally Connected
- Absolute (Rheostat): 50 ppm Typical
(0°C to +70°C)
Description
- Ratiometric (Potentiometer): 15 ppm Typical
The MCP41HVX1 family of devices have dual power
rails (analog and digital). The analog power rail allows
high voltage on the resistor network terminal pins. The
analog voltage range is determined by the V+ and V–
voltages. The maximum analog voltage is +36V, while
the operating analog output minimum specifications
are specified from either 10V or 20V. As the analog
supply voltage becomes smaller, the analog switch
resistances increase, which effect certain performance
specifications. The system can be implemented as dual
rail (±18V) relative to the digital logic ground (DGND).
• SPI Serial Interface
(10 MHz, Modes 0,0and 1,1)
• Resistor Network Terminal Disconnect Via:
- Shutdown Pin (SHDN)
- Terminal Control (TCON) Register
• Write Latch (WLAT) Pin to control update of
Volatile Wiper Register (such as Zero Crossing)
• Power-On Reset / Brown-Out Reset for both:
- Digital Supply (VL/DGND); 1.5V Typical
- Analog Supply (V+ / V-); 3.5V Typical
The device also has a Write Latch (WLAT) function,
which will inhibit the volatile wiper register from being
updated (latched) with the received data, until the
WLAT pin is low. This allows the application to specify
a condition where the volatile wiper register is updated
(such as zero crossing).
• Serial Interface Inactive Current (3 µA Typical)
• 500 kHz Typical Bandwidth (-3 dB) Operation
(5.0 k Device)
• Extended Temperature Range (-40°C to +125°C)
• Package Types: TSSOP-14 and QFN-20 (5x5)
2013 Microchip Technology Inc.
DS20005207A-page 1
MCP41HVX1
Device Block Diagram
V+ V–
Power-up/
Brown-out
Control
VL
Power-up/
Brown-out
Control
DGND
(Digital)
(Analog)
CS
SCK
SDI
SPI Serial
Interface
Module and
Control
P0A
Resistor
SDO
Logic
Network 0
(Pot 0)
WLAT
SHDN
P0W
Wiper 0
and TCON
Register
Memory (2x8)
P0B
Wiper0 (V)
TCON
Device Features
Number
of:
Resistance (Typical)
RABOptions Wiper-
Specified Operating Range
Wiper
Configuration
Device
VL ( 2)
V+ ( 3)
(k)
RW ()
(
Potentiometer
5.0, 10.0,
50.0, 100.0
10V 4) to 36V
MCP41HV31
MCP41HV51
1
1
SPI 3Fh
SPI 7Fh
75
127 128 1.8V to 5.5V
255 256 1.8V to 5.5V
( 1)
(
Potentiometer
5.0, 10.0,
50.0, 100.0
10V 4) to 36V
75
( 1)
Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).
2: This is relative to the DGND signal. There is a separate requirement for the V+ / V- voltages. When
VL = 1.8V operation, DGND must be 0.9V above V-.
3: Relative to V-, the VL and DGND signals must be between V- and V+.
4: Analog operation will continue while the V+ voltage is above the device’s Analog Power-on Reset (POR) /
Brown-out Reset (BOR) voltage. Operational characteristics may exceed specified limits while the V+ volt-
age is below the specified minimum voltage.
DS20005207A-page 2
2013 Microchip Technology Inc.
MCP41HVX1
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on V- with respect to DGND ......................................................................................... DGND + 0.6V to -40.0V
Voltage on V+ with respect to DGND ........................................................................................... DGND - 0.3V to 40.0V
Voltage on V+ with respect to V- .................................................................................................. DGND - 0.3V to 40.0V
Voltage on VL with respect to V+ ............................................................................................................ -0.6V to -40.0V
Voltage on VL with respect to V- ............................................................................................................. -0.6V to +40.0V
Voltage on VL with respect to DGND ....................................................................................................... -0.6V to +7.0V
Voltage on CS, SCK, SDI, WLAT, and SHDN with respect to DGND ................................................ -0.6V to VL + 0.6V
Voltage on all other pins (PxA, PxW, and PxB) with respect to V- ......................................................-0.3V to V+ + 0.3V
Input clamp current, IIK (VI < 0, VI > VL, VI > VPP on HV pins) ............................................................................ ±20 mA
Output clamp current, IOK (VO < 0 or VO > VL) ................................................................................................... ±20 mA
Maximum current out of DGND pin...................................................................................................................... 100 mA
Maximum current into VL pin................................................................................................................................ 100 mA
Maximum current out of V- pin............................................................................................................................. 100 mA
Maximum current into V+ pin ................................................................................................................................100 mA
Maximum current into PXA, PXW, & PXB pins (Continuous)
RAB = 5 k ............................................................................................................................. ±25 mA
RAB = 10 k ........................................................................................................................ ±12.5 mA
RAB = 50 k .......................................................................................................................... ±6.5 mA
RAB = 100 k ........................................................................................................................ ±6.5 mA
Maximum current into PXA, PXW, & PXB pins (Pulsed)
FPULSE > 10 kHz ......................................................................................................... (Max IContinuous) / (Duty Cycle)
FPULSE 10 kHz ...................................................................................................... (Max IContinuous) / (Duty Cycle)
Maximum output current sunk by any Output pin .................................................................................................. 25 mA
Maximum output current sourced by any Output pin ............................................................................................ 25 mA
Package Power Dissipation (TA = + 50°C, TJ = +150°C)
TSSOP-14 ............................................................................................................................................. 1000 mW
SOIC-16 ................................................................................................................................................ 1250 mW
QFN-20 (5 x 5) ...................................................................................................................................... 2800 mW
QFN-20 (4x4) ......................................................................................................................................... 2300 mW
Soldering temperature of leads (10 seconds) ..................................................................................................... +300°C
ESD protection on all pins
Human Body Model (HBM) ...................................................................................................................... ±4 kV
Machine Model (MM) ±400V
Maximum Junction Temperature (TJ)..................................................................................................................... 150°C
Storage temperature ............................................................................................................................. -65°C to +150°C
Ambient temperature with power applied .............................................................................................. -40°C to +125°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2013 Microchip Technology Inc.
DS20005207A-page 3
MCP41HVX1
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
DC Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Digital Positive
Supply Voltage (VL)
VL
2.7
1.8
—
—
5.5
5.5
V
V
With respect to DGND (Note 4)
DGND = V- + 0.9V (referenced to V-)
(Note 1, Note 4)
—
VL ( 16)
—
—
0
V
V
With respect to V+
Analog Positive
Supply Voltage (V+)
V+
VDGND
V-
36.0
With respect to V- (Note 4)
Digital Ground
Voltage (DGND)
V-
—
—
—
—
—
—
V+ - VL
0
V
V
V
V
V
V
With respect to V- (Note 4, Note 5)
With respect to DGND and VL = 1.8V
Delta voltage between V+ and V- (Note 4)
Analog Negative
-36.0 + VL
Supply Voltage (V-)
Resistor Network
Supply Voltage
VRN
—
—
—
—
36V
1.8
VL Start Voltage to
ensure Wiper Reset
VDPOR
VAPOR
VLS
With respect to DGND, V+ > 6.0V
RAM retention voltage (VRAM) < VDBOR
V+ Voltage to ensure
Wiper Reset
6.0
With respect to V-, VL = 0V
RAM retention voltage (VRAM) < VBOR
Digital to Analog
Level Shifter
2.3
VL to V- voltage.
DGND = V-
Operational Voltage
Power Rail Voltages
during Power Up
(Note 1)
VLPOR
—
—
—
—
5.5
36
V
V
Digital Powers (VL / DGND) up 1st:
V+ and V- floating
or
as V+ / V- powers up
(V+ must be to DGND) (Note 18)
V+POR
Analog Powers (V+ / V-) up 1st:
VL and DGND floating
or
as VL / DGND powers up
(DGND must be between V- and V+)
(Note 18)
VL Rise Rate to
ensure Power-on
Reset
VLRR
(Note 6)
V/ms With respect to DGND
Note 1
Note 4
This specification by design.
V+ voltage is dependent on V- voltage. The maximum delta voltage between V+ and V- is 36V. The digital
logic DGND potential can be anywhere between V+ and V-, the VL potential must be DGND and V+.
Note 5
Minimum value determined by maximum V- to V+ potential equals 36V and minimum VL = 1.8V for opera-
tion. So 36V - 1.8V = 34.2V.
Note 6
POR/BOR is not rate dependent.
Note 16 For specified analog performance, V+ must be 20V or greater (unless otherwise noted).
Note 18 During the power up sequence, to ensure expected Analog POR operation, the two power systems (Analog
and Digital) should have a common reference to ensure that the driven DGND voltage is not at a higher
potential than the driven V+ voltage.
DS20005207A-page 4
2013 Microchip Technology Inc.
MCP41HVX1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Sym
TBORD
Min
Typ
Max
Units
Conditions
Delay after
—
10
20
µs
device exits the
reset state (VL >
VBOR
)
Supply Current
(Note 7)
IDDD
—
45
300
µA
Serial Interface Active,
Write all 0’s to Volatile Wiper 0 (address 0h)
VL = 5.5V, CS = VIL, FSCK = 5 MHz,
V- = DGND
—
—
—
—
7
5
µA
µA
Serial Interface Inactive,
VL = 5.5V, SCK = VIH, CS = VIH, Wiper = 0,
V- = DGND
IDDA
RAB
Current V+ to V-, PxA = PxB = PxW,
DGND = V- +(V+/2)
Resistance
(± 20%)(Note 8)
4.0
8.0
40.0
80.0
—
5
6.0
12.0
60.0
120.0
9.00
4.50
0.90
0.45
k
k
-502 devices, V+/V- = 10V to 36V
-103 devices, V+/V- = 10V to 36V
-503 devices, V+/V- = 10V to 36V
-104 devices, V+/V- = 10V to 36V
10
50
k
100
k
RAB Current
IAB
—
—
mA
mA
mA
mA
-502 devices 36V / RAB(MIN),
V- = -18V, V+ = +18V,
(Note 9)
—
-103 devices
-503 devices
-104 devices
—
—
—
—
Resolution
N
256
Taps 8-bit
Taps 7-bit
No Missing Codes
No Missing Codes
Note 1
128
Step Resistance
(see Appendix
B.4)
RS
—
—
RAB/ (255)
RAB/ (127)
—
—
8-bit
7-bit
Note 1
Note 1
Note 7
Note 8
Note 9
This specification by design.
Supply current (IDDD and IDDA) is independent of current through the resistor network.
Resistance (RAB) is defined as the resistance between Terminal A to Terminal B.
Guaranteed by the RAB specification and Ohms Law.
2013 Microchip Technology Inc.
DS20005207A-page 5
MCP41HVX1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
DC Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
RW
Wiper Resistance
(see Appendix B.5)
—
75
170
IW = 1 mA
V+ = +18V, V- = -18V,
code = 00h, PxA = floating,
PxB = V-.
—
145
200
I
W = 1 mA
V+ = +5.0V, V- = -5.0V,
code = 00h, PxA = floating,
PxB = V-. (Note 2)
RAB/T
VWB/T
Nominal Resistance
Tempco
(see Appendix B.23)
—
—
50
—
—
ppm/°C TA = -40°C to +85°C
ppm/°C TA = -40°C to +125°C
100
Ratiometeric Tempco
(see Appendix B.22)
—
V-
15
—
—
ppm/°C Code = Mid-scale (80h or 40h)
Resistor Terminal Input VA,VW,VB
Voltage Range
V+
V
Note 1, Note 11
(Terminals A, B and W)
Current through
Terminals
(A, B, and Wiper)
(Note 1)
IT, IW
—
—
—
—
—
—
—
—
—
—
—
5
25
12.5
6.5
6.5
36
mA
mA
mA
mA
mA
nA
-502 devices IBW(
-103 devices IBW(
-503 devices IBW(
-104 devices IBW(
IBW(W = ZS , or IAW(
) and IAW(
) and IAW(
) and IAW(
) and IAW(
W
W
W
W
ZS
ZS
ZS
ZS
W
W
W
W
FS
FS
FS
FS
)
)
)
)
≠
≠
≠
≠
≠
≠
≠
≠
W = FS
)
)
Leakage current into A,
W or B
ITL
—
A = W = B = V-
Note 1
Note 2
This specification by design.
This parameter is not tested, but specified by characterization.
Note 11 Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
DS20005207A-page 6
2013 Microchip Technology Inc.
MCP41HVX1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
DC Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
VAB = 20V to 36V
Full Scale Error
(Potentiometer)
(8-bit code = FFh,
7-bit code = 7Fh)
(Note 10, Note 17)
(VA = V+, VB = V- )
(see Appendix
B.10)
VWFSE
-8.5
-13.5
-4.5
-7.0
-4.5
-6.0
-2.25
-3.5
-0.9
-1.25
-0.95
-1.1
-0.5
-0.7
-0.75
-0.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
5 k
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
—
—
—
10 k
50 k
100 k
5 k
V
AB = 20V to 36V
VAB = 10V to 36V
VAB = 20V to 36V
—
—
—
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
VAB = 20V to 36V
—
—
—
—
—
—
—
—
Zero Scale Error
(Potentiometer)
(8-bit code = 00h,
7-bit code = 00h)
(Note 10, Note 17)
(VA = V+, VB = V- )
(see Appendix
B.11)
VWZSE
+8.5
+13.5
+4.5
+7.0
+4.0
+6.0
+2.0
+3.0
+0.8
+1.2
+0.5
+0.7
+0.5
+0.7
+0.25
+0.4
—
—
—
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
VAB = 20V to 36V
—
10 k
50 k
100 k
—
—
—
—
—
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
—
—
—
VAB = 20V to 36V
—
VAB = 10V to 36V
VAB = 20V to 36V
VAB = 10V to 36V
—
—
Note 10 Measured at VW with VA = V+ and VB = V-.
Note 17 Analog switch leakage effects this specification. Higher temperatures increase the switch leakage.
2013 Microchip Technology Inc.
DS20005207A-page 7
MCP41HVX1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
DC Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
Potentiometer
Integral
Non-linearity
(Note 10,
Note 17)
(see Appendix
B.12)
P-INL
-1
-0.5
-1
±0.5
±0.25
±0.5
+1
+0.5
+1
LSb
LSb
LSb
LSb
LSb
LSb
5 k
8-bit
7-bit
8-bit
7-bit
8-bit
10 k
50 k
-0.5
-1.1
-1
±0.25
±0.5
+0.5
+1.1
+1
±0.5
VAB = 20V to 36V,
(Note 2)
-1
±0.5
+1
LSb
VAB = 10V to 36V,
–40°C TA +85°C
(Note 2)
VAB = 10V to 36V
VAB = 10V to 36V
-0.6
-1.85
-1.2
±0.25
±0.5
±0.5
+0.6
+1.85
+1.2
LSb
LSb
LSb
7-bit
8-bit
100 k
VAB = 20V to 36V,
(Note 2)
-1
±0.5
+1
LSb
VAB = 10V to 36V,
–40°C TA +85°C
(Note 2)
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
VAB = 10V to 36V
-1
±0.5
±0.25
±0.125
±0.125
±0.1
+1
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
Potentiometer
Differential
Non-linearity
(Note 10,
Note 17)
(see Appendix
B.13)
P-DNL
-0.5
+0.5
5 k
-0.25
-0.25
-0.125
-0.25
-0.125
-0.25
-0.125
+0.25
+0.25
+0.125
+0.25
+0.125
+0.25
+0.125
10 k
50 k
100 k
±0.125
±0.1
±0.125
-0.15
Note 2
Note 10 Measured at VW with VA = V+ and VB = V-.
Note 17 Analog switch leakage effects this specification. Higher temperatures increase the switch leakage.
This parameter is not tested, but specified by characterization.
DS20005207A-page 8
2013 Microchip Technology Inc.
MCP41HVX1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
DC Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Bandwidth -3 dB
(load = 30 pF)
BW
—
—
—
—
—
—
—
—
—
480
480
240
240
48
—
—
—
—
—
—
—
—
—
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
µs
5 k
8-bit Code = 7Fh
7-bit Code = 3Fh
8-bit Code = 7Fh
7-bit Code = 3Fh
8-bit Code = 7Fh
7-bit Code = 3Fh
10 k
50 k
48
24
100 k 8-bit Code = 7Fh
24
7-bit Code = 3Fh
VW Settling Time
(VA = 10V, VB = 0V,
±1LSb error band,
CL = 50 pF )
tS
1
5 k
Code = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
—
—
—
1
2.5
5
—
—
—
µs
µs
µs
10 k
50 k
Code = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
(see Appendix B.17)
Code = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
100 k Code = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
2013 Microchip Technology Inc.
DS20005207A-page 9
MCP41HVX1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
DC Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Rheostat Integral
Non-linearity
(Note 12, Note 13,
Note 14, Note 17)
(see Appendix
B.5)
R-INL
-1.75
-2.5
-4.0
-1.0
-1.5
-2.0
-1.0
-1.75
-2.0
-0.5
-0.8
-1.0
-1.0
-1.0
-1.2
-0.5
-0.5
-0.6
-1.0
-1.0
-1.2
-0.5
-0.5
-0.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+1.75
+2.5
+4.0
+1.0
+1.5
+2.0
+1.0
+1.75
+2.0
+0.5
+0.8
+1.0
+1.0
+1.0
+1.2
+0.5
+0.5
+0.6
+1.0
+1.0
+1.2
+0.5
+0.5
+0.6
LSb 5 k
LSb
8-bit
I
W = 6.0 mA, (V+ - V-) = 36V (Note 2)
IW = 3.3 mA, (V+ - V-) = 20V (Note 2)
LSb
IW = 1.7 mA, (V+ - V-) = 10V
LSb
7-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2)
IW = 3.3 mA, (V+ - V-) = 20V (Note 2)
IW = 1.7 mA, (V+ - V-) = 10V
LSb
LSb
LSb 10 k 8-bit
IW = 3.0 mA, (V+ - V-) = 36V (Note 2)
LSb
LSb
IW = 1.7 mA, (V+ - V-) = 20V (Note 2)
IW = 830 µA, (V+ - V-) = 10V
LSb
LSb
LSb
7-bit IW = 3.0 mA, (V+ - V-) = 36V (Note 2)
IW = 1.7 mA, (V+ - V-) = 20V (Note 2)
IW = 830 µA, (V+ - V-) = 10V
LSb 50 k 8-bit IW = 600 µA, (V+ - V-) = 36V (Note 2)
LSb
LSb
LSb
LSb
LSb
IW = 330 µA, (V+ - V-) = 20V (Note 2)
IW = 170 µA, (V+ - V-) = 10V
7-bit IW = 600 µA, (V+ - V-) = 36V (Note 2)
IW = 330 µA, (V+ - V-) = 20V (Note 2)
IW = 170 µA, (V+ - V-) = 10V
LSb 100 k 8-bit IW = 300 µA, (V+ - V-) = 36V (Note 2)
LSb
LSb
LSb
LSb
LSb
IW = 170 µA, (V+ - V-) = 20V(Note 2)
IW = 83 µA, (V+ - V-) = 10V
7-bit IW = 300 µA, (V+ - V-) = 36V (Note 2)
IW = 170 µA, (V+ - V-) = 20V (Note 2)
IW = 83 µA, (V+ - V-) = 10V
Note 2
This parameter is not tested, but specified by characterization.
Note 12 Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature.
Note 13 Externally connected to a Rheostat configuration (RBW), and then tested.
Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition, the delta voltage between V+
and V- (voltages are 36V, 20V, and 10V).
Note 17 Analog switch leakage effects this specification. Higher temperatures increase the switch leakage.
DS20005207A-page 10
2013 Microchip Technology Inc.
MCP41HVX1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
DC Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max Units
Conditions
Rheostat
Differential
R-DNL
-0.5
-0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+0.5
+0.5
LSb 5 k
8-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2)
IW = 3.3 mA, (V+ - V-) = 20V (Note 2)
IW = 1.7 mA, (V+ - V-) = 10V
LSb
LSb
LSb
LSb
LSb
Non-linearity
(Note 12,Note 13,
Note 14, Note 17)
(see Appendix
B.5)
-0.6
+0.6
-0.25
-0.25
-0.3
+0.25
+0.25
+0.3
7-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2)
IW = 3.3 mA, (V+ - V-) = 20V (Note 2)
IW = 1.7 mA, (V+ - V-) = 10V
-0.5
+0.5
LSb 10 k 8-bit
IW = 3.0 mA, (V+ - V-) = 36V (Note 2)
-0.5
+0.5
LSb
LSb
IW = 1.7 mA, (V+ - V-) = 20V (Note 2)
-0.5
+0.5
IW = 830 µA, (V+ - V-) = 10V
-0.25
-0.25
-0.25
-0.5
+0.25
+0.25
+0.25
+0.5
LSb
LSb
LSb
7-bit IW = 3.0 mA, (V+ - V-) = 36V (Note 2)
IW = 1.7 mA, (V+ - V-) = 20V (Note 2)
IW = 830 µA, (V+ - V-) = 10V
LSb 50 k 8-bit IW = 600 µA, (V+ - V-) = 36V (Note 2)
-0.5
+0.5
LSb
LSb
LSb
LSb
LSb
IW = 330 µA, (V+ - V-) = 20V (Note 2)
IW = 170 µA, (V+ - V-) = 10V
-0.5
+0.5
-0.25
-0.25
-0.25
-0.5
+0.25
+0.25
+0.25
+0.5
7-bit IW = 600 µA, (V+ - V-) = 36V (Note 2)
IW = 330 µA, (V+ - V-) = 20V (Note 2)
IW = 170 µA, (V+ - V-) = 10V
LSb 100 k 8-bit IW = 300 µA, (V+ - V-) = 36V (Note 2)
-0.5
+0.5
LSb
LSb
LSb
LSb
LSb
IW = 170 µA, (V+ - V-) = 20V (Note 2)
IW = 83 µA, (V+ - V-) = 10V
-0.5
+0.5
-0.25
-0.25
-0.25
+0.25
+0.25
+0.25
7-bit IW = 300 µA, (V+ - V-) = 36V (Note 2)
IW = 170 µA, (V+ - V-) = 20V (Note 2)
IW = 83 µA, (V+ - V-) = 10V
Note 2 This parameter is not tested, but specified by characterization.
Note 12 Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature.
Note 13 Externally connected to a Rheostat configuration (RBW), and then tested.
Note 14 Wiper current (IW) condition determined by RAB(max) and Voltage Condition, the delta voltage between V+
and V- (voltages are 36V, 20V, and 10V).
Note 17 Analog switch leakage effects this specification. Higher temperatures increase the switch leakage.
2013 Microchip Technology Inc.
DS20005207A-page 11
MCP41HVX1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
DC Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Capacitance (PA)
CA
—
75
—
pF
Measured to V-, f =1 MHz,
Wiper code = Mid-Scale
Capacitance (Pw)
Capacitance (PB)
CW
CB
—
—
—
—
120
75
5
—
—
—
—
pF
pF
nA
pF
Measured to V-, f =1 MHz,
Wiper code = Mid-Scale
Measured to V-, f =1 MHz,
Wiper code = Mid-Scale
Common-Mode
Leakage
ICM
VA = VB = VW
Digital Interface Pin
Capacitance
CIN,
COUT
10
fC = 400 kHz
Digital Inputs/Outputs (CS, SDI, SDO, SCK, SHDN, WLAT)
Schmitt Trigger High-
Input Threshold
VIH
0.45 VL
0.5 VL
—
—
—
VL + 0.3V
VL + 0.3V
0.2 VL
V
V
V
2.7V VL 5.5V
1.8V VL 2.7V
Schmitt Trigger Low-
Input Threshold
VIL
DGND - 0.5V
Hysteresis of Schmitt VHYS
Trigger Inputs
—
0.1 VL
—
V
Output Low
Voltage (SDO)
VOL
VOH
IIL
DGND
DGND
0.8 VL
0.8 VL
-1
—
—
—
—
0.2 VL
0.2 VL
VL
V
V
VL = 5.5V, IOL = 5 mA
VL = 1.8V, IOL = 800 uA
VL = 5.5V, IOH = -2.5 mA
VL = 1.8V, IOL = -800 uA
VIN = VL and VIN = DGND
Output High
Voltage (SDO)
V
VL
V
Input Leakage
Current
1
uA
DS20005207A-page 12
2013 Microchip Technology Inc.
MCP41HVX1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
DC Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
RAM (Wiper, TCON) Value
Wiper Value Range
N
0h
0h
—
FFh
7Fh
hex 8-bit
hex 7-bit
hex 8-bit
hex 7-bit
hex
—
Wiper POR/BOR Value NPOR/BOR
7Fh
3Fh
—
TCON Value Range
N
0h
FFh
TCON POR/BOR Value
Power Requirements
NTCON
FF
hex All Terminals connected
Power Supply
Sensitivity
(see Appendix B.20)
PSS
—
—
0.0015 0.0035 %/% 8-bit
0.0015 0.0035 %/% 7-bit
VL = 2.7V to 5.5V,
V+ = 18V, V- = -18V,
Code = 7Fh
VL = 2.7V to 5.5V,
V+ = 18V, V- = -18V,
Code = 3Fh
Power Dissipation
PDISS
—
—
—
—
260
130
26
—
—
—
—
mW 5 k
VL = 5.5V, V+ = 18V, V- = -18V
(Note 15)
mW 10 k
mW 50 k
mW 100 k
13
Note 15 PDISS = I * V, or ( (IDDD * 5.5V) + (IDDA * 36V) + (IAB * 36V) ).
2013 Microchip Technology Inc.
DS20005207A-page 13
MCP41HVX1
AC / DC Notes:
1. This specification by design.
2. This parameter is not tested, but specified by characterization.
3. See Absolute Maximum Ratings.
4. V+ voltage is dependent on V- voltage. The maximum delta voltage between V+ and V- is 36V. The digital logic
DGND potential can be anywhere between V+ and V-, the VL potential must be DGND and V+.
5. Minimum value determined by maximum V- to V+ potential equals 36V and minimum VL = 1.8V for operation. So
36V - 1.8V = 34.2V.
6. POR/BOR is not rate dependent.
7. Supply current (IDDD and IDDA) is independent of current through the resistor network.
8. Resistance (RAB) is defined as the resistance between Terminal A to Terminal B.
9. Guaranteed by the RAB specification and Ohms Law.
10. Measured at VW with VA = V+ and VB = V-.
11. Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
12. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature.
13. Externally connected to a Rheostat configuration (RBW), and then tested.
14. Wiper current (IW) condition determined by RAB(max) and Voltage Condition, the delta voltage between V+ and V-
(voltages are 36V, 20V, and 10V).
15. PDISS = I * V, or ( (IDDD * 5.5V) + (IDDA * 36V) + (IAB * 36V) ).
16. For specified analog performance, V+ must be 20V or greater (unless otherwise noted).
17. Analog switch leakage effects this specification. Higher temperatures increase the switch leakage.
18. During the power up sequence, to ensure expected Analog POR operation, the two power systems (Analog and
Digital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential than
the driven V+ voltage.
DS20005207A-page 14
2013 Microchip Technology Inc.
MCP41HVX1
1.1
SPI Mode Timing Waveforms and Requirements
± 1 LSb
New Value
Old Value
W
FIGURE 1-1:
Settling Time Waveforms.
TABLE 1-1:
WIPER SETTLING TIMING
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
V+ = 10V to 36V (referenced to V-);
Timing Characteristics
V+ = +5V to +18V & V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V),
VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VL = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
V
W Settling Time
tS
—
1
—
µs
5 k
Code = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
(VA = 10V, VB = 0V,
±1LSb error band,
CL = 50 pF )
—
—
—
1
2.5
5
—
—
—
µs
µs
µs
10 k Code = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
50 k Code = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
100 k Code = 00h -> FFh (7Fh);
FFh (7Fh) -> 00h
CS
84
“1”
“1”
85
70b
WLAT
“0”
“0”
70a
71
83b
SCK
83a
72
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
BIT6 - - - -1
77
MSb IN
74
LSb IN
73
FIGURE 1-2:
SPI Timing Waveform (Mode = 11).
2013 Microchip Technology Inc.
DS20005207A-page 15
MCP41HVX1
TABLE 1-2:
#
SPI REQUIREMENTS (MODE = 11)
Characteristic
Symbol
Min
Max Units
Conditions
SCK Input Frequency
FSCK
—
—
25
20
10
1
MHz VL = 2.7V to 5.5V
MHz VL = 1.8V to 2.7V
70a CS Active (VIL) to SCK input
TcsA2scH
TwlA2scH
—
—
ns
ns
70b WLAT Active (VIL) to eighth (or sixteenth) SCK
of the Serial Command to ensure previous data is
latched (setup time)
71 SCK input high time
TscH
TscL
35
120
35
—
—
—
—
—
—
50
55
90
—
—
ns VL = 2.7V to 5.5V
ns VL = 1.8V to 2.7V
72 SCK input low time
ns VL = 2.7V to 5.5V
120
10
ns VL = 1.8V to 2.7V
73 Setup time of SDI input to SCK edge
74 Hold time of SDI input from SCK edge
TDIV2scH
TscH2DIL
ns
20
ns
77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ
—
ns Note 1
80 SDO data output valid after SCK edge
TscL2DOV
—
ns VL = 2.7V to 5.5V
ns VL = 1.8V to 2.7V
83a CS Inactive (VIH) after SCK edge
TscH2csI
100
50
ns
ns
83b WLAT Inactive (VIH) after eighth (or sixteenth)
TscH2wlatI
SCK edge (hold time)
84 Hold time of CS (or WLAT) Inactive (VIH) to
CS (or WLAT) Active (VIL)
TcsA2csI
20
25
—
—
ns
ns
85 WLAT input low time
TWLATL
Note 1: This specification by design.
82
CS
84
“1”
“1”
WLAT
“0”
“0”
70b
83a
83b
SCK
70a
80
71
72
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
73
MSb IN
74
LSb IN
FIGURE 1-3:
SPI Timing Waveform (Mode = 00).
DS20005207A-page 16
2013 Microchip Technology Inc.
MCP41HVX1
TABLE 1-3:
#
SPI REQUIREMENTS (MODE = 00)
Characteristic
Symbol
Min
Max Units
Conditions
SCK Input Frequency
FSCK
—
—
25
20
10
1
MHz VL = 2.7V to 5.5V
MHz VL = 1.8V to 2.7V
70a CS Active (VIL) to SCK input
TcsA2scH
—
—
ns
ns
70b WLAT Active (VIL) to eighth (or sixteenth) SCK TwlA2scH
of the Serial Command to ensure previous data
is latched (setup time)
71 SCK input high time
TscH
35
120
35
—
—
—
—
—
—
50
55
90
70
ns VL = 2.7V to 5.5V
ns VL = 1.8V to 2.7V
ns VL = 2.7V to 5.5V
ns VL = 1.8V to 2.7V
ns
72 SCK input low time
TscL
120
10
73 Setup time of SDI input to SCK edge
74 Hold time of SDI input from SCK edge
TDIV2scH
TscH2DIL
20
ns
77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ
—
ns Note 1
80 SDO data output valid after SCK edge
TscL2DOV
—
ns VL = 2.7V to 5.5V
ns VL = 1.8V to 2.7V
ns
82 SDO data output valid after
CS Active (VIL)
TssL2doV
—
83a CS Inactive (VIH) after SCK edge
83b WLAT Inactive (VIH) after SCK edge
TscL2csI
TscL2wlatI
TcsA2csI
100
50
—
—
—
ns
ns
ns
84 Hold time of CS (or WLAT) Inactive (VIH) to
CS (or WLAT) Active (VIL)
20
85 WLAT input low time
TWLAT
L
25
—
ns
Note 1: This specification by design.
2013 Microchip Technology Inc.
DS20005207A-page 17
MCP41HVX1
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
Thermal Package Resistances
Thermal Resistance, 14L-TSSOP (ST)
Thermal Resistance, 20L-QFN (MQ)
JA
JA
—
—
100
—
—
°C/W
°C/W
36.1
DS20005207A-page 18
2013 Microchip Technology Inc.
MCP41HVX1
2.0
TYPICAL PERFORMANCE CURVES
Note:
The device Performance Curves are available in a separate document. This is done to keep the file size of
this PDF document less than the 10MB file attachment limit of many mail servers.
The MCP41HVX1 Performance Curves document is literature number DS20005209, and can be found on
the Microchip website. Look at the MCP41HVX1 Product Page under Documentation and Software, in the
Data Sheets category.
2013 Microchip Technology Inc.
DS20005207A-page 19
MCP41HVX1
NOTES:
DS20005207A-page 20
2013 Microchip Technology Inc.
MCP41HVX1
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP41HVX1
Pin
TSSOP
14L
QFN
20L
Function
Buffer
Type
Symbol
Type
1
2
3
4
5
6
1
2
3
4
5
6
VL
SCK
CS
P
I
—
ST
ST
ST
—
Positive Digital Power Supply Input
SPI Serial Clock pin
Chip Select
I
SDI
I
SPI Serial Data In pin
SPI Serial Data Out
SDO
WLAT
O
I
ST
Wiper Latch Enable
0 = Received SPI Shift Register Buffer (SPIBUF) value is
transferred to Wiper register.
1 = Received SPI data value is held in SPI Shift Register
Buffer (SPIBUF).
7
8
7
SHDN
DGND
NC
I
ST
—
—
Shutdown
Ground
11
P
9
8, 9, 10, 17,
18, 19, 20
—
Pin not internally connected to die. To reduce noise
coupling, connect pin either to DGND or VL.
10
11
12
12
13
14
V-
P
—
A
Analog Negative Potential Supply
Potentiometer 0 Terminal B
P0B
P0W
I/O
I/O
A
Potentiometer 0 Wiper
Terminal
13
14
—
15
16
21
P0A
V+
I/O
P
A
Potentiometer 0 Terminal A
—
—
Analog Positive Potential Supply
EP
P
Exposed Pad, connect to V- signal or Not Connected
(floating). (Note 1)
Legend:
A = Analog
I = Input
ST = Schmitt Trigger
O = Output
I/O = Input/Output
P = Power
Note 1: The QFN package has a contact on the bottom of the package. This contact is conductively connected to
the die substrate, and therefore should be unconnected or connected to the same ground as the device’s
V- pin.
2013 Microchip Technology Inc.
DS20005207A-page 21
MCP41HVX1
3.1
Positive Power Supply Input (V )
3.11 Potentiometer Terminal B
L
The VL pin is the device’s positive power supply input.
The input power supply is relative to DGND and can
range from 1.8V to 5.5V. A de-coupling capacitor on VL
(to DGND) is recommended to achieve maximum
performance.
The terminal B pin is connected to the internal
potentiometer’s terminal B.
The potentiometer’s terminal B is the fixed connection
to the zero scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x00 for both 7-bit and 8-bit devices.
While the device’s VL < Vmin (2.7V), the electrical
performance of the device may not meet the data sheet
specifications.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between V+ and V-.
3.2
Serial Clock (SCK)
The SCK pin is the serial interface's Serial Clock pin.
This pin is connected to the host controllers SCK pin.
The MCP41HVX1 is an SPI slave device, so its SCK
pin is an input only pin.
3.12 Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal
potentiometer’s terminal W (the Wiper). The wiper
terminal is the adjustable terminal of the digital
potentiometer. The terminal W pin does not have a
polarity relative to terminal’s A or B pins. The terminal
W pin can support both positive and negative current.
The voltage on terminal W must be between V+ and
V-.
3.3
Chip Select (CS)
The CS pin is the serial interface’s chip select input.
Forcing the CS pin to VIL enables the serial commands.
3.4
Serial Data In (SDI)
If the V+ voltage powers up before the VL voltage, the
Wiper is forced to midscale once the Analog POR
voltage is crossed.
The SDI pin is the serial interfaces Serial Data In pin.
This pin is connected to the host controller’s SDO pin.
If the V+ voltage powers up after the VL voltage is
greater than the Digital POR voltage, the Wiper is
forced to the value in the Wiper Register once the
Analog POR voltage is crossed.
3.5
Serial Data Out (SDO)
The SDO pin is the serial interface’s Serial Data Out
pin. This pin is connected to the host controller’s SDI
pin.
3.13 Potentiometer Terminal A
This pin allows the host controller to read the digital
potentiometer registers (Wiper and TCON), or monitor
the state of the command error bit.
The terminal A pin is connected to the internal
potentiometer’s terminal A.
The potentiometer’s terminal A is the fixed connection
to the full scale wiper value of the digital potentiometer.
This corresponds to a wiper value of 0xFF for 8-bit
devices or 0x7F for 7-bit devices.
3.6
Wiper Latch (WLAT)
The WLAT pin is used to hold off the transfer of the
received wiper value (in the shift register) to the wiper
register. This allows this transfer to be synchronized to
an external event (such as zero crossing).
The terminal A pin does not have a polarity relative to
the terminal W or B pins. The terminal A pin can
support both positive and negative current. The voltage
on terminal A must be between V+ and V-.
3.7
Shutdown (SHDN)
The SHDN pin is used to force the resistor network
terminals into the hardware shutdown state.
3.14 Analog Positive Voltage (V+)
Analog circuitry positive supply voltage. Must have a
higher potential then the V- pin.
3.8
Digital Ground (DGND)
The DGND pin is the device’s Digital ground reference.
3.15 Exposed Pad (EP)
3.9
Not Connected (NC)
This pad is only on the bottom of the QFN packages.
This pad is conductively connect to the device
substrate. The EP pin must be connected to the V-
signal or left floating. This pad could be connected to a
PCB heat sink to assist as a heat sink for the device.
This pin is not internally connected to the die. To reduce
noise coupling, these pins should be connected to
either VL or DGND.
3.10 Analog Negative Voltage (V-)
Analog circuitry negative supply voltage. Must not
have a higher potential then the DGND pin.
DS20005207A-page 22
2013 Microchip Technology Inc.
MCP41HVX1
4.1
Operating Voltage Range
4.0
FUNCTIONAL OVERVIEW
The MCP41HVX1 devices have four voltage signals.
These are:
This data sheet covers a family of two volatile Digital
Potentiometer devices that will be referred to as
MCP41HVX1.
• V+
• VL
• DGND
• V-
- Analog Power
- Digital Power
- Digital Ground
- Analog Ground
As the Device Block Diagram shows, there are six
main functional blocks. These are:
• Operating Voltage Range
• POR/BOR Operation
• Memory Map
Figure 4-1 shows the two possible power-up
sequences; analog power rails power-up first, or digital
power rails power-up first. The device has been
designed so that either power rail may power-up first.
The device has a POR circuit for both Digital power
circuitry and Analog power circuitry.
• Control Module
• Resistor Network
• Serial Interface (SPI)
The POR/BOR operation and the Memory Map are
discussed in this section and the Resistor Network and
SPI operation are described in their own sections. The
Device Commands are discussed in Section 7.0.
If the V+ voltage powers-up before the VL voltage, the
Wiper is forced to midscale once the Analog POR
voltage is crossed.
If the V+ voltage powers-up after the VL voltage is
greater than the Digital POR voltage, the Wiper is
forced to the value in the Wiper Register, once the
Analog POR voltage is crossed.
Figure 4-2 shows the three cases of the digital power
signals (VL / DGND) with respect to the analog power
signals (V+ / V-). The device implement level shifts
between the digital and analog power systems, which
allows the digital interface voltage to be anywhere in
the V+ / V- voltage window.
Analog Voltage Powers Up First
Digital Voltage Powers Up First
Referenced to V-
V+
Referenced to V-
V+
VL
VL
DGND
V-
DGND
V-
Referenced to DGND
V+
Referenced to DGND
V+
VL
VL
DGND
V-
DGND
V-
FIGURE 4-1:
Power-On Sequences.
2013 Microchip Technology Inc.
DS20005207A-page 23
MCP41HVX1
V+
V+ and VL
DGND
V+
Case 3
Case 1
Case 2
Anywhere
between
V+ and V-
(VL DGND)
VL
High-
Voltage
Range
High-
Voltage
Range
High-
Voltage
Range
DGND
VL
V-
V- and DGND
V-
FIGURE 4-2:
Voltage Ranges.
DS20005207A-page 24
2013 Microchip Technology Inc.
MCP41HVX1
4.2.1.1
Digital Circuitry
4.2
POR/BOR Operation
The Digital Power-on Reset (DPOR) is the case where
the device’s VL signal has power applied (referenced
from DGND) and the voltage rises above the trip point.
The Brown-out Reset (BOR) occurs when a device had
power applied to it, and the voltage drops below the trip
point.
The resister network’s devices are powered by the
analog power signals (V+ / V-), but the digital logic
(including the wiper registers) is powered by the digital
power signals (VL / DGND). So, both the digital circuitry
and analog circuitry have independent POR/BOR
circuits.
The device’s RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR). The
maximum VPOR/VBOR voltage is less then 1.8V.
The wiper position will be forced to the default state
when the V+ voltage (relative to V-) is above the analog
POR/BOR trip point. The wiper register will be in the
default state when the VL voltage (relative to DGND) is
above the digital POR/BOR trip point.
When the device powers up, the device VL will cross
the VPOR/VBOR voltage. Once the VL voltage crosses
the VPOR/VBOR voltage, the following happens:
The digital-signal-to-analog-signal voltage level shifters
require a minimum voltage between the VL and V-
signals. This voltage requirement is below the
operating supply voltage specifications. The wiper
output may fluctuate while the VL voltage is less than
the level shifter operating voltage, since the analog
values may not reflect the digital value. Output issues
may be reduced by powering-up the digital supply
voltages to their operating voltage, before powering the
analog supply voltage.
• Volatile wiper registers are loaded with the POR/
BOR value
• The TCON registers are loaded with the default
values
• The device is capable of digital operation
Table 4-2 shows the default POR/BOR Wiper Register
Setting Selection.
When VPOR/VBOR < VDD < 2.7V, the electrical
performance may not meet the data sheet
specifications. In this region, the device is capable of
incrementing, decrementing, reading and writing to its
volatile memory if the proper serial command is
executed.
4.2.1
POWER-ON RESET
Each power system has its own independent Power-
on-Reset circuitry. This is done so that regardless of the
power-up sequencing of the analog and digital power
rails, the wiper output will be forced to a default value
after minimum conditions are meet for either power
supply.
TABLE 4-2:
DEFAULT POR/BOR WIPER
REGISTER SETTING
(DIGITAL)
Table 4-1 shows the interaction between the analog
and digital PORs for the V+ and VL voltages on the
wiper pin state.
Default
POR Wiper
Register Resolution Code
Setting
Typical
RAB
Value
Device
Wiper
TABLE 4-1:
WIPER PIN STATE BASED
ON POR CONDITIONS
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
7Fh
3Fh
7Fh
3Fh
7Fh
3Fh
7Fh
3Fh
5.0 k -502
10.0 k -103
50.0 k -503
100.0 k -104
Mid-scale
Mid-scale
Mid-scale
Mid-scale
V+ Voltage
Comments
VL Voltage
V+ <
V+
VAPOR
VAPOR
VL < VDPOR Unknown Mid-Scale
Unknown Wiper
Wiper Register
VL VDPOR
Register can be updated
Value ( 1)
Note 1: Register setting independent of Analog
Note 1: Default POR state of the Wiper Register
power voltage.
value is the Mid-Scale value.
2013 Microchip Technology Inc.
DS20005207A-page 25
MCP41HVX1
4.2.1.2
Analog Circuitry
TABLE 4-3:
DEFAULT POR/BOR WIPER
SETTING (ANALOG)
The Analog Power-on Reset (APOR) is the case where
the device’s V+ pin voltage has power applied (refer-
enced from V-) and the V+ pin voltage rises above the
trip point.
Default
Device
Typical
RAB Value
POR Wiper
Resolution
Setting
Once the VL pin voltage exceeds the digital POR trip
point voltage, the Wiper Register will control the wiper
setting.
8-bit
5.0 k
10.0 k
50.0 k
-502
Mid-scale
Mid-scale
Mid-scale
Mid-scale
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
Table 4-3 shows the default POR/BOR Wiper Setting
for when the VL pin is not powered (< digital POR trip
point).
-103
-503
100.0 k -104
Note 1: Wiper setting is dependent on the Wiper
Register value if the VL voltage is greater
than the digital POR voltage.
Referenced to DGND
V+
VL
VPOR / VBOR
DGND
V-
Digital logic has been
reset (POR). This
includes the wiper register.
condition,
Digital logic has been
reset (POR). This
includes the wiper register.
Brown-out
Digital logic has been
reset (POR). This
includes the wiper register.
Wiper value
unknown
Analog Power
is recovering (still low) and VL
rail/pin no longer sources current
to V+
Brown-out condition
Wiper value unknown
Analog Power
is Low
Note: When VL is above V+ (floating), the VL pin ESD clamping diode will cause the V+ level to be pulled up.
FIGURE 4-3:
DGND, VL, V+, and V- Signal Waveform Examples.
DS20005207A-page 26
2013 Microchip Technology Inc.
MCP41HVX1
Whenever VL transitions from VL < VDBOR to VL
>
4.2.2
BROWN-OUT RESET
VDBOR, (a POR event) the Wiper’s POR/BOR value is
latched into the Wiper Register and the volatile TCON
register is forced to the POR/BOR state.
Each power system has its own independent Brown-
Out-Reset circuitry. This is done so that regardless of
the power-down sequencing of the analog and digital
power rails, the wiper output will be forced to a default
value after the low voltage conditions are meet for
either power supply.
When 1.8V VL, the device is capable of digital
operation.
Table 4-5 shows the digital potentiometer’s level of
functionality across the entire VL range, while Figure 4-
4 illustrates the Power-up and Brown-out functionality.
Table 4-4 shows the interaction between the analog
and digital BORs for the V+ and VL voltages on the
wiper pin state.
4.2.2.2
Analog Circuitry
TABLE 4-4:
WIPER PIN STATE BASED
ON BOR CONDITIONS
The Analog Brown-Out-Reset (ABOR) is the case
where the device’s V+ pin has power applied (refer-
enced from V-) and the V+ pin voltage drops below the
trip point. In this case, the resistor network terminals
pins can become an unknown state.
V+ Voltage
Comments
VL Voltage
V+ <
V+
VABOR
VABOR
VL < VDBOR Unknown Mid-Scale
Unknown Wiper
Wiper Register
VL VDBOR
Register can be updated
Value ( 1)
Note 1: Default POR state of the Wiper Register
value is the Mid-Scale value.
4.2.2.1
Digital Circuitry
When the device’s digital power supply powers down,
the device VL pin voltage will cross the digital VDPOR
VDBOR voltage.
/
/
Once the VL voltage decreases below the VDPOR
VDBOR voltage, the following happens:
• Serial Interface is disabled
If the VL voltage decreases below the VRAM voltage the
following happens:
• Volatile wiper registers may become corrupted
• TCON registers may become corrupted
Section 4.2.1, Power-on Reset describes what
occurs as the voltage recovers above the VDPOR
/
VDBOR voltage.
Serial commands not completed due to a brown-out
condition may cause the memory location to become
corrupted.
The brown-out circuit establishes a minimum VDBOR
threshold for operation (VDBOR < 1.8V). The digital
BOR voltage (VDBOR) is higher then the RAM retention
voltage (VRAM) so that as the device voltage crosses
the digital BOR threshold, the value that is loaded into
the volatile wiper register is not corrupted, due to RAM
retention issues.
When VL < VDBOR, all communications are ignored and
potentiometer terminals are forced to the analog BOR
state.
2013 Microchip Technology Inc.
DS20005207A-page 27
MCP41HVX1
TABLE 4-5:
DEVICE FUNCTIONALITY AT EACH VL REGION
Wiper
Serial
Potentiometer
VL Level
V+ / V- Level
Comment
Interface Terminals ( 2)
Register
Setting
Output
( 2)
VL < VDBOR < 1.8V Valid Range Ignored
Invalid Range Ignored
“unknown”
“unknown”
Unknown
Unknown
Invalid
Invalid
VDBOR VL < 1.8V Valid Range “Unknown” connected
Volatile wiper Valid
The volatile registers are
forced to the POR/BOR
state when VL transitions
above the VDPOR trip
point
Register
Invalid Range “Unknown” connected
Invalid
initialized
1.8V VL 5.5V
Valid Range Accepted connected
Invalid Range Accepted connected
Volatile wiper Valid
Register
Invalid
determines
Wiper Setting
Note 1: For system voltages below the minimum operating voltage, it is recommended to use a voltage supervisor
to hold the system in reset. This ensures that MCP41HVX1 commands are not attempted out of the oper-
ating range of the device.
2: Assumes that V+ > VAPOR
.
Normal Operation Range
L
Normal Operation Range
Outside Specified
AC/DC Range
V
1.8V
POR/BOR
V
V
RAM
DGND
Device’s Serial
Interface is
“Not Operational”
Device’s Serial
Interface is
“Not Specified
V
Delay
BOR
Wiper Forced to Default POR/BOR setting
FIGURE 4-4:
Power-up and Brown out - V+ / V- at Normal Operating Voltage.
DS20005207A-page 28
2013 Microchip Technology Inc.
MCP41HVX1
4.3.1.2
Terminal Control Register
4.3
Control Module
The Terminal Control (TCON) register allows the
device’s terminal pins to be independently removed
from the application circuit. These terminal control
settings do not modify the wiper setting values. Also
this has no effect on the serial interface and the
memory/wipers are still under full user control.
The control module controls the following functionality:
• Shutdown
• Wiper Latch
4.3.1
SHUTDOWN
The MCP41HVX1 has two methods to disconnect the
terminal’s pins (P0A, P0W, and P0B) from the resistor
network. These are:
The resistor network has four TCON bits associated
with it. One bit for each terminal (A, W, and B) and one
to have a software configuration that matches the
configuration of the SHDN pin. These bits are named
R0A, R0W, R0B, and R0HW. Register 4-1 describes
theoperationoftheR0HW, R0A, R0B, andR0Wbits.
• Hardware Shutdown pin (SHDN)
• Terminal Control Register (TCON)
4.3.1.1
Hardware Shutdown Pin Operation
Note:
When the R0HW bit forces the resistor
network into the hardware SHDN state,
the state of the TCON register R0A, R0W,
and R0B bits is overridden (ignored).
When the state of the R0HW bit no longer
forces the resistor network into the
hardware SHDN state, the TCON register
R0A, R0W, and R0B bits return to
controlling the terminal connection state.
That is, the R0HW bit does not corrupt the
state of the R0A, R0W, and R0B bits.
The SHDN pin has the same functionality as
Microchip’s family of standard voltage devices. When
the SHDN pin is low, the P0A terminal will disconnect
(become open) while the P0W terminal simultaneously
connect to the P0B terminal (see Figure 4-5).
Note:
When the SHDN pin is Active (VIL), the
state of the TCON register bits is
overridden (ignored). When the state of
the SHDN pin returns to the Inactive state
(VIH), the TCON register bits return to
controlling the terminal connection state.
That is the value in the TCON register is
not corrupted
Figure 4-6 shows how the SHDN pin signal and the
R0HW bit signal interact to control the hardware
shutdown of each resistor network (independently).
The Hardware Shutdown pin mode does not corrupt
the Volatile Wiper Register. So when Shutdown is
exited, the device returns to the Wiper setting specified
by the Volatile Wiper value. See Section 5.7 for
additional description details.
SHDN (from pin)
To Pot 0 Hardware
Shutdown Control
R0HW
(from TCON register)
Note:
When the SHDN pin is active, the Serial
Interface is not disabled, and serial inter-
face activity is executed.
FIGURE 4-6:
Interaction.
R0HW bit and SHDN pin
A
W
B
FIGURE 4-5:
Hardware Shutdown
Resistor Network Configuration.
2013 Microchip Technology Inc.
DS20005207A-page 29
MCP41HVX1
4.3.2
WIPER LATCH
The wiper latch pin is used to control when the new
wiper value in the Wiper register is transferred to the
wiper. This is useful for applications that need to
synchronize the wiper updates. This may be for
synchronization to an external event, such as zero
crossing, or to synchronize the update of multiple
digital potentiometers.
Note 1: This feature only inhibits the data transfer
from the Wiper register to the Wiper.
2: When the WLAT pin becomes active,
data transferred to the Wiper will not be
corrupted due to the Wiper Register Buf-
fer getting loaded from an active SPI
command.
When the WLAT pin is high, transfers from the Wiper
register to the Wiper are inhibited. When the WLAT pin
is low, transfers may occur from the Wiper register to
the Wiper. Figure 4-7 shows the interaction of the
WLAT pin and the loading of the Wiper.
4.3.3
DEVICE CURRENT MODES
There are two current modes for Volatile devices.
These are:
• Serial Interface Inactive (Static Operation)
• Serial Interface Active
If the external event crossing time is long, then the
wiper could be updated the entire time that the WLAT
signal is low. Once the WLAT signal goes high, the
transfer from the Wiper register is disabled. The Wiper
register can continue to be updated. Only the CS pin is
used to enable/disable serial commands.
For the SPI interface, Static Operation occurs when
the CS pin is at the VIH voltage and the SCK pin is
static (High or Low).
If the application does not require synchronized Wiper
register updates, then the WLAT pin should be tied low.
VIH
CS
VIL
VIH
WLAT
VIL
VIL
16 SCK
16 SCK
16 SCK
16 SCK
SCK
Wiper
Register
Loaded
Wiper
Register
Transferred
to Wiper
When WLAT goes low during an SPI active transfer,
the previously loaded Wiper Register value is
transferred to the wiper. (1)
When WLAT goes high during an SPI active transfer,
the Wiper Register value will be updated with
the new value from this serial command when the
command completes. The wiper will retain the
value that was last transferred from the Wiper
Register before the WLAT pin went high.
Note 1: The Wiper Register may be updated on 16 SCK cycles for a Write command, or on 8 SCK cycles with an
Increment or Decrement command.
2: The WLAT pin should not be brought high during the falling edge of the 8th clock cycle of an Increment
or Decrement command or the 16th clock cycle of a Write command.
FIGURE 4-7:
WLAT Interaction with Wiper During Serial Communication - (SPI Mode 1,1).
DS20005207A-page 30
2013 Microchip Technology Inc.
MCP41HVX1
4.4
Memory Map
TABLE 4-6:
WIPER POR STANDARD
SETTINGS
The device memory supports 16 locations that are 8-
bits wide (16x8 bits). This memory space contains only
volatile locations (see Table 4-7).
Wiper
Code
Default
POR Wiper
Setting
Resistance
Code
Typical
RAB Value
4.4.1
VOLATILE MEMORY (RAM)
8-bit 7-bit
There are two volatile memory locations. These are:
-502
-103
-503
-104
5.0 k
10.0 k
50.0 k
100.0 k
Mid scale
Mid scale
Mid scale
Mid scale
7Fh 3Fh
7Fh 3Fh
7Fh 3Fh
7Fh 3Fh
• Volatile Wiper 0
• Terminal Control (TCON0) Register 0
The volatile memory starts functioning at the RAM
retention voltage (VRAM). The POR/BOR Wiper code is
shown in Table 4-6.
4.4.1.1
Write to Invalid (Reserved)
Addresses
Table 4-7 shows this memory map and which serial
commands operate (and don’t) on each of these
locations.
Any write to a reserved address will be ignored and will
generate an error condition. To exit the error condition,
the user must take the CS pin to the VIH level and then
back to the active state (VIL).
Accessing an “invalid” address (for that device) or an
invalid command for that address will cause an error
condition (CMDERR) on the serial interface.
TABLE 4-7:
Address
00h
MEMORY MAP AND THE SUPPORTED COMMANDS
Function
Allowed Commands
Disallowed Commands (1)
Memory Type
Volatile Wiper 0
Read, Write,
—
RAM
Increment, Decrement
01h - 03h Reserved
none
Read, Write
none
Read, Write,
Increment, Decrement
—
RAM
—
04h
Volatile
Increment, Decrement
TCON Register
05h - 0Fh Reserved
Read, Write,
Increment, Decrement
Note 1: This command on this address will generate an error condition. To exit the error condition, the user must
take the CS pin to the VIH level and then back to the active state (VIL).
2013 Microchip Technology Inc.
DS20005207A-page 31
MCP41HVX1
The value that is written to this register will appear on
the resistor network terminals when the serial
command has completed.
4.4.1.2
Terminal Control (TCON) Registers
The Terminal Control (TCON) Register contains 4
control bits for Wiper 0. Register 4-1 describes each bit
of the TCON register.
On a POR/BOR, these registers are loaded with FFh,
for all terminals connected. The host controller needs
to detect the POR/BOR event and then update the
volatile TCON register values.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
REGISTER 4-1:
TCON0 BITS ( 1) (CONTINUED)
R-1
D7
R-1
D6
R-1
D5
R-1
D4
R/W-1
R0HW
R/W-1
R0A
R/W-1
R0W
R/W-1
R0B
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7:4
bit 3
D7-D4: Reserved. Forced to “1”
R0HW: Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin
1= Resistor 0 is NOT forced to the hardware pin “shutdown” configuration
0= Resistor 0 is forced to the hardware pin “shutdown” configuration
bit 2
bit 1
bit 0
R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1= P0A pin is connected to the Resistor 0 Network
0= P0A pin is disconnected from the Resistor 0 Network
R0W: Resistor 0 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network
1= P0W pin is connected to the Resistor 0 Network
0= P0W pin is disconnected from the Resistor 0 Network
R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network
1= P0B pin is connected to the Resistor 0 Network
0= P0B pin is disconnected from the Resistor 0 Network
Note 1: These bits do not affect the wiper register values.
2: The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the
inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the
state of the TCON bits.
DS20005207A-page 32
2013 Microchip Technology Inc.
MCP41HVX1
5.1
Resistor Ladder Module
5.0
RESISTOR NETWORK
The RAB resistor ladder is composed of the series of
equal value Step resistors (RS) and the Full-Scale
(RFS) and Zero-Scale (RZS) resistances:
The Resistor Network has either 7-bit or 8-bit
resolution. Each Resistor Network allows zero scale to
full-scale connections. Figure 5-1 shows a block
diagram for the resistive network of a device. The
Resistor network has up to three external connections.
These are referred to as Terminal A, Terminal B, and
the Wiper (or Terminal W).
RAB = RZS + n * RS + RFS
Where “n” is determined by the resolution of the device.
The RFS and RZS resistances are discussed in
Section 5.1.3.
The Resistor Network is made up of several parts.
These include:
There is a connection point (tap) between each RS
resistor. Each tap point is a connection point for an
analog switch. The opposite side of the analog switch
is connected to a common signal which is connected to
the Terminal W (Wiper) pin (see Section 5.2).
• Resistor Ladder Module
• Wiper
• Shutdown Control (Terminal Connections)
Figure 5-1 shows a block diagram of the Resistor
Network. The RAB (and RS) resistance has small
variations over voltage and temperature.
Terminal A and B as well as the Wiper W do not have a
polarity. These terminals can support both positive and
negative current.
The end points of the resistor ladder are connected to
analog switches, which are connected to the device
Terminal A and Terminal B pins. In the ideal case, these
switches would have 0 of resistance, that is
RFS = RZS = 0. This will also be referred as the
Simplified model.
A
8-Bit
N =
7-Bit
N =
RFS
255
127
(FFh)
(7Fh)
(1)
RW
For an 8-bit device, there are 255 resistors in a string
between Terminal A and Terminal B. The wiper can be
set to tap onto any of these 255 resistors, thus provid-
ing 256 possible settings (including Terminal A and
Terminal B). A wiper setting of 00h connects Terminal
W (wiper) to Terminal B (Zero Scale). A wiper setting of
7Fh is the Mid-scale setting. A wiper setting of FFh con-
nects Terminal W (wiper) to Terminal A (Full Scale).
Table 5-2 illustrates the full wiper setting map.
RS
254
(FEh)
126
(7Eh)
(1)
(1)
RW
RW
RS
RS
253
(FDh)
125
(7Dh)
RAB
For a 7-bit device, there are 127 resistors in a string
between Terminal A and Terminal B. The wiper can be
set to tap onto any of these 127 resistors, thus provid-
ing 128 possible settings (including Terminal A and
Terminal B). A wiper setting of 00h connects Terminal
W (wiper) to Terminal B (Zero Scale). A wiper setting of
3Fh is the Mid-scale setting. A wiper setting of 7Fh con-
nects the wiper to Terminal A (Full Scale). Table 5-2
illustrates the full wiper setting map.
W
1
1
(01h)
(01h)
(1)
(1)
RW
RW
RS
0
0
(00h)
(00h)
RZS
Analog Mux
5.1.1
RAB CURRENT (IRAB)
B
The current through the RAB resistor (A pin to B pin) is
dependent on the voltage on the VA and VB pins and
the RAB resistance.
Note 1: The wiper resistance is dependent on
several factors including wiper code,
device V+ voltage, terminal voltages (on
A, B and W), and temperature.
EQUATION 5-1:
RAB
Also for the same conditions, each tap
selection resistance has a small variation.
This RW variation has greater effect on
some specifications (such as INL) for the
smaller resistance devices (5.0 k)
compared to larger resistance devices
(100.0 k).
| (VA - VB) |
RAB = RZS + ( n * RS ) + RFS
=
(IRAB
)
VA is the voltage on the VA pin.
VB is the voltage on the VB pin.
IRAB is the current into the VREF pin.
FIGURE 5-1:
Resistor Block Diagram.
2013 Microchip Technology Inc.
DS20005207A-page 33
MCP41HVX1
5.1.2
STEP RESISTANCE (RS)
EQUATION 5-2:
RS CALCULATION
Step resistance (RS) is the resistance from one tap set-
ting to the next. This value will be dependent on the
RAB value that has been selected (and the full scale
and zero scale resistances). The RS resistors are
manufactured so that they should be very consistent
with each other, and track each other’s values as
voltage and/or temperature change.
Simplified Model (assumes RFS = RZS = 0)
RAB = ( n * RS )
8-bit
7-bit
RAB
n
RAB
RAB
RS =
RS =
RS =
255
127
Detailed Model
Equation 5-2 shows the simplified and detailed equa-
tions for calculating the RS value. The simplified equa-
tion assumes RFS = RZS = 0. Table 5-1 shows
example step resistance calculations for each device,
FS 0;
RAB = RFS + ( n * RS ) + RZS
RAB - RFS - RZS
RS =
n
RanZdS th0ev)afrroiamtiotnheosfimthpelifideedtmailoeddelm(RoFdSel=(RRZS = 0).
As the RAB resistance option increases, the effects of
the RZS and RFS resistance decreases.
or
(VFS - VZS
)
n
RS =
IAB
The total resistance of the device has minimal variation
due to operating voltage (see device characterization
graphs).
Where:
“n” = 255 (8-bit) or 127 (7-bit)
VFS is the wiper voltage at Full-Scale code
ZS is the wiper voltage at Zero-Scale code
Equation 5-2 shows calculations for the step
resistance.
V
IAB is the current between Terminal A and
Terminal B
TABLE 5-1:
RAB
EXAMPLE STEP RESISTANCES (RS) CALCULATIONS
Example Resistance ()
Variation
RS
Equation
Resolution Comment
% ( 1)
RZS ( 3) RFS ( 3)
Value
0
80
0
0
60
0
5,000 / 127
4,860 / 127
5,000 / 255
4,860 / 255
10,000 / 127
9,860 / 127
10,000 / 255
9,860 / 255
50,000 / 127
49,860 / 127
50,000 / 255
49,860 / 255
100,000 / 127
99,860 / 127
100,000 / 255
99,860 / 255
39.37
38.27
0
-2.80
0
7-bit
(127 RS)
Simplified Model ( 2)
5,000
19.61
8-bit
(255 RS)
Simplified Model ( 2)
Simplified Model ( 2)
Simplified Model ( 2)
Simplified Model ( 2)
Simplified Model ( 2)
Simplified Model ( 2)
Simplified Model ( 2)
80
0
60
0
19.06
-2.80
0
78.74
7-bit
(127 RS)
80
0
60
0
77.64
-1.40
0
10,000
50,000
100,000
39.22
8-bit
(255 RS)
80
0
60
0
38.67
-1.40
0
393.70
392.60
196.08
195.53
787.40
786.30
392.16
391.61
7-bit
(127 RS)
80
0
60
0
-0.28
0
8-bit
(255 RS)
80
0
60
0
-0.28
0
7-bit
(127 RS)
80
0
60
0
-0.14
0
8-bit
(255 RS)
80
60
-0.14
Note 1: Delta % from Simplified Model RS calculation value:
2: Assumes RFS = RZS = 0.
3: Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of
the device, including the V+ / V- voltage, the voltages on the A, B and W terminals, the wiper code
selected, the RAB resistance, and the temperature of the device.
DS20005207A-page 34
2013 Microchip Technology Inc.
MCP41HVX1
5.1.3
RFS AND RZS RESISTORS
5.2
Wiper
The RFS and RZS resistances are artifacts of the RAB
resistor network implementation. In the ideal model, the
RFS and RZS resistances would be 0. These resistors
are included in the block diagram to help better model
the actual device operation. Equation 5-3 shows how to
estimate the RS, RFS, and RZS resistances, based on
the measured voltages of VREF, VFS, and VZS and the
The wiper terminal is connected to an analog switch
mux, where one side of all the analog switches are
connected together, the W terminal. The other side of
each analog switch is connected to one of the taps of
the RAB resistor string (see Figure 5-1).
The value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder. The wiper
register is 8-bits wide, and Table 5-2 shows the wiper
value state for both 7-bit and 8-bit devices.
measured current IVREF
.
EQUATION 5-3:
ESTIMATING RS, RFS
AND RZS
,
The wiper resistance (RW) is the resistance of the
selected analog switch in the analog mux. This
resistance is dependent on many operational
characteristics of the device, including the V+ / V- volt-
age, the voltages on the A, B and W terminals, the
wiper code selected, the RAB resistance, and the tem-
perature of the device.
| ( VA - VFS ) |
RFS
RZS
=
=
(IRAB
| ( VZS - VB) |
(IRAB
)
)
VS
RS =
(IRAB
)
When the wiper value is at zero scale (00h), the Wiper
is connected closest to the B terminal. When the wiper
value is at full scale (FFh for 8-bit, 7Fh for 7-bit), the
Wiper is connected closest to the A terminal.
Where:
VS =
( VFS - VZS
255
)
)
(8-bit device)
(7-bit device)
A zero-scale wiper value connects the W terminal
(wiper) to the B terminal (wiper = 00h). A full-scale
wiper value connects the W terminal (wiper) to the A
terminal (wiper = FFh (8-bit), or wiper = 7Fh (7-bit)). In
these configurations, the only resistance between the
terminal W and the other terminal (A or B) is that of the
analog switches.
( VFS - VZS
127
VS =
VFS is the VW voltage when the wiper code is at
full-scale.
V
ZS is the VW voltage when the wiper code is at
zero-scale.
TABLE 5-2:
VOLATILE WIPER VALUE VS.
WIPER POSITION
Wiper Setting
Properties
7-bit
8-bit
7Fh
FFh Full Scale (W = A),
Increment commands ignored
7Eh -
40h
FEh - W = N
80h
3Fh
7Fh W = N (Mid Scale)
3Eh -
01h
7Eh - W = N
01h
00h
00h
Zero Scale (W = B)
Decrement command ignored
2013 Microchip Technology Inc.
DS20005207A-page 35
MCP41HVX1
5.2.1
WIPER RESISTANCE (RW)
5.2.2
POTENTIOMETER
CONFIGURATION
Wiper resistance is significantly dependent on:
In a potentiometer configuration, the wiper resistance
variation does not effect the output voltage seen on the
W pin and therefore is not a significant source of error.
• The Resistor Network’s Supply Voltage (VRN
• The Resistor Network’s Terminal (A, B, and W)
Voltages
)
• Switch leakage (occurs at higher temperatures)
• IW current
5.2.3
RHEOSTAT CONFIGURATION
In a rheostat configuration, the wiper resistance varia-
tion creates nonlinearity in the RBW (or RAW) value. The
lower the nominal resistance (RAB), the greater the
possible relative error. Also a change in voltage needs
to be taken into account. For the 5.0 k device the
maximum wiper resistance at 5.5V is approximately 6%
of the total resistance, while at 2.7V it is approximately
6.5% of the total resistance.
Figure 5-2 show the wiper resistance characterization
data for all four RAB resistances and temperatures.
Each RAB resistance determined the maximum wiper
current
based
on
worst
case
conditions
RAB = RAB maximum and at full scale code, VBW ~= V+
(but not exceeding V+). The V+ targets were 10V, 20V,
and 36V. What this graph shows is that at higher RAB
resistances (50 k and 100 k) and at the highest tem-
perature (+125°C), the analog switch leakage causes a
increase in the measured result of RW. Where RW is
5.2.4
LEVEL SHIFTERS
(DIGITAL TO ANALOG)
measured in a rheostat configuration with RW = (VBW
BA) / IBW
-
V
.
Since the digital logic may operate anywhere within the
analog power range, level shifters are present so that
the digital signals control the analog circuitry. This level
shifter logic is relative to the V- and VL voltages. A delta
voltage of 2.7V between VL and V- is required for the
serial interface to operate at the maximum specified
frequency.
2400
2200
2000
1800
1600
1400
1200
1000
800
Ͳ40Cꢀ5kꢀIWꢀ=ꢀ1.7mA
Ͳ40Cꢀ5kꢀIWꢀ=ꢀ3.3mA
Ͳ40Cꢀ5kꢀIWꢀ=6.0mA
Ͳ40Cꢀ10kꢀIWꢀ=ꢀ830uA
Ͳ40Cꢀ10kꢀIWꢀ=ꢀ1.7mA
Ͳ40Cꢀ10kꢀIWꢀ=ꢀ3.0mA
Ͳ40Cꢀ50kꢀIWꢀ=ꢀ170uA
Ͳ40Cꢀ50kꢀIWꢀ=ꢀ330uA
Ͳ40Cꢀ50kꢀIWꢀ=ꢀ600uA
Ͳ40Cꢀ100kꢀIWꢀ=ꢀ83uA
Ͳ40Cꢀ100kꢀIWꢀ=170uA
Ͳ40Cꢀ100kꢀIWꢀ=ꢀ300uA
+25Cꢀ5kꢀIWꢀ=ꢀ1.7mA
+25Cꢀ5kꢀIWꢀ=ꢀ3.3mA
+25Cꢀ5kꢀIWꢀ=ꢀ6.0mA
+25Cꢀ10kꢀIWꢀ=ꢀ830uA
+25Cꢀ10kꢀIWꢀ=ꢀ1.7mA
+25Cꢀ10kꢀIWꢀ=ꢀ3.0mA
+25Cꢀ50kꢀIWꢀ=ꢀ170uA
+25Cꢀ50kꢀIWꢀ=ꢀ330uA
+25Cꢀ50kꢀIWꢀ=ꢀ600uA
+25Cꢀ100kꢀIWꢀ=ꢀ83uA
+25Cꢀ100kꢀIWꢀ=ꢀ170uA
+25Cꢀ100kꢀIWꢀ=ꢀ300uA
+85Cꢀ5kꢀIWꢀ=ꢀ1.7mA
+85Cꢀ5kꢀIWꢀ=ꢀ3.3mA
+85Cꢀ5kꢀIWꢀ=ꢀ6.0mA
+85Cꢀ10kꢀIWꢀ=ꢀ830uA
+85Cꢀ10kꢀIWꢀ=ꢀ1.7mA
+85Cꢀ10kꢀIWꢀ=ꢀ3.0mA
+85Cꢀ50kꢀIWꢀ=ꢀ170uA
+85Cꢀ50kꢀIWꢀ=ꢀ330uA
+85Cꢀ50kꢀIWꢀ=ꢀ600uA
+85Cꢀ100kꢀIWꢀ=ꢀ83uA
+85Cꢀ100kꢀIWꢀ=ꢀ170uA
+85Cꢀ100kꢀIWꢀ=ꢀ300uA
+125Cꢀ5kꢀIWꢀ=ꢀ1.7mA
+125Cꢀ5kꢀIWꢀ=ꢀ3.3mA
+125Cꢀ5kꢀIWꢀ=ꢀ6.0mA
+125Cꢀ10kꢀIWꢀ=ꢀ830uA
+125Cꢀ10kꢀIWꢀ=ꢀ1.7mA
+125Cꢀ10kꢀIWꢀ=ꢀ3.0mA
+125Cꢀ50kꢀIWꢀ=ꢀ170uA
+125Cꢀ50kꢀIWꢀ=ꢀ330uA
+125Cꢀ50kꢀIWꢀ=ꢀ600uA
+125Cꢀ100kꢀIWꢀ=ꢀ83uA
+125Cꢀ100kꢀIWꢀ=ꢀ170uA
+125Cꢀ100kꢀIWꢀ=ꢀ300uA
IW =ꢀ83uA,ꢀ+125Cꢀ(100k:)
Increasedꢀwiperꢀresistanceꢀ(RW)ꢀoccursꢀꢀ
dueꢀtoꢀincreasedꢀanalog switchꢀleakage atꢀꢀ
higherꢀtemperaturesꢀ(suchꢀasꢀ+125C)ꢀand
largerꢀRAB resistances.
IW =ꢀ170uA,ꢀ+125Cꢀ(100k:)
W =ꢀ170uA,ꢀ+125Cꢀ(50k:)
IW =ꢀ300uA,ꢀ+125Cꢀ(100k:)
I
600
400
200
0
0
32
64
96
128
160
192
224
256
DAC Wiper Code
FIGURE 5-2:
RW Resistance vs RAB,
Wiper Current (IW), Temperature and Wiper
Code.
Since there is minimal variation of the total device
resistance (RAB) over voltage, at a constant tempera-
ture (see device characterization graphs), the change
in wiper resistance over voltage can have a significant
impact on the RINL and RDNL errors.
DS20005207A-page 36
2013 Microchip Technology Inc.
MCP41HVX1
ues, without violating the maximum terminal current
specification. Table 5-3 shows resistance and current
calculations based on the RAB resistance (RS resis-
tance) for a system that supports ± 18V ( 36V). In
Rheostat configuration, the minimum wiper-code value
is shown (for VBW = 36V). As the VBW voltage
decreases, the minimum wiper-code value also
decreases. Using a wiper code less then this value will
cause the maximum terminal current (IT) specification
to be violated.
5.3
Terminal Currents
The terminal currents are limited by several factors,
including the RAB resistance (RS resistance). The
maximum current occurs when the wiper is at either the
zero-scale (IBW) or full-scale (IAW) code. In this case,
the current is only going through the analog switches
(see IT specification in Electrical Characteristics).
When the current passes through at least one RS
resistive element, then the maximum terminal current
(IT) has a different limit. The current through the RAB
resistor is limited by the RAB resistance. The worst
case (max current) occurs when the resistance is at the
minimum RAB value.
Note:
For high terminal-current applications, it is
recommended that proper PCB layout
techniques be used to address the thermal
implications of this high current. The QFN
package has better thermal properties
than the TSSOP package.
Higher current capabilities allow a greater delta voltage
between the desired terminals for a given resistance.
This also allows a more usable range of wiper code val-
TABLE 5-3:
TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0)
RAB Resistance ()
RS(MIN) ()
Typical
Min
Max
8-bit
7-bit
8-bit 7-bit
8-bit
7-bit
5,000
4,000
8,000
6,000
15.686
31.373
31.496
62.992
9.00
4.50
0.90
0.45
25.0
12.5
6.5
1,440
2,880
5539
5539
91
91
35
17
45
45
17
8
0.392
0.392
1.020
2.039
0.787
0.787
2.047
4.094
10,000
12,000
50,000
40,000
60,000 156.863 314.961
629.9
100,000
80,000 120,000 313.725
6.5
Note 1: IBW or IAW currents can be much higher then this depending on voltage differential between Terminal B and
Terminal W or Terminal A and Terminal W.
2: Any RBW resistance greater then this limits the current.
3: If VBW = 36V, then the wiper code value must be greater than or equal to Min ‘N’. Wiper codes less than
Min ‘N’ will cause the wiper current (IW) to exceed the specification. Wiper codes greater than Min ‘N’ will
cause the wiper current to be less then the maximum. The Min ‘N’ number has been rounded up from the
calculated number to ensure that the wiper current does not exceed the maximum specification.
2013 Microchip Technology Inc.
DS20005207A-page 37
MCP41HVX1
Figure 5-3 through Figure 5-6 show a graph of the cal-
culated currents (minimum, typical, and maximum) for
each resistor option. These graphs are based on
25 mA (5 k), 12.5 mA (10 k), and 6.5 mA (50 k
and 100 k) specifications.
RAB(MIN)
RAB(TYP)
To ensure no damage to the resistor network (including
long-term reliability) the maximum terminal current
must not be exceeded. This means that the application
must assume that the RAB resistance is the minimum
RAB(MAX)
RAB value (RAB(MIN), see blue lines in graphs).
Looking at the 50 k device, the maximum terminal
current is 6.5 mA. That means that any wiper code
value greater than 36 ensures that the terminal current
is less than 6.5 mA. This is ~14% of the full scale value.
If the application could change to the 100 k device,
which has the same maximum terminal current specifi-
cation, any wiper-code value greater than 18 ensures
that the terminal current is less than 6.5 mA. This is
~7% of the full-scale value. Supporting higher terminal
current allows a greater wiper code range for a given
VBW voltage.
FIGURE 5-5:
Code - 50 k .
Maximum IBW vs Wiper
RAB(MIN)
RAB(TYP)
RAB = 5k:ꢀ
30.0E-3
25.0E-3
RAB(TYP)
RAB(MAX)
20.0E-3
RAB(MIN)
15.0E-3
RAB(MAX)
10.0E-3
FIGURE 5-6:
Code - 100 k .
Maximum IBW vs Wiper
5.0E-3
000.0E+0
Figure 5-7 shows a graph of the maximum VBW voltage
vs wiper code (for 5 k and 10 k devices). To ensure
that no damage is done to the resistor network, the
RAB(MIN) resistance (blue line) should be used to deter-
mine VBW voltages for the circuit. Devices where the
RAB resistance is greater than the RAB(MIN) resistance
will naturally support a higher voltage limit.
0
32
64
96
128
160
192
224
256
Wiper Code
FIGURE 5-3:
Code - 5 k .
Maximum IBW vs Wiper
RAB = 10k:ꢀ
14.0E-3
12.0E-3
10.0E-3
8.0E-3
6.0E-3
4.0E-3
2.0E-3
40.0
35.0
RAB(TYP)
RAB(MIN)
RAB(MAX)
30.0
25.0
20.0
15.0
10.0
5.0
RAB(TYP)
RAB(MAX)
RAB(MIN)
000.0E+0
0
32
64
96
128
160
192
224
256
Wiper Code
0.0
0
32
64
96
128
160
192
224
256
FIGURE 5-4:
Maximum IBW vs Wiper
Wiper Code
Code - 10 k .
FIGURE 5-7:
Maximum VBW vs Wiper
Code (5 k and 10 k devices).
DS20005207A-page 38
2013 Microchip Technology Inc.
MCP41HVX1
Table 5-4 shows the maximum VBW voltage that can be
applied across the Terminal B to Terminal W pins for a
given wiper code value (for the 5 k and 10 k
devices). These calculations assume the ideal model
(RW = RFS = RZS = 0) and show the calculations
based on RS(MIN) and RS(MAX). Table 5-5 shows the
same calculations for the 50 k devices, and Table 5-6
shows the calculations for the 100 k devices. These
tables are supplied as a quick reference.
TABLE 5-4:
MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V,
5K AND 10K DEVICES.
Code
V
Code
V
Code
V
BW(MAX)
BW(MAX)
BW(MAX)
Hex
00h
Dec
R
R
Hex
20h
Dec
R
R
Hex
Dec
R
R
S(MAX)
S(MIN)
S(MAX)
S(MIN)
S(MAX)
S(MIN)
0
0.000
0.392
0.784
1.176
1.569
1.961
2.353
2.745
3.137
3.529
3.922
4.314
4.706
5.098
5.490
5.882
5.275
6.667
7.059
7.451
7.843
8.235
8.627
9.020
9.412
9.804
10.196
10.588
10.980
11.373
11.765
12.157
0.000
0.588
1.176
1.765
2.353
2.941
3.529
4.118
4.706
5.294
5.882
6.471
7.059
7.647
8.235
8.824
9.412
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
12.549
12.941
13.333
13.725
14.118
14.510
14.902
15.294
15.686
16.078
16.471
16.863
17.255
17.647
18.039
18.431
18.824
19.216
19.608
20.000
20.392
20.784
21.176
21.569
21.961
22.353
22.745
23.137
23.529
23.922
18.824 40h
19.412 41h
20.000 42h
20.588 43h
21.176 44h
21.765 45h
22.353 46h
22.941 47h
23.529 48h
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
25.098
25.490
25.882
25.275
26.667
27.059
27.451
27.843
28.235
28.627
29.020
29.412
29.804
30.196
30.588
30.980
31.373
31.765
32.157
32.549
32.941
33.333
33.725
34.118
34.510
34.902
35.294
35.686
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
1
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
2
3
4
5
6
7
8
9
24.118
49h
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
24.706 4Ah
25.294 4Bh
25.882 4Ch
26.471 4Dh
27.059 4Eh
27.647 4Fh
28.235 50h
28.824 51h
29.412 52h
30.000 53h
30.588 54h
31.176 55h
31.765 56h
32.353 57h
32.941 58h
33.529 59h
10.000 31h
10.588 32h
11.176 33h
11.765 34h
12.353 35h
12.941 36h
13.529 37h
14.118 38h
14.706 39h
15.294 3Ah
15.882 3Bh
16.471 3Ch
17.059 3Dh
17.647 3Eh
18.235 3Fh
34.118
5Ah
34.706 5Bh
35.294 5Ch
35.882
92 - 255 36.0 ( 1, 2)
24.314 36.0 ( 1, 2)
24.706
Note 1: Calculated R
voltage is greater than 36V (highlighted in color), must be limited to 36V (V+ - V-).
BW
2: This wiper code and greater will limit the IBW current to less than the maximum supported terminal current
(IT).
2013 Microchip Technology Inc.
DS20005207A-page 39
MCP41HVX1
TABLE 5-5:
MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V,
50K DEVICES.
Code
V
Code
V
Code
V
BW(MAX)
BW(MAX)
BW(MAX)
Hex
00h
Dec
R
R
Hex
10h
Dec
R
R
Hex
Dec
R
R
S(MAX)
S(MIN)
S(MAX)
S(MIN)
S(MAX)
S(MIN)
0
1
0.000
1.020
2.039
3.059
4.078
5.098
6.118
0.000
1.529
3.059
4.588
6.118
7.647
9.176
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
16.314
17.333
18.353
19.373
20.392
21.412
22.431
23.451
24,471 20h
26.000 21h
27.529 22h
29.059 23h
32
33
34
35
32.627
33.647
34.667
35.686
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
11h
12h
13h
14h
15h
16h
2
3
4
30.588 24h - FFh 36 - 255 36.0 ( 1, 2)
5
32.118
33.647
35.176
6
7
7.137
8.157
9.176
10.196
11.216
12.235
13.255
14.275
15.294
10.706 17h
12.235 18h
13.765 19h
15.294 1Ah
16.824 1Bh
18.353 1Ch
19.882 1Dh
21.412 1Eh
22.941 1Fh
8
24.471 36.0 ( 1, 2)
9
25.490
10
11
12
13
14
15
26.510
27.529
28.549
29.569
30.588
31.608
Note 1: Calculated R
voltage is greater than 36V (highlighted in color), must be limited to 36V (V+ - V-).
BW
2: This wiper code and greater will limit the I
current to less than the maximum supported terminal current (I ).
T
BW
TABLE 5-6:
MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V,
100K DEVICES.
Code
V
Code
V
BW(MAX)
BW(MAX)
Hex
00h
Dec
R
R
Hex
10h
11h
Dec
R
R
S(MAX)
S(MIN)
S(MAX)
S(MIN)
0
1
0.000
2.039
0.000
3.059
16
17
32.627
34.667
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
2
4.078
6.118
12h - FFh 18 - 255 36.0 ( 1, 2)
3
6.118
9.176
4
8.157
12.235
15.294
18.353
21.412
24.471
27.529
30.588
33.647
5
10.196
12.235
14.275
16.314
18.353
20.392
22.431
6
7
8
9
10
11
12
13
14
15
24.471 36.0 ( 1, 2)
26.510
28.549
30.588
Note 1: Calculated R
voltage is greater than 36V (highlighted in color), must be limited to 36V (V+ - V-).
BW
2: This wiper code and greater will limit the I
current to less than the maximum supported terminal current (I ).
T
BW
DS20005207A-page 40
2013 Microchip Technology Inc.
MCP41HVX1
5.4
Variable Resistor (Rheostat)
5.5
Analog Circuitry Power
Requirements
A variable resistor is created using terminal W and
either terminal A or Terminal B. Since the wiper-code
value of 0 connects the wiper to the terminal B, the RBW
resistance increases with increasing wiper code value.
Conversely, the RAW resistance will decrease with
increasing wiper code value. Figure 5-8 shows the con-
nections from a potentiometer to create a rheostat con-
figuration.
This device has two power supplies. One is for the
digital interface (VL and DGND) and the other is for the
high voltage analog circuitry (V+ and V-). The
maximum delta voltage between V+ and V- is 36V. The
digital power signals must be between V+ and V-.
If the digital ground (DGND) pin is at half the potential
of V+ (relative to V-), then the terminal pins potentials
can be ±(V+/2) relative to DGND.
Figure 5-9 shows the relationship of the four power sig-
nals. This shows that the V+ / V- signals do not need to
be symmetric around the DGND signal.
A
RAW
To ensure that the wiper register has been properly
loaded with the POR/BOR value, the VL voltage must
be at the minimum specified operating voltage (refer-
enced to DGND).
RAW or
Resistor
RBW
W
RBW
B
V+
FIGURE 5-8:
Rheostat Configuration.
Equation 5-4 shows the RBW and RAW calculations.
The RBW calculation is for the resistance between the
wiper and terminal B. The RAW calculation is for the
resistance between the wiper and terminal A.
V+ - V— Voltage
+36V max
+10V min
VL
DGND
EQUATION 5-4:
RBW AND RAW
CALCULATION
V—
Simplified Model (assumes RFS = RZS = 0)
RBW = ( n * RS )
This can be anywhere
between V- and V+.
RAW = ( ( FSV - n ) * RS )
FIGURE 5-9:
Analog Circuitry Voltage
Ranges.
8-bit
RAB
7-bit
RAB
Where:
RS =
RAB
RS =
RS =
Resolution
5.6
Resistor Characteristics
255
127
n = wiper code
FSV = The full scale vale
(255 for 8-bit or 127 for 7-bit)
Detailed Model
5.6.1
V+ / V- LOW VOLTAGE OPERATION
The resistor network is specified from 20V to 36V. At
voltages below 20V, the resistor network will function,
but the operational characteristics may be outside the
specified limits. Please refer to Section 2.0 “Typical
Performance Curves” for additional information.
RBW = RZS + ( n * RS )
RAW = RFS + ( ( FSV - n ) * RS )
Where:
5.6.2
RESISTOR TEMPCO
n = wiper code
FSV = The full scale vale
Biasing the ends (Terminal A and Terminal B) near mid-
supply ( (V+ - |V-| ) / 2 ) will give the worst switch
resistance tempco.
(255 for 8-bit or 127 for 7-bit)
2013 Microchip Technology Inc.
DS20005207A-page 41
MCP41HVX1
5.7
Shutdown Control
Note:
When the R0HW bit forces the resistor
network into the hardware SHDN state,
the state of the TCON0 register’s R0A,
R0W and R0B bits is overridden (ignored).
When the state of the R0HW bit no longer
forces the resistor network into the
hardware SHDN state, the TCON0
register’s R0A, R0W and R0B bits return
to controlling the terminal connection
state. In other words, the R0HW bit does
not corrupt the state of the R0A, R0W and
R0B bits.
Shutdown is used to minimize the device’s current
consumption. The MCP41HVX1 has two methods to
achieve this:
• Hardware Shutdown Pin (SHDN)
• Terminal Control Register (TCON)
The Hardware Shutdown pin is backwards compatible
with the MCP42X1 devices.
5.7.1
HARDWARE SHUTDOWN PIN
(SHDN)
The SHDN pin is available on the potentiometer
devices. When the SHDN pin is forced active (VIL):
The R0HW bit does NOT corrupt the values in the
Volatile Wiper registers nor the TCON register. When
the Shutdown mode is exited (R0HW bit = 1):
• The P0A terminal is disconnected
• The P0W terminal is connected to the P0B termi-
nal (see Figure 4-5)
• The device returns to the Wiper setting specified
by the Volatile Wiper value
• The Serial Interface is NOT disabled, and all
Serial Interface activity is executed
• The TCON register bits return to controlling the
terminal connection state
The Hardware Shutdown pin mode does NOT corrupt
the values in the Volatile Wiper Registers nor the
TCON register. When the Shutdown mode is exited
(SHDN pin is inactive (VIH)):
A
W
• The device returns to the Wiper setting specified
by the Volatile Wiper value
• The TCON register bits return to controlling the
terminal connection state
B
FIGURE 5-11:
State (R0HW = 0).
Resistor Network Shutdown
A
5.7.3
INTERACTION OF SHDN PIN AND
TCON REGISTER
W
Figure 4-6 shows how the SHDN pin signal and the
R0HW bit signal interact to control the hardware
shutdown of the resistor network.
B
FIGURE 5-10:
Resistor Network Configuration.
Hardware Shutdown
SHDN (from pin)
To Pot 0 Hardware
Shutdown Control
R0HW
(from TCON register)
5.7.2 TERMINAL CONTROL REGISTER
(TCON)
The Terminal Control (TCON) register is a volatile
register used to configure the connection of each
resistor network terminal pin (A, B and W) to the
Resistor Network. This register is shown in Register 4-
1.
FIGURE 5-12:
Interaction.
R0HW bit and SHDN pin
The R0HW bit forces the selected resistor network into
the same state as the SHDN pin. Alternate low-power
configurations may be achieved with the R0A, R0W
and R0B bits.
When the R0HW bit is “0”:
• The P0A terminal is disconnected
• The P0W terminal is simultaneously connect to
the P0B terminal (see Figure 5-11)
DS20005207A-page 42
2013 Microchip Technology Inc.
MCP41HVX1
The MCP41HVX1 SPI’s module supports two (of the
four) standard SPI modes. These are Mode 0,0 and
1,1. The SPI mode is determined by the state of the
SCK pin (VIH or VIL) on the when the CS pin transitions
from inactive (VIH) to active (VIL).
6.0
SERIAL INTERFACE (SPI)
The MCP41HVX1 devices support the SPI serial
protocol. This SPI operates in the Slave mode (does
not generate the serial clock). The device’s SPI com-
mand format operates on multiples of 8-bits.
Note:
Some Host Controller SPI modules only
operate with 16-bit transfers. For these
Host Controllers, only the Read and Write
Commands may be used, or the Continu-
ous Increment or Decrement Commands
that are an even multiple of Increment or
Decrement commands.
The SPI interface uses up to four pins. These are:
• CS – Chip Select
• SCK – Serial Clock
• SDI – Serial Data In
• SDO – Serial Data Out
A typical SPI interface is shown in Figure 6-1. In the
SPI interface, the Master’s Output pin is connected to
the Slave’s Input pin and the Master’s Input pin is
connected to the Slave’s Output pin.
Typical SPI Interface Connections
MCP41HVX1
Host
Controller
( Master Out - Slave In (MOSI) )
( Master In - Slave Out (MISO) )
SDI
SDO
SDI
SDO
SCK
SCK
CS
I/O
I/O
I/O
WLAT
SHDN
FIGURE 6-1:
Typical SPI Interface Block Diagram.
2013 Microchip Technology Inc.
DS20005207A-page 43
MCP41HVX1
6.1.4
THE CHIP SELECT SIGNAL (CS)
6.1
SDI, SDO, SCK, and CS Operation
The Chip Select (CS) signal is used to select the device
and frame a command sequence. To start a command,
or sequence of commands, the CS signal must
transition from the inactive state (VIH) to an active state
(VIL).
The operation of the four SPI interface pins are
discussed in this section. These pins are:
• Serial Data In (SDI)
• Serial Data Out (SDO)
• Serial Clock (SCK)
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
• The Chip Select Signal (CS)
The serial interface works on either 8-bit or 16-bit
boundaries depending on the selected command. The
Chip Select (CS) pin frames the SPI commands.
Note:
There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
If an error condition occurs for an SPI command, then
the command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (VIL). To exit the
error condition, the user must take the CS pin to the VIH
level.
6.1.1
SERIAL DATA IN (SDI)
The Serial Data In (SDI) signal is the data signal into
the device. The value on this pin is latched on the rising
edge of the SCK signal.
When the CS pin returns to the inactive state (VIH), the
SPI module resets (including the Address Pointer).
While the CS pin is in the inactive state (VIH), the serial
interface is ignored. This allows the host controller to
interface to other SPI devices using the same SDI,
SDO and SCK signals.
6.1.2
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
Once the CS pin is forced to the active level (VIL), the
SDO pin will be driven. The state of the SDO pin is
determined by the serial bit’s position in the command,
the command selected, and if there is a command error
state (CMDERR).
6.1.5
LOW VOLTAGE SUPPORT
The Serial Interface is designed to also support 1.8V
operation (at reduced specifications - frequency,
thresholds, etc.). This allows the MCP41HVX1 device
to interface to low-voltage host controllers.
6.1.3
SERIAL CLOCK (SCK)
The Serial Clock (SCK) signal is the clock signal of the
SPI module. The frequency of the SCK pin determines
the SPI frequency of operation.
At 1.8V VL operation, the DGND signal must be 0.9V or
greater above the V- signal. If VL is 2.0V or greater,
than the DGND signal can be tied to the V- signal (see
Table 6-1).
The SPI interface is specified to operate up to 10 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used. Table 6-1
shows the SCK frequency.
6.1.6
SPLIT RAIL SUPPORT
The Serial Interface is designed to support split rail
systems. In a split rail system, the microcontroller can
operate at a lower voltage than the MCP41HXX1
device. This is achieved with the VIH specification.
TABLE 6-1:
SCK FREQUENCY
Command
For VL 2.7V, the minimum VIH = 0.45 * VL. So if the
microcontroller VOH at 1.8V is 0.8 * VDD, then VL can
be a maximum of 3.2V (see Equation 6-1).
VL
Voltage
Write,
Read Increment,
Decrement
Comment
See Section 8.1 for additional discussion on split rail
support.
2.7V
1.8V
2.0V
10 MHz
10 MHz
1 MHz
1 MHz
1 MHz
1 MHz
DGND = V- + 0.9V
DGND = V-
EQUATION 6-1:
CALCULATING MAX VL
FORMICROCONTROLLER
AT 1.8V
If VOH = 0.8 * VDD = 0.8 * 1.8V = 1.44V
Then: VIH(MIN) = 1.44V
With VIH = 0.45 * VL
Then: VL = 1.44V / 0.45 = 3.2V
DS20005207A-page 44
2013 Microchip Technology Inc.
MCP41HVX1
6.2
The SPI Modes
6.3
SPI Waveforms
The SPI module supports two (of the four) standard SPI
modes. These are Mode 0,0 and 1,1. The mode is
determined by the state of the SDI pin on the rising
edge of the first clock bit (of the 8-bit byte).
Figure 6-2 through Figure 6-5 show the different SPI
command waveforms. Figure 6-2 and Figure 6-3 are
read and write commands. Figure 6-4 and Figure 6-5
are Increment and Decrement commands.
6.2.1
MODE 0,0
6.4
Daisy Chaining
In Mode 0,0: SCK Idle state = low (VIL), data is clocked
in on the SDI pin on the rising edge of SCK and clocked
out on the SDO pin on the falling edge of SCK.
This SPI Interface does NOT support daisy chaining.
6.2.2
MODE 1,1
In Mode 1,1: SCK Idle state = high (VIH), data is
clocked in on the SDI pin on the rising edge of SCK and
clocked out on the SDO pin on the falling edge of SCK.
VIH
CS
VIL
SCK
PIC Writes
to SSPBUF
CMDERR bit
SDO
SDI
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8 bit7 bit6 bit5
bit4 bit3 bit2 bit1
bit0
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
bit9
bit8 bit7 bit6 bit5
bit4 bit3 bit2 bit1
bit0
C1
C0
Input
Sample
FIGURE 6-2:
16-Bit Commands (Write, Read) – SPI Waveform (Mode 1,1).
VIH
CS
VIL
SCK
PIC Writes
to SSPBUF
CMDERR bit
SDO
SDI
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8 bit7 bit6 bit5
bit4 bit3 bit2 bit1
bit0
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
bit9
bit8 bit7 bit6 bit5
bit4 bit3 bit2 bit1
bit0
C1
C0
Input
Sample
FIGURE 6-3:
16-Bit Commands (Write, Read) – SPI Waveform (Mode 0,0).
2013 Microchip Technology Inc.
DS20005207A-page 45
MCP41HVX1
VIH
CS
VIL
SCK
PIC Writes
to SSPBUF
CMDERR bit
“1” = Valid Command
“0” = Invalid Command
SDO
SDI
bit6
bit2
bit5
bit4
bit1
bit0
bit7
bit3
AD2
AD1
X
AD0
C0
AD3
bit7
C1
X
bit0
Input
Sample
FIGURE 6-4:
8-Bit Commands (Increment, Decrement) – SPI Waveform with PIC MCU (Mode 1,1).
VIH
CS
VIL
SCK
PIC Writes
to SSPBUF
CMDERR bit
“1” = Valid Command
“0” = Invalid Command
bit6
AD2
bit2
C0
bit5
bit4
AD0
bit1
bit0
SDO
SDI
bit7
bit3
C1
AD1
X
AD3
bit7
X
bit0
Input
Sample
FIGURE 6-5:
8-Bit Commands (Increment, Decrement) – SPI Waveform with PIC MCU (Mode 0,0).
DS20005207A-page 46
2013 Microchip Technology Inc.
MCP41HVX1
7.1
Command Format
7.0
DEVICE COMMANDS
All commands have a Command Byte, which specifies
the register address and the command. Commands
which require data (write and read commands), also
have the Data Byte.
The MCP41HVX1’s SPI command format supports
16 memory address locations and four commands.
These commands are shown in Table 7-1.
Commands may be sent when the CS pin is driven to
VIL. The 8-bit commands (Increment Wiper and Dec-
rement Wiper commands) contain a command byte,
see Figure 7-1, while 16-bit commands (Read Data
and Write Data commands) contain a command byte
and a data byte. The command byte contains two data
bits, see Figure 7-1.
7.1.1
COMMAND BYTE
The command byte has three fields, the address, the
command, and two data bits, see Figure 7-1. Currently
only one of the data bits is defined (D8). This is for the
Write command.
The device memory is accessed when the master
sends a proper command byte to select the desired
operation. The memory location to be accessed is con-
tained in the command byte’s AD3:AD0 bits. The action
desired is contained in the command byte’s C1:C0 bits,
see Table 7-1. C1:C0 determines if the desired memory
location will be read, written, incremented (wiper set-
ting +1) or decremented (wiper setting -1). The Incre-
ment and Decrement commands are only valid on the
volatile wiper registers.
Table 7-2 shows the supported commands for each
memory location and the corresponding values on the
SDI and SDO pins.
TABLE 7-1:
C1:C0
Bit Command Name
States
COMMANDS
# of
Bits
11
Read Data
16-Bits
16-Bits
8-Bits
As the command byte is being loaded into the device
(on the SDI pin), the device’s SDO pin is driving. The
SDO pin will output high bits for the first six bits of that
command. On the 7th bit, the SDO pin will output the
CMDERR bit state (see Section 7.1.1.1 “Error
Condition”). The 8th bit state depends on the
command selected.
00
01
10
Write Data
Increment Wiper
Decrement Wiper
8-Bits
16-bit Command
8-bit Command
Command Byte
Data Byte
Command Byte
A A A A C C D D D D D D D D D D
D D D D 1 0 9 8 7 6 5 4 3 2 1 0
3 2 1 0
A A A A C C D D
D D D D 1 0 9 8
3 2 1 0
Command
Bits
C C
1 0
Data
Bits
0 0 = Write Data
0 1 = INCR
Data
Bits
Memory
Address
Memory
Address
1 0 = DECR
1 1 = Read Data
Command
Bits
Command
Bits
This bit is only used as the CMDERR bit.
This bit is not used. Maintained for code compatibility with MCP41XX, MCP42XX, and MCP43XX devices.
General SPI Command Formats.
D9
D8
FIGURE 7-1:
2013 Microchip Technology Inc.
DS20005207A-page 47
MCP41HVX1
TABLE 7-2:
Address
Function
MEMORY MAP AND THE SUPPORTED COMMANDS
SPI String (Binary)
MOSI (SDI pin)
MISO (SDO pin) ( 2)
Data
Command
(10-bits) ( 1)
Value
00h
Volatile Wiper 0 Write Data
Read Data
nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111
nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn
Increment Wiper
—
—
—
0000 0100
0000 1000
—
1111 1111
1111 1111
—
Decrement Wiper
—
01h - Reserved
03h ( 4)
04h ( 3) Volatile
Write Data
Read Data
—
nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111
nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn
TCON Register
05h - Reserved
—
—
—
0Fh ( 4)
Note 1: The data memory is 8-bits wide, so the two MSbs (D9:D8) are ignored by the device.
2: All these address/command combinations are valid, so the CMDERR bit is set. Any other address/
command combination is a command error state and the CMDERR bit will be clear.
3: Increment or Decrement commands are invalid for these addresses.
4: Reserved addresses: Any command is invalid for these addresses.
DS20005207A-page 48
2013 Microchip Technology Inc.
MCP41HVX1
7.1.1.1
Error Condition
7.1.2
DATA BYTE
The CMDERR bit indicates if the four address bits
received (AD3:AD0) and the two command bits
Only the Read command and the Write command use
the data byte, see Figure 7-1. These commands
concatenate the 8 bits of the data byte with the one
data bit (D8) contained in the command byte to form 9-
bits of data (D8:D0). The command byte format
supports up to 9-bits of data, but the MCP41HVX1 only
uses the lower 8-bits. That means that the Full Scale
code of the 8-bit resistor network is FFh. When at Full
Scale, the wiper connects to Terminal A. The D8 bit is
maintained for code compatibility with the MCP41XX,
MCP42XX, and MCP43XX devices.
received (C1:C0) are
a valid combination. The
CMDERR bit is high if the combination is valid and low
if the combination is invalid (see Table 7-3).
The command error bit will also be low if a write to a
Reserved Address has been specified. SPI commands
that do not have a multiple of eight clocks are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the inactive state (VIH).
The D9 bit is currently unused, and corresponds to the
position on the SDO data of the CMDERR bit.
TABLE 7-3:
CMDERR
COMMAND ERROR BIT
7.1.3
CONTINUOUS COMMANDS
The device supports the ability to execute commands
continuously while the CS pin is in the active state (VIL).
Any sequence of valid commands may be received.
Description
Bit States
1
0
“Valid” Command/Address combination
“Invalid” Command/Address combination
The following example is a valid sequence of events:
1. CS pin driven active (VIL).
2. Read Command.
Aborting a Transmission
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks have
been received. Some commands also require the CS
pin to be forced inactive (VIH). If the CS pin is forced to
the inactive state (VIH), the serial interface is reset.
Partial commands are not executed.
3. Increment Command (Wiper 0).
4. Increment Command (Wiper 0).
5. Decrement Command (Wiper 0).
6. Write Command.
7. Read Command.
8. CS pin driven inactive (VIH).
SPI is more susceptible to noise than other bus
protocols. The most likely case is that this noise
corrupts the value of the data being clocked into the
MCP41HVX1 or the SCK pin is injected with extra clock
pulses. This may cause data to be corrupted in the
device, or a command error to occur, since the address
and command bits were not a valid combination. The
extra SCK pulse will also cause the SPI data (SDI) and
clock (SCK) to be out of sync. Forcing the CS pin to the
inactive state (VIH) resets the serial interface. The SPI
interface will ignore activity on the SDI and SCK pins
until the CS pin transition to the active state is detected
(VIH to VIL).
Note 1: It is recommended that while the CS pin is
active, only one type of command should
be issued. When changing commands, it
is recommended to take the CS pin
inactive, then force it back to the active
state.
2: It is also recommended that long
command strings should be broken down
into shorter command strings. This
reduces the probability of noise on the
SCK pin corrupting the desired SPI
command string.
Note 1: When data is not being received by the
MCP41HVX1, it is recommended that the
CS pin be forced to the inactive level (VIL)
2: It is also recommended that long
continuous command strings should be
broken down into single commands or
shorter continuous command strings.
This reduces the probability of noise on
the SCK pin corrupting the desired SPI
commands.
2013 Microchip Technology Inc.
DS20005207A-page 49
MCP41HVX1
7.2.1
SINGLE WRITE TO VOLATILE
MEMORY
7.2
Write Data
The Write command is a 16-bit command. The format
of the command is shown in Figure 7-2.
The write operation requires that the CS pin be in the
active state (VIL). Typically, the CS pin will be in the
inactive state (VIH) and is driven to the active state
(VIL). The 16-bit Write command (command byte and
data byte) is then clocked (SCK pin) in on the SDI pin.
Once all 16 bits have been received, the specified
volatile address is updated. A write will not occur if the
write command isn’t exactly 16 clocks pulses.
A Write command to a volatile memory location
changes that location after a properly formatted Write
command (16-clock) has been received.
Figure 6-2 and Figure 6-3 show possible waveforms
for a single write.
COMMAND BYTE
DATA BYTE
A
D
3
A
D
2
A
D
1
A
D
0
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDI
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Valid Address/Command combination
Invalid Address/Command combination (1)
SDO
Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-2:
Write Command – SDI and SDO States.
DS20005207A-page 50
2013 Microchip Technology Inc.
MCP41HVX1
7.2.2
CONTINUOUS WRITES TO
VOLATILE MEMORY
Continuous writes are possible only when writing to the
volatile memory registers (address 00h and 04h).
Figure 7-3 shows the sequence for three continuous
writes. The writes do not need to be to the same volatile
memory address.
COMMAND BYTE
DATA BYTE
A
D
3
A
D
2
A
D
1
A
D
0
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDI
1
1
1
1
1
0
1
0
1*
1
1
1
1
1
1
1
1
1
SDO
A
D
3
A
D
2
A
D
1
A
D
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1
1
1
0
1
0
1*
1
1
1
1
1
1
1
1
1
A
D
3
A
D
2
A
D
1
A
D
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1
1
1
1
1*
1
1
1
1
1
1
1
1
1
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
FIGURE 7-3:
Continuous Write Sequence.
2013 Microchip Technology Inc.
DS20005207A-page 51
MCP41HVX1
7.3.1
SINGLE READ
7.3
Read Data
The read operation requires that the CS pin be in the
active state (VIL). Typically, the CS pin will be in the
inactive state (VIH) and is driven to the active state
(VIL). The 16-bit Read command (command byte and
data byte) is then clocked (SCK pin) in on the SDI pin.
The SDO pin starts driving data on the 7th bit
(CMDERR bit) and the addressed data comes out on
the 8th through 16th clocks. Figure 6-2 through
Figure 6-3 show possible waveforms for a single read.
The Read command is a 16-bit command. The format
of the command is shown in Figure 7-4.
The first six bits of the Read command determine the
address and the command. The 7th clock will output
the CMDERR bit on the SDO pin. The 8th clock will be
fixed at 1, and the remaining 8-clocks the device will
transmit the eight data bits (D7:D0) of the specified
address (AD3:AD0).
Figure 7-4 shows the SDI and SDO information for a
Read command.
COMMAND BYTE
DATA BYTE
A
D
3
A
D
2
A
D
1
A
D
0
1
1
1
1
X
1
X
1
X
X
X
X
X
X
X
X
SDI
1
1
1
1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D Valid Address/Command combination
0
SDO
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved
Memory location
READ DATA
FIGURE 7-4:
Read Command – SDI and SDO States.
DS20005207A-page 52
2013 Microchip Technology Inc.
MCP41HVX1
Figure 7-5 shows the sequence for three continuous
reads. The reads do not need to be to the same
memory address.
7.3.2
CONTINUOUS READS
Continuous reads allow the device’s memory to be
read quickly. Continuous reads are possible to all
memory locations.
COMMAND BYTE
DATA BYTE
A
D
3
A
D
2
A
D
1
A
D
0
1
1
X
X
1
X
X
X
X
X
X
X
X
SDI
1 1 1 1 1 1 1*
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDO
A
D
3
A
D
2
A
D
1
A
D
0
1
1
X
X
1
X
X
X
X
X
X
X
X
1 1 1 1 1 1 1*
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
D
3
A
D
2
A
D
1
A
D
0
1
1
X
X
1
X
X
X
X
X
X
X
X
1 1 1 1 1 1 1*
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
FIGURE 7-5:
Continuous Read Sequence.
2013 Microchip Technology Inc.
DS20005207A-page 53
MCP41HVX1
7.4.1
SINGLE INCREMENT
7.4
Increment Wiper
Typically, the CS pin starts at the inactive state (VIH),
but may already be in the active state due to the
completion of another command.
The Increment command is an 8-bit command. The
Increment command can only be issued to specific
volatile memory locations (the Wiper register). The for-
mat of the command is shown in Figure 7-6.
Figure 6-4 through Figure 6-5 show possible
waveforms for a single increment. The increment
operation requires that the CS pin be in the active state
(VIL). Typically, the CS pin will be in the inactive state
(VIH) and is driven to the active state (VIL). The 8-bit
Increment command (command byte) is then clocked
in on the SDI pin by the SCK pins. The SDO pin drives
the CMDERR bit on the 7th clock.
An Increment command to the volatile memory location
changes that location after a properly formatted
command (8-clocks) have been received.
Increment commands provide a quick and easy
method to modify the value of the volatile wiper location
by +1 with minimal overhead.
The wiper value will increment up to FFh on 8-bit
devices and 7Fh on 7-bit devices. After the wiper value
has reached full scale (8-bit = FFh, 7-bit = 7Fh), the
wiper value will not be incremented further. See
Table 7-4 for additional information on the Increment
command versus the current volatile wiper value.
COMMAND BYTE
(INCR COMMAND (n+1))
A
D
3
A
D
2
A
D
1
A
D
0
0
1
X
X
SDI
The increment operations only require the Increment
command byte while the CS pin is active (VIL) for a
single increment.
1 1 1 1 1 1 1* 1 Note 1, 2
1 1 1 1 1 1 0 0 Note 1, 3
SDO
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions on the SCK pin do not cause
the wiper setting to change. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
Note 1: Only functions when writing the volatile
wiper register (AD3:AD0 = 0h).
2: Valid Address/Command combination.
3: Invalid Address/Command combination
all following SDO bits will be low until the
CMDERR condition is cleared (the CS
pin is forced to the inactive state).
TABLE 7-4:
INCREMENT OPERATION VS.
VOLATILE WIPER VALUE
4: If a Command Error (CMDERR) occurs
at this bit location (*), then all following
SDO bits will be driven low until the CS
pin is driven inactive (VIH).
Current Wiper
Setting
Increment
Wiper (W)
Command
Properties
7-bit
Pot
8-bit
Pot
Operates?
FIGURE 7-6:
Increment Command –
7Fh
FFh Full Scale (W = A)
No
Yes
Yes
SDI and SDO States.
7Eh
40h
FEh W = N
80h
Note:
Table 7-2 shows the valid addresses for
the Increment Wiper command. Other
addresses are invalid.
3Fh
7Fh
W = N (Mid-scale)
3Eh
01h
7Eh W = N
01h
00h
00h
Zero Scale (W = B)
DS20005207A-page 54
2013 Microchip Technology Inc.
MCP41HVX1
When executing a continuous command string, the
Increment command can be followed by any other valid
command.
7.4.2
CONTINUOUS INCREMENTS
Continuous increments are possible only when writing
to the volatile Wiper registers (address 00h).
The wiper terminal will move after the command has
been received (8th clock).
Figure 7-7 shows a continuous increment sequence.
When executing a continuous Increment command,
the selected wiper will be altered from n to n+1 for each
Increment command received. The wiper value will
increment up to FFh on 8-bit devices and 7Fh on 7-bit
devices. After the wiper value has reached full scale (8-
bit = FFh, 7-bit = 7Fh), the wiper value will not be incre-
mented further.
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions (on the SCK pin do not cause
the wiper setting to change). Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
Increment commands can be sent repeatedly without
raising CS until a desired condition is met.
COMMAND BYTE
COMMAND BYTE
(INCR COMMAND (n+2))
COMMAND BYTE
(INCR COMMAND (n+1))
(INCR COMMAND (n+3))
A
D
3
A
D
2
A
D
1
A
D
0
0
1
X
X
A
D
3
A
D
2
A
D
1
A
D
0
0
1
X
X
A
D
3
A
D
2
A
D
1
A
D
0
0
1
X
X
SDI
1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 Note 1, 2
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3, 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3, 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3, 4
SDO
Note 1: Only functions when writing the volatile wiper register (AD3:AD0 = 0h).
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-7:
Continuous Increment Command – SDI and SDO States.
2013 Microchip Technology Inc.
DS20005207A-page 55
MCP41HVX1
7.5.1
SINGLE DECREMENT
7.5
Decrement Wiper
Typically, the CS pin starts at the inactive state (VIH),
but may already be in the active state due to the
completion of another command.
The Decrement command is an 8-bit command. The
Decrement command can only be issued to volatile
Wiper locations. The format of the command is shown
in Figure 7-8.
Figure 6-4 through Figure 6-5 show possible
waveforms for a single decrement. The decrement
operation requires that the CS pin be in the active state
(VIL). Typically, the CS pin will be in the inactive state
(VIH) and is driven to the active state (VIL). Then the 8-
bit Decrement command (command byte) is clocked in
on the SDI pin by the SCK pin. The SDO pin drives the
CMDERR bit on the 7th clock.
A Decrement command to the volatile Wiper location
changes that location after a properly formatted
command (8 clocks) have been received.
Decrement commands provide a quick and easy
method to modify the value of the volatile wiper location
by -1 with minimal overhead.
The wiper value will decrement from the wiper’s full
scale value (FFh on 8-bit devices and 7Fh on 7-bit
devices). If the wiper register has a zero scale value
(00h), then the wiper value will not decrement. See
Table 7-5 for additional information on the Decrement
command vs. the current volatile wiper value.
COMMAND BYTE
(DECR COMMAND (n+1))
A
D
3
A
D
2
A
D
1
A
D
0
1
0
X
X
SDI
The Decrement commands only require the Decrement
1 1 1 1 1 1 1* 1 Note 1, 2
1 1 1 1 1 1 0 0 Note 1, 3
command byte, while the CS pin is active (VILor VIHH
)
SDO
for a single decrement.
After the wiper is decremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions on the SCK pin do not cause
the wiper setting to change. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired decrement occurs.
Note 1: Only functions when writing the volatile
wiper registers (AD3:AD0 = 0h).
2: Valid Address/Command combination.
3: Invalid Address/Command combination,
all following SDO bits will be low until the
CMDERR condition is cleared.
(the CS pin is forced to the inactive
state).
TABLE 7-5:
DECREMENT OPERATION VS.
VOLATILE WIPER VALUE
4: If a Command Error (CMDERR) occurs
at this bit location (*), then all following
SDO bits will be driven low until the CS
pin is driven inactive (VIH).
Current Wiper
Setting
Decrement
Wiper (W)
Command
Properties
7-bit
Pot
8-bit
Pot
Operates?
FIGURE 7-8:
SDI and SDO States.
Decrement Command –
7Fh
FFh Full Scale (W = A)
Yes
Yes
No
7Eh
40h
FEh W = N
80h
Note:
Table 7-2 shows the valid addresses for
the Decrement Wiper command. Other
addresses are invalid.
3Fh
7Fh
W = N (Mid-scale)
3Eh
01h
7Eh W = N
01h
00h
00h
Zero Scale (W = B)
DS20005207A-page 56
2013 Microchip Technology Inc.
MCP41HVX1
When executing a continuous command string, the
Decrement command can be followed by any other
valid command.
7.5.2
CONTINUOUS DECREMENTS
Continuous decrements are possible only when writing
to the volatile Wiper register (address 00h).
The wiper terminal will move after the command has
been received (8th clock).
Figure 7-9 shows a continuous decrement sequence.
When executing continuous Decrement commands,
the selected wiper will be altered from n to n-1 for each
Decrement command received. The wiper value will
decrement from the wiper’s full scale value (FFh on 8-
bit devices and 7Fh on 7-bit devices). If the Wiper
register has a zero scale value (00h), then the wiper
value will not decrement. See Table 7-5 for additional
information on the Decrement command vs. the current
volatile wiper value.
After the wiper is decremented to the desired position,
the CS pin should be forced to VIH to ensure that
“unexpected” transitions (on the SCK pin do not cause
the wiper setting to change). Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired decrement occurs.
Decrement commands can be sent repeatedly without
raising CS until a desired condition is met.
COMMAND BYTE
COMMAND BYTE
(DECR COMMAND (n-1))
COMMAND BYTE
(DECR COMMAND (n-1))
(DECR COMMAND (n-1))
A
D
3
A
D
2
A
D
1
A
D
0
1
0
X
X
A
D
3
A
D
2
A
D
1
A
D
0
1
0
X
X
A
D
3
A
D
2
A
D
1
A
D
0
1
0
X
X
SDI
1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 Note 1, 2
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3, 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3, 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3, 4
SDO
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0 = 0h).
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-9:
Continuous Decrement Command – SDI and SDO States.
2013 Microchip Technology Inc.
DS20005207A-page 57
MCP41HVX1
NOTES:
DS20005207A-page 58
2013 Microchip Technology Inc.
MCP41HVX1
8.0
APPLICATIONS EXAMPLES
3.0V
Voltage
Digital potentiometers have a multitude of practical
uses in modern electronic circuits. The most popular
uses include precision calibration of set point
thresholds, sensor trimming, LCD bias trimming, audio
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming.
Regulator
2.0V (1.8V min)
PIC® MCU
MCP41HVX1
SDI
SDO
CS
SCK
SDO
CS
SCK
SDI
WLAT
SHDN
I/O
I/O
8.1
Split Rail Applications
Split rail applications are when one device operates
from one voltage level (rail) and the second device
operates from a second voltage level (rail). The typical
scenario will be when the microcontroller is operating at
a lower voltage level (for power savings, etc) and the
MCP41HVX1 is operating at a higher voltage level to
maximize operational performance. This configuration
is shown in Figure 8-1.
FIGURE 8-1:
Example Split Rail System.
TABLE 8-1:
MCP41HVX1 VL VOLTAGE
BASED ON
MICROCONTROLLER VOH
PIC® MCU
VOH (minimum) ( 1)
MCP41HVX1
Max VL
VDD
(minimum)
To ensure that communication properly occurs
between the devices, care must be done to verify the
compatibility of the VIL, VIH, VOL, VOH levels of the
interface signals between the devices. These interface
signals are:
Formula
Calculated
(with load)
0.7 * VDD
1.26V
1.44V
1.53V
1.62V
1.8V
2.8V
3.2V
3.4V
3.6V
4.0V
2.44V
4.2V
4.8V
5.4V
5.5V
0.8 * VDD
0.85 * VDD
0.9 * VDD
VDD
• CS
• SCK
• SDI
• SDO
• SHDN
• WLAT
1.8V
VDD - 0.7V
0.7 * VDD
0.8 * VDD
0.9 * VDD
VDD
1.1V
1.89V
2.16V
2.43V
2.7V
When the microcontroller is at a lower voltage rail, the
VOH of the microcontroller needs to be greater than the
VIH of the MCP41HVX1, and the VIL of the microcon-
troller needs to be greater than the VOL of the
MCP41HVX1.
2.7V
Note 1: The VOH minimum voltage is determined
by the load on the pin. If the load is small,
a typical output’s voltage should approach
the device’s VDD voltage. This is depen-
dent on the device’s output driver design.
Table 8-1
MCP41HVX1 VL based on the microcontroller’s
minimum VOH
shows
the
calculated
maximum
.
Note:
VOH specifications typically have a current
load specified. This is due to the pin
expected to drive externally circuitry. If the
pin is unloaded (or lightly loaded), then the
VOH of the pin could approach the device
2: Split Rail voltages are dependent on VIL,
VIH, VOL, and VOH of the microcontroller
and the MCP41HVX1 devices.
V
DD (this is dependent on the implementa-
tion of the output driver circuit). For VOL
unloaded (or lightly loaded) pins could
approach the device VSS
,
.
For VOH and VOL characterization graphs
from an example microcontroller, see the
PIC16F1934 data sheet (DS41364), Fig-
ure 31-15 and Figure 31-16.
FIGURE 8-2:
Example PIC®
Microcontroller VOH Characterization Graph
(VDD = 1.8V).
2013 Microchip Technology Inc.
DS20005207A-page 59
MCP41HVX1
8.2
Using Shutdown Modes
8.3
High-Voltage DAC
Figure 8-3 shows a possible application circuit where
the independent terminals could be used.
Disconnecting the wiper allows the transistor input to
be taken to the bias voltage level (disconnecting A and
or B may be desired to reduce system current).
Disconnecting Terminal A modifies the transistor input
by the RBW rheostat value to the Common B.
Disconnecting Terminal B modifies the transistor input
by the RAW rheostat value to the Common A. The
Common A and Common B connections could be
connected to V+ and V-.
A high-voltage DAC can be implemented using the
MCP41HVXX, with voltages as high as 36V. The circuit
is shown in Figure 8-4. The equation to calculate the
voltage output is shown in Figure 8-1.
V+
High Voltage DAC
V+
VD
MCP41HVXX
A
+
OPA170
-
D1
Common A
B
R1
R2
Input
V+
+
A
OPA170
-
VOUT
To base
of Transistor
W
FIGURE 8-4:
High Voltage DAC.
(or Amplifier)
EQUATION 8-1:
DAC OUTPUT VOLTAGE
CALCULATION
8-bit
N
R1
R2
B
V
OUT(N) =
x ( VD x ( 1 +
) )
255
N = 0 to 255 (decimal)
Input
7-bit
VOUT(N) =
Common B
N
127
R1
R2
x ( VD x ( 1 +
) )
Balance
FIGURE 8-3:
Bias
N = 0 to 127 (decimal)
Example Application Circuit
using Terminal Disconnects.
DS20005207A-page 60
2013 Microchip Technology Inc.
MCP41HVX1
8.4
Variable Gain Instrumentation
Amplifier
8.5
Audio Volume Control
A digital volume control can be implemented with the
MCP41HVXX. Figure 8-6 shows a simple audio
volume control implementation.
A variable gain instrumentation amplifier can be
implemented using the MCP41HVXX along with a high
voltage dual analog switch and a high voltage
instrumentation amplifier.
Figure 8-7 shows a circuit-referenced voltage detect
circuit. The output of this circuit could be used to control
the Wiper Latch of the MCP41HVXX device in the
Audio Volume control circuit to reduce zipper noise or
to update the different channels at the same time.
Figure 8-4. The equation to calculate the voltage output
is shown in Figure 8-1.
The op amp (U1) could be an MCP6001, while the gen-
eral purpose comparators (U2 and U3) could be an
MCP6541. U4 is a simple AND gate.
ADG1207
S1A
V+
DA
B
A
U1 establishes the signal zero reference. The upper
limit of the comparator is set above its offset. The WLAT
pin is forced high whenever the voltage falls between
2.502V and 2.497V (a 0.005V window).
S8A
S1B
W
AD8221
VOUT
DB
S8B
The capacitor C1 AC couples the VIN signal into the cir-
cuit, before feeding into the windowed comparator (and
MCP41HVXX Terminal A pin).
FIGURE 8-5:
Instrumentation Amplifier for Data Acquisition
System.
Variable Gain
V+
EQUATION 8-2:
DAC OUTPUT VOLTAGE
CALCULATION
MCP41HVXX
A
VIN
V+
V-
8-bit
VL
GND
49.4 k
+
-
Gain(N) = 1 +
(N / 255) x RAB
VOUT
SDI
SCK
WLAT
N = 0 to 255 (decimal)
B
7-bit
Gain(N) = 1 +
49.4 k
(N / 127) x RAB
V-
FIGURE 8-6:
Audio Volume Control.
N = 0 to 127 (decimal)
+5V
VIN
R3
+5V
100 k
C1
+
1 µF
U2
R4
-
200 k
R1
90 k
WLAT
U4
+5V
R2
+
10 k
+5V
U3
-
+
-
U1
R5
100 k
FIGURE 8-7:
Referenced Voltage
Crossing Detect.
2013 Microchip Technology Inc.
DS20005207A-page 61
MCP41HVX1
8.6
Programmable Power Supply
8.7
Programmable Bidirectional
Current Source
The ADP1611 is a step-up DC-to-DC switching con-
verter. Using the MCP41HVXX device allows the power
supply to be programmable up to 20V. Figure 8-7
shows a programmable power supply implementation.
A programmable bidirectional current source can be
implemented with the MCP41HVXX. Figure 8-9 shows
an implementation where U1 and U2 work together to
deliver the desired current (dependent on selected
device) in both directions. The circuit is symmetrical
(R1A = R1B, R2A = R2B, R3A = R3B) in order to improve
stability. If the resistors are matched, the load current
(IL) calculation is shown below:
Equation 8-3 shows the equation to calculate the
output voltage of the programmable power supply. This
output is derived from the RBW resistance of the
MCP41HVXX device and the R2 resistor. The
ADP1611 will adjust its output voltage to maintain
1.23V on the FB pin.
EQUATION 8-4:
(R2A + R3A
LOAD CURRENT (IL)
When power is connected, L1 acts as a short, and
VOUT is a diode drop below the +5V voltage. The VOUT
voltage will ramp to the programmed value.
)
IL =
x VW
R1A * R3A
R1B
R2B
MCP41HVXX
+5V
(100 k)
C2
10 µF
V+
A
150 k
15 k
W
L1
4.7 µF
C2
ADP1611
C1
0.1 µF
IN
RT
B
D1
10 pF
+15V
R3B
50 k
FB SW
R1
8.5 k
-
SS
COMP
U2
VOUT
+
C3
22 nF
R2
-15V
C5
10 µF
220 k
C4
150 pF
C1
R3A
V+
50 k
A
FIGURE 8-8:
Supply.
Programmable Power
+15V
-15V
10 pF
R1A
W
R2A
+
U1
-
VL
IL
EQUATION 8-3:
POWER SUPPLY OUTPUT
VOLTAGE
CALCULATION
14.95 k
R4
500
150 k
B
V-
8-bit
N * RAB
255
R2
FIGURE 8-9:
Current Source.
Programmable Bidirectional
VOUT(N) = 1.23V x ( 1 + (
N = 0 to 255 (decimal)
7-bit
) )
N * RAB
127
R2
VOUT(N) = 1.23V x ( 1 + (
N = 0 to 127 (decimal)
) )
DS20005207A-page 62
2013 Microchip Technology Inc.
MCP41HVX1
8.8
LCD Contrast Control
8.9
Serial Interface Communication
Times
The MCP41HVXX can be used for LCD contrast
control. Figure 8-10 shows a simple programmable
LCD contrast control implementation.
Table 8-2 shows the time for each SPI serial interface
command as well as the effective data update rate that
can be supported by the digital interface (based on the
two SPI serial interface frequencies). So, the Serial
Interface performance, along with the wiper response
time, would be used to determine your application’s
volatile Wiper register update rate.
Some LCD panels support a fixed power supply of up
to 28V. The high voltage digital potentiometer's wiper
can support contrast adjustments through the entire
voltage range.
LCD Panel
Fixed
D1
VOUT (LCD Bias)
(up to +28V)
C1
10 µF
A
B
uController
W
+16V to +26V
Contrast Adj.
SDO
SCK
CS
FIGURE 8-10:
Programmable Contrast
Control.
TABLE 8-2:
SERIAL INTERFACE TIMES / FREQUENCIES
Example
Command
Time (µs)
Effective Data Update
Frequency (kHz) (2)
# of Serial
# Bytes
# of Serial
Command
Interface bits Transferred Interface bits
1MHz
10MHz
1MHz
62,500
12,500
62,500
12,500
10MHz
625,000
125,000
625,000
125,000
Write Single Byte
16
N * 16
16
1
5
1
5
1
5
1
5
16
80
16
80
8
16
80
16
80
8
1.6
8
Write Continuous Bytes
Read Byte
1.6
8
Read Continuous Bytes
Increment Wiper
N * 16
8
0.8
4
125,000 1,250,000
25,000 250,000
125,000 1,250,000
25,000 250,000
Continuous Increments
Decrement Wiper
N * 8
8
40
8
40
8
0.8
4
Continuous Decrements
N * 8
40
40
Note 1: Includes the Start or Stop bits.
2: This is the command frequency multiplied by the number of bytes transferred.
2013 Microchip Technology Inc.
DS20005207A-page 63
MCP41HVX1
8.10.2
LAYOUT CONSIDERATIONS
8.10 Design Considerations
In the design of a system with the MCP41HVX1
devices, the following layout considerations should be
taken into account:
In the design of a system with the MCP41HVX1
devices, the following considerations should be taken
into account:
• Noise
• Power Supply Considerations
• Layout Considerations
• PCB Area Requirements
• Power Dissipation
8.10.1
POWER SUPPLY
CONSIDERATIONS
8.10.2.1
Noise
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP41HVX1’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply’s traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-11 illustrates an
appropriate bypass strategy.
boards utilizing
a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the
silicon is capable of providing. Particularly harsh
environments may require shielding of critical signals.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VL) as
possible.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V+ and V-
should reside on the analog plane.
8.10.2.2
PCB Area Requirements
In some applications, PCB area is a criteria for device
selection. Table 8-3 shows the package dimensions
and area for the different package options. The table
also shows the relative area factor compared to the
smallest area. For space critical applications, the QFN
package would be the suggested package.
VDD
0.1 µF
VL
V+
TABLE 8-3:
Package
PACKAGE FOOTPRINT ( 1)
Package Footprint
0.1 µF
V-
0.1 µF
Dimensions
(mm)
Type
Code
X
Y
SDI
SDO
SCK
A
14 TSSOP
20 QFN
ST
5.10 6.40 32.64 1.31
5.00 5.00 25.00
W
MQ
1
Note 1: Does not include recommended land
pattern dimensions.
CS
B
DGND V-
VSS
FIGURE 8-11:
Typical Microcontroller
Connections.
DS20005207A-page 64
2013 Microchip Technology Inc.
MCP41HVX1
8.10.3
RESISTOR TEMPCO
TABLE 8-4:
Typical
RAB POWER DISSIPATION
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in the device character-
ization graphs.
RAB Resistance ()
| VA | + |VB | Power
=
(mW)
(V)
( 1)
Min
Max
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end-to-end change in RAB resistance.
5,000
4,000
8,000
6,000
36
36
36
36
324
162
10,000
50,000
12,000
40,000 60,000
32.4
16.2
100,000 80,000 120,000
8.10.3.1
Power Dissipation
Note 1: Power = V * I = V2 / RAB(MIN)
.
The power dissipation of the high-voltage digital poten-
tiometer will most likely be determined by the power
dissipation through the resistor networks.
TABLE 8-5: BW POWER DISSIPATION
R
RAB () | VW | + |VB | = IBW ( 2)
Power
(mA)
Table 8-4 shows the power dissipation through the
resistor ladder (RAB) when Terminal A = +18V and
Terminal B = -18V. This is not the worst case power
dissipation based on the 25 mA terminal current
specification. Table 8-4 show the worst case current
(per resistor network), which is independent of the RAB
value).
(Typical)
(V)
(mW) ( 1)
5,000
36
36
36
36
25
12.5
6.5
900
450
234
234
10,000
50,000
100,000
6.5
Note 1: Power = V * I.
2: See Electrical Specifications (max IW).
2013 Microchip Technology Inc.
DS20005207A-page 65
MCP41HVX1
NOTES:
DS20005207A-page 66
2013 Microchip Technology Inc.
MCP41HVX1
9.2
Custom Options
9.0
DEVICE OPTIONS
Custom options can be made available.
9.1
Standard Options
9.2.1
CUSTOM WIPER VALUE ON POR/
BOR EVENT
9.1.1
POR/BOR WIPER SETTING
The default wiper setting (mid-scale) is indicated by the
customer in three digit suffix: -202, -502, -103 and -503.
Table 9-1 indicates the device’s default settings.
Customers can specify a custom wiper setting via the
NSCAR process.
Note 1: Non-Recurring
Engineering
(NRE)
TABLE 9-1:
DEFAULT POR/BOR WIPER
SETTING SELECTION
charges and minimum ordering require-
ments for custom orders. Please contact
Microchipsales for additional information.
Typical
RAB
Value
Default
POR Wiper
Setting
Device
Wiper
2: A custom device will be assigned custom
Resolution Code
device marking.
5.0 k -502
10.0 k -103
50.0 k -503
100.0 k -104
Mid-scale
Mid-scale
Mid-scale
Mid-scale
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
8-bit
7-bit
7Fh
3Fh
7Fh
3Fh
7Fh
3Fh
7Fh
3Fh
2013 Microchip Technology Inc.
DS20005207A-page 67
MCP41HVX1
NOTES:
DS20005207A-page 68
2013 Microchip Technology Inc.
MCP41HVX1
10.2 Technical Documentation
10.0 DEVELOPMENT SUPPORT
10.1 Development Tools
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 10-2 shows
some of these documents.
Several development tools are available to assist in
your design and evaluation of the MCP41HVX1
devices. The currently available tools are shown in
Table 10-1.
Figure 10-1 shows how the TSSOP20EV bond-out
PCB can be populated to easily evaluate the
MCP41HVX1 devices. Evaluation can use the PICkit™
Serial Analyzer to control the position of the volatile
Wiper and state of the TCON register.
Figure 10-2 shows how the SOIC14EV bond-out PCB
can be populated to evaluate the MCP41HVX1
devices. The use of the PICkit Serial Analyzer would
require blue wire since the header H1 is not compatibly
connected.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
TABLE 10-1: DEVELOPMENT TOOLS
Board Name
Part #
Comment
20-pin TSSOP and SSOP Evaluation Board
TSSOP20EV
Can easily interface to PICkit Serial Analyzer
(Order #: DV164122)
14-pin SOIC/TSSOP/DIP Evaluation Board
SOIC14EV
TABLE 10-2: TECHNICAL DOCUMENTATION
Application
Title
Literature #
Note Number
TB3073
AN1316
AN1080
AN737
AN692
AN691
AN219
—
Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer
Using Digital Potentiometers for Programmable Amplifier Gain
Understanding Digital Potentiometers Resistor Variations
Using Digital Potentiometers to Design Low-Pass Adjustable Filters
Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect
Optimizing the Digital Potentiometer in Precision Circuits
Comparing Digital Potentiometers to Mechanical Potentiometers
Digital Potentiometer Design Guide
DS93073
DS01316
DS01080
DS00737
DS00692
DS00691
DS00219
DS22017
DS21825
DS01005
—
Signal Chain Design Guide
—
Analog Solutions for Automotive Applications Design Guide
2013 Microchip Technology Inc.
DS20005207A-page 69
MCP41HVX1
MCP41HVx1-xxxE/ST
installed in U3 (bottom 14 pins of TSSOP-20 footprint)
Connected to
Digital Ground
(DGND) Plane
Connected to
Digital Power (VL) Plane
1.0 µF
0
V+
VL
SCK
CS
P0A pin shorted
(jumpered) to
V+ pin
P0A
P0W
Through-hole Test
Point (Orange)
Wiper 0
P0B
V-
SDI
0
P0B pin shorted
(jumpered) to
V- pin
SDO
DGND
NC
WLAT
SHDN
0
0
0
Four blue wire jumpers to connect
PICkit™ Serial interface (SPI) to device pins
1x6 male header, with 90° right angle
FIGURE 10-1:
Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV.
DS20005207A-page 70
2013 Microchip Technology Inc.
MCP41HVX1
1.0 µF
FIGURE 10-2:
Digital Potentiometer Evaluation Board Circuit Using SOIC14EV.
2013 Microchip Technology Inc.
DS20005207A-page 71
MCP41HVX1
NOTES:
DS20005207A-page 72
2013 Microchip Technology Inc.
MCP41HVX1
11.0 PACKAGING INFORMATION
11.1 Package Marking Information
Example
14-Lead TSSOP (4.4 mm)
XXXXXXXX
YYWW
41H51502
E320
NNN
256
Part Number
Code
Part Number
Code
MCP41HV51-502E/ST
MCP41HV51-103E/ST
MCP41HV51-503E/ST
MCP41HV51-104E/ST
41H51502
41H51103
41H51503
41H51104
MCP41HV31-502E/ST 41H31502
MCP41HV31-103E/ST 41H31103
MCP41HV31-503E/ST 41H31503
MCP41HV31-104E/ST 41H31104
20-Lead QFN (5x5x0.9 mm)
Example
PIN 1
PIN 1
41HV31
502E/MQ
e
3
1320256
Part Number
Code
Part Number
Code
MCP41HV51-502E/MQ 502E/MQ MCP41HV31-502E/MQ 502E/MQ
MCP41HV51-103E/MQ 103E/MQ MCP41HV31-103E/MQ 103E/MQ
MCP41HV51-503E/MQ 503E/MQ MCP41HV31-503E/MQ 503E/MQ
MCP41HV51-104E/MQ 104E/MQ MCP41HV31-104E/MQ 104E/MQ
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
RoHS Compliant JEDEC designator for Matte Tin (Sn)
This package is RoHS Compliant. The RoHS Compliant
e
3
*
JEDEC designator ( ) can be found on the outer packaging
e
3
for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2013 Microchip Technology Inc.
DS20005207A-page 73
MCP41HVX1
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005207A-page 74
2013 Microchip Technology Inc.
MCP41HVX1
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc.
DS20005207A-page 75
MCP41HVX1
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005207A-page 76
2013 Microchip Technology Inc.
MCP41HVX1
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ꢕꢄꢍꢊꢌꢍꢎꢄꢒ ꢗꢉꢍꢎꢅꢌꢈꢌꢐꢋ ꢑꢊꢇ*ꢄꢅꢐ <ꢚꢖꢝꢁꢏO;
2013 Microchip Technology Inc.
DS20005207A-page 77
MCP41HVX1
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DS20005207A-page 78
2013 Microchip Technology Inc.
MCP41HVX1
APPENDIX A: REVISION HISTORY
APPENDIX B: TERMINOLOGY
This appendix discusses the terminology used in this
document as well as describes how a parameter is
measured.
Revision A (May 2013)
• Original Release of this Document.
B.1
Potentiometer (Voltage Divider)
The potentiometer configuration is when all three
terminals of the device are tied to different nodes in the
circuit. This allows the potentiometer to output a
voltage proportional to the input voltage. This
configuration is sometimes called voltage divider
mode. The potentiometer is used to provide a variable
voltage by adjusting the wiper position between the two
endpoints as shown in Figure B-1. Reversing the
polarity of the A and B terminals will not affect
operation.
V1
A
V3
W
B
V2
FIGURE B-1:
POTENTIOMETER
CONFIGURATION.
The temperature coefficient of the RAB resistors is
minimal by design. In this configuration, the resistors all
change uniformly, so minimal variation should be seen.
B.2
Rheostat (Variable Resistor)
The rheostat configuration is when two of the three dig-
ital potentiometer’s terminals are used as a resistive
element in the circuit. With terminal W (wiper) and
either terminal A or terminal B, a variable resistor is
created. The resistance will depend on the tap setting
of the wiper (and the wiper’s resistance). The
resistance is controlled by changing the wiper setting.
Figure B-2 shows the two possible resistors that can be
used. Reversing the polarity of the A and B terminals
will not affect operation.
A
RAW or
Resistor
RBW
W
B
FIGURE B-2:
RHEOSTAT
CONFIGURATION.
2013 Microchip Technology Inc.
DS20005207A-page 79
MCP41HVX1
EQUATION B-2:
RW CALCULATION
B.3
Resolution
(VW - VA)
IWB
The resolution is the number of Wiper output states that
divide the full-scale range. For the 8-bit digital
potentiometer, the resolution is 28, meaning the digital
potentiometer Wiper code ranges from 0 to 255.
RW(Measured)
=
where:
VA = Voltage on Terminal A pin
VW = Voltage on Terminal W pin
IWB = Measured current through W and B pins
B.4
Step Resistance (R )
S
The resistance Step size (RS) equates to one LSb of
the resistor ladder. Equation B-1 shows the calculation
for the step resistance (RS).
The wiper resistance in potentiometer-generated
voltage divider applications is not a significant source
of error (it does not effect the output voltage seen on
the W pin).
EQUATION B-1:
Ideal
RS CALCULATION
The wiper resistance in rheostat applications can
create significant nonlinearity as the wiper is moved
toward zero scale (00h). The lower the nominal
resistance, the greater the possible error.
RAB
2N -1
(VA - VB) / IAB
2N -1
RS(Ideal)
=
or
Measured
RS(Measured)
B.6
R
Resistance
ZS
(VW(@FS) - VW(@ZS)) / IAB
2N - 1
=
The analog switch between the resistor ladder and the
Terminal B pin introduces a resistance, which we call
the Zero-Scale resistance (RZS). Equation B-3 shows
how to calculate this resistance.
where:
2N - 1 = 255 (MCP41HV51/61)
= 127 (MCP41HV31/41)
VA = Voltage on Terminal A pin
VB = Voltage on Terminal B pin
EQUATION B-3:
RZS CALCULATION
IAB = Measured Current through A and B pins
VW(@FS) = Measured Voltage on W pin at
Full-Scale code (FFh or 7Fh)
VW(@ZS) = Measured Voltage on W pin at
(VW(@ZS) - VB)
IAB
RZS(Measured)
=
where:
VW(@ZS) = Voltage on Terminal W pin
Zero-Scale code (00h)
at Zero-Scale wiper code
VB = Voltage on Terminal B pin
IWB = Measured Current through A and B pins
B.5
Wiper Resistance
Wiper resistance is the series resistance of the analog
switch that connects the selected resistor ladder node
to the Wiper Terminal common signal (see Figure 5-1).
B.7
R
Resistance
FS
The analog switch between the resistor ladder and the
Terminal A pin introduces a resistance, which we call
the Full-Scale resistance (RFS). Equation B-4 shows
how to calculate this resistance.
A value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The resistance is dependent on the voltages on the
analog switch source, gate, and drain nodes, as well as
the device’s wiper code, temperature, and the current
through the switch. As the device voltage decreases,
the wiper resistance increases.
EQUATION B-4:
RFS CALCULATION
(VA - VW(@FS)
IAB
)
RFS(Measured)
=
where:
The wiper resistance is measured by forcing a current
through the W and B terminals (IWB) and measuring the
voltage on the W and A terminals (VW and VA).
Equation B-2 shows how to calculate this resistance.
VA = Voltage on Terminal A pin
VW(@FS) = Voltage on Terminal W pin
at Full-Scale wiper code
IWB = Measured Current through A and B pins
B.8
Least Significant Bit (LSb)
This is the difference between two successive codes
(either in resistance or voltage). For a given output
range it is divided by the resolution of the device
(Equation B-5).
DS20005207A-page 80
2013 Microchip Technology Inc.
MCP41HVX1
EQUATION B-5:
Ideal
LSb CALCULATION
B.9
Monotonic Operation
Monotonic operation means that the device’s output
(resistance (RBW) or voltage (VW)) increases with
every one code step (LSb) increment of the wiper
register.
In Resistance
In Voltage
VA - VB
RAB
LSb(Ideal) =
2N -1
2N - 1
VS64
Measured
0x40
0x3F
LSb(Measured) =
VS63
(VW(@FS) - VW(@ZS)) / IAB
2N - 1
0x3E
VW(@FS) - VW(@ZS)
2N - 1
VS3
0x03
where:
2N - 1 = 255 (MCP41HV51/61)
VS1
0x02
= 127 (MCP41HV31/41)
VS0
VA = Voltage on Terminal A pin
VB = Voltage on Terminal B pin
0x01
VAB = Measured Voltage between A and B pins
IAB = Measured Current through A and B pins
0x00
VW (@ tap)
n = ?
VW(@FS) = Measured Voltage on W pin at
VW
=
VSn + VZS(@ Tap 0)
n = 0
Full-Scale code (FFh or 7Fh)
VW(@ZS) = Measured Voltage on W pin at
Zero-Scale code (00h)
Voltage (VW ~= VOUT
)
FIGURE B-3:
THEORETICAL VW
OUTPUT VS CODE (MONOTONIC
OPERATION).
RS63
0x3F
0x3E
0x3D
RS62
RS3
0x03
RS1
0x02
RS0
0x01
0x00
RW
n = ?
(@ tap)
RBW
=
RSn + RW(@ Tap n)
n = 0
Resistance (RBW
)
FIGURE B-4:
THEORETICAL RBW
OUTPUT VS CODE (MONOTONIC
OPERATION).
2013 Microchip Technology Inc.
DS20005207A-page 81
MCP41HVX1
B.10 Full-Scale Error (E )
B.11 Zero-Scale Error (E )
FS
ZS
The Full-Scale Error (see Figure B-5) is the error of
the VW pin relative to the expected VW voltage
(theoretical) for the maximum device Wiper register
code (code FFh for 8-bit and code 7Fh for 7-bit), see
Equation B-6. The error is dependent on the resistive
load on the VOUT pin (and where that load is tied to,
such as VSS or VDD). For loads (to VSS) greater than
specified, the full scale error will be greater.
The Zero-Scale Error (see Figure B-6) is the difference
between the ideal and measured VOUT voltage with the
Wiper register code equal to 00h (Equation B-7). The
error is dependent on the resistive load on the VOUT pin
(and where that load is tied to, such as VSS or VDD). For
loads (to VDD) greater than specified, the zero scale
error will be greater.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
Note:
Analog switch leakage increases with tem-
perature. This leakage increase substan-
tially at higher temperatures (> ~100°C).
As analog switch leakage increases the
Zero-Scale output value decreases, which
decreases the Zero-Scale Error.
Note:
Analog switch leakage increases with tem-
perature. This leakage increase substan-
tially at higher temperatures (> ~100°C).
As analog switch leakage increases, the
Full-Scale output value decreases, which
increases the Full-Scale Error.
EQUATION B-7:
ZERO SCALE ERROR
EQUATION B-6:
FULL-SCALE ERROR
V
W@ZS)
E
=
ZS
V
- V
A
W(@FS)
V
LSb(IDEAL)
E
=
FS
V
LSb(IDEAL)
Where:
E
is expressed in LSb
Where:
FS
E
is expressed in LSb
V
is the V voltage when the Wiper
FS
W@ZS)
W
register code is at Zero-scale.
V
is the V voltage when the Wiper
W@FS)
W
register code is at Full-scale.
V
is the theoretical voltage step size.
LSb(IDEAL)
V
V
is the ideal output voltage when the
Wiper register code is at Full-scale.
IDEAL(@FS)
is the theoretical voltage step size.
LSb(IDEAL)
V
A
V
FS
Actual
Transfer
Function
V
A
V
FS
Actual
Transfer
Function
Ideal Transfer
Function
Full-Scale
Error (E
V
V
)
ZS
FS
B
0
Full-Scale
Zero-Scale
Error (E
Ideal Transfer
Function
Wiper Code
)
ZS
V
ZS
V
FIGURE B-6:
EXAMPLE.
ZERO-SCALE ERROR
B
0
Full-Scale
Wiper Code
FIGURE B-5:
EXAMPLE.
FULL-SCALE ERROR
DS20005207A-page 82
2013 Microchip Technology Inc.
MCP41HVX1
B.12 Integral Non-linearity (P-INL)
Potentiometer Configuration
B.13 Differential Nonlinearity (P-DNL)
Potentiometer Configuration
The Potentiometer Integral nonlinearity (P-INL) error is
the maximum deviation of an actual VW transfer
function from an ideal transfer function (straight line).
The Potentiometer Differential nonlinearity (P-DNL)
error (see Figure B-8) is the measure of VW step size
between codes. The ideal step size between codes is
1 LSb. A P-DNL error of zero would imply that every
code is exactly 1 LSb wide. If the P-DNL error is less
than 1 LSb, the Digital Potentiometer guarantees
monotonic output and no missing codes. The P-DNL
error between any two adjacent codes is calculated in
Equation B-9.
In the MCP41HVX1, P-INL is calculated using the
Zero-Scale and Full-Scale wiper code end points. P-
INL is expressed in LSb. P-INL is also called relative
accuracy. Equation B-8 shows how to calculate the P-
INL error in LSb and Figure B-7 shows an example of
P-INL accuracy.
P-DNL error is the measure of variations in code widths
from the ideal code width.
Positive P-INL means higher VW voltage than ideal.
Negative P-INL means lower VW voltage than ideal.
Note:
Analog switch leakage increases with tem-
perature. This leakage increase substan-
tially at higher temperatures (> ~100°C).
As analog switch leakage increases, the
Wiper output voltage (VW) decreases,
which effects the DNL Error.
Note:
Analog switch leakage increases with tem-
perature. This leakage increase substan-
tially at higher temperatures (> ~100°C).
As analog switch leakage increases, the
Wiper output voltage (VW) decreases,
which effects the INL Error.
EQUATION B-9:
P-DNL ERROR
EQUATION B-8:
P-INL ERROR
( VW(code = n+1) - VW(code = n) ) - VLSb(Measured)
)
( VW(@Code) - ( VLSb(Measured) * Code ))
EDNL
=
EINL
=
VLSb(Measured)
VLSb(Measured)
Where:
Where:
INL is expressed in LSb.
DNL is expressed in LSb.
= Wiper Register Value
Code
VW(Code = n) = The measured VW output
voltage with a given Wiper
register code.
= The measured VW output
voltage with a given Wiper
register code
VW(@Code)
VLSb = For Ideal:
VAB / Resolution
= For Ideal:
VLSb
VAB / Resolution
For Measured:
(VW(@FS) - VW(@ZS)) / 255
For Measured:
(VW(@FS) - VW(@ZS)) / # of RS
INL < 0
111
111
110
101
Actual
transfer
function
110
Actual
transfer
101
function
100
Wiper
Code
Ideal transfer
function
100
011
010
001
000
Wiper
Code
011
010
001
000
Ideal transfer
function
Wide code, > 1 LSb
Narrow code < 1 LSb
INL < 0
VW Output Voltage
P-DNL ACCURACY.
VW Output Voltage
FIGURE B-8:
FIGURE B-7:
P-INL ACCURACY.
2013 Microchip Technology Inc.
DS20005207A-page 83
MCP41HVX1
B.14 Integral Non-linearity (R-INL)
Rheostat Configuration
B.15 Differential Nonlinearity (R-DNL)
Rheostat Configuration
The Rheostat Integral nonlinearity (R-INL) error is the
maximum deviation of an actual RBW transfer function
from an ideal transfer function (straight line).
The Rheostat Differential nonlinearity (R-DNL) error
(see Figure B-10) is the measure of RBW step size
between codes in actual transfer function. The ideal
step size between codes is 1 LSb. A R-DNL error of
zero would imply that every code is exactly 1 LSb wide.
If the R-DNL error is less than 1 LSb, the RBW Resis-
tance guarantees monotonic output and no missing
codes. The R-DNL error between any two adjacent
codes is calculated in Equation B-11.
In the MCP41HVX1, INL is calculated using the Zero-
Scale and Full-Scale wiper code end points. R-INL is
expressed in LSb. R-INL is also called relative
accuracy. Equation B-10 shows how to calculate the R-
INL error in LSb and Figure B-9 shows an example of
R-INL accuracy.
R-DNL error is the measure of variations in code widths
from the ideal code width. A R-DNL error of zero would
imply that every code is exactly 1 LSb wide.
Positive R-INL means higher VOUT voltage than ideal.
Negative R-INL means lower VOUT voltage than ideal.
EQUATION B-10: R-INL ERROR
EQUATION B-11: R-DNL ERROR
( RBW(@code) - RBW(Ideal)
)
EINL
=
EDNL
( VOUT(code = n+1) - VOUT(code = n) ) - VLSb(Measured)
VLSb(Measured)
=
RLSb(Ideal)
)
Where:
INL is expressed in LSb.
Where:
DNL is expressed in LSb.
= The measured RBW resistance
with a given wiper register code
RBW(Code = n)
= For Ideal:
RLSb
= The measured RBW resistance
RBW(Code = n)
RAB / Resolution
For Measured:
RBW(@FS) / # of RS
with a given wiper register code
RLSb = For Ideal:
RAB / Resolution
For Measured:
RBW(@FS) / # of RS
INL < 0
111
110
101
Actual
transfer
function
111
110
Actual
transfer
function
100
011
010
001
000
Wiper
Code
101
100
011
010
001
000
Ideal transfer
function
Wiper
Code
Ideal transfer
function
Wide code, > 1 LSb
Narrow code < 1 LSb
INL < 0
RBW Resistance
FIGURE B-9:
R-INL ACCURACY.
RBW Resistance
FIGURE B-10:
R-DNL ACCURACY.
DS20005207A-page 84
2013 Microchip Technology Inc.
MCP41HVX1
B.16 Total Unadjusted Error (E )
B.18 Major-Code Transition Glitch
T
The Total Unadjusted Error (ET) is the difference
between the ideal and measured VW voltage.
Typically, calibration of the output voltage is
implemented to improve system performance.
Major-code transition glitch is the impulse energy
injected into the Wiper pin when the code in the Wiper
register changes state. It is normally specified as the
area of the glitch in nV-Sec, and is measured when the
digital code is changed by 1 LSb at the major carry tran-
sition (Example: 01111111 to 10000000, or
10000000to 01111111).
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
Equation B-12 shows the Total Unadjusted Error
calculation.
B.19 Digital Feedthrough
Note:
Analog switch leakage increases with tem-
perature. This leakage increase substan-
tially at higher temperatures (> ~100°C).
As analog switch leakage increases, the
Wiper output voltage (VW) decreases,
which effects the total Unadjusted Error.
The Digital feedthrough is the glitch that appears at the
analog output caused by coupling from the digital input
pins of the device. The area of the glitch is expressed
in nV-Sec, and is measured with a full-scale change
(Example: all 0s to all 1s and vice versa) on the digital
input pins. The digital feedthrough is measured when
the digital potentiometer is not being written to the out-
put register.
EQUATION B-12: TOTAL UNADJUSTED
ERROR CALCULATION
B.20 Power-Supply Sensitivity (PSS)
( VW_Actual(@code) - VW_Ideal(@Code)
VLSb(Ideal)
)
ET =
PSS indicates how the output (VW or RBW) of the digital
potentiometer is affected by changes in the supply volt-
age. PSS is the ratio of the change in VW to a change
in VDD for mid-scale output of the digital potentiometer.
The VW is measured while the VDD is varied from 5.5V
to 2.7V as a step, and expressed in % / %, which is the
% change of the VW output voltage with respect to the
% change of the VDD voltage.
Where:
ET is expressed in LSb.
VW_Actual(@code) = The measured W pin output
voltage at the specified code
VW_Ideal(@code) = The calculated W pin output
voltage at the specified code
( code * VLSb(Ideal)
)
EQUATION B-13: PSS CALCULATION
VLSb(Ideal)
=
VAB / # RS
8-bit = VAB / 255
7-bit = VAB / 127
( VW(@5.5V) - VW(@2.7V) ) / VW(@5.5V)
(5.5V - 2.7V) / 5.5V
)
PSS =
Where:
B.17 Settling Time
PSS is expressed in % / %.
The Settling time is the time delay required for the VW
voltage to settle into its new output value. This time is
measured from the start of code transition, to when the
VW voltage is within the specified accuracy. It is related
to the RC characteristics of the resistor ladder and
wiper switches.
VW(@5.5V) = The measured VW output
voltage with VDD = 5.5V
VW(@2.7V) = The measured VW output
voltage with VDD = 2.7V
B.21 Power-Supply Rejection Ratio
(PSRR)
In the MCP41HVX1, the settling time is a measure of
the time delay until the VW voltage reaches within 0.5
LSb of its final value, when the volatile Wiper Register
changes from Zero Scale to Full Scale (or Full Scale to
Zero Scale).
PSRR indicates how the output of the digital potentiom-
eter is affected by changes in the supply voltage. PSRR
is the ratio of the change in VW to a change in VDD for
full-scale output of the digital potentiometer. The VW is
measured while the VDD is varied +/- 10% (VA and VB
voltages held constant), and expressed in dB or µV/V.
2013 Microchip Technology Inc.
DS20005207A-page 85
MCP41HVX1
B.22 Ratiometric Temperature
Coefficient
The ratiometric temperature coefficient quantifies the
error in the ratio RAW/RWB due to temperature drift.
This is typically the critical error when using a digital
potentiometer in a voltage divider configuration.
B.23 Absolute Temperature Coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end resistance (Nominal resistance
RAB) due to temperature drift. This is typically the
critical error when using the device in an adjustable
resistor configuration.
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Section 2.0 “Typi-
cal Performance Curves”.
B.24 -3dB Bandwidth
This is the frequency of the signal at the A terminal, that
causes the voltage at the W pin to fall -3 dB value from
that value of a static value on the A terminal. The output
decreases due to the RC characteristics of the resistor
network.
B.25 Resistor Noise Density (e
)
N_WB
This is the random noise generated by the device’s
internal resistances. It is specified as a spectral density
(voltage per square root Hertz).
DS20005207A-page 86
2013 Microchip Technology Inc.
MCP41HVX1
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
XXX
X
/XX
a) MCP41HV51T-502E/ST
Resistance Temperature Package
Version Range
5 k, 8-bit, 14-LD TSSOP.
b) MCP41HV51T-103E/ST
10 k, 8-bit, 14-LD TSSOP.
c) MCP41HV31T-503E/ST
50 k, 7-bit, 14-LD TSSOP.
d) MCP41HV31T-104E/MQ
Device:
MCP41HV31: Single Potentiometer (7-bit) with
SPI Interface
MCP41HV31T: Single Potentiometer (7-bit) with
SPI Interface (Tape and Reel)
MCP41HV51: Single Potentiometer (8-bit) with
SPI Interface
100 k, 7-bit, 20-LD QFN (5x5).
a) MCP41HV51T-502E/MQ
MCP41HV51T: Single Potentiometer (8-bit) with
SPI Interface (Tape and Reel)
5 k, 8-bit, 20-LD QFN (5x5).
b) MCP41HV51T-103E/MQ
10 k, 8-bit, 20-LD QFN (5x5).
c) MCP41HV31T-503E/MQ
50 k, 7-bit, 20-LD QFN (5x5).
d) MCP41HV31T-104E/MQ
Resistance
Version:
502 = 5 k
103 = 10 k
503 = 50 k
104 = 100 k
100 k, 7-bit, 20-LD QFN (5x5).
Temperature
Range:
E
= -40°C to +125°C
Package:
ST = Plastic TSSOP-14, 14-lead
MQ = Plastic QFN-20 (5x5), 20-lead
2013 Microchip Technology Inc.
DS20005207A-page 87
MCP41HVX1
NOTES:
DS20005207A-page 88
2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620772270
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2013 Microchip Technology Inc.
DS20005207A-page 89
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Toronto
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Canada
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11/29/12
DS20005207A-page 90
2013 Microchip Technology Inc.
相关型号：
MCP41HV51T
7/8-Bit Single, 36V (±18V) Digital POT with SPI Serial Interface and Volatile Memory
MICROCHIP
MCP41HVX1
7/8-Bit Single, 36V (±18V) Digital POT with SPI Serial Interface and Volatile Memory
MICROCHIP
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