MCP4341-104E/ST_技术文档

MCP434X/436X

7/8-Bit Quad SPI Digital POT with

Non-Volatile Memory

Package Types (Top View)

Features

• Quad Resistor Network

MCP43X1 Quad Potentiometers

• Potentiometer or Rheostat configuration options

• Resistor Network Resolution

- 7-bit: 128 Resistors (129 Taps)

- 8-bit: 256 Resistors (257 Taps)

• R_ABResistances options of:

- 5 kΩ

- 10 kΩ

- 50 kΩ

- 100 kΩ

P2A

P2W

P2B

V_DD

SDO

P3A

P3W

P3B

CS

SCK

SDI

20

19

18

17

16

1

2

3

4

5

6

7

8

9

10

15 RESET

14 WP

V_SS

P0B

12

P1B

P1W

P1A

P0W

P0A

12

11

• Zero Scale to Full Scale Wiper operation

• Low Wiper Resistance: 75 Ω (typical)

• Low Tempco:

TSSOP

- Absolute (Rheostat): 50 ppm typical

(0°C to 70°C)

- Ratiometric (Potentiometer): 15 ppm typical

• Non-volatile Memory

- Automatic Recall of Saved Wiper Setting

- WiperLock™ Technology

• SPI serial interface (10 MHz, modes 0,0 & 1,1)

- High-Speed Read/Writes to wiper registers

- Read/Write to Data EEPROM registers

- Serially enabled EEPROM write protect

17 16

18

19

20

15 V_DD

P3B

1

2

3

4

5

SDO

RESET

WP

14

13

12

CS

SCK

SDI

EP

21

P0B

11

V_SS

8

9 10

6

7

• Resistor Network Terminal Disconnect Feature

via Terminal Control (TCON) Register

• Reset input pin

4x4 QFN

MCP43X2 Quad Rheostat

• Write Protect Feature:

- Hardware Write Protect (WP) Control pin

- Software Write Protect (WP) Configuration bit

• Brown-out reset protection (1.5V typical)

• Serial Interface Inactive current (2.5 uA typical)

• High-Voltage Tolerant Digital Inputs: Up to 12.5V

• Supports Split Rail Applications

• Internal weak pull-up on all digital inputs

• Wide Operating Voltage:

- 2.7V to 5.5V - Device Characteristics

Specified

P2W

P2B

V_DD

SDO

P0B

P0W

P1W

P3W

P3B

CS

SCK

SDI

V_SS

P1B

14

13

12

11

10

9

1

2

3

4

5

6

7

8

TSSOP

- 1.8V to 5.5V - Device Operation

• Wide Bandwidth (-3 dB) Operation:

- 2 MHz (typical) for 5.0 kΩ device

• Extended temperature range (-40°C to +125°C)

DS22233A-page 1

MCP434X/436X

Device Block Diagram

V_DD

V_SS

Power-up/

Brown-out

Control

P0A

Resistor

Network 0

(Pot 0)

P0W

Wiper 0

CS

SCK

SDI

SPI Serial

Interface

Module &

Control

Logic

(WiperLock™

Technology)

& TCON0

Register

P0B

P1A

SDO

Resistor

Network 1

(Pot 1)

WP

RESET

P1W

Wiper 1

& TCON0

Register

Memory (16x9)

Wiper0 (V & NV)

Wiper1 (V & NV)

Wiper2 (V & NV)

Wiper3 (V & NV)

P1B

P2A

Resistor

Network 2

(Pot 2)

TCON0

TCON1

STATUS

P2W

Wiper 2

& TCON1

Register

Data EEPROM

(5 x 9-bits)

P2B

P3A

Resistor

Network 3

(Pot 3)

P3W

P3B

Wiper 3

& TCON1

Register

Device Features

Resistance (typical)

Wiper

V_DD

Wiper

Configuration

Device

Operating

Range ⁽²⁾

R_ABOptions (kΩ)

- R_W

(Ω)

MCP4331 ⁽³⁾

MCP4332 ⁽³⁾

MCP4341

4

Potentiometer⁽¹⁾SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾SPI

Rheostat SPI

75

129 1.8V to 5.5V

129 2.7V to 5.5V

257 1.8V to 5.5V

257 2.7V to 5.5V

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4342

MCP4351 ⁽³⁾

MCP4352 ⁽³⁾

MCP4361

Potentiometer⁽¹⁾SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾SPI

Rheostat SPI

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4362

Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).

2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.

3: Please check Microchip web site for device release and availability.

DS22233A-page 2

MCP434X/436X

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

Voltage on V_DDwith respect to V_SS................ -0.6V to +7.0V

Voltage on CS, SCK, SDI, SDI/SDO, WP, and

RESET with respect to V_{SS ...................................}-0.6V to 12.5V

Voltage on all other pins (PxA, PxW, PxB, and

SDO) with respect to V_{SS ............................}-0.3V to V_DD+ 0.3V

Input clamp current, I_IK

(V_I< 0, V_I> V_DD, V_I> V_PPON HV pins)......................±20 mA

Output clamp current, I_OK

(V_O< 0 or V_O> V_DD) ..................................................±20 mA

Maximum output current sunk by any Output pin

......................................................................................25 mA

Maximum output current sourced by any Output pin

......................................................................................25 mA

Maximum current out of V_SSpin .................................100 mA

Maximum current into V_DDpin ....................................100 mA

Maximum current into PXA, PXW & PXB pins ............±2.5 mA

Storage temperature ....................................-65°C to +150°C

Ambient temperature with power applied

.....................................................................-40°C to +125°C

Package power dissipation (T_A= +50°C, T_J= +150°C)

TSSOP-14................................................................1000 mW

TSSOP-20................................................................ 1110 mW

QFN-20 (4x4)...........................................................2320 mW

Soldering temperature of leads (10 seconds).............+300°C

ESD protection on all pins ................................... ≥ 4 kV (HBM),

.......................................................................... ≥ 300V (MM)

Maximum Junction Temperature (T_J) .........................+150°C

DS22233A-page 3

MCP434X/436X

AC/DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

–40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Supply Voltage

V_DD

2.7

1.8

—

5.5

2.7

V

Serial Interface only.

CS, SDI, SDO,

V_HV

V_SS

12.5V

V_DD

4.5V

≥

The CS pin will be at one

of three input levels

SCK, WP, RESET

pin Voltage Range

(V_IL, V_IHor V_IHH). (Note 6)

V_SS

—

V_DD

8.0V

+

V

V_DD

4.5V

<

V_DDStart Voltage

to ensure Wiper

Reset

V_BOR

V_DDRR

T_BORD

1.65

RAM retention voltage (V_RAM) < V_BOR

V_DDRise Rate to

ensure Power-on

Reset

(Note 9)

V/ms

µs

Delay after device

exits the reset

state

—

10

20

450

1

(V_DD> V_BOR

)

Supply Current

(Note 10)

I_DD

—

µA

Serial Interface Active,

V_DD= 5.5V, CS = V_IL, SCK @ 5 MHz,

write all 0’s to volatile Wiper 0 (address

0h)

mA

EE Write Current,

V_DD= 5.5V, CS = V_IL, SCK @ 5 MHz,

write all 0’s to non-volatile Wiper 0

(address 2h)

—

2.5

5

1

µA

Serial Interface Inactive,

CS = V_IH, V_DD= 5.5V

0.55

mA

Serial Interface Active,

V_DD= 5.5V, CS = V_IHH

,

SCK @ 5 MHz,

decrement non-volatile Wiper 0

(address 2h)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP43X1 only.

4: MCP43X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22233A-page 4

MCP434X/436X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

-502 devices (Note 1)

Resistance

(± 20%)

R_AB

4.0

8.0

5

10

6.0

12.0

60.0

120.0

kΩ

-103 devices (Note 1)

-503 devices (Note 1)

-104 devices (Note 1)

40.0

80.0

50

100

257

129

R_AB

Resolution

N

Taps 8-bit

Taps 7-bit

No Missing Codes

Note 6

Step Resistance

R_S

—

/

—

Ω

8-bit

(256)

R_AB

/

Ω

7-bit

Note 6

(128)

Nominal

(| R_ABWC

-

—

0.2

1.50

1.25

1.0

%

Ω

MCP43X1 devices only

Resistance Match R_ABMEAN|) /

R_ABMEAN

0.2

1.0

(| R_BWWC

R_BWMEAN|) /

R_BWMEAN

-

0.25

75

1.75

1.50

1.25

160

300

—

Code = Full Scale

Wiper Resistance

(Note 3, Note 4)

R_W

V_DD= 5.5 V, I_W= 2.0 mA, code = 00h

V_DD= 2.7 V, I_W= 2.0 mA, code = 00h

75

Ω

Nominal

Resistance

Tempco

ΔR_AB/ΔT

50

ppm/°C T_A= -20°C to +70°C

ppm/°C T_A= -40°C to +85°C

ppm/°C T_A= -40°C to +125°C

ppm/°C Code = Midscale (80h or 40h)

100

150

15

—

Ratiometeric

Tempco

ΔV_WB/ΔT

—

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP43X1 only.

4: MCP43X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22233A-page 5

MCP434X/436X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

Parameters

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Sym

Min

Typ

Max

Units

Conditions

Note 5, Note 6

Resistor Terminal

Input Voltage

V_A,V_W,V_B

Vss

—

V_DD

V

Range (Terminals

A, B and W)

Maximum current

through A, W or B

I_W

—

2.5

mA

Note 6, Worst case current through

wiper when wiper is either Full Scale or

Zero Scale.

Leakage current

into A, W or B

I_WL

—

100

—

nA

MCP43X1 PxA = PxW = PxB = V_SS

MCP43X2 PxB = PxW = V_SS

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP43X1 only.

4: MCP43X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22233A-page 6

MCP434X/436X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Full Scale Error

(MCP43X1 only)

(8-bit code = 100h,

7-bit code = 80h)

V_WFSE

-6.0

-4.0

-3.5

-2.0

-0.8

-0.5

—

-0.1

—

LSb

5 kΩ

8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

-0.1

—

10 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

-0.1

—

-0.1

—

50 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

-0.1

—

-0.1

—

100 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

-0.1

—

Zero Scale Error

(MCP43X1 only)

(8-bit code = 00h,

7-bit code = 00h)

V_WZSE

+0.1

±0.5

±0.25

+6.0

+3.0

+3.5

+2.0

+0.8

+0.5

+1

5 kΩ

8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

—

10 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

—

50 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

—

100 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

—

Potentiometer

Integral

Non-linearity

INL

DNL

BW

-1

8-bit

7-bit

3.0V ≤ V_DD≤ 5.5V

MCP43X1 devices only

(Note 2)

-0.5

+0.5

Potentiometer

Differential

Non-linearity

-0.5

±0.25

+0.5

LSb

8-bit

7-bit

3.0V ≤ V_DD≤ 5.5V

MCP43X1 devices only

(Note 2)

-0.25

±0.125

+0.25

Bandwidth -3 dB

(See Figure 2-54,

load = 30 pF)

—

2

—

MHz 5 kΩ

8-bit Code = 80h

7-bit Code = 40h

MHz

1

MHz 10 kΩ 8-bit Code = 80h

1

MHz

kHz

7-bit Code = 40h

50 kΩ 8-bit Code = 80h

7-bit Code = 40h

200

100

100 kΩ 8-bit Code = 80h

7-bit Code = 40h

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP43X1 only.

4: MCP43X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22233A-page 7

MCP434X/436X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

Parameters

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Sym

Min

Typ

Max

Units

Conditions

Rheostat Integral

Non-linearity

MCP43X1

(Note 4, Note 8)

MCP43X2devices

only (Note 4)

R-INL

-1.5

±0.5

+4.5

+1.5

LSb

5 kΩ

8-bit 5.5V, I_W= 900 µA

-8.25

+8.25

3.0V, I_W= 480 µA

(Note 7)

-1.125

-6.0

±0.5

+4.5

+1.125

+6.0

LSb

7-bit 5.5V, I_W= 900 µA

3.0V, I_W= 480 µA

(Note 7)

-1.5

-5.5

±0.5

+2.5

+1.5

+5.5

LSb

10 kΩ 8-bit 5.5V, I_W= 450 µA

3.0V, I_W= 240 µA

(Note 7)

-1.125

-4.0

±0.5

+2.5

+1.125

+4.0

LSb

7-bit 5.5V, I_W= 450 µA

3.0V, I_W= 240 µA

(Note 7)

-1.5

-2.0

±0.5

+1

+1.5

+2.0

LSb

50 kΩ 8-bit 5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

-1.125

-1.5

±0.5

+1

+1.125

+1.5

LSb

7-bit 5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

-1.0

-1.5

±0.5

+1.0

+1.5

LSb

100 kΩ 8-bit 5.5V, I_W= 45 µA

+0.25

3.0V, I_W= 24 µA

(Note 7)

-0.8

±0.5

+0.8

LSb

7-bit 5.5V, I_W= 45 µA

-1.125

+0.25

+1.125

3.0V, I_W= 24 µA

(Note 7)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP43X1 only.

4: MCP43X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22233A-page 8

MCP434X/436X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Rheostat

R-DNL

-0.5

-1.0

±0.25

+0.5

+1.0

LSb

pF

5 kΩ

8-bit 5.5V, I_W= 900 µA

3.0V (Note 7)

Differential

Non-linearity

MCP43X1

(Note 4, Note 8)

MCP43X2devices

only

-0.375

-0.75

-0.5

±0.25

+0.5

+0.375

+0.75

+0.5

7-bit 5.5V, I_W= 900 µA

3.0V (Note 7)

±0.25

+0.25

±0.25

+0.5

10 kΩ 8-bit 5.5V, I_W= 450 µA

3.0V (Note 7)

-1.0

+1.0

(Note 4)

-0.375

-0.75

-0.5

+0.375

+0.75

+0.5

7-bit 5.5V, I_W= 450 µA

3.0V (Note 7)

±0.25

75

50 kΩ 8-bit 5.5V, I_W= 90 µA

3.0V (Note 7)

-0.5

+0.5

-0.375

-0.5

+0.375

+0.5

7-bit 5.5V, I_W= 90 µA

3.0V (Note 7)

100 kΩ 8-bit 5.5V, I_W= 45 µA

3.0V (Note 7)

-0.5

+0.5

-0.375

—

+0.375

—

7-bit 5.5V, I_W= 45 µA

3.0V (Note 7)

Capacitance (P_A)

Capacitance (P_w)

Capacitance (P_B)

C_AW

C_W

f =1 MHz, Code = Full Scale

—

120

—

pF

C_BW

—

75

—

pF

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP43X1 only.

4: MCP43X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22233A-page 9

MCP434X/436X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

Parameters

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Sym

Min

Typ

Max

Units

Conditions

Digital Inputs/Outputs (CS, SDI, SDO, SCK, WP, RESET)

Schmitt Trigger

High Input

Threshold

V_IH

0.45 V_DD

—

V

2.7V ≤ V_DD≤ 5.5V

(Allows 2.7V Digital V_DDwith

5V Analog V_DD

)

0.5 V_DD

—

V

1.8V ≤ V_DD≤ 2.7V

Schmitt Trigger

Low Input

V_IL

0.2V_DD

Threshold

Hysteresis of

Schmitt Trigger

Inputs

V_HYS

—

0.1V_DD

—

V

High Voltage Input

Entry Voltage

V_IHH

8.5

—

12.5 ⁽⁶⁾

V

Threshold for WiperLock™ Technology

High Voltage Input

Exit Voltage

V_DD+

0.8V

12.5 ⁽⁶⁾

0.3V_DD

V_DD

High Voltage Limit

V_MAX

V_OL

—

V

Pin can tolerate V_MAXor less.

I_OL= 5 mA, V_DD= 5.5V

I_OL= 1 mA, V_DD= 1.8V

I_OH= -2.5 mA, V_DD= 5.5V

I_OL= -1 mA, V_DD= 1.8V

Output Low

Voltage (SDO)

V_SS

Output High

Voltage (SDO)

V_OH

0.7V_DD

V_DD

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP43X1 only.

4: MCP43X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22233A-page 10

MCP434X/436X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Weak Pull-up

Current

I_PU

—

1.75

mA

Internal V_DDpull-up, V_IHHpull-down,

V_DD= 5.5V, V_CS= 12.5V

—

170

16

—

µA

CS pin, V_DD= 5.5V, V_CS= 3V

V_DD= 5.5V, V_CS= 3V

CS Pull-up /

Pull-down

R_CS

kΩ

Resistance

RESET Pull-up

Resistance

R_RESET

I_IL

—

-1

—

16

—

10

—

1

kΩ

µA

pF

V_DD= 5.5V, V_RESET= 0V

Input Leakage

Current

V_IN= V_DD(all pins) and

V_IN= V_SS(all pins except RESET)

Pin Capacitance

C_IN, C_OUT

—

f_C= 20 MHz

RAM (Wiper, TCON) Value

Value Range

N

0h

—

1FFh

hex

8-bit device

7-bit device

TCON POR/BOR

Setting

1FF

All Terminals connected

EEPROM

Endurance

E_ndurance

—

1M

—

Cycles

hex

EEPROM Range

N

0h

1FFh

Initial NV Wiper

POR/BOR Setting

080h

040h

000h

hex

8-bit

7-bit

WiperLock Technology = Off

hex

Initial EEPROM

N

hex

POR/BOR Setting

EEPROM

t_WC

—

3

10

ms

Programming

Write Cycle Time

Power Requirements

Power Supply

Sensitivity

(MCP43X1)

PSS

—

0.0015 0.0035

%/% 8-bit

%/% 7-bit

V_DD= 2.7V to 5.5V,

V_A= 2.7V, Code = 80h

V_DD= 2.7V to 5.5V,

V_A= 2.7V, Code = 40h

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP43X1 only.

4: MCP43X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22233A-page 11

MCP434X/436X

1.1

SPI Mode Timing Waveforms and Requirements

RESET

t_RSTD

t_RST

SCK

Wx

FIGURE 1-1:

RESET Waveforms.

RESET TIMING

TABLE 1-1:

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

Timing Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

RESET pulse width

t_RST

50

—

ns

RESET rising edge

normal mode (Wiper

driving and SPI

t_RSTD

20

interface operational)

DS22233A-page 12

MCP434X/436X

V_IHH

V_IH

84

CS

V_IL

70

72

SCK

83

71

80

78

79

MSb

LSb

SDO

SDI

BIT6 - - - - - -1

77

75, 76

MSb IN

74

BIT6 - - - -1

LSb IN

73

FIGURE 1-2:

SPI Timing Waveform (Mode = 11).

TABLE 1-2:

#

SPI REQUIREMENTS (MODE = 11)

Characteristic

Symbol

Min

Max Units

Conditions

SCK Input Frequency

F_SCK

—

10

1

MHz V_DD= 2.7V to 5.5V

MHz V_DD= 1.8V to 2.7V

ns

70 CS Active (V_ILor V_IHH) to SCK↑ input

71 SCK input high time

TcsA2scH

TscH

60

45

500

45

500

10

20

—

50

70

170

—

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns

72 SCK input low time

TscL

73 Setup time of SDI input to SCK↑ edge

TDIV2scH

74 Hold time of SDI input from SCK↑ edge

77 CS Inactive (V_IH) to SDO output hi-impedance

80 SDO data output valid after SCK↓ edge

TscH2DIL

TcsH2DOZ

TscL2DOV

ns Note 1

—

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns V_DD= 2.7V to 5.5V

ms V_DD= 1.8V to 2.7V

ns

83 CS Inactive (V_IH) after SCK↑ edge

TscH2csI

TcsA2csI

100

1

84 Hold time of CS Inactive (V_IH) to

50

—

CS Active (V_ILor V_IHH

)

Note 1: This specification by design.

DS22233A-page 13

MCP434X/436X

V_IHH

V_IH

84

82

CS

V_IL

70

SCK

83

80

71

72

MSb

BIT6 - - - - - -1

BIT6 - - - -1

LSb

SDO

SDI

75, 76

77

73

MSb IN

74

LSb IN

FIGURE 1-3:

SPI Timing Waveform (Mode = 00).

SPI REQUIREMENTS (MODE = 00)

TABLE 1-3:

#

Characteristic

Symbol

Min

Max Units

Conditions

SCK Input Frequency

F_SCK

—

10

1

MHz V_DD= 2.7V to 5.5V

MHz V_DD= 1.8V to 2.7V

ns

70 CS Active (V_ILor V_IHH) to SCK↑ input

71 SCK input high time

TcsA2scH

TscH

60

45

500

45

500

10

20

—

50

70

170

85

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns

72 SCK input low time

TscL

73 Setup time of SDI input to SCK↑ edge

74 Hold time of SDI input from SCK↑ edge

77 CS Inactive (V_IH) to SDO output hi-impedance

80 SDO data output valid after SCK↓ edge

TDIV2scH

TscH2DIL

TcsH2DOZ

TscL2DOV

ns

ns Note 1

—

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns

82 SDO data output valid after

TssL2doV

TscH2csI

—

CS Active (V_ILor V_IHH

)

83 CS Inactive (V_IH) after SCK↓ edge

100

1

—

ns V_DD= 2.7V to 5.5V

ms V_DD= 1.8V to 2.7V

ns

84 Hold time of CS Inactive (V_IH) to

TcsA2csI

50

CS Active (V_ILor V_IHH

)

Note 1: This specification by design.

DS22233A-page 14

MCP434X/436X

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 14L-TSSOP

Thermal Resistance, 20L-QFN

Thermal Resistance, 20L-TSSOP

T_A

-40

-65

—

+125

+150

°C

θ_JA

—

100

43

—

°C/W

90

DS22233A-page 15

MCP434X/436X

NOTES:

DS22233A-page 16

MCP434X/436X

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

700

250

200

150

100

50

1000

800

600

400

200

0

2.7V -40°C

650

2.7V 25°C

600

2.7V 85°C

550

2.7V 125°C

5.5V -40°C

5.5V 25°C

5.5V 85°C

5.5V 125°C

500

450

400

350

300

250

200

150

100

50

I_CS

-200

-400

-600

-800

-1000

R_CS

0

0.00

2.00

4.00

6.00

f_SCK(MHz)

8.00 10.00 12.00

2

3

4

5

6

7

8

9

10

V_CS(V)

FIGURE 2-1:

Frequency (f

Device Current (I ) vs. SPI

) and Ambient Temperature

FIGURE 2-4:

Resistance (R ) and Current (I ) vs. CS Input

CS Pull-up/Pull-down

DD

SCK

CS

(V = 2.7V and 5.5V).

Voltage (V ) (V = 5.5V).

DD

CS DD

3.0

2.5

2.0

1.5

1.0

0.5

0.0

12

10

8

5.5V Entry

5.5V Exit

5.5V

2.7V Entry

6

4

2.7V Exit

2.7V

2

0

-40

25

85

125

-40 -20

0

20

40

60

80 100 120

Ambient Temperature (°C)

FIGURE 2-2:

Device Current (I

) and

FIGURE 2-5:

CS High Input Entry/Exit

SHDN

V

. (CS = V ) vs. Ambient Temperature.

Threshold vs. Ambient Temperature and V

.

DD

700.0

600.0

500.0

400.0

300.0

200.0

100.0

5.5V

2.7V

-40

25

85

125

Ambient Temperature (°C)

FIGURE 2-3:

Write Current (I

) vs.

WRITE

Ambient Temperature and V

.

DD

DS22233A-page 17

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

1.25

0.75

0.25

-0.25

-0.75

-1.25

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

DNL

-40°C

40

-40°C 25°C

R_W

25°C

85°C

R_W

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-6:

5 kΩ Pot Mode – R (Ω),

FIGURE 2-9:

5 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

6

260

220

180

140

100

60

260

220

180

140

100

60

INL

4

DNL

2

R_W

125°C

-0.1

-0.2

-0.3

0

-40°C

85°C

25°C

DNL

-40°C

125°C 85°C

20

-2

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-7:

5 kΩ Pot Mode – R (Ω),

FIGURE 2-10:

5 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

DD

5300

5250

5200

5150

5100

5050

6000

5000

4000

3000

2000

1000

0

2.7V

5.5V

-40°C

25°C

85°C

125°C

-40

0

40

80

120

0

32

64

96

128 160 192 224 256

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-8:

5 kΩ – Nominal Resistance

FIGURE 2-11:

5 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS22233A-page 18

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-12:

5 kΩ – Low-Voltage

FIGURE 2-15:

5 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

FIGURE 2-13:

5 kΩ – Low-Voltage

FIGURE 2-16:

5 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

FIGURE 2-14:

5 kΩ – Power-Up Wiper

Response Time (20 ms/Div).

DS22233A-page 19

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.5

0

INL

DNL

60

-0.1

-0.2

-0.3

-0.5

-1

DNL

40

-40°C

40

-40°C

R_W

25°C

85°C

85°C 25°C

R_W

125°C

20

0

25 50 75 100 125150175200225 250

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-17:

10 kΩ Pot Mode – R (Ω),

FIGURE 2-20:

10 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

4

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

260

220

180

140

100

60

3

260

220

180

140

100

60

INL

DNL

2

1

0

-0.1

-0.2

-0.3

R_W

DNL R_W

-40°C

-1

-2

-40°C

25°C

85°C 25°C

85°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

25 50 75 100 125 150 175 200 225 250

Wiper Setting (decimal)

FIGURE 2-18:

10 kΩ Pot Mode – R (Ω),

FIGURE 2-21:

10 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

DD

10250

10200

12000

10000

8000

6000

4000

2000

0

10150

2.7V

10100

-40°C

25°C

85°C

125°C

5.5V

10050

10000

-40

0

40

80

120

0

32

64

96 128 160 192 224 256

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-19:

10 kΩ – Nominal Resistance

FIGURE 2-22:

10 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS22233A-page 20

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-23:

10 kΩ – Low-Voltage

FIGURE 2-25:

10 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

FIGURE 2-24:

10 kΩ – Low-Voltage

FIGURE 2-26:

10 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

DS22233A-page 21

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

-40°C

40

-40°C

R_W

25°C

85°C

25°C

85°C

R_W

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-27:

50 kΩ Pot Mode – R (Ω),

FIGURE 2-30:

50 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.75

0.5

0.25

0

260

220

180

140

100

60

260

220

180

140

100

60

INL

DNL

-0.25

-0.5

-0.75

-1

R_W

-0.1

-0.2

-0.3

R_W

-40°C

25°C

85°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-28:

50 kΩ Pot Mode – R (Ω),

FIGURE 2-31:

50 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

DD

50800

50600

50400

60000

50000

40000

30000

20000

10000

0

50200

2.7V

50000

5.5V

-40°C

25°C

85°C

49800

49600

49400

125°C

-40

0

40

80

120

0

32

64

96 128 160 192 224 256

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-29:

50 kΩ – Nominal Resistance

FIGURE 2-32:

50 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS22233A-page 22

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-33:

50 kΩ – Low-Voltage

FIGURE 2-35:

50 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

FIGURE 2-34:

50 kΩ – Low-Voltage

FIGURE 2-36:

50 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

DS22233A-page 23

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

-0.1

-0.2

40

-40°C

R_W

25°C

85°C

R_W

85°C 25°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-37:

100 kΩ Pot Mode – R (Ω),

FIGURE 2-40:

100 kΩ Rheo Mode – R

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

0.6

0.4

0.2

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.2

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

260

220

180

140

100

60

0.15

0.1

260

220

180

140

100

60

INL

DNL

0.05

0

-0.05

-0.1

-0.15

-0.2

-0.4

-0.6

R_W

-40°C

85°C 25°C

85°C

25°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-38:

100 kΩ Pot Mode – R (Ω),

FIGURE 2-41:

100 kΩ Rheo Mode – R

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

DD

101500

101000

120000

100000

80000

60000

40000

20000

0

100500

2.7V

100000

-40°C

25°C

85°C

5.5V

99500

125°C

99000

0

32 64

96 128 160 192 224 256

-40

0

40

80

120

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-39:

100 kΩ – Nominal

FIGURE 2-42:

100 kΩ – R

(Ω) vs. Wiper

WB

Resistance (Ω) vs. Ambient Temperature and

Setting and Ambient Temperature.

V

.

DD

DS22233A-page 24

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-43:

100 kΩ – Low-Voltage

FIGURE 2-45:

100 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

FIGURE 2-44:

100 kΩ – Low-Voltage

FIGURE 2-46:

100 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

DS22233A-page 25

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

2.4

2.2

0

-5

5.5V

-10

-15

-20

-25

-30

-35

-40

-45

2

2.7V

1.8

1.6

5.5V

1.4

2.7V

1.2

1

-40

0

40

80

120

-40

0

40

Temperature (°C)

80

120

Temperature (°C)

FIGURE 2-47:

V

(SDI, SCK, CS, and

FIGURE 2-49:

I

(SDO) vs. V and

IH

OH

DD

RESET) vs. V and Temperature.

Temperature.

DD

1.4

1.3

50

45

40

35

30

25

20

15

10

5

5.5V

1.2

1.1

1

0.9

2.7V

0.8

0.7

0.6

0

-40

0

40

Temperature (°C)

80

120

-40

0

40

Temperature (°C)

80

120

FIGURE 2-48:

V

(SDI, SCK, CS, and

FIGURE 2-50:

I

(SDO) vs. V and

IL

OL DD

RESET) vs. V and Temperature.

Temperature.

DD

DS22233A-page 26

MCP434X/436X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

4.0

3.5

3.0

14.2

14.1

14.0

13.9

13.8

13.7

13.6

13.5

13.4

5.5V

2.7V

2.5

2.0

5.5V

1.5

1.0

-40

0

40

80

120

-40

0

40

80

120

Temperature (°C)

FIGURE 2-51:

Nominal EEPROM Write

FIGURE 2-53:

SCK Input Frequency vs.

Cycle Time vs. V and Temperature.

Voltage and Temperature.

DD

2.1

Test Circuits

2

1.6

1.2

0.8

0.4

0

+5V

A

B

V

IN

W

V

+

-

OUT

Offset

GND

-40

0

40

80

120

Temperature (°C)

2.5V DC

FIGURE 2-52:

POR/BOR Trip point vs. V

DD

and Temperature.

FIGURE 2-54:

-3 db Gain vs. Frequency

Test.

DS22233A-page 27

MCP434X/436X

NOTES:

DS22233A-page 28

MCP434X/436X

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

Additional descriptions of the device pins follows.

TABLE 3-1:

PINOUT DESCRIPTION FOR THE MCP434X/436X

Weak

Pull-up/

down

TSSOP

QFN

20L

Standard Function

Buffer

Type

Symbol

I/O

(Note 1)

14L

20L

P3A

P3W

P3B

CS

A

I

Analog

No

—

1

2

19

20

1

Potentiometer 3 Terminal A

Potentiometer 3 Wiper Terminal

Potentiometer 3 Terminal B

SPI Chip Select Input

2

3

HV w/ST “smart”

3

4

2

SCK

SDI

I

4

5

3

SPI Clock Input

I

5

6

4

SPI Serial Data Input

V_SS

—

A

I

P

Analog

I

—

No

6

7

5

Ground

P1B

P1W

P1A

P0A

P0W

P0B

WP

7

8

6

Potentiometer 1 Terminal B

Potentiometer 1 Wiper Terminal

Potentiometer 1 Terminal A

Potentiometer 0 Terminal A

Potentiometer 0 Wiper Terminal

Potentiometer 0 Terminal B

Hardware EEPROM Write Protect

Hardware Reset Pin

No

8

9

7

No

—

9

10

11

12

13

14

15

16

17

18

19

20

—

8

No

9

No

10

11

12

13

14

15

16

17

18

21

No

10

—

11

12

13

14

—

“smart”

Yes

No

RESET

SDO

V_DD

P2B

P2W

P2A

EP

I

HV w/ST

O

—

A

—

SPI Serial Data Output

P

—

Positive Power Supply Input

Potentiometer 2 Terminal B

Potentiometer 2 Wiper Terminal

Potentiometer 2 Terminal A

Exposed Pad. (Note 2)

Analog

—

No

—

Legend:

HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)

A = Analog pins (Potentiometer terminals)

O = digital output

I = digital input (high Z)

I/O = Input / Output

P = Power

Note 1: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and

shut-down current.

2: The QFN package has a contact on the bottom of the package. This contact is conductively connected to

the die substrate, and therefore should be unconnected or connected to the same ground as the device’s

V_SSpin.

DS22233A-page 29

MCP434X/436X

3.1

Chip Select (CS)

3.6

Potentiometer Terminal A

The CS pin is the serial interface’s chip select input.

Forcing the CS pin to V_ILenables the serial commands.

Forcing the CS pin to V_IHHenables the high-voltage

serial commands.

The terminal A pin is available on the MCP43X1

devices, and is connected to the internal

potentiometer’s terminal A.

The potentiometer’s terminal A is the fixed connection

to the Full Scale wiper value of the digital

potentiometer. This corresponds to a wiper value of

0x100 for 8-bit devices or 0x80 for 7-bit devices.

3.2

Serial Data In (SDI)

The SDI pin is the serial interfaces Serial Data In pin.

This pin is connected to the Host Controllers SDO pin.

The terminal A pin does not have a polarity relative to

the terminal W or B pins. The terminal A pin can

support both positive and negative current. The voltage

3.3

Ground (V_SS)

on terminal A must be between V_SSand V_DD

.

The V_SSpin is the device ground reference.

The terminal A pin is not available on the MCP43X2

devices, and the internally terminal A signal is floating.

3.4

Potentiometer Terminal B

MCP43X1 devices have four terminal A pins, one for

each resistor network.

The terminal B pin is connected to the internal

potentiometer’s terminal B.

3.7

Write Protect (WP)

The potentiometer’s terminal B is the fixed connection

to the Zero Scale wiper value of the digital

potentiometer. This corresponds to a wiper value of

0x00 for both 7-bit and 8-bit devices.

The WP pin is used to force the non-volatile memory to

be write protected.

The terminal B pin does not have a polarity relative to

the terminal W or A pins. The terminal B pin can

support both positive and negative current. The voltage

3.8

Reset (RESET)

The RESET pin is used to force the device into the

POR/BOR state.

on terminal B must be between V_SSand V_DD

.

MCP43XX devices have four terminal B pins, one for

each resistor network.

3.9

Serial Data Out (SDO)

The SDO pin is the serial interfaces Serial Data Out pin.

This pin is connected to the Host Controllers SDI pin.

3.5

Potentiometer Wiper (W) Terminal

This pin allows the Host Controller to read the digital

potentiometers registers, or monitor the state of the

command error bit.

The terminal W pin is connected to the internal

potentiometer’s terminal W (the wiper). The wiper

terminal is the adjustable terminal of the digital

potentiometer. The terminal W pin does not have a

polarity relative to terminals A or B pins. The terminal

W pin can support both positive and negative current.

The voltage on terminal W must be between V_SSand

3.10 Positive Power Supply Input (V_DD

)

The V_DDpin is the device’s positive power supply input.

The input power supply is relative to V_SS

.

V_DD

.

While the device V_DD< V_min(2.7V), the electrical

performance of the device may not meet the data sheet

specifications.

MCP43XX devices have four terminal W pins, one for

each resistor network.

3.11 Exposed Pad (EP)

This pad is conductively connected to the device's

substrate. This pad should be tied to the same potential

as the V_SSpin (or left unconnected). This pad could be

used to assist as a heat sink for the device when

connected to a PCB heat sink.

DS22233A-page 30

MCP434X/436X

4.1.2

BROWN-OUT RESET

4.0

FUNCTIONAL OVERVIEW

When the device powers down, the device V_DDwill

cross the V_POR/V_BORvoltage.

This Data Sheet covers a family of four non-volatile

Digital Potentiometer and Rheostat devices that will be

referred to as MCP43XX. The MCP43X1 devices are

the Potentiometer configuration, while the MCP43X2

devices are the Rheostat configuration.

Once the V_DDvoltage decreases below the V_POR/V_BOR

voltage the following happens:

• Serial Interface is disabled

As the Device Block Diagram shows, there are four

main functional blocks. These are:

• EEPROM Writes are disabled

If the V_DDvoltage decreases below the V_RAMvoltage,

the following happens:

• POR/BOR and RESET Operation

• Memory Map

• Volatile wiper registers may become corrupted

• TCON registers may become corrupted

• Resistor Network

• Serial Interface (SPI)

As the voltage recovers above the V_POR/V_BORvoltage

The POR/BOR operation and the Memory Map are

discussed in this section and the Resistor Network and

SPI operation are described in their own sections. The

Device Commands commands are discussed in

Section 7.0.

see Section 4.1.1 “Power-on Reset”.

Serial commands not completed due to a brown-out

condition may cause the memory location (volatile and

non-volatile) to become corrupted.

4.1.3

RESET PIN

4.1

POR/BOR and RESET Operation

The RESET pin can be used to force the device into

the POR/BOR state of the device. When the RESET

pin is forced Low, the device is forced into the reset

state. This means that the TCON and STATUS

registers are forced to their default values and the

volatile wiper registers are loaded with the value in the

corresponding Non-Volatile wiper register. Also the

SPI interface is disabled. Any non-volatile write cycle

is not interrupted, and allowed to complete.

The Power-on Reset is the case where the device is

having power applied to it from V_SS. The Brown-out

Reset occurs when a device had power applied to it,

and that power (voltage) drops below the specified

range.

The devices RAM retention voltage (V_RAM) is lower

than the POR/BOR voltage trip point (V_POR/V_BOR). The

maximum V_POR/V_BORvoltage is less then 1.8V.

This feature allows a hardware method for all registers

to be updated at the same time.

When V_POR/V_BOR< V_DD< 2.7V, the electrical

performance may not meet the data sheet

specifications. In this region, the device is capable of

reading and writing to its EEPROM and incrementing,

decrementing, reading and writing to its volatile

memory if the proper serial command is executed.

4.1.4

INTERACTION OF RESET PIN AND BOR/

POR CIRCUITRY

Figure 4-1 shows how the RESET pin signal and the

POR/BOR signal interact to control the hardware reset

state of the device.

When V_DD< V_POR/V_BORor the RESET pin is Low, the

pin weak pull-ups are enabled.

4.1.1

POWER-ON RESET

RESET (from pin)

Device reset

When the device powers up, the device V_DDwill cross

the V_POR/V_BORvoltage. Once the V_DDvoltage crosses

the V_POR/V_BORvoltage, the following happens:

POR/BOR signal

FIGURE 4-1:

RESET Pin Interaction.

POR/BOR Signal and

• Volatile wiper register is loaded with value in the

corresponding non-volatile wiper register

• The TCON registers are loaded their default value

• The device is capable of digital operation

DS22233A-page 31

MCP434X/436X

4.2

Memory Map

The device memory is 16 locations that are 9-bits wide

(16x9 bits). This memory space contains both volatile

and non-volatile locations (see Table 4-1).

TABLE 4-1:

Address

MEMORY MAP AND THE SUPPORTED COMMANDS

Memory

Type

Factory

Initialization

Function

Allowed Commands Disallowed Commands ⁽²⁾

—

00h

01h

02h

Volatile Wiper 0

Volatile Wiper 1

RAM

Read, Write,

Increment, Decrement

—

RAM

Read, Write,

Increment, Decrement

—

Non-Volatile Wiper 0 EEPROM

Non-Volatile Wiper 1 EEPROM

Read, Write ⁽¹⁾

Increment, Decrement

8-bit

7-bit

8-bit

7-bit

80h

40h

80h

03h

04h

Read, Write ⁽¹⁾

Increment, Decrement

40h

—

Volatile

TCON0 Register

RAM

Read, Write

Read

—

05h

06h

Status Register

Volatile Wiper 2

RAM

Write, Increment, Decrement

—

Read, Write,

Increment, Decrement

—

07h

08h

Volatile Wiper 3

RAM

Read, Write,

Increment, Decrement

—

Non-Volatile Wiper 2 EEPROM

Non-Volatile Wiper 3 EEPROM

Read, Write ⁽¹⁾

Read, Write

Increment, Decrement

8-bit

7-bit

8-bit

7-bit

80h

40h

80h

09h

0Ah

Increment, Decrement

40h

—

Volatile

RAM

TCON1 Register

0Bh

0Ch

0Dh

0Eh

0Fh

Data EEPROM

EEPROM

Read, Write ⁽¹⁾

Increment, Decrement

000h

Note 1: When an EEPROM write is active, these are invalid commands and will generate an error condition. The

user should use a read of the Status register to determine when the write cycle has completed. To exit the

error condition, the user must take the CS pin to the V_IHlevel and then back to the active state (V_ILor

V_IHH).

2: This command on this address will generate an error condition. To exit the error condition, the user must

take the CS pin to the V_IHlevel and then back to the active state (V_ILor V_IHH).

DS22233A-page 32

MCP434X/436X

4.2.1

NON-VOLATILE MEMORY

(EEPROM)

4.2.1.4

Special Features

There are 5 non-volatile bits that are not directly

mapped into the address space. These bits control the

following functions:

This memory can be grouped into two uses of

non-volatile memory. These are:

• EEPROM Write Protect

• General Purpose Registers

• Non-Volatile Wiper Registers

• WiperLock Technology for Non-Volatile Wiper 0

• WiperLock Technology for Non-Volatile Wiper 1

• WiperLock Technology for Non-Volatile Wiper 2

• WiperLock Technology for Non-Volatile Wiper 3

The non-volatile wipers starts functioning below the

devices V_POR/V_BORtrip point.

4.2.1.1

General Purpose Registers

The operation of WiperLock Technology is discussed in

Section 5.3. The state of the WL0, WL1, WL2, WL3,

and WP bits is reflected in the STATUS register (see

Register 4-1).

These locations allow the user to store up to 5 (9-bit)

locations worth of information.

4.2.1.2

Non-Volatile Wiper Registers

These locations contain the wiper values that are

loaded into the corresponding volatile wiper register

whenever the device has a POR/BOR event. There are

four registers, one for each resistor network.

EEPROM Write Protect

All internal EEPROM memory can be Write Protected.

When EEPROM memory is Write Protected, Write

commands to the internal EEPROM are prevented.

The non-volatile wiper register enables stand-alone

operation of the device (without Microcontroller control)

after being programmed to the desired value.

Write Protect (WP) can be enabled/disabled by two

methods. These are:

• External WP Hardware pin (MCP43X1 devices

only)

4.2.1.3

Factory Initialization of Non-Volatile

Memory (EEPROM)

• Non-Volatile configuration bit (WP)

The Non-Volatile Wiper values will be initialized to

mid-scale value. This is shown in Table 4-2.

High Voltage commands are required to enable and

disable the non-volatile WP bit. These commands are

shown in Section 7.9 “Modify Write Protect or

WiperLock Technology (High Voltage)”.

The General purpose EEPROM memory will be

programmed to a default value of 0x000.

It is good practice in the manufacturing flow to

configure the device to your desired settings.

To write to EEPROM, both the external WP pin and the

internal WP EEPROM bit must be disabled. Write

Protect does not block commands to the volatile

registers.

TABLE 4-2:

DEFAULT FACTORY

SETTINGS SELECTION

4.2.2

VOLATILE MEMORY (RAM)

Wiper

Code

There are seven Volatile Memory locations. These are:

• Volatile Wiper 0

• Volatile Wiper 1

• Volatile Wiper 2

8-bit 7-bit

• Volatile Wiper 3

• Status Register

• Terminal Control (TCON0) Register 0

• Terminal Control (TCON)1 Register 1

-502

5.0 kΩ Mid scale 80h 40h Disabled

-103 10.0 kΩ Mid scale 80h 40h Disabled

-503 50.0 kΩ Mid scale 80h 40h Disabled

-104 100.0 kΩ Mid scale 80h 40h Disabled

The volatile memory starts functioning at the RAM

retention voltage (V_RAM).

DS22233A-page 33

MCP434X/436X

4.2.2.1

Status (STATUS) Register

This register contains 7 status bits. These bits show the

state of the WiperLock bits, the Write Protect bit, and if

an EEPROM write cycle is active. The STATUS register

can be accessed via the READ commands.

Register 4-1 describes each STATUS register bit.

The STATUS register is placed at Address 05h.

REGISTER 4-1:

STATUS REGISTER

R-1 R-1

R-1

D8:D7

bit 7

R-1

R-0

R-x

R-1

—

R-x

WP ⁽¹⁾

(1)

WL3

WL2

EEWA

WL1

WL0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 8-7

bit 6

D8:D7: Reserved. Forced to “1”

WL3: WiperLock Status bit for Resistor Network 3 (Refer to Section 5.3 “WiperLock™ Technology”

for further information)

The WiperLock Technology bit (WL3) prevents the Volatile and Non-Volatile Wiper 3 addresses and the

TCON1 register bits R3HW, R3A, R3W, and R3B from being written to. High Voltage commands are

required to enable and disable WiperLock Technology.

1= Wiper and TCON1 register bits R3HW, R3A, R3W, and R3B of Resistor Network 3 (Pot 3) are

“Locked” (Write Protected)

0= Wiper and TCON1 of Resistor Network 3 (Pot 3) can be modified

Note:

The WL3 bit always reflects the result of the last programming cycle to the non-volatile WL3

bit. After a POR/BOR or RESET pin event, the WL3 bit is loaded with the non-volatile WL3

bit value.

bit 5

WL2: WiperLock Status bit for Resistor Network 2 (Refer to Section 5.3 “WiperLock™ Technology”

for further information)

The WiperLock Technology bit (WL2) prevents the Volatile and Non-Volatile Wiper 2 addresses and the

TCON1 register bits R2HW, R2A, R2W, and R2B from being written to. High Voltage commands are

required to enable and disable WiperLock Technology.

1= Wiper and TCON1 register bits R2HW, R2A, R2W, and R2B of Resistor Network 2 (Pot 2) are

“Locked” (Write Protected)

0= Wiper and TCON1 of Resistor Network 2 (Pot 2) can be modified

Note:

The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0

bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the non-volatile WL0

bit value.

bit 4

EEWA: EEPROM Write Active Status bit

This bit indicates if the EEPROM Write Cycle is occurring.

1= An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory

locations are allowed (addresses 00h, 01h, 04h, and 05h)

0= An EEPROM Write cycle is NOT currently occurring

Note 1: Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is

Not directly written, but reflects the system state (for this feature).

DS22233A-page 34

MCP434X/436X

REGISTER 4-1:

bit 3

STATUS REGISTER (CONTINUED)

WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 “WiperLock™ Technology”

for further information)

The WiperLock Technology bit (WL1) prevents the Volatile and Non-Volatile Wiper 1 addresses and the

TCON0 register bits R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are

required to enable and disable WiperLock Technology.

1= Wiper and TCON0 register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are

“Locked” (Write Protected)

0= Wiper and TCON0 of Resistor Network 1 (Pot 1) can be modified

Note:

The WL1 bit always reflects the result of the last programming cycle to the non-volatile WL1

bit. After a POR/BOR or RESET pin event, the WL1 bit is loaded with the non-volatile WL1

bit value.

bit 2

WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 “WiperLock™ Technology”

for further information)

The WiperLock Technology bit (WL0) prevents the Volatile and Non-Volatile Wiper 0 addresses and the

TCON0 register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are

required to enable and disable WiperLock Technology.

1= Wiper and TCON0 register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are

“Locked” (Write Protected)

0= Wiper and TCON0 of Resistor Network 0 (Pot 0) can be modified

Note:

The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0

bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the non-volatile WL0

bit value.

bit 1

bit 0

Reserved: Forced to “1”

WP: EEPROM Write Protect Status bit (Refer to Section “EEPROM Write Protect” for further

information)

This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is

enabled, writes to all non-volatile memory are prevented. This includes the General Purpose EEPROM

memory, and the non-volatile Wiper registers. Write Protect does not block modification of the volatile

wiper register values or the volatile TCON0 and TCON1 register values (via Increment, Decrement, or

Write commands).

This status bit is an OR of the devices Write Protect pin (WP) and the internal non-volatile WP bit. High

Voltage commands are required to enable and disable the internal WP EEPROM bit.

1= EEPROM memory is Write Protected

0= EEPROM memory can be written

Note 1: Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is

Not directly written, but reflects the system state (for this feature).

DS22233A-page 35

MCP434X/436X

The value that is written to the specified TCON register

will appear on the appropriate resistor network

terminals when the serial command has completed.

4.2.2.2

Terminal Control (TCON) Registers

There are two Terminal Control (TCON) Registers.

These are called TCON0 and TCON1. Each register

contains 8 control bits. Four bits for each Wiper.

Register 4-2 describes each bit of the TCON0 register,

while Register 4-3 describes each bit of the TCON1

register.

When the WL1 bit is enabled, writes to the TCON0

register bits R1HW, R1A, R1W, and R1B are inhibited.

When the WL0 bit is enabled, writes to the TCON0

register bits R0HW, R0A, R0W, and R0B are inhibited.

The state of each resistor network terminal connection

is individually controlled. That is, each terminal

connection (A, B and W) can be individually connected/

disconnected from the resistor network. This allows the

system to minimize the currents through the digital

potentiometer.

When the WL3 bit is enabled, writes to the TCON1

register bits R3HW, R3A, R3W, and R3B are inhibited.

When the WL2 bit is enabled, writes to the TCON1

register bits R2HW, R2A, R2W, and R2B are inhibited.

On a POR/BOR these registers are loaded with

1FFh (9-bits), for all terminals connected. The Host

Controller needs to detect the POR/BOR event and

then update the Volatile TCON register values.

DS22233A-page 36

MCP434X/436X

(1)

REGISTER 4-2:

TCON0 BITS

R-1

D8

R/W-1

R1HW

R/W-1

R1W

R/W-1

R1B

R/W-1

R0HW

R/W-1

R0A

R/W-1

R0W

R/W-1

R0B

R1A

bit 8

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8

bit 7

D8: Reserved. Forced to “1”

R1HW: Resistor 1 Hardware Configuration Control bit

This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin

1= Resistor 1 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 1 is forced to the hardware pin “shutdown” configuration

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network

1= P1A pin is connected to the Resistor 1 Network

0= P1A pin is disconnected from the Resistor 1 Network

R1W: Resistor 1 Wiper (P1W pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network

1= P1W pin is connected to the Resistor 1 Network

0= P1W pin is disconnected from the Resistor 1 Network

R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network

1= P1B pin is connected to the Resistor 1 Network

0= P1B pin is disconnected from the Resistor 1 Network

R0HW: Resistor 0 Hardware Configuration Control bit

This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin

1= Resistor 0 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 0 is forced to the hardware pin “shutdown” configuration

R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network

1= P0A pin is connected to the Resistor 0 Network

0= P0A pin is disconnected from the Resistor 0 Network

R0W: Resistor 0 Wiper (P0W pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network

1= P0W pin is connected to the Resistor 0 Network

0= P0W pin is disconnected from the Resistor 0 Network

R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network

1= P0B pin is connected to the Resistor 0 Network

0= P0B pin is disconnected from the Resistor 0 Network

Note 1: These bits do not affect the wiper register values.

DS22233A-page 37

MCP434X/436X

(1)

REGISTER 4-3:

TCON1 BITS

R-1

D8

R/W-1

R3HW

R/W-1

R3W

R/W-1

R3B

R/W-1

R2HW

R/W-1

R2A

R/W-1

R2W

R/W-1

R2B

R3A

bit 8

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8

bit 7

D8: Reserved. Forced to “1”

R3HW: Resistor 3 Hardware Configuration Control bit

This bit forces Resistor 3 into the “shutdown” configuration of the Hardware pin

1= Resistor 3 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 3 is forced to the hardware pin “shutdown” configuration

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R3A: Resistor 3 Terminal A (P3A pin) Connect Control bit

This bit connects/disconnects the Resistor 3 Terminal A to the Resistor 3 Network

1= P3A pin is connected to the Resistor 3 Network

0= P3A pin is disconnected from the Resistor 3 Network

R3W: Resistor 3 Wiper (P3W pin) Connect Control bit

This bit connects/disconnects the Resistor 3 Wiper to the Resistor 3 Network

1= P3W pin is connected to the Resistor 3 Network

0= P3W pin is disconnected from the Resistor 3 Network

R3B: Resistor 3 Terminal B (P3B pin) Connect Control bit

This bit connects/disconnects the Resistor 3 Terminal B to the Resistor 3 Network

1= P3B pin is connected to the Resistor 3 Network

0= P3B pin is disconnected from the Resistor 3 Network

R2HW: Resistor 2 Hardware Configuration Control bit

This bit forces Resistor 2 into the “shutdown” configuration of the Hardware pin

1= Resistor 2 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 2 is forced to the hardware pin “shutdown” configuration

R2A: Resistor 2 Terminal A (P0A pin) Connect Control bit

This bit connects/disconnects the Resistor 2 Terminal A to the Resistor 2 Network

1= P2A pin is connected to the Resistor 2 Network

0= P2A pin is disconnected from the Resistor 2 Network

R2W: Resistor 2 Wiper (P0W pin) Connect Control bit

This bit connects/disconnects the Resistor 2 Wiper to the Resistor 2 Network

1= P2W pin is connected to the Resistor 2 Network

0= P2W pin is disconnected from the Resistor 2 Network

R2B: Resistor 2 Terminal B (P2B pin) Connect Control bit

This bit connects/disconnects the Resistor 2 Terminal B to the Resistor 2 Network

1= P2B pin is connected to the Resistor 2 Network

0= P2B pin is disconnected from the Resistor 2 Network

Note 1: These bits do not affect the wiper register values.

DS22233A-page 38

MCP434X/436X

5.1

Resistor Ladder Module

5.0

RESISTOR NETWORK

The resistor ladder is a series of equal value resistors

(R_S) with a connection point (tap) between the two

resistors. The total number of resistors in the series

(ladder) determines the R_ABresistance (see

Figure 5-1). The end points of the resistor ladder are

connected to analog switches which are connected to

the device Terminal A and Terminal B pins. The R_AB

(and R_S) resistance has small variations over voltage

and temperature.

The Resistor Network has either 7-bit or 8-bit

resolution. Each Resistor Network allows zero scale to

full scale connections. Figure 5-1 shows a block

diagram for the resistive network of a device.

The Resistor Network is made up of several parts.

These include:

• Resistor Ladder

• Wiper

• Shutdown (Terminal Connections)

For an 8-bit device, there are 256 resistors in a string

between terminal A and terminal B. The wiper can be

set to tap onto any of these 256 resistors thus providing

257 possible settings (including terminal A and terminal

B).

Devices have either four resistor networks. These are

referred to as Pot 0, Pot 1 Pot 2, and Pot 3.

A

For a 7-bit device, there are 128 resistors in a string

between terminal A and terminal B. The wiper can be

set to tap onto any of these 128 resistors thus providing

129 possible settings (including terminal A and terminal

B).

8-Bit

N =

257

7-Bit

N =

128

(100h)

(80h)

(1)

R_W

R_S

Equation 5-1 shows the calculation for the step

resistance.

256

(FFh)

127

(7Fh)

(1)

R_W

EQUATION 5-1:

R CALCULATION

S

255

(FEh)

126

(7Eh)

R_AB

R_S= -------------

8-bit Device

R_AB

(256)

W

R_AB

R_S= -------------

(128)

7-bit Device

1

(01h)

(1)

R_W

R_S

0

(00h)

Analog Mux

B

Note 1: The wiper resistance is dependent on

several factors including, wiper code,

device V_DD, Terminal voltages (on A, B,

and W), and temperature.

Also for the same conditions, each tap

selection resistance has a small variation.

This R_Wvariation has greater effects on

some specifications (such as INL) for the

smaller resistance devices (5.0 kΩ)

compared to larger resistance devices

(100.0 kΩ).

FIGURE 5-1:

Resistor Block Diagram.

DS22233A-page 39

MCP434X/436X

5.2

Wiper

5.3

WiperLock™ Technology

Each tap point (between the R_Sresistors) is a

connection point for an analog switch. The opposite

side of the analog switch is connected to a common

signal which is connected to the Terminal W (Wiper)

pin.

The MCP43XX device’s WiperLock technology allows

application-specific calibration settings to be secured in

the EEPROM without requiring the use of an additional

write-protect pin. There are four WiperLock Technology

configuration bits (WL0, WL1, WL2, and WL3). These

bits prevent the Non-Volatile and Volatile addresses

and bits for the specified resistor network from being

written.

A value in the volatile wiper register selects which

analog switch to close, connecting the W terminal to

the selected node of the resistor ladder.

The WiperLock technology prevents the serial

commands from doing the following:

The wiper can connect directly to Terminal B or to

Terminal A. A zero scale connections, connects the

Terminal W (wiper) to Terminal B (wiper setting of

000h). A full scale connections, connects the Terminal

W (wiper) to Terminal A (wiper setting of 100h or 80h).

In these configurations the only resistance between the

Terminal W and the other Terminal (A or B) is that of the

analog switches.

• Changing a volatile wiper value

• Writing to the specified non-volatile wiper memory

location

• Changing the related volatile TCON register bits

For either Resistor Network 0, Resistor Network 1,

Resistor Network 2, or Resistor Network 3 (Potx), the

WLx bit controls the following:

A wiper setting value greater than full scale (wiper

setting of 100h for 8-bit device or 80h for 7-bit devices)

will also be a Full Scale setting (Terminal W (wiper)

connected to Terminal A). Table 5-1 illustrates the full

wiper setting map.

• Non-Volatile Wiper Register

• Volatile Wiper Register

• Volatile TCON register bits RxHW, RxA, RxW, and

RxB

Equation 5-2 illustrates the calculation used to

determine the resistance between the wiper and

terminal B.

High Voltage commands are required to enable and

disable WiperLock. Please refer to the Modify Write

Protect or WiperLock Technology (High Voltage)

command for operation.

EQUATION 5-2:

R

CALCULATION

WB

5.3.1

POR/BOR OPERATION WHEN

WIPERLOCK TECHNOLOGY

ENABLED

R_AB

N

R_WB= ------------- + R_W

8-bit Device

(256)

N = 0 to 256 (decimal)

The WiperLock Technology state is not affected by a

POR/BOR event. A POR/BOR event will load the

Volatile Wiper register value with the Non-Volatile

Wiper register value, refer to Section 4.1.

R_AB

N

7-bit Device

R_WB= ------------- + R_W

(128)

N = 0 to 128 (decimal)

TABLE 5-1:

Wiper Setting

VOLATILE WIPER VALUE VS.

WIPER POSITION MAP

Properties

7-bit

8-bit

3FFh – 3FFh – Reserved (Full Scale (W = A)),

081h

101h Increment and Decrement

commands ignored

080h

100h Full Scale (W = A),

Increment commands ignored

07Fh – 0FFh – W = N

041h

081h

040h

080h W = N (Mid Scale)

03Fh – 07Fh – W = N

001h

000h

000h Zero Scale (W = B)

Decrement command ignored

DS22233A-page 40

MCP434X/436X

The RxHW bit does NOT corrupt the values in the

Volatile Wiper Registers nor the TCON register. When

the Shutdown mode is exited (RxHW bit = “1”):

5.4

Shutdown

Shutdown is used to minimize the device’s current

consumption. The MCP43XX has one method to

achieve this. This is:

• The device returns to the Wiper setting specified

by the Volatile Wiper value

• The TCON register bits return to controlling the

terminal connection state

• Terminal Control Register (TCON)

This is different from the MCP42XXX devices in that the

Hardware Shutdown Pin (SHDN) has been replaced by

a RESET pin. The Hardware Shutdown Pin function is

still available via software commands to the TCON

register.

A

W

5.4.1

TERMINAL CONTROL REGISTER

(TCON)

The Terminal Control (TCON) register is a volatile

register used to configure the connection of each

resistor network terminal pin (A, B, and W) to the

Resistor Network. These registers are shown in

Register 4-2 and Register 4-3.

B

FIGURE 5-2:

Resistor Network Shutdown

State (RxHW = ‘0’).

The RxHW bits forces the selected resistor network

into the same state as the MCP42X1’s SHDN pin.

Alternate low power configurations may be achieved

with the RxA, RxW, and RxB bits.

When the RxHW bit is “0”:

• The P0A, P1A, P2A, and P3A terminals are

disconnected

• The P0W, P1W, P2W, and P3W terminals are

simultaneously connect to the P0B, P1B, P2B,

and P3B terminals, respectively (see Figure 5-2)

Note:

When the RxHW bit forces the resistor

network into the hardware SHDN state,

the state of the TCON0 or TCON1

register’s RxA, RxW, and RxB bits is

overridden (ignored). When the state of

the RxHW bit no longer forces the resistor

network into the hardware SHDN state,

the TCON0 or TCON1 register’s RxA,

RxW, and RxB bits return to controlling the

terminal connection state. In other words,

the RxHW bit does not corrupt the state of

the RxA, RxW, and RxB bits.

DS22233A-page 41

MCP434X/436X

NOTES:

DS22233A-page 42

MCP434X/436X

Typical SPI Interface is shown in Figure 6-1. In the SPI

interface, the Master’s Output pin is connected to the

Slave’s Input pin and the Master’s Input pin is

connected to the Slave’s Output pin.

6.0

SERIAL INTERFACE (SPI)

The MCP43XX devices support the SPI serial protocol.

This SPI operates in the slave mode (does not

generate the serial clock).

The MCP4XXX SPI’s module supports two (of the four)

standard SPI modes. These are Mode 0,0 and 1,1.

The SPI mode is determined by the state of the SCK

pin (V_IHor V_IL) on the when the CS pin transitions from

inactive (V_IH) to active (V_ILor V_IHH).

The SPI interface uses up to four pins. These are:

• CS - Chip Select

• SCK - Serial Clock

• SDI - Serial Data In

• SDO - Serial Data Out

All SPI interface signals are high-voltage tolerant.

Typical SPI Interface Connections

Host

MCP4XXX

Controller

(Master Out - Slave In (MOSI))

(Master In - Slave Out (MISO))

SDI

SDO

SCK

CS

SDO

SDI

SCK

(1)

I/O

Note 1: If High voltage commands are desired, some type of external circuitry needs to be implemented.

FIGURE 6-1: Typical SPI Interface Block Diagram.

DS22233A-page 43

MCP434X/436X

6.1.4

THE CS SIGNAL

6.1

SDI, SDO, SCK, and CS Operation

The Chip Select (CS) signal is used to select the device

and frame a command sequence. To start a command,

or sequence of commands, the CS signal must

transition from the inactive state (V_IH) to an active state

(V_ILor V_IHH).

The operation of the four SPI interface pins are

discussed in this section. These pins are:

• SDI (Serial Data In)

• SDO (Serial Data Out)

• SCK (Serial Clock)

• CS (Chip Select)

After the CS signal has gone active, the SDO pin is

driven and the clock bit counter is reset.

The serial interface works on either 8-bit or 16-bit

boundaries depending on the selected command. The

Chip Select (CS) pin frames the SPI commands.

Note:

There is a required delay after the CS pin

goes active to the 1st edge of the SCK pin.

6.1.1

SERIAL DATA IN (SDI)

If an error condition occurs for an SPI command, then

the Command byte’s Command Error (CMDERR) bit

(on the SDO pin) will be driven low (V_IL). To exit the

error condition, the user must take the CS pin to the V_IH

level.

The Serial Data In (SDI) signal is the data signal into

the device. The value on this pin is latched on the rising

edge of the SCK signal.

6.1.2

SERIAL DATA OUT (SDO)

When the CS pin returns to the inactive state (V_IH) the

SPI module resets (including the address pointer).

While the CS pin is in the inactive state (V_IH), the serial

interface is ignored. This allows the Host Controller to

interface to other SPI devices using the same SDI,

SDO, and SCK signals.

The Serial Data Out (SDO) signal is the data signal out

of the device. The value on this pin is driven on the

falling edge of the SCK signal.

Once the CS pin is forced to the active level (V_ILor

V_IHH), the SDO pin will be driven. The state of the SDO

pin is determined by the serial bit’s position in the

command, the command selected, and if there is a

command error state (CMDERR).

The CS pin has an internal pull-up resistor. The resistor

is disabled when the voltage on the CS pin is at the V_IL

level. This means that when the CS pin is not driven,

the internal pull-up resistor will pull this signal to the V_IH

level. When the CS pin is driven low (V_IL), the

resistance becomes very large to reduce the device

current consumption.

6.1.3

SERIAL CLOCK (SCK)

(SPI FREQUENCY OF OPERATION)

The SPI interface is specified to operate up to 10 MHz.

The actual clock rate depends on the configuration of

the system and the serial command used. Table 6-1

shows the SCK frequency for different configurations.

The high voltage capability of the CS pin allows High

Voltage commands. High Voltage commands allow the

device’s WiperLock Technology and write protect

features to be enabled and disabled.

TABLE 6-1:

SCK FREQUENCY

Command

Write,

Memory Type Access

Read

Increment,

Decrement

Non-Volatile SDI, SDO

Memory

10 MHz

10 MHz ^{(1, 2)}

Volatile

SDI, SDO

10 MHz

Memory

Note 1: Non-Volatile memory does not support the

Increment or Decrement command.

2: After a Write command, the internal write

cycle must complete before the next SPI

command is received.

3: This is the maximum clock frequency

without an external pull-up resistor.

DS22233A-page 44

MCP434X/436X

6.2.2

MODE 1,1

6.2

The SPI Modes

In Mode 1,1: SCK idle state = high (V_IH), data is

clocked in on the SDI pin on the rising edge of SCK and

clocked out on the SDO pin on the falling edge of SCK.

The SPI module supports two (of the four) standard SPI

modes. These are Mode 0,0 and 1,1. The mode is

determined by the state of the SDI pin on the rising

edge of the 1st clock bit (of the 8-bit byte).

6.3

SPI Waveforms

6.2.1

MODE 0,0

Figure 6-2 through Figure 6-5 show the different SPI

command waveforms. Figure 6-2 and Figure 6-3 are

read and write commands. Figure 6-4 and Figure 6-5

are increment and decrement commands. The high

voltage increment and decrement commands are used

to enable and disable WiperLock Technology and Write

Protect.

In Mode 0,0: SCK idle state = low (V_IL), data is clocked

in on the SDI pin on the rising edge of SCK and clocked

out on the SDO pin on the falling edge of SCK.

V

IHH

V

IH

CS

V

IL

SCK

Write to

SSPBUF

CMDERR bit

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5

SDO

bit4 bit3 bit2 bit1

bit0

AD3 AD2 AD1 AD0

bit15 bit14 bit13 bit12

X

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDI

bit9

bit8 bit7 bit6 bit5

bit4 bit3 bit2 bit1

bit0

C1

C0

Input

Sample

FIGURE 6-2:

16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).

V

IHH

V

IH

CS

V

IL

SCK

Write to

SSPBUF

CMDERR bit

SDO

bit15 bit14 bit13 bit12 bit11 bit10 bit9

bit8 bit7 bit6 bit5

bit4 bit3 bit2 bit1

bit0

AD3 AD2 AD1 AD0

bit15 bit14 bit13 bit12

X

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDI

bit9

bit8 bit7 bit6 bit5

bit4 bit3 bit2 bit1

bit0

C1

C0

Input

Sample

FIGURE 6-3:

16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).

DS22233A-page 45

MCP434X/436X

V

IHH

IL

V

IH

CS

SCK

Write to

SSPBUF

CMDERR bit

“1” = Valid Command

“0” = Invalid Command

SDO

SDI

bit6

bit2

bit5

bit4

bit1

bit0

bit7

bit3

AD1

AD2

X

AD0

C0

AD3

bit7

C1

X

bit0

Input

Sample

FIGURE 6-4:

8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock

Technology) - SPI Waveform with PIC MCU (Mode 1,1).

V

IHH

V

IH

CS

V

IL

SCK

Write to

SSPBUF

CMDERR bit

“1” = Valid Command

“0” = Invalid Command

bit6

AD2

bit2

C0

bit5

bit4

AD0

bit1

bit0

SDO

SDI

bit7

bit3

C1

AD1

X

AD3

bit7

X

bit0

Input

Sample

FIGURE 6-5:

8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock

Technology) - SPI Waveform with PIC MCU (Mode 0,0).

DS22233A-page 46

MCP434X/436X

7.1

Command Byte

7.0

DEVICE COMMANDS

The Command Byte has three fields, the Address, the

Command, and 2 Data bits, see Figure 7-1. Currently

only one of the data bits is defined (D8). This is for the

Write command.

The MCP43XX’s SPI command format supports 16

memory address locations and four commands. Each

command has two modes. These are:

• Normal Serial Commands

The device memory is accessed when the master

sends a proper Command Byte to select the desired

operation. The memory location getting accessed is

contained in the Command Byte’s AD3:AD0 bits. The

action desired is contained in the Command Byte’s

C1:C0 bits, see Table 7-1. C1:C0 determines if the

desired memory location will be read, written,

Incremented (wiper setting +1) or Decremented (wiper

setting -1). The Increment and Decrement commands

are only valid on the volatile wiper registers, and in

High Voltage commands to enable/disable WiperLock

Technology and Software Write Protect.

• High-Voltage Serial Commands

Normal serial commands are those where the CS pin is

driven to V_IL. With High-Voltage Serial Commands, the

CS pin is driven to V_IHH. In each mode, there are four

possible commands. These commands are shown in

Table 7-1.

The 8-bit commands (Increment Wiper and

Decrement Wiper commands) contain a Command

Byte, see Figure 7-1, while 16-bit commands (Read

Data and Write Data commands) contain a Command

Byte and a Data Byte. The Command Byte contains

two data bits, see Figure 7-1.

As the Command Byte is being loaded into the device

(on the SDI pin), the device’s SDO pin is driving. The

SDO pin will output high bits for the first six bits of that

command. On the 7th bit, the SDO pin will output the

CMDERR bit state (see Section 7.3 “Error

Condition”). The 8th bit state depends on the

command selected.

Table 7-2 shows the supported commands for each

memory location and the corresponding values on the

SDI and SDO pins.

Table 7-3 shows an overview of all the SPI commands

and their interaction with other device features.

TABLE 7-1:

C1:C0

COMMAND BIT OVERVIEW

Operates on

# of

Bits

Volatile/

Non-Volatile

memory

Bit

Command

States

11

00

01

10

Read Data

16-Bits Both

Write Data

16-Bits Both

Increment ⁽¹⁾

Decrement ⁽¹⁾

8-Bits Volatile Only

Note 1: High Voltage Increment and Decrement

commands on select non-volatile memory

locations

enable/disable

WiperLock

Technology and the software Write

Protect feature.

16-bit Command

Data Byte

8-bit Command

Command Byte

A A A A C C D D D D D D D D D D

D D D D 1 0 9 8 7 6 5 4 3 2 1 0

3 2 1 0

A A A A C C D D

D D D D 1 0 9 8

3 2 1 0

Command

Bits

C C

1 0

Data

Bits

0 0 = Write Data

0 1 = INCR

Data

Bits

Memory

Address

Memory

Address

1 0 = DECR

1 1 = Read Data

Command

Bits

Command

Bits

FIGURE 7-1:

General SPI Command Formats.

DS22233A-page 47

MCP434X/436X

TABLE 7-2:

MEMORY MAP AND THE SUPPORTED COMMANDS

Address

SPI String (Binary)

Data

Command

(10-bits) ⁽¹⁾

Value

Function

MOSI (SDI pin)

MISO (SDO pin) ⁽²⁾

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

Write Data

nn nnnn nnnn

—

0000 00nn nnnn nnnn

0000 11nn nnnn nnnn

0000 0100

00h

Volatile Wiper 0

Read Data

Increment Wiper

Decrement Wiper

Write Data

—

0000 1000

1111 1111

nn nnnn nnnn

—

0001 00nn nnnn nnnn

0001 11nn nnnn nnnn

0001 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

01h

02h

03h

Volatile Wiper 1

NV Wiper 0

Read Data

Increment Wiper

Decrement Wiper

Write Data

—

0001 1000

1111 1111

nn nnnn nnnn

—

0010 00nn nnnn nnnn

0010 11nn nnnn nnnn

0010 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

Read Data

(3)

(4)

HV Inc. (WL0 DIS)

HV Dec. (WL0 EN)

Write Data

—

0010 1000

1111 1111

nn nnnn nnnn

—

0011 00nn nnnn nnnn

0011 11nn nnnn nnnn

0011 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

NV Wiper 1

Read Data

(3)

(4)

HV Inc. (WL1 DIS)

HV Dec. (WL1 EN)

Write Data

—

0011 1000

1111 1111

04h ⁽⁵⁾Volatile

TCON 0 Register

05h ⁽⁵⁾Status Register

nn nnnn nnnn

—

0100 00nn nnnn nnnn

0100 11nn nnnn nnnn

0101 11nn nnnn nnnn

0110 00nn nnnn nnnn

0110 11nn nnnn nnnn

0110 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

Read Data

Write Data

06h

07h

08h

09h

Volatile Wiper 2

Volatile Wiper 3

NV Wiper 2

Read Data

Increment Wiper

Decrement Wiper

Write Data

—

0110 1000

1111 1111

nn nnnn nnnn

—

0111 00nn nnnn nnnn

0111 11nn nnnn nnnn

0111 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

Read Data

Increment Wiper

Decrement Wiper

Write Data

—

0111 1000

1111 1111

nn nnnn nnnn

—

1000 00nn nnnn nnnn

1000 11nn nnnn nnnn

1000 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

Read Data

(3)

(4)

HV Inc. (WL2 DIS)

HV Dec. (WL2 EN)

Write Data

—

1000 1000

1111 1111

nn nnnn nnnn

—

1001 00nn nnnn nnnn

1001 11nn nnnn nnnn

1001 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

NV Wiper 3

Read Data

(3)

(4)

HV Inc. (WL3 DIS)

HV Dec. (WL3 EN)

Write Data

—

1001 1000

1111 1111

0Ah ⁽⁵⁾Volatile

TCON 1 Register

nn nnnn nnnn

—

1010 00nn nnnn nnnn

1010 11nn nnnn nnnn

1011 00nn nnnn nnnn

1011 11nn nnnn nnnn

1100 00nn nnnn nnnn

1100 11nn nnnn nnnn

1101 00nn nnnn nnnn

1101 11nn nnnn nnnn

1110 00nn nnnn nnnn

1110 11nn nnnn nnnn

1111 00nn nnnn nnnn

1111 11nn nnnn nnnn

1111 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

Read Data

0Bh ⁽⁵⁾Data EEPROM

0Ch ⁽⁵⁾Data EEPROM

0Dh ⁽⁵⁾Data EEPROM

0Eh ⁽⁵⁾Data EEPROM

Write Data

Read Data

Write Data

Read Data

Write Data

Read Data

Write Data

Read Data

Write Data

0Fh

Data EEPROM

Read Data

(3)

HV Inc. (WP DIS)

HV Dec. (WP EN)

(4)

—

1111 1000

1111 1111

Note 1:

2:

The Data Memory is only 9-bits wide, so the MSb is ignored by the device.

All these Address/Command combinations are valid, so the CMDERR bit is set. Any other Address/Command combination is a

command error state and the CMDERR bit will be clear.

3:

4:

5:

Disables WiperLock Technology for wiper 0, wiper 1, wiper 2, wiper3, or disables Write Protect.

Enables WiperLock Technology for wiper 0, wiper 1, wiper 2, wiper3, or enables Write Protect.

Increment or Decrement commands are invalid for these addresses.

DS22233A-page 48

MCP434X/436X

7.3.1

ABORTING A TRANSMISSION

7.2

Data Byte

All SPI transmissions must have the correct number of

SCK pulses to be executed. The command is not

executed until the complete number of clocks have

been received. Some commands also require the CS

pin to be forced inactive (V_IH). If the CS pin is forced to

the inactive state (V_IH) the serial interface is reset.

Partial commands are not executed.

Only the Read Command and the Write Command use

the Data Byte, see Figure 7-1. These commands

concatenate the 8 bits of the Data Byte with the one

data bit (D8) contained in the Command Byte to form

9-bits of data (D8:D0). The Command Byte format

supports up to 9-bits of data so that the 8-bit resistor

network can be set to Full Scale (100h or greater). This

allows wiper connections to Terminal A and to

Terminal B.

SPI is more susceptible to noise than other bus

protocols. The most likely case is that this noise

corrupts the value of the data being clocked into the

MCP43XX or the SCK pin is injected with extra clock

pulses. This may cause data to be corrupted in the

device, or a command error to occur, since the address

and command bits were not a valid combination. The

extra SCK pulse will also cause the SPI data (SDI) and

clock (SCK) to be out of sync. Forcing the CS pin to the

inactive state (V_IH) resets the serial interface. The SPI

interface will ignore activity on the SDI and SCK pins

until the CS pin transition to the active state is detected

(V_IHto V_ILor V_IHto V_IHH).

The D9 bit is currently unused, and corresponds to the

position on the SDO data of the CMDERR bit.

7.3

Error Condition

The CMDERR bit indicates if the four address bits

received (AD3:AD0) and the two command bits

received (C1:C0) are

a valid combination (see

Table 4-1). The CMDERR bit is high if the combination

is valid and low if the combination is invalid.

The command error bit will also be low if a write to a

Non-Volatile Address has been specified and another

SPI command occurs before the CS pin is driven

inactive (V_IH).

Note 1: When data is not being received by the

MCP43XX, It is recommended that the

CS pin be forced to the inactive level (V_IL)

SPI commands that do not have a multiple of 8 clocks

are ignored.

2: It is also recommended that long

continuous command strings should be

broken down into single commands or

shorter continuous command strings.

This reduces the probability of noise on

the SCK pin corrupting the desired SPI

commands.

Once an error condition has occurred, any following

commands are ignored. All following SDO bits will be

low until the CMDERR condition is cleared by forcing

the CS pin to the inactive state (V_IH).

DS22233A-page 49

MCP434X/436X

7.4

Continuous Commands

Note 1: It is recommended that while the CS pin is

active, only one type of command should

be issued. When changing commands, it

is recommended to take the CS pin

inactive then force it back to the active

state.

The device supports the ability to execute commands

continuously. While the CS pin is in the active state (V_IL

or V_IHH). Any sequence of valid commands may be

received.

The following example is a valid sequence of events:

2: It is also recommended that long

command strings should be broken down

into shorter command strings. This

reduces the probability of noise on the

SCK pin corrupting the desired SPI

command string.

1. CS pin driven active (V_ILor V_IHH).

2. Read Command.

3. Increment Command (Wiper 0).

4. Increment Command (Wiper 0).

5. Decrement Command (Wiper 1).

6. Write Command (Volatile memory).

7. Write Command (Non-Volatile memory).

8. CS pin driven inactive (V_IH).

DS22233A-page 50

MCP434X/436X

TABLE 7-3:

COMMANDS

Operates on

Volatile/

Non-Volatile (V_IHH) on

High

Voltage

Works

when

Wiper is

“locked”?

Writes

Value in

EEPROM

Impact on

WiperLock or

Write Protect

# of

Bits

Command Name

memory

CS pin?

Write Data

16-Bits

8-Bits

16-Bits

8-Bits

Yes ⁽¹⁾

—

Both

—

unlocked ⁽¹⁾

unchanged

No

Yes

No

Yes

Read Data

Increment Wiper

—

Volatile Only

Both

—

Decrement Wiper

—

High Voltage Write Data

High Voltage Read Data

High Voltage Increment Wiper

High Voltage Decrement Wiper

Yes

—

Yes

Both

—

Volatile Only

—

(2)

Modify Write Protect or Wiper-

Lock Technology (High Voltage) -

Enable

—

Non-Volatile

Only ⁽²⁾

locked/

protected ⁽²⁾

(3)

Modify Write Protect or Wiper-

Lock Technology (High Voltage) -

Disable

8-Bits

—

Non-Volatile

Only ⁽³⁾

Yes

unlocked/

unprotected

Yes

(3)

Note 1: This command will only complete if wiper is “unlocked” (WiperLock Technology is Disabled).

2: If the command is executed using address 02h, 03h, 08h, or 09h then that corresponding wiper is locked or

if with address 0Fh, then Write Protect is enabled.

3: If the command is executed using with address 02h, 03h, 08h, or 09h, then that corresponding wiper is

unlocked or if with address 0Fh, then Write Protect is disabled.

DS22233A-page 51

MCP434X/436X

7.5.2

SINGLE WRITE TO NON-VOLATILE

MEMORY

7.5

Write Data

Normal and High Voltage

The sequence to write to a single non-volatile memory

location is the same as a single write to volatile memory

with the exception that after the CS pin is driven

inactive (V_IH), the EEPROM write cycle (t_WC) is started.

A write cycle will not start if the write command isn’t

exactly 16 clocks pulses. This protects against system

issues from corrupting the Non-Volatile memory

locations.

The Write command is a 16-bit command. The Write

Command can be issued to both the Volatile and

Non-Volatile memory locations. The format of the

command is shown in Figure 7-2.

A Write command to a Volatile memory location

changes that location after a properly formatted Write

Command (16-clock) have been received.

A Write command to a Non-Volatile memory location

will only start a write cycle after a properly formatted

Write Command (16-clock) have been received and the

CS pin transitions to the inactive state (V_IH).

After the CS pin is driven inactive (V_IH), the serial

interface may immediately be re-enabled by driving the

CS pin to the active state (V_ILor V_IHH).

During an EEPROM write cycle, only serial commands

to Volatile memory (addresses 00h, 01h, 04h, 05h, 06h,

07h, and 0Ah) are accepted. All other serial commands

are ignored until the EEPROM write cycle (t_wc) com-

pletes. This allows the Host Controller to operate on the

Volatile Wiper registers and the TCON register, and to

Read the Status Register. The EEWA bit in the Status

register indicates the status of an EEPROM Write

Cycle.

Note:

Writes to certain memory locations will be

dependant on the state of the WiperLock

Technology bits and the Write Protect bit.

7.5.1

SINGLE WRITE TO VOLATILE

MEMORY

The write operation requires that the CS pin be in the

active state (V_ILor V_IHH). Typically, the CS pin will be in

the inactive state (V_IH) and is driven to the active state

(V_IL). The 16-bit Write Command (Command Byte and

Data Byte) is then clocked in on the SCK and SDI pins.

Once all 16 bits have been received, the specified

volatile address is updated. A write will not occur if the

write command isn’t exactly 16 clocks pulses. This

protects against system issues from corrupting the

Non-Volatile memory locations.

Once a write command to a Non-Volatile memory

location has been received, NO other SPI commands

should be received before the CS pin transitions to the

inactive state (V_IH) or the current SPI command will

have a Command Error (CMDERR) occur.

Figure 6-2 and Figure 6-3 show possible waveforms

for a single write.

COMMAND BYTE

DATA BYTE

A

D

3

A

D

2

A

D

1

A

D

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

SDI

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid Address/Command combination

Invalid Address/Command combination ⁽¹⁾

SDO

Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

FIGURE 7-2:

Write Command - SDI and SDO States.

DS22233A-page 52

MCP434X/436X

7.5.3

CONTINUOUS WRITES TO

VOLATILE MEMORY

7.5.4

CONTINUOUS WRITES TO

NON-VOLATILE MEMORY

Continuous writes are possible only when writing to the

volatile memory registers (address 00h, 01h, and 04h).

Continuous writes to non-volatile memory are not

allowed, and attempts to do so will result in a command

error (CMDERR) condition.

Figure 7-3 shows the sequence for three continuous

writes. The writes do not need to be to the same volatile

memory address.

COMMAND BYTE

DATA BYTE

A

D

3

A

D

2

A

D

1

A

D

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

SDI

1

0

1

0

1*

1

SDO

A

D

3

A

D

2

A

D

1

A

D

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

1

0

1

0

1*

1

A

D

3

A

D

2

A

D

1

A

D

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

1

1*

1

Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be

driven low until the CS pin is driven inactive (V_IH).

FIGURE 7-3:

Continuous Write Sequence (Volatile Memory only).

DS22233A-page 53

MCP434X/436X

7.6.1

SINGLE READ

7.6

Read Data

Normal and High Voltage

The read operation requires that the CS pin be in the

active state (V_ILor V_IHH). Typically, the CS pin will be in

the inactive state (V_IH) and is driven to the active state

(V_ILor V_IHH). The 16-bit Read Command (Command

Byte and Data Byte) is then clocked in on the SCK and

SDI pins. The SDO pin starts driving data on the 7th bit

(CMDERR bit) and the addressed data comes out on

the 8th through 16th clocks. Figure 6-2 through

Figure 6-3 show possible waveforms for a single read.

The Read command is a 16-bit command. The Read

Command can be issued to both the Volatile and

Non-Volatile memory locations. The format of the

command is shown in Figure 7-4.

The first 6 bits of the Read command determine the

address and the command. The 7th clock will output

the CMDERR bit on the SDO pin. The remaining

9-clocks the device will transmit the 9 data bits (D8:D0)

of the specified address (AD3:AD0).

Figure 7-4 shows the SDI and SDO information for a

Read command.

During a write cycle (Write or High Voltage Write to a

Non-Volatile memory location) the Read command can

only read the Volatile memory locations. By reading the

Status Register (04h), the Host Controller can

determine when the write cycle has completed (via the

state of the EEWA bit).

COMMAND BYTE

DATA BYTE

A

D

3

A

D

2

A

D

1

A

D

0

1

X

SDI

1

0

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D Valid Address/Command combination

0

SDO

1

0

Attempted Non-Volatile Memory Read

during Non-Volatile Memory Write Cycle

READ DATA

Read Command - SDI and SDO States.

FIGURE 7-4:

DS22233A-page 54

MCP434X/436X

Figure 7-5 shows the sequence for three continuous

reads. The reads do not need to be to the same

memory address.

7.6.2

CONTINUOUS READS

Continuous reads allow the devices memory to be read

quickly. Continuous reads are possible to all memory

locations. If a non-volatile memory write cycle is

occurring, then Read commands may only access the

volatile memory locations.

COMMAND BYTE

DATA BYTE

A

D

3

A

D

2

A

D

1

A

D

0

1

X

SDI

1

1*

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

SDO

A

D

3

A

D

2

A

D

1

A

D

0

1

X

1

1*

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

D

3

A

D

2

A

D

1

A

D

0

1

X

1

1*

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be

driven low until the CS pin is driven inactive (V_IH).

FIGURE 7-5:

Continuous Read Sequence.

DS22233A-page 55

MCP434X/436X

7.7.1

SINGLE INCREMENT

7.7

Increment Wiper

Normal and High Voltage

Typically, the CS pin starts at the inactive state (V_IH),

but may be already be in the active state due to the

completion of another command.

The Increment Command is an 8-bit command. The

Increment Command can only be issued to volatile

memory locations. The format of the command is

shown in Figure 7-6.

Figure 6-4 through Figure 6-5 show possible

waveforms for a single increment. The increment

operation requires that the CS pin be in the active state

(V_ILor V_IHH). Typically, the CS pin will be in the inactive

state (V_IH) and is driven to the active state (V_ILor V_IHH).

The 8-bit Increment Command (Command Byte) is

then clocked in on the SDI pin by the SCK pins. The

SDO pin drives the CMDERR bit on the 7th clock.

An Increment Command to the volatile memory

location changes that location after

formatted command (8-clocks) have been received.

a properly

Increment commands provide a quick and easy

method to modify the value of the volatile wiper location

by +1 with minimal overhead.

The wiper value will increment up to 100h on 8-bit

devices and 80h on 7-bit devices. After the wiper value

has reached Full Scale (8-bit =100h, 7-bit =80h), the

wiper value will not be incremented further. If the Wiper

register has a value between 101h and 1FFh, the

Increment command is disabled. See Table 7-4 for

additional information on the Increment Command

versus the current volatile wiper value.

COMMAND BYTE

(INCR COMMAND (n+1))

A

D

3

A

D

2

A

D

1

A

D

0

1

X

SDI

1

1*

0

1

0

Note 1, 2

Note 1, 3

The Increment operations only require the Increment

SDO

command byte while the CS pin is active (V_ILor V_IHH

)

for a single increment.

Note 1: Only functions when writing the volatile

After the wiper is incremented to the desired position,

the CS pin should be forced to V_IHto ensure that

unexpected transitions on the SCK pin do not cause

the wiper setting to change. Driving the CS pin to V_IH

should occur as soon as possible (within device

specifications) after the last desired increment occurs.

wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination.

3: Invalid Address/Command combination

all following SDO bits will be low until the

CMDERR condition is cleared.

(the CS pin is forced to the inactive

state).

TABLE 7-4:

INCREMENT OPERATION VS.

VOLATILE WIPER VALUE

4: If a Command Error (CMDERR) occurs

at this bit location (*), then all following

SDO bits will be driven low until the CS

pin is driven inactive (V_IH).

Current Wiper

Setting

Increment

Wiper (W)

Command

Properties

7-bit

Pot

8-bit

Pot

Operates?

FIGURE 7-6:

Increment Command -

3FFh

081h

3FFh Reserved

101h (Full Scale (W = A))

No

SDI and SDO States.

080h

100h Full Scale (W = A)

Note:

Table 7-2 shows the valid addresses for

the Increment Wiper command. Other

addresses are invalid.

07Fh

041h

0FFh W = N

081

040h

080h W = N (Mid Scale)

Yes

03Fh

001h

07Fh W = N

001

000h

000h Zero Scale (W = B)

DS22233A-page 56

MCP434X/436X

Increment commands can be sent repeatedly without

raising CS until a desired condition is met. The value in

the Volatile Wiper register can be read using a Read

Command and written to the corresponding

Non-Volatile Wiper EEPROM using a Write Command.

7.7.2

CONTINUOUS INCREMENTS

Continuous Increments are possible only when writing

to the volatile memory registers (address 00h, and

01h).

Figure 7-7 shows a Continuous Increment sequence

for three continuous writes. The writes do not need to

be to the same volatile memory address.

When executing a continuous command string, the

Increment command can be followed by any other valid

command.

When executing an continuous Increment commands,

the selected wiper will be altered from n to n+1 for each

Increment command received. The wiper value will

increment up to 100h on 8-bit devices and 80h on 7-bit

devices. After the wiper value has reached Full Scale

(8-bit =100h, 7-bit =80h), the wiper value will not be

incremented further. If the Wiper register has a value

between 101h and 1FFh, the Increment command is

disabled.

The wiper terminal will move after the command has

been received (8th clock).

After the wiper is incremented to the desired position,

the CS pin should be forced to V_IHto ensure that

unexpected transitions (on the SCK pin do not cause

the wiper setting to change). Driving the CS pin to V_IH

should occur as soon as possible (within device

specifications) after the last desired increment occurs.

COMMAND BYTE

(INCR COMMAND (n+2))

COMMAND BYTE

(INCR COMMAND (n+1))

(INCR COMMAND (n+3))

A

D

3

A

D

2

A

D

1

A

D

0

1

X

A

D

3

A

D

2

A

D

1

A

D

0

1

X

A

D

3

A

D

2

A

D

1

A

D

0

1

X

SDI

1

1*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1*

0

1

0

Note 1, 2

Note 3, 4

SDO

1

0

1

0

Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination.

3: Invalid Address/Command combination.

4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

FIGURE 7-7:

Continuous Increment Command - SDI and SDO States.

DS22233A-page 57

MCP434X/436X

7.8.1

SINGLE DECREMENT

7.8

Decrement Wiper

Normal and High Voltage

Typically, the CS pin starts at the inactive state (V_IH),

but may already be in the active state due to the

completion of another command.

The Decrement Command is an 8-bit command. The

Decrement Command can only be issued to volatile

memory locations. The format of the command is

shown in Figure 7-6.

Figure 6-4 through Figure 6-5 show possible

waveforms for a single Decrement. The decrement

operation requires that the CS pin be in the active state

(V_ILor V_IHH). Typically, the CS pin will be in the inactive

state (V_IH) and is driven to the active state (V_ILor V_IHH).

Then the 8-bit Decrement Command (Command Byte)

is clocked in on the SDI pin by the SCK pins. The SDO

pin drives the CMDERR bit on the 7th clock.

A Decrement Command to the volatile memory location

changes that location after a properly formatted

command (8 clocks) have been received.

Decrement commands provide a quick and easy

method to modify the value of the volatile wiper location

by -1 with minimal overhead.

The wiper value will decrement from the wiper’s Full

Scale value (100h on 8-bit devices and 80h on 7-bit

devices). Above the wiper’s Full Scale value

(8-bit =101h to 1FFh, 7-bit = 81h to FFh), the

decrement command is disabled. If the Wiper register

has a Zero Scale value (000h), then the wiper value will

not decrement. See Table 7-4 for additional information

on the Decrement Command vs. the current volatile

wiper value.

COMMAND BYTE

(DECR COMMAND (n+1))

A

D

3

A

D

2

A

D

1

A

D

0

1

0

X

SDI

1

1*

0

1

0

Note 1, 2

Note 1, 3

SDO

The Decrement commands only require the Decrement

command byte, while the CS pin is active (V_ILor V_IHH

)

Note 1: Only functions when writing the volatile

for a single decrement.

wiper registers (AD3:AD0) 0h and 1h.

After the wiper is decremented to the desired position,

the CS pin should be forced to V_IHto ensure that

unexpected transitions on the SCK pin do not cause

the wiper setting to change. Driving the CS pin to V_IH

should occur as soon as possible (within device

specifications) after the last desired decrement occurs.

2: Valid Address/Command combination.

3: Invalid Address/Command combination

all following SDO bits will be low until the

CMDERR condition is cleared.

(the CS pin is forced to the inactive

state).

TABLE 7-5:

DECREMENT OPERATION VS.

VOLATILE WIPER VALUE

4: If a Command Error (CMDERR) occurs

at this bit location (*), then all following

SDO bits will be driven low until the CS

pin is driven inactive (V_IH).

Current Wiper

Setting

Decrement

Wiper (W)

Command

Properties

7-bit

Pot

8-bit

Pot

Operates?

FIGURE 7-8:

Decrement Command -

SDI and SDO States.

3FFh

081h

3FFh Reserved

101h (Full Scale (W = A))

No

Note:

Table 7-2 shows the valid addresses for

the Decrement Wiper command. Other

addresses are invalid.

080h

100h Full Scale (W = A)

Yes

07Fh

041h

0FFh W = N

081

040h

080h W = N (Mid Scale)

Yes

No

03Fh

001h

07Fh W = N

001

000h

000h Zero Scale (W = B)

DS22233A-page 58

MCP434X/436X

Decrement commands can be sent repeatedly without

raising CS until a desired condition is met. The value in

the Volatile Wiper register can be read using a Read

Command and written to the corresponding

Non-Volatile Wiper EEPROM using a Write Command.

7.8.2

CONTINUOUS DECREMENTS

Continuous Decrements are possible only when writing

to the volatile memory registers (address 00h, 01h, and

04h).

Figure 7-9 shows a continuous Decrement sequence

for three continuous writes. The writes do not need to

be to the same volatile memory address.

When executing a continuous command string, the

Decrement command can be followed by any other

valid command.

When executing continuous Decrement commands,

the selected wiper will be altered from n to n-1 for each

Decrement command received. The wiper value will

decrement from the wiper’s Full Scale value (100h on

8-bit devices and 80h on 7-bit devices). Above the

wiper’s Full Scale value (8-bit =101h to 1FFh,

7-bit = 81h to FFh), the decrement command is

disabled. If the Wiper register has a Zero Scale value

(000h), then the wiper value will not decrement. See

Table 7-4 for additional information on the Decrement

Command vs. the current volatile wiper value.

The wiper terminal will move after the command has

been received (8th clock).

After the wiper is decremented to the desired position,

the CS pin should be forced to V_IHto ensure that

“unexpected” transitions (on the SCK pin do not cause

the wiper setting to change). Driving the CS pin to V_IH

should occur as soon as possible (within device

specifications) after the last desired decrement occurs.

COMMAND BYTE

(DECR COMMAND (n-1))

COMMAND BYTE

(DECR COMMAND (n-1))

A

D

3

A

D

2

A

D

1

A

D

0

1

0

X

A

D

3

A

D

2

A

D

1

A

D

0

1

0

X

A

D

3

A

D

2

A

D

1

A

D

0

1

0

X

SDI

1

1*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1*

0

1

0

Note 1, 2

Note 3, 4

SDO

1

0

1

0

Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination.

3: Invalid Address/Command combination.

4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

FIGURE 7-9:

Continuous Decrement Command - SDI and SDO States.

DS22233A-page 59

MCP434X/436X

7.9.1

SINGLE ENABLE WRITE PROTECT

OR WIPERLOCK TECHNOLOGY

(HIGH VOLTAGE)

7.9

Modify Write Protect or WiperLock

Technology (High Voltage)

Enable and Disable

Figure 6-4 through Figure 6-5 show possible

waveforms for a single Modify Write Protect or

WiperLock Technology command.

This command is a special case of the High Voltage

Decrement Wiper and High Voltage Increment Wiper

commands to the non-volatile memory locations 02h,

03h, and 0Fh. This command is used to enable or

disable either the software Write Protect, wiper 0, wiper

1, wiper 2 and wiper 3 WiperLock Technology.

Table 7-6 shows the memory addresses, the High

Voltage command and the result of those commands

on the non-volatile WP, WL0 WL1, WL2, or WL3 bits.

The format of the command is shown in Figure 7-8

(Enable) or Figure 7-6 (Disable).

A Modify Write Protect or WiperLock Technology

Command will only start an EEPROM write cycle (t_wc

)

after a properly formatted Command (8-clocks) has

been received and the CS pin transitions to the inactive

state (V_IH).

After the CS pin is driven inactive (V_IH), the serial

interface may immediately be re-enabled by driving the

CS pin to the active state (V_ILor V_IHH).

During an EEPROM write cycle, only serial commands

to Volatile memory (addresses 00h, 01h, 04h, 05h, 06h,

07h, and 0Ah) are accepted. All other serial commands

are ignored until the EEPROM write cycle (t_wc) com-

pletes. This allows the Host Controller to operate on the

Volatile Wiper registers and the TCON register, and to

Read the Status Register. The EEWA bit in the Status

register indicates the status of an EEPROM Write

Cycle.

TABLE 7-6:

ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY

Command’s and Result

Memory

Address

High Voltage Decrement Wiper

High Voltage Increment Wiper

00h

01h

Wiper 0 register is decremented

Wiper 1 register is decremented

WL0 is enabled

Wiper 0 register is incremented

Wiper 1 register is incremented

WL0 is disabled

02h

03h

WL1 is enabled

WL1 is disabled

04h ⁽¹⁾

TCON0 register not changed, CMDERR bit is

set

TCON0 register not changed, CMDERR bit is

set

05h ⁽¹⁾

STATUS register not changed, CMDERR bit is

set

STATUS register not changed, CMDERR bit is

set

06h

07h

Wiper 2 register is decremented

Wiper 3 register is decremented

WL2 is enabled

Wiper 2 register is incremented

Wiper 3 register is incremented

WL2 is disabled

08h

09h

WL3 is enabled

WL3 is disabled

0Ah ⁽¹⁾

TCON1 register not changed, CMDERR bit is

set

TCON1 register not changed, CMDERR bit is

set

0Bh - 0Eh ⁽¹⁾

0Fh

Reserved

WP is enabled

WP is disabled

Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses.

DS22233A-page 60

MCP434X/436X

8.0

APPLICATIONS EXAMPLES

5V

3V

Voltage

Non-volatile digital potentiometers have a multitude of

practical uses in modern electronic circuits. The most

popular uses include precision calibration of set point

thresholds, sensor trimming, LCD bias trimming, audio

attenuation, adjustable power supplies, motor control

overcurrent trip setting, adjustable gain amplifiers and

offset trimming. The MCP434X/436X devices can be

used to replace the common mechanical trim pot in

applications where the operating and terminal voltages

are within CMOS process limitations (V_DD= 2.7V to

5.5V).

Regulator

MCP4XXX

PIC MCU

SDI

CS

SCK

WP

SDI

CS

SCK

WP

RESET

SDO

I/O

SDO

FIGURE 8-1:

System 1.

Example Split Rail

8.1

Split Rail Applications

All inputs that would be used to interface to a Host

Controller support High Voltage on their input pin. This

allows the MCP43XX device to be used in split power

rail applications.

5V

Voltage

Regulator

3V

An example of this is a battery application where the

PIC^®MCU is directly powered by the battery supply

(4.8V) and the MCP43XX device is powered by the

3.3V regulated voltage.

MCP4XXX

PIC MCU

SDI

CS

SCK

WP

RESET

SDI

CS

SCK

WP

I/O

For SPI applications, these inputs are:

• CS

• SCK

SDO

• SDI (or SDI/SDO)

• WP

FIGURE 8-2:

Example Split Rail

• RESET

System 2.

Figure 8-1 through Figure 8-2 show three example split

rail systems. In this system, the MCP43XX interface

input signals need to be able to support the PIC MCU

output high voltage (V_OH).

TABLE 8-1:

PIC ⁽¹⁾

V

- V COMPARISONS

MCP4XXX ⁽²⁾

OH

IH

Comment

In Example #1 (Figure 8-1), the MCP43XX interface

input signals need to be able to support the PIC MCU

output high voltage (V_OH). If the split rail voltage delta

becomes too large, then the customer may be required

to do some level shifting due to MCP43XX V_OHlevels

related to Host Controller V_IHlevels.

V_DDV_IHV_OHV_DDV_IH

V_OH

5.5

5.0

4.5

3.3

3.0

2.7

4.4

4.0

3.6

4.4

4.0

3.6

2.7 1.215 — ⁽³⁾

(3)

3.0 1.35

—

3.3 1.485 — ⁽³⁾

2.64 2.64 4.5 2.025 — ⁽³⁾

(3)

2.4

5.0 2.25

—

In Example #2 (Figure 8-2), the MCP43XX interface

input signals need to be able to support the lower

voltage of the PIC MCU output high voltage level (V_OH).

2.16 2.16 5.5 2.475 — ⁽³⁾

Note 1: V_OHminimum = 0.8 * V_DD

;

V_OLmaximum = 0.6V

V_IHminimum = 0.8 * V_DD

V_ILmaximum = 0.2 * V_DD

Table 8-1 shows an example PIC microcontroller I/O

;

voltage

specifications

and

the

MCP43XX

specifications. So this PIC MCU operating at 3.3V will

drive a V_OHat 2.64V, and for the MCP43XX operating

at 5.5V, the V_IHis 2.47V. Therefore, the interface

signals meet specifications.

2: V_OHminimum (SDA only) =;

V_OLmaximum = 0.2 * V_DD

V_IHminimum = 0.45 * V_DD

V_ILmaximum = 0.2 * V_DD

;

3: The only MCP4XXX output pin is SDO,

which is Open-Drain (or Open-Drain with

Internal Pull-up) with High Voltage Support

DS22233A-page 61

MCP434X/436X

8.2

Techniques to Force the CS Pin to

V_IHH

PIC10F206

R₁

GP0

The circuit in Figure 8-3 shows a method using the

TC1240A doubling charge pump. When the SHDN pin

is high, the TC1240A is off, and the level on the CS pin

is controlled by the PIC® microcontrollers (MCUs) IO2

pin.

MCP4XXX

GP2

CS

When the SHDN pin is low, the TC1240A is on and the

V_OUTvoltage is 2 * V_DD. The resistor R₁allows the CS

pin to go higher than the voltage such that the PIC

C₁

C₂

FIGURE 8-4:

MCP4XXX Non-volatile

MCU’s IO2 pin “clamps” at approximately V_DD

.

Digital Potentiometer Evaluation Board

(MCP402XEV) implementation to generate the

TC1240A

V_IN

V

voltage.

IHH

C+

PIC MCU

C₁

C-

SHDN

8.3

Using Shutdown Modes

V_OUT

IO1

Figure 8-5 shows a possible application circuit where

the independent terminals could be used.

Disconnecting the wiper allows the transistor input to

be taken to the Bias voltage level (disconnecting A and

or B may be desired to reduce system current).

Disconnecting Terminal A modifies the transistor input

by the R_BWrheostat value to the Common B.

Disconnecting Terminal B modifies the transistor input

by the R_AWrheostat value to the Common A. The

Common A and Common B connections could be

MCP4XXX

R₁

CS

IO2

C₂

FIGURE 8-3:

Generate the V

Using the TC1240A to

Voltage.

IHH

connected to V_DDand V_SS

.

The circuit in Figure 8-4 shows the method used on the

MCP402X Non-volatile Digital Potentiometer

Evaluation Board (Part Number: MCP402XEV). This

method requires that the system voltage be

approximately 5V. This ensures that when the

PIC10F206 enters a brown-out condition, there is an

insufficient voltage level on the CS pin to change the

stored value of the wiper. The MCP402X Non-volatile

Digital Potentiometer Evaluation Board User’s Guide

(DS51546) contains a complete schematic.

Common A

Input

A

GP0 is a general purpose I/O pin, while GP2 can either

be a general purpose I/O pin or it can output the internal

clock.

To base

of Transistor

(or Amplifier)

W

For the serial commands, configure the GP2 pin as an

input (high impedance). The output state of the GP0 pin

will determine the voltage on the CS pin (V_ILor V_IH).

For high-voltage serial commands, force the GP0

output pin to output a high level (V_OH) and configure the

GP2 pin to output the internal clock. This will form a

charge pump and increase the voltage on the CS pin

(when the system voltage is approximately 5V).

B

Input

Common B

Balance

Bias

Example Application Circuit

FIGURE 8-5:

using Terminal Disconnects.

DS22233A-page 62

MCP434X/436X

8.4.2

LAYOUT CONSIDERATIONS

8.4

Design Considerations

Several layout considerations may be applicable to

your application. These may include:

In the design of a system with the MCP43XX devices,

the following considerations should be taken into

account:

• Noise

• Footprint Compatibility

• PCB Area Requirements

• Power Supply Considerations

• Layout Considerations

8.4.2.1

Noise

8.4.1

POWER SUPPLY

CONSIDERATIONS

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP43XX’s performance.

Careful board layout minimizes these effects and

increases the Signal-to-Noise Ratio (SNR). Multi-layer

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 8-6 illustrates an

appropriate bypass strategy.

boards utilizing

a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are critical to achieving the performance that the silicon

is capable of providing. Particularly harsh

environments may require shielding of critical signals.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close (within 4 mm) to the device power pin (V_DD) as

possible.

If low noise is desired, breadboards and wire-wrapped

boards are not recommended.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, V_DDand

V_SSshould reside on the analog plane.

8.4.2.2

Footprint Compatibility

The specification of the MCP43XX pinouts was done to

allow systems to be designed to easily support the use

of either the dual (MCP42XX) or quad (MCP43XX)

device.

V_DD

Figure 8-7 shows how the dual pinout devices fit on the

quad device footprint. For the Rheostat devices, the

dual device is in the MSOP package, so the footprints

would need to be offset from each other.

0.1 µF

V_DD

MCP43X1 Quad Potentiometers

0.1 µF

P2A

P2W

P2B

V_DD

SDO

P3A

P3W

P3B

CS

SCK

SDI

20

19

18

17

16

1

2

3

4

5

6

7

8

9

10

15 RESET

14 WP

A

W

MCP42X1 Pinout ⁽¹⁾

V_SS

P0B

12

P1B

P1W

P1A

U/D

P0W

P0A

12

11

TSSOP

MCP43X2 Quad Rheostat

CS

B

P2W

P2B

V_DD

SDO

P0B

P0W

P1W

P3W

P3B

CS

SCK

SDI

V_SS

P1B

14

13

12

11

10

9

1

2

3

4

5

6

7

V_SS

MCP42X2 Pinout

FIGURE 8-6:

Typical Microcontroller

8

Connections.

TSSOP

Note 1: Pin 15 (RESET) is the Shutdown (SHDN)

pin on the MCP42x1 device.

FIGURE 8-7:

Quad Pinout (TSSOP

Package) vs. Dual Pinout.

DS22233A-page 63

MCP434X/436X

Figure 8-8 shows possible layout implementations for

an application to support the quad and dual options on

the same PCB.

8.4.2.3

PCB Area Requirements

In some applications, PCB area is a criteria for device

selection. Table 8-2 shows the package dimensions

and area for the different package options. The table

also shows the relative area factor compared to the

smallest area. For space critical applications, the QFN

package would be the suggested package.

Potentiometers Devices

MCP43X1

(1)

TABLE 8-2:

Package

PACKAGE FOOTPRINT

Package Footprint

MCP42X1

Dimensions

(mm)

Type

Code

X

Y

Rheostat Devices

MCP42X2

14 TSSOP

ST

ML

ST

5.10 6.40 32.64 2.04

4.00 4.00 16.00

6.60 6.40 42.24 2.64

QFN

20

1

TSSOP

MCP43X2

Note 1: Does not include recommended land

pattern dimensions.

8.4.3

RESISTOR TEMPCO

Characterization curves of the resistor temperature

coefficient (Tempco) are shown in Figure 2-8,

Figure 2-19, Figure 2-29, and Figure 2-39.

FIGURE 8-8:

Dual Devices.

Layout to support Quad and

These curves show that the resistor network is

designed to correct for the change in resistance as

temperature increases. This technique reduces the

end to end change is R_ABresistance.

8.4.4

HIGH VOLTAGE TOLERANT PINS

High Voltage support (V_IHH) on the Serial Interface pins

supports two features. These are:

• In-Circuit Accommodation of split rail applications

and power supply sync issues

• User configuration of the Non-Volatile EEPROM,

Write Protect, and WiperLock feature

Note:

In many applications, the High Voltage will

only be present at the manufacturing

stage so as to “lock” the Non-Volatile wiper

value (after calibration) and the contents

of the EEPROM. This ensures that since

High Voltage is not present under normal

operating conditions, these values can not

be modified.

DS22233A-page 64

MCP434X/436X

9.2

Technical Documentation

9.0

9.1

DEVELOPMENT SUPPORT

Development Tools

Several additional technical documents are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs, and Design Guides. Table 9-2 shows

some of these documents.

Several development tools are available to assist in

your design and evaluation of the MCP43XX devices.

The currently available tools are shown in Table 9-1.

These boards may be purchased directly from the

Microchip web site at www.microchip.com.

TABLE 9-1:

Board Name

DEVELOPMENT TOOLS

Part #

Supported Devices

20-pin TSSOP and SSOP Evaluation Board

MCP4361 Evaluation Board ⁽¹⁾

TSSOP20EV

MCP43XXEV

MCP43XX

MCP4361

MCP42XX

MCP42XX Digital Potentiometer PICtail Plus Demo MCP42XXDM-PTPLS

Board

MCP4XXX Digital Potentiometer Daughter Board ⁽²⁾MCP4XXXDM-DB

MCP42XXX, MCP42XX, MCP4021,

and MCP4011

Note 1: This Evaluation Board is planned to be available by March 2010. This board uses the TSSOP20EV PCB

and requires the PICkit Serial Analyzer (see User’s Guide for details). This kit also includes 1 blank

TSSOP20EV PCB.

2: Requires the use of a PICDEM Demo board (see User’s Guide for details)

TABLE 9-2:

TECHNICAL DOCUMENTATION

Title

Application

Literature #

Note Number

AN1080

AN737

AN692

AN691

AN219

—

Understanding Digital Potentiometers Resistor Variations

Using Digital Potentiometers to Design Low-Pass Adjustable Filters

Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect

Optimizing the Digital Potentiometer in Precision Circuits

Comparing Digital Potentiometers to Mechanical Potentiometers

Digital Potentiometer Design Guide

DS01080

DS00737

DS00692

DS00691

DS00219

DS22017

DS21825

—

Signal Chain Design Guide

DS22233A-page 65

MCP434X/436X

NOTES:

DS22233A-page 66

MCP434X/436X

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

14-Lead TSSOP

Example

4362502E

0940

XXXXXXXX

YYWW

NNN

256

20-Lead QFN (4x4)

Example

XXXXX

XXXXXX

YYWWNNN

4361

502EML

e

3

0940

^^

256

20-Lead TSSOP

Example

XXXXXXXX

MCP4361

256

NNN

XXXXX

EST

e3

^^

YYWW

0940

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22233A-page 67

MCP434X/436X

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢏꢒꢌꢐꢓꢇꢑꢔꢅꢉꢉꢇꢕꢖꢋꢉꢌꢐꢄꢇꢗꢑꢎꢘꢇMꢇꢁꢙꢁꢇꢔꢔꢇꢚꢛꢆꢜꢇ ꢎꢑꢑꢕꢈ!

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ꢎꢁ ꢏꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢏꢅꢆꢄ#ꢅ+ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢐꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢑꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢐꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢒꢁꢀ,ꢅ''ꢅꢐꢈꢉꢅ!ꢃ#ꢈꢁ

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/ꢕ01 /ꢆ!ꢃꢌꢅꢏꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢗꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢘ+21 ꢘꢈ%ꢈꢉꢈꢄꢌꢈꢅꢏꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢐ"ꢉꢐꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢑꢃꢌꢉꢋꢌꢍꢃꢐ ꢗꢈꢌꢍꢄꢋꢇꢋꢓꢊ ꢏꢉꢆ*ꢃꢄꢓ 0ꢒꢖꢞꢒꢚꢜ/

DS22233A-page 68

MCP434X/436X

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22233A-page 69

MCP434X/436X

$%ꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ&ꢖꢅꢆꢇ'ꢉꢅꢋ(ꢇ"ꢛꢇꢃꢄꢅꢆꢇꢈꢅꢍꢓꢅ)ꢄꢇꢗ*ꢃꢘꢇMꢇꢁ+ꢁ+%ꢙ,ꢇꢔꢔꢇꢚꢛꢆꢜꢇ &'"!

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ꢍ&&ꢐ144***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢐꢁꢌꢋ'4ꢐꢆꢌ3ꢆꢓꢃꢄꢓ

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ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ

ꢎꢁ ꢂꢆꢌ3ꢆꢓꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢓ"ꢇꢆ&ꢈ#ꢁ

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ꢘ+21 ꢘꢈ%ꢈꢉꢈꢄꢌꢈꢅꢏꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢐ"ꢉꢐꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢑꢃꢌꢉꢋꢌꢍꢃꢐ ꢗꢈꢌꢍꢄꢋꢇꢋꢓꢊ ꢏꢉꢆ*ꢃꢄꢓ 0ꢒꢖꢞꢀꢎ:/

DS22233A-page 70

MCP434X/436X

"ꢛꢋꢄ# 2ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢐꢆꢌ3ꢆꢓꢈꢅ#ꢉꢆ*ꢃꢄꢓ!(ꢅꢐꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢑꢃꢌꢉꢋꢌꢍꢃꢐꢅꢂꢆꢌ3ꢆꢓꢃꢄꢓꢅꢕꢐꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ

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DS22233A-page 71

MCP434X/436X

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ꢎꢁ ꢏꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢏꢅꢆꢄ#ꢅ+ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢐꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢑꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢐꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢒꢁꢀ,ꢅ''ꢅꢐꢈꢉꢅ!ꢃ#ꢈꢁ

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/ꢕ01 /ꢆ!ꢃꢌꢅꢏꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢗꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢘ+21 ꢘꢈ%ꢈꢉꢈꢄꢌꢈꢅꢏꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢐ"ꢉꢐꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

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DS22233A-page 72

MCP434X/436X

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22233A-page 73

MCP434X/436X

NOTES:

DS22233A-page 74

MCP434X/436X

APPENDIX A: REVISION HISTORY

Revision A (December 2009)

• Original Release of this Document.

DS22233A-page 75

MCP434X/436X

NOTES:

DS22233A-page 76

MCP434X/436X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

-XXX

X

/XX

a)

b)

c)

d)

e)

f)

MCP4341-502E/XX: 5 kΩ, 20-LD Device

Resistance Temperature

Version

Package

MCP4341T-502E/XX: T/R, 5 kΩ, 20-LD Device

MCP4341-103E/XX: 10 kΩ, 20-LD Device

MCP4341T-103E/XX: T/R, 10 kΩ, 20-LD Device

MCP4341-503E/XX: 50 kΩ, 20-LD Device

MCP4341T-503E/XX: T/R, 50 kΩ, 20-LD Device

MCP4341-104E/XX: 100 kΩ, 20-LD Device

MCP4341T-104E/XX: T/R, 100 kΩ,

Range

Device

MCP4341:

MCP4341T:

Quad Non-Volatile 7-bit Potentiometer

(Tape and Reel)

Quad Non-Volatile 7-bit Rheostat

(Tape and Reel)

Quad Non-Volatile 8-bit Potentiometer

(Tape and Reel)

Quad Non-Volatile 8-bit Rheostat

(Tape and Reel)

g)

h)

MCP4342:

MCP4342T:

20-LD Device

a)

b)

c)

d)

e)

f)

MCP4342-502E/XX: 5 kΩ, 14-LD Device

MCP4342T-502E/XX: T/R, 5 kΩ, 14-LD Device

MCP4342-103E/XX: 10 kΩ, 14-LD Device

MCP4342T-103E/XX: T/R, 10 kΩ, 14-LD Device

MCP4342-503E/XX: 50 kΩ, 8LD Device

MCP4342T-503E/XX: T/R, 50 kΩ, 14-LD Device

MCP4342-104E/XX: 100 kΩ, 14-LD Device

MCP4342T-104E/XX: T/R, 100 kΩ,

MCP4361:

MCP4361T:

MCP4362:

MCP4362T:

g)

h)

14-LD Device

Resistance Version: 502

=

5 kΩ

a)

b)

c)

d)

e)

f)

MCP4361-502E/XX: 5 kΩ, 20-LD Device

MCP4361T-502E/XX: T/R, 5 kΩ, 20-LD Device

MCP4361-103E/XX: 10 kΩ, 20-LD Device

MCP4361T-103E/XX: T/R, 10 kΩ, 20-LD Device

MCP4361-503E/XX: 50 kΩ, 20-LD Device

MCP4361T-503E/XX: T/R, 50 kΩ, 20-LD Device

MCP4361-104E/XX: 100 kΩ, 20-LD Device

MCP4361T-104E/XX: T/R, 100 kΩ,

103

503

104

10 kΩ

50 kΩ

100 kΩ

Temperature Range

Package

E

=

-40°C to +125°C (Extended)

g)

h)

20-LD Device

ST

ML

=

Plastic Thin Shrink Small Outline (TSSOP),

14/20-lead

Plastic Quad Flat No-lead (4x4 QFN), 20-lead

a)

b)

c)

d)

e)

f)

MCP4362-502E/XX: 5 kΩ, 14-LD Device

MCP4362T-502E/XX: T/R, 5 kΩ, 14-LD Device

MCP4362-103E/XX: 10 kΩ, 14-LD Device

MCP4362T-103E/XX: T/R, 10 kΩ, 14-LD Device

MCP4362-503E/XX: 50 kΩ, 14-LD Device

MCP4362T-503E/XX: T/R, 50 kΩ, 14-LD Device

MCP4362-104E/XX: 100 kΩ, 14-LD Device

MCP4362T-104E/XX: T/R, 100 kΩ,

g)

h)

14-LD Device

XX

=

ST for 14/20-lead TSSOP

ML for 20-lead QFN

DS22233A-page 77

MCP434X/436X

NOTES:

DS22233A-page 78

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, PIC³²logo, REAL ICE, rfLAB, Select Mode, Total

Endurance, TSHARC, UniWinDriver, WiperLock and ZENA

are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22233A-page 79

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

03/26/09

DS22233A-page 80


型号：	MCP4341-104E/ST
厂家：	MICROCHIP
描述：	QUAD 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 129 POSITIONS, PDSO20, 4.40 MM, LEAD FREE, PLASTIC, TSSOP-20 光电二极管转换器电阻器
文件：	总80页 (文件大小：1638K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP4341-104E/ST [MICROCHIP]

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