MCP47A1_技术文档

MCP47A1

6-Bit Volatile DAC with Command Code

Package Types

Features:

MCP47A1

• 6-Bit DAC

- 65 Taps: 64 Resistors with Taps to Full-Scale

and Zero-Scale (Wiper Code 00h to 40h)

V_DD

V_SS

SCL

A

V_REF

V_OUT

SDA

1

2

3

6

5

4

W

B

• V_REFPull-down Resistance: 20 k (typical)

• V_OUTVoltage Range

SC70-6

- V_SSto V_REF

™

• I²C Protocol

Device Block Diagram

- Supports SMBus 2.0 Write Byte/Word

Protocol Formats

- Supports SMBus 2.0 Read Byte/Word

Protocol Formats

V_DD

V_REF

A

Power-up

and

Brown-out

Control

- Slave Addresses: 5Ch and 7Ch

V_SS

• Brown-out Reset Protection (1.5V typical)

• Power-on Default Wiper Setting (Mid-scale)

• Low-PowerOperation:90 µAStaticCurrent(typical)

• Wide Operating Voltage Range:

2-Wire

Interface

and

Control

Logic

SDA

SCL

- 1.8V to 5.5V

V_OUT

• Low Tempco: 15 ppm (typical)

• 100 kHz (typical) Bandwidth (-3 dB) Operation

• Extended Temperature Range (-40°C to +125°C)

• Small Packages, SC70-6

B

• Lead Free (Pb-free) Package

Description

Applications

The MCP47A1 devices are volatile, 6-Bit digital

potentiometers with a buffered output. The wiper

setting is controlled through an I²C serial interface. The

I²C slave addresses of “010 1110”and “011 1110”

are supported.

• Set point or offset trimming

• Cost-sensitive mechanical trim pot replacement

 2012 Microchip Technology Inc.

DS25154A-page 1

MCP47A1

Device Features

Device

Package(s)

(1)

MCP47A1

MCP47DA1

MCP4706

MCP4716

MCP4726

MCP4725

I²C 65

64

20

30

00h - 40h

00h - 7Fh

00h - FFh

20h 5Ch, 7Ch 1.8V

V

_SSto V_REF

SC70-6

to 5.5V

(2)

(1)

40h 5Ch, 7Ch 1.8V

1/3 V_REFto

2/3 V_REF

SC70-6,

SOT-23-6

to 5.5V

(3)

(4)

I²C 256 256

I²C 1024 1024

I²C 4096 4096

210

7Fh

Cxh

2.7V to V_SSto V_DDor SOT-23-6,

5.5V

(5)

V_SSto V_REF

DFN-6(2x2)

000h - 3FFh 1FFh Cxh

000h - FFFh 3FFh Cxh

2.7V to V_SSto V_DDor SOT-23-6,

5.5V

(5)

V_SSto V_REF

DFN-6(2x2)

2.7V to V_SSto V_DDor SOT-23-6,

5.5V

(5)

V_SSto V_REF

V_SSto V_DD

DFN-6(2x2)

SOT-23-6

I²C 4096 4096 N.A. 000h - FFFh 3FFh Cxh

2.7V to

5.5V

Note 1: Analog characteristics only tested from 2.7V to 5.5V.

2: Refer to MCP47DA1 Data Sheet (DS25118).

3: The A2:A0 bits are determined by device ordered.

4: The A2 and A1 bits are determined by device ordered and A0 is determined by the state of the A0 pin.

5: User programmable.

DS25154A-page 2

 2012 Microchip Technology Inc.

MCP47A1

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Voltage on V_DDwith respect to V_SS.......................................................................................................... 0.6V to +7.0V

Voltage on SCL, and SDA with respect to V_{SS .....................................................................................................}-0.6V to V_DD+ 0.3V

Voltage on all other pins (V_OUTand V_REF) with respect to V_{SS .....................................................................}-0.3V to V_DD+ 0.3V

Input clamp current, I_IK(V_I< 0, V_I> V_DD)............................................................................................................ ±20 mA

Output clamp current, I_OK(V_O< 0 or V_O> V_DD).................................................................................................. ±20 mA

Maximum output current sunk by any Output pin .................................................................................................. 25 mA

Maximum output current sourced by any Output pin ............................................................................................ 25 mA

Maximum current out of V_SSpin .......................................................................................................................... 100 mA

Maximum current into V_DDpin ............................................................................................................................. 100 mA

Maximum current into V_REFpin............................................................................................................................. 250 uA

Maximum current sourced by V_OUTpin ................................................................................................................. 40 mA

Maximum current sunk by V_REFpin....................................................................................................................... 40 mA

Package power dissipation (T_A= +50°C, T_J= +150°C)

SC70-6..................................................................................................................................................... 480 mW

Storage temperature .............................................................................................................................. -65°C to +150°C

Ambient temperature with power applied .............................................................................................. -40°C to +125°C

ESD protection on all pins .......................................................................................................................... 6 kV (HBM)

..................................................................................................................................................................... 400V (MM)

 1.5 kV (CDM)

Latchup (JEDEC JESD78A) at +125°C ............................................................................................................. ±100 mA

Soldering temperature of leads (10 seconds)...................................................................................................... +300°C

Maximum Junction Temperature (T_J) .................................................................................................................. +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at those or any other conditions above those indicated in the

operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

 2012 Microchip Technology Inc.

DS25154A-page 3

MCP47A1

AC/DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

–40°C  T_A +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to +5.5V. C_L= 1 nF, R_L= 5 k .

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Supply Voltage

V_DD

2.7

1.8

—

5.5

V

Analog Characteristics specified

Digital Characteristics specified

RAM retention voltage (V_RAM) < V_BOR

V_DDStart Voltage

to ensure Wiper to

default reset state

V_BOR

V_DDRR

T_BORD

1.65

V_DDRise Rate to

ensure Power-on

Reset

Note 5

V/ms

µS

Delay after device

exits the reset

state

—

1

(V_DD> V_BOR) to

Digital Interface

Active

Delay after device

exits the reset

state

(V_DD> V_BOR) to

V_OUTvalid

T_OUTV

20

µS

µA

Within ± 0.5 LSb of V_REF/ 2

(for default POR/BOR wiper value).

Supply Current

(Note 6)

I_DD

—

130

220

Serial Interface Active,

Write all 0’s to Volatile Wiper,

No Load on V_OUT

V_DD= 5.5V, V_REF= V_DD

,

F

_SCL= 400 kHz

—

1

90

—

130

V_DD

µA

V

Serial Interface Inactive (Static),

(Stop condition, SCL = SDA = V_IH),

No Load on V_OUT

Wiper = 0, V_DD= 5.5V, V_REF= V_DD

V_REFInput Range

V_REF

Note 7

Note 1: Resistance is defined as the resistance between the V_REFpin and the V_SSpin.

2: INL and DNL are measured at V_OUTfrom Code = 00h (Zero-Scale) through Code = 3Fh (Full-Scale - 1).

3: This specification by design.

4: Nonlinearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

5: POR/BOR is not rate dependent.

6: Supply current is independent of V_REFcurrent.

7: See Section 7.1.3.

DS25154A-page 4

 2012 Microchip Technology Inc.

MCP47A1

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C  T_A +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to +5.5V. C_L= 1 nF, R_L= 5 k .

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Output Amplifier

Minimum Output

Voltage

V_OUT(MIN)

V_OUT(MAX)

—

V_SS

—

V

Device Output minimum drive

Device Output maximum drive

Maximum Output

Voltage

V_REF

Phase Margin

Slew Rate

PM

SR

I_SC

—

5

66

0.55

15

—

24

Degree (°) C_L= 400 pF, R_L= 

V/µs

mA

Short Circuit

Current

Settling Time

t_SETTLING

—

15

—

µs

External Reference (V_REF) (Note 3)

Input Capacitance

C_VREF

THD

—

7

—

pF

Total Harmonic

Distortion

-73

dB

V_REF= 1.65V ± 0.1V,

Frequency = 1 kHz

Dynamic Performance (Note 3)

Major Code

Transition Glitch

—

45

—

nV-s

1 LSb change around major carry

(20h to 1Fh)

Digital

<10

Feedthrough

Note 1: Resistance is defined as the resistance between the V_REFpin and the V_SSpin.

2: INL and DNL are measured at V_OUTfrom Code = 00h (Zero-Scale) through Code = 3Fh (Full-Scale - 1).

3: This specification by design.

4: Nonlinearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

5: POR/BOR is not rate dependent.

6: Supply current is independent of V_REFcurrent.

7: See Section 7.1.3.

 2012 Microchip Technology Inc.

DS25154A-page 5

MCP47A1

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C  T_A +125°C (extended)

DC Characteristics

Parameters

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to +5.5V. C_L= 1 nF, R_L= 5 k .

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Sym

Min

Typ

Max

Units

Conditions

Resistance

(± 20%)

R_VREF

16.0

20

24.0

k

Note 1,

Resolution

N

R_S

65

R_VREF/ 64

50

Taps



No Missing Codes

Note 3

Step Resistance

—

Nominal

Resistance

Tempco

R_VREF/T

ppm/°C

T_A= -20°C to +70°C

T_A= -40°C to +85°C

T_A= -40°C to +125°C

Code = Midscale (20h)

100

150

Ratiometeric

Tempco

V_OUT/T

15

V

_OUTAccuracy

_OUTLoad

0.72

5

0.75

—

0.78

—

V

V_REF= 1.5V, code = 20h

Resistive Load

V

L_VOUTR

L_VOUTC

I_VREF

k

nF

µA

—

1

Capacitive Load

V_REF= 5.5V

Maximum current

through Terminal

(V_REF) Note 3

—

345

Leakage current

into V_REF

I_L

—

-1

100

±0.35

±0.25

100

—

+1

nA

LSb

kHz

pF

V_REF= V_SS

Full-Scale Error

(code = 40h)

V_FSE

V_ZSE

INL

V_REF= V_DD

Zero-Scale Error

(code = 00h)

-0.75

-1

+0.75

+1

V_REF= V_DD

V_OUTIntegral

Nonlinearity

Note 2, V_REF= V_DD

V_OUTDifferential

DNL

BW

-0.5

—

+0.5

—

Nonlinearity

Bandwidth -3 dB

V_DD= 5.0V, V_REF= 3.0V ± 2.0V,

Code = 20h

Capacitance

C_REF

—

75

—

f =1 MHz, Code = Full-Scale

(V_REF

)

Note 1: Resistance is defined as the resistance between the V_REFpin and the V_SSpin.

2: INL and DNL are measured at V_OUTfrom Code = 00h (Zero-Scale) through Code = 3Fh (Full-Scale - 1).

3: This specification by design.

4: Nonlinearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

5: POR/BOR is not rate dependent.

6: Supply current is independent of V_REFcurrent.

7: See Section 7.1.3.

DS25154A-page 6

 2012 Microchip Technology Inc.

MCP47A1

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C  T_A +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to +5.5V. C_L= 1 nF, R_L= 5 k .

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Digital Inputs/Outputs (SDA, SCK)

Schmitt Trigger

High Input

V_IH

0.7 V_D

—

V

1.8V  V_DD 5.5V

D

Threshold

Schmitt Trigger

Low Input

V_IL

-0.5

—

0.3V_D

V

1.8V  V_DD 5.5V

D

Threshold

Hysteresis of

Schmitt Trigger

Inputs (Note 3)

V_HYS

N.A.

—

V

_DD< 2.0V

V_DD 2.0V

V_DD< 2.0V

100 kHz

400 kHz

SDA

and

SCL

0.1 V_D

D

0.05 V

DD

—

V

V_DD 2.0V

Output Low

Voltage (SDA)

V_OL

V_SS

—

0.4

V

V_DD 2.0V, I_OL= 3 mA

V_DD< 2.0V, I_OL= 1 mA

V_SS

0.2V_D

D

Input Leakage

Current

I_IL

-1

—

1

µA

pF

V_REF= V_DDand V_REF= V_SS

f_C= 400 kHz

Pin Capacitance

RAM (Wiper) Value

Value Range

C_IN, C_OUT

—

10

—

N

0h

—

40h

hex

Wiper POR/BOR

Value

N_POR/BOR

20h

Power Requirements

Power Supply

Sensitivity

PSS

—

0.0015

0.003

5

%/%

V_REF= V_DD, Code = 20h

Note 1: Resistance is defined as the resistance between the V_REFpin and the V_SSpin.

2: INL and DNL are measured at V_OUTfrom Code = 00h (Zero-Scale) through Code = 3Fh (Full-Scale - 1).

3: This specification by design.

4: Nonlinearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

5: POR/BOR is not rate dependent.

6: Supply current is independent of V_REFcurrent.

7: See Section 7.1.3.

 2012 Microchip Technology Inc.

DS25154A-page 7

MCP47A1

2

1.1

I C Mode Timing Waveforms and Requirements

SCL

93

91

90

92

SDA

START

STOP

Condition

FIGURE 1-1:

I²C Bus Start/Stop Bits Timing Waveforms.

103

102

92

100

101

109

SCL

90

106

91

107

SDA

In

110

109

SDA

Out

Note:

Refer to specification D102 (Cb) for load conditions.

I²C Bus Data Timing.

FIGURE 1-2:

TABLE 1-1:

I²C BUS START/STOP BITS REQUIREMENTS

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40C  TA  +125C (Extended)

Operating Voltage V_DDrange is described in Section 2.0 “Typical

Performance Curves”

Param.

Symbol

No.

Characteristic

Standard Mode

Min

Max

Units

Conditions

F_SCL

0

100

400

—

kHz C_b= 400 pF, 1.8V - 5.5V

Fast Mode

0

kHz C_b= 400 pF, 2.7V - 5.5V

D102

90

Cb

Bus capacitive

loading

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

—

pF

—

TSU:STA START condition

Setup time

4700

600

4000

600

4000

600

4000

600

ns

Only relevant for repeated

START condition

—

91

THD:STA START condition

Hold time

—

After this period, the first

clock pulse is generated

—

92

TSU:STO STOP condition

Setup time

—

93

THD:STO STOP condition

Hold time

—

DS25154A-page 8

 2012 Microchip Technology Inc.

MCP47A1

TABLE 1-2:

I²C AC Characteristics

I²C BUS DATA REQUIREMENTS (SLAVE MODE)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40C  TA  +125C (Extended)

Operating Voltage VDD range is described in AC/DC characteristics

Parame-

ter No.

Sym

Characteristic

Min

Max Units

Conditions

100

T_HIGH

Clockhightime 100 kHz mode

400 kHz mode

4000

—

ns

1.8V-5.5V

600

—

ns

2.7V-5.5V

101

T_LOW

Clock low time

100 kHz mode

4700

1.8V-5.5V

400 kHz mode

100 kHz mode

1300

—

ns

2.7V-5.5V

(5)

T_RSCLSCL rise time

T_RSDASDA rise time

1000

C_bis specified to be from

10 to 400 pF

102A

400 kHz mode

100 kHz mode

20 + 0.1Cb

—

300

ns

(5)

1000

C_bis specified to be from

10 to 400 pF

102B

400 kHz mode

100 kHz mode

20 + 0.1Cb

—

300

ns

(5)

T_FSCL

SCL fall time

C_bis specified to be from

10 to 400 pF

103A

400 kHz mode

100 kHz mode

20 + 0.1Cb

—

40

ns

(5)

T_FSDASDA fall time

300

C_bis specified to be from

10 to 400 pF

103B

(5)

400 kHz mode

300

—

ns

20 + 0.1Cb

0

106

THD:DAT Data input hold 100 kHz mode

1.8V-5.5V (Note 6)

2.7V-5.5V (Note 6)

Note 5

time

400 kHz mode

0

—

ns

107

109

TSU:DAT Data input

setup time

100 kHz mode

400 kHz mode

100 kHz mode

250

100

—

T_AA

Output valid

from clock

3450

Note 5

400 kHz mode

100 kHz mode

—

900

—

ns

110

T_BUF

Bus free time

4700

Time the bus must be free

before a new transmission

can start

400 kHz mode

1300

—

ns

T_SP

Input filter spike 100 kHz mode

—

50

ns

Philips Spec states N.A.

suppression

400 kHz mode

(SDA and SCL)

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the

requirement tsu; DAT  250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line

TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before

the SCL line is released.

3: The MCP47A1 device must provide a data hold time to bridge the undefined part between VIH and VIL of

the falling edge of the SCL signal. This specification is not a part of the I²C specification, but must be

tested in order to guarantee that the output data will meet the setup and hold specifications for the

receiving device.

4: Use C_bin pF for the calculations.

5: Not tested.

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

 2012 Microchip Technology Inc.

DS25154A-page 9

MCP47A1

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Temperature Ranges

Sym

Min

Typ

Max

Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 6L-SC70

T_A

-40

-65

—

+125

+150

°C

_JA

—

207

—

°C/W Note 1

Note 1: Package Power Dissipation (P_DIS) is calculated as follows:

P_DIS= (T_J- T_A) / _JA

where: T_J= Junction Temperature, T_A= Ambient Temperature.

,

DS25154A-page 10

 2012 Microchip Technology Inc.

MCP47A1

2.0

TYPICAL PERFORMANCE CURVES

Note 1: The graphs and tables provided following this note are a statistical summary based on a limited number

of samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

Typical Device

1.00

0.75

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

ꢀ0.75

ꢀ1.00

1.00

0.75

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

ꢀ0.75

ꢀ1.00

ꢀ40Cꢁꢀ 5.5V

ꢀ40Cꢁꢀ 2.7V

ꢀ40Cꢁꢀ 1.8V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 5.5V

+25Cꢁꢀ 2.7V

+25Cꢁꢀ 1.8V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 5.5V

+85Cꢁꢀ 2.7V

+85Cꢁꢀ 1.8V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 5.5V

+125Cꢁꢀ 2.7V

+125Cꢁꢀ 1.8V

+125Cꢁꢀ 1.0V

ꢀ40Cꢁꢀ 2.0V

ꢀ40Cꢁꢀ 1.8V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 2.0V

+25Cꢁꢀ 1.8V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 2.0V

+85Cꢁꢀ 1.8V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 2.0V

+125Cꢁꢀ 1.8V

+125Cꢁꢀ 1.0V

0

8

16

24

32

40

48

56

64

0

8

16

24

32

40

48

56

64

DAC Wiper Code

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-1:

and Temperature.

INL vs. Code (00h to 3Fh)

FIGURE 2-3:

and Temperature.

INL vs. Code (00h to 3Fh)

V_DD= 5.5V, V_REF= 5.5V, 2.7V, 1.8V, and 1.0V.

V_DD= 2.0V, V_REF= 2.0V, 1.8V, and 1.0V.

Typical Device

1.00

0.75

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

ꢀ0.75

ꢀ1.00

0.75

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

ꢀ40Cꢁꢀ 2.7V

ꢀ40Cꢁꢀ 1.8V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 2.7V

+25Cꢁꢀ 1.8V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 2.7V

+85Cꢁꢀ 1.8V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 2.7V

+125Cꢁꢀ 1.8V

+125Cꢁꢀ 1.0V

ꢀ0.75

ꢀ1.00

ꢀ40Cꢁꢀ 1.6V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 1.6V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 1.6V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 1.6V

+125Cꢁꢀ 1.0V

0

8

16

24

32

40

48

56

64

0

8

16

24

32

40

48

56

64

DAC Wiper Code

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-2:

and Temperature.

_DD= 2.7V, V_REF= 2.7V, 1.8V, and 1.0V.

INL vs. Code (00h to 3Fh)

FIGURE 2-4:

and Temperature.

V_DD= 1.8V, V_REF= 1.6V, and 1.0V.

INL vs. Code (00h to 3Fh)

V

 2012 Microchip Technology Inc.

DS25154A-page 11

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

Typical Device

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

ꢀ40Cꢁꢀ 5.5V

ꢀ40Cꢁꢀ 2.7V

ꢀ40Cꢁꢀ 1.8V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 5.5V

+25Cꢁꢀ 2.7V

+25Cꢁꢀ 1.8V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 5.5V

+85Cꢁꢀ 2.7V

+85Cꢁꢀ 1.8V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 5.5V

+125Cꢁꢀ 2.7V

+125Cꢁꢀ 1.8V

+125Cꢁꢀ 1.0V

ꢀ40Cꢁꢀ 2.0V

ꢀ40Cꢁꢀ 1.8V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 2.0V

+25Cꢁꢀ 1.8V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 2.0V

+85Cꢁꢀ 1.8V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 2.0V

+125Cꢁꢀ 1.8V

+125Cꢁꢀ 1.0V

0

8

16

24

32

40

48

56

64

0

8

16

24

32

40

48

56

64

DAC Wiper Code

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-5:

and Temperature.

DNL vs. Code (00h to 3Fh)

FIGURE 2-7:

and Temperature.

DNL vs. Code (00h to 3Fh)

V_DD= 5.5V, V_REF= 5.5V, 2.7V, 1.8V, and 1.0V.

V_DD= 2.0V, V_REF= 2.0V, 1.8V, and 1.0V.

Typical Device

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

ꢀ40Cꢁꢀ 1.6V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 1.6V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 1.6V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 1.6V

+125Cꢁꢀ 1.0V

ꢀ40Cꢁꢀ 2.7V

ꢀ40Cꢁꢀ 1.8V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 2.7V

+25Cꢁꢀ 1.8V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 2.7V

+85Cꢁꢀ 1.8V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 2.7V

+125Cꢁꢀ 1.8V

+125Cꢁꢀ 1.0V

0.25

0.00

ꢀ0.25

ꢀ0.50

0

8

16

24

32

40

48

56

64

0

8

16

24

32

40

48

56

64

DAC Wiper Code

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-6:

and Temperature.

_DD= 2.7V, V_REF= 2.7V, 1.8V, and 1.0V.

DNL vs. Code (00h to 3Fh)

FIGURE 2-8:

and Temperature.

V_DD= 1.8V, V_REF= 1.6V, and 1.0V.

DNL vs. Code (00h to 3Fh)

V

DS25154A-page 12

 2012 Microchip Technology Inc.

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

Typical Device

0.00

ꢀ0.20

ꢀ0.40

ꢀ0.60

ꢀ0.80

ꢀ1.00

0.00

ꢀ0.20

ꢀ0.40

ꢀ0.60

ꢀ0.80

ꢀ1.00

ꢀ1.20

ꢀ1.40

ꢀ1.60

WhenꢁV_REF=ꢁV_DD

FSEꢁꢀ 5.5V

FSEꢁꢀ 2.7V

FSEꢁꢀ 1.8V

FSEꢁꢀ 1.0V

FSEꢁꢀ 2.0V

FSEꢁꢀ 1.8V

FSEꢁꢀ 1.0V

ꢀ40

ꢀ20

0

20

40

60

80

100

120

ꢀ40

ꢀ20

0

20

40

60

80

100

120

Temperature (°C)

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-9:

Full Scale Error (FSE) vs.

FIGURE 2-11:

Full Scale Error (FSE) vs.

Temperature.

V_DD= 5.5V, V_REF= 5.5V, 2.7V, 1.8V, and 1.0V.

V_DD= 2.0V, V_REF= 2.0V, 1.8V, and 1.0V.

Typical Device

0.00

ꢀ1.00

ꢀ2.00

ꢀ3.00

ꢀ4.00

ꢀ5.00

ꢀ0.20

ꢀ0.40

ꢀ0.60

WhenꢁV_REF=ꢁV_DD

ꢀ0.80

FSEꢁꢀ 2.7V

FSEꢁꢀ 1.6V

FSEꢁꢀ 1.0V

FSEꢁꢀ 1.8V

FSEꢁꢀ 1.0V

ꢀ1.00

ꢀ40

ꢀ20

0

20

40

60

80

100

120

ꢀ40

ꢀ20

0

20

40

60

80

100

120

Temperature (°C)

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-10:

Full Scale Error (FSE) vs.

FIGURE 2-12:

Full Scale Error (FSE) vs.

Temperature.

V_DD= 2.7V, V_REF= 2.7V, 1.8V, and 1.0V.

V_DD= 1.8V, V_REF= 1.6V, and 1.0V.

 2012 Microchip Technology Inc.

DS25154A-page 13

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

Typical Device

1.00

0.80

0.60

0.40

0.20

0.00

1.00

0.80

0.60

0.40

0.20

0.00

ZSEꢁꢀ 2.0V

ZSEꢁꢀ 1.8V

ZSEꢁꢀ 1.0V

ZSEꢁꢀ 5.5V

ZSEꢁꢀ 2.7V

ZSEꢁꢀ 1.8V

ZSEꢁꢀ 1.0V

ꢀ40

ꢀ20

0

20

40

60

80

100

120

ꢀ40

ꢀ20

0

20

40

60

80

100

120

Temperature (°C)

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-13:

Zero Scale Error (ZSE) vs.

FIGURE 2-15:

Zero Scale Error (ZSE) vs.

Temperature.

V_DD= 5.5V, V_REF= 5.5V, 2.7V, 1.8V, and 1.0V.

V_DD= 2.0V, V_REF= 2.0V, 1.8V, and 1.0V.

Typical Device

1.00

0.80

0.60

0.40

0.20

0.00

ZSEꢁꢀ 2.7V

ZSEꢁꢀ 1.6V

ZSEꢁꢀ 1.0V

ZSEꢁꢀ 1.8V

ZSEꢁꢀ 1.0V

0.80

0.60

0.40

0.20

0.00

ꢀ40

ꢀ20

0

20

40

60

80

100

120

ꢀ40

ꢀ20

0

20

40

60

80

100

120

Temperature (°C)

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-14:

Zero Scale Error (ZSE) vs.

FIGURE 2-16:

Zero Scale Error (ZSE) vs.

Temperature.

V_DD= 2.7V, V_REF= 2.7V, 1.8V, and 1.0V.

V_DD= 1.8V, V_REF= 1.6V, and 1.0V.

DS25154A-page 14

 2012 Microchip Technology Inc.

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

Typical Device

1.00

0.75

1.00

0.75

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

ꢀ0.75

ꢀ1.00

ꢀ40Cꢁꢀ 5.5V

+25Cꢁꢀ 5.5V

+25Cꢁꢀ 2.7V

+25Cꢁꢀ 1.8V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 5.5V

+125Cꢁꢀ 5.5V

+125Cꢁꢀ 2.7V

+125Cꢁꢀ 1.8V

+125Cꢁꢀ 1.0V

ꢀ40Cꢁꢀ 2.0V

ꢀ40Cꢁꢀ 1.8V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 2.0V

+25Cꢁꢀ 1.8V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 2.0V

+85Cꢁꢀ 1.8V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 2.0V

+125Cꢁꢀ 1.8V

+125Cꢁꢀ 1.0V

ꢀ40Cꢁꢀ 2.7V

ꢀ40Cꢁꢀ 1.8V

ꢀ40Cꢁꢀ 1.0V

+85Cꢁꢀ 2.7V

+85Cꢁꢀ 1.8V

+85Cꢁꢀ 1.0V

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

ꢀ0.75

ꢀ1.00

ꢀ1.25

ꢀ1.50

WhenꢁV_REF=ꢁV_DD

(codeꢁ=ꢁ64)

0

8

16

24

32

40

48

56

64

0

8

16

24

32

40

48

56

64

DAC Wiper Code

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-17:

Code and Temperature.

_DD= 5.5V, V_REF= 5.5V, 2.7V, 1.8V, and 1.0V.

Total Unadjusted Error vs.

FIGURE 2-19:

Code and Temperature.

Total Unadjusted Error vs.

V

_DD= 2.0V, V_REF= 2.0V, 1.8V, and 1.0V.

Typical Device

1.00

0.75

0.50

0.25

0.00

ꢀ0.25

ꢀ0.50

ꢀ0.75

ꢀ1.00

1.00

ꢀ40Cꢁꢀ 1.6V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 1.6V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 1.6V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 1.6V

+125Cꢁꢀ 1.0V

ꢀ40Cꢁꢀ 2.7V

ꢀ40Cꢁꢀ 1.8V

ꢀ40Cꢁꢀ 1.0V

+25Cꢁꢀ 2.7V

+25Cꢁꢀ 1.8V

+25Cꢁꢀ 1.0V

+85Cꢁꢀ 2.7V

+85Cꢁꢀ 1.8V

+85Cꢁꢀ 1.0V

+125Cꢁꢀ 2.7V

+125Cꢁꢀ 1.8V

+125Cꢁꢀ 1.0V

0.00

ꢀ1.00

ꢀ2.00

ꢀ3.00

ꢀ4.00

ꢀ5.00

WhenꢁV_REF=ꢁ1.6Vꢁ

(dueꢁtoꢁOutputꢁDriverꢁlinearityꢁatꢁV_DD=ꢁ1.8V)

WhenꢁV_REF=ꢁV_DD

(codeꢁ=ꢁ64)

0

8

16

24

32

40

48

56

64

0

8

16

24

32

40

48

56

64

DAC Wiper Code

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-18:

Code and Temperature.

_DD= 2.7V, V_REF= 2.7V, 1.8V, and 1.0V.

Total Unadjusted Error vs.

FIGURE 2-20:

Code and Temperature.

V_DD= 1.8V, V_REF= 1.6V, and 1.0V.

Total Unadjusted Error vs.

V

 2012 Microchip Technology Inc.

DS25154A-page 15

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

Typical Device

85.00

80.00

75.00

70.00

65.00

60.00

55.00

50.00

45.00

40.00

35.00

30.00

25.00

20.00

15.00

10.00

5.00

10.00

8.00

PPMꢁ/ꢁCꢁꢀ 2.0V

PPMꢁ/ꢁCꢁꢀ 1.8V

PPMꢁ/ꢁCꢁꢀ 1.0V

PPMꢁ/ꢁCꢁꢀ 5.5V

PPMꢁ/ꢁCꢁꢀ2.7V

PPMꢁ/ꢁCꢁꢀ 1.8V

PPMꢁ/ꢁCꢁꢀ 1.0V

6.00

4.00

2.00

0.00

ꢀ2.00

ꢀ4.00

ꢀ6.00

ꢀ8.00

ꢀ10.00

0.00

ꢀ5.00

ꢀ10.00

0

8

16

24

32

40

48

56

64

0

8

16

24

32

40

48

56

64

DAC Wiper Code

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-21:

V_OUTTempco vs. Code ( ( (

FIGURE 2-23:

V_OUTTempco vs. Code ( ( (

(V_OUT(+125C)- V_OUT(-40C)) / V_{OUT(+25C,Code=FS)}

/ 165 ) * 1,000,000 ),

)

(V_OUT(+125C)- V_OUT(-40C)) / V_{OUT(+25C,Code=FS)}

/ 165 ) * 1,000,000 ),

)

V_DD= 5.5V, V_REF= 5.5V, 2.7V, 1.8V, and 1.0V.

V

_DD= 2.0V, V_REF= 2.0V, 1.8V, and 1.0V.

Typical Device

350

PPMꢁ/ꢁCꢁꢀ 1.8V

PPMꢁ/ꢁCꢁꢀ 1.0V

14.00

330

310

290

270

250

230

210

190

170

150

130

110

90

PPMꢁ/ꢁCꢁꢀ 2.7V

12.00

PPMꢁ/ꢁCꢁꢀ 1.8V

PPMꢁ/ꢁCꢁꢀ 1.0V

10.00

8.00

6.00

4.00

2.00

0.00

ꢀ2.00

ꢀ4.00

ꢀ6.00

ꢀ8.00

ꢀ10.00

70

50

30

10

ꢀ10

0

8

16

24

32

40

48

56

64

0

8

16

24

32

40

48

56

64

DAC Wiper Code

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-22:

V_OUTTempco vs. Code ( ( (

FIGURE 2-24:

V_OUTTempco vs. Code ( ( (

(V_OUT(+125C)- V_OUT(-40C)) / V_{OUT(+25C,Code=FS)}

/ 165 ) * 1,000,000 ),

)

(V_OUT(+125C)- V_OUT(-40C)) / V_{OUT(+25C,Code=FS)}

/ 165 ) * 1,000,000 ),

)

V_DD= 2.7V, V_REF= 2.7V, 1.8V, and 1.0V.

V_DD= 1.8V, V_REF= 1.6V, and 1.0V.

DS25154A-page 16

 2012 Microchip Technology Inc.

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

Typical Device

1.0

0.8

0.6

0.4

0.2

0.0

220

200

180

160

140

120

100

80

VIL 5.5V

VIH 5.5V

VIL 2.7V

VIH 2.7V

VIL 1.8V

VIH 1.8V

400kHz 5.5V

400kHz 3.3V

400kHz 2.7V

400kHz 1.8V

100kHz 1.8V

100kHz 5.5V

100kHz 3.3V

100kHz 2.7V

60

40

-40 -20

0

20

40

60

80 100 120

-40 -20

0

20

40

60

80 100 120

Temperature (°C)

Temperature (C)

FIGURE 2-25:

SDA/SCL Inputs vs. Temperature and V_DD

V_IH/ V_ILThreshold of

FIGURE 2-27:

(I_DD) vs. SCL Frequency (f_SCL) and Temperature

Interface Active Current

.

V

_DD= 1.8V, 2.7V and 5.5V,

_REF= 1.0V and V_DD. (no load on V_OUT).

Typical Device

0.5

VOL 5.5V

VOL 2.7V

VOL 1.8V

Typical Device

0.4

0.3

0.2

0.1

0.0

220

Static 5.5V

Static 3.3V

Static 2.7V

Static 1.8V

200

180

160

140

120

100

80

-40 -20

0

20

40

60

80 100 120

60

Temperature (°C)

40

-40 -20

0

20

40

60

80 100 120

FIGURE 2-26:

Temperature.

V_OL(SDA) vs. V_DDand

Temperature (C)

FIGURE 2-28:

Interface Inactive Current

(STATIC) vs. Temperature and V_DD

.

V

_DD= 1.8V, 2.7V and 5.5V, V_REF= 1.0V and

_DD. (no load on V_OUT, SCL = SDA = V_DD).

 2012 Microchip Technology Inc.

DS25154A-page 17

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

Typical Device

5

4

3

2

1

0

5

4

3

2

1

0

Code = 40h

Code = 00h

Code = 40h

0

1000

2000

3000

4000

5000

0

2

4

6

8

10

12

14

I

_SOURCE/SINK(mA)

I

_SOURCE/SINK(mA)

FIGURE 2-29:

V_OUTvs. Resistive Load.

FIGURE 2-31:

V_OUTvs. Source / Sink

V_DD= 5.0V.

Current. V_DD= 5.0V.

Typical Device

2.7

1.8

0.9

0.0

Code = 40h

Code = 00h

Code = 40h

1.8

0.9

0.0

0

1000

2000

3000

4000

5000

0

2

4

6

8

10

12

14

I

_SOURCE/SINK(mA)

I_SOURCE/SINK(mA)

FIGURE 2-30:

_DD= 2.7V.

V_OUTvs. Resistive Load.

FIGURE 2-32:

Current. V_DD= 2.7V.

V_OUTvs. Source / Sink

V

DS25154A-page 18

 2012 Microchip Technology Inc.

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

Typical Device

0.78

0.77

0.76

0.75

0.74

0.73

0.72

VOUT 5.5V

VOUT 2.7V

-40 -20

0

20

40

60

80 100 120

Temperature (C)

FIGURE 2-33:

V_OUTAccuracy vs. V_DDand

Temperature.

Typical Device

23000

22000

21000

20000

19000

18000

RVREF5.5V

RVREF 2.7V

RVREF 1.8V

17000

-40 -20

0

20 40 60 80 100 120

Temperature (°C)

Analog Performance Specified for VDD ≥ 2.7V.

FIGURE 2-34:

R_VREFResistances vs. V_DD

and Temperature.

Typical Device

3.00

0.00

ꢀ3.00

ꢀ6.00

ꢀ9.00

ꢀ12.00

ꢀ15.00

ꢀ18.00

ꢀ21.00

ꢀ24.00

ꢀ27.00

ꢀ30.00

FullꢀScaleꢁꢀ VREFꢁ=ꢁ2.7V

MidꢀScaleꢁVREFꢁ=ꢁ2.7V

QuarterꢁScaleꢁVREFꢁ=ꢁ2.7V

FullꢀScaleꢁVREFꢁ=ꢁ5.5V

MidꢀScaleꢁVREFꢁ=ꢁ5.5V

QuarterꢁScaleꢁVREFꢁ=ꢁ5.5V

1

10

100

1000

Frequency (kHz)

FIGURE 2-35:

-3dB Bandwidth vs

Frequency, V_DD= 5.5V.

 2012 Microchip Technology Inc.

DS25154A-page 19

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

FIGURE 2-36:

Settling Time (00h to 40h),

_DD= 5.0V, V_REF= 5.0V, R_L= 5k, C_L= 200 pF

(Time scale = 2 µs / div).

Zero-Scale to Full-Scale

FIGURE 2-38:

(10h to 30h),

Half-Scale Settling Time

V

_DD= 5.0V, V_REF= 5.0V, R_L= 5k, C_L= 200 pF.

(Time scale = 2 µs / div)

FIGURE 2-37:

Full-Scale to Zero-Scale

FIGURE 2-39:

Half-Scale Settling Time

Settling Time (40h to 00h),

(30h to 10h),

V_DD= 5.0V, V_REF= 5.0V, R_L= 5k, C_L= 200 pF

V

_DD= 5.0V, V_REF= 5.0V, R_L= 5k, C_L= 200 pF

(Time scale = 2 µs / div).

DS25154A-page 20

 2012 Microchip Technology Inc.

MCP47A1

Note: Unless otherwise indicated, T_A= +25°C, V_DD= V_REF= 5V, V_SS= 0V, R_L= 5 k, C_L= 1 nF.

2.1

Test Circuit

V_DD

V_REF

V_IN

4.0V

(peak to

peak)

W

V_OUT

+

-

1.0V DC

FIGURE 2-41:

-3 db Gain vs. Frequency

Test.

FIGURE 2-40:

Digital Feedthrough

(SCL signal coupling to V_OUTpin);

V_DD= 5.0V, V_REF= 5.0V, F_SCL= 100 kHz,

V_OUT= 20h (V_OUTVoltage Scale = 20 mV/div,

Time scale = 2 µs / div).

 2012 Microchip Technology Inc.

DS25154A-page 21

MCP47A1

NOTES:

DS25154A-page 22

 2012 Microchip Technology Inc.

MCP47A1

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

Additional descriptions of the device pins follow.

TABLE 3-1:

PINOUT DESCRIPTION FOR THE MCP47A1

Package

Name

Type

Buffer

Type

Function

SC70-6

V_DD

V_SS

1

2

3

4

5

P

—

Positive Power Supply Input

Ground

P

SCL

SDA

V_OUT

I/O

ST (OD) I²C Serial Clock pin

ST (OD) I²C Serial Data pin

A

Output voltage

V_REF

6

I/O

Reference Voltage for V_OUToutput

Legend: A = Analog input

ST (OD) = Schmitt Trigger with Open Drain

I = Input

O = Output

I/O = Input/Output

P = Power

3.1

Positive Power Supply Input (V

)

3.5

Analog Output Voltage Pin (V

)

DD

OUT

The V_DDpin is the device’s positive power supply input.

The input power supply is relative to V_SSand can range

from 1.8V to 5.5V. A decoupling capacitor on V_DD

V_OUTis the DAC analog output pin. The DAC output

has an output amplifier.

V_OUTcan swing from approximately V_ZS(= V_SS) to V_FS

(= V_REF). In normal mode, the DC impedance of the

output pin is about 1 . See Section 7.0 “Output

Buffer” for more information.

(to V_SS) is recommended to achieve maximum

performance. Analog specifications are tested from

2.7V.

3.2

Ground (V

)

SS

3.6

Voltage Reference Pin (V

)

REF

The V_SSpin is the device ground reference.

This pin is the external voltage reference input. The

V_REFpin signal is unbuffered so the reference voltage

must have the current capability not to drop its voltage

when connected to the internal resistor ladder circuit

(20 k typical). See Section 6.0 “Resistor Network”

for more information.

2

3.3

I C Serial Clock (SCL)

The SCL pin is the serial clock pin of the I²C interface.

The MCP47A1 acts only as a slave and the SCL pin

accepts only external serial clocks. The SCL pin is an

open-drain output. Refer to Section 5.0 “Serial

Interface - I²C Module” for more details of I²C Serial

Interface communication.

2

3.4

I C Serial Data (SDA)

The SDA pin is the serial data pin of the I²C interface.

The SDA pin has a Schmitt trigger input and an

open-drain output. Refer to Section 5.0 “Serial

Interface - I²C Module” for more details of I²C Serial

Interface communication.

 2012 Microchip Technology Inc.

DS25154A-page 23

MCP47A1

NOTES:

DS25154A-page 24

 2012 Microchip Technology Inc.

MCP47A1

4.0

GENERAL OVERVIEW

V_REF

The MCP47A1 device is a general purpose DAC

intended to be used in applications where a program-

mable voltage output with moderate bandwidth is

desired.

A

R_FS

Applications generally suited for the MCP47A1 devices

include:

(1)

R_W

R_S

• Set point or offset trimming

• Sensor calibration

R_S

• Cost-sensitive mechanical trim pot replacement

Goes to Output

Buffer’s input

The MCP47A1 has four main functional blocks. These

are:

W

• POR/BOR Operation

• Serial Interface - I²C Module

• Resistor Network

(1)

R_W

R_S

• Output Buffer

The POR/BOR operation is discussed in this section

and the I²C and Resistor Network operation are

described in their own sections. The commands are

discussed in Section 5.3, Serial Commands.

R_ZS

Analog Switch Mux

B

Figure 4-1 shows a block diagram for the resistive

network of the device. An external pin, called V_REF, is

the DAC’s reference voltage. The resistance from the

V_REFpin to ground is typically 20 k. The reference

voltage connected to the V_REFpin needs to support this

resistive load.

+

Op Amp

V_OUT

-

This resistor network functions as a windowed voltage

divider. This means that the V_OUTpin’s voltage range is

from approximately V_SSto approximately V_REF

.

Note 1: The wiper resistance is tap dependent.

That is, each tap selection resistance

has a small variation.

2: The R_FSand R_ZSresistances are

determined by the analog switches that

connect the resistor network to the other

circuitry.

FIGURE 4-1:

Resistor Network and

Output Buffer Block Diagram.

 2012 Microchip Technology Inc.

DS25154A-page 25

MCP47A1

4.1.2

BROWN-OUT RESET

4.1

POR/BOR Operation

When the device powers down, the device V_DDwill

cross the V_POR/V_BORvoltage (V_BOR< 1.8V). Once the

V_DDvoltage decreases below the V_POR/V_BORvoltage,

the following happens:

The Power-on Reset is the case where the device has

power applied to it from V_SS. The Brown-out Reset

occurs when a device had power applied to it, and that

power (voltage) drops below the specified range.

• Serial Interface is disabled

The device’s RAM retention voltage (V_RAM) is lower

than the POR/BOR voltage trip point (V_POR/V_BOR).

This ensures that when the device Power-on Reset

occurs, the logic can retain default values that are

loaded. The maximum V_POR/V_BORvoltage is less than

1.8V. When V_POR/V_BOR< V_DD< 1.8V, the DACs’ elec-

trical performance may not meet the data sheet

specifications.

If the V_DDvoltage decreases below the V_RAMvoltage,

the following happens:

• Volatile Serial Shift Register (SSR) and Wiper

register may become corrupted

As the voltage recovers above the V_POR/V_BORvoltage,

see Section 4.1.1 “Power-on Reset”.

Serial commands not completed due to a Brown-out

condition may cause the memory location to become

corrupted.

Table 4-2 shows the DAC’s level of functionality across

the entire V_DDrange, while Figure 4-2 illustrates the

Power-up and Brown-out functionality.

4.1.3

WIPER REGISTER (RAM)

4.1.1

POWER-ON RESET

The Wiper Register is 7-bit volatile memory that starts

functioning at the RAM retention voltage (V_RAM). The

Wiper Register will be loaded with the default wiper

value when V_DDrises above the V_POR/V_BORvoltage.

When the device powers up, the device V_DDwill cross

the V_POR/V_BORvoltage. Once the V_DDvoltage crosses

the V_POR/V_BORvoltage, the following happens:

• Volatile Serial Shift Register / Wiper register is

loaded with the default values (see Table 4-1)

4.1.4

DEVICE CURRENTS

• The device is capable of digital operation

The current of the device can be classified into two

modes of the device operation. These are:

Note:

At voltages below V_DD(MIN), the electrical

performance of the I²C interface may not

meet the data sheet specifications

• Serial Interface Inactive (Static Operation)

• Serial Interface Active

Static Operation occurs when a Stop condition is

received. Static Operation is exited when a Start

condition is received.

TABLE 4-1:

DEFAULT POR WIPER

SETTING SELECTION

Default POR

Wiper Setting Register (SSR)

Serial Shift

Wiper Register

Mid-scale

20h

TABLE 4-2:

V_DDLevel

DEVICE FUNCTIONALITY AT EACH V_DDREGION (Note 1)

Serial

V_OUT

DAC Register Setting

Comment

Interface

V

_DD< V_TH

Ignored

“Unknown”

Pulled Low

Unknown

V_TH< V_DD< V_BORIgnored

V_BOR V_DD< 1.8V “Unknown” Operational with reduced DAC Register loaded with

electrical specifications POR/BOR value

1.8V  V_DD 5.5V Accepted Operational DAC Register determines Meets the data sheet

Serial Value specifications

Note 1: For system voltages below the minimum operating voltage, it is recommended to use a voltage supervisor

to hold the system in reset. This will ensure that MCP47x1 commands are not attempted out of the oper-

ating range of the device.

DS25154A-page 26

 2012 Microchip Technology Inc.

MCP47A1

Normal Operation Range

V_DD

Outside Specified

AC/DC Range

Normal Operation Range

1.8V

V_POR/BOR

V_RAM

V_SS

Below Minimum Operating Voltage

Device’s Serial

Interface is

“Not Operational”

V_BORdelay

Wiper forced to default POR/BOR setting

FIGURE 4-2:

Power-up and Brown-out.

 2012 Microchip Technology Inc.

DS25154A-page 27

MCP47A1

NOTES:

DS25154A-page 28

 2012 Microchip Technology Inc.

MCP47A1

2

5.1

I C I/O Considerations

5.0

SERIAL INTERFACE -

I C MODULE

2

I²C specifications require active low, passive high

functionality on devices interfacing to the bus. Since

devices may be operating on separate power supply

sources, ESD clamping diodes are not permitted. The

specification recommends using open drain transistors

tied to V_SS(common) with a pull-up resistor. The

specification makes some general recommendations

on the size of this pull-up, but does not specify the

exact value since bus speeds and bus capacitance

impacts the pull-up value for optimum system

performance.

A 2-wire I²C serial protocol is used to write or read the

DAC’s wiper register. The I²C protocol utilizes the SCL

input pin and SDA input/output pin.

The I²C serial interface supports the following features:

• Slave mode of operation

• 7-bit addressing

• The following clock rate modes are supported:

- Standard mode, bit rates up to 100 kb/s

- Fast mode, bit rates up to 400 kb/s

• Support Multi-Master Applications

Common pull-up values range from 1 k to a maximum

of ~10 k. Power sensitive applications tend to choose

higher values to minimize current losses during

communication but these applications also typically

The serial clock is generated by the Master.

The I²C Module is compatible with the NXP I²C

specification (# UM10204). Only the field types, field

lengths, timings, etc. of a frame are defined. The frame

content defines the behavior of the device. The frame

content for the MCP47A1 device is defined in this sec-

tion of the data sheet.

utilize lower V_DD

.

The SDA and SCL float (are not driving) when the

device is powered down.

A "glitch" filter is on the SCL and SDA pins when the pin

is an input. When these pins are an output, there is a

slew rate control of the pin that is independent of device

frequency.

Figure 5-1 shows a typical I²C bus configuration.

Single I²C Bus Configuration

5.1.1

SLOPE CONTROL

The device implements slope control on the SDA

output. The slope control is defined by the fast mode

specifications.

Device 1

Device 3

Device n

Host

Controller

For Fast (FS) mode, the device has spike suppression

and Schmidt trigger inputs on the SDA and SCL pins.

Device 4

Typical Application I²C Bus

Device 2

FIGURE 5-1:

Configurations.

Refer to Section 2.0 “Typical Performance Curves”,

AC/DC Electrical Characteristics table for detailed input

threshold and timing specifications.

 2012 Microchip Technology Inc.

DS25154A-page 29

MCP47A1

2

If the Slave Address is not valid, the Slave Device will

issue a Not A (A). The A bit will have the SDA signal

high.

5.2

I C Bit Definitions

I²C bit definitions include:

• Start Bit

If an error condition occurs (such as an A instead of A)

then a START bit must be issued to reset the command

state machine.

• Data Bit

• Acknowledge (A) Bit

• Repeated Start Bit

• Stop Bit

TABLE 5-1:

Event

MCP47A1 A / A RESPONSES

• Clock Stretching

Acknowledge

Comment

Bit Response

Figure 5-8 shows the waveform for these states.

General Call

A

5.2.1

START BIT

SlaveAddress

valid

The Start bit (see Figure 5-2) indicates the beginning of

a data transfer sequence. The Start bit is defined as the

SDA signal falling when the SCL signal is “High”.

SlaveAddress

not valid

A

Bus Collision

N.A.

I²C Module Resets,

or a “Don’t Care” if

the collision occurs

on the Masters

“Start bit”.

2nd Bit

1st Bit

SDA

SCL

S

FIGURE 5-2:

Start Bit.

5.2.4

REPEATED START BIT

The Repeated Start bit (see Figure 5-5) indicates

the current Master Device wishes to continue

communicating with the current Slave Device without

releasing the I²C bus. The Repeated Start condition is

the same as the Start condition, except that the

Repeated Start bit follows a Start bit (with the Data bits

+ A bit) and not a Stop bit.

5.2.2 DATA BIT

The SDA signal may change state while the SCL signal

is Low. While the SCL signal is High, the SDA signal

MUST be stable (see Figure 5-3).

2nd Bit

1st Bit

SDA

The Start bit is the beginning of a data transfer

sequence and is defined as the SDA signal falling when

the SCL signal is “High”.

SCL

Note 1: A bus collision during the Repeated Start

FIGURE 5-3:

Data Bit.

condition occurs if:

• SDA is sampled low when SCL goes

from low to high.

5.2.3

ACKNOWLEDGE (A) BIT

The A bit (see Figure 5-4) is a response from the Slave

device to the Master device. Depending on the context

of the transfer sequence, the A bit may indicate

different things. Typically the Slave device will supply

an A response after the Start bit and 8 “data” bits have

been received. The A bit will have the SDA signal low.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data "1".

1st Bit

SDA

D0

A

SDA

SCL

8

9

SCL

FIGURE 5-4:

Acknowledge Waveform.

Sr = Repeated Start

FIGURE 5-5:

Repeat Start Condition

Waveform.

DS25154A-page 30

 2012 Microchip Technology Inc.

MCP47A1

5.2.5

STOP BIT

5.2.7

ABORTING A TRANSMISSION

The Stop bit (see Figure 5-6) indicates the end of the

I²C Data Transfer Sequence. The Stop bit is defined as

the SDA signal rising when the SCL signal is “High”.

A Stop bit resets the I²C interface of the other devices.

If any part of the I²C transmission does not meet the

command format, it is aborted. This can be intentionally

accomplished with a START or STOP condition. This is

done so that noisy transmissions (usually an extra

START or STOP condition) are aborted before they

corrupt the device.

A / A

SDA

SCL

5.2.8

IGNORING AN I²C TRANSMISSION

AND “FALLING OFF” THE BUS

The MCP47A1 expects to receive entire, valid I²C com-

mands and will assume any command not defined as a

valid command is due to a bus corruption, and will enter

a passive high condition on the SDA signal. All signals

will be ignored until the next valid START condition and

CONTROL BYTE are received.

P

FIGURE 5-6:

Transmit Mode.

Stop Condition Receive or

5.2.6

CLOCK STRETCHING

“Clock Stretching” is something that the secondary

device can do, to allow additional time to “respond” to

the “data” that has been received.

The MCP47A1 will not stretch the clock signal (SCL)

since memory read accesses occur fast enough.

SDA

SCL

S

1st 2nd 3rd 4th 5th 6th 7th 8th A/A 1st 2nd 3rd 4th 5th 6th 7th 8th A/A

P

Bit Bit Bit Bit Bit Bit Bit Bit

FIGURE 5-7:

Typical 16-bit I²C Waveform Format.

SDA

SCL

START

Condition

Data allowed

to change

Data or

A valid

STOP

Condition

FIGURE 5-8:

I²C Data States and Bit Sequence.

 2012 Microchip Technology Inc.

DS25154A-page 31

MCP47A1

5.2.9

I²C COMMAND PROTOCOL

TABLE 5-2:

Device

DEVICE I²C ADDRESS

I²C Address

The MCP47A1 is a slave I²C device which supports 7-

bit slave addressing. The slave address contains seven

fixed bits. Figure 5-9 shows the control byte format.

Binary

‘0101110’ 0x5C

‘0111110’ 0x7C

Hex ⁽¹⁾Code Comment

A0

A1

MCP47A1

5.2.9.1

Control Byte (Slave Address)

Note 1: The LSb of the 8-bit hex code is the I²C

Read/Write (R/W) bit. This hex value has

a R/W bit = “0” (write). If the R/W bit

reflected a read, these values would be

0x5D and 0x7D.

The Control Byte is always preceded by a START

condition. The Control Byte contains the slave address

consisting of seven fixed bits and the R/W bit. Figure 5-

9 shows the control byte format and Table 5-2 shows

the I²C address for the devices.

Note 1: The MCP47A1 device supports two differ-

ent I²C address (A0 and A1). This allows

two MCP47A1 devices on the same I²C

bus.

Slave Address

S

A6 A5 A4 A3 A2 A1 A0 R/W

“0”“1” “0”“1” “1” “1”“0”

A/A

5.2.9.2

Hardware Address Pins

Start

bit

The MCP47A1 does not support hardware address

bits.

R/W bit

R/W = 0= write

R/W = 1= read

5.2.10

GENERAL CALL

A bit (controlled by slave device)

The General Call is a method that the Master device

can communicate with all other Slave devices.

A = 0= Slave Device Acknowledges byte

A = 1= Slave Device does not Acknowledge byte

The MCP47A1 devices do not respond to General Call

address and commands, and therefore the

communications are Not Acknowledged.

FIGURE 5-9:

Slave Address Bits in the

I²C Control Byte.

Second Byte

0 0 0 0 0 0 0 0

0

A

S

A

X X

X

P

General Call Address

“7-bit Command”

Reserved 7-bit Commands (By I²C Specification - NXP specification # UM10204, Ver. 03 16 January 2007)

“0000 011”b- Reset and write programmable part of slave address by hardware

“0000 010”b- Write programmable part of slave address by hardware

“0000 000”b- NOT Allowed

The Following is a “Hardware General Call” Format

Second Byte

n occurrences of (Data + A / A)

A X X X X A P

0 0 0 0 0 0 0 0

S

A

X X

X

1

X

General Call Address

“7-bit Command”

This indicates a “Hardware General Call”.

MCP47A1 will ignore this byte and

all following bytes (and A), until

a Stop bit (P) is encountered.

FIGURE 5-10:

General Call Formats.

DS25154A-page 32

 2012 Microchip Technology Inc.

MCP47A1

5.3.2

READ OPERATIONS

5.3

Serial Commands

The read operation requires the START condition,

Control Byte, Acknowledge, Command Code,

Acknowledge, Restart Condition, Control Byte,

Acknowledge, Data Byte, the master generating the

A and STOP (or RESTART) condition. The first Control

Byte requires the R/W bit equal to a logic zero (R/W =

“0”) to write the Command Code, while the second

Control Byte requires the R/W bit equal to a logic one

(R/W = “1”) to generate a read sequence. The

MCP47A1 will A the Slave Address Byte and A all the

Data Bytes. The I²C Master will A the Slave Address

Byte and the last Data Byte. If there are multiple Data

Bytes, the I²C Master will A all Data Bytes except the

last Data Byte (which it will A).

The MCP47A1 devices support two serial commands.

These commands are:

• Write Operation

• Read Operations

The I²C command formats have been defined to

support the SMBus version 2.0 Write Byte/Word

Protocol formats and Read Byte/Word Protocol

formats. The SMBus specification that defines this

operation is Section 5 of the Version 2.0 document

(August 3, 2000).

This protocol format may be convenient for customers

using library routines for the I²C bus, where all they

need to do is specify the command (read, write, ...) with

the Device Address, the Register Address, and the

Data.

The MCP47A1 maintains control of the SDA signal until

all data bits have been clocked out.

The command is terminated once a Stop (P) or Restart

(S) condition occurs. Refer to Figure 5-14 for the read

command sequence. For a single read, the master

sends a STOP or RESTART condition after the 1st data

byte (and A bit) is sent from the slave.

5.3.1

WRITE OPERATION

The write operation requires the START condition,

Control Byte, Acknowledge, Command Code,

Acknowledge, Data Byte, Acknowledge and STOP (or

RESTART) condition. The Control (Slave Address)

Byte requires the R/W bit equal to a logic zero (R/W =

“0”) to generate a write sequence. The MCP47A1 is

responsible for generating the Acknowledge (A) bits.

The MSb of each Data Byte is always a “0”, since the

wiper register is only 7-bits wide.

Figure 5-15 shows the I²C read communication

behavior of the Master Device and the MCP47A1

device and the resultant I²C bus values.

Data is written to the MCP47A1 after every byte

transfer (during the A bit). If a STOP or RESTART

condition is generated during a data transfer (before

the A bit), the data will not be written to MCP47A1.

Note:

A command code with a non-zero value

will cause the data not to be read from the

wiper register

Data bytes may be written after each Acknowledge.

The command is terminated once a Stop (P) condition

occurs. Refer to Figure 5-11 for the single byte write

sequence and Figure 5-12 for the generic (multi-byte)

write sequence. For a single byte write, the master

sends a STOP or RESTART condition after the 1st data

byte is sent.

The MSb of each Data Byte is a don’t care, since the

wiper register is only 7-bits wide.

The command is terminated once a Stop (P) or Restart

(S) condition occurs.

Figure 5-13 shows the I²C write communication

behavior of the Master Device and the MCP47A1

device and the resultant I²C bus values.

Note:

A command code with a non-zero value

will cause the data not to be written to the

wiper register

 2012 Microchip Technology Inc.

DS25154A-page 33

MCP47A1

Fixed

Address

Read/Write bit (“0”= Write)

STOP bit

0

P

S 0 1 0 1 1 1 0 0 A

Slave Address Byte ⁽¹⁾

0

A X D6 D5 D4 D3 D2 D1 D0 A

Data Byte

Command Code

Legend

S = Start Condition

P = Stop Condition

A = Acknowledge

X = Don’t Care

R/W = Read/Write bit

D6:D0 = Data bits

Note 1: Example using Slave Address Option A0 (5Ch).

FIGURE 5-11:

I²C Single Byte Write Command Format.

Fixed

Address

Read/Write bit (“0”= Write)

0

0 0

S 0 1 0 1 1 1 1 0 A

0

A X D6 D5 D4 D3 D2 D1 D0 A

Slave Address Byte ⁽¹⁾

Command Code

Data Byte

STOP bit

X D6 D5 D4

P

D3 D2 D1 D0 A X D6 D5 D4 D3 D2 D1 D0 A

Data Byte Data Byte

Legend

S = Start Condition

P = Stop Condition

A = Acknowledge

X = Don’t Care

R/W = Read/Write bit

D6:D0 = Data bits

Note 1: Example using Slave Address Option A0 (5Ch).

FIGURE 5-12:

I²C Write Command Format.

DS25154A-page 34

 2012 Microchip Technology Inc.

MCP47A1

Write 1 Byte with Command Code = 00h

R A

A

/

C

S Slave Address

W K Command Code

K Data Byte

K P

Master

S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1 P

MCP47A1

I²C Bus

0

S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0 P

Write 2 Byte with Command Code = 00h

R A

A

C

A

C

K

/

C

S Slave Address

W K Command Code

K Data Byte

Master

S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1

MCP47A1

I²C Bus

0

S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0

A

C

Data Byte

K P

Master

0 d d d d d d d 1 P

MCP47A1

I²C Bus

0

0 d d d d d d d 0 P

FIGURE 5-13:

I²C Write Communication Behavior.

 2012 Microchip Technology Inc.

DS25154A-page 35

MCP47A1

Read/Write bit (“0”= Write)

0

0 0

S

0

1

0

1

0

0 A

0

0 0 A

Legend

S = Start Condition

Slave Address Byte ⁽³⁾

Command Code

Read/Write bit (“1”= Read)

P = Stop Condition

A = Acknowledge

X = Don’t Care

STOP bit

⁽²⁾P

0

1

0 1

S

1

0

1 A 0 D6 D5 D4 D3 D2 D1 D0 A

R/W = Read/Write bit

D6:D0 = Data bits

Slave Address Byte ⁽³⁾

Data Byte

Note 1: Master Device is responsible for ACK / NACK signal. If a NACK signal occurs, the MCP47A1 will abort this transfer

and release the bus.

2: The Master Device will Not ACK, and the MCP47A1 will release the bus so the Master Device can generate a Stop or

Repeated Start condition.

3: Example using Slave Address Option A0 (5Ch).

FIGURE 5-14:

I²C Read Command Format.

Read 1 Byte with Command Code = 00h

R A

A

R A

/

C

C R

/ C

S Slave Address

W K Command Code

K S Slave Address

W K

Master

S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1

MCP47A1

I²C Bus

0

S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0

A

C

Data Byte

K P

Master

1 P

MCP47A1

0 d d d d d d d 1

I²C Bus

0 d d d d d d d 1 P

Read 2 Byte with Command Code = 00h

R A

A

R A

/

C

C R

/ C

S Slave Address

W K Command Code

K S Slave Address

W K

Master

S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1

MCP47A1

I²C Bus

0

S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0

A

C

Data Byte

K Data Byte

K P

Master

0

1 P

MCP47A1

I²C Bus

0 d d d d d d d 1 0 d d d d d d d 1

0 d d d d d d d 0 0 d d d d d d d 1 P

FIGURE 5-15:

I²C Read Communication Behavior.

DS25154A-page 36

 2012 Microchip Technology Inc.

MCP47A1

6.2

R

Resistor Ladder

AB

6.0

RESISTOR NETWORK

The R_ABresistor ladder is a digital potentiometer in a

voltage divider configuration. The R_ABresistor ladder

has 64 R_Sresistors in series. This resistor ladder has

65 wiper taps which allow wiper connectivity to the

bottom (terminal B), Zero-Scale, and the top (terminal

A), Full-Scale, of the resistor ladder (see Figure 6-1).

With an even number of R_Sresistors in the R_ABladder,

when the wiper is at the Mid-Scale value, V_OUTequals

V_REF/ 2. The R_ABresistance also includes the R_FSand

The Resistor Network is made up of an R_ABresistor

ladder. The R_ABresistor has a typical resistance of

20 k. Figure 6-1 shows a block diagram for the

resistor network and output buffer. The resistance from

the V_REFpin to ground is referred to as R_VREF

.

The 7-bit I²C Data Byte (00h - 7Fh) is decoded to the 6-

bit wiper value (00h - 40h). Section 6.3 describes the

Serial Shift buffer to Wiper register decoding.

R

_ZSresistances (see Section 6.2.2). The R_AB(and R_S)

6.1

R

Resistance

VREF

resistance has small variations over voltage and

temperature. The typical R_ABresistance is 10k .

R_VREFresistance is the resistance from the V_REFpin to

ground and is the R_ABresistances. Equation 6-1 shows

6.2.1

THE WIPER

how to calculate R_VREF

.

The value in the volatile wiper register selects which

analog switch to close, connecting the W terminal to

the selected node of the resistor ladder. The Wiper reg-

ister value is derived from the Serial Shift Register

value (see Section 6.3).

6.1.1 V_REFPIN CURRENT (I_VREF

)

The current into the V_REFpin is dependent on the volt-

age on the V_REFpin (V_REF) and the R_VREFresistance.

The V_REFpin’s voltage source current capability should

support a resistive load that is the minimum R_VREF

resistance.

Any variation of the wiper resistance does not effect the

voltage at the W terminal, and therefore the input of the

output buffer.

EQUATION 6-1:

(V_REF

CALCULATING R_VREF

6.2.2

R_FSAND R_ZSRESISTORS

)

The R_FSand R_ZSresistances are artifacts of the R_AB

resistor implementation. These resistors are included

in the block diagram to help better model the actual

device operation. Equation 6-2 shows how to estimate

the R_S, R_FS, and R_ZSresistances, based on the

measured voltages of V_REF, V_FS, and V_ZSand the

R_VREF

=

(I_VREF

)

V_REFis the voltage on the V_REFpin.

_VREFis the current into the V_REFpin.

I

measured current I_VREF

.

EQUATION 6-2:

ESTIMATING R_S, R_FS

AND R_ZS

,

V_REF

R_FS

=

I_VREF

V_ZS

R_ZS

I_VREF

V_S

R_S=

I_VREF

Where:

V_S=

( V_FS- V_ZS

64

)

V_FSis the V_OUTvoltage when the wiper code is at

full-scale.

V_ZSis the V_OUTvoltage when the wiper code is at

zero-scale.

 2012 Microchip Technology Inc.

DS25154A-page 37

MCP47A1

V_REF

A

R_FS

N = 64

(40h)

(1)

R_W

R_S

N = 63

(3Fh)

(1)

R_W

N = 62

(3Eh)

W

+

Op Amp

V_OUT

N = 1

(01h)

-

(1)

R_W

R_S

N = 0

(00h)

Output Buffer

(Section 7.0)

Analog

Mux

R_ZS

B

Wiper Value

Resistor Network (Section 6.0)

Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a

small variation.

FIGURE 6-1:

Resistor Network and Output Buffer Block Diagram.

DS25154A-page 38

 2012 Microchip Technology Inc.

MCP47A1

6.3

Serial Buffer to Wiper Register

Decode

6.4

Resistor Variations

(Voltage and Temperature)

The I²C’s Data Byte is 8-bits, where only the lower 7-

bits are implemented. This register is called the Serial

Shift Register (SSR). The Wiper register supports

addressing of 65 taps (6-bit resolution). Table 6-1

shows the decoding of the Serial Shift Register to the

Wiper Register value.

The R_ABresistors are implemented to have minimal

variations (by design). Any variations should occur

uniformly on all the resistor elements, so the resistor’s

elements will track each other over temperature and

process variations.

The variation of the resistive elements over the operat-

ing voltage range is also minimal. Therefore the V_REF

resistance (R_VREF) of the device has minimal variation

due to operating voltage.

Note 1: The I²C Write and Read commands

access the value in the Serial Shift Regis-

ter (SSR).

2: The MSb of the I²C Data Byte is ignored

and not loaded into the SSR. A write of

C0h, will result in the same V_OUTvoltage

as a write of 40h (mid-scale). A subse-

quent read command (of the SSR) will

result in a value of 40h.

Since the V_OUTpin’s voltage is ratiometric, and the

resistive elements change uniformly over temperature,

process, and operating voltage variations. Minimal

variation should be seen on the V_OUTpin’s voltage.

6.5

POR Value

3: The 7-bit SSR value is decoded to a 6-bit

(65 taps) value that controls the wiper’s

position.

A POR/BOR event will load the volatile Serial Shift

Register (and therefore Wiper register) with the default

value. Table 6-2 shows the default values offered.

TABLE 6-1:

SERIAL SHIFT REGISTER

VALUE TO WIPER VALUE

TABLE 6-2:

Device

POR/BOR SETTINGS

Register Value ⁽¹⁾

I²C Write

Data

Wiper

Setting

SSR⁽¹⁾

Comment

Value⁽²⁾

SSR

Wiper

MCP47A1

Mid-scale

20h or A0h

20h

00h

Wiper Register at

Zero Scale,

V_OUT= V_SS

Note 1: Custom POR/BOR Wiper Setting options

are available; contact the local Microchip

Sales Office for additional information.

Custom options have NRE and minimum

volume requirements.

01h or 81h

02h or 82h

01h

02h

:

01h

02h

:

20h or A0h

20h

Mid-Scale (POR

value),

V_OUT= (1/2) * V_REF

:

3Eh or BEh 3Eh

3Eh

Wiper Register =

SSR - 20h

3Fh or BFh 3Fh

3Fh

40h

Wiper Register =

SSR - 20h

40h - 7Fh or 40h -

C0h - FFh 7Fh

Wiper Register at

Full Scale,

V_OUT= V_REF

Note 1: The Serial Shift Register (SSR) is 7-bits

wide and holds the value written from the

I²C Write command. An I²C Read com-

mand will read the value in this register.

2: The Wiper value is the value that controls

the resistor ladder’s wiper position.

 2012 Microchip Technology Inc.

DS25154A-page 39

MCP47A1

NOTES:

DS25154A-page 40

 2012 Microchip Technology Inc.

MCP47A1

7.1.1

OUTPUT VOLTAGE

7.0

OUTPUT BUFFER

The volatile DAC Register’s value controls the analog

V_OUTvoltage. The volatile Wiper Register’s value is

unsigned binary. The formula for the output voltage is

given in Equation 7-1.

As the device powers up, the V_OUTpin will float to an

unknown value. When the device’s V_DDis above the

transistor threshold voltage of the device, the output

will start being pulled low. After the V_DDis above the

POR/BOR trip point (V_BOR/V_POR), the resistor net-

work’s wiper will be loaded with the POR value (20h,

which is midscale). The output voltage of the buffer

(V_OUT) may not be within specification until the device

V_DDis at 2.7V. The outputs’ slew rate and settling time

must also be taken into account.

EQUATION 7-1:

CALCULATING OUTPUT

VOLTAGE (V_OUT

)

V_OUT= V_ZS+ (N * V_S)

When R_FS= R_ZS= 0 : V_ZS= 0V

_FS= V_REF

V

7.1

Output Buffer / V

Operation

OUT

V_ZSis the V_OUTvoltage when the wiper code = 00h.

The DAC output is buffered with a low power and

precision output amplifier (op amp). This amplifier

provides a rail-to-rail output with low offset voltage and

low noise. The amplifier’s output can drive the resistive

and capacitive loads without oscillation. The amplifier

provides a maximum load current which is enough for

most programmable voltage reference applications.

Figure 7-1 shows a block diagram.

N = wiper code = 0 to 64;

The Serial Shift Register’s value will be latched on the

falling edge of the acknowledge pulse of the write

command’s last byte. Then the V_OUTvoltage will start

driving to the new value.

The following events update the analog voltage output

(V_OUT):

Note 1: The load resistance must stay higher than

5 k for the stable and expected analog

output (to meet electrical specifications).

Refer to:

• Power-On-Reset.

• Falling edge of the acknowledge pulse of the last

write command byte.

•

Section 1.0 “Electrical Charac-

teristics” for the specifications of

the output amplifier.

7.1.2

STEP VOLTAGE (V_S)

The Step voltage is dependent on the device resolution

(64 R_S) and the output voltage range (V_ZSto V_FS).

Equation 7-2 shows the calculation for the step resis-

tance.

•

Section 7.3 “Driving Resistive

and Capacitive Loads” for addi-

tional design information.

EQUATION 7-2:

V_SCALCULATION

Gain =1x

(V_FS- V_ZS

)

V_S=

64

Op

V_FSis the V_OUTvoltage when the wiper code is at

full-scale.

V_OUT

Amp

V_W

V_ZSis the V_OUTvoltage when the wiper code is at

zero-scale.

FIGURE 7-1:

Output Buffer Block

Diagram.

Table 7-1 shows the calculated V_OUTvoltages for the

given volatile Wiper Register value. These calculations

are based on different V_REFvoltage values (1.5V, 3.3V,

and 5.0V) with an assumption that R_FS= R_ZS= 0 .

 2012 Microchip Technology Inc.

DS25154A-page 41

MCP47A1

TABLE 7-1:

Wiper Value

THEORETICAL DAC OUTPUT VALUES

V_OUT⁽1⁾

V_REF

3.3

V_OUT⁽1⁾

V_REF

3.3

Wiper Value

Ratio

Hex

Dec

1.5

5.0

Hex

Dec

1.5

5.0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

0

0.0000 0.0000 0.0000 0.0000

0.0156 0.0234 0.0516 0.0781

0.0313 0.0469 0.1031 0.1563

0.0469 0.0703 0.1547 0.2344

0.0625 0.0938 0.2063 0.3125

0.0781 0.1172 0.2578 0.3906

0.0938 0.1406 0.3094 0.4688

0.1094 0.1641 0.3609 0.5469

0.1250 0.1875 0.4125 0.6250

0.1406 0.2109 0.4641 0.7031

0.1563 0.2344 0.5156 0.7813

0.1719 0.2578 0.5672 0.8594

0.1875 0.2813 0.6188 0.9375

0.2031 0.3047 0.6703 1.0156

0.2188 0.3281 0.7219 1.0938

0.2344 0.3516 0.7734 1.1719

0.2500 0.3575 0.8250 1.2500

0.2656 0.3984 0.8766 1.3281

0.2813 0.4219 0.9281 1.4063

0.2969 0.4453 0.9797 1.4844

0.3125 0.4688 1.0313 1.5625

0.3281 0.4922 1.0828 1.6406

0.3438 0.5156 1.1344 1.7188

0.3594 0.5391 1.1859 1.7969

0.3750 0.5625 1.2375 1.8750

0.3906 0.5859 1.2891 1.9531

0.4063 0.6094 1.3406 2.0313

0.4219 0.6328 1.3922 2.1094

0.4375 0.6563 1.4438 2.1875

0.4531 0.6797 1.4953 2.2656

0.4688 0.7031 1.5469 2.3438

0.4844 0.7266 1.5984 2.4219

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

0.5000

0.5156

0.5313

0.5469

0.5625

0.5781

0.5938

0.6094

0.6250

0.6406

0.6563

0.6719

0.6875

0.7031

0.7188

0.7344

0.7500

0.7656

0.7813

0.7969

0.8125

0.8281

0.8438

0.8594

0.8750

0.8906

0.9063

0.9219

0.9375

0.9531

0.9688

0.9844

1.0000

0.7500 1.6500 2.5000

0.7734 1.7016 2.5781

0.7969 1.7531 2.6563

0.8203 1.8047 2.7344

0.8438 1.8563 2.8125

0.8672 1.9078 2.8906

0.8906 1.9594 2.9688

0.9141 2.0109 3.0469

0.9375 2.0625 3.1250

0.9609 2.1141 3.2031

0.9844 2.1656 3.2813

1.0078 2.2172 3.3594

1.0313 2.2688 3.4375

1.0547 2.3203 3.5156

1.0781 2.3719 3.5938

1.1016 2.4234 3.6719

1.1250 2.4750 3.7500

1.1484 2.5266 3.8281

1.1719 2.5781 3.9063

1.1953 2.6297 3.9844

1.2188 2.6813 4.0625

1.2422 2.7328 4.1406

1.2656 2.7844 4.2188

1.2891 2.8359 4.2969

1.3125 2.8875 4.3750

1.3359 2.9391 4.4531

1.3594 2.9906 4.5313

1.3828 3.0422 4.6094

1.4063 3.0938 4.6875

1.4297 3.1453 4.7656

1.4531 3.1969 4.8438

1.4766 3.2484 4.9219

1.5000 3.3000 5.0000

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Note 1:

V_OUTvoltages based on R_FSand R_ZS= 0 .

DS25154A-page 42

 2012 Microchip Technology Inc.

MCP47A1

Figure 7-3 shows the equations for solving for V_OUT

voltage, the V_REFvoltage, or the maximum DAC

Register code, based on knowing the requirements for

two of these variables. For V_DDvoltages below the

specified analog performance voltage (2.7V), the

calibration of the device could be done to ensure V_OUT

voltage is not driven into the output amplifier nonlinear

region via the DAC Register value / V_REFvoltage.

Using the measured V_NLvoltage as the V_OUTvoltage

will allow you to balance your selection of the V_REF

voltage and maximum DAC Code. The DAC Register

code of 64 is the full-scale code.

7.1.3

AMPLIFIER INPUT VOLTAGE (V_W)

To ensure that the amplifier is operating in its linear

range, the voltage (V_W) into the output amplifier’s input

has requirements that must be met.

For device V_DDvoltages  2.7V, the amplifier is in the

linear region for all V_REFvoltages ( 1.0V) and DAC

register codes.

For device V_DDvoltages < 2.7V, there will be a voltage

where the amplifier output is no longer linear with the

amplifier input voltage (V_W). This is shown in Figure 2-

20, where V_DD= 1.8V and the V_REF= 1.6V. Higher

DAC register codes are the first to encounter the

nonlinearity of the output buffer. The nonlinearity is also

influenced by the temperature of operation.

DAC Code

V_OUT= V_REF

*

64

Figure 7-2 shows the trend of the amplifier linearity

based on the device V_DD/ V_REFvoltages and the input

voltage to the amplifier. The trend will also be affected

by device temperature. V_NLis the voltage where the

amplifier’s output becomes nonlinear. While the V_W

voltage is less than the V_NLvoltage, the amplifier’s out-

put is linear. Once the device V_DDhas been lowered to

where the amplifier’s nonlinear range increases, the

two methods to keep V_W< V_NLare:

64 * V_OUT

DAC Code

V_REF

=

64 * V_OUT

DAC Code =

V_REF

FIGURE 7-3:

DAC Register Code.

Solving for V_OUT, V_REF, or

1. Lower the V_REFvoltage

2. Decrease the DAC Register code

Both methods reduce the maximum usable output

voltage.

V_DD

V_REF

/

V_DD= 5.5V

V_DD= 1.8V

V_W

Ideal

Actual

(Based on device

V_DDand temperature)

0

V_DD/ V_REF

V_OUT

FIGURE 7-2:

Amplifier Input (V_W) to

Amplifier Output (V_OUT) General Characteristics

(V_REF= V_DD).

 2012 Microchip Technology Inc.

DS25154A-page 43

MCP47A1

7.2

Output Slew Rate

7.3

Driving Resistive and Capacitive

Loads

Figure 7-4 shows an example of the slew rate of the

V_OUTpin. The slew rate can be affected by the

characteristics of the circuit connected to the V_OUTpin.

The V_OUTpin can drive up to 100 pF of capacitive load

in parallel with a 5 k resistive load (to meet electrical

specifications). Figure 2-29 shows the V_OUTvs.

Resistive Load.

V_OUT(B)

V_OUTdrops slowly as the load resistance decreases

after about 3.5 k . It is recommended to use a load

with R_Lgreater than 5 k.

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response with overshoot and ringing in the step

response. That is, since the V_OUTpin’s voltage does

not quickly follow the buffer’s input voltage (due to the

large capacitive load), the output buffer will overshoot

the desired target voltage. Once the driver detects this

overshoot, it compensates by forcing it to a voltage

below the target. This causes voltage ringing on the

V_OUTpin.

V_OUT(A)

Wiper = A

Wiper = B

Time

| V_OUT(B)- V_OUT(A)

|

Slew Rate =

T

FIGURE 7-4:

V_OUTPin Slew Rate.

7.2.1

SMALL CAPACITIVE LOAD

With a small capacitive load, the output buffer’s current

is not affected by the capacitive load (C_L). But still, the

V_OUTpin’s voltage is not a step transition from one

output value (wiper code value) to the next output

value. The change of the V_OUTvoltage is limited by the

output buffer’s characteristics, so the V_OUTpin voltage

will have a slope from the old voltage to the new

voltage. This slope is fixed for the output buffer, and is

referred to as the buffer slew rate (SR_BUF).

So, when driving large capacitive loads with the output

buffer, a small series resistor (R_ISO) at the output (see

Figure 7-5) improves the output buffer’s stability (feed-

back loop’s phase margin) by making the output load

resistive at higher frequencies. The bandwidth will be

generally lower than the bandwidth with no capacitive

load.

7.2.2

LARGE CAPACITIVE LOAD

V_OUT

V_CL

C_L

Op

Amp

V_W

With a larger capacitive load, the slew rate is deter-

mined by two factors:

R_ISO

R_L

• The output buffer’s short circuit current (I_SC

• The V_OUTpin’s external load

)

I_OUTcannot exceed the output buffer’s short circuit

current (I_SC), which fixes the output buffer slew rate

FIGURE 7-5:

Buffer for Large Capacitive Loads (C_L).

Circuit to Stabilize Output

(SR_BUF). The voltage on the capacitive load (C_L), V_CL

,

The R_ISOresistor value for your circuit needs to be

selected. The resulting frequency response peaking

and step response overshoot for this R_ISOresistor

value should be verified on the bench. Modify the

changes at a rate proportional to I_OUT, which fixes a

capacitive load slew rate (SR_CL).

So the V_CLvoltage slew rate is limited to the slower of

the output buffer’s internally set slew rate (SRBUF) and

the capacitive load slew rate (SR_CL).

R_ISO’s resistance value until the output characteristics

meet your requirements.

A method to evaluate the system’s performance is to

inject a step voltage on the V_REFpin and observe the

V_OUTpin’s characteristics.

Note:

Additional insight into circuit design for

driving capacitive loads can be found in

AN884 “Driving Capacitive Loads With Op

Amps” (DS00884).

DS25154A-page 44

 2012 Microchip Technology Inc.

MCP47A1

TABLE 7-2:

CALCULATION COMPARISON

7.4

Output Errors

Example Theoretical

Delta

The output error is caused by two factors. These are:

R_VREF

R_FS

20,180

—

• Characteristics of the Resistor Network

• Characteristics of the Output Buffer

100

80

0

100

80

R_ZS

Figure 7-6 shows the components of the error on the

output voltage. The first part of the error is from the

resistor ladder and the R_FSand R_ZSresistances. The

second part is due to the output buffer’s input offset

characteristics.

R₁+ 64*R_S+

R₂

30,000

30,180

- 180

R₁, R_AB, R₂

V_REF

V_FS

10,000

10,060

- 60

—

5.00 V

The R_FSand R_ZSresistances affect the voltage

between V_ZSand V_FS. The larger that R_FS+ R_ZSis, the

smaller that the step voltage (V_S) will be (from the

theoretical step voltage). The increase in the R_FSand

R_ZSresistances also effects the Full Scale Error (FSE),

Zero Scale Error (ZSE), and gain error.

3.3267 V

1.6700 V

3.3333 V

1.6667 V

- 6.6 mV

+ 3.3 mV

V_ZS

V_S

25.88 mV 26.04 mV - 0.16 mV

V_REF

V_FS

1.5V

1.0000 V

0.5000 V

—

0.9980 V

0.5010 V

- 2.0 mV

+ 1.0 mV

Table 7-2 compares theoretical resistor network volt-

ages for full scale and zero scale, where R_FS= R_ZS

V_ZS

=

V_S

7.766 mV 7.813 mV -0.047mV

0 , to an example where R_FSand R_ZSand non-zero.

The voltage calculations show cases of V_REF= 5.0V

and V_REF= 1.5V. Figure 2-34 shows R_VREF, R_FS, and

Note 1: R_VREF= R₁+ R_AB+ R₂,

R_AB= R_FS+ 64*R_S+ R_ZS

V_S= (V_FS- V_ZS) / 64

.

R_ZSresistances V_DD

.

So, as the voltage reference (V_REF) decreases, the

Step voltages (V_S) decrease. At a low V_REFvoltage, the

step voltage approaches the magnitude of the output

buffer’s input offset voltage (design target of ± 4.5 mV).

So, for low V_REFvoltages, the output buffer errors have

greater influence on the V_OUTvoltage.

Theoretical V_FS( V_REF

)

( R_FS 0 )

V_REF

V_OUT(FS)

V_FS-RL

Variations due to Output Buffer’s

Input Offset voltage and Buffer’s Impedance / Load

(Due to R_FS 0)

V_ZS-RL

(Due to R_ZS 0)

(V_FS- V_ZS

)

Step Voltage (V_S) =

When:

* V_REF

64

V_OUT(ZS)

V_SS

R

_FS= R_ZS= 0 .

V_S= V_REF/ 64

V_REF

2.7V

Theoretical V_ZS( V_SS

( R_ZS 0 )

)

5.0V

1.8V

1.5V

1.0V

V_S78.125mV 42.19mV 28.13mV 23.44mV 15.63mV

when R_FS= R_ZS= 0 .

FIGURE 7-6:

Output Voltage (V_OUT) Error.

 2012 Microchip Technology Inc.

DS25154A-page 45

MCP47A1

NOTES:

DS25154A-page 46

 2012 Microchip Technology Inc.

MCP47A1

8.1

DC Set Point or Calibration

8.0

APPLICATIONS EXAMPLES

A

common application for the devices is

a

The MCP47A1 family of devices are general purpose,

single-channel voltage output DACs for various

applications where a precision operation with low

power is needed.

digitally-controlled set point and/or calibration of

variable parameters, such as sensor offset or slope.

For example, the MCP47A1 provides 64 output steps

over the voltage reference range. If voltage reference is

1.65V, the LSb size is 1.65V / 64, or ~ 25.78 mV.

The MCP47A1 devices are rail-to-rail output DACs

designed to operate with a V_DDrange of 1.8V to 5.5V.

The internal output op amplifier is robust enough to

drive common, small-signal loads directly, thus

eliminating the cost and size of external buffers for

most applications.

Applications that need accurate detection of an input

threshold event often need several sources of error

eliminated. Use of comparators and operational

amplifiers (op amps) with low offset and gain error can

help achieve the desired accuracy, but in many

applications, the input source variation is beyond the

designer’s control. If the entire system can be

calibrated after assembly in a controlled environment

(like factory test), these sources of error are minimized,

if not entirely eliminated. Figure 8-1 illustrates this

example circuit. Equation 8-1 shows a quick estimation

Applications generally suited for the devices are:

• Set Point or Offset Trimming

• Sensor Calibration

• Portable Instrumentation (Battery Powered)

• Motor Control

Application examples include:

of the wiper value given the desired voltage trip (V_TRIP

point.

)

• DC Set Point or Calibration

• Decreasing Output Step Size

• Building a “Window” DAC

V_REFV_DD

MCP47A1

V_CC

+

• Selectable Gain and Offset Bipolar Voltage

Output

V_O

V_SENSE

Comp.

• Building Programmable Current Source

• Serial Interface Communication Times

• Software I2C Interface Reset Sequence

V_TRIP

C₁

V_OUT

V_CC

–

I²C™

In the design of a system with the MCP47A1 devices,

the following considerations should be taken into

account:

2-wire

FIGURE 8-1:

Calibration.

Set Point or Threshold

• Power Supply Considerations (Noise)

• PCB Area Requirements

EQUATION 8-1:

ESTIMATING THE WIPER

VALUE (N) FROM THE

DESIRED V_TRIP

• Connecting to I2C BUS using Pull-Up

Resistors

V_TRIP= V_OUT= (N * V_S)

( V_TRIP- V_REF

V_S

)

N =

Where: V_S= V_REF/ 64

Note: Calculation does not take into account R_FS

and R_ZSresistors of the DAC’s resistor ladder (see

Section 7.1 for additional information).

 2012 Microchip Technology Inc.

DS25154A-page 47

MCP47A1

8.1.1

DECREASING OUTPUT STEP SIZE

8.1.2

BUILDING A “WINDOW” DAC

Due to the step voltage and output range of the

MCP47A1, it may be desirable to reduce the step

voltage while also modifying the range of the output. A

common method to achieve this smaller step size is a

voltage divider on the DAC’s output. Figure 8-2

illustrates this concept. Equation 8-2 shows a quick

estimation of the wiper value given the desired voltage

trip (V_TRIP) point.

When calibrating a set point or threshold of a sensor,

typically only a small portion of the DAC output range is

utilized. If the LSb size is adequate enough to meet the

application’s accuracy needs, the unused range is

sacrificed without consequences. If greater accuracy is

needed, then the output range will need to be reduced

to increase the resolution around the desired threshold.

If the threshold is not near V_REF, 2 • V_REF, or V_SSthen

creating a “window” around the threshold has several

advantages. One simple method to create this

“window” is to use a voltage divider network with a

pull-up and pull-down resistor. Figure 8-3 and Figure 8-

4 illustrate this concept.

For example, if R₁= R₂, then the V_TRIPvoltage range

is from V_SSto 1/2 * V_REF. Also at the V_TRIPnode, the

step voltage is 1/2 the step voltage at the V_OUTnode.

A bypass capacitor on the output of the voltage divider

plays a critical function in attenuating the output noise

of the DAC and the induced noise from the

environment.

V_CC+

V_REFV_DD

R_SENSE

V_CC

+

V_REFV_DD

MCP47A1

V_CC+

V_O

V_SENSE

R₁

V_OUT

Comp.

R₃

R₂

V_O

R₁

MCP47A1

V_TRIP

Comp.

V_TRIP

C₁

R₂

V_CC

–

V_OUT

C₁

I²C™

V_CC–

2-wire

I²C™

2-wire

V_CC–

FIGURE 8-2:

Example Circuit Of Set Point

or Threshold Calibration.

FIGURE 8-3:

Single-Supply “Window”

DAC.

EQUATION 8-2:

V_OUTAND V_TRIP

ESTIMATIONS

EQUATION 8-3:

V

_OUTAND V_TRIP

ESTIMATIONS

V_OUT= N * V_S

V_S= V_REF/ 64

V_OUT= N * V_S

V_S= V_REF/ 64

R₂

R₁+ R₂

V_TRIP= V_OUT

*

V_OUT* R₂₃+ V₂₃* R₁

R₁+ R₂₃

V_TRIP

=

Note:

The V_OUTvoltage can also be scaled by a

resistor from the V_REFpin to the system

reference voltage. Care should be taken

with this implementation due to the ± 20%

variation to the 20k typical resistance

from the V_REFpin to ground (R_VREF). This

variation in resistance directly effects the

actual V_OUTvoltage.

R₂* R₃

R₂+ R₃

R₂₃

V₂₃

=

Thevenin

Equivalent

(V_CC+* R₂) * (V_CC-* R₃)

R₂+ R₃

R₁

V_OUT

V_TRIP

R₂₃

V₂₃

DS25154A-page 48

 2012 Microchip Technology Inc.

MCP47A1

EQUATION 8-4:

GAIN CALCULATION

8.2

Selectable Gain and Offset Bipolar

Voltage Output

R₂

Gain =

R₁

In some applications, control of the output range is

desirable. Figure 8-4 shows a circuit using a DAC

device to achieve a bipolar or single-supply application.

This circuit is typically used for linearizing a sensor

whose slope and offset varies. Depending on the out-

put range desired, resistor R₄or resistor R₅may not be

required. Equation 8-4 shows the calculation of the

Gain, while Equation 8-5 shows the calculation of the

V_Ovoltage.

If desired Gain = 0.5, and R₁is selected as 20 k

then R₂would need to be 10 k .

EQUATION 8-5:

BIPOLAR “WINDOW” DAC

CALCULATIONS

R₂

R₁

R₂

R₁

V_O= V_OA+• ( 1 +

) - V_IN• (

)

This circuit can be simplified if the window range is

limited (by removing either the R₄or R₅resistor).

Figure 8-5 shows a circuit for the case where the R₅

resistor is removed. Resistors R₁and R₂control the

gain, while resistors R₃and R₄shift the DAC's output

to a selected offset. Equation 8-6 shows the calculation

of the V_Ovoltage.

Offset Adjust

Gain Adjust

(V_OUT• R₄₅) + (V₄₅• R₃)

R₃+ R₄₅

V_OA+

=

(V_CC+• R₄) + (V_CC-• R₅)

R₄+ R₅

V₄₅

Note:

R4 can be tied to V_DD, instead of V_SS, if a

higher offset is desired.

R₄• R₅

R₄₅

=

R₄+ R₅

V_CC

+

(1)

V_OUT= N * V_S

V_REFV_DD

MCP47A1

V_CC

+

R₅

V_REF

R₃

V_OUT

V_OA+

C₁

V_S=

V_O

192

R₄

Note 1: V_OUTcalculation does not take into

account R_FSand R_ZSresistors of the DAC’s

resistor ladder (see Section 7.1 for additional

information).

V_CC–

I²C™

2-wire

V

–

CC

R₂

V_IN

R₁

Note: Capacitor C₁is recommended (0.1uF typical)

EQUATION 8-6:

SIMPLIFIED BIPOLAR

“WINDOW” DAC

CALCULATIONS

FIGURE 8-4:

Selectable Gain and Offset Circuit.

Bipolar Voltage Source with

R₂

R₁

R₂

R₁

V_O= V_OA+• ( 1 +

) - V_IN• (

)

V_REFV_DD

R₄

V_OA+= V_OUT• (

)

V_CC

+

R₃+ R₄

R₃

V_OA+

V_O

MCP47A1

V_OUT= N * V_S

V_OUT

C₁

R₄

Note 1: V_OUTcalculation does not take into

account R_FSand R_ZSresistors of the DAC’s

resistor ladder (see Section 7.1 for additional

information).

V_CC

–

I²C™

2-wire

R₂

V_IN

R₁

Note: Capacitor C₁is recommended (0.1uF typical)

FIGURE 8-5: Simplified Bipolar Voltage

Source with Selectable Gain and Offset Circuit.

 2012 Microchip Technology Inc.

DS25154A-page 49

MCP47A1

8.3

Building Programmable Current

Source

8.4

Serial Interface Communication

Times

Figure 8-6 shows an example of building

a

Table 8-1 shows time for each I²C serial interface

command as well as the effective data update rate that

can be supported by the digital interface (based on the

two I²C serial interface frequencies). The continuous

write command allows a higher data update frequency

since for the fixed overhead more bytes are

transferred. The Serial Interface performance, along

with the V_OUToutput performance (such as slew rate),

would be used to determine the application’s volatile

DAC register update rate.

programmable current source using a voltage follower.

The current sensor resistor is used to convert the DAC

voltage output into a digitally-selectable current source.

The smaller R_SENSEis, the less power is dissipated

across it. However, this also reduces the resolution that

the current can be controlled.

V_DD

(or V_REF

)

V_REFV_DD

MCP47A1

Load

V_CC

+

V_OUT

I_L

I_b

I²C™

V_CC–

2-wire

I_L

R_SENSE

I_b= ----



V_OUT



I_L= --------------  ------------

R_sense + 1

where Common-Emitter Current Gain

FIGURE 8-6:

Digitally-Controlled Current

Source.

TABLE 8-1:

SERIAL INTERFACE TIMES / FREQUENCIES

Example

Command

Time (µs)

Effective Data Update

Frequency (kHz) ⁽²⁾

# of Serial

# Bytes

# of Serial

Interface bits⁽¹⁾Transferred Interface bits 100kHz 400kHz

100kHz

3.4

400kHz

13.8

Command

Write Single Byte

Write Continuous Bytes

Read Byte

29

20 + N * 9

39

1

5

1

29

65

39

290.0

650.0

390.0

72.5

162.5

97.5

7.7

30.8

2.6

10.3

Note 1: Includes the Start or Stop bits.

2: This is the command frequency multiplied by the number of bytes transferred.

DS25154A-page 50

 2012 Microchip Technology Inc.

MCP47A1

2

The nine bits of ‘1’ are used to force a Reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP47A1 is driving an Abit on

the I²C bus, or is in output mode (from a Read

command) and is driving a data bit of ‘0’ onto the I²C

bus. In both of these cases, the previous Start bit could

not be generated due to the MCP47A1 holding the bus

low. By sending out nine ‘1’ bits, it is ensured that the

device will see an A bit (the Master Device does not

drive the I²C bus low to acknowledge the data sent by

the MCP47A1), which also forces the MCP47A1 to

reset.

8.5

Software I C Interface Reset

Sequence

Note:

This technique should be supported by

any I²C compliant device. The 24XXXX

I²C Serial EEPROM devices support this

technique, which is documented in

AN1028.

At times, it may become necessary to perform a

Software Reset Sequence to ensure the MCP47A1

device is in a correct and known I²C Interface state.

This technique only resets the I²C state machine.

The 2nd Start bit is sent to address the rare possibility

of an erroneous write. This could occur if the Master

Device was reset while sending a Write command to

the MCP47A1, AND then as the Master Device returns

to normal operation and issues a Start condition, while

the MCP47A1 is issuing an Acknowledge. In this case,

if the 2nd Start bit is not sent (and the Stop bit was sent)

the MCP47A1 could initiate a write cycle.

This is useful if the MCP47A1 device powers up in an

incorrect state (due to excessive bus noise, etc), or if

the Master Device is reset during communication.

Figure 8-7 shows the communication sequence to

software reset the device.

S

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’

S

P

Nine bits of ‘1’

Start bit

Note:

The potential for this erroneous write

ONLY occurs if the Master Device is reset

while sending a Write command to the

MCP47A1.

Start

bit

Stop bit

FIGURE 8-7:

Format.

Software Reset Sequence

The Stop bit terminates the current I²C bus activity. The

MCP47A1 waits to detect the next Start condition.

The 1st Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

Master Device. In this mode, the device is monitoring

the data bus in Receive mode and can detect if the

Start bit forces an internal Reset.

This sequence does not effect any other I²C devices

which may be on the bus, as they should disregard this

as an invalid command.

 2012 Microchip Technology Inc.

DS25154A-page 51

MCP47A1

8.6

Design Considerations

V_DD

8.6.1

POWER SUPPLY

CONSIDERATIONS (NOISE)

0.1 µF

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP47A1’s performance.

Careful board layout minimizes these effects and

increases the Signal-to-Noise Ratio (SNR). Multi-layer

SCL

SDA

V_REF

V_OUT

boards utilizing

a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are suggested. Particularly harsh environments may

require shielding of critical signals.

The device’s power sources (V_DDand V_REF) should be

as clean as possible. Any noise induced on the V_DD

and V_REFsignals can affect the DAC performance.

Separate digital and analog ground planes are

recommended.

V_SS

FIGURE 8-8:

Connections.

Typical Microcontroller

Typical applications require a bypass capacitor in order

to filter high-frequency noise on the V_DDand V_REFsig-

nals. The noise can be induced onto the power supply’s

traces or as a result of changes on the DAC output. The

bypass capacitor helps to minimize the effect of these

noise sources on signal integrity. Figure 8-8 illustrates

an appropriate bypass strategy.

Optional

V

REF

Analog

Optional

C3

C4 C5

Output

V

C1 C2

V_DD

6 V_REF

1

2

5

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close to the device power pin (V_DD) as possible (within

4 mm).

DD

V_SS

V_OUT

SDA

4

R1

R2

SCL 3

To MCU

Separate digital and analog ground planes are

recommended. In this case, the V_SSpin and the ground

pins of the V_DDcapacitors should be terminated to the

analog ground plane and V_DDand V_SSshould reside

on the analog plane.

2

R1 and R2 are I C pull-up resistors:

R1 and R2:

5 k - 10 k for f

=

100 kHz to 400 kHz

Ceramic

SCL

Figure 8-9 shows an example of using two bypass

capacitors (a 10 µF tantalum capacitor and a 0.1 µF

ceramic capacitor) in parallel on the V_DDline. These

capacitors should be placed as close to the V_DDpin as

possible (within 4 mm). If the application circuit has

separate digital and analog power supplies, the V_DD

and V_SSpins of the device should reside on the analog

plane.

C1: 0.1 µF capacitor

C2: 10 µF capacitor

C3: ~ 0.1 µF

Tantalum

Optional to reduce noise

in V pin.

OUT

C4: 0.1 µF capacitor

C5: 10 µF capacitor

Ceramic

Tantalum

FIGURE 8-9:

Example MCP47A1 Circuit.

Note:

Breadboards and wire-wrapped boards

are not recommended.

DS25154A-page 52

 2012 Microchip Technology Inc.

MCP47A1

8.6.2

PCB AREA REQUIREMENTS

8.6.4

CONNECTING TO I²C BUS USING

PULL-UP RESISTORS

In some applications, PCB area is a criteria for device

selection. Table 8-2 shows the typical package

dimensions and area for the different package options.

The SCL and SDA pins of the MCP47A1 devices are

open-drain configurations. These pins require a pull-up

resistor as shown in Figure 8-9.

TABLE 8-2:

Package

PACKAGE FOOTPRINT ⁽¹⁾

Package Footprint

The pull-up resistor values (R1 and R2) for SCL and

SDA pins depend on the operating speed (standard,

fast, and high speed) and loading capacitance of the

I²C bus line. A higher value of the pull-up resistor

consumes less power, but increases the signal

transition time (higher RC time constant) on the bus

line. Therefore, it can limit the bus operating speed.

The lower resistor value, on the other hand, consumes

higher power, but allows higher operating speed. If the

bus line has higher capacitance due to long metal

traces or multiple device connections to the bus line, a

smaller pull-up resistor is needed to compensate the

long RC time constant. The pull-up resistor is typically

chosen between 1 kand 10 kranges for standard

and fast modes.

Dimensions (mm)

Type

Code

Length

Width

6

SC70

LT

3.10

3.20

9.92

Note 1: Does not include recommended Land

Pattern dimensions. Dimensions are Max

values.

8.6.3

PINOUT/FOOTPRINT

COMPATIBILITY

The MCP47A1 has a pinout and footprint compatibility

to the MCP40D18 and MCP4018 devices.

8.6.4.1

Device Connection Test

The user can test the presence of the device on the I²C

bus line using a simple I²C command. This test can be

achieved by checking an acknowledge response from

the device after sending a read or write command.

Figure 8-10 shows an example with a read command.

The steps are:

The MCP40D18/MCP4018’s W pin is analogous to the

MCP47A1’s V_OUTpin, while the MCP40D18/

MCP4018’s A pin is analogous to the MCP47A1’s V_REF

pin. The MCP40D18 and MCP47A1 share the same

I²C command protocol structure.

a) Set the R/W bit “High” in the device’s address

byte.

b) Check the ACK bit of the address byte.

If the device acknowledges (ACK = 0) the

command, then the device is connected,

otherwise it is not connected.

c) Send Stop bit.

Address Byte

SCL

SDA

1

2

1

3

0

4

1

5

6

7

8

1

9

A2 A1 A0

Start

Bit

Stop

Bit

Address bits

Device Code

R/W

Device

Response

FIGURE 8-10:

I²C Bus Connection Test.

 2012 Microchip Technology Inc.

DS25154A-page 53

MCP47A1

NOTES:

DS25154A-page 54

 2012 Microchip Technology Inc.

MCP47A1

9.0

9.1

DEVELOPMENT SUPPORT

Note:

Since the SC70EV is a generic board, the

noise immunity of the board will not be

optimal. If noise immunity is a require-

ment, then a you will need to develop a

custom PCB for the MCP47A1. This PCB

would need to use good layout techniques

to reduce noise coupling.

Evaluation/Demonstration Boards

The MCP47A1 devices do not have a dedicated

evaluation or demonstration board. Figure 9-1 shows

the component connections to make an evaluation

board using the SC70EV Bond Out PCB (order #

SC70EV). This will allow the MCP47A1’s capabilities to

be evaluated with the PICkit™ Serial Analyzer (order #

DV164122).

0 

1.0 µF

0.1 µF

(1)

VDD

V

REF

VSS

V

OUT

0 

C_L& R_L

4.7 k

SCL

SDA

Required components

Recommended components for noise filtering

Optional I²C bus pull up resistors (value may need to be adjusted for your system)

Optional VOUT loading components (stacked), C_L= 1 nF max and R_L= 5 k max

Note 1: The V_REFpin (P8) will need to be connected to a reference voltage source (such as V_DD).

FIGURE 9-1:

SC70EV Bond Out PCB – Top Layer and Silk-Screen.

 2012 Microchip Technology Inc.

DS25154A-page 55

MCP47A1

9.2

Technical Documentation

Several additional technical documents are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs, and Design Guides. Table 9-1 shows

some of these documents.

TABLE 9-1:

TECHNICAL DOCUMENTATION

Title

Application

Literature #

Note Number

AN1326

Using DAC for LDMOS Amplifier Bias Control Applications

Signal Chain Design Guide

DS01326

DS21825

DS01005

—

Analog Solutions for Automotive Applications Design Guide

DS25154A-page 56

 2012 Microchip Technology Inc.

MCP47A1

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

6-Lead SC-70

Example

BANN

Part Number

Code

Part Number

Code

MCP47A1T-A0E/LT

BANN

MCP47A1T-A1E/LT

BCNN

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2012 Microchip Technology Inc.

DS25154A-page 57

MCP47A1

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS25154A-page 58

 2012 Microchip Technology Inc.

MCP47A1

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2012 Microchip Technology Inc.

DS25154A-page 59

MCP47A1

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS25154A-page 60

 2012 Microchip Technology Inc.

MCP47A1

APPENDIX A: REVISION HISTORY

Revision A (August 2012)

• Original Release of this Document.

 2012 Microchip Technology Inc.

DS25154A-page 61

MCP47A1

B.4

Full-Scale Error (FSE)

APPENDIX B: TERMINOLOGY

The Full-Scale Error (FSE) is the difference between

the ideal and measured DAC output voltage with the

Wiper’s position set to its maximum (Wiper code =

40h); see Figure B-3. Full-scale error may also be

thought of as the sum of the offset error plus gain error.

B.1

Resolution

The resolution is the number of DAC output states that

divide the full-scale range. For the 6-bit DAC, the

resolution is 2⁶, meaning the DAC code ranges from 0

to 64.

See Figure 2-9 through Figure 2-12 for FSE

characterization graphs.

B.2

Least Significant Bit (LSb)

EQUATION B-2:

FULL SCALE ERROR

Normally, this is thought of as the ideal voltage

difference between two successive codes. This bit has

the smallest value or weight of all bits in the register.

V

- V

OUT(@FS)

IDEAL(@FS)

FSE =

V

LSb

For a given output voltage range, which is typically the

voltage between the Full-Scale voltage and the Zero-

Scale voltage (V_OUT(FS)- V_OUT(ZS)), it is divided by the

resolution of the device (Equation B-1).

Where:

FSE is expressed in LSb

V

is the V

register code is at Full-scale.

voltage when the DAC

OUT

OUT(@FS)

is the ideal output voltage when the

DAC register code is at Full-scale.

IDEAL(@FS)

EQUATION B-1:

LSb VOLTAGE

CALCULATION

is the delta voltage of one DAC register code

step (such as code 20h to code 21h).

LSb

V_OUT(FS)- V_OUT(ZS)

2^N

V_LSb

=

B.5

Zero-Scale Error (ZSE)

2^N= 64 (MCP47A1)

The Zero-Scale Error (ZSE) is the difference between

the ideal and measured V_OUTvoltage with the Wiper

position set to its minimum (Wiper code = 00h); see

Figure B-3. The Zero-Scale Error is the same as the

Offset Error for this case (Wiper code = 00h).

Equation B-3 shows how to calculate the zero scale

error.

B.3

Monotonic Operation

Monotonic operation means that the device’s output

voltage (V_OUT) increases with every one code step

(LSb) change (from terminal B to terminal A). The V_OUT

voltage (V_Wvoltage) is the sum of all the Step voltages

plus the voltage at Zero-Scale (V_ZS). The Zero-Scale

voltage is dependent on the resistance between the tap

0 point and the B Terminal.

See Figure 2-13 through Figure 2-16 for ZSE

characterization graphs.

EQUATION B-3:

ZERO SCALE ERROR

V

OUT(@ZS)

V_S64

ZSE =

0x40

0x3F

V

LSb

V_S63

Where:

FSE is expressed in LSb

V

is the V

register code is at Zero-scale.

voltage when the DAC

OUT

OUT(@ZS)

0x3E

V

is the delta voltage of one DAC register code

step (such as code 20h to code 21h).

LSb

V_S3

0x03

V_S1

0x02

V_S0

0x01

0x00

V_W

n = ?

(@ tap)

V_W

=

V_Sn+ V_{ZS(@ Tap 0)}

n = 0

Voltage (V_W~= V_OUT

)

FIGURE B-1:

V_W(V_OUT).

DS25154A-page 62

 2012 Microchip Technology Inc.

MCP47A1

B.6

Total Unadjusted Error

B.9

Gain Error

The Total Unadjusted Error is the difference between

the ideal and measured V_OUTvoltage. Typically,

calibration of the output voltage is implemented to

improve system performance.

The Gain error (see Figure B-3) is the difference

between the actual full-scale output voltage, from the

ideal output voltage of the DAC transfer curve. The

gain error is calculated after nullifying the offset error,

or full scale error minus the offset error.

Total Unadjusted Error can be calculated, see

Equation B-4.

The gain error indicates how well the slope of the actual

transfer function matches the slope of the ideal transfer

function. The gain error is usually expressed as percent

of full-scale range (% of FSR) or in LSb. The gain error

is not calibrated at the factory and most of the gain error

is contributed by the output buffer (op amp) saturation.

EQUATION B-4:

TOTAL UNADJUSTED

ERROR (LSb)

V

REF

V

=

* DAC Code

IDEAL

64

REF

Actual Transfer Function

V

LSb

64

Full-Scale

Error

V

- V

MEASURED

IDEAL

Error

=

LSb

V

LSb

Where:

Gain Error

V

is the voltage on the V

pin.

REF

Analog

Output

V

is the V

voltage for the same DAC

OUT

MEASURED

register code as V

is calculated.

IDEAL

Actual Transfer Function

See Figure 2-17 through Figure 2-20 for Total

Unadjusted Error characterization graphs.

after Offset Error is removed

Ideal Transfer Function

Zero-Scale

Error

B.7

Offset Error

0

DAC Input Code

The Offset error (see Figure B-2) is the deviation from

zero voltage output when the volatile DAC Register

value = 00h (zero scale voltage). This error affects all

codes by the same amount. The offset error can be

calibrated by software in application circuits.

FIGURE B-3:

SCALE ERROR EXAMPLE.

GAIN ERROR AND FULL-

B.10 Gain Error Drift

The Gain error drift is the variation in gain error due to

a change in ambient temperature. The gain error drift is

typically expressed in ppm/^oC.

Actual Transfer Function

Analog

Output

Ideal Transfer Function

DAC Input Code

Offset

Error

(ZSE)

0

FIGURE B-2:

OFFSET ERROR.

B.8 Offset Error Drift

The Offset error drift is the variation in offset error due

to a change in ambient temperature. The offset error

drift is typically expressed in ppm/^oC.

 2012 Microchip Technology Inc.

DS25154A-page 63

MCP47A1

B.11 Integral Nonlinearity (INL)

B.12 Differential Nonlinearity (DNL)

The Integral Nonlinearity (INL) error is the maximum

deviation of an actual transfer function from an ideal

transfer function (straight line).

The Differential Nonlinearity (DNL) error (see Figure B-

5) is the measure of step size between codes in actual

transfer function. The ideal step size between codes is

1 LSb. A DNL error of zero would imply that every code

is exactly 1 LSb wide. If the DNL error is less than

1 LSb, the DAC guarantees monotonic output and no

missing codes. The DNL error between any two

adjacent codes is calculated as follows:

In the MCP47A1, INL is calculated using two end

points. The points used are Zero-Scale (00h) and Full-

Scale - 1 (3Fh). INL can be expressed as a percentage

of full scale range (FSR) or in a fraction of an LSb. INL

is also called relative accuracy. Equation B-5 shows

how to calculate the INL error in LSb and Figure B-4

shows an example of INL accuracy.

DNL error is the measure of variations in code widths

from the ideal code width. A DNL error of zero would

imply that every code is exactly 1 LSb wide.

INL error for these devices is the maximum deviation

between an actual code transition point and its

corresponding ideal transition point after offset and

gain errors have been removed. These endpoints are

from 0x00 to 0x40 for the MCP47A1. Refer to Figure B-

4.

See Figure 2-5 through Figure 2-8 for DNL character-

ization graphs.

EQUATION B-6:

DNL ERROR

V

- ( V

- V

)

S

(Code = n)

(Code = n-1)

Positive INL means higher V_OUTvoltage than ideal.

Negative INL means lower V_OUTvoltage than ideal.

DNL

=

LSb

V

S

V

- V

ZS

See Figure 2-1 through Figure 2-4 for INL character-

ization graphs.

(Code=63)

V

=

S

63

EQUATION B-5:

INL ERROR

V

- V

IDEAL

OUT

INL

=

LSb

V

S

111

V

= V + ( V * DAC Code )

IDEAL

ZS

S

110

101

100

011

010

001

000

Actual

transfer

function

V

- V

ZS

(Code=63)

V

=

S

63

Wiper

Code

Ideal transfer

function

INL < 0

Wide code, > 1 LSb

111

Actual

transfer

function

110

101

100

Narrow code < 1 LSb

V_OUTOutput Voltage

Wiper

Code

FIGURE B-5:

DNL ACCURACY.

011

010

001

000

Ideal transfer

function

INL < 0

_OUTOutput Voltage

INL ACCURACY.

V

FIGURE B-4:

DS25154A-page 64

 2012 Microchip Technology Inc.

MCP47A1

B.13 Settling Time

B.16 Power-Supply Rejection Ratio

(PSRR)

The Settling time is the time delay required for the V_OUT

voltage to settle into its new output value. This time is

measured from the start of code transition, to when the

PSRR indicates how the output of the DAC is affected

by changes in the supply voltage. PSRR is the ratio of

the change in V_OUTto a change in V_DDfor full-scale

output of the DAC. The V_OUTis measured while the

V_OUTvoltage is within the specified accuracy.

In the MCP47A1, the settling time is a measure of the

time delay until the V_OUTvoltage reaches within 0.5

LSb of its final value, when the volatile DAC Register

changes from 40h to 50h.

V_DDis varied +/- 10%, and expressed in dB or µV/V.

B.17 Ratiometric Temperature

Coefficient

See Figure 2-36 through Figure 2-39 for Settling Time

oscilloscope screen captures.

The ratiometric temperature coefficient quantifies the

error in the ratio of the resistor setting (Resistance from

VREF pin to Wiper position (R_VREF-W) and the Wiper

position to Ground (R_W-VSS) due to temperature drift.

This error also includes the drift of the output driver

over temperature. This is typically the critical error

when using a DAC.

B.14 Major-Code Transition Glitch

Major-code transition glitch is the impulse energy

injected into the DAC analog output when the code in

the DAC register changes state. It is normally specified

as the area of the glitch in nV-Sec, and is measured

when the digital code is changed by 1 LSb at the major

carry transition (Example: Wiper code changes from

“011111” to “100000”, or from “100000” to

“011111”).

See Figure 2-21 through Figure 2-24 for Tempco

characterization graphs.

B.18 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies the

error in the end-to-end output voltage (Nominal output

voltage V_OUT) due to temperature drift. For a DAC, this

error is typically not an issue, due to the ratiometric

aspect of the output.

B.15 Digital Feedthrough

The Digital feedthrough is the glitch that appears at the

analog output caused by coupling from the digital input

pins of the device. The area of the glitch is expressed

in nV-Sec, and is measured with a full scale change

(Example: all 0s to all 1s and vice versa) on the digital

input pins. The digital feedthrough is measured when

the DAC is not being written to the output register.

 2012 Microchip Technology Inc.

DS25154A-page 65

MCP47A1

NOTES:

DS25154A-page 66

 2012 Microchip Technology Inc.

MCP47A1

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

XXX

X

/XX

a) MCP47A1T-A0E/LT:

6-bit DAC,

SC70-6,

2

I C Slave Temperature Package

Address Range

Address = 5Ch,

Tape and Reel

6-bit DAC,

2

b) MCP47A1T-A1E/LT:

Device:

MCP47A1T: 6-bit Single DAC with I C interface

(Tape and Reel)

SC70-6,

Address = 7Ch,

Tape and Reel

2

I C Slave Address A0 = 5Ch

A1 = 7Ch

Temperature

Range:

E

= -40°C to +125°C

Package:

LT = Plastic Small Outline Transistor

(SC70), 6-lead

 2012 Microchip Technology Inc.

DS25154A-page 67

MCP47A1

NOTES:

DS25154A-page 68

 2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-62076-491-6

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2012 Microchip Technology Inc.

DS25154A-page 69

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11/29/11

DS25154A-page 70

 2012 Microchip Technology Inc.


型号：	MCP47A1
厂家：	MICROCHIP
描述：	6-Bit Volatile DAC with Command Code
文件：	总70页 (文件大小：1836K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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