MCP6024T-E/SLVAO [MICROCHIP]
Operational Amplifier, 4 Func, 2500uV Offset-Max, CMOS, PDSO14;
| 型号： | MCP6024T-E/SLVAO |
| 厂家： | 
MICROCHIP |
| 描述： | Operational Amplifier, 4 Func, 2500uV Offset-Max, CMOS, PDSO14 光电二极管 |
| 文件： | 总54页 (文件大小：1416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6021/1R/2/3/4
Rail-to-Rail Input/Output, 10 MHz Op Amps
Description
Features
• Rail-to-Rail Input/Output
The MCP6021, MCP6021R, MCP6022, MCP6023 and
MCP6024 from Microchip Technology Inc. are rail-to-
rail input and output operational amplifiers with high
performance. Key specifications include: wide band-
width (10 MHz), low noise (8.7 nV/Hz), low input offset
voltage and low distortion (0.00053% THD+N). The
MCP6023 also offers a Chip Select pin (CS) that gives
power savings when the part is not in use.
• Wide Bandwidth: 10 MHz (typical)
• Low Noise: 8.7 nV/Hz at 10 kHz (typical)
• Low Offset Voltage:
- Industrial Temperature: ±500 µV (max.)
- Extended Temperature: ±250 µV (max.)
• Mid-Supply V
: MCP6021 and MCP6023
REF
• Low Supply Current: 1 mA (typical)
• Total Harmonic Distortion:
- 0.00053% (typical, G = 1 V/V)
• Unity Gain Stable
The single MCP6021 and MCP6021R are available in
SOT-23-5 packages. The single MCP6021, single
MCP6023 and dual MCP6022 are available in 8-lead
PDIP, SOIC and TSSOP packages. The Extended
Temperature single MCP6021 is available in 8-lead
MSOP. The quad MCP6024 is offered in 14-lead PDIP,
SOIC and TSSOP packages.
• Power Supply Range: 2.5V to 5.5V
• Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
The MCP6021/1R/2/3/4 family is available in Industrial
and Extended temperature ranges. It has a power
supply range of 2.5V to 5.5V.
Applications
Package Types
• Automotive
MCP6021
SOT-23-5
MCP6022
PDIP, SOIC, TSSOP
• Multi-Pole Active Filters
• Audio Processing
• DAC Buffer
VDD VOUTA
VDD
VOUT
VSS
5
4
1
2
3
4
8
7
6
5
1
• Test Equipment
• Medical Instrumentation
VINA
-
VOUTB
2
3
VINA+
VIN-
VINB
-
VIN+
VSS
VINB
+
MCP6021R
SOT-23-5
Design Aids
MCP6023
PDIP, SOIC, TSSOP
• SPICE Macro Models
VSS
VIN-
VOUT
VDD
®
5
1
2
3
• FilterLab Software
®
NC
VIN-
VIN+
VSS
1
2
3
4
8 CS
• MPLAB Mindi™ Analog Simulator
VDD
7
6
5
VIN+
4
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
VOUT
VREF
MCP6021
PDIP, SOIC,
MSOP, TSSOP
MCP6024
PDIP, SOIC, TSSOP
Typical Application
NC
NC
VIN-
VIN+
VSS
8
7
6
5
1
2
3
4
5.6 pF
Photo
Detector
VOUTA
V
V
V
V
V
1
2
3
4
5
6
7
14
13
12
11
10
9
OUTD
VDD
VINA
-
-
100 k
IND
VOUT
VREF
VINA
VDD
VINB
VINB
+
+
IND
100 pF
SS
MCP6021
+
+
INC
VDD/2
-
VINC
-
Transimpedance Amplifier
VOUTB
VOUTC
8
2001-2017 Microchip Technology Inc.
DS20001685E-page 1
MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 2
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
V
– V ........................................................................7.0V
SS
DD
Current Analog Input Pins (V +, V -)..........................±2 mA
IN
IN
†† See Section 4.1.2, Input Voltage Limits.
Analog Inputs (V +, V -) ††......... V – 1.0V to V + 1.0V
IN
IN
SS
DD
All Other Inputs and Outputs.......... V – 0.3V to V + 0.3V
SS
DD
Difference Input Voltage ...................................... |V – V
|
SS
DD
Output Short-Circuit Current ................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature.................................+150°C
ESD Protection on All Pins (HBM; MM) 2 kV; 200V
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
V /2
A
DD
SS
CM
DD
OUT DD
and R = 10 kto V /2.
L
DD
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset
Input Offset Voltage:
Industrial Temperature Parts
Extended Temperature Parts
Extended Temperature Parts
V
V
V
-500
-250
-2.5
—
—
—
+500
+250
+2.5
µV
µV
V
V
V
= 0V
OS
OS
OS
CM
CM
CM
= 0V, V = 5.0V
DD
mV
= 0V, V = 5.0V,
DD
T = -40°C to +125°C
A
Input Offset Voltage Temperature Drift V /T
—
±3.5
90
—
—
µV/°C T = -40°C to +125°C
A
OS
A
Power Supply Rejection Ratio
Input Current and Impedance
Input Bias Current:
PSRR
74
dB
V
= 0V
CM
I
I
I
—
—
—
—
—
—
1
—
150
5,000
—
pA
pA
B
B
B
Industrial Temperature Parts
Extended Temperature Parts
Input Offset Current
30
T = +85°C
A
640
±1
pA
T = +125°C
A
I
pA
OS
13
Common-Mode Input Impedance
Differential Input Impedance
Common-Mode
Z
10 ||6
—
||pF
||pF
CM
13
Z
10 ||3
—
DIFF
Common-Mode Input Range
Common-Mode Rejection Ratio
V
V
– 0.3
—
90
85
90
V
+ 0.3
V
CMR
SS
DD
CMRR
CMRR
CMRR
74
70
74
—
dB
dB
dB
V
V
V
= 5V, V
= 5V, V
= 5V, V
= -0.3V to 5.3V
DD
DD
DD
CM
CM
CM
—
—
= 3.0V to 5.3V
= -0.3V to 3.0V
Voltage Reference (MCP6021 and MCP6023 only)
V
V
Accuracy (V
– V /2)
V
REF_ACC
-50
—
—
+50
—
mV
REF
REF
REF
DD
Temperature Drift
V
/T
±100
µV/°C T = -40°C to +125°C
A
REF
A
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
A
90
110
—
dB
V
V
= 0V,
CM
OL
= V + 0.3V to V – 0.3V
OUT
SS
DD
Output
Maximum Output Voltage Swing
Output Short Circuit Current
V
, V
V
+ 15
—
V – 20
DD
mV
mA
mA
0.5V input overdrive
OL
OH
SS
I
I
—
—
±30
±22
—
—
V
V
= 2.5V
= 5.5V
SC
SC
DD
DD
Power Supply
Supply Voltage
V
2.5
0.5
—
5.5
V
DD
Quiescent Current per Amplifier
I
1.0
1.35
mA
I = 0
O
Q
2001-2017 Microchip Technology Inc.
DS20001685E-page 3
MCP6021/1R/2/3/4
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
V /2,
OUT DD
A
DD
SS
CM
DD
R
= 10 kto V /2 and C = 60 pF.
DD L
L
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
—
10
65
—
—
—
—
MHz
°
G = +1 V/V
Settling Time, 0.2%
Slew Rate
t
250
7.0
ns
G = +1 V/V, V
= 100 mV
OUT p-p
SETTLE
SR
V/µs
Total Harmonic Distortion Plus Noise
f = 1 kHz, G = +1 V/V
THD + N
—
—
0.00053
0.00064
—
—
%
%
V
= 0.25V to 3.25V (1.75V ± 1.50V ),
OUT PK
V
= 5.0V, BW = 22 kHz
DD
f = 1 kHz, G = +1 V/V, R = 600 THD + N
V
V
= 0.25V to 3.25V (1.75V ± 1.50V ),
L
OUT
PK
= 5.0V, BW = 22 kHz
DD
f = 1 kHz, G = +1 V/V
f = 1 kHz, G = +10 V/V
f = 1 kHz, G = +100 V/V
Noise
THD + N
THD + N
THD + N
—
—
—
0.0014
0.0009
0.005
—
—
—
%
%
%
V
V
V
= 4V , V = 5.0V, BW = 22 kHz
P-P DD
OUT
OUT
OUT
= 4V , V = 5.0V, BW = 22 kHz
P-P DD
= 4V , V = 5.0V, BW = 22 kHz
P-P DD
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
E
e
—
—
—
2.9
8.7
3
—
—
—
µVp-p f = 0.1 Hz to 10 Hz
nV/Hz f = 10 kHz
ni
ni
i
fA/Hz f = 1 kHz
ni
MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2,
DD
A
DD
SS
CM
V
V /2, R = 10 kto V /2 and C = 60 pF.
OUT
DD
L
DD
L
Parameters
Sym.
Min.
Typ.
Max. Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
CS Input Current, Low
CS High Specifications
CS Logic Threshold, High
CS Input Current, High
GND Current
V
V
—
0.2 V
—
V
IL
SS
DD
I
-1.0
0.01
µA CS = V
CSL
SS
V
0.8 V
—
—
V
DD
V
IH
DD
I
0.01
-0.05
0.01
2.0
—
µA CS = V
µA CS = V
µA CS = V
CSH
DD
DD
DD
I
-2
SS
O(LEAK)
Amplifier Output Leakage
CS Dynamic Specifications
I
—
—
CS Low to Amplifier Output Turn-on Time
CS High to Amplifier Output High-Z Time
Hysteresis
t
—
—
—
2
10
—
—
µs
µs
V
G = +1, V = V
,
SS
ON
IN
CS = 0.2 V to V
= 0.45 V time
DD
DD
OUT
t
0.01
0.6
G = +1, V = V
,
SS
OFF
IN
CS = 0.8 V to V
= 0.05 V time
DD
DD
OUT
V
V
= 5.0V, internal switch
HYST
DD
DS20001685E-page 4
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, V = +2.5V to +5.5V and V = GND.
DD
SS
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Industrial Temperature Range
Extended Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-TSSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
T
-40
-40
-40
-65
—
—
—
—
+85
°C
°C
°C
°C
A
T
+125
+125
+150
A
T
(Note 1)
A
T
A
—
—
—
—
—
—
—
—
256
85
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JA
JA
JA
JA
JA
163
206
124
70
120
100
Note 1: The industrial temperature devices operate over this Extended temperature range, but with reduced performance. In any
case, the internal Junction Temperature (T ) must not exceed the absolute maximum specification of +150°C.
J
1.1
Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.7 “Supply Bypass”.
CS
t
t
ON
OFF
Amplifier On
High-Z
High-Z
V
OUT
VDD
1 µF
-1 mA
0.1 µF
RN
VIN
-50 nA
I
(typical)
-50 nA
SS
(typical)
(typical)
CB1 CB2
VOUT
1 k:
I
MCP6021
CS
10 nA
(typical)
10 nA
(typical)
10 nA
(typical)
CL
60 pF
RL
10 k:
RG
RF
VDD/2
VL
FIGURE 1-1:
Pin on the MCP6023.
Timing Diagram for the CS
2 k:
2 k:
FIGURE 1-2:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
V
DD
1 µF
0.1 µF
R
/2
N
V
DD
C
C
B1 B2
V
OUT
1 k:
MCP6021
C
60 pF
R
L
L
10 k:
R
R
F
V
G
IN
V
L
2 k:
2 k:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
FIGURE 1-3:
2001-2017 Microchip Technology Inc.
DS20001685E-page 5
MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 6
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
V /2,
A
DD
SS
CM
DD
OUT DD
R = 10 k to V /2 and C = 60 pF.
L
DD
L
16%
14%
12%
10%
8%
24%
22%
20%
18%
16%
14%
12%
10%
8%
1192 Samples
VCM = 0V
I-Temp
Parts
1192 Samples
VCM = 0V
TA = -40°C to +85°C
I-Temp
Parts
TA = +25°C
6%
4%
6%
4%
2%
2%
0%
0%
Input Offset Voltage Drift (µV/°C)
Input Offset Voltage (µV)
FIGURE 2-1:
Input Offset Voltage
FIGURE 2-4:
Input Offset Voltage Drift
(Industrial Temperature Parts).
(Industrial Temperature Parts).
24%
22%
24%
438 Samples
VCM = 0V
E-Temp
22%
438 Samples
VDD = 5.0V
VCM = 0V
E-Temp
20%
Parts
Parts
20%
TA = -40°C to +125°C
18%
16%
14%
12%
10%
8%
18%
16%
14%
12%
10%
8%
TA = +25°C
6%
6%
4%
4%
2%
2%
0%
0%
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Input Offset Voltage
FIGURE 2-5:
Input Offset Voltage Drift
(Extended Temperature Parts).
(Extended Temperature Parts).
500
500
400
300
200
100
0
-40°C
VDD = 2.5V
400
300
200
100
0
-100
-200
-300
-400
-500
VDD = 5.5V
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-100
-200
-300
-400
-500
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs.
Common-Mode Input Voltage with VDD = 2.5V.
Common-Mode Input Voltage with VDD = 5.5V.
2001-2017 Microchip Technology Inc.
DS20001685E-page 7
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
V /2,
A
DD
SS
CM
DD
OUT DD
R = 10 k to V /2 and C = 60 pF.
L
DD
L
100
50
200
150
100
50
VCM = VDD/2
0
VDD = 5.5V
-50
-100
-150
-200
-250
-300
0
VDD = 2.5V
-50
-100
-150
-200
VDD = 5.0V
VCM = 0V
-50
-25
0
25
50
75
100
125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Ambient Temperature (°C)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
Input Offset Voltage vs.
Temperature.
Output Voltage.
1,000
100
10
24
VDD = 5.0V
22
20
18
16
14
12
10
8
f = 1 kHz
f = 10 kHz
6
4
2
0
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1
0.1
1
10
100
1k
10k 100k 1M
Common Mode Input Voltage (V)
Frequency (Hz)
FIGURE 2-8:
Input Noise Voltage Density
FIGURE 2-11:
Input Noise Voltage Density
vs. Frequency.
vs. Common-Mode Input Voltage.
110
105
100
90
80
70
60
50
40
30
PSRR+
PSRR-
CMRR
100
95
90
PSRR (VCM = 0V)
85
CMRR
80
75
70
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
20
100
1k
10k
100k
1M
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
CMRR, PSRR vs.
Frequency.
Temperature.
DS20001685E-page 8
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
V /2,
A
DD
SS
CM
DD
OUT DD
R = 10 k to V /2 and C = 60 pF.
L
DD
L
10,000
1,000
100
10
10,000
1,000
100
10
VDD = 5.5V
IB, TA = +125°C
VCM = VDD
VDD = 5.5V
IOS, TA = +125°C
IB, TA = +85°C
IB
IOS
IOS, TA = +85°C
1
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
FIGURE 2-13:
Input Bias, Offset Currents
FIGURE 2-16:
Input Bias, Offset Currents
vs. Common-Mode Input Voltage.
vs. Temperature.
1.2
1.1
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VDD = 5.5V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VDD = 2.5V
+125°C
+85°C
+25°C
-40°C
VCM = VDD - 0.5V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
FIGURE 2-14:
Quiescent Current vs.
FIGURE 2-17:
Quiescent Current vs.
Supply Voltage.
Temperature.
120
110
100
90
80
70
60
50
40
30
20
10
0
0
35
30
25
20
15
10
5
-15
-30
-45
-60
-75
Phase
-90
-105
-120
-135
-150
-165
-180
-195
-210
+125°C
+85°C
+25°C
-40°C
Gain
-10
0
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
-20
1
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
FIGURE 2-15:
vs. Supply Voltage.
Output Short-Circuit Current
FIGURE 2-18:
Frequency.
Open-Loop Gain, Phase vs.
2001-2017 Microchip Technology Inc.
DS20001685E-page 9
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
V /2,
A
DD
SS
CM
DD
OUT
DD
R = 10 k to V /2 and C = 60 pF.
L
DD
L
120
115
110
105
100
95
130
120
110
100
90
VDD = 5.5V
VDD = 5.5V
VDD = 2.5V
VDD = 2.5V
1.E+02
1.E+04
80
90
1k
100k
10k
100
-50
-25
0
25
50
75
100
125
Load Resistance (ΩΩ)
Ambient Temperature (°C)
FIGURE 2-19:
DC Open-Loop Gain vs.
FIGURE 2-22:
DC Open-Loop Gain vs.
Load Resistance.
Temperature.
14
105
90
120
VCM = VDD/2
Gain Bandwidth Product
12
10
8
110
100
90
75
VDD = 5.5V
60
Phase Margin, G = +1
45
6
VDD = 2.5V
4
30
15
0
80
2
VDD = 5.0V
70
0.00
0.05
Output Voltage Headroom (V);
DD - VOH or VOL - VSS
0.10
0.15
0.20
0.25
0.30
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
V
FIGURE 2-20:
Small Signal DC Open-Loop
FIGURE 2-23:
Gain Bandwidth Product,
Gain vs. Output Voltage Headroom.
Phase Margin vs. Common-Mode Input Voltage.
14
12
10
8
105
90
75
60
45
30
15
0
10
9
8
7
6
100
90
80
70
60
50
40
30
20
10
0
Gain Bandwidth Product
Phase Margin, G = +1
5
6
GBWP, VDD = 5.5V
4
GBWP, VDD = 2.5V
PM, VDD = 2.5V
PM, VDD = 5.5V
3
2
1
0
4
VDD = 5.0V
VCM = VDD/2
2
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (V)
-50 -25
0
25
50
75 100 125
Ambient Temperature (°C)
FIGURE 2-21:
Gain Bandwidth Product,
FIGURE 2-24:
Gain Bandwidth Product,
Phase Margin vs. Temperature.
Phase Margin vs. Output Voltage.
DS20001685E-page 10
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
V /2,
A
DD
SS
CM
DD
OUT
DD
R = 10 k to V /2 and C = 60 pF.
L
DD
L
11
10
9
8
7
6
5
10
Falling, VDD = 5.5V
Rising, VDD = 5.5V
VDD = 5.5V
VDD = 2.5V
1
4
3
Falling, VDD = 2.5V
Rising, VDD = 2.5V
2
1
0
1.E+04
1.E+05
1.E+06
1.E+07
0.1
-50
-25
0
25
50
75
100
125
10k
100k
Frequency (Hz)
1M
10M
Ambient Temperature (°C)
FIGURE 2-25:
Slew Rate vs. Temperature.
FIGURE 2-28:
Maximum Output Voltage
Swing vs. Frequency.
0.1000%
0.0100%
0.1000%
f = 1 kHz
G = +100 V/V
BWMeas = 22 kHz
VDD = 5.0V
G = +10 V/V
0.0100%
G = +100 V/V
G = +10 V/V
G = +1 V/V
0.0010%
0.0010%
0.0001%
f = 20 kHz
BWMeas = 80 kHz
VDD = 5.0V
G = +1 V/V
0.0001%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
)
Output Voltage (VP-P
)
FIGURE 2-26:
Total Harmonic Distortion
FIGURE 2-29:
Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 1 kHz.
plus Noise vs. Output Voltage with f = 20 kHz.
6
135
130
125
120
115
VDD = 5.0V
VOUT
G = +2 V/V
5
4
VIN
3
2
1
110
G = +1 V/V
0
1.E+03
1.E+04
1.E+05
1.E+06
105
1k
10k
100k
1M
-1
Frequency (Hz)
Time (10 µs/div)
10 20 30 40 50 60 70 80 90 100
0
FIGURE 2-27:
The MCP6021/1R/2/3/4
FIGURE 2-30:
Channel-to-Channel
Family Shows No Phase Reversal Under
Overdrive.
Separation vs. Frequency (MCP6022 and
MCP6024 only).
2001-2017 Microchip Technology Inc.
DS20001685E-page 11
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
V /2,
A
DD
SS
CM
DD
OUT DD
R = 10 k to V /2 and C = 60 pF.
L
DD
L
1,000
100
10
10
9
8
7
6
5
4
3
2
1
0
VOL – VSS
VDD – VOH
VOL – VSS
VDD – VOH
1
0.01
0.1
1
10
-50
-25
0
25
50
75
100 125
Output Current Magnitude (mA)
Ambient Temperature (°C)
FIGURE 2-31:
Output Voltage Headroom
FIGURE 2-34:
Output Voltage Headroom
vs. Output Current.
vs. Temperature.
6.E-02
5.E-02
4.E-02
3.E-02
2.E-02
1.E-02
0.E+00
-1.E-02
-2.E-02
-3.E-02
-4.E-02
-5.E-02
-6.E-02
6.E-02
5.E-02
4.E-02
3.E-02
2.E-02
1.E-02
0.E+00
-1.E-02
-2.E-02
-3.E-02
-4.E-02
-5.E-02
-6.E-02
G = +1 V/V
G = -1 V/V
RF = 1 kΩ
0.E+00
2.E-07
4.E-07
6.E-07
8.E-07
1.E-06
1.E-06
1.E-06
2.E-06
2.E-06
2.E-06
Time (200 ns/div)
0.E+00
2.E-07
4.E-07
6.E-07
8.E-07
1.E-06
1.E-06
1.E-06
2.E-06
2.E-06
2.E-06
Time (200 ns/div)
FIGURE 2-32:
Small Signal Non-Inverting
FIGURE 2-35:
Small Signal Inverting Pulse
Pulse Response.
Response.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
G = +1 V/V
G = -1 V/V
RF = 1 kΩ
0.E+00
5.E-07
1.E-06
2.E-06
2.E-06
3.E-06
3.E-06
4.E-06
4.E-06
5.E-06
5.E-06
0.0
0.E+00
5.E-07
1.E-06
2.E-06
2.E-06
3.E-06
3.E-06
4.E-06
4.E-06
5.E-06
5.E-06
0.0
Time (500 ns/div)
Time (500 ns/div)
FIGURE 2-33:
Large Signal Non-Inverting
FIGURE 2-36:
Large Signal Inverting Pulse
Pulse Response.
Response.
DS20001685E-page 12
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2, V
V /2,
A
DD
SS
CM
DD
OUT DD
R = 10 k to V /2 and C = 60 pF.
L
DD
L
50
40
30
50
40
30
Representative Part
20
10
0
-10
-20
-30
-40
-50
20
10
0
-10
-20
-30
-40
-50
VDD = 5.5V
VDD = 2.5V
-50
-25
0
25
50
75
100 125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-37:
VREF Accuracy vs. Supply
FIGURE 2-40:
VREF Accuracy vs.
Voltage (MCP6021 and MCP6023 only).
Temperature (MCP6021 and MCP6023 only).
1.6
1.6
Op Amp
Op Amp
Op Amp
Op Amp
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
shuts off here
turns on here
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
shuts off here
turns on here
Hysteresis
CS swept
Hysteresis
high to low
CS swept
high to low
CS swept
CS swept
low to high
VDD = 2.5V
G = +1 V/V
VIN = 1.25V
low to high
VDD = 5.5V
G = +1 V/V
VIN = 2.75V
0.0
0.5
1.0
1.5
2.0
2.5
Chip Select Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
FIGURE 2-38:
Chip Select (CS) Hysteresis
FIGURE 2-41:
Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 2.5V.
(MCP6023 only) with VDD = 5.5V.
5.5
5.0
10m
VDD = 5.0V
G = +1 V/V
VIN = VSS
1.E-02
1m
CS Voltage
4.5
1.E-03
100µ
4.0
3.5
1.E-04
10µ
1.E-05
VOUT
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
1µ
1.E-06
100n
1.E-07
10n
1.E-08
Output
on
Output High-Z
Output
on
+125°C
+85°C
+25°C
-40°C
1n
1.E-09
100p
1.E-10
10p
1.E-11
0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
3.5E-05
1p
1.E-12
Time (5 µs/div)
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-39:
Amplifier Output Response Time (MCP6023
Only).
Chip Select (CS) to
FIGURE 2-42:
Input Voltage (Below VSS
Measured Input Current vs.
)
2001-2017 Microchip Technology Inc.
DS20001685E-page 13
MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 14
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP6021
MCP6021
MCP6022
MCP6023
MCP6024
PDIP, SOIC,
MSOP,
TSSOP
Symbol
Description
PDIP, SOIC, PDIP, SOIC, PDIP, SOIC,
(2)
SOT-23-5
SOT-23-5
TSSOP
TSSOP
TSSOP
(1)
6
2
1
1
1
2
6
2
1
2
V
, V
Analog Output (Op Amp A)
Inverting Input (Op Amp A)
Non-Inverting Input (Op Amp A)
Positive Power Supply
OUT OUTA
4
4
V
-, V
-
IN
INA
INA
3
3
3
3
3
3
V
+, V
+
IN
7
5
2
8
7
4
V
DD
—
—
—
—
—
—
4
—
—
—
—
—
—
2
—
—
—
—
—
—
5
5
—
—
—
—
—
—
4
5
V
+
–
Non-Inverting Input (Op Amp B)
Inverting Input (Op Amp B)
Analog Output (Op Amp B)
Analog Output (Op Amp C)
Inverting Input (Op Amp C)
Non-Inverting Input (Op Amp C)
Negative Power Supply
INB
INB
6
6
V
7
7
V
V
OUTB
OUTC
—
—
—
4
8
9
V
V
–
+
INC
INC
10
11
12
13
14
—
—
—
V
SS
—
—
—
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
V
V
+
Non-Inverting Input (Op Amp D)
Inverting Input (Op Amp D)
Analog Output (Op Amp D)
Reference Voltage
IND
IND
–
V
OUTD
V
REF
—
1, 8
8
CS
Chip Select
1
NC
No Internal Connection
Note 1: The MCP6021 in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts.
2: The MCP6021R is only available in the 5-pin SOT-23 package and for E-temp (Extended Temperature) parts.
3.1
Analog Outputs
3.4
Chip Select Digital Input (CS)
The operational amplifier output pins are low-impedance
voltage sources.
This is a CMOS, Schmitt triggered input that places the
part into a Low-Power mode of operation.
3.2
Analog Inputs
3.5
Power Supply (V and V
)
SS
DD
The operational amplifier non-inverting and inverting
inputs are high-impedance CMOS inputs with low bias
currents.
The positive power supply pin (V ) is 2.5V to 5.5V
DD
higher than the negative power supply pin (V ). For
SS
normal operation, the other pins are at voltages
between V and V
.
SS
DD
3.3
Reference Voltage (V
)
Typically, these parts are used in a single (positive)
REF
supply configuration. In this case, V is connected to
MCP6021 and MCP6023
SS
ground and V
is connected to the supply. V
will
DD
DD
Mid-supply reference voltage is provided by the single
operational amplifiers (except in the SOT-23-5
package). This is an unbuffered, resistor voltage divider
internal to the part.
need a bypass capacitor.
2001-2017 Microchip Technology Inc.
DS20001685E-page 15
MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 16
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
4.0
APPLICATIONS INFORMATION
V
DD
The MCP6021/1R/2/3/4 family of operational amplifiers
is fabricated on Microchip’s state-of-the-art CMOS
process. The amplifiers are unity-gain stable and suitable
for a wide range of general purpose applications.
U
D
D
2
1
1
V
V
1
V
MCP602X
OUT
4.1
Rail-to-Rail Input
2
4.1.1
PHASE REVERSAL
The MCP6021/1R/2/3/4 operational amplifiers are
designed to prevent phase reversal when the input pins
exceed the supply voltages. Figure 2-42 shows the
input voltage exceeding the supply voltage without any
phase reversal.
FIGURE 4-2:
Protecting the Analog Inputs.
4.1.3 INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins. See the Absolute Maximum Ratings†
section. Figure 4-3 shows one approach to protecting
4.1.2
INPUT VOLTAGE LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins. See the Absolute Maximum Ratings†
section.
these inputs. The resistors, R and R , limit the pos-
1
2
sible currents in or out of the input pins (and the ESD
diodes, D and D ). The diode currents will go through
1
2
either V or V
.
DD
SS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors and to minimize Input Bias
V
DD
(I ) current.
B
D
D
2
U
1
1
V
Bond
Pad
1
VDD
V
OUT
R
R
1
MCP602X
V
2
2
Bond
Pad
Bond
Pad
Input
Stage
VINꢀ
VIN+
V
– min (V ,V )
SS
1
2
min(R ,R ) >
1
2
2 mA
max(V ,V ) – V
1
2
DD
min(R ,R ) >
1
2
2 mA
Bond
Pad
VSS
FIGURE 4-3:
Protecting the Analog Inputs.
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
4.1.4 NORMAL OPERATION
The input stage of the MCP6021/1R/2/3/4 operational
amplifiers uses two differential CMOS input stages in
parallel. One operates at a low Common-Mode Voltage
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below V . They also
SS
clamp any voltages that go well above V . Their
DD
(V ) input, while the other operates at high V . With
CM
CM
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
this topology, the device operates with V
up to 0.3V
CM
above V and 0.3V below V
.
DD
SS
overvoltage (beyond V ) events. Very fast ESD
DD
events (that meet the specifications) are limited so that
damage does not occur. In some applications, it may
be necessary to prevent excessive voltages from
reaching the operational amplifier inputs. Figure 4-2
shows one approach to protecting these inputs.
4.2
Rail-to-Rail Output
The maximum output voltage swing is the maximum
swing possible under a particular output load. According
to the specification table, the output can reach within
20 mV of either supply rail when R = 10 k. See
Figure 2-31 and Figure 2-34 for more information
concerning typical performance.
A significant amount of current can flow out of the
L
inputs when the Common-Mode Voltage (V ) is below
CM
ground (V ). See Figure 2-42.
SS
2001-2017 Microchip Technology Inc.
DS20001685E-page 17
MCP6021/1R/2/3/4
4.3
Capacitive Loads
4.4
Gain Peaking
Driving large capacitive loads can cause stability
problems for voltage feedback operational amplifiers.
As the load capacitance increases, the feedback loop’s
phase margin decreases and the closed loop
bandwidth is reduced. This produces gain peaking in
the frequency response, with overshoot and ringing in
the step response.
Figure 2-35 and Figure 2-36 use R = 1 k to avoid
(frequency response) gain peaking and (step response)
overshoot. The capacitance to ground at the inverting
F
input (C ) is the op amp’s Common-mode input capaci-
G
tance plus board parasitic capacitance. C is in parallel
G
with R , which causes an increase in gain at high frequen-
G
cies for non-inverting gains greater than 1 V/V (unity
gain). C also reduces the phase margin of the feedback
loop for both non-inverting and inverting gains.
G
When driving large capacitive loads with these opera-
tional amplifiers (e.g., > 60 pF when G = +1), a small
series resistor at the output (R
in Figure 4-4)
ISO
improves the feedback loop’s phase margin (stability)
by making the load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
V
IN
V
OUT
R
F
C
G
V
R
IN
G
R
ISO
V
MCP602X
OUT
C
L
FIGURE 4-6:
Non-Inverting Gain Circuit
with Parasitic Capacitance.
The largest value of R in Figure 4-6 that should be
F
FIGURE 4-4:
Stabilizes Large Capacitive Loads.
Output Resistor, RISO,
used is a function of noise gain (see G in Section 4.3
N
“Capacitive Loads”) and C . Figure 4-7 shows results
G
Figure 4-5 gives recommended
R
values for
for various conditions. Other compensation techniques
may be used, but they tend to be more complicated to
design.
ISO
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C /G ), where G is the
L
N
N
circuit’s noise gain. For non-inverting gains, G and the
N
Signal Gain are equal. For inverting gains, G is
1.E+05
100k
N
GN > +1 V/V
1+|Signal Gain| (e.g., -1 V/V gives G = +2 V/V).
N
CG = 7 pF
CG = 20 pF
1,000
1.E+04
10k
G
N ≥ +1
1k
1.E+03
CG = 50 pF
100
10
CG = 100 pF
1.E+10020
1
10
Noise Gain; GN (V/V)
FIGURE 4-7:
with Parasitic Capacitance.
Non-Inverting Gain Circuit
10
100
1,000
10,000
Normalized Capacitance; CL/GN (pF)
4.5
MCP6023 Chip Select (CS)
FIGURE 4-5:
Recommended RISO Values
for Capacitive Loads.
The MCP6023 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
After selecting R
for your circuit, double-check the
ISO
to 10 nA (typical) and flows through the CS pin to V
.
resulting frequency response peaking and step
SS
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 MΩ (typical)
response overshoot. Modify R ’s value until the
ISO
response is reasonable. Evaluation on the bench and
simulations with the MCP6021/1R/2/3/4 Spice macro
model are helpful.
pull-down resistor connected to V , so it will go low if
SS
the CS pin is left floating. Figure 1-1 and Figure 2-39
show the output voltage and supply current response to
a CS pulse.
DS20001685E-page 18
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
4.6
MCP6021 and MCP6023 Reference
Voltage
R
R
G
F
V
V
OUT
IN
The single operational amplifiers (MCP6021 and
MCP6023), not in the SOT-23-5 package, have an
internal mid-supply reference voltage connected to the
V
pin (see Figure 4-8). The MCP6021 has CS inter-
V
REF
REF
nally tied to V , which always keeps the operational
SS
amplifier on and always provides a mid-supply refer-
ence. With the MCP6023, taking the CS pin high
conserves power by shutting down both the operational
C
B
amplifier and the V
circuitry. Taking the CS pin low
REF
turns on the operational amplifier and V
circuitry.
FIGURE 4-10:
Inverting Gain Circuit Using
REF
V
REF (MCP6021 and MCP6023 only).
V
DD
If you don’t need the mid-supply reference, leave the
pin open.
V
REF
50 k
50 k
4.7
Supply Bypass
V
REF
With this family of operational amplifiers, the power
supply pin (V for single supply) should have a local
DD
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
CS
5 M
4.8
Unused Operational Amplifiers
An unused operational amplifier in a quad package
(MCP6024) should be configured as shown in
Figure 4-11. These circuits prevent the output from tog-
gling and causing crosstalk. Circuit A sets the opera-
tional amplifier at its minimum noise gain. The resistor
divider produces any desired reference voltage within
the output voltage range of the operational amplifier.
The operational amplifier buffers that reference
voltage. Circuit B uses the minimum number of compo-
nents and operates as a comparator, but it may draw
more current.
V
SS
(CS tied internally to V for MCP6021)
SS
FIGURE 4-8:
Simplified Internal VREF
Circuit (MCP6021 and MCP6023 only).
See Figure 4-9 for a non-inverting gain circuit using the
internal mid-supply reference. The DC Blocking
Capacitor (C ) also reduces noise by coupling the
B
operational amplifier input to the source.
¼ MCP6024 (A)
¼ MCP6024 (B)
R
R
F
G
V
V
DD
DD
V
DD
R
V
1
OUT
C
B
V
REF
V
REF
V
R
IN
2
FIGURE 4-9:
Using VREF (MCP6021 and MCP6023 only).
Non-Inverting Gain Circuit
R
2
V
= V
+ --------------------
REF
DD
R
+ R
1
2
To use the internal mid-supply reference for an
inverting gain circuit, connect the V
non-inverting input, as shown in Figure 4-10. The
pin to the
REF
FIGURE 4-11:
Amplifiers.
Unused Operational
capacitor, C , helps reduce power supply noise on the
B
output.
2001-2017 Microchip Technology Inc.
DS20001685E-page 19
MCP6021/1R/2/3/4
Use a solid ground plane and connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
4.9
PCB Surface Leakage
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
Separate digital from analog, low speed from high
speed and low power from high power. This will reduce
interference.
12
between nearby traces is 10 . A 5V difference would
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high-frequency (low rise time)
signals.
cause 5 pA of current to flow, which is greater than the
MCP6021/1R/2/3/4 family’s bias current at +25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-12 shows an example of this type of layout.
Sometimes it helps to place guard traces next to victim
traces. They should be on both sides of the victim trace
and as close as possible. Connect the guard trace to
the ground plane at both ends and in the middle for long
traces.
Guard Ring
V - V +
IN IN
Use coax cables (or low-inductance wiring) to route
signal and power to and from the PCB.
4.11 Typical Applications
4.11.1
A/D CONVERTER DRIVER AND
ANTI-ALIASING FILTER
FIGURE 4-12:
Example Guard Ring Layout.
Figure 4-13 shows a third-order Butterworth filter that
can be used as an A/D Converter driver. It has a band-
width of 20 kHz and a reasonable step response. It will
work well for conversion rates of 80 ksps and greater (it
has 29 dB attenuation at 60 kHz).
1. Non-Inverting Gain and Unity Gain Buffer.
a) Connect the guard ring to the inverting input
pin (V -); this biases the guard ring to the
IN
Common-mode input voltage.
b) Connect the non-inverting pin (V +) to the
IN
input with a wire that does not touch the
PCB surface.
1.0 nF
MCP602X
33.2 k
8.45 k 14.7 k
2. Inverting (Figure 4-12) and Transimpedance Gain
Amplifiers (convert current to voltage, such as
photo detectors).
100 pF
1.2 nF
a) Connect the guard ring to the non-inverting
input pin (V +). This biases the guard ring
IN
to the same reference voltage as the
FIGURE 4-13:
Anti-Aliasing Filter with a 20 kHz Cutoff
Frequency.
A/D Converter Driver and
operational amplifier’s input (e.g., V /2 or
DD
ground).
b) Connect the inverting pin (V -) to the input
IN
This filter can easily be adjusted to another bandwidth
by multiplying all capacitors by the same factor.
Alternatively, the resistors can all be scaled by another
common factor to adjust the bandwidth.
with a wire that does not touch the PCB
surface.
4.10 High-Speed PCB Layout
Due to their speed capabilities, a little extra care in the
PCB (Printed Circuit Board) layout can make a signifi-
cant difference in the performance of these operational
amplifiers. Good PC board layout techniques will help
you achieve the performance shown in Section 1.0
“Electrical Characteristics” and Section 2.0 “Typical
Performance Curves”, while also helping you minimize
EMC (Electro-Magnetic Compatibility) issues.
DS20001685E-page 20
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
4.11.2
OPTICAL DETECTOR AMPLIFIER
5.6 pF
Photo
Detector
Figure 4-14 shows the MCP6021 operational amplifier
used as a transimpedance amplifier in a photo detector
circuit. The photo detector looks like a capacitive
current source, so the 100 k resistor gains the input
signal to a reasonable level. The 5.6 pF capacitor
stabilizes this circuit and produces a flat frequency
response with a bandwidth of 370 kHz.
100 k
100 pF
MCP6021
V
/2
DD
FIGURE 4-14:
Transimpedance Amplifier
for an Optical Detector.
2001-2017 Microchip Technology Inc.
DS20001685E-page 21
MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 22
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
5.5
Analog Demonstration and
Evaluation Boards
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6021/1R/2/3/4 family of operational amplifiers.
Microchip offers a broad spectrum of analog demon-
stration and evaluation boards that are designed to
help you achieve faster time to market. For a complete
listing of these boards, and their corresponding user’s
guides and technical information, visit the Microchip
web site at www.microchip.com/analogtools.
5.1
SPICE Macro Model
The latest SPICE macro model available for the
MCP6021/1R/2/3/4 operational amplifiers is on
Microchip’s web site at www.microchip.com. This
model is intended as an initial design tool that works
well in the operational amplifier’s linear region of oper-
ation at room temperature. There is information on its
capabilities within the macro model file.
Some boards that are especially useful are:
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N: SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N: SOIC14EV
®
5.2
FilterLab Software
®
Microchip’s FilterLab software is an innovative software
tool that simplifies analog active filter (using operational
amplifiers) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams of
the filter circuit with component values. It also outputs
the filter circuit in SPICE format, which can be used with
the macro model to simulate actual filter performance.
5.6
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
• ADN003, “Select the Right Operational Amplifier
for your Filtering Circuits” (DS21821)
• AN722, “Operational Amplifier Topologies and DC
Specifications” (DS00722)
®
5.3
MPLAB Mindi™ Analog
Simulator
• AN723, “Operational Amplifier AC Specifications
and Applications” (DS00723)
Microchip’s Mindi™ circuit designer and simulator aids
in the design of various circuits useful for active filter,
amplifier and power management applications. It is a
free online circuit designer and simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer and simulator enables
designers to quickly generate circuit diagrams and
simulate circuits. Circuits developed using the MPLAB
Mindi analog simulator can be downloaded to a
personal computer or workstation.
• AN884, “Driving Capacitive Loads With Op Amps”
(DS00884)
• AN990, “Analog Sensor Conditioning Circuits –
An Overview” (DS00990)
• AN1177, “Op Amp Precision Design: DC Errors”
(DS01177)
• AN1228, “Op Amp Precision Design: Random
Noise” (DS01228)
These application notes and others are listed in the
design guide: “Signal Chain Design Guide” (DS21825).
5.4
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor pro-
fessionals efficiently identify Microchip devices that fit a
particular design requirement. Available at no cost from
the Microchip web site at www.microchip.com/maps,
the MAPS is an overall selection tool for Microchip’s
product portfolio, that includes analog, memory, MCUs
and DSCs. Using this tool you can define a filter to sort
features for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for data sheets, purchasing and
sampling of Microchip parts.
2001-2017 Microchip Technology Inc.
DS20001685E-page 23
MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 24
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SOT-23 (MCP6021/MCP6021R)
Example:
Device
E-Temp Code
MCP6021
EYNN
EZNN
EY25
MCP6021R
Note:
Applies to 5-Lead SOT-23.
8-Lead PDIP (300 mil)
Example:
MCP6021
MCP6021
I/P256
1603
OR
e
3
256
E/P
1603
8-Lead SOIC (150 mil)
Example:
MCP6021E
SN 1603
MCP6021
I/SN1603
256
OR
e
3
256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
®
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2001-2017 Microchip Technology Inc.
DS20001685E-page 25
MCP6021/1R/2/3/4
Package Marking Information (Continued)
8-Lead MSOP
Example:
6021E
903256
8-Lead TSSOP
Example:
6021
E903
256
14-Lead PDIP (300 mil) (MCP6024)
Example:
MCP6024-I/P
0903256
OR
e
3
MCP6024-E/P
0903256
DS20001685E-page 26
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6024)
Example:
MCP6024-I/SL
1603256
OR
MCP6024
e
3
E/SL
1603256
14-Lead TSSOP (MCP6024)
Example:
6024E
1603
256
2001-2017 Microchip Technology Inc.
DS20001685E-page 27
MCP6021/1R/2/3/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A2
A1
A
0.20 C
SEATING PLANE
A
SEE SHEET 2
C
SIDE VIEW
Microchip Technology Drawing C04-028D [OT] Sheet 1 ofꢁꢂ
DS20001685E-page 28
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
6
0.95 BSC
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
-
-
-
-
1.45
1.30
0.15
2.80 BSC
1.60 BSC
2.90 BSC
0.30
-
0.60
Footprint
Foot Angle
Lead Thickness
Lead Width
L1
0.60 REF
I
0°
0.08
0.20
-
-
-
10°
0.26
0.51
c
b
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091D [OT] Sheet 2 ofꢁꢂ
2001-2017 Microchip Technology Inc.
DS20001685E-page 29
MCP6021/1R/2/3/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
C
X
0.95 BSC
2.80
Contact Pad Spacing
Contact Pad Width (X5)
Contact Pad Length (X5)
Distance Between Pads
Distance Between Pads
Overall Width
0.60
1.10
Y
G
GX
Z
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091A [OT]
DS20001685E-page 30
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
A2
A
C
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
2001-2017 Microchip Technology Inc.
DS20001685E-page 31
MCP6021/1R/2/3/4
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
INCHES
NOM
8
.100 BSC
-
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
-
.210
.195
-
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
.130
-
.310
.250
.365
.130
.010
.060
.018
-
.325
.280
.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing
§
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
DS20001685E-page 32
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2017 Microchip Technology Inc.
DS20001685E-page 33
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001685E-page 34
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
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2001-2017 Microchip Technology Inc.
DS20001685E-page 35
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001685E-page 36
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2017 Microchip Technology Inc.
DS20001685E-page 37
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001685E-page 38
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
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1ꢐ (ꢌꢈꢃ1ꢃ3ꢌ"#ꢊꢍꢃꢌꢈ%ꢆ6ꢃ)ꢆꢊꢄ#ꢂꢆꢃ!ꢊꢑꢃ3ꢊꢂꢑ'ꢃ7#ꢄꢃ!#"ꢄꢃ7ꢆꢃꢍꢁꢇꢊꢄꢆ%ꢃ&ꢌꢄꢅꢌꢈꢃꢄꢅꢆꢃꢅꢊꢄꢇꢅꢆ%ꢃꢊꢂꢆꢊꢐ
ꢒꢐ ꢓꢌ!ꢆꢈ"ꢌꢁꢈ"ꢃꢓꢃꢊꢈ%ꢃ81ꢃ%ꢁꢃꢈꢁꢄꢃꢌꢈꢇꢍ#%ꢆꢃ!ꢁꢍ%ꢃ)ꢍꢊ"ꢅꢃꢁꢂꢃꢉꢂꢁꢄꢂ#"ꢌꢁꢈ"ꢐꢃꢎꢁꢍ%ꢃ)ꢍꢊ"ꢅꢃꢁꢂꢃꢉꢂꢁꢄꢂ#"ꢌꢁꢈ"ꢃ"ꢅꢊꢍꢍꢃꢈꢁꢄꢃꢆ6ꢇꢆꢆ%ꢃꢔꢐ1;ꢃ!!ꢃꢉꢆꢂꢃ"ꢌ%ꢆꢐ
<ꢐ ꢓꢌ!ꢆꢈ"ꢌꢁꢈꢌꢈꢋꢃꢊꢈ%ꢃꢄꢁꢍꢆꢂꢊꢈꢇꢌꢈꢋꢃꢉꢆꢂꢃꢕꢏꢎ8ꢃ=1ꢖꢐ;ꢎꢐ
>ꢏ?* >ꢊ"ꢌꢇꢃꢓꢌ!ꢆꢈ"ꢌꢁꢈꢐꢃꢗꢅꢆꢁꢂꢆꢄꢌꢇꢊꢍꢍꢑꢃꢆ6ꢊꢇꢄꢃ3ꢊꢍ#ꢆꢃ"ꢅꢁ&ꢈꢃ&ꢌꢄꢅꢁ#ꢄꢃꢄꢁꢍꢆꢂꢊꢈꢇꢆ"ꢐ
ꢘ8ꢀ* ꢘꢆ)ꢆꢂꢆꢈꢇꢆꢃꢓꢌ!ꢆꢈ"ꢌꢁꢈ'ꢃ#"#ꢊꢍꢍꢑꢃ&ꢌꢄꢅꢁ#ꢄꢃꢄꢁꢍꢆꢂꢊꢈꢇꢆ'ꢃ)ꢁꢂꢃꢌꢈ)ꢁꢂ!ꢊꢄꢌꢁꢈꢃꢉ#ꢂꢉꢁ"ꢆ"ꢃꢁꢈꢍꢑꢐ
ꢎꢌꢇꢂꢁꢇꢅꢌꢉ ꢗꢆꢇꢅꢈꢁꢍꢁꢋꢑ ꢓꢂꢊ&ꢌꢈꢋ ?ꢔꢖꢟꢔꢚJ>
2001-2017 Microchip Technology Inc.
DS20001685E-page 39
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001685E-page 40
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
ꢩꢨꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢪꢐꢄꢈꢆꢡꢑꢁꢂꢋꢑꢃꢆꢒꢇꢔꢆꢕꢆꢚꢝꢝꢆꢎꢋꢈꢆꢞꢗꢅꢟꢆꢠꢇꢪꢡꢇꢣ
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
c
A1
b1
b
e
eB
@ꢈꢌꢄ"
ꢓꢌ!ꢆꢈ"ꢌꢁꢈꢃAꢌ!ꢌꢄ"
ꢙE?K8ꢏ
EGꢎ
1ꢖ
ꢐ1ꢔꢔꢃ>ꢏ?
ꢛ
ꢎꢙE
ꢎꢕH
E#!7ꢆꢂꢃꢁ)ꢃ(ꢌꢈ"
(ꢌꢄꢇꢅ
E
ꢆ
ꢕ
ꢗꢁꢉꢃꢄꢁꢃꢏꢆꢊꢄꢌꢈꢋꢃ(ꢍꢊꢈꢆ
ꢛ
ꢐꢒ1ꢔ
ꢐ1ꢜ;
ꢛ
ꢎꢁꢍ%ꢆ%ꢃ(ꢊꢇ$ꢊꢋꢆꢃꢗꢅꢌꢇ$ꢈꢆ""
>ꢊ"ꢆꢃꢄꢁꢃꢏꢆꢊꢄꢌꢈꢋꢃ(ꢍꢊꢈꢆ
ꢏꢅꢁ#ꢍ%ꢆꢂꢃꢄꢁꢃꢏꢅꢁ#ꢍ%ꢆꢂꢃNꢌ%ꢄꢅ
ꢎꢁꢍ%ꢆ%ꢃ(ꢊꢇ$ꢊꢋꢆꢃNꢌ%ꢄꢅ
G3ꢆꢂꢊꢍꢍꢃAꢆꢈꢋꢄꢅ
ꢗꢌꢉꢃꢄꢁꢃꢏꢆꢊꢄꢌꢈꢋꢃ(ꢍꢊꢈꢆ
Aꢆꢊ%ꢃꢗꢅꢌꢇ$ꢈꢆ""
@ꢉꢉꢆꢂꢃAꢆꢊ%ꢃNꢌ%ꢄꢅ
ꢕꢒ
ꢕ1
8
81
ꢓ
A
ꢇ
71
7
ꢆ>
ꢐ11;
ꢐꢔ1;
ꢐꢒꢜꢔ
ꢐꢒꢖꢔ
ꢐꢝ<;
ꢐ11;
ꢐꢔꢔꢚ
ꢐꢔꢖ;
ꢐꢔ1ꢖ
ꢛ
ꢐ1<ꢔ
ꢛ
ꢐ<1ꢔ
ꢐꢒ;ꢔ
ꢐꢝ;ꢔ
ꢐ1<ꢔ
ꢐꢔ1ꢔ
ꢐꢔJꢔ
ꢐꢔ1ꢚ
ꢛ
ꢐ<ꢒ;
ꢐꢒꢚꢔ
ꢐꢝꢝ;
ꢐ1;ꢔ
ꢐꢔ1;
ꢐꢔꢝꢔ
ꢐꢔꢒꢒ
ꢐꢖ<ꢔ
Aꢁ&ꢆꢂꢃAꢆꢊ%ꢃNꢌ%ꢄꢅ
G3ꢆꢂꢊꢍꢍꢃꢘꢁ&ꢃꢏꢉꢊꢇꢌꢈꢋꢃꢃꢠ
ꢓꢗꢊꢃꢉꢤ
1ꢐ (ꢌꢈꢃ1ꢃ3ꢌ"#ꢊꢍꢃꢌꢈ%ꢆ6ꢃ)ꢆꢊꢄ#ꢂꢆꢃ!ꢊꢑꢃ3ꢊꢂꢑ'ꢃ7#ꢄꢃ!#"ꢄꢃ7ꢆꢃꢍꢁꢇꢊꢄꢆ%ꢃ&ꢌꢄꢅꢃꢄꢅꢆꢃꢅꢊꢄꢇꢅꢆ%ꢃꢊꢂꢆꢊꢐ
ꢒꢐ ꢠꢃꢏꢌꢋꢈꢌ)ꢌꢇꢊꢈꢄꢃ?ꢅꢊꢂꢊꢇꢄꢆꢂꢌ"ꢄꢌꢇꢐ
<ꢐ ꢓꢌ!ꢆꢈ"ꢌꢁꢈ"ꢃꢓꢃꢊꢈ%ꢃ81ꢃ%ꢁꢃꢈꢁꢄꢃꢌꢈꢇꢍ#%ꢆꢃ!ꢁꢍ%ꢃ)ꢍꢊ"ꢅꢃꢁꢂꢃꢉꢂꢁꢄꢂ#"ꢌꢁꢈ"ꢐꢃꢎꢁꢍ%ꢃ)ꢍꢊ"ꢅꢃꢁꢂꢃꢉꢂꢁꢄꢂ#"ꢌꢁꢈ"ꢃ"ꢅꢊꢍꢍꢃꢈꢁꢄꢃꢆ6ꢇꢆꢆ%ꢃꢐꢔ1ꢔRꢃꢉꢆꢂꢃ"ꢌ%ꢆꢐ
ꢖꢐ ꢓꢌ!ꢆꢈ"ꢌꢁꢈꢌꢈꢋꢃꢊꢈ%ꢃꢄꢁꢍꢆꢂꢊꢈꢇꢌꢈꢋꢃꢉꢆꢂꢃꢕꢏꢎ8ꢃ=1ꢖꢐ;ꢎꢐ
>ꢏ?*ꢃ>ꢊ"ꢌꢇꢃꢓꢌ!ꢆꢈ"ꢌꢁꢈꢐꢃꢗꢅꢆꢁꢂꢆꢄꢌꢇꢊꢍꢍꢑꢃꢆ6ꢊꢇꢄꢃ3ꢊꢍ#ꢆꢃ"ꢅꢁ&ꢈꢃ&ꢌꢄꢅꢁ#ꢄꢃꢄꢁꢍꢆꢂꢊꢈꢇꢆ"ꢐ
ꢎꢌꢇꢂꢁꢇꢅꢌꢉ ꢗꢆꢇꢅꢈꢁꢍꢁꢋꢑ ꢓꢂꢊ&ꢌꢈꢋ ?ꢔꢖꢟꢔꢔ;>
2001-2017 Microchip Technology Inc.
DS20001685E-page 41
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001685E-page 42
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2017 Microchip Technology Inc.
DS20001685E-page 43
MCP6021/1R/2/3/4
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ
DS20001685E-page 44
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2017 Microchip Technology Inc.
DS20001685E-page 45
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001685E-page 46
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2017 Microchip Technology Inc.
DS20001685E-page 47
MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 48
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
Revision B (November 2003)
APPENDIX A: REVISION HISTORY
Revision E (January 2017)
• Second Release of this Document
Revision A (November 2001)
The following is the list of modifications:
1. Updated the AC Electrical Characteristics table.
• Original Release of this Document
2. Added Section 4.1.2, Input Voltage Limits and
Section 4.1.3, Input Current Limits.
3. Added package information for 8-pin TSSOP.
4. Various typographical edits.
Revision D (February 2009)
The following is the list of modifications:
1. Changed all references to 6.0V back to 5.5V
throughout document.
2. Design Aids: Name change for Mindi Simulation
Tool.
3. Section 1.0, Electrical Characteristics, Section
“”: Corrected “Maximum Output Voltage Swing”
condition from 0.9V Input Overdrive to 0.5V
Input Overdrive.
4. Section 1.0, Electrical Characteristics, Section
“AC Electrical Characteristics”: Changed
Phase Margin condition from G = +1 to G= +1 V/V.
5. Section 1.0, Electrical Characteristics, Section
“AC Electrical Characteristics”: Changed
Settling Time, 0.2% condition from G = +1 to
G = +1 V/V.
6. Section 1.0, Electrical Characteristics: Added
Section 1.1, Test Circuits
7. Section 5.0, Design Aids: Name change for
Mindi Simulation Tool. Added new boards to
Section 5.5, Analog Demonstration and Evalua-
tion Boards and new application notes to
Section 5.6, Application Notes.
8. Updates Appendix A: “Revision History”
Revision C (December 2005)
The following is the list of modifications:
1. Added SOT-23-5 package option for single op
amps MCP6021 and MCP6021R (E-temp only).
2. Added MSOP-8 package option for E-temp
single op amp (MCP6021).
3. Corrected package drawing on front page for
dual op amp (MCP6022).
4. Clarified spec conditions (I , PM and THD+N)
SC
in Section 2.0, Typical Performance Curves.
5. Added Section 3.0, Pin Descriptions.
6. Updated Section 4.0, Applications Information
for THD+N, unused op amps, and gain peaking
discussions.
7. Corrected and updated package marking infor-
mation in Section 6.0, Packaging Information.
8. Added Appendix A: “Revision History”.
2001-2017 Microchip Technology Inc.
DS20001685E-page 49
MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 50
2001-2017 Microchip Technology Inc.
MCP6021/1R/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office
.
(1)
Examples:
a) MCP6021T-E/OT: Tape and Reel,
X
/XX
PART NO.
Device
[X]
Temperature Package
Range
Tape and Reel
Option
Extended temperature,
5LD SOT-23.
b) MCP6021-E/P:
Extended temperature,
8LD PDIP.
c) MCP6021-E/SN: Extended temperature,
8LD SOIC.
Device:
MCP6021
MCP6021T Single Op Amp
(Tape and Reel for SOT-23, SOIC, TSSOP,
MSOP)
MCP6021R Single Op Amp
MCP6021RT Single Op Amp
Single Op Amp
a) MCP6021RT-E/OT: Tape and Reel,
Extended temperature,
5LD SOT-23.
a) MCP6022-I/P:
b) MCP6022-E/P:
Industrial temperature,
8LD PDIP.
Extended temperature,
8LD PDIP.
(Tape and Reel for SOT-23)
Dual Op Amp
MCP6022T Dual Op Amp
(Tape and Reel for SOIC and TSSOP)
Single Op Amp w/CS
MCP6023T Single Op Amp w/CS
(Tape and Reel for SOIC and TSSOP)
Quad Op Amp
MCP6024T Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
MCP6022
c) MCP6022T-E/ST: Tape and Reel,
Extended temperature,
MCP6023
8LD TSSOP.
a) MCP6023-I/P:
b) MCP6023-E/P:
Industrial temperature,
8LD PDIP.
Extended temperature,
8LD PDIP.
MCP6024
c) MCP6023-E/SN: Extended temperature,
8LD SOIC.
Tape and Reel
Option:
Blank = Standard packaging (tube or tray)
T
= Tape and Reel(1)
a) MCP6024-I/SL:
Industrial temperature,
14LD SOIC.
b) MCP6024-E/SL: Extended temperature,
14LD SOIC.
c) MCP6024T-E/ST: Tape and Reel,
Extended temperature,
14LD TSSOP.
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Package:
OT
= Plastic Small Outline Transistor (SOT-23), 5-Lead
(MCP6021, E-Temp; MCP6021R, E-Temp)
MS = Plastic MSOP, 8-Lead (MCP6021, E-Temp)
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identi-
fier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
P
= Plastic DIP (300 mil Body), 8-Lead, 14-Lead
= Plastic SOIC (150 mil Body), 8-Lead
= Plastic SOIC (150 mil Body), 14-Lead
= Plastic TSSOP, 8-Lead (MCP6021, I-Temp; MCP6022,
I-Temp, E-Temp; MCP6023, I-Temp, E-Temp)
= Plastic TSSOP, 14-Lead
SN
SL
ST
availability with the Tape and Reel option.
ST
2001-2017 Microchip Technology Inc.
DS20001685E-page 51
MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 52
2001-2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEE
LOQ,
K
EEL
OQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
are for its PIC® MCUs and dsPIC® DSCs, KEE OQ® code hopping
L
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2001-2017, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-1278-6
== ISO/TS 16949 ==
2001-2017 Microchip Technology Inc.
DS20001685E-page 53
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
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DS20001685E-page 54
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11/07/16
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