MCP604-EST [MICROCHIP]
2.7V to 6.0V Single Supply CMOS Op Amps; 2.7V至6.0V单电源CMOS运算放大器
| 型号： | MCP604-EST |
| 厂家： | 
MICROCHIP |
| 描述： | 2.7V to 6.0V Single Supply CMOS Op Amps |
| 文件： | 总34页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP601/1R/2/3/4
2.7V to 6.0V Single Supply CMOS Op Amps
Description
Features
• Single-Supply: 2.7V to 6.0V
• Rail-to-Rail Output
The Microchip Technology Inc. MCP601/1R/2/3/4
family of low-power operational amplifiers (op amps)
are offered in single (MCP601), single with Chip Select
(CS) (MCP603), dual (MCP602), and quad (MCP604)
configurations. These op amps utilize an advanced
CMOS technology that provides low bias current, high-
speed operation, high open-loop gain, and rail-to-rail
output swing. This product offering operates with a
single supply voltage that can be as low as 2.7V, while
drawing 230 µA (typical) of quiescent current per
amplifier. In addition, the common mode input voltage
range goes 0.3V below ground, making these
amplifiers ideal for single-supply operation.
• Input Range Includes Ground
• Gain Bandwidth Product: 2.8 MHz (typical)
• Unity-Gain Stable
• Low Quiescent Current: 230 µA/amplifier (typical)
• Chip Select (CS): MCP603 only
• Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Available in Single, Dual, and Quad
These devices are appropriate for low power, battery
operated circuits due to the low quiescent current, for
A/D convert driver amplifiers because of their wide
bandwidth or for anti-aliasing filters by virtue of their low
input bias current.
Typical Applications
• Portable Equipment
• A/D Converter Driver
• Photo Diode Pre-amp
• Analog Filters
The MCP601, MCP602, and MCP603 are available in
standard 8-lead PDIP, SOIC, and TSSOP packages.
The MCP601 and MCP601R are also available in a
standard 5-lead SOT-23 package, while the MCP603 is
available in a standard 6-lead SOT-23 package. The
MCP604 is offered in standard 14-lead PDIP, SOIC,
and TSSOP packages.
• Data Acquisition
• Notebooks and PDAs
• Sensor Interface
Available Tools
The MCP601/1R/2/3/4 family is available in the
Industrial and Extended temperature ranges and has a
power supply range of 2.7V to 6.0V.
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Simulation Tool
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
Package Types
MCP604
MCP603
MCP601
PDIP, SOIC, TSSOP
NC
MCP602
PDIP, SOIC, TSSOP
PDIP, SOIC, TSSOP
PDIP, SOIC, TSSOP
VOUTA
VOUTA
NC
V
OUTD
1
NC
1
VDD
8
7
1
2
3
4
5
6
7
8
1
CS
14
13
12
11
10
9
8
7
VDD
V
IN– 2
VOUTB
VINA
–
+
V
INA– 2
VDD
7
V
IN– 2
VIND
VIND
VSS
–
+
VIN
+
VINA
VINA
+
VIN
+
3
4
6 VOUT
3
4
6 VINB
–
+
3
4
6 VOUT
VSS
VDD
VSS
VSS
5
5
5
NC
VINB
NC
VINB
+
–
VINC
VINC
+
–
MCP601
SOT23-5
MCP601R
SOT23-5
MCP603
SOT23-6
VINB
VOUTB
8
VOUTC
VOUT
VSS
VOUT
VDD
VOUT
VSS
1
2
3
VDD
1
VSS
1
VDD
6
5
5
2
3
2
3
5 CS
4 VIN
VIN
+
VIN
+
VIN+
4 VIN
–
4 VIN
–
–
© 2007 Microchip Technology Inc.
DS21314G-page 1
MCP601/1R/2/3/4
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Input Pins .....................................................±2 mA
Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Difference Input Voltage ...................................... |VDD – VSS
|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD Protection On All Pins (HBM; MM) .............. ≥ 3 kV; 200V
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters
Input Offset
Sym
Min
Typ
Max
Units
Conditions
Input Offset Voltage
VOS
VOS
-2
-3
±0.7
±1
+2
+3
mV
Industrial Temperature
Extended Temperature
Input Offset Temperature Drift
Power Supply Rejection
Input Current and Impedance
Input Bias Current
mV TA = -40°C to +85°C (Note 1)
mV TA = -40°C to +125°C (Note 1)
µV/°C TA = -40°C to +125°C
VOS
-4.5
—
±1
+4.5
—
ΔVOS/ΔTA
PSRR
±2.5
88
80
—
dB
VDD = 2.7V to 5.5V
IB
IB
—
—
—
—
—
1
—
60
pA
Industrial Temperature
Extended Temperature
Input Offset Current
20
pA TA = +85°C (Note 1)
pA TA = +125°C (Note 1)
pA
IB
450
±1
1013||6
1013||3
5000
—
IOS
ZCM
Common Mode Input Impedance
—
Ω||pF
Differential Input Impedance
ZDIFF
—
—
Ω||pF
Common Mode
Common Mode Input Range
Common Mode Rejection Ratio
Open-loop Gain
VCMR
VSS – 0.3
75
—
VDD – 1.2
—
V
CMRR
90
dB VDD = 5.0V, VCM = -0.3V to 3.8V
DC Open-loop Gain (large signal)
AOL
AOL
100
95
115
110
—
—
dB RL = 25 kΩ to VL,
V
OUT = 0.1V to VDD – 0.1V
dB RL = 5 kΩ to VL,
V
OUT = 0.1V to VDD – 0.1V
Output
Maximum Output Voltage Swing
VOL, VOH VSS + 15
OL, VOH VSS + 45
—
—
VDD – 20
VDD – 60
mV RL = 25 kΩ to VL, Output overdrive = 0.5V
mV RL = 5 kΩ to VL, Output overdrive = 0.5V
V
Linear Output Voltage Swing
Output Short Circuit Current
VOUT
VOUT
ISC
VSS + 100
VSS + 100
—
—
VDD – 100 mV RL = 25 kΩ to VL, AOL ≥ 100 dB
VDD – 100 mV RL = 5 kΩ to VL, AOL ≥ 95 dB
—
±22
±12
—
—
mA VDD = 5.5V
mA VDD = 2.7V
ISC
—
Power Supply
Supply Voltage
VDD
IQ
2.7
—
—
6.0
V
(Note 2)
Quiescent Current per Amplifier
230
325
µA IO = 0
Note 1: These specifications are not tested in either the SOT-23 or TSSOP packages with date codes older than YYWW = 0408.
In these cases, the minimum and maximum values are by design and characterization only.
2: All parts with date codes November 2007 and later have been screened to ensure operation at VDD=6.0V. However, the
other minimum and maximum specifications are measured at 1.4V and/or 5.5V.
DS21314G-page 2
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, CL = 50 pF, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Frequency Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
2.8
50
—
—
MHz
°
G = +1 V/V
Step Response
Slew Rate
SR
—
—
2.3
4.5
—
—
V/µs G = +1 V/V
µs G = +1 V/V, 3.8V step
Settling Time (0.01%)
Noise
tsettle
Input Noise Voltage
Input Noise Voltage Density
Eni
eni
eni
ini
—
—
—
—
7
—
—
—
—
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 kHz
29
21
0.6
nV/√Hz f = 10 kHz
fA/√Hz f = 1 kHz
Input Noise Current Density
MCP603 CHIP SELECT (CS) CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, CL = 50 pF, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
CS Input Current, Low
VIL
VSS
-1.0
—
—
0.2 VDD
—
V
ICSL
µA
CS = 0.2VDD
CS High Specifications
CS Logic Threshold, High
CS Input Current, High
VIH
0.8 VDD
—
—
0.7
-0.7
1
VDD
2.0
—
V
ICSH
µA
µA
nA
CS = VDD
CS = VDD
Shutdown VSS current
IQ_SHDN
IO_SHDN
-2.0
—
Amplifier Output Leakage in Shutdown
Timing
—
CS Low to Amplifier Output Turn-on Time
CS High to Amplifier Output High-Z Time
Hysteresis
tON
tOFF
—
—
—
3.1
100
0.4
10
—
—
µs
ns
V
CS ≤ 0.2VDD, G = +1 V/V
CS ≥ 0.8VDD, G = +1 V/V, No load.
VDD = 5.0V
VHYST
CS
tON
tOFF
VOUT
Hi-Z
Output Active
Hi-Z
2 nA
(typical)
IDD
230 µA
(typical)
-230 µA
(typical)
ISS
-700 nA
(typical)
2 nA
(typical)
CS
Current
700 nA
(typical)
FIGURE 1-1:
MCP603 Chip Select (CS)
Timing Diagram.
© 2007 Microchip Technology Inc.
DS21314G-page 3
MCP601/1R/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
TA
TA
TA
TA
-40
-40
-40
-65
—
—
—
—
+85
°C
°C
°C
°C
Industrial temperature parts
Extended temperature parts
Note
+125
+125
+150
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT23
Thermal Resistance, 6L-SOT23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-TSSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
—
—
—
—
—
—
—
—
256
230
85
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
163
124
70
120
100
Note:
The Industrial temperature parts operate over this extended range, but with reduced performance. The
Extended temperature specs do not apply to Industrial temperature parts. In any case, the internal Junction
temperature (TJ) must not exceed the absolute maximum specification of 150°C.
1.1
Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.5 “Supply Bypass”.
VDD
1 µF
0.1 µF
VIN
VOUT
RL
RN
RG
MCP60X
CL
RF
VDD/2
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
VDD
1 µF
0.1 µF
VDD/2
VOUT
RL
RN
RG
MCP60X
CL
RF
VIN
VL
FIGURE 1-3:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
DS21314G-page 4
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
120
100
80
0
300
250
200
150
100
50
IO = 0
-30
Phase
-60
Gain
60
-90
40
-120
-150
-180
-210
-240
20
TA
TA
TA
=
=
=
-40°C
+25°C
+85°C
0
-20
TA = +125°C
-40
0
0.1
1
10 100 1k 10k 100k 1M 10M
1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
01 00 01 02 03 04 05 06 07
Frequency (Hz)
FIGURE 2-1:
Open-Loop Gain, Phase vs.
FIGURE 2-4:
Quiescent Current vs.
Frequency.
Supply Voltage.
300
250
200
150
100
50
3.5
3.0
2.5
2.0
1.5
1.0
0.5
IO = 0
VDD = 5.0V
Falling Edge
VDD = 5.5V
Rising Edge
VDD = 2.7V
0.0
-50
0
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-2:
Slew Rate vs. Temperature.
FIGURE 2-5:
Quiescent Current vs.
Temperature.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
110
100
90
80
70
1.E+104µ
GBWP
1µ
1.E+03
60
50
PM, G = +1
40
30
20
10
0
100n
1.E+02
10n
1.E+01
0.1
1
10
100
1k
10k 100k 1M
-50 -25
0
25
50
75 100 125
1.E- 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0
Ambient Temperature (°C)
01
0
1 Freq2uency3(Hz) 4
5
6
FIGURE 2-3:
Gain Bandwidth Product,
FIGURE 2-6:
Input Noise Voltage Density
Phase Margin vs. Temperature.
vs. Frequency.
© 2007 Microchip Technology Inc.
DS21314G-page 5
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
16%
14%
12%
10%
8%
18%
16%
14%
12%
10%
8%
1200 Samples
A = –40 to +125°C
1200 Samples
T
6%
6%
4%
4%
2%
2%
0%
0%
-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0
Input Offset Voltage (mV)
-10 -8 -6 -4 -2
0
2
4
6
8
10
Input Offset Voltage Drift (µV/°C)
FIGURE 2-7:
Input Offset Voltage.
FIGURE 2-10:
Input Offset Voltage Drift.
0.5
0.4
100
95
90
85
80
75
VDD = 5.5V
VDD = 2.7V
0.3
0.2
0.1
PSRR
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
CMRR
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
CMRR, PSRR vs.
Temperature.
Temperature.
800
800
VDD = 2.7V
VDD = 5.5V
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
TA = –40°C
TA = +25°C
TA = +85°C
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
TA = +125°C
-100
-200
-100
-200
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Input Offset Voltage vs.
Common Mode Input Voltage with V = 2.7V.
Common Mode Input Voltage with V = 5.5V.
DD
DD
DS21314G-page 6
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
150
140
130
120
110
100
90
100
90
80
70
60
50
40
30
20
10
No Load
Input Referred
PSRR+
PSRR–
CMRR
VDD = 5.0V
10
1
100
1k
10k
100k
1M
1k
10k
1.E+04
100k
1.E+05
Frequency (Hz)
1M
1.E+06
1.E+03
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
FIGURE 2-13:
Channel-to-Channel
FIGURE 2-16:
CMRR, PSRR vs.
Separation vs. Frequency.
Frequency.
1000
1000
VDD = 5.5V
IB, +125°C
VCM = 4.3V
VDD = 5.5V
max. VCMR ≥ 4.3V
100
100
10
1
IB, +85°C
IOS, +125°C
IB
IOS
10
1
IOS, +85°C
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias Current, Input
FIGURE 2-17:
Input Bias Current, Input
Offset Current vs. Ambient Temperature.
Offset Current vs. Common Mode Input Voltage.
120
120
RL = 25 kΩ
VDD = 5.5V
VDD = 2.7V
110
100
90
110
100
90
80
80
100
1k
10k
100k
1.E+02
1.E+03
1.E+04
1.E+05
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power Supply Voltage (V)
Load Resistance (Ω)
FIGURE 2-15:
DC Open-Loop Gain vs.
FIGURE 2-18:
DC Open-Loop Gain vs.
Load Resistance.
Supply Voltage.
© 2007 Microchip Technology Inc.
DS21314G-page 7
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
90
130
120
110
100
90
VDD = 5.0V
RL = 25 kΩ
GBWP
VDD = 5.5V
80
70
PM, G = +1 60
RL = 5 kΩ
50
40
30
VDD = 2.7V
80
-50
-25
0
25
50
75
100
125
100
1k
1.E+03
Load Resistance (Ω)
10k
100k
1.E+02
1.E+04
1.E+05
Ambient Temperature (°C)
FIGURE 2-19:
Gain Bandwidth Product,
FIGURE 2-22:
DC Open-Loop Gain vs.
Phase Margin vs. Load Resistance.
Temperature.
1,000
1000
VDD = 5.5V
RL tied to VDD/2
RL = 5 kΩ
100
100
10
1
VDD – VOH
VDD – VOH
VOL – VSS
10
RL = 25 kΩ
VOL – VSS
1
-50
-25
0
25
50
75
100 125
0.01
0.1
1
10
Output Current Magnitude (mA)
Ambient Temperature (°C)
FIGURE 2-20:
Output Voltage Headroom
FIGURE 2-23:
Output Voltage Headroom
vs. Output Current.
vs. Temperature.
10
30
VDD = 5.5V
TA
TA
TA
=
=
=
–40°C
+25°C
+85°C
25
20
15
10
5
VDD = 2.7V
TA = +125°C
1
0
0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
10k
100k
Frequency (Hz)
1M
1.E+06
1.E+04
1.E+05
FIGURE 2-21:
Maximum Output Voltage
FIGURE 2-24:
Output Short-Circuit Current
Swing vs. Frequency.
vs. Supply Voltage.
DS21314G-page 8
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.0V
G = +1
VDD = 5.0V
G = –1
Time (1 µs/div)
Time (1 µs/div)
FIGURE 2-25:
Large Signal Non-Inverting
FIGURE 2-28:
Large Signal Inverting Pulse
Pulse Response.
Response.
VDD = 5.0V
G = –1
VDD = 5.0V
G = +1
Time (1 µs/div)
Time (1 µs/div)
FIGURE 2-26:
Small Signal Non-Inverting
FIGURE 2-29:
Small Signal Inverting Pulse
Pulse Response.
Response.
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
VDD = 5.5V
CS
-100
-200
-300
-400
-500
-600
-700
-800
VDD = 5.0V
G = +1
VIN = 2.5V
RL = 100 kΩ to GND
VOUT Active
VOUT High-Z
Time (5 µs/div)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
FIGURE 2-27:
(MCP603).
Chip Select Timing
FIGURE 2-30: Quiescent Current Through
V vs. Chip Select Voltage (MCP603).
SS
© 2007 Microchip Technology Inc.
DS21314G-page 9
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
6
0.8
VDD = +5.0V
G = +2
VDD = 5.5V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
5
4
3
2
VIN
VOUT
1
0
-1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Time (5 µs/div)
FIGURE 2-31:
Chip Select Pin Input
FIGURE 2-33:
The MCP601/1R/2/3/4
Current vs. Chip Select Voltage.
family of op amps shows no phase reversal
under input overdrive.
3.0
1.E1-00m2
VDD = 5.0V
1m
1.E-03
Amplifier On
2.5
1.E10-004µ
10µ
1.E-05
1µ
1.E-06
2.0
100n
1.5
1.0
0.5
0.0
CS Hi to Low
CS Low to Hi
1.E- 7
10n
1.E-08
1n
1.E-09
100p
1.E-10
+125°C
+85°C
+25°C
-40°C
10p
1.E-11
Amplifier Hi-Z
1p
1.E-12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Chip Select Voltage (V)
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-32:
Hysteresis of Chip Select’s
FIGURE 2-34:
Measured Input Current vs.
Internal Switch.
Input Voltage (below V ).
SS
DS21314G-page 10
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP601
MCP601R
MCP603
PDIP, SOIC,
Symbol
Description
PDIP, SOIC,
TSSOP
SOT-23-5
(Note 1)
SOT-23-5
SOT-23-6
TSSOP
6
2
3
7
4
1
4
3
5
2
1
4
3
2
5
6
2
3
7
4
6
2
3
7
4
VOUT
VIN–
VIN+
VDD
VSS
Analog Output
Inverting Input
Non-inverting Input
Positive Power Supply
Negative Power Supply
—
—
—
—
—
8
8
1
CS
NC
Chip Select
1, 5, 8
1, 5
No Internal Connection
Note 1: The MCP601R is only available in the 5-pin SOT-23 package.
TABLE 3-2:
MCP602
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP604
Symbol
Description
PDIP, SOIC,
TSSOP
PDIP, SOIC,
TSSOP
1
2
1
2
VOUTA
Analog Output (op amp A)
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Positive Power Supply
VINA
VINA
–
3
3
+
8
4
VDD
5
5
VINB
+
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Analog Output (op amp B)
Analog Output (op amp C)
Inverting Input (op amp C)
Non-inverting Input (op amp C)
Negative Power Supply
6
6
VINB
–
7
7
VOUTB
VOUTC
—
—
—
4
8
9
VINC
–
+
10
11
12
13
14
VINC
VSS
—
—
—
VIND
+
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Analog Output (op amp D)
VIND
–
VOUTD
3.1
Analog Outputs
3.4
Power Supply Pins
The op amp output pins are low-impedance voltage
sources.
The positive power supply pin (VDD) is 2.5V to 6.0V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD
.
3.2
Analog Inputs
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
The op amp non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3
Chip Select Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
© 2007 Microchip Technology Inc.
DS21314G-page 11
MCP601/1R/2/3/4
4.0
APPLICATIONS INFORMATION
VDD
The MCP601/1R/2/3/4 family of op amps are fabricated
on Microchip’s state-of-the-art CMOS process. They
are unity-gain stable and suitable for a wide range of
general purpose applications.
D1 D2
R1
V1
V2
MCP60X
4.1
Inputs
4.1.1
PHASE REVERSAL
R2
The MCP601/1R/2/3/4 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-34 shows the input voltage
exceeding the supply voltage without any phase
reversal.
R3
VSS – (minimum expected V1)
R1 >
R2 >
2 mA
VSS – (minimum expected V2)
2 mA
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
FIGURE 4-2:
Protecting the Analog
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
Inputs.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-34. Applications that are
high impedance may need to limit the useable voltage
range.
Bond
VDD
Pad
4.1.3
NORMAL OPERATION
Bond
Pad
Bond
Pad
Input
Stage
The Common Mode Input Voltage Range (VCMR
)
VIN+
VIN–
includes ground in single-supply systems (VSS), but
does not include VDD. This means that the amplifier
input behaves linearly as long as the Common Mode
Input Voltage (VCM) is kept within the specified VCMR
limits (VSS–0.3V to VDD–1.2V at +25°C).
Bond
Pad
VSS
Figure 4-3 shows a unity gain buffer. Since VOUT is the
same voltage as the inverting input, VOUT must be kept
below VDD–1.2V for correct operation.
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
VIN
+
VOUT
MCP60X
–
FIGURE 4-3:
Unity Gain Buffer has a
Range.
Limited V
OUT
DS21314G-page 12
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
4.2
Rail-to-Rail Output
RISO
There are two specifications that describe the output
swing capability of the MCP601/1R/2/3/4 family of op
amps. The first specification (Maximum Output Voltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load conditions. For
instance, the output voltage swings to within 15 mV of
the negative rail with a 25 kΩ load to VDD/2. Figure 2-33
shows how the output voltage is limited when the input
goes beyond the linear region of operation.
+
VOUT
MCP60X
–
CL
RG
RF
FIGURE 4-4:
Output resistor R
ISO
stabilizes large capacitive loads.
The second specification that describes the output
swing capability of these amplifiers is the Linear Output
Voltage Swing. This specification defines the maximum
output swing that can be achieved while the amplifier is
still operating in its linear region. To verify linear
operation in this range, the large signal (DC Open-Loop
Gain (AOL)) is measured at points 100 mV inside the
supply rails. The measurement must exceed the
specified gains in the specification table.
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN) in order to make
it easier to interpret the plot for arbitrary gains. GN is the
circuit’s noise gain. For non-inverting gains, GN and the
gain are equal. For inverting gains, GN = 1 + |Gain|
(e.g., -1 V/V gives GN = +2 V/V).
1k
4.3
MCP603 Chip Select
The MCP603 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to -0.7 µA (typ.), which is pulled through the CS pin to
VSS. When this happens, the amplifier output is put into
a high-impedance state. Pulling CS low enables the
amplifier.
100
GN = +1
GN ≥ +2
10
10p
100p
1n
10n
The CS pin has an internal 5 MΩ (typical) pull-down
resistor connected to VSS, so it will go low if the CS pin
is left floating. Figure 1-1 is the Chip Select timing
diagram and shows the output voltage, supply currents,
and CS current in response to a CS pulse. Figure 2-27
shows the measured output voltage response to a CS
pulse.
Normalized Load Capacitance;
CL / GN (F)
FIGURE 4-5:
for capacitive loads.
Recommended R
values
ISO
Once you have selected RISO for your circuit, double-
check the resulting frequency response peaking and
step response overshoot in your circuit. Evaluation on
the bench and simulations with the MCP601/1R/2/3/4
SPICE macro model are very helpful. Modify RISO’s
value until the response is reasonable.
4.4
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response.
4.5
Supply Bypass
With this family of op amps, the power supply pin (VDD
for single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-
frequency performance. It also needs a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
nearby analog parts.
When driving large capacitive loads with these op
amps (e.g., > 40 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
© 2007 Microchip Technology Inc.
DS21314G-page 13
MCP601/1R/2/3/4
2. Connect the guard ring to the non-inverting input
pin (VIN+) for inverting gain amplifiers and
transimpedance amplifiers (converts current to
voltage, such as photo detectors). This biases
the guard ring to the same reference voltage as
the op amp (e.g., VDD/2 or ground).
4.6
Unused Op Amps
An unused op amp in a quad package (MCP604)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
4.8
Typical Applications
4.8.1
ANALOG FILTERS
Figure 4-8 and Figure 4-9 show low-pass, second-
order, Butterworth filters with a cutoff frequency of
10 Hz. The filter in Figure 4-8 has a non-inverting gain
of +1 V/V, and the filter in Figure 4-9 has an inverting
gain of -1 V/V.
¼ MCP604 (A)
VDD
¼ MCP604 (B)
VDD
VDD
R1
R2
G = +1 V/V
fP = 10 Hz
C1
47 nF
VREF
R2
R1
641 kΩ
382 kΩ
R2
------------------
⋅
VIN
+
VREF = VDD
R1 + R2
C2
VOUT
MCP60X
22 nF
–
FIGURE 4-6:
Unused Op Amps.
4.7
PCB Surface Leakage
FIGURE 4-8:
Second-Order, Low-Pass
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference
would cause 5 pA of current to flow. This is greater
than the MCP601/1R/2/3/4 family’s bias current at
+25°C (1 pA, typical).
Sallen-Key Filter.
G = -1 V/V
fP = 10 Hz
R2
618 kΩ
R3
C1
8.2 nF
R1
1.00 MΩ
618 kΩ
VIN
VOUT
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
C2
47 nF
–
MCP60X
VDD/2
+
Guard Ring
VIN– VIN+
FIGURE 4-9:
Second-Order, Low-Pass
Multiple-Feedback Filter.
The MCP601/1R/2/3/4 family of op amps have low
input bias current, which allows the designer to select
larger resistor values and smaller capacitor values for
these filters. This helps produce a compact PCB layout.
These filters, and others, can be designed using
Microchip’s Design Aids; see Section 5.2 “FilterLab®
Software” and Section 5.3 “Mindi™ Simulatior
Tool”.
FIGURE 4-7:
Example Guard Ring layout.
1. Connect the guard ring to the inverting input pin
(VIN–) for non-inverting gain amplifiers, includ-
ing unity-gain buffers. This biases the guard ring
to the common mode input voltage.
DS21314G-page 14
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
4.8.2
INSTRUMENTATION AMPLIFIER
CIRCUITS
4.8.3
PHOTO DETECTION
The MCP601/1R/2/3/4 op amps can be used to easily
convert the signal from a sensor that produces an
output current (such as a photo diode) into a voltage (a
transimpedance amplifier). This is implemented with a
single resistor (R2) in the feedback loop of the
amplifiers shown in Figure 4-12 and Figure 4-13. The
optional capacitor (C2) sometimes provides stability for
these circuits.
Instrumentation amplifiers have a differential input that
subtracts one input voltage from another and rejects
common mode signals. These amplifiers also provide a
single-ended output voltage.
The three-op amp instrumentation amplifier is illustrated
in Figure 4-10. One advantage of this approach is unity-
gain operation, while one disadvantage is that the
common mode input range is reduced as R2/RG gets
larger.
A photodiode configured in the Photovoltaic mode has
zero voltage potential placed across it (Figure 4-12). In
this mode, the light sensitivity and linearity is
maximized, making it best suited for precision
applications. The key amplifier specifications for this
application are: low input bias current, low noise,
common mode input voltage range (including ground),
and rail-to-rail output.
V1
+
R3
R4
MCP60X
–
–
VOUT
MCP60X
R2
+
C2
R2
RG
R2
R3
R4
–
VOUT
ID1
VREF
MCP60X
VDD
–
+
V2
D1
Light
MCP60X
R4
-----
R3
2R2
⎛
⎞ ⎛
⎠ ⎝
⎞
⎠
VOUT = (V1 – V2) 1 + ---------
+ VREF
⎝
+
RG
VOUT = ID1 R2
FIGURE 4-10:
Three-Op Amp
Instrumentation Amplifier.
FIGURE 4-12:
Photovoltaic Mode Detector.
The two-op amp instrumentation amplifier is shown in
Figure 4-11. While its power consumption is lower than
the three-op amp version, its main drawbacks are that
the common mode range is reduced with higher gains
and it must be configured in gains of two or higher.
In contrast, a photodiode that is configured in the
Photoconductive mode has a reverse bias voltage
across the photo-sensing element (Figure 4-13). This
decreases the diode capacitance, which facilitates
high-speed operation (e.g., high-speed digital
communications). The design trade-off is increased
diode leakage current and linearity errors. The op amp
needs to have a wide Gain Bandwidth Product
(GBWP).
RG
VOUT
R1
R2
R2
R1
-
-
C2
R2
VREF
V2
MCP60X
+
MCP60X
+
ID1
VOUT
V1
VDD
–
R1 2R1
D1
⎛
⎞
VOUT = (V1 – V2) 1 + ----- + -------- + VREF
Light
MCP60X
⎝
⎠
R2 RG
+
VOUT = ID1 R2
VBIAS < 0V
VBIAS
FIGURE 4-11:
Two-Op Amp
Instrumentation Amplifier.
Both instrumentation amplifiers should use a bulk
bypass capacitor of at least 1 µF. The CMRR of these
amplifiers will be set by both the op amp CMRR and
resistor matching.
FIGURE 4-13:
Detector.
Photoconductive Mode
© 2007 Microchip Technology Inc.
DS21314G-page 15
MCP601/1R/2/3/4
5.5
Analog Demonstration and
Evaluation Boards
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP601/1R/2/3/4 family of op amps.
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
5.1
SPICE Macro Model
a
complete listing of these boards and their
The latest SPICE macro model for the MCP601/1R/2/
3/4 op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especially useful are:
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evalu-
ation Board
5.6
Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental
reference resources.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
5.3
Mindi™ Simulatior Tool
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
Microchip’s Mindi™ simulator tool aids in the design of
various circuits useful for active filter, amplifier and
power-management applications. It is a free online
simulation tool available from the Microchip web site at
www.microchip.com/mindi. This interactive simulator
enables designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
simulation tool can be downloaded to a personal
computer or workstation.
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
5.4
MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparasion
reports. Helpful links are also provided for Datasheets,
Purchase, and Sampling of Microchip parts.
DS21314G-page 16
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
Example:
5-Lead SOT-23 (MCP601 and MCP601R only)
I-Temp
E-Temp
Code
Device
Code
XXNN
SJ25
MCP601
SANN
SJNN
SLNN
MCP601R
SMNN
Example:
6-Lead SOT-23 (MCP603 only)
I-Temp
Code
E-Temp
Code
Device
XXNN
AU25
MCP603
AENN
AUNN
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS21314G-page 17
MCP601/1R/2/3/4
Package Marking Information (Continued)
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP601
I/P256
0722
MCP601
E/P 256
0722
e
3
OR
YYWW
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
MCP601
MCP601E
e
3
XXXXYYWW
I/SN0722
SN 0722
OR
NNN
256
256
Example:
8-Lead TSSOP
601
I722
256
XXXX
XYWW
NNN
DS21314G-page 18
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP604)
Example:
MCP604-I/P
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
0722256
MCP604
e
3
E/P
OR
0722256
14-Lead SOIC (150 mil) (MCP604)
Example:
MCP604ISL
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
0722256
MCP604
OR
E/SL^
e
3
0722256
Example:
14-Lead TSSOP (MCP604)
XXXXXXXX
YYWW
604E
0722
NNN
256
© 2007 Microchip Technology Inc.
DS21314G-page 19
MCP601/1R/2/3/4
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢏꢒꢖꢆꢗꢍꢏꢒꢁꢘꢙꢚ
ꢛꢔꢊꢃꢜ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
b
N
E
E1
3
2
1
e
e1
D
A2
c
A
φ
A1
L
L1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
0ꢅꢊꢋꢉ,ꢃꢍꢎꢒ
2
ꢅ
!
ꢗꢁ6!ꢉ"ꢜ#
3ꢐꢍꢇꢃꢋꢅꢉ0ꢅꢊꢋꢉ,ꢃꢍꢎꢒ
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑ
3'ꢅꢓꢊꢏꢏꢉ;ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ;ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
ꢅꢀ
ꢛ
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
0
ꢀꢁ6ꢗꢉ"ꢜ#
ꢗꢁ6ꢗ
ꢗꢁ96
ꢗꢁꢗꢗ
ꢘꢁꢘꢗ
ꢀꢁ:ꢗ
ꢘꢁꢙꢗ
ꢗꢁꢀꢗ
ꢗꢁ:!
ꢗꢞ
M
M
M
M
M
M
M
M
M
M
M
ꢀꢁ !
ꢀꢁ:ꢗ
ꢗꢁꢀ!
:ꢁꢘꢗ
ꢀꢁ9ꢗ
:ꢁꢀꢗ
ꢗꢁ<ꢗ
ꢗꢁ9ꢗ
:ꢗꢞ
0ꢀ
ꢀ
ꢎ
5
ꢗꢁꢗ9
ꢗꢁꢘꢗ
ꢗꢁꢘ<
ꢗꢁ!ꢀ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀꢘꢙꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ >ꢗ6ꢀ"
DS21314G-page 20
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕ !ꢖꢆꢗꢍꢏꢒꢁꢘꢙꢚ
ꢛꢔꢊꢃꢜ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
c
A
φ
A2
L
A1
L1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
<
ꢗꢁ6!ꢉ"ꢜ#
3ꢐꢍꢇꢃꢋꢅꢉ0ꢅꢊꢋꢉ,ꢃꢍꢎꢒ
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑ
3'ꢅꢓꢊꢏꢏꢉ;ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ;ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
ꢅꢀ
ꢛ
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
0
ꢀꢁ6ꢗꢉ"ꢜ#
ꢗꢁ6ꢗ
ꢗꢁ96
ꢗꢁꢗꢗ
ꢘꢁꢘꢗ
ꢀꢁ:ꢗ
ꢘꢁꢙꢗ
ꢗꢁꢀꢗ
ꢗꢁ:!
ꢗꢞ
M
M
M
M
M
M
M
M
M
M
M
ꢀꢁ !
ꢀꢁ:ꢗ
ꢗꢁꢀ!
:ꢁꢘꢗ
ꢀꢁ9ꢗ
:ꢁꢀꢗ
ꢗꢁ<ꢗ
ꢗꢁ9ꢗ
:ꢗꢞ
0ꢀ
ꢀ
ꢎ
5
ꢗꢁꢗ9
ꢗꢁꢘꢗ
ꢗꢁꢘ<
ꢗꢁ!ꢀ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀꢘꢙꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ >ꢗꢘ9"
© 2007 Microchip Technology Inc.
DS21314G-page 21
MCP601/1R/2/3/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ$ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆꢙ&&ꢆꢎꢋꢈꢆ'ꢔꢅ(ꢆꢗꢇ#$ꢇꢚ
ꢛꢔꢊꢃꢜ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
A1
c
e
eB
b1
b
.ꢆꢃꢍꢇ
/2#7ꢌꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
9
ꢁꢀꢗꢗꢉ"ꢜ#
M
ꢁꢀ:ꢗ
M
ꢁ:ꢀꢗ
ꢁꢘ!ꢗ
ꢁ:<!
ꢁꢀ:ꢗ
ꢁꢗꢀꢗ
ꢁꢗ<ꢗ
ꢁꢗꢀ9
M
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
%ꢈꢔꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
"ꢊꢇꢅꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
ꢜꢒꢈꢐꢏꢋꢅꢓꢉꢍꢈꢉꢜꢒꢈꢐꢏꢋꢅꢓꢉ;ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ;ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
2
ꢅ
ꢛ
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
0
ꢎ
5ꢀ
5
ꢅ"
M
ꢁꢘꢀꢗ
ꢁꢀ6!
M
ꢁꢀꢀ!
ꢁꢗꢀ!
ꢁꢘ6ꢗ
ꢁꢘ ꢗ
ꢁ: 9
ꢁꢀꢀ!
ꢁꢗꢗ9
ꢁꢗ ꢗ
ꢁꢗꢀ
M
ꢁ:ꢘ!
ꢁꢘ9ꢗ
ꢁ ꢗꢗ
ꢁꢀ!ꢗ
ꢁꢗꢀ!
ꢁꢗꢙꢗ
ꢁꢗꢘꢘ
ꢁ :ꢗ
%ꢃꢔꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
.ꢔꢔꢅꢓꢉ0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
0ꢈ(ꢅꢓꢉ0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ1ꢈ(ꢉꢜꢔꢊꢎꢃꢆꢚꢉꢉꢟ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢟꢉꢜꢃꢚꢆꢃꢑꢃꢎꢊꢆꢍꢉ#ꢒꢊꢓꢊꢎꢍꢅꢓꢃꢇꢍꢃꢎꢁ
:ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢁꢗꢀꢗ@ꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ꢉ"ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ >ꢗꢀ9"
DS21314G-page 22
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢛꢖꢆMꢆꢛꢄꢓꢓꢔ)*ꢆꢙ+,&ꢆꢎꢎꢆ'ꢔꢅ(ꢆꢗꢍꢏ$ ꢚ
ꢛꢔꢊꢃꢜ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
c
φ
A2
A
L
A1
L1
β
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
9
ꢀꢁꢘꢙꢉ"ꢜ#
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢛ
M
ꢀꢁꢘ!
ꢗꢁꢀꢗ
M
M
M
ꢀꢁꢙ!
M
ꢗꢁꢘ!
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉꢉ
ꢛꢘ
ꢛꢀ
ꢌ
ꢟ
3'ꢅꢓꢊꢏꢏꢉ;ꢃꢋꢍꢒ
<ꢁꢗꢗꢉ"ꢜ#
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ;ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
#ꢒꢊꢄꢑꢅꢓꢉAꢈꢔꢍꢃꢈꢆꢊꢏB
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
ꢌꢀ
ꢂ
ꢒ
:ꢁ6ꢗꢉ"ꢜ#
ꢁ6ꢗꢉ"ꢜ#
ꢗꢁꢘ!
ꢗꢁ ꢗ
M
M
ꢗꢁ!ꢗ
ꢀꢁꢘꢙ
0
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢉꢂꢓꢊꢑꢍꢉꢛꢆꢚꢏꢅꢉ%ꢈꢔ
ꢕꢈꢏꢋꢉꢂꢓꢊꢑꢍꢉꢛꢆꢚꢏꢅꢉ"ꢈꢍꢍꢈꢄ
0ꢀ
ꢀ
ꢀꢁꢗ ꢉ1ꢌ)
ꢗꢞ
ꢗꢁꢀꢙ
ꢗꢁ:ꢀ
!ꢞ
M
M
M
M
M
9ꢞ
ꢎ
5
ꢁ
ꢗꢁꢘ!
ꢗꢁ!ꢀ
ꢀ!ꢞ
ꢂ
!ꢞ
ꢀ!ꢞ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢟꢉꢜꢃꢚꢆꢃꢑꢃꢎꢊꢆꢍꢉ#ꢒꢊꢓꢊꢎꢍꢅꢓꢃꢇꢍꢃꢎꢁ
:ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀ!ꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
1ꢌ)$ 1ꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆ+ꢉꢐꢇꢐꢊꢏꢏ&ꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅ+ꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏ&ꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ >ꢗ!ꢙ"
© 2007 Microchip Technology Inc.
DS21314G-page 23
MCP601/1R/2/3/4
"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢒ-ꢋꢑꢆꢍ-ꢓꢋꢑ.ꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢒꢖꢆMꢆ/+/ꢆꢎꢎꢆ'ꢔꢅ(ꢆꢗꢒꢍꢍꢏꢇꢚ
ꢛꢔꢊꢃꢜ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
D
N
E
E1
NOTE 1
1
2
b
e
c
φ
A
A2
A1
L
L1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
9
ꢗꢁ<!ꢉ"ꢜ#
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉ
ꢛ
M
ꢗꢁ9ꢗ
ꢗꢁꢗ!
M
ꢀꢁꢗꢗ
M
ꢀꢁꢘꢗ
ꢀꢁꢗ!
ꢗꢁꢀ!
ꢛꢘ
ꢛꢀ
ꢌ
3'ꢅꢓꢊꢏꢏꢉ;ꢃꢋꢍꢒ
<ꢁ ꢗꢉ"ꢜ#
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ;ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
ꢌꢀ
ꢂ
0
ꢁ:ꢗ
ꢘꢁ6ꢗ
ꢗꢁ !
ꢁ ꢗ
:ꢁꢗꢗ
ꢗꢁ<ꢗ
ꢁ!ꢗ
:ꢁꢀꢗ
ꢗꢁꢙ!
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
0ꢀ
ꢀ
ꢀꢁꢗꢗꢉ1ꢌ)
ꢗꢞ
ꢗꢁꢗ6
ꢗꢁꢀ6
M
M
M
9ꢞ
ꢎ
5
ꢗꢁꢘꢗ
ꢗꢁ:ꢗ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀ!ꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
:ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
1ꢌ)$ 1ꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆ+ꢉꢐꢇꢐꢊꢏꢏ&ꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅ+ꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏ&ꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ >ꢗ9<"
DS21314G-page 24
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
0/ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢐꢄꢈꢆ$ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆꢙ&&ꢆꢎꢋꢈꢆ'ꢔꢅ(ꢆꢗꢇ#$ꢇꢚ
ꢛꢔꢊꢃꢜ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
c
A1
b1
b
e
eB
.ꢆꢃꢍꢇ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
/2#7ꢌꢜ
23ꢕ
ꢀ
ꢁꢀꢗꢗꢉ"ꢜ#
M
ꢕ/2
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
ꢛ
%ꢈꢔꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
M
ꢁꢘꢀꢗ
ꢁꢀ6!
M
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
"ꢊꢇꢅꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
ꢜꢒꢈꢐꢏꢋꢅꢓꢉꢍꢈꢉꢜꢒꢈꢐꢏꢋꢅꢓꢉ;ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ;ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
%ꢃꢔꢉꢍꢈꢉꢜꢅꢊꢍꢃꢆꢚꢉ,ꢏꢊꢆꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
.ꢔꢔꢅꢓꢉ0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
0
ꢎ
5ꢀ
5
ꢅ"
ꢁꢀꢀ!
ꢁꢗꢀ!
ꢁꢘ6ꢗ
ꢁꢘ ꢗ
ꢁꢙ:!
ꢁꢀꢀ!
ꢁꢗꢗ9
ꢁꢗ !
ꢁꢗꢀ
M
ꢁꢀ:ꢗ
M
ꢁ:ꢀꢗ
ꢁꢘ!ꢗ
ꢁꢙ!ꢗ
ꢁꢀ:ꢗ
ꢁꢗꢀꢗ
ꢁꢗ<ꢗ
ꢁꢗꢀ9
M
ꢁ:ꢘ!
ꢁꢘ9ꢗ
ꢁꢙꢙ!
ꢁꢀ!ꢗ
ꢁꢗꢀ!
ꢁꢗꢙꢗ
ꢁꢗꢘꢘ
ꢁ :ꢗ
0ꢈ(ꢅꢓꢉ0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ1ꢈ(ꢉꢜꢔꢊꢎꢃꢆꢚꢉꢉꢟ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢟꢉꢜꢃꢚꢆꢃꢑꢃꢎꢊꢆꢍꢉ#ꢒꢊꢓꢊꢎꢍꢅꢓꢃꢇꢍꢃꢎꢁ
:ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢁꢗꢀꢗ@ꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ꢉ"ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ >ꢗꢗ!"
© 2007 Microchip Technology Inc.
DS21314G-page 25
MCP601/1R/2/3/4
0/ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢂꢖꢆMꢆꢛꢄꢓꢓꢔ)*ꢆꢙ+,&ꢆꢎꢎꢆ'ꢔꢅ(ꢆꢗꢍꢏ$ ꢚ
ꢛꢔꢊꢃꢜ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
D
N
E
E1
NOTE 1
1
2
3
e
h
b
α
h
c
φ
A2
A
L
A1
β
L1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
ꢀ
ꢀꢁꢘꢙꢉ"ꢜ#
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉꢉꢟ
ꢛ
M
ꢀꢁꢘ!
ꢗꢁꢀꢗ
M
M
M
ꢀꢁꢙ!
M
ꢗꢁꢘ!
ꢛꢘ
ꢛꢀ
ꢌ
3'ꢅꢓꢊꢏꢏꢉ;ꢃꢋꢍꢒ
<ꢁꢗꢗꢉ"ꢜ#
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ;ꢃꢋꢍꢒ
3'ꢅꢓꢊꢏꢏꢉ0ꢅꢆꢚꢍꢒ
#ꢒꢊꢄꢑꢅꢓꢉAꢈꢔꢍꢃꢈꢆꢊꢏB
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
ꢌꢀ
ꢂ
ꢒ
:ꢁ6ꢗꢉ"ꢜ#
9ꢁ<!ꢉ"ꢜ#
ꢗꢁꢘ!
ꢗꢁ ꢗ
M
M
ꢗꢁ!ꢗ
ꢀꢁꢘꢙ
0
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢉꢂꢓꢊꢑꢍꢉꢛꢆꢚꢏꢅꢉ%ꢈꢔ
ꢕꢈꢏꢋꢉꢂꢓꢊꢑꢍꢉꢛꢆꢚꢏꢅꢉ"ꢈꢍꢍꢈꢄ
0ꢀ
ꢀ
ꢀꢁꢗ ꢉ1ꢌ)
ꢗꢞ
ꢗꢁꢀꢙ
ꢗꢁ:ꢀ
!ꢞ
M
M
M
M
M
9ꢞ
ꢎ
5
ꢁ
ꢗꢁꢘ!
ꢗꢁ!ꢀ
ꢀ!ꢞ
ꢂ
!ꢞ
ꢀ!ꢞ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢟꢉꢜꢃꢚꢆꢃꢑꢃꢎꢊꢆꢍꢉ#ꢒꢊꢓꢊꢎꢍꢅꢓꢃꢇꢍꢃꢎꢁ
:ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀ!ꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
1ꢌ)$ 1ꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆ+ꢉꢐꢇꢐꢊꢏꢏ&ꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅ+ꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏ&ꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ >ꢗ<!"
DS21314G-page 26
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
0/ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢒ-ꢋꢑꢆꢍ-ꢓꢋꢑ.ꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢒꢖꢆMꢆ/+/ꢆꢎꢎꢆ'ꢔꢅ(ꢆꢗꢒꢍꢍꢏꢇꢚ
ꢛꢔꢊꢃꢜ )ꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎ*ꢊꢚꢅꢉꢋꢓꢊ(ꢃꢆꢚꢇ+ꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉ,ꢊꢎ*ꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔ$--(((ꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄ-ꢔꢊꢎ*ꢊꢚꢃꢆꢚ
D
N
E
E1
NOTE 1
1
2
e
b
c
φ
A2
A
A1
L
L1
.ꢆꢃꢍꢇ
ꢕ/00/ꢕꢌ%ꢌ1ꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉ0ꢃꢄꢃꢍꢇ
ꢕ/2
23ꢕ
ꢕꢛ4
2ꢐꢄ5ꢅꢓꢉꢈꢑꢉ,ꢃꢆꢇ
,ꢃꢍꢎꢒ
2
ꢅ
ꢀ
ꢗꢁ<!ꢉ"ꢜ#
3'ꢅꢓꢊꢏꢏꢉ7ꢅꢃꢚꢒꢍ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉ
3'ꢅꢓꢊꢏꢏꢉ;ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ;ꢃꢋꢍꢒ
ꢕꢈꢏꢋꢅꢋꢉ,ꢊꢎ*ꢊꢚꢅꢉ0ꢅꢆꢚꢍꢒ
)ꢈꢈꢍꢉ0ꢅꢆꢚꢍꢒ
ꢛ
M
ꢗꢁ9ꢗ
ꢗꢁꢗ!
M
ꢀꢁꢗꢗ
M
<ꢁ ꢗꢉ"ꢜ#
ꢁ ꢗ
!ꢁꢗꢗ
ꢗꢁ<ꢗ
ꢀꢁꢘꢗ
ꢀꢁꢗ!
ꢗꢁꢀ!
ꢛꢘ
ꢛꢀ
ꢌ
ꢌꢀ
ꢂ
ꢁ:ꢗ
ꢁ6ꢗ
ꢗꢁ !
ꢁ!ꢗ
!ꢁꢀꢗ
ꢗꢁꢙ!
0
)ꢈꢈꢍꢔꢓꢃꢆꢍ
)ꢈꢈꢍꢉꢛꢆꢚꢏꢅ
0ꢅꢊꢋꢉ%ꢒꢃꢎ*ꢆꢅꢇꢇ
0ꢅꢊꢋꢉ;ꢃꢋꢍꢒ
0ꢀ
ꢀ
ꢀꢁꢗꢗꢉ1ꢌ)
ꢗꢞ
ꢗꢁꢗ6
ꢗꢁꢀ6
M
M
M
9ꢞ
ꢎ
5
ꢗꢁꢘꢗ
ꢗꢁ:ꢗ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ ,ꢃꢆꢉꢀꢉ'ꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊ&ꢉ'ꢊꢓ&+ꢉ5ꢐꢍꢉꢄꢐꢇꢍꢉ5ꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉ(ꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀ!ꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
:ꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀ ꢁ!ꢕꢁ
"ꢜ#$ "ꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉ%ꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏ&ꢉꢅꢖꢊꢎꢍꢉ'ꢊꢏꢐꢅꢉꢇꢒꢈ(ꢆꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
1ꢌ)$ 1ꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆ+ꢉꢐꢇꢐꢊꢏꢏ&ꢉ(ꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅ+ꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏ&ꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ %ꢅꢎꢒꢆꢈꢏꢈꢚ& ꢂꢓꢊ(ꢃꢆꢚ #ꢗ >ꢗ9ꢙ"
© 2007 Microchip Technology Inc.
DS21314G-page 27
MCP601/1R/2/3/4
NOTES:
DS21314G-page 28
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
APPENDIX A: REVISION HISTORY
Revision G (December 2007)
• Updated Figure 2-15 and Figure 2-19.
• Updated Table 3-1 and Table 3-2.
• Updated notes to Section 1.0 “Electrical
Characteristics”.
• Expanded Analog Input Absolute Maximum
Voltage Range (applies retroactively).
• Expanded operating VDD to a maximum of 6.0V.
• Added Figure 2-34.
• Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current Lim-
its”, and Section 4.1.3 “Normal Operation”.
• Corrected Section 6.0 “Packaging Informa-
tion”.
Revision F (February 2004)
• Undocumented changes.
Revision E (September 2003)
• Undocumented changes.
Revision D (April 2000)
• Undocumented changes.
Revision C (July 1999)
• Undocumented changes.
Revision B (June 1999)
• Undocumented changes.
Revision A (March 1999)
• Original Release of this Document.
© 2007 Microchip Technology Inc.
DS21314G-page 29
MCP601/1R/2/3/4
NOTES:
DS21314G-page 30
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
–X
/XX
a)
b)
c)
MCP601-I/P:
Single Op Amp,
Industrial Temperature,
8 lead PDIP package.
Temperature
Range
Package
MCP601-E/SN: Single Op Amp,
Extended Temperature,
8 lead SOIC package.
MCP601T-E/ST: Tape and Reel,
Device
MCP601
Single Op Amp
MCP601T Single Op Amp
(Tape and Reel for SOT-23, SOIC and TSSOP)
MCP601RT Single Op Amp
(Tape and Reel for SOT-23-5)
Dual Op Amp
MCP602T Dual Op Amp
(Tape and Reel for SOIC and TSSOP)
Single Op Amp with Chip Select
MCP603T Single Op Amp with Chip Select
(Tape and Reel for SOT-23, SOIC and TSSOP)
Quad Op Amp
MCP604T Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
Extended Temperature,
Single Op Amp,
8 lead TSSOP package
d)
e)
MCP601RT-I/OT:Tape and Reel,
MCP602
Industrial Temperature,
Single Op Amp, Rotated
5 lead SOT-23 package.
MCP603
MCP601RT-E/OT:Tape and Reel,
Extended Temperature,
Single Op Amp, Rotated,
5 lead SOT-23 package.
MCP604
a)
b)
c)
MCP602-I/SN: Dual Op Amp,
Industrial Temperature,
8 lead SOIC package.
Dual Op Amp,
Extended Temperature,
8 lead PDIP package.
Temperature Range
Package
I
E
= -40° C to +85° C
= -40° C to +125° C
MCP602-E/P:
MCP602T-E/ST: Tape and Reel,
Extended Temperature,
OT
CH
P
SN
SL
ST
=
=
=
=
=
=
Plastic SOT-23, 5-lead (MCP601 only)
Plastic SOT-23, 6-lead (MCP603 only)
Plastic DIP (300 mil body), 8, 14 lead
Plastic SOIC (3.90 mm body), 8 lead
Plastic SOIC (3.90 mm body), 14 lead
Plastic TSSOP (4.4 mm body), 8, 14 lead
Dual Op Amp,
8 lead TSSOP package.
a)
b)
c)
MCP603-I/SN: Industrial Temperature,
Single Op Amp with Chip
Select, 8 lead SOIC package.
Extended Temperature,
Single Op Amp with Chip
Select, 8 lead PDIP package.
MCP603-E/P:
MCP603T-E/ST: Tape and Reel,
Extended Temperature,
Single Op Amp with Chip
Select 8 lead TSSOP package.
MCP603T-I/SN: Tape and Reel,
d)
Industrial Temperature,
Single Op Amp with Chip
Select, 8 lead SOIC package.
a)
b)
c)
MCP604-I/P:
Industrial Temperature,
Quad Op Amp,
14 lead PDIP package.
MCP604-E/SL: Extended Temperature,
Quad Op Amp,
14 lead SOIC package.
MCP604T-E/ST: Tape and Reel,
Extended Temperature,
Quad Op Amp,
14 lead TSSOP package.
© 2007 Microchip Technology Inc.
DS21314G-page 31
MCP601/1R/2/3/4
NOTES:
DS21314G-page 32
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
DS21314G-page 33
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
10/05/07
DS21314G-page 34
© 2007 Microchip Technology Inc.
相关型号：
MCP604-I/ST
QUAD OP-AMP, 2000 uV OFFSET-MAX, 2.8 MHz BAND WIDTH, PDSO14, PLASTIC, TSSOP-14
MICROCHIP
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