MCP6041T-I/SNG [MICROCHIP]
暂无描述;
MICROCHIP 
MCP6041/2/3/4
M
600 nA, Rail-to-Rail Input/Output Op Amps
Features
Description
• Low Quiescent Current: 600 nA/Amplifier (typ)
The MCP6041/2/3/4 family of operational amplifiers
from Microchip Technology, Inc. operate with a single
supply voltage as low as 1.4 V, while drawing less than
1 µA (max) of quiescent current per amplifier. These
devices are also designed to support rail-to-rail input
and output operation. This combination of features sup-
ports battery-powered and portable applications.
The MCP6041/2/3/4 amplifiers have a typical gain
bandwidth product of 14 kHz (typ) and are unity gain
stable. These specs make these operational amplifiers
appropriate for low frequency applications, such as
battery current monitoring and sensor conditioning.
The MCP6041/2/3/4 family operational amplifiers are
offered in single (MCP6041), single with a Chip Select
(CS) feature (MCP6043), dual (MCP6042) and quad
(MCP6044) configurations. The MCP6041 device is
available in the 5-lead SOT-23 package.
• Rail-to-Rail Input: -0.3 V to V +0.3 V (max)
DD
• Rail-to-Rail Output:
V
+10 mV to V -10 mV (max)
DD
SS
• Gain Bandwidth Product: 14 kHz (typ)
• Wide Supply Voltage Range: 1.4 V to 5.5 V (max)
• Unity Gain Stable
• Available in Single, Dual and Quad
• Chip Select (CS) with MCP6043
• 5-lead SOT-23 package (MCP6041 only)
Applications
• Toll Booth Tags
• Wearable Products
• Temperature Measurement
• Battery Powered
Typical Application
Available Tools
V
DD
• Spice macro models (at www.microchip.com)
V
DD
®
• FilterLab Software (at www.microchip.com)
I
Package Types
DD
10
Ω
MCP604X
MCP6041
MCP6042
+2.5 V
to
V
SS
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
100 k
Ω
NC
VDD
1
2
3
4
5.5 V
8 NC
1
2
3
4
8
7
6
5
OUTA
A
-IN
+IN
VSS
-
+
-
OUTB
-INB
7
+
VDD
6 OUT
NC
-INA
+INA
VSS
1 M
High Side Battery Current Sensor
Ω
B
-
+
+INB
5
MCP6041
SOT-23-5
MCP6044
PDIP, SOIC, TSSOP
1
2
3
4
OUTD
14
13 -IND
OUTA
VDD
5
1
2
OUT
VSS
A
D
-
-
+
-INA1
+INA1
VDD
+
+IND
12
-
V
+INC
-INC
11
10
9
SS
-IN
4
+IN
3
+INB
-INB
OUTB1
5
6
7
-
-
+
+
C
B
8
OUTC
MCP6043
PDIP, SOIC, MSOP
NC
1
2
3
4
CS
8
7
6
5
-
+
VDD
OUT
NC
-IN
+IN
VSS
2002 Microchip Technology Inc.
DS21669B-page 1
MCP6041/2/3/4
1.0
ELECTRICAL
PIN FUNCTION TABLE
CHARACTERISTICS
Name
Function
+IN/+INA/+INB/+INC/+IND
-IN/-INA/-INB/-INC/-IND
VDD
VSS
Non-inverting Inputs
Inverting Inputs
Positive Power Supply
Negative Power Supply
1.1
Maximum Ratings*
VDD - VSS ......................................................................................7.0 V
All inputs and outputs................................... VSS –0.3 V to VDD +0.3 V
Difference Input voltage ..................................................... |VDD - VSS
|
Output Short Circuit Current ...............................................continuous
Current at Input Pins ..................................................................±2 mA
Current at Output and Supply Pins ..........................................±30 mA
Storage temperature ...................................................-65°C to +150°C
Ambient temp. with power applied ..............................-55°C to +125°C
ESD protection on all pins (HBM).....................................................≥ 4 kV
OUT/OUTA/OUTB/OUTC/OUTD Outputs
CS
Chip Select
No internal connection to
IC
NC
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
MCP6041/2/3/4 DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4 V to +5.5 V, VSS = GND, TA = 25 °C,
VCM = VDD/2, RL = 1 MΩ to VDD/2, and VOUT ~ VDD/2
Parameters
Sym
Min
Typ
Max
Units
Conditions
VCM = VSS
Input Offset:
Input Offset Voltage
Drift with Temperature
Power Supply Rejection
VOS
∆VOS/∆T
PSRR
-3.0
—
70
—
±1.5
85
+3.0
—
—
mV
µV/°C TA= -40°C to+85°C
dB
Input Bias Current and Impedance:
Input Bias Current
Input Bias Current Over Temperature
Input Offset Current
Common Mode Input Impedance
Differential Input Impedance
Common Mode:
IB
IB
IOS
ZCM
ZDIFF
—
—
—
—
—
1.0
—
1.0
1013||6
1013||6
—
100
—
—
—
pA
pA
pA
Ω||pF
Ω||pF
TA= -40°C to+85°
Common-Mode Input Range
Common-Mode Rejection Ratio
VCMR
CMRR
V
SS−0.3
62
—
80
V
DD+0.3
—
V
dB
VDD = 5 V,
CM = -0.3 V to 5.3 V
VDD = 5 V,
CM = 2.5 V to 5.3 V
VDD = 5 V,
CM = -0.3 V to 2.5 V
V
60
60
75
80
—
—
dB
dB
V
V
Open Loop Gain:
DC Open Loop Gain (large signal)
AOL
95
115
—
dB
RL = 50 kΩ to VDD/2,
100 mV < VOUT < (VDD
100 mV)
−
Output:
Maximum Output Voltage Swing
Linear Region Output Voltage Swing
VOL, VOH VSS + 10
—
—
VDD − 10
VDD − 100
mV
mV
RL = 50 kΩ to VDD/2
RL = 50 kΩ to VDD/2,
AOL ≥ 95 dB
VOVR
VSS + 100
Output Short Circuit Current
Power Supply:
Supply Voltage
IO
—
21
—
mA
VOUT = 2.5 V, VDD = 5 V
VDD
IQ
1.4
0.3
—
0.6
5.5
1.0
V
µA
Quiescent Current per amplifier
IO = 0
DS21669B-page 2
2002 Microchip Technology Inc.
MCP6041/2/3/4
MCP6041/2/3/4 AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +5 V, VSS = GND, TA = 25 °C,
VCM = VDD/2, RL = 1 MΩ to VDD/2, CL = 60 pF, and VOUT ~ VDD/2
Parameters
Gain Bandwidth Product
Slew Rate
Sym
GBWP
SR
PM
En
Min
—
—
—
—
Typ
14
3.0
65
5.0
170
0.6
Max
—
—
—
—
Units
kHz
V/ms
°
Conditions
Phase Margin
G = +1
Input Voltage Noise
Input Voltage Noise Density
Input Current Noise Density
µVp-p f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 kHz
fA/√Hz f = 1 kHz
en
in
—
—
—
—
SPECIFICATIONS FOR MCP6043 CHIP SELECT FEATURE
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4 V to +5.5 V, VSS = GND, TA = 25 °C,
VCM = VDD/2, RL = 1 MΩ to VDD/2, CL = 60 pF, and VOUT ~ VDD/2
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Low Specifications:
CS Logic Threshold, Low
CS Input Current, Low
VIL
VSS
—
—
VSS + 0.3
—
V
For entire VDD range
CS = VSS
ICSL
5.0
pA
CS High Specifications:
CS Logic Threshold, High
CS Input Current, High
VIH
ICSH
IQ
VDD - 0.3
—
5.0
20
VDD
—
V
For entire VDD range
CS = VDD
—
—
—
pA
pA
pA
CS Input High, GND Current
Amplifier Output Leakage, CS High
Dynamic Specifications:
—
CS = VDD
20
—
CS = VDD
CS Low to Amplifier Output High
Turn-on Time
tON
tOFF
—
—
—
2.0
10
50
—
—
ms
µs
V
CS low = VSS + 0.3 V, G = +1 V/V,
V
OUT = 0.9 VDD/2
CS high = VDD - 0.3 V, G = +1 V/V
OUT = 0.1 VDD/2
CS High to Amplifier Output High Z
Hysteresis
V
VHYST
0.6
VDD = 5 V
MCP6041/2/3/4 TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4 V to +5.5 V, VSS = GND
Parameters
Symbol
Min
Typ
Max
Units
Conditions
Temperature Ranges:
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+85
+125
+150
°C
°C
°C
Note 1
Thermal Package Resistances:
Thermal Resistance, 5L-SOT23
—
—
—
—
—
—
—
—
—
—
—
—
—
—
θJA
θJA
θJA
θJA
θJA
θJA
θJA
256
85
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
163
206
70
120
100
Note 1: The MCP6041/2/3/4 family of op amps operates over this extended range, but with reduced performance.
2002 Microchip Technology Inc.
DS21669B-page 3
MCP6041/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, V = +5 V, V = GND, T = 25°C, V
= V /2, R = 1 MΩ to V /2,
DD
SS
A
CM
DD
L
DD
C = 60 pF, and V
~ V /2.
DD
L
OUT
35%
30%
25%
20%
15%
10%
5%
35%
30%
25%
20%
15%
10%
5%
1196 Samples
1196 Samples
V
DD = 5.5V
V
DD = 1.4V
CM = VDD
VCM = VDD
V
0%
0%
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
Input Offset Voltage (mV)
Input Offset Voltage (mV)
FIGURE 2-1:
Histogram of Input Offset
FIGURE 2-4:
Histogram of Input Offset
Voltage with V = 5.5 V, V
= V
.
Voltage with V = 1.4 V, V
= V
.
DD
CM
DD
DD
CM
DD
35%
35%
1199 Samples
1199 Samples
V
DD = 5.5V
V
DD = 1.4V
30%
25%
20%
15%
10%
5%
30%
25%
20%
15%
10%
5%
VCM = VDD/2
VCM = VDD/2
0%
0%
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
Input Offset Voltage (mV)
Input Offset Voltage (mV)
FIGURE 2-2:
Histogram of Input Offset
FIGURE 2-5:
Histogram of Input Offset
Voltage with V = 5.5 V, V
= V /2.
Voltage with V = 1.4 V, V
= V /2.
CM DD
DD
CM
DD
DD
35%
35%
1199 Samples
1199 Samples
VDD = 5.5V
30%
V
DD = 1.4V
CM = VSS
30%
25%
20%
15%
10%
5%
VCM = VSS
V
25%
20%
15%
10%
5%
0%
0%
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
Input Offset Voltage (mV)
Input Offset Voltage (mV)
FIGURE 2-3:
Histogram of Input Offset
FIGURE 2-6:
Histogram of Input Offset
= V
Voltage with V = 5.5 V, V
= V
.
Voltage with V = 1.4 V, V
.
SS
DD
CM
SS
DD
CM
DS21669B-page 4
2002 Microchip Technology Inc.
MCP6041/2/3/4
Note: Unless otherwise indicated, V = +5 V, V = GND, T = 25°C, V
= V /2, R = 1 MΩ to V /2,
DD L DD
DD
SS
A
CM
C = 60 pF, and V
~ V /2.
DD
L
OUT
400
300
200
100
0
35%
30%
25%
20%
15%
10%
5%
VDD = 5.5V
1176 Samples
V
DD = 5.5V
VCM = VDD/2
TA = +85°C
TA = +25°C
TA = -40°C
-100
-200
-300
-400
TA = +85°C
TA = +25°C
TA = -40°C
0%
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Offset Voltage Drift (µV/°C)
Common Mode Input Voltage (V)
FIGURE 2-7:
Histogram of Input Offset
FIGURE 2-10:
Input Offset Voltage vs.
Voltage Drift with V = 5.5 V, V
= V /2.
Common Mode Input Voltage vs. Temperature
DD
CM
DD
with V = 5.5 V.
DD
35%
1000
VDD = 1.4V
1143 Samples
800
600
400
200
0
30%
25%
20%
15%
10%
5%
VDD = 5.5V
VCM = VSS
TA = +85°C
-200
-400
-600
TA = -40°C
TA = +25°C
TA = +85°C
-800
TA = +85°C
0.0
0%
-1000
-0.5
0.5
1.0
1.5
2.0
Input Offset Voltage Drift (µV/°C)
Common Mode Input Voltage (V)
FIGURE 2-8:
Histogram of Input Offset
FIGURE 2-11:
Input Offset Voltage vs.
Voltage Drift with V = 5.5 V, V
= V
.
Common Mode Input Voltage vs. Temperature
DD
CM
SS
with V = 1.4 V.
DD
35%
500
450
1124 Samples
Ω
RL = 50 k
V
DD = 1.4V
CM = VSS
30%
25%
20%
15%
10%
5%
V
VDD = 1.4V
400
350
300
250
VDD = 5.5V
0%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Offset Voltage Drift (µV/°C)
Output Voltage (V)
FIGURE 2-9:
Histogram of Input Offset
FIGURE 2-12:
Input Offset Voltage vs.
Voltage Drift with V = 1.4 V, V
= V
.
Output Voltage vs. Power Supply Voltage.
DD
CM
SS
2002 Microchip Technology Inc.
DS21669B-page 5
MCP6041/2/3/4
Note: Unless otherwise indicated, V = +5 V, V = GND, T = 25°C, V
= V /2, R = 1 MΩ to V /2,
DD L DD
DD
SS
A
CM
C = 60 pF, and V
~ V /2.
DD
L
OUT
300
250
200
150
100
50
1000
eni = 170 nV/Hz, f = 1 kHz
f = 1 kHz
VDD = 5V
Eni = 5.0 µVp-p,
f = 0.1 to 10 Hz
100
0
0.1
1
10
Frequency (Hz)
100
1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Noise Voltage Density
FIGURE 2-16:
Input Noise Voltage Density
vs. Frequency.
vs. Common Mode Input Voltage.
90
80
70
60
50
40
100
1182 Samples
V
DD = 5.0V
CM = VSS
95
90
85
80
75
70
V
PSRR-
PSRR+
PSRR
CMRR
CMRR
30
VDD = 5.0V
20
-40
-20
0
20
40
60
80
0.1
1
10
100
1000
Frequency (Hz)
Temperature (°C)
FIGURE 2-14:
Common Mode Rejection
FIGURE 2-17:
Common Mode Rejection
Ratio, Power Supply Rejection Ratio vs.
Frequency.
Ratio, Power Supply Rejection Ratio vs.
Temperature.
45
50
TA = 85°C
VDD = 5.5V
VCM = VDD
40
V
DD = 5.5V
40
30
20
10
0
35
30
25
20
Input Bias Current
Input Offset Current
Input Bias Current
Input Offset Current
15
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-40
-20
0
20
40
60
80
Common Mode Input Voltage (V)
Temperature ( °C)
FIGURE 2-15:
Input Bias, Offset Currents
FIGURE 2-18:
Input Bias, Offset Currents
vs. Common Mode Input Voltage with
Temperature = 85°C.
vs. Temperature.
DS21669B-page 6
2002 Microchip Technology Inc.
MCP6041/2/3/4
Note: Unless otherwise indicated, V = +5 V, V = GND, T = 25°C, V
= V /2, R = 1 MΩ to V /2,
DD L DD
DD
SS
A
CM
C = 60 pF, and V
~ V /2.
DD
L
OUT
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
TA = +85°C
VDD = 5.5V
TA = +25°C
TA = -40°C
VDD = 1.4V
-40
-20
0
20
40
60
80
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Power Supply Voltage, VDD (V)
Temperature (° C)
FIGURE 2-19:
Quiescent Current vs.
FIGURE 2-22:
Quiescent Current Vs.
Temperature vs. Power Supply Voltage.
Power Supply Voltage vs. Temperature.
130
140
0
VDD = 5.5V
Open Loop Gain
120
-30
-60
V
OUT = 0.5V to 5.0V
120
110
100
90
100
Open Loop Phase
80
60
40
20
-90
-120
-150
-180
-210
1.E+05 -240
VDD = 1.4V
OUT = 0.5V to 0.9V
V
80
0
70
VDD = 5.5V
-20 1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1. E+0
2
1. E+0
3
1. E+0
4
1. E+0 5
60
100
0.001 0.01 0.1
1
10
100
1k
10k 100k
1k
10k
100k
Ω
Frequency (Hz)
Load Resistance (
)
FIGURE 2-20:
Open Loop Gain, Phase vs.
FIGURE 2-23:
Open Loop Gain vs. Load
Frequency with V = 5.5 V.
Resistance vs. Power Supply Voltage.
DD
140
140
Ω
RL = 50 k
RL = 50 kΩ
VSS + 100 mV < VOUT < VDD - 100 mV
130
130
120
110
100
90
VDD = 5.5V
120
110
100
90
VDD = 1.4V
80
0.00
80
0.05
0.10
0.15
0.20
0.25
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power Supply Voltage, VDD (V)
Output Voltage Headroom, VDD-VOUT or VOUT-VSS (V)
FIGURE 2-21:
Supply Voltage.
Open Loop Gain vs. Power
FIGURE 2-24:
Open Loop Gain vs. Output
Voltage Headroom vs. Power Supply Voltage.
2002 Microchip Technology Inc.
DS21669B-page 7
MCP6041/2/3/4
Note: Unless otherwise indicated, V = +5 V, V = GND, T = 25°C, V
= V /2, R = 1 MΩ to V /2,
DD L DD
DD
SS
A
CM
C = 60 pF, and V
~ V /2.
DD
L
OUT
130
120
110
100
90
18
16
4
2
0
8
90
80
70
60
50
40
30
20
10
0
Phase Margin
Gain Bandwidth Product
6
80
4
VDD = 5V
RL = 100 k
70
2
Ω
Input Referred
G = +1 V/V
0
60
1.E+02
1.E+03
1.E+04
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
100
1k
10k
Common Mode Input Voltage(V)
Frequency (Hz)
FIGURE 2-25:
Channel to Channel
FIGURE 2-28:
Gain Bandwidth Product,
Separation vs. Frequency (MCP6042 and
MCP6044 only).
Phase Margin vs. Common Mode Input Voltage
with Unity Gain.
18
16
14
12
10
8
90
80
70
60
50
40
30
20
10
0
18
16
14
12
90
80
70
60
50
40
30
20
10
0
Phase Margin
Gain Bandwidth Product
Phase Margin
10
8
Gain Bandwidth Product
6
6
4
4
VDD = 5.5V
VDD = 1.4V
G = +1 V/V
2
2
G = +1 V/V
0
0
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature (°C)
Temperature (°C)
FIGURE 2-26:
Gain Bandwidth Product,
FIGURE 2-29:
Gain Bandwidth Product,
Phase Margin vs. Temperature with V = 5.5 V,
Phase Margin vs. Temperature with V = 1.4 V,
DD
DD
Unity Gain.
Unity Gain.
18
16
14
12
10
8
90
80
70
60
50
40
30
20
10
0
40
35
| ISC- | @ VDD=5.5V
30
ISC+ @ VDD=5.5V
25
20
Unity Loop Gain Frequency
15
6
| ISC- | @ VDD=1.4V
Phase Margin
ISC+ @ VDD=1.4V
10
4
VDD = 5.5V
G = +1 V/V
5
0
2
RL = 10 kΩ
0
-40
-20
0
20
40
60
80
10
100
Load Capacitance (pF)
1000
Temperature (°C)
FIGURE 2-27:
Unity Loop Gain Frequency,
FIGURE 2-30:
Output Short Circuit Current
Phase Margin vs. Load Capacitance.
vs. Temperature vs. Power Supply Voltage.
DS21669B-page 8
2002 Microchip Technology Inc.
MCP6041/2/3/4
Note: Unless otherwise indicated, V = +5 V, V = GND, T = 25°C, V
= V /2, R = 1 MΩ to V /2,
DD
SS
A
CM
DD
L
DD
C = 60 pF, and V
~ V /2.
DD
L
OUT
10
6
5
4
3
2
1
0
VDD = 5.0V
VDD = 5.5V
High-to-Low Transition
Low-to-High Transition
VDD = 1.4V
1
0.1
1.E+01
1.E+02
1.E+03
1.E+04
-40
-20
0
20
40
60
80
10
100
1k
10k
Temperature (°C)
Frequency (Hz)
FIGURE 2-31:
Slew Rate vs. Temperature.
FIGURE 2-34:
Output Voltage Swing vs.
Frequency vs. Power Supply Voltage.
100
5
VOL-VSS @ VDD = 5.5V
VDD-VOH @ VDD = 5.5V
VDD = 5.5V
Ω
RL = 50 k
4
3
2
1
0
VOL - VSS
10
VDD-VOH @ VDD = 1.4V
VOL-VSS @ VDD = 1.4V
VDD - VOH
1
1.E+03
1.E+04
1.E+05
1k
10k
Load Resistance (:)
100k
-40
-20
0
20
40
60
80
Temperature (°C)
FIGURE 2-32:
Output Voltage Headroom
FIGURE 2-35:
Output Voltage Headroom
vs. Load Resistance vs. Power Supply Voltage.
vs. Temperature.
3.E-02
0.025
VDD = 5.0V
2.E-02
VDD = 5.0V
0.020
G = +1 V/V
G = -1 V/V
Ω
RL = 50 k
2.E-02
0.015
RL = 50 kΩ
1.E-02
5.E-03
0.E+00
0.010
0.005
0.000
-5.E-03
-0.005
-1.E-02
-0.010
-2.E-02
-0.015
-2.E-02
-0.020
-3.
E-0
2
0.E+00
1.E-04
2.E-04
3.E-04
4.E-04
5.E-04
6.E-04
7.E-04
8.E-04
9.E-04
1.E-03
-0.
025
0.0E+00
1.0E-04
2.0E-04
3.0E-04
4.0E-04
5.0E-04
6.0E-04
7.0E-04
8.0E-04
9.0E-04
1.0E-03
Time (100 µs/div)
Time (100 µs/div)
FIGURE 2-33:
Pulse Response.
Small Signal Non-Inverting
FIGURE 2-36:
Small Signal Inverting Pulse
Response.
2002 Microchip Technology Inc.
DS21669B-page 9
MCP6041/2/3/4
Note: Unless otherwise indicated, V = +5 V, V = GND, T = 25°C, V
= V /2, R = 1 MΩ to V /2,
DD L DD
DD
SS
A
CM
C = 60 pF, and V
~ V /2.
DD
L
OUT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.0V
G = +1 V/V
RL = 50 kΩ
VDD = 5.0V
G = -1 V/V
R
L = 50 kΩ
0.E+00
1.E-03
2.E-03
3.E-03
4.E-03
5.E-03
6.E-03
7.E-03
8.E-03
9.E-03
1.E-02
0.E+00
1.E-03
2.E-03
3.E-03
4.E-03
5.E-03
6.E-03
7.E-03
8.E-03
9.E-03
1.E-02
Time (1 ms/div)
Time (1 ms/div)
FIGURE 2-37:
Large Signal Non-Inverting
FIGURE 2-40:
Large Signal Inverting Pulse
Pulse Response.
Response.
5.0
3.0
Amplifier Output–Active (driven)
VDD = 5.0V
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
CS
2.5
0.0
CS Input High
to Low
VDD = 5.0V
2.5
2.0
1.5
1.0
0.5
0.0
CS Input Low
to High
VOUT
-
-
Amplifier Output–Hi-Z
4
Output Driven
Output Hi-Z
Output Hi-Z
0
1
2
3
5
CS Input Voltage (V)
Time (1 ms/div)
FIGURE 2-38:
Chip Select (CS) to
FIGURE 2-41:
(MCP6043 only).
Chip Select (CS) Hysteresis
Amplifier Output Response Time (MCP6043
only).
6
VIN
5
VOUT
4
3
2
1
VDD = 5.0V
0
G = +2 V/V
-1 0.00E+00
5.00E-03
1.00E-0
2
1.50E-0
2
2.00E-02
2.50E-02
Time (5 ms/div)
FIGURE 2-39:
The MCP6041/2/3/4 family
shows no phase reversal (for information only–
the Maximum Absolute Input Voltage is still
V
-0.3 V and V +0.3 V).
DD
SS
DS21669B-page 10
2002 Microchip Technology Inc.
MCP6041/2/3/4
The second specification, Linear Region Output Volt-
age Swing, details the output voltage range that sup-
3.0
APPLICATIONS INFORMATION
The MCP6041/2/3/4 family of operational amplifiers
are fabricated on Microchip’s state-of-the-art CMOS
process. They are unity gain stable and suitable for a
wide range of applications requiring very low power
consumption. With these op amps, the power supply
pin needs to be by-passed with a 0.1 µF capacitor.
ports the specified Open Loop Gain (A ≥ 95 dB with
OL
R = 50 kΩ).
L
3.4
Input Voltage and Phase Reversal
The MCP6041/2/3/4 op amp family uses CMOS tran-
sistors at the input. It is designed to not exhibit phase
inversion when the input pins exceed the supply volt-
ages. Figure 2-39 shows an input voltage exceeding
both supplies with no resulting phase inversion.
3.1
Rail to Rail Input
The input stage of the family of devices uses two differ-
ential input stages in parallel; one operates at low V
CM
The maximum operating V
(common mode input
CM
(common mode input voltage) and the other at high
voltage) that can be applied to the inputs is V -0.3 V
SS
V
. With this topology, the MCP6041/2/3/4 family
CM
and V
+0.3 V. Voltage on the input that exceed this
DD
operates with V up to 300 mV past either supply rail.
CM
absolute maximum rating can cause excessive current
to flow in or out of the input pins. Current beyond ±2 mA
can cause possible reliability problems. Applications
that exceed this rating must be externally limited with
an input resistor as shown in Figure 3-1.
The Input Offset Voltage is measured at both
V
= V - 0.3 V and V
+ 0.3 V to ensure proper
DD
CM
SS
operation.
3.2
Output Loads and Battery Life
The MCP6041/2/3/4 op amp family has outstanding
quiescent current, which supports battery-powered
applications. There is minimal quiescent current glitch-
ing when chip select (CS) is raised or lowered. This
prevents excessive current draw and reduced battery
life, when the part is turned off or on.
V
R
MCP604X
OUT
IN
V
IN
Heavy resistive loads at the output can cause exces-
sive battery drain. Driving a DC voltage of 2.5 V across
a 100 kΩ load resistor will cause the supply current to
increase by 25 µA, depleting the battery 43 times as
(Maximum expected VIN) – VDD
RIN
RIN
≥
------------------------------------------------------------------------------
2 mA
V
SS – (Minimum expected VIN
)
fast as I (0.6 µA typ) alone.
≥
Q
---------------------------------------------------------------------------
2 mA
High frequency signals (fast edge rate) across capaci-
tive loads will also significantly increase supply current.
For instance, a 0.1 µF capacitor at the output presents
an AC impedance of 15.9 kΩ (1/2πfC) to a 100 Hz
sinewave. It can be shown that the average power
drawn from the battery by a 5.0 Vp-p sinewave
(1.77 Vrms), under these conditions, is:
FIGURE 3-1:
An input resistor, R ,
IN
should be used to limit excessive input current if
the inputs exceed the Absolute Maximum
specification.
3.5
Capacitive Load and Stability
EQUATION
Driving capacitive loads can cause stability problems
with voltage feedback op amps. A buffer configuration
(G = +1) is the most sensitive to capacitive loads.
Figure 2-27 shows how increasing the load capaci-
tance will decrease the phase margin. While a phase
margin above 60° is ideal, 45° is sufficient. As can be
PSUPPLY = (VDD – VSS)(IQ + VL(p – p)fCL)
= (5V)(0.6µA + 5.0Vp – p • 100Hz • 0.1µF)
= 3.0µW + 50µW
seen, up to C = 150 pF can be placed on the
This will drain the battery 18 times as fast as I alone.
L
Q
MCP6041/2/3/4 op amp outputs without any problems,
while 250 pF is usable with a 45° phase margin.
3.3
Rail to Rail Output
When the op amp is required to drive large capacitive
The output voltage range of the MCP6041/2/3/4 family
is specified two ways. The first specification, Maximum
Output Voltage Swing, defines the maximum swing
possible under a particular output load. According to
the spec table, the output can reach ≤ 10 mV of either
supply rail when R = 50 kΩ. See Figure 2-32 for infor-
mation on Maximum Output Voltage Swing vs. load
resistance.
loads (C >150 pF), a small series resistor (R
in
L
ISO
Figure 3-2) at the output of the amplifier improves the
phase margin. This resistor makes the output load
resistive at higher frequencies, which improves the
phase margin. The bandwidth reduction caused by the
capacitive load, however, is not changed. To select
L
R
, start with 1 kΩ, then use the MCP6041 SPICE
ISO
2002 Microchip Technology Inc.
DS21669B-page 11
MCP6041/2/3/4
macro model and bench testing to adjust R
until the
Surface leakage is caused by a difference in voltage
between traces, combined with high humidity, dust or
other contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces
ISO
frequency response peaking is reasonable. Use the
smallest reasonable value.
12
is 10 Ω. A 5 V difference would cause 5 pA of current
to flow; this is greater than the input current of the
MCP6041/2/3/4 family at 25°C (1 pA, typ).
The simplest technique to reduce surface leakage is
using a guard ring around sensitive pins (or traces).
The guard ring is biased at the same voltage as the
sensitive pin or trace. Figure 3-4 shows an example of
a typical layout.
R
ISO
V
MCP604X
OUT
V
IN
C
L
FIGURE 3-2:
Amplifier circuit for heavy
capacitive loads.
IN-
IN+
V
SS
3.6
The MCP6043 Chip Select (CS)
Option
The MCP6043 is a single amplifier with a chip select
(CS) option. When CS is pulled high, the supply current
drops to 20 pA (typ) and goes through the CS pin to
V
. When this happens, the amplifier is put into a high
SS
impedance state. By pulling CS low, the amplifier is
enabled. If the CS pin is left floating, the amplifier will
not operate properly. Figure 3-3 shows the output volt-
age and supply current response to a CS pulse.
Guard Ring
FIGURE 3-4:
layout.
Example of Guard Ring
Circuit schematics for different guard ring implementa-
tions are shown in Figure 3-5. Figure 3-5A biases the
guard ring to the input common mode voltage, which is
most effective for non-inverting gains, including unity
gain. Figure 3-5B biases the guard ring to a reference
CS
VIL
tON
VIH
tOFF
VOUT
Hi-Z
Hi-Z
voltage (V
, which can be ground). This is useful for
REF
inverting gains and precision photo sensing circuits.
0.6 µA, typ
0.6 µA, typ
Figure 3-5A
5 pA, typ
5 pA, typ
IVDD
V
DD
20 pA, typ
5 pA, typ
20 pA, typ
5 pA, typ
IVSS
MCP604X
V
REF
ICS
Figure 3-5B
FIGURE 3-3:
Timing Diagram for the CS
function on the MCP6043 op amp.
3.7 Layout Considerations
V
DD
Good PC board layout techniques will help you achieve
the performance shown in the specs and Typical Per-
formance Curves. It will also assist in minimizing Elec-
tro-Magnetic Compatibility (EMC) issues.
MCP604X
V
REF
3.7.1
SURFACE LEAKAGE
FIGURE 3-5:
Two possible guard ring
connection strategies to reduce surface leakage
effects.
In applications where low input bias current is critical,
PC board surface leakage effects and signal coupling
from trace to trace need to be considered.
DS21669B-page 12
2002 Microchip Technology Inc.
MCP6041/2/3/4
3.7.2
COMPONENT PLACEMENT
3.8
Typical Applications
BATTERY CURRENT SENSING
Separate digital from analog and low speed from high
speed. This helps prevent crosstalk.
3.8.1
The MCP6041/2/3/4 op amps’ Common Mode Input
Range, which goes 300 mV beyond both supply rails,
supports their use in high side and low side battery
current sensing applications. The very low quiescent
current (0.6 µA, typ) help prolong battery life while the
rail-to-rail output allows you to detect low currents.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
Use a 0.1 µF supply bypass capacitor within 0.1”
(2.5 mm) of the V pin. It must connect directly to the
DD
Figure 3-7 shows a high side battery current sensor cir-
ground plane.
cuit. The 10 Ω resistors are sized to minimize power
losses. The battery current (I ) through the 10 Ω
DD
3.7.3
SIGNAL COUPLING
resistor causes its top terminal to be more negative
The input pins of the MCP6041/2/3/4 family of op amps
are high impedance, which allows noise injection. This
noise can be capacitively or magnetically coupled. In
either case, using a ground plane helps reduce noise
injection.
than the bottom terminal. This keeps the common
mode input voltage of the op amp ≤ V , which is within
DD
its allowed range. The output of the op amp can reach
V
- 0.1 mV (see Figure 2-32), which is a smaller
DD
error than the offset voltage.
When noise is coupled capacitively, the ground plane
provides shunt capacitance to ground for high fre-
quency signals. Figure 3-6 shows the equivalent cir-
V
DD
V
DD
cuit. The coupled current, I , produces a lower voltage
M
(V
) on the victim trace when the trace to ground
TRACE 2
I
plane capacitance (C
) is large and the terminating
resistor (R ) is small. Increasing the distance between
DD
10
Ω
MCP604X
SH2
T2
+2.5 V
to
V
SS
traces, and using wider traces, also helps.
100 k
Ω
5.5 V
C
I
M
V
M
TRACE 2
1 M
Ω
V
TRACE 1
FIGURE 3-7:
High Side Battery Current
Sensor.
C
C
R
SH1
SH2
T2
3.8.2
INSTRUMENTATION AMPLIFIER
The MCP6041/2/3/4 op amp is well suited for condition-
ing sensor signals in battery-powered applications.
Figure 3-8 shows a two op amp instrumentation
amplifier, using the MCP6042, that works well for appli-
cations requiring rejection of common mode noise at
FIGURE 3-6:
Equivalent circuit for
capacitive coupling between traces on a PC
board (with ground plane).
When noise is coupled magnetically, ground plane
reduces the mutual inductance between traces. This
occurs because the ground return current at high fre-
quencies will follow a path directly beneath the signal
trace. Increasing the separation between traces makes
a significant difference. Changing the direction of one
of the traces can also reduce magnetic coupling.
If these techniques are not enough, it may help to place
guard traces next to the victim trace. They should be on
both sides of the victim trace and be as close as possi-
ble. Connect the guard traces to ground plane at both
ends, and in the middle, for long traces.
higher gains. The reference voltage (V
) is supplied
REF
by
a
low impedance source. In single supply
is typically V /2.
applications, V
REF
DD
R
G
V
R
R
R
R
V
OUT
REF
1
1
1
1
V
V
2
½
MCP6042
½ MCP6042
1
R1 2R1
VOUT = (V1 – V2) 1 + ----- + --------- + VREF
R2 RG
FIGURE 3-8:
Two Op Amp
Instrumentation Amplifier.
2002 Microchip Technology Inc.
DS21669B-page 13
MCP6041/2/3/4
4.0 SPICE MACRO MODEL
The Spice macro model for the MCP6041, MCP6042,
MCP6043 and MCP6044 simulates the typical ampli-
fier performance of: offset voltage, DC power supply
rejection, input capacitance, DC common mode rejec-
tion, open loop gain over frequency, phase margin, out-
put swing, DC power supply current, power supply
current change with supply voltage, input common
mode range, output voltage range vs. load and input
voltage noise.
The characteristics of the MCP6041, MCP6042,
MCP6043 and MCP6044 amplifiers are similar in terms
of performance and behavior. This single op amp
macro model supports all four devices with the excep-
tion of the chip select function of the MCP6043, which
is not modeled.
The listing for this macro model is shown on the next
page. The most recent revision of the model can be
downloaded from
www.microchip.com.
Microchip’s
web site at
DS21669B-page 14
2002 Microchip Technology Inc.
MCP6041/2/3/4
Software License Agreement
The software supplied herewith by Microchip Technology Incorporated (the “Company”) is intended and supplied to you, the Com-
pany’s customer, for use solely and exclusively on Microchip products.
The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved.
Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil
liability for the breach of the terms and conditions of this license.
THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATU-
TORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU-
LAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR
SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
.SUBCKT MCP6041 1 2 3 4 5
R11 10 12 78K
C11 11 12 4.9P
*
*
*
*
*
*
*
| | | | |
| | | | Output
| | | Negative Supply
| | Positive Supply
| Inverting Input
Non-inverting Input
C12
1
0 6P
E12 1 14 POLY(4) 20 0 21 0 26 0 27 0
1 1
G12 14 0 POLY(2) 22 0 23 0
M12 11 14 15 15 NMI
C13 14 2 3P
1M 1 1
1.5P 1U 1U
* Macromodel for the MCP6041/2/3/4 op amp
family:
M14 12 2 15 15 NMI
G14
C14
2
2
0 POLY(2) 24 0 25 0
0 6P
0.5P 1U 1U
*
*
*
MCP6041 (single)
MCP6042 (dual)
MCP6043 (single w/ CS; chip select is not
I15 15 4 500N
V16 16 4 0.18
D16 16 15 DL
modeled)
*
*
MCP6044 (quad)
V13 3 13 0.00
D13 14 13 DL
* Revision History:
*
*
*
REV A: 7-9-01 created KEB
* Noise Sources
I20 21 20 17.2N
D20 20 0 DN1
D21 0 21 DN1
I22 23 22 588U
D22 22 0 DN23
D23 0 23 DN23
I24 25 24 588U
D24 24 0 DN23
D25 0 25 DN23
*
* Recommendations:
Use PSPICE (other simulators may require
translation)
*
*
For a quick, effective design, use a com-
bination of: data sheet
*
with this macromodel
*
specs, bench testing, and simulations
For high impedance circuits, set
GMIN=100F in the.OPTIONS
*
*
statement
* PSRR and CMRR
G26 0 26 POLY(1) 3 4
R26 26 0 1
G27 0 27 POLY(2) 1 3 2 4
R27 27 0 1
110U -20U
-275U 50U 50U
* Supported:
*
(25 degrees C)
Typical performance at room temperature
*
*
DC, AC, Transient, and Noise analyses.
Most specs, including: offsets, PSRR,
*
* Open Loop Gain, Slew Rate
CMRR, input impedance,
G30 0 30 POLY(1) 12 11
R30 30 0 1
0 1MEG
*
open loop gain, voltage ranges, supply
current,..., etc.
*
* Not Supported:
C30 30 0 11.4
G31 0 31 POLY(1) 30 0
R31 31 0 1
0 1
*
*
Chip Select (MCP6043)
Variation in specs vs. Power Supply Volt-
C31 31 0 775N
*
age
*
*
* Output Stage
G40 0 40 POLY(1) 45 5
D41 40 41 DL
Distortion (detailed non-linear behavior)
Temperature analysis
0 22.7M
*
Process variation
R41 41 0 1K
*
Behavior outside normal operating region
D42 42 40 DL
*
R42 42 0 1K
* Input Stage
V10 3 10 -0.3
R10 10 11 78K
G43
G47
3
0
0 POLY(1) 41 0
4 POLY(1) 42 0
100N 1M
100N -1M
0 1
E43 43 0 POLY(1) 3 0
2002 Microchip Technology Inc.
DS21669B-page 15
MCP6041/2/3/4
E47 47 0 POLY(1) 4 0
V44 43 44 1M
0 1
D44 45 44 DLS
D46 46 45 DLS
V46 46 47 1M
G45 47 45 POLY(2) 31 0 3 4
R45 45 47 125K
0 8U 4U
R48 45 5 44
C48
*
5
0 2P
* Models
.MODEL NMI NMOS L=2 W=42
.MODEL DL D N=1 IS=1F
.MODEL DLS D N=1M IS=1F
.MODEL DN1 D IS=1F KF=1.13E-18 AF=1
.MODEL DN23 D IS=1F KF=3E-20
AF=1
*
.ENDS MCP6041
DS21669B-page 16
2002 Microchip Technology Inc.
MCP6041/2/3/4
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP6041
I/PNNN
YYWW
YYWW
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
MCP6041
I/SNYYWW
NNN
NNN
Example:
8-Lead MSOP
XXXXXX
YWWNNN
6041
YWWNNN
Example:
5
5-Lead SOT-23 (MCP6041 only)
5
4
4
XXNN
SBNN
1
2
3
1
2
3
Legend: XX...X Customer specific information*
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
2002 Microchip Technology Inc.
DS21669B-page 17
MCP6041/2/3/4
5.1
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6044)
Example:
MCP6044-I/P
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
YYWWNNN
14-Lead SOIC (150 mil) (MCP6044)
Example:
MCP6044ISL
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
YYWWNNN
Example:
14-Lead TSSOP (MCP6044)
XXXXXX
YYWW
6044ST
YYWW
NNN
NNN
Legend: XX...X Customer specific information*
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
DS21669B-page 18
2002 Microchip Technology Inc.
MCP6041/2/3/4
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
MAX
n
p
A
A2
A1
E
E1
D
L
c
B1
B
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
8
8
.100
.155
.130
2.54
3.94
3.30
.140
.170
.145
3.56
4.32
3.68
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
2.92
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
2002 Microchip Technology Inc.
DS21669B-page 19
MCP6041/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
8
MAX
n
p
A
A2
A1
E
E1
D
h
L
φ
Number of Pins
Pitch
Overall Height
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
Standoff
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21669B-page 20
2002 Microchip Technology Inc.
MCP6041/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
p
E1
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.026
0.65
Overall Height
Molded Package Thickness
A
A2
A1
E
E1
D
.044
1.18
.030
.034
.038
.006
.200
.122
.122
.028
.039
0.76
0.86
0.97
0.15
.5.08
3.10
3.10
0.70
1.00
Standoff
§
.002
.184
.114
.114
.016
.035
0.05
4.67
2.90
2.90
0.40
0.90
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint (Reference)
Foot Angle
.193
.118
.118
.022
.037
4.90
3.00
3.00
0.55
0.95
L
F
φ
0
6
0
6
c
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
.004
.010
.006
.012
.008
.016
0.10
0.25
0.15
0.30
0.20
0.40
B
α
β
7
7
7
7
*Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
Drawing No. C04-111
2002 Microchip Technology Inc.
DS21669B-page 21
MCP6041/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
E
E1
p
B
p1
D
n
1
α
c
A
A2
φ
A1
L
β
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
5
MAX
n
p
p1
A
A2
A1
E
E1
D
Number of Pins
Pitch
Outside lead pitch (basic)
Overall Height
5
.038
.075
.046
.043
.003
.110
.064
.116
.018
5
0.95
1.90
.035
.035
.000
.102
.059
.110
.014
0
.057
0.90
0.90
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
1.45
Molded Package Thickness
.051
.006
.118
.069
.122
.022
10
.008
.020
10
1.30
0.15
3.00
1.75
3.10
0.55
10
0.20
0.50
10
Standoff
§
0.00
2.60
1.50
2.80
0.35
0
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
L
φ
c
.004
.014
0
.006
.017
5
0.09
0.35
0
0.15
0.43
5
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-178
Drawing No. C04-091
DS21669B-page 22
2002 Microchip Technology Inc.
MCP6041/2/3/4
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
A
A2
A1
E
E1
D
L
c
B1
B
Number of Pins
Pitch
Top to Seating Plane
14
14
.100
.155
.130
2.54
3.94
3.30
.140
.170
.145
3.56
4.32
3.68
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
2002 Microchip Technology Inc.
DS21669B-page 23
MCP6041/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
A
A2
A1
E
E1
D
Number of Pins
Pitch
Overall Height
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
.053
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
Standoff
.052
.004
.228
.150
.337
.010
.016
0
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
h
L
φ
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
DS21669B-page 24
2002 Microchip Technology Inc.
MCP6041/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
A1
A2
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
Overall Height
14
14
.026
0.65
A
.043
1.10
Molded Package Thickness
A2
A1
E
E1
D
.033
.002
.246
.169
.193
.020
0
.004
.007
0
.035
.004
.251
.173
.197
.024
4
.006
.010
5
.037
.006
.256
.177
.201
.028
8
.008
.012
10
0.85
0.90
0.10
6.38
4.40
5.00
0.60
4
0.15
0.25
5
0.95
0.15
6.50
4.50
5.10
0.70
8
0.20
0.30
10
Standoff
§
0.05
6.25
4.30
4.90
0.50
0
0.09
0.19
0
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
L
φ
c
B1
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
2002 Microchip Technology Inc.
DS21669B-page 25
MCP6041/2/3/4
NOTES:
DS21669B-page 26
2002 Microchip Technology Inc.
MCP6041/2/3/4
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
013001
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2002 Microchip Technology Inc.
DS21669B-page 27
MCP6041/2/3/4
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
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Reader Response
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RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS21669B
Device:
MCP6041/2/3/4
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS21669B-page 28
2002 Microchip Technology Inc.
MCP6041/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
Examples:
Temperature Package
Range
a)
b)
c)
d)
e)
f)
MCP6041-I/P:
Industrial temperature,
PDIP package.
MCP6041T-I/OT: Tape and Reel, Indus-
trial temperature, SOT-23 package.
MCP6042-I/SN: Industrial temperature,
SOIC package.
MCP6043-I/MS: Industrial temperature,
MSOP package.
MCP6044-I/SL:
SIOC package.
Device:
MCP6041: CMOS Single Op Amp
MCP6041T: CMOS Single Op Amp
(Tape and Reel for SOT-23, SOIC, MSOP)
MCP6042: CMOS Dual Op Amp
MCP6042T: CMOS Dual Op Amp
(Tape and Reel for SOIC and TSSOP)
Industrial temperature,
MCP6043: CMOS Single Op Amp w/CS Function
MCP6043T: CMOS Single Op Amp w/CS Function
(Tape and Reel for SOIC and MSOP)
MCP6044-I/ST:
TSSOP package.
Industrial temperature,
MCP6044: CMOS Quad Op Amp
MCP6044T: CMOS Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
Temperature Range:
Package:
I
=
-40°C to +85°C
MS
P
=
=
=
=
Plastic MSOP, 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic Small Outline Transistor (SOT-23),
5-lead (Tape and Reel - MCP6041 only)
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP (4.4mm Body), 14-lead
SN
OT
SL
ST
=
=
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21669B-page 29
MCP6041/2/3/4
NOTES:
DS21669B-page 30
2002 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
®
PICmicro 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21669B - page 31
M
WORLDWIDE SALES AND SERVICE
Japan
AMERICAS
ASIA/PACIFIC
Microchip Technology Japan K.K.
Benex S-1 6F
Corporate Office
Australia
2355 West Chandler Blvd.
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 2121, NSW
3-18-20, Shinyokohama
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Chandler, AZ 85224-6199
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Technical Support: 480-792-7627
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Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wan Tai Bldg.
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Atlanta
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Tel: 770-640-0034 Fax: 770-640-0307
China - Chengdu
#07-02 Prime Centre
Boston
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401, 24th Floor,
Singapore, 188980
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Tel: 978-692-3848 Fax: 978-692-3821
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Taiwan
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No. 88 TIDU Street
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Tung Hua North Road
Taipei, 105, Taiwan
Tel: 630-285-0071 Fax: 630-285-0075
China - Fuzhou
Dallas
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
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4570 Westgrove Drive, Suite 160
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Denmark
Tri-Atria Office Building
Tel: 86-591-7503506 Fax: 86-591-7503521
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Kokomo
Room 701, Bldg. B
2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles
Far East International Plaza
No. 317 Xian Xia Road
France
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
18201 Von Karman, Suite 1090
Irvine, CA 92612
China - Shenzhen
Batiment A - ler Etage
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 1315, 13/F, Shenzhen Kerry Centre,
Renminnan Lu
91300 Massy, France
Tel: 949-263-1888 Fax: 949-263-1338
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
New York
Germany
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Shenzhen 518001, China
Tel: 631-273-5305 Fax: 631-273-5335
Tel: 86-755-2350361 Fax: 86-755-2366086
San Jose
China - Hong Kong SAR
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Italy
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Tel: 408-436-7950 Fax: 408-436-7955
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
India
Milan, Italy
Microchip Technology Inc.
India Liaison Office
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Divyasree Chambers
Microchip Ltd.
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
Austria
Microchip Technology Austria GmbH
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
05/16/02
DS21669B-page 32
2002 Microchip Technology Inc.
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