MCP6141-E/MS_技术文档

MCP6141/2/3/4

600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps

Features:

Description:

• Low Quiescent Current: 600 nA/amplifier (typical)

• Gain Bandwidth Product: 100 kHz (typical)

• Stable for gains of 10 V/V or higher

• Rail-to-Rail Input/Output

The MCP6141/2/3/4 family of non-unity gain stable

operational amplifiers (op amps) from Microchip

Technology Inc. operate with a single supply voltage as

low as 1.4V, while drawing less than 1 µA (maximum)

of quiescent current per amplifier. These devices are

also designed to support rail-to-rail input and output

operation. This combination of features supports

battery-powered and portable applications.

• Wide Supply Voltage Range: 1.4V to 6.0V

• Available in Single, Dual, and Quad

• Chip Select (CS) with MCP6143

• Available in 5-lead and 6-lead SOT-23 Packages

• Temperature Ranges:

The MCP6141/2/3/4 amplifiers have a gain bandwidth

product of 100 kHz (typical) and are stable for gains of

10 V/V or higher. These specifications make these op

amps appropriate for battery powered applications

where a higher frequency response from the amplifier

is required.

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Applications:

The MCP6141/2/3/4 family operational amplifiers are

offered in single (MCP6141), single with Chip Select

(CS) (MCP6143), dual (MCP6142) and quad

(MCP6144) configurations. The MCP6141 device is

available in the 5-lead SOT-23 package, and the

MCP6143 device is available in the 6-lead SOT-23

package.

• Toll Booth Tags

• Wearable Products

• Temperature Measurement

• Battery Powered

Design Aids:

Package Types

• SPICE Macro Models

• FilterLab^®Software

MCP6141

PDIP, SOIC, MSOP

MCP6143

PDIP, SOIC, MSOP

• Mindi™ Simulation Tool

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

NC 1

8

7

6

NC

NC 1

8

7

6

CS

2

3

4

V_IN

–

+

V_DD

V_OUT

2

3

4

V_IN

–

+

V_DD

V_OUT

V_IN

5 NC

V_SS

5 NC

V_SS

Related Devices:

MCP6141

SOT-23-5

MCP6143

SOT-23-6

• MCP6041/2/3/4: Unity Gain Stable Op Amps

V_OUT

V_SS

1

5

V_OUT

V_SS

1

6

5

4

V_DD

CS

Typical Application

2

3

2

3

R₁

4

V_IN

+

V_IN

–

V_IN

+

V_IN–

V₁

MCP6142

PDIP, SOIC, MSOP

MCP6144

PDIP, SOIC, TSSOP

R₂

R₃

V₂

V₃

R_F

V_OUTA

1

2

3

4

5

6

7

14

13

12

V_OUTD

V_OUTA

1

2

3

4

8

7

6

V_DD

V_OUT

V_INA

–

+

V_IND

–

+

V_INA

–

+

V_OUTB

V_INA

V_INB

–

+

MCP614X

11 V_SS

V_DD

5 V_INB

V_SS

V_REF

10

9

V_INB

+

–

V_INC

+

–

V_INB

Inverting, Summing Amplifier

8 V_OUTC

V_OUTB

DS21668D-page 1

MCP6141/2/3/4

NOTES:

DS21668D-page 2

MCP6141/2/3/4

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V_DD– V_SS........................................................................7.0V

Current at Analog Input Pins.........................................±2 mA

Analog Inputs (V_IN+, V_IN–) ††........ V_SS– 1.0V to V_DD+ 1.0V

All Other Inputs and Outputs ......... V_SS– 0.3V to V_DD+ 0.3V

†† See Section 4.1.2 “Input Voltage and Current Limits”.

Difference Input Voltage ...................................... |V_DD– V_SS

|

Output Short Circuit Current ................................Continuous

Current at Output and Supply Pins ............................±30 mA

Storage Temperature ...................................–65°C to +150°C

Maximum Junction Temperature (T_J)..........................+150°C

ESD Protection On All Pins (HBM; MM) .............. ≥ 4 kV; 400V

DC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V_DD= +1.4V to +5.5V, V_SS= GND, T_A= +25°C, V_CM= V_DD/2,

V_OUT≈ V_DD/2, V_L= V_DD/2, R_L= 1 MΩ to V_Land CS is tied low (refer to Figure 1-2 and Figure 1-3).

Parameters

Sym

Min

Typ

Max

Units

Conditions

Input Offset

Input Offset Voltage

V_OS

-3

—

+3

—

mV

V_CM= V_SS

Drift with Temperature

ΔV_OS/ΔT_A

±1.8

±10

µV/°C V_CM= V_SS, T_A= -40°C to +85°C

µV/°C V_CM= V_SS

,

T_A= +85°C to +125°C

Power Supply Rejection

Input Bias Current and Impedance

Input Bias Current

PSRR

70

85

—

dB

V_CM= V_SS

I_B

—

1

20

—

100

5000

—

pA

Industrial Temperature

T_A= +85°

Extended Temperature

I_B

1200

pA

T_A= +125°

Input Offset Current

I_OS

Z_CM

Z_DIFF

1

pA

Common Mode Input Impedance

Differential Input Impedance

Common Mode

10¹³||6

—

Ω||pF

—

Common-Mode Input Range

Common-Mode Rejection Ratio

V_CMR

CMRR

V_SS−0.3

62

—

80

75

80

V_DD+0.3

V

—

dB

V_DD= 5V, V_CM= -0.3V to 5.3V

V_DD= 5V, V_CM= 2.5V to 5.3V

V_DD= 5V, V_CM= -0.3V to 2.5V

60

Open-Loop Gain

DC Open-Loop Gain (large signal)

A_OL

95

115

—

dB

R_L= 50 kΩ to V_L,

V

_OUT= 0.1V to V_DD−0.1V

Output

Maximum Output Voltage Swing

V_OL, V_OHV_SS+ 10

—

V_DD− 10

mV

R_L= 50 kΩ to V_L,

0.5V input overdrive

Linear Region Output Voltage Swing

Output Short Circuit Current

V_OVR

V_SS+ 100

V_DD− 100

R_L= 50 kΩ to V_L,

A_OL≥ 95 dB

I_SC

—

2

—

mA

V_DD= 1.4V

V_DD= 5.5V

20

Power Supply

Supply Voltage

V_DD

I_Q

1.4

0.3

—

6.0

1.0

V

Note 1

Quiescent Current per Amplifier

0.6

µA

I_O= 0

Note 1: All parts with date codes February 2008 and later have been screened to ensure operation at V = 6.0V. However, the

DD

other minimum and maximum specifications are measured at 1.8V and 5.5V

DS21668D-page 3

MCP6141/2/3/4

AC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V_DD= +1.4V to +5.5V, V_SS= GND, T_A= +25°C, V_CM= V_DD/2,

V_OUT≈ V_DD/2, V_L= V_DD/2, R_L= 1 MΩ to V_L, C_L= 60 pF and CS is tied low (refer to Figure 1-2 and Figure 1-3).

Parameters

Sym

Min

Typ

Max Units

Conditions

AC Response

Gain Bandwidth Product

Slew Rate

GBWP

SR

—

100

24

—

kHz

V/ms

°

Phase Margin

PM

60

G = +10 V/V

Noise

Input Voltage Noise

Input Voltage Noise Density

Input Current Noise Density

E_ni

e_ni

i_ni

—

5.0

170

0.6

—

µV_P-Pf = 0.1 Hz to 10 Hz

nV/√Hz f = 1 kHz

fA/√Hz f = 1 kHz

MCP6143 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V_DD= +1.4V to +5.5V, V_SS= GND, T_A= +25°C, V_CM= V_DD/2,

V_OUT≈ V_DD/2, V_L= V_DD/2, R_L= 1 MΩ to V_L, and C_L= 60 pF (refer to Figure 1-2 and Figure 1-3).

Parameters

Sym

Min

Typ

Max

Units

Conditions

CS Low Specifications

CS Logic Threshold, Low

V_IL

V_SS

—

5

V_SS+0.3

—

V

CS Input Current, Low

I_CSL

pA

CS = V_SS

CS High Specifications

CS Logic Threshold, High

CS Input Current, High

V_IH

I_CSH

I_SS

V_DD–0.3

—

5

V_DD

—

V

—

pA

CS = V_DD

CS Input High, GND Current

Amplifier Output Leakage, CS High

Dynamic Specifications

-20

20

—

I_OLEAK

—

CS Low to Amplifier Output Turn-on Time

t_ON

—

2

50

ms

G = +1 V/V, CS = 0.3V to

_OUT= 0.9V_DD/2

V

CS High to Amplifier Output High-Z

Hysteresis

t_OFF

—

10

—

µs

V

G = +1 V/V, CS = V_DD–0.3V to

_OUT= 0.1V_DD/2

V

V_HYST

0.6

V_DD= 5.0V

V_IL

CS

V_IH

t_OFF

High-Z

t_ON

V_OUT

High-Z

-0.6 µA

(typical)

I_SS

-20 pA

(typical)

5 pA (typical)

I_CS

5 pA (typical)

FIGURE 1-1:

Chip Select (CS) Timing

Diagram (MCP6143 only).

DS21668D-page 4

MCP6141/2/3/4

TEMPERATURE CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V_DD= +1.4V to +5.5V, V_SS= GND.

Parameters Sym. Min. Typ. Max. Units

Temperature Ranges

Conditions

Specified Temperature Range

T_A

-40

-65

—

+85

°C Industrial Temperature parts

°C Extended Temperature parts

°C (Note 1)

+125

+150

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23

Thermal Resistance, 6L-SOT-23

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-PDIP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 14L-PDIP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

°C

θ_JA

—

256

230

206

85

—

°C/W

163

70

120

100

Note 1: The MCP6141/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with

reduced performance. In any case, the internal Junction Temperature (T_J) must not exceed the Absolute

Maximum specification of +150°C.

1.1

Test Circuits

The test circuits used for the DC and AC tests are

shown in Figure 1-2 and Figure 1-2. The bypass

capacitors are laid out according to the rules discussed

in Section 4.6 “Supply Bypass”.

V_DD

1 µF

0.1 µF

V_IN

V_OUT

R_L

R_N

R_G

MCP614X

C_L

R_F

V_DD/2

V_L

FIGURE 1-2:

AC and DC Test Circuit for

Most Non-Inverting Gain Conditions.

V_DD

1 µF

0.1 µF

V_DD/2

V_OUT

R_L

R_N

R_G

MCP614X

C_L

R_F

V_IN

V_L

FIGURE 1-3:

AC and DC Test Circuit for

Most Inverting Gain Conditions.

DS21668D-page 5

MCP6141/2/3/4

NOTES:

DS21668D-page 6

MCP6141/2/3/4

2.0

TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.4V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

V_L= V_DD/2, R_L= 1 MΩ to V_L, C_L= 60 pF, and CS is tied low.

12%

10%

234 Samples

2396 Samples

11%

Representative Lot

9%

8%

7%

6%

5%

4%

3%

2%

1%

0%

V_CM= V_SS

10%

9%

8%

7%

6%

5%

4%

3%

2%

1%

0%

V_DD= 1.4V

V_CM= V_SS

T_A= +85°C to +125°C

-3

-2

-1

0

1

2

3

-10 -8 -6 -4 -2

0

2

4

6

8

10

Input Offset Voltage (mV)

Input Offset Voltage Drift (µV/°C)

FIGURE 2-1:

Input Offset Voltage.

FIGURE 2-4:

Input Offset Voltage Drift

with T = +85°C to +125°C and V = 1.4V.

A

DD

16%

14%

12%

10%

8%

12%

234 Samples

Representative Lot

V_DD= 5.5V

V_CM= V_SS

T_A= +85°C to +125°C

2267 Samples

T_A= -40°C to +85°C

V_CM= V_SS

11%

10%

9%

8%

7%

6%

5%

4%

3%

2%

1%

0%

6%

4%

2%

0%

-10 -8 -6 -4 -2

0

2

4

6

8

10

-10 -8 -6 -4 -2

0

2

4

6

8

10

Input Offset Voltage Drift (µV/°C)

FIGURE 2-2:

Input Offset Voltage Drift

FIGURE 2-5:

Input Offset Voltage Drift

with T = -40°C to +85°C.

with T = +85°C to +125°C and V = 5.5V.

A

DD

1000

800

V_DD= 1.4V

800

V_DD= 5.5V

T_A= +125°C

T_A= +85°C

600

400

200

0

600

T_A= +125°C

T_A= +85°C

400

200

0

-200

-400

-600

-200

-400

-600

-800

-1000

T_A= +25°C

T_A= -40°C

T_A= +25°C

T_A= -40°C

-800

-1000

Common Mode Input Voltage (V)

FIGURE 2-3:

Input Offset Voltage vs.

FIGURE 2-6:

Input Offset Voltage vs.

Common Mode Input Voltage with V = 1.4V.

Common Mode Input Voltage with V = 5.5V.

DD

DS21668D-page 7

MCP6141/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.4V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

V_L= V_DD/2, R_L= 1 MΩ to V_L, C_L= 60 pF, and CS is tied low.

500

450

400

350

300

250

6

5

V_DD= 5.0V

G = +11 V/V

4

V_DD= 1.4V

3

2

V_IN

1

V_DD= 5.5V

V_OUT

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

-1

0

5

Ti1m0e (5 ms/1d5iv)

20

25

FIGURE 2-7:

Input Offset Voltage vs.

FIGURE 2-10:

The MCP6141/2/3/4 Family

Output Voltage.

Shows No Phase Reversal.

300

1,000

f = 1 kHz

V_DD= 5.0V

250

200

150

100

50

0

100

0.1

1

10

100

1000

Frequency (Hz)

Common Mode Input Voltage (V)

FIGURE 2-8:

Input Noise Voltage Density

FIGURE 2-11:

Input Noise Voltage Density

vs. Frequency.

vs. Common Mode Input Voltage.

100

90

80

70

60

50

40

30

100

95

PSRR–

PSRR+

CMRR

PSRR (V_CM= V_SS

)

90

85

80

75

70

CMRR (V_DD= 5.0V,

V_CM= -0.3V to +5.3V)

Referred to Input

20

1

10

100

1k

1,000

10k

10,000

-50

-25

0

25

50

75

100

125

1

Frequency (Hz)

Ambient Temperature (°C)

FIGURE 2-9:

CMRR, PSRR vs.

FIGURE 2-12:

CMRR, PSRR vs. Ambient

Frequency.

Temperature.

DS21668D-page 8

MCP6141/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.4V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

V_L= V_DD/2, R_L= 1 MΩ to V_L, C_L= 60 pF, and CS is tied low.

10k

100 0

10k

V_DD= 5.5V

V_CM= V_DD

V_DD= 5.5V

1k

1000

10010k

100

I_B

T_A= +125°C

T_A= +85°C

100

I_B

10

| I_OS

|

| I_OS

|

1

0.1

45

55

65

75

85

95 105 115 125

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

Ambient Temperature (°C)

FIGURE 2-13:

Input Bias, Offset Currents

FIGURE 2-16:

Input Bias, Offset Currents

vs. Ambient Temperature.

vs. Common Mode Input Voltage.

120

100

80

0

130

120

-30

-60

V_DD= 5.5V

Phase

110

60

-90

100

40

-120

-150

-180

-210

-240

V_DD= 1.4V

Gain

90

20

80

70

0

-20

V_OUT= 0.1V to V_DD– 0.1V

-40

60

0.01 0.1 10 100 1k 10k 100k

1

100

1k

1.E+03

10k

1.E+04

100k

1.E+05

1.E- 1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+

1.E+02

Load Resistance (Ω)

02 01 00 Fre0q1uenc0y2(Hz)03 04 05

FIGURE 2-14:

Open-Loop Gain, Phase vs.

FIGURE 2-17:

DC Open-Loop Gain vs.

Frequency.

Load Resistance.

140

130

120

110

100

90

140

R_L= 50 kΩ

130

120

110

100

90

V_DD= 5.5V

V_DD= 1.4V

80

R_L= 50 kΩ

70

V

_OUT= 0.1V to V_DD– 0.1V

80

0.00

0.05

0.10

0.15

0.20

0.25

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Output Voltage Headroom;

V_DD– V_OHor V_OL– V_SS(V)

FIGURE 2-15:

DC Open-Loop Gain vs.

FIGURE 2-18:

DC Open-Loop Gain vs.

Power Supply Voltage.

Output Voltage Headroom.

DS21668D-page 9

MCP6141/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.4V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

V_L= V_DD/2, R_L= 1 MΩ to V_L, C_L= 60 pF, and CS is tied low.

140

130

120

110

100

90

120

110

100

90

80

70

60

50

40

30

20

10

0

120

110

100

90

80

70

60

50

40

30

20

10

0

GBWP

PM

(G = +10)

V_DD= 5.0V

Input Referred

80

1k

10k

1.E+03

1.E+04

Frequency (Hz)

Common Mode Input Voltage

FIGURE 2-19:

Channel to Channel

FIGURE 2-22:

Gain Bandwidth Product,

Separation vs. Frequency (MCP6142 and

MCP6144 only).

Phase Margin vs. Common Mode Input Voltage.

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

PM

(G = +10)

GBWP

80

70

60

50

PM

(G = +10)

GBWP

40

30

20

10

V_DD= 5.5V

V_DD= 1.4V

0

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

Ambient Temperature (°C)

FIGURE 2-23:

Gain Bandwidth Product,

FIGURE 2-20:

Gain Bandwidth Product,

Phase Margin vs. Ambient Temperature with

V

= 5.5V.

V

= 1.4V.

DD

35

30

25

20

15

10

5

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

T_A= -40°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Ambient Temperature (°C)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

FIGURE 2-24:

Output Short Circuit Current

FIGURE 2-21:

Quiescent Current vs.

vs. Power Supply Voltage.

Power Supply Voltage.

DS21668D-page 10

MCP6141/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.4V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

V_L= V_DD/2, R_L= 1 MΩ to V_L, C_L= 60 pF, and CS is tied low.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1000

100

10

V_DD= 5.5V

R

_L= 50 kΩ

V_OL– V_SS

V_DD– V_OH

V_OL– V_SS

1

0.01

0.1

1

10

-50

-25

0

25

50

75

100 125

Output Current Magnitude (mA)

Ambient Temperature (°C)

FIGURE 2-25:

Output Voltage Headroom

FIGURE 2-28:

Output Voltage Headroom

vs. Output Current Magnitude.

vs. Ambient Temperature.

10

40

35

30

V_DD= 5.5V

High-to-Low

25

20

15

10

5

V_DD= 5.5V

V_DD= 1.4V

1

Low-to-High

V_DD= 1.4V

0

0.1

-50

-25

0

25

50

75

100

125

100

1k

1.E+03

Frequency (Hz)

10k

1.E+04

1.E+02

Ambient Temperature (°C)

FIGURE 2-26:

Slew Rate vs. Ambient

FIGURE 2-29:

Maximum Output Voltage

Temperature.

Swing vs. Frequency.

80

60

80

60

G = +11 V/V

_L= 50 kΩ

G = -10 V/V

R_L= 50 kΩ

R

40

20

0

-20

-40

-60

-80

-20

-40

-60

-80

0.0 0.1 0.2 0.3 Ti0m.4e (10.05µs0/d.6iv) 0.7 0.8 0.9 1.0

0.0 0.1 0.2 0.3 Ti0m.4e (100.05µs0/d.6iv) 0.7 0.8 0.9 1.0

FIGURE 2-27:

Pulse Response.

Small Signal Non-inverting

FIGURE 2-30:

Response.

Small Signal Inverting Pulse

DS21668D-page 11

MCP6141/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.4V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

V_L= V_DD/2, R_L= 1 MΩ to V_L, C_L= 60 pF, and CS is tied low.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_DD= 5.0V

G = +11 V/V

V_DD= 5.0V

G = -10 V/V

R_L= 50 kΩ

0

1 Tim1e (2010 µs/1div) 1

2

0

1 Tim1e (2010 µs/1div) 1

2

FIGURE 2-31:

Large Signal Non-inverting

FIGURE 2-34:

Large Signal Inverting Pulse

Pulse Response.

Response.

25.0

5.0

5.5

5.0

V_DD= 5.0V

On

G = +11 V/V

V_IN= +3.0V

On

22.5

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_OUTOn

4.5

20.0

17.5

15.0

12.5

10.0

7.5

Hysteresis

CS

4.0

3.5

CS

High-to-Low

V_OUT

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Low-to-High

High-Z

V_OUTHigh-Z

V_DD= 5.0V

G = +11 V/V

V_IN= 3.0V

5.0

CS

2.5

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

CS Voltage (V)

0

1

2

3 Tim4e (15ms6/div)7

8

9

10

FIGURE 2-32:

Chip Select (CS) to

FIGURE 2-35:

Internal Chip Select (CS)

Amplifier Output Response Time (MCP6143

only).

Hysteresis (MCP6143 only).

1.E1-00m2

1m

1.E-03

100µ

1.E-04

10µ

1.E-05

1µ

1.E-06

100n

1.E-07

10n

1.E-08

1n

1.E-09

100p

1.E-10

10p

1.E-11

+125°C

+85°C

+25°C

-40°C

1p

1.E-12

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

FIGURE 2-33:

Input Current vs. Input

Voltage (Below V ).

SS

DS21668D-page 12

MCP6141/2/3/4

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

MCP6141

PIN FUNCTION TABLE

MCP6142

MCP6143

MCP6144

MSOP,

PDIP,

SOIC

MSOP,

PDIP,

SOIC

MSOP,

PDIP,

SOIC

MSOP,

PDIP,

SOIC

Symbol

Description

SOT-23-5

SOT-23-6

6

1

2

6

2

1

2

V_OUT, V_OUTAAnalog Output (op amp A)

2

4

V_IN–, V_INA

V_IN+, V_INA

V_DD

–

+

Inverting Input (op amp A)

Non-inverting Input (op amp A)

Positive Power Supply

3

7

5

8

7

6

4

—

4

—

2

5

—

4

—

2

5

V_INB

+

–

Non-inverting Input (op amp B)

Inverting Input (op amp B)

Analog Output (op amp B)

Analog Output (op amp C)

Inverting Input (op amp C)

Non-inverting Input (op amp C)

Negative Power Supply

6

V_INB

7

V_OUTB

V_OUTC

—

4

8

9

V_INC

–

+

10

11

12

13

14

V_INC

V_SS

—

V_IND

+

Non-inverting Input (op amp D)

Inverting Input (op amp D)

Analog Output (op amp D)

V_IND

–

V_OUTD

—

8

5

—

CS

NC

Chip Select

1, 5, 8

1, 5

—

No Internal Connection

3.1

Analog Outputs

3.4

Power Supply Pins

The output pins are low-impedance voltage sources.

The positive power supply pin (V_DD) is 1.4V to 6.0V

higher than the negative power supply pin (V_SS). For

normal operation, the other pins are at voltages

3.2

Analog Inputs

between V_SSand V_DD

.

The non-inverting and inverting inputs are

high-impedance CMOS inputs with low bias currents.

Typically, these parts are used in a single (positive)

supply configuration. In this case, V_SSis connected to

ground and V_DDis connected to the supply. V_DDwill

need bypass capacitors.

3.3

CS Digital Input

This is a CMOS, Schmitt-triggered input that places the

part into a low power mode of operation.

DS21668D-page 13

MCP6141/2/3/4

NOTES:

DS21668D-page 14

MCP6141/2/3/4

dump any currents onto V_DD. When implemented as

shown, resistors R₁and R₂also limit the current

through D₁and D₂.

4.0

APPLICATIONS INFORMATION

The MCP6141/2/3/4 family of op amps is manufactured

using Microchip’s state of the art CMOS process These

op amps are stable for gains of 10 V/V and higher. They

are suitable for a wide range of general purpose, low

power applications.

V_DD

See Microchip’s related MCP6041/2/3/4 family of op

amps for applications needing unity gain stability.

D₁

R₁

V₁

D₂

V_OUT

MCP604X

4.1

Rail-to-Rail Input

V₂

4.1.1

PHASE REVERSAL

R₂

The MCP6141/2/3/4 op amps are designed to not

exhibit phase inversion when the input pins exceed the

supply voltages. Figure 2-10 shows an input voltage

exceeding both supplies with no phase inversion.

V_SS– (minimum expected V₁)

R₁>

R₂>

2 mA

V_SS– (minimum expected V₂)

2 mA

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

FIGURE 4-2:

Protecting the Analog

Inputs.

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This structure was chosen to

protect the input transistors, and to minimize input bias

current (I_B). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

V_SS. They also clamp any voltages that go too far

above V_DD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass

quick ESD events within the specified limits.

It is also possible to connect the diodes to the left of the

resistor R₁and R₂. In this case, the currents through

the diodes D₁and D₂need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (V_IN+ and

V_IN–) should be very small.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the common

mode voltage (V_CM) is below ground (V_SS); see

Figure 2-33. Applications that are high impedance may

need to limit the usable voltage range.

Bond

V_DD

Pad

4.1.3

NORMAL OPERATION

The input stage of the MCP6141/2/3/4 op amps uses

two differential input stages in parallel. One operates at

a low common mode input voltage (V_CM), while the

other operates at a high V_CM. With this topology, the

device operates with a V_CMup to 300 mV above V_DD

and 300 mV below V_SS. The input offset voltage is

measured at V_CM= V_SS– 0.3V and V_DD+ 0.3V to

ensure proper operation.

Bond

Pad

Bond

Pad

Input

Stage

V_IN+

V_IN–

Bond

Pad

V_SS

FIGURE 4-1:

Structures.

Simplified Analog Input ESD

There are two transitions in input behavior as V_CMis

changed. The first occurs, when V_CMis near

V

_SS+ 0.4V, and the second occurs when V_CMis near

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

(and voltages) at the input pins (see Absolute

Maximum Ratings † at the beginning of Section 1.0

“Electrical Characteristics”). Figure 4-2 shows the

recommended approach to protecting these inputs.

The internal ESD diodes prevent the input pins (V_IN+

and V_IN–) from going too far below ground, and the

resistors R₁and R₂limit the possible current drawn out

of the input pins. Diodes D₁and D₂prevent the input

pins (V_IN+ and V_IN–) from going too far above V_DD, and

V_DD– 0.5V (see Figure 2-3 and Figure 2-6). For the

best distortion performance with non-inverting gains,

avoid these regions of operation.

DS21668D-page 15

MCP6141/2/3/4

4.2

Rail-to-Rail Output

4.4

Stability

There are two specifications that describe the output

swing capability of the MCP6141/2/3/4 family of op

amps. The first specification (Maximum Output Voltage

Swing) defines the absolute maximum swing that can

be achieved under the specified load condition. Thus,

the output voltage swings to within 10 mV of either

supply rail with a 50 kΩ load to V_DD/2. Figure 2-10

shows how the output voltage is limited when the input

goes beyond the linear region of operation.

4.4.1

NOISE GAIN

The MCP6141/2/3/4 op amp family is designed to give

high bandwidth and slew rate for circuits with high noise

gain (G_N) or signal gain. Low gain applications should

be realized using the MCP6041/2/3/4 op amp family;

this simplifies design and implementation issues.

Noise gain is defined to be the gain from a voltage

source at the non-inverting input to the output when all

other voltage sources are zeroed (shorted out). Noise

gain is independent of signal gain and depends only on

components in the feedback loop. The amplifier circuits

in Figure 4-3 and Figure 4-4 have their noise gain

calculated as follows:

The second specification that describes the output

swing capability of these amplifiers is the Linear Output

Voltage Range. This specification defines the

maximum output swing that can be achieved while the

amplifier still operates in its linear region. To verify

linear operation in this range, the large signal DC

Open-Loop Gain (A_OL) is measured at points inside the

supply rails. The measurement must meet the specified

A_OLcondition in the specification table.

EQUATION 4-2:

R_F

------

G_N= 1 +

≥ 10 V/V

R_G

4.3

Output Loads and Battery Life

In order for the amplifiers to be stable, the noise gain

should meet the specified minimum noise gain. Note

that a noise gain of G_N= +10 V/V corresponds to a

non-inverting signal gain of G = +10 V/V, or to an

inverting signal gain of G = -9 V/V.

The MCP6141/2/3/4 op amp family has outstanding

quiescent current, which supports battery-powered

applications. There is minimal quiescent current

glitching when Chip Select (CS) is raised or lowered.

This prevents excessive current draw, and reduced

battery life, when the part is turned off or on.

R_IN

Heavy resistive loads at the output can cause

excessive battery drain. Driving a DC voltage of 2.5V

across a 100 kΩ load resistor will cause the supply

current to increase by 25 µA, depleting the battery 43

times as fast as I_Q(0.6 µA, typical) alone.

V_IN

V_OUT

MCP614X

R_G

R_F

High frequency signals (fast edge rate) across

capacitive loads will also significantly increase supply

current. For instance, a 0.1 µF capacitor at the output

presents an AC impedance of 15.9 kΩ (1/2πfC) to a

100 Hz sinewave. It can be shown that the average

power drawn from the battery by a 5.0 V_P-Psinewave

(1.77 V_rms), under these conditions, is:

FIGURE 4-3:

Gain Configuration.

Noise Gain for Non-inverting

R_G

R_F

V_OUT

V_IN

EQUATION 4-1:

P_Supply= (V_DD- V_SS) (I_Q+ V_L(p-p)f C_L)

= (5V)(0.6 µA + 5.0V_p-p· 100Hz · 0.1µF)

= 3.0 µW + 50 µW

MCP614X

R_IN

FIGURE 4-4:

Gain Configuration.

Noise Gain for Inverting

This will drain the battery 18 times as fast as I_Qalone.

DS21668D-page 16

MCP6141/2/3/4

Figure 4-5 shows three example circuits that are

unstable when used with the MCP6141/2/3/4 family.

The unity gain buffer and low gain amplifier

(non-inverting or inverting) are at gains that are too low

for stability (see Equation 4-2).The Miller integrator’s

capacitor makes it reach unity gain at high frequencies,

causing instability.

When driving large capacitive loads with these op

amps (e.g., > 60 pF when G = +10), a small series

resistor at the output (R_ISOin Figure 4-6) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

Note:

The three circuits shown in Figure 4-5 are

not to be used with the MCP6141/2/3/4 op

amps. They are included for illustrative

purposes only.

R_G

R_F

R_ISO

C_L

V_OUT

V_A

MCP614X

Unity Gain Buffer

V_B

FIGURE 4-6:

Output Resistor, R

ISO

stabilizes large capacitive loads.

V_OUT

MCP614X

V_IN

Figure 4-7 gives recommended R_ISOvalues for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (C_L/G_N), where G_Nis the

circuit’s noise gain. For non-inverting gains, G_Nand the

Signal Gain are equal. For inverting gains, G_Nis

1 + |Signal Gain| (e.g., -9 V/V gives G_N= +10 V/V).

Low Gain Amplifier

R_G

R_F

V_OUT

V₁

MCP614X

1 +

R_N

100,000

100k

V₂

R_F

------

R_G

< 10

10k

10,0 0

Miller Integrator

G_N= +10

_N= +20

G

R

C

G_N≥ +50

V_IN

V_OUT

1k

1,000

1p

10p

1.E+01

100p

1n

1.E+03

1.E+00

1.E+02

Normalized Load Capacitance; C_L/G_N(F)

MCP614X

FIGURE 4-7:

Recommended R

Values

ISO

for Capacitive Loads.

FIGURE 4-5:

Circuits for the MCP6141/2/3/4 Family.

Examples of Unstable

After selecting R_ISOfor your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify R_ISO’s value until the

response is reasonable. Bench evaluation and

simulations with the MCP6141/2/3/4 SPICE macro

model are helpful.

4.4.2 CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. A unity gain buffer (G = +1) is the most

sensitive to capacitive loads, though all gains show the

same general behavior.

4.5

MCP6143 Chip Select

The MCP6143 is a single op amp with Chip Select

(CS). When CS is pulled high, the supply current drops

to 50 nA (typical) and flows through the CS pin to V_SS

.

When this happens, the amplifier output is put into a

high impedance state. By pulling CS low, the amplifier

is enabled. If the CS pin is left floating, the amplifier will

not operate properly. Figure 1-1 shows the output

voltage and supply current response to a CS pulse.

DS21668D-page 17

MCP6141/2/3/4

4.6

Supply Bypass

Guard Ring

V_IN– V_IN+

With this family of operational amplifiers, the power

supply pin (V_DDfor single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high frequency performance. It can use a bulk

capacitor (i.e., 1 µF or larger) within 100 mm to provide

large, slow currents. This bulk capacitor is not required

for most applications and can be shared with other

nearby analog parts.

FIGURE 4-9:

for Inverting Gain.

Example Guard Ring Layout

4.7

Unused Op Amps

1. Non-inverting Gain and Unity Gain Buffer:

a) Connect the non-inverting pin (V_IN+) to the

input with a wire that does not touch the

PCB surface.

An unused op amp in a quad package (MCP6144)

should be configured as shown in Figure 4-8. These

circuits prevent the output from toggling and causing

crosstalk.

b) Connect the guard ring to the inverting input

pin (V_IN–). This biases the guard ring to the

common mode input voltage.

Circuits A sets the op amp near its minimum noise gain.

The resistor divider produces any desired reference

voltage within the output voltage range of the op amp;

the op amp buffers that reference voltage. Circuit B

uses the minimum number of components and

operates as a comparator, but it may draw more

current.

2. Inverting Gain and Transimpedance Gain

(convert current to voltage, such as photo

detectors) amplifiers:

a) Connect the guard ring to the non-inverting

input pin (V_IN+). This biases the guard ring

to the same reference voltage as the op

amp (e.g., V_DD/2 or ground).

¼ MCP6144 (A)

¼ MCP6144 (B)

b) Connect the inverting pin (V_IN–) to the input

with a wire that does not touch the PCB

surface.

V_DD

R₁

V_DD

V_REF

R

10R

R₂

R

2

--------------------

V

= V

⋅

REF

DD

R + R

1

2

FIGURE 4-8:

Unused Op Amps.

4.8

PCB Surface Leakage

In applications where low input bias current is critical,

printed circuit board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 10¹²Ω. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP6141/2/3/4 family’s bias current at +25°C (1 pA,

typical).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-9.

DS21668D-page 18

MCP6141/2/3/4

4.9.2

INVERTING SUMMING AMPLIFIER

4.9

Application Circuits

The MCP6141/2/3/4 op amp is well suited for the

inverting summing amplifier shown in Figure 4-11 when

the resistors at the input (R₁, R₂, and R₃) make the

noise gain at least 10 V/V. The output voltage (V_OUT) is

a weighted sum of the inputs (V₁, V₂, and V₃), and is

shifted by the V_REFinput. The necessary calculations

follow in Equation 4-3.

4.9.1

BATTERY CURRENT SENSING

The MCP6141/2/3/4 op amps’ Common Mode Input

Range, which goes 0.3V beyond both supply rails,

supports their use in high side and low side battery

current sensing applications. The very low quiescent

current (0.6 µA, typical) help prolong battery life, and

the rail-to-rail output supports detection low currents.

.

Figure 4-10 shows a high side battery current sensor

circuit. The 1 kΩ resistor is sized to minimize power

losses. The battery current (I_DD) through the 1 kΩ

resistor causes its top terminal to be more negative

than the bottom terminal. This keeps the common

mode input voltage of the op amp below V_DD, which is

within its allowed range. When no current is flowing, the

output will be at its Maximum Output Voltage Swing

R₁

V₁

R₂

R₃

V₂

V₃

R_F

V_OUT

MCP614X

(V_OH), which is virtually at V_DD

.

V_REF

.

I_DD

FIGURE 4-11:

Summing Amplifier.

V_DD

1.4V

1 kΩ

to

EQUATION 4-3:

Noise Gain:

6.0V

V_OUT

MCP6141

1

⎞

⎛

G_N= 1 + R_F----- + ----- + ----- ≥ 10 V/V

⎝

⎠

R₁R₂R₃

Signal Gains:

G₁= –R_F⁄ R₁

G₂= –R_F⁄ R₂

G₃= –R_F⁄ R₃

100 kΩ

1 MΩ

V_OUT= V_DD– (1 kΩ)(11 V/V)I_DD

FIGURE 4-10:

High Side Battery Current

Output Signal:

Sensor.

V_OUT= V₁G₁+ V₂G₂+ V₃G₃+ V_REFG_N

DS21668D-page 19

MCP6141/2/3/4

NOTES:

DS21668D-page 20

MCP6141/2/3/4

5.5

Analog Demonstration and

Evaluation Boards

5.0 DESIGN AIDS

Microchip provides the basic design tools needed for

the MCP6141/2/3/4 family of op amps.

Microchip offers

a

broad spectrum of Analog

Demonstration and Evaluation Boards that are

designed to help you achieve faster time to market. For

5.1

SPICE Macro Model

a

complete listing of these boards and their

The latest SPICE macro model for the MCP6141/2/3/4

op amps is available on the Microchip web site at

www.microchip.com. This model is intended to be an

initial design tool that works well in the op amp’s linear

region of operation over the temperature range. See

the model file for information on its capabilities.

corresponding user’s guides and technical information,

visit the Microchip web site at www.microchip.com/

analogtools.

Two of our boards that are especially useful are:

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,

P/N SOIC8EV

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

• 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N

SOIC14EV

5.6

Application Notes

The following Microchip Analog Design Note and

Application Notes are available on the Microchip web

site at www.microchip.com/appnotes and are

recommended as supplemental reference resources.

5.2

FilterLab^®Software

Microchip’s FilterLab^®software is an innovative

software tool that simplifies analog active filter (using

op amps) design. Available at no cost from the

Microchip web site at www.microchip.com/filterlab, the

FilterLab design tool provides full schematic diagrams

of the filter circuit with component values. It also

outputs the filter circuit in SPICE format, which can be

used with the macro model to simulate actual filter

performance.

• ADN003: “Select the Right Operational Amplifier

for your Filtering Circuits”, DS21821

• AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

• AN723: “Operational Amplifier AC Specifications

and Applications”, DS00723

• AN884: “Driving Capacitive Loads With Op

Amps”, DS00884

5.3

Mindi™ Simulation Tool

• AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

Microchip’s Mindi™ simulation tool aids in the design of

various circuits useful for active filter, amplifier and

power-management applications. It is a free online

simulation tool available from the Microchip web site at

www.microchip.com/mindi. This interactive simulator

enables designers to quickly generate circuit diagrams,

simulate circuits. Circuits developed using the Mindi

simulation tool can be downloaded to a personal

computer or workstation.

These application notes and others are listed in the

design guide:

• “Signal Chain Design Guide”, DS21825

5.4

Microchip Advanced Part Selector

(MAPS)

MAPS is a software tool that helps semiconductor

professionals efficiently identify Microchip devices that

fit a particular design requirement. Available at no cost

from the Microchip website at www.microchip.com/

maps, the MAPS is an overall selection tool for

Microchip’s product portfolio that includes Analog,

Memory, MCUs and DSCs. Using this tool you can

define a filter to sort features for a parametric search of

devices and export side-by-side technical comparison

reports. Helpful links are also provided for Data sheets,

Purchase, and Sampling of Microchip parts.

DS21668D-page 21

MCP6141/2/3/4

NOTES:

DS21668D-page 22

MCP6141/2/3/4

6.0

6.1

PACKAGING INFORMATION

Package Marking Information

Example:

5-Lead SOT-23 (MCP6141)

Device

MCP6141

E-Temp Code

ASNN

XXNN

AS25

Note: Applies to 5-Lead SOT-23

Example:

6-Lead SOT-23 (MCP6143)

Device

MCP6143

E-Temp Code

AWNN

XXNN

AW25

Note: Applies to 6-Lead SOT-23

Example:

8-Lead MSOP

XXXXXX

6143I

YWWNNN

918256

8-Lead PDIP (300 mil)

Example:

XXXXXXXX

XXXXXNNN

MCP6141

E/P 256

0918

e

3

I/P256

OR

YYWW

0918

8-Lead SOIC (150 mil)

Example:

XXXXXXXX

XXXXYYWW

MCP6142

I/SN0918

MCP6142E

e

3

SN 0918

NNN

256

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21668D-page 23

MCP6141/2/3/4

Package Marking Information (Continued)

14-Lead PDIP (300 mil) (MCP6144)

Example:

MCP6144-I/P

XXXXXXXXXXXXXX

YYWWNNN

0918256

MCP6144

e

3

I/P

OR

0918256

14-Lead SOIC (150 mil) (MCP6144)

Example:

MCP6144ISL

XXXXXXXXXX

YYWWNNN

0918256

MCP6144

OR

I/SL^

e

^3

0918256

Example:

14-Lead TSSOP (MCP6144)

6144ST

XXXXXXXX

YYWW

0918

256

NNN

6144EST

0918

OR

256

DS21668D-page 24

MCP6141/2/3/4

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢏꢒꢖꢆꢗꢍꢏꢒꢁꢘꢙꢚ

ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ

ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ

b

N

E

E1

3

2

1

e

e1

D

A2

c

A

φ

A1

L

L1

3ꢆꢃ#

ꢏꢙ44ꢙꢏ"ꢗ"ꢚꢕ

ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#

ꢏꢙ5

56ꢏ

ꢏꢔ7

5$ꢄ8ꢅꢍꢈꢇ%ꢈ1ꢃꢆ

4ꢅꢉ!ꢈ1ꢃ#ꢊꢌ

5

ꢅ

(

ꢐꢁꢛ(ꢈ)ꢕ*

6$# ꢃ!ꢅꢈ4ꢅꢉ!ꢈ1ꢃ#ꢊꢌ

6,ꢅꢍꢉꢋꢋꢈ9ꢅꢃꢓꢌ#

ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈꢗꢌꢃꢊ/ꢆꢅ

ꢕ#ꢉꢆ!ꢇ%%

6,ꢅꢍꢉꢋꢋꢈ<ꢃ!#ꢌ

ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ<ꢃ!#ꢌ

6,ꢅꢍꢉꢋꢋꢈ4ꢅꢆꢓ#ꢌ

.ꢇꢇ#ꢈ4ꢅꢆꢓ#ꢌ

.ꢇꢇ#ꢎꢍꢃꢆ#

.ꢇꢇ#ꢈꢔꢆꢓꢋꢅ

4ꢅꢉ!ꢈꢗꢌꢃꢊ/ꢆꢅ

4ꢅꢉ!ꢈ<ꢃ!#ꢌ

ꢅꢀ

ꢔ

ꢔꢑ

ꢔꢀ

"

"ꢀ

ꢂ

4

ꢀꢁꢛꢐꢈ)ꢕ*

ꢐꢁꢛꢐ

ꢐꢁ;ꢛ

ꢐꢁꢐꢐ

ꢑꢁꢑꢐ

ꢀꢁꢜꢐ

ꢑꢁꢒꢐ

ꢐꢁꢀꢐ

ꢐꢁꢜ(

ꢐꢝ

M

ꢀꢁꢖ(

ꢀꢁꢜꢐ

ꢐꢁꢀ(

ꢜꢁꢑꢐ

ꢀꢁ;ꢐ

ꢜꢁꢀꢐ

ꢐꢁ=ꢐ

ꢐꢁ;ꢐ

ꢜꢐꢝ

4ꢀ

ꢀ

ꢊ

8

ꢐꢁꢐ;

ꢐꢁꢑꢐ

ꢐꢁꢑ=

ꢐꢁ(ꢀ

ꢛꢔꢊꢃꢉꢜ

ꢀꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀꢑꢒꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ

ꢑꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ

)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ

ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐꢛꢀ)

DS21668D-page 25

MCP6141/2/3/4

ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕ !ꢖꢆꢗꢍꢏꢒꢁꢘꢙꢚ

ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ

ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ

b

4

N

E

E1

PIN 1 ID BY

LASER MARK

1

2

3

e

e1

D

c

A

φ

A2

L

A1

L1

3ꢆꢃ#

ꢏꢙ44ꢙꢏ"ꢗ"ꢚꢕ

ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#

ꢏꢙ5

56ꢏ

ꢏꢔ7

5$ꢄ8ꢅꢍꢈꢇ%ꢈ1ꢃꢆ

1ꢃ#ꢊꢌ

5

ꢅ

=

ꢐꢁꢛ(ꢈ)ꢕ*

6$# ꢃ!ꢅꢈ4ꢅꢉ!ꢈ1ꢃ#ꢊꢌ

6,ꢅꢍꢉꢋꢋꢈ9ꢅꢃꢓꢌ#

ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈꢗꢌꢃꢊ/ꢆꢅ

ꢕ#ꢉꢆ!ꢇ%%

6,ꢅꢍꢉꢋꢋꢈ<ꢃ!#ꢌ

ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ<ꢃ!#ꢌ

6,ꢅꢍꢉꢋꢋꢈ4ꢅꢆꢓ#ꢌ

.ꢇꢇ#ꢈ4ꢅꢆꢓ#ꢌ

.ꢇꢇ#ꢎꢍꢃꢆ#

.ꢇꢇ#ꢈꢔꢆꢓꢋꢅ

4ꢅꢉ!ꢈꢗꢌꢃꢊ/ꢆꢅ

4ꢅꢉ!ꢈ<ꢃ!#ꢌ

ꢅꢀ

ꢔ

ꢔꢑ

ꢔꢀ

"

"ꢀ

ꢂ

4

ꢀꢁꢛꢐꢈ)ꢕ*

ꢐꢁꢛꢐ

ꢐꢁ;ꢛ

ꢐꢁꢐꢐ

ꢑꢁꢑꢐ

ꢀꢁꢜꢐ

ꢑꢁꢒꢐ

ꢐꢁꢀꢐ

ꢐꢁꢜ(

ꢐꢝ

M

ꢀꢁꢖ(

ꢀꢁꢜꢐ

ꢐꢁꢀ(

ꢜꢁꢑꢐ

ꢀꢁ;ꢐ

ꢜꢁꢀꢐ

ꢐꢁ=ꢐ

ꢐꢁ;ꢐ

ꢜꢐꢝ

4ꢀ

ꢀ

ꢊ

8

ꢐꢁꢐ;

ꢐꢁꢑꢐ

ꢐꢁꢑ=

ꢐꢁ(ꢀ

ꢛꢔꢊꢃꢉꢜ

ꢀꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀꢑꢒꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ

ꢑꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ

)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ

ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐꢑ;)

DS21668D-page 26

MCP6141/2/3/4

"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ#ꢋꢌꢓꢔꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢇꢄꢌ$ꢄ%ꢃꢆꢕ#ꢍꢖꢆꢗ#ꢍꢏꢇꢚ

ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ

ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ

D

N

E

E1

NOTE 1

2

b

1

e

c

φ

A2

A

L

L1

A1

3ꢆꢃ#

ꢏꢙ44ꢙꢏ"ꢗ"ꢚꢕ

ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#

ꢏꢙ5

56ꢏ

ꢏꢔ7

5$ꢄ8ꢅꢍꢈꢇ%ꢈ1ꢃꢆ

1ꢃ#ꢊꢌ

5

ꢅ

;

ꢐꢁ=(ꢈ)ꢕ*

6,ꢅꢍꢉꢋꢋꢈ9ꢅꢃꢓꢌ#

ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈꢗꢌꢃꢊ/ꢆꢅ

ꢕ#ꢉꢆ!ꢇ%%ꢈ

6,ꢅꢍꢉꢋꢋꢈ<ꢃ!#ꢌ

ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ<ꢃ!#ꢌ

6,ꢅꢍꢉꢋꢋꢈ4ꢅꢆꢓ#ꢌ

.ꢇꢇ#ꢈ4ꢅꢆꢓ#ꢌ

ꢔ

M

ꢐꢁꢒ(

ꢐꢁꢐꢐ

M

ꢐꢁ;(

ꢀꢁꢀꢐ

ꢐꢁꢛ(

ꢐꢁꢀ(

ꢔꢑ

ꢔꢀ

"

"ꢀ

ꢂ

M

ꢖꢁꢛꢐꢈ)ꢕ*

ꢜꢁꢐꢐꢈ)ꢕ*

ꢐꢁ=ꢐ

4

ꢐꢁꢖꢐ

ꢐꢁ;ꢐ

.ꢇꢇ#ꢎꢍꢃꢆ#

.ꢇꢇ#ꢈꢔꢆꢓꢋꢅ

4ꢀ

ꢀ

ꢐꢁꢛ(ꢈꢚ".

M

ꢐꢝ

;ꢝ

4ꢅꢉ!ꢈꢗꢌꢃꢊ/ꢆꢅ

4ꢅꢉ!ꢈ<ꢃ!#ꢌ

ꢊ

8

ꢐꢁꢐ;

ꢐꢁꢑꢑ

M

ꢐꢁꢑꢜ

ꢐꢁꢖꢐ

ꢛꢔꢊꢃꢉꢜ

ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢃꢆꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ

ꢑꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀ(ꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ

ꢜꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ

)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ

ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ

ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢀꢀꢀ)

DS21668D-page 27

MCP6141/2/3/4

"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ&ꢐꢄꢈꢆ'ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆꢙ))ꢆꢎꢋꢈꢆ*ꢔꢅ+ꢆꢗꢇ&'ꢇꢚ

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ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ

N

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E1

3

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2

D

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c

e

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b1

b

3ꢆꢃ#

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;

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6,ꢅꢍꢉꢋꢋꢈ4ꢅꢆꢓ#ꢌ

5

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8

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ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ

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ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐꢀ;)

DS21668D-page 28

MCP6141/2/3/4

,-ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ&ꢐꢄꢈꢆ'ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆꢙ))ꢆꢎꢋꢈꢆ*ꢔꢅ+ꢆꢗꢇ&'ꢇꢚ

ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ

ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ

N

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3

1

2

D

E

A2

A

L

c

A1

b1

b

e

eB

3ꢆꢃ#

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56ꢏ

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ꢅ

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M

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ꢜꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢁꢐꢀꢐ@ꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ

ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ

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ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐꢐ()

DS21668D-page 29

MCP6141/2/3/4

"ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢛꢖꢆMꢆꢛꢄꢓꢓꢔ./ꢆꢙ01)ꢆꢎꢎꢆ*ꢔꢅ+ꢆꢗꢍꢏ' ꢚ

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D

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DS21668D-page 30

MCP6141/2/3/4

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DS21668D-page 31

MCP6141/2/3/4

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DS21668D-page 32

MCP6141/2/3/4

APPENDIX A: REVISION HISTORY

Revision D (May 2009)

Revision A (September 2002)

The following is the list of modifications:

• Original Release of this Document.

1. DC Electrical Charactistics table: Corrected

formatting issue in Output section.

2. AC Electrical Characteristics table: Slew Rate

- changed typical value from 3.0 to 24. Changed

Phase Margin from 65 to 60. Changed Phase

Margin Condition from G=+1 to G=+10 V/V.

3. Updated Package Outline Drawings

4. Updated Revision History.

Revision C (December 2007)

• Updated Figures 2.4 and 2.5

• Expanded Analog Input Absolute Max Voltage

Range (applies retroactively)

• Expanded maximum operating V_DD(going

forward)

• Section 1.0 “Electrical Characteristics”

updated

• Section 2.0 “Typical Performance Curves”

updated

• Section 4.0 “Applications Information”

- Updated input stage explanation

• Section 5.0 “Design Aids” updated

Revision B (November 2005)

The following is the list of modifications:

1. Added the following:

a) SOT-23-5 package for the MCP6141 single

op amps.

b) SOT-23-6 package for the MCP6143 single

op amps with Chip Select.

c) Extended Temperature (-40°C to +125°C)

op amps.

2. Updated

specifications

in

Section 1.0

“Electrical Characteristics” for E-temp parts.

3. Corrected and updated plots in Section 2.0

“Typical Performance Curves”.

4. Added Section 3.0 “Pin Descriptions”.

5. Updated

Section 4.0

“Applications

Information” and added section on unused op

amps.

6. Updated Section 5.0 “Design Aids” to include

FilterLab.

7. Added SOT-23-5 and SOT-23-6 packages and

corrected package marking information in

Section 6.0 “Packaging Information”.

8. Added Appendix A: “Revision History”.

DS21668D-page 33

MCP6141/2/3/4

NOTES:

DS21668D-page 34

MCP6141/2/3/4

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

- X

/ XX

a)

MCP6141-I/P:

Industrial Temperature

8 lead PDIP package.

Device

Temperature

Range

Package

b)

MCP6141T-E/OT: Tape and Reel,

Extended Temperature

5 lead SOT-23 package.

Device:

MCP6141:

MCP6141T:

Single Op Amp

(Tape and Reel for SOT-23, SOIC, MSOP)

Dual Op Amp

(Tape and Reel for SOIC and MSOP)

Single Op Amp w/ CS

(Tape and Reel for SOT-23, SOIC, MSOP)

Quad Op Amp

a)

b)

MCP6142-I/SN:

Industrial Temperature

8 lead SOIC package.

MCP6142T-E/MS: Tape and Reel,

Extended Temperature

MCP6142:

MCP6142T:

8 lead MSOP package.

MCP6143:

MCP6143T:

a)

b)

MCP6143-I/P:

Industrial Temperature,

8 lead PDIP package.

MCP6143T-E/CH: Tape and Reel,

Extended Temperature

MCP6144:

MCP6144T:

6 lead SOT-23 package.

(Tape and Reel for SOIC and TSSOP)

a)

b)

MCP6144-I/SL:

Industrial Temperature

14 lead PDIP package.

Temperature Range:

Package:

I

E

=

-40°C to +85°C (industrial)

-40°C to +125°C (extended)

MCP6144T-E/ST: Tape and Reel,

Extended Temperature

14 lead TSSOP package.

CH

=

Plastic Small Outline Transistor (SOT-23),

6-lead (Tape and Reel - MCP6143 only)

Plastic Micro Small Outline (MSOP), 8-lead

Plastic Small Outline Transistor (SOT-23),

5-lead (Tape and Reel - MCP6141 only)

Plastic DIP (300 mil body), 8-lead, 14-lead

Plastic SOIC (3.9 mm body), 14-lead

Plastic SOIC (3.9 mm body), 8-lead

MS

OT

=

P

=

SL

SN

ST

Plastic TSSOP (4.4 mm body), 14-lead

DS21668D-page 35

MCP6141/2/3/4

NOTES:

DS21668D-page 36

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Hampshire, Linear Active Thermistor, MXDEV,

MXLAB, SEEVAL, SmartSensor and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,

PICkit, PICDEM, PICDEM.net, PICtail, PIC³²logo, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Total Endurance, TSHARC, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS21668D-page 37

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

03/26/09

DS21668D-page 38


型号：	MCP6141-E/MS
厂家：	MICROCHIP
描述：	600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps 600 nA的，非单位增益，轨到轨输入/输出运算放大器运算放大器放大器电路光电二极管
文件：	总38页 (文件大小：664K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP6141-E/MS [MICROCHIP]

相关型号：

MCP6141-E/OT

MCP6141-E/P

MCP6141-E/SL

MCP6141-E/SN

MCP6141-E/SNVAO

MCP6141-E/ST

MCP6141-I/CH

MCP6141-I/MS

MCP6141-I/OT

MCP6141-I/P

MCP6141-I/SL

MCP6141-I/SN