MCP6231_05 [MICROCHIP]
20 レA, 300 kHz Rail-to-Rail Op Amp; 20 μA ， 300 kHz的轨至轨运算放大器
| 型号： | MCP6231_05 |
| 厂家： | 
MICROCHIP |
| 描述： | 20 レA, 300 kHz Rail-to-Rail Op Amp |
| 文件： | 总28页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6231/2/4
20 µA, 300 kHz Rail-to-Rail Op Amp
Features
Description
• Gain Bandwidth Product: 300 kHz (typ.)
• Supply Current: IQ = 20 µA (typ.)
The Microchip Technology Inc. MCP6231/2/4 opera-
tional amplifiers (op amps) provide wide bandwidth for
the quiescent current. The MCP6231/2/4 family has a
300 kHz Gain Bandwidth Product (GBWP) and 65°
(typ.) phase margin. This family operates from a single
supply voltage as low as 1.8V, while drawing 20 µA
(typ.) quiescent current. In addition, the MCP6231/2/4
family supports rail-to-rail input and output swing, with
a common mode input voltage range of VDD + 300 mV
to VSS – 300 mV. These op amps are designed in one
of Microchip’s advanced CMOS processes.
• Supply Voltage: 1.8V to 5.5V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in 5-Pin SC-70 and SOT-23 packages
Applications
• Automotive
• Portable Equipment
• Transimpedance amplifiers
• Analog Filters
Package Types
MCP6231
MCP6231
PDIP, SOIC, MSOP
• Notebooks and PDAs
• Battery-Powered Systems
SOT-23-5
NC
1
2
3
4
8
7
6
5
NC
VDD
VOUT
VSS
1
2
3
5
4
VDD
VIN
–
+
–
+
Available Tools
–
VIN
VOUT
NC
VIN
+
VIN–
• SPICE Macro Models (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
VSS
MCP6231R
MCP6232
PDIP, SOIC, MSOP
Typical Application
SOT-23-5
V
VSS
VOUT
VDD
V
V
8
7
6
5
1
5
4
OUTA
1
2
R
DD
G2
_
V
2
3
V
-
+
IN2
INA
OUTB
–
R
_
VIN+
VIN–
G1
V
+ 3
4
+ -
V
V
INA
INB
V
IN1
V
R
+
SS
F
INB
V
DD
MCP6231U
SC-70-5, SOT-23-5
MCP6234
PDIP, SOIC, TSSOP
–
R
X
Y
V
OUT
MCP6231
+
VDD
VIN
VSS
VIN
+
V
14 V
1
1
2
3
5
OUTA
OUTD
+
R
R
Z
V
– 2
- + + 13 V
-
–
INA
IND
–
V
+
12 V
+
3
4
–
VOUT
4
INA
IND
V
V
SS
11
DD
V
V
+
–
10 V
9 V
8 V
+
5
6
7
INB
INC
- + + -
–
Summing Amplifier Circuit
INB
INC
V
OUTB
OUTC
© 2005 Microchip Technology Inc.
DS21881C-page 1
MCP6231/2/4
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
- V .........................................................................7.0V
SS
DD
All Inputs and Outputs ................. V – 0.3V to V + 0.3V
SS
DD
Difference Input Voltage ...................................... |V – V
|
DD
SS
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Junction Temperature (T )...........................................+150°C
J
ESD Protection On All Pins (HBM;MM) ............... ≥ 4 kV; 300V
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,
VCM = VDD/2, RL = 100 kΩ to VDD/2 and VOUT ≈ VDD/2.
Sym
Min
Typ
Max
Units Conditions
mV VCM = VSS
Parameters
Input Offset
Input Offset Voltage
VOS
VOS
-5.0
-7.0
—
—
+5.0
+7.0
Extended Temperature
mV TA = -40°C to +125°C,
VCM = VSS (Note)
Input Offset Drift with Temperature ΔVOS/ΔTA
—
—
±3.0
83
—
—
µV/°C TA= -40°C to +125°C,
VCM = VSS
Power Supply Rejection Ratio
Input Bias Current and Impedance
Input Bias Current:
PSRR
dB VCM = VSS
IB
IB
—
—
—
—
—
—
±1.0
20
—
—
—
—
—
—
pA
At Temperature
pA TA = +85°C
At Temperature
IB
1100
pA TA = +125°C
Input Offset Current
IOS
ZCM
ZDIFF
±1.0
pA
Common Mode Input Impedance
Differential Input Impedance
Common Mode
1013||6
1013||3
Ω||pF
Ω||pF
Common Mode Input Range
Common Mode Rejection Ratio
VCMR
VSS – 0.3
61
—
VDD + 0.3
—
V
CMRR
75
dB VCM = -0.3V to 5.3V,
VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (large signal)
AOL
90
110
—
—
dB VOUT = 0.3V to VDD – 0.3V,
VCM = VSS
Output
Maximum Output Voltage Swing
VOL, VOH VSS + 35
VDD – 35
mV RL =10 kΩ, 0.5V Output
Overdrive
Output Short-Circuit Current
ISC
ISC
—
—
±6
—
—
mA VDD = 1.8V
mA VDD = 5.5V
±23
Power Supply
Supply Voltage
VDD
IQ
1.8
10
—
5.5
30
V
Quiescent Current per Amplifier
20
µA IO = 0, VCM = VDD – 0.5V
Note:
The SC-70 package is only tested at +25°C.
DS21881C-page 2
© 2005 Microchip Technology Inc.
MCP6231/2/4
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
300
65
—
—
—
kHz
°
G = +1
Slew Rate
SR
0.15
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Eni
eni
ini
—
—
—
6.0
52
—
—
—
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 kHz
fA/√Hz f = 1 kHz
0.6
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Extended Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SC70
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
Note
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
331
256
206
85
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
163
70
120
100
Note:
The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
© 2005 Microchip Technology Inc.
DS21881C-page 3
MCP6231/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
90
85
80
75
70
20%
18%
16%
14%
12%
10%
8%
630 Samples
CM = VSS
V
PSRR (VCM = VSS
)
6%
CMRR (VCM = -0.3V to +5.3V,
DD = 5.0V)
4%
V
2%
0%
-50
-25
0
25
50
75
100
125
Input Offset Voltage (mV)
Ambient Temperature (°C)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
CMRR, PSRR vs. Ambient
Temperature.
100
90
80
70
60
50
40
30
120
100
80
0
RL = 10 kΩ
VCM = VDD/2
PSRR-
-30
Gain
-60
CMRR
60
-90
Phase
PSRR+
40
20
0
-120
-150
-180
-210
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
20
-20
10
100
1k
10k
100k
0.1
1
10 100 1k 10k 100k 1M 10M
1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+
01 00 01 Fr0e2que0n3cy (0H4z) 05 06 07
Frequency (Hz)
FIGURE 2-2:
PSRR, CMRR vs.
FIGURE 2-5:
Open-Loop Gain, Phase vs.
Frequency.
Frequency.
20%
30%
630 Samples
CM = VDD/2
A = +85°C
632 Samples
VCM = VDD/2
TA = +125°C
18%
16%
14%
12%
10%
8%
V
T
25%
20%
15%
10%
5%
6%
4%
2%
0%
0%
Input Bias Current (pA)
Input Bias Current (nA)
FIGURE 2-3:
Input Bias Current at +85°C.
FIGURE 2-6:
Input Bias Current at +125°C.
DS21881C-page 4
© 2005 Microchip Technology Inc.
MCP6231/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
1,000
20%
628 Samples
18%
V
CM = VSS
16%
14%
12%
10%
8%
TA = -40°C to +125°C
100
6%
4%
2%
0%
10
0.1
1
10
100
1k
10k 100k
1.E-01 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0
4
Input Offset Voltage Drift (µV/°C)
0
1Freque2ncy (Hz3)
5
FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
Input Offset Voltage Drift.
vs. Frequency.
100
50
550
VCM = VSS
VDD = 1.8V
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
450
350
250
150
0
-50
-100
-150
-200
VDD = 5.5V
VDD = 1.8V
-250
-300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-11:
Input Offset Voltage vs.
FIGURE 2-8:
Input Offset Voltage vs.
Output Voltage.
Common Mode Input Voltage at VDD = 1.8V.
30
25
20
15
10
5
200
+ISC
VDD = 5.5 V
150
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
100
TA = +125°C
TA = +85°C
50
0
-5
0
-50
TA = +25°C
A = -40°C
T
-10
-15
-20
-25
-30
-100
-150
-200
-ISC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-12:
Output Short-Circuit Current
FIGURE 2-9:
Input Offset Voltage vs.
vs. Ambient Temperature.
Common Mode Input Voltage at VDD = 5.5V.
© 2005 Microchip Technology Inc.
DS21881C-page 5
MCP6231/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
0.30
0.25
0.20
0.15
0.10
0.05
G = +1 V/V
L = 10 kΩ
VDD = 5.5V
R
Falling Edge
VDD = 1.8V
50
Rising Edge
-50 -25
0
25
75
100 125
Time (2 µs/div)
Ambient Temperature (°C)
FIGURE 2-13:
Slew Rate vs. Ambient
FIGURE 2-16:
Small-Signal, Non-Inverting
Temperature.
Pulse Response.
1,000
100
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.0V
G = +1 V/V
VDD – VOH
VOL – VSS
1
10µ
100µ
1
1m
1.0
10m
11
12
Output Current Magnitude (A)
Time (20 µs/div)
FIGURE 2-14:
Output Voltage Headroom
FIGURE 2-17:
Large-Signal, Non-Inverting
vs. Output Current Magnitude.
Pulse Response.
30
10
VCM = 0.9VDD
25
20
15
10
5
VDD = 5.5V
VDD = 1.8V
1
TA = +125°C
T
A = +85°C
TA = +25°C
A = -40°C
T
0
0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
1k
10k
1.E+04
100k
1.E+05
1M
1.E+06
1.E+03
Frequency (Hz)
FIGURE 2-15:
Maximum Output Voltage
FIGURE 2-18:
Quiescent Current vs.
Swing vs. Frequency.
Power Supply Voltage.
DS21881C-page 6
© 2005 Microchip Technology Inc.
MCP6231/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6231
(PDIP, SOIC, MSOP)
MCP6231
(SOT-23-5)
MCP6231R
(SOT-23-5)
MCP6231U
(SOT-23-5)
Symbol
Description
Analog Output
6
1
4
1
4
4
3
VOUT
VIN–
VIN+
VDD
VSS
2
Inverting Input
3
3
3
1
Non-inverting Input
Positive Power Supply
Negative Power Supply
No Internal Connection
7
4
5
2
5
2
5
2
1, 5, 8
—
—
—
NC
TABLE 3-2:
MCP6232
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6234
Symbol
Description
Analog Output (op amp A)
Inverting Input (op amp A)
1
2
1
2
VOUTA
VINA
–
+
3
3
VINA
Non-inverting Input (op amp A)
Positive Power Supply
8
4
VDD
5
5
VINB
+
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Analog Output (op amp B)
Analog Output (op amp C)
Inverting Input (op amp C)
Non-inverting Input (op amp C)
Negative Power Supply
6
6
VINB
–
7
7
VOUTB
VOUTC
—
—
—
4
8
9
VINC
–
+
10
11
12
13
14
VINC
VSS
—
—
—
VIND
+
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Analog Output (op amp D)
VIND
–
VOUTD
3.1
Analog Outputs
3.3
Power Supply (V and V
)
DD
SS
The output pins are low-impedance voltage sources.
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
3.2
Analog Inputs
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts can
share a bulk capacitor (typically 1 µF to 100 µF) with
other nearby analog parts; it needs to be within 100 mm
of the VDD pin.
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
© 2005 Microchip Technology Inc.
DS21881C-page 7
MCP6231/2/4
4.0
APPLICATION INFORMATION
–
The MCP6231/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-cost, low-power and
general-purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6231/2/4 ideal for battery-powered applications.
VOUT
RIN
MCP623X
+
VIN
(Maximum expected VIN) – VDD
------------------------------------------------------------------------------
2 mA
RIN
≥
4.1
Rail-to-Rail Inputs
VSS – (Minimum expected VIN
)
The MCP6231/2/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 4-1 shows the input voltage exceeding
the supply voltage without any phase reversal.
---------------------------------------------------------------------------
RIN
≥
2 mA
FIGURE 4-2:
Input Current-Limiting
Resistor (RIN).
6.0
VDD = 5.0V
VOUT
4.2
Rail-to-Rail Output
5.0
4.0
3.0
2.0
1.0
0.0
-1.0
G = +2 V/V
The output voltage range of the MCP6231/2/4 op amps
is VDD – 35 mV (max.) and VSS + 35 mV (min.) when
RL = 10 kΩ is connected to VDD/2 and VDD = 5.5V.
Refer to Figure 2-14 for more information.
VIN
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, but all gains show the
same general behavior.
Time (1 ms/div)
FIGURE 4-1:
Phase Reversal.
The MCP6231/2/4 Show No
The input stage of the MCP6231/2/4 op amps use two
differential input stages in parallel. One operates at low
common mode input voltage (VCM) and the other at
high VCM. With this topology, the device operates with
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series resis-
tor at the output (RISO in Figure 4-3) improves the feed-
back loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The band-
width will be generally lower than the bandwidth with no
capacitive load.
VCM up to 300 mV above VDD and 300 mV below VSS
.
The input offset voltage is measured at
VCM = VSS – 300 mV and VDD + 300 mV to ensure
proper operation.
Input voltages that exceed the input voltage range
(VSS – 0.3V to VDD + 0.3V at 25°C) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-2.
–
RISO
VOUT
MCP623X
+
VIN
CL
FIGURE 4-3:
Output resistor, RISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
signal gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., –1 V/V gives GN = +2 V/V).
DS21881C-page 8
© 2005 Microchip Technology Inc.
MCP6231/2/4
4.6
PCB Surface Leakage
10,01000k
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6231/2/4 family’s bias current at 25°C (1 pA, typ.).
1k
1,000
GN = 1 V/V
GN = 2 V/V
GN t 4 V/V
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
100
100
10p
100p
100
Normalized Load Capacitance; CL/GN (F)
1n
10n
10000
10
1000
FIGURE 4-4:
for Capacitive Loads.
Recommended RISO Values
VIN–
VIN+
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6231/2/4 SPICE macro
model are very helpful. Modify RISO’s value until the
response is reasonable.
VSS
4.4
Supply Bypass
With this op amp, the power supply pin (VDD for
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-
frequency performance. It can use a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other nearby analog parts.
Guard Ring
Example Guard Ring Layout
FIGURE 4-6:
for Inverting Gain.
1. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
4.5
Unused Op Amps
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
An unused op amp in a quad package (MCP6234)
should be configured as shown in Figure 4-5. Both
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage
and minimizes the supply current draw of the unused
2. Inverting Gain and Transimpedance Amplifiers
(convert current to voltage, such as photo
detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
op amp. Circuit
B
minimizes the number of
components, but may draw a little more supply current
for the unused op amp.
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
¼ MCP6234 (A)
¼ MCP6234 (B)
VDD
VDD
VDD
FIGURE 4-5:
Unused Op Amps.
© 2005 Microchip Technology Inc.
DS21881C-page 9
MCP6231/2/4
To minimize output offset voltage and increase circuit
accuracy, the resistor values need to meet the
conditions:
4.7
Application Circuits
4.7.1
MATCHING THE IMPEDANCE AT
THE INPUTS
RVIN = RIN
–
+
To minimize the effect of input bias current in an ampli-
fier circuit (this is important for very high source-
impedance applications, such as pH meters and
transimpedance amplifiers), the impedances at the
inverting and non-inverting inputs need to be
matched. This is done by choosing the circuit resistor
values so that the total resistance at each input is the
same. Figure 4-7 shows a summing amplifier circuit.
4.7.2
COMPENSATING FOR THE
PARASITIC CAPACITANCE
In analog circuit design, the PCB parasitic capacitance
can compromise the circuit behavior; Figure 4-8 shows
a typical scenario. If the input of an amplifier sees
parasitic capacitance of several picofarad (CPARA
,
R
G2
which includes the common mode capacitance of 6 pF,
typ.), and large RF and RG, the frequency response of
the circuit will include a zero. This parasitic zero
introduces gain-peaking and can cause circuit
instability.
V
V
IN2
IN1
R
G1
R
F
V
DD
–
R
X
Y
V
OUT
MCP623X
+
V
+
AC
V
MCP623X
–
OUT
R
R
Z
R
R
G
F
V
DC
FIGURE 4-7:
Summing Amplifier Circuit.
To match the inputs, set all voltage sources to ground
and calculate the total resistance at the input nodes. In
this summing amplifier circuit, the resistance at the
inverting input is calculated by setting VIN1, VIN2 and
VOUT to ground. In this case, RG1, RG2 and RF are in
parallel. The total resistance at the inverting input is:
C
PARA
C
F
RG
------
RF
CF = CPARA
•
FIGURE 4-8:
Effect of Parasitic
Capacitance at the Input.
1
---------------------------------------------
RIN – =
One solution is to use smaller resistor values to push
the zero to a higher frequency. Another solution is to
compensate by introducing a pole at the point at which
the zero occurs. This can be done by adding CF in
parallel with the feedback resistor (RF). CF needs to be
selected so that the ratio CPARA:CF is equal to the ratio
of RF:RG.
1
1
1
⎛
⎞
--------- --------- ------
+
+
⎝
⎠
RG1 RG2 RF
Where:
RVIN– = total resistance at the inverting input
At the non-inverting input, VDD is the only voltage
source. When VDD is set to ground, both Rx and Ry are
in parallel. The total resistance at the non-inverting
input is:
1
------------------------
RVIN
=
+ RZ
+
1
1
⎛
⎞
------ -----
+
⎝
⎠
RX RY
Where:
+
RVIN = total resistance at the inverting
input
DS21881C-page 10
© 2005 Microchip Technology Inc.
MCP6231/2/4
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6231/2/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6231/2/4 op
amps is available on our web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the macro
model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
®
5.2
FilterLab Software
Microchip’s FilterLab software is an innovative tool that
simplifies analog active-filter (using op amps) design.
Available at no cost from our web site at
www.microchip.com, the FilterLab design tool provides
full schematic diagrams of the filter circuit with
component values. It also outputs the filter circuit in
SPICE format, which can be used with the macro
model to simulate actual filter performance.
© 2005 Microchip Technology Inc.
DS21881C-page 11
MCP6231/2/4
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SC-70 (MCP6231U Only)
Example:
XXN (Front)
YWW (Back)
AS2 (Front)
546 (Back)
XXNN
AS25
OR
OR
Example:
5
5-Lead SOT-23
5
4
3
4
3
Device
Code
MCP6231
BJNN
BKNN
BLNN
BJ25
XXNN
MCP6231R
MCP6231U
1
2
1
2
Note:
Applies to 5-Lead SOT-23.
Example:
8-Lead MSOP
XXXXXX
YWWNNN
6232E
546256
8-Lead PDIP (300 mil)
Example:
MCP6232
XXXXXXXX
XXXXXNNN
e
3
E/P^256
YYWW
0546
8-Lead SOIC (150 mil)
Example:
MCP6232E
XXXXXXXX
XXXXYYWW
SN
e3
0546
NNN
256
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS21881C-page 12
© 2005 Microchip Technology Inc.
MCP6231/2/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6234)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP6234
e
3
E/P^
YYWWNNN
0546256
14-Lead SOIC (150 mil) (MCP6234)
Example:
MCP6234
XXXXXXXXXX
XXXXXXXXXX
e
3
E/SL^
YYWWNNN
0546256
Example:
14-Lead TSSOP (MCP6234)
6234E
0546
XXXXXXXX
YYWW
256
NNN
© 2005 Microchip Technology Inc.
DS21881C-page 13
MCP6231/2/4
5-Lead Small Outline Transistor Package (SC-70)
E
E1
D
p
B
n
1
Q1
A2
A
c
A1
L
Units
INCHES
NOM
5
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
5
MAX
n
p
Number of Pins
Pitch
.026 (BSC)
0.65 (BSC)
Overall Height
A
.031
.043
0.80
1.10
1.00
0.10
2.40
1.35
2.20
0.30
0.40
0.18
0.30
Molded Package Thickness
Standoff
A2
A1
E
.031
.000
.071
.045
.071
.004
.004
.004
.006
.039
.004
.094
.053
.087
.012
.016
.007
.012
0.80
0.00
1.80
1.15
1.80
0.10
0.10
0.10
0.15
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
Q1
c
Top of Molded Pkg to Lead Shoulder
Lead Thickness
Lead Width
B
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
JEITA (EIAJ) Standard: SC-70
Drawing No. C04-061
DS21881C-page 14
© 2005 Microchip Technology Inc.
MCP6231/2/4
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
E
E1
p
B
p1
D
n
1
α
c
A
A2
φ
A1
L
β
Units
Dimension Limits
INCHES*
NOM
5
MILLIMETERS
MIN
MAX
MIN
NOM
5
MAX
n
p
Number of Pins
Pitch
.038
0.95
p1
Outside lead pitch (basic)
Overall Height
.075
.046
.043
.003
.110
.064
.116
.018
5
1.90
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
A
A2
A1
E
.035
.035
.000
.102
.059
.110
.014
0
.057
0.90
1.45
Molded Package Thickness
Standoff
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
0
1.30
0.15
3.00
1.75
3.10
0.55
10
Overall Width
Molded Package Width
Overall Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.004
.014
0
.006
.017
5
.008
.020
10
0.09
0.35
0
0.15
0.43
5
0.20
0.50
10
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
0
5
10
0
5
10
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Drawing No. C04-091
© 2005 Microchip Technology Inc.
DS21881C-page 15
MCP6231/2/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
8
MILLIMETERS*
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.026 BSC
0.65 BSC
Overall Height
A
A2
A1
E
-
-
.043
-
-
1.10
Molded Package Thickness
Standoff
.030
.000
.033
.037
.006
0.75
0.85
0.95
0.15
-
0.00
-
Overall Width
.193 TYP.
4.90 BSC
Molded Package Width
Overall Length
Foot Length
E1
D
.118 BSC
3.00 BSC
.118 BSC
3.00 BSC
L
.016
.024
.031
0.40
0.60
0.80
Footprint (Reference)
Foot Angle
F
.037 REF
0.95 REF
φ
c
0°
.003
.009
5°
-
.006
.012
-
8°
.009
.016
15°
0°
0.08
0.22
5°
-
-
-
-
-
8°
0.23
0.40
15°
Lead Thickness
Lead Width
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
5°
-
15°
5°
15°
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111
DS21881C-page 16
© 2005 Microchip Technology Inc.
MCP6231/2/4
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.100
.155
.130
2.54
3.94
3.30
Top to Seating Plane
A
.140
.170
3.56
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
2.92
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
3.68
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2005 Microchip Technology Inc.
DS21881C-page 17
MCP6231/2/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21881C-page 18
© 2005 Microchip Technology Inc.
MCP6231/2/4
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
© 2005 Microchip Technology Inc.
DS21881C-page 19
MCP6231/2/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.150
.337
.010
.016
0
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
DS21881C-page 20
© 2005 Microchip Technology Inc.
MCP6231/2/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
A1
A2
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
14
14
.026
0.65
Overall Height
A
.043
1.10
Molded Package Thickness
Standoff
A2
A1
E
.033
.002
.246
.169
.193
.020
0
.035
.004
.251
.173
.197
.024
4
.037
.006
.256
.177
.201
.028
8
0.85
0.90
0.10
6.38
4.40
5.00
0.60
4
0.95
0.15
6.50
4.50
5.10
0.70
8
§
0.05
6.25
4.30
4.90
0.50
0
Overall Width
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
Lead Width
B1
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
© 2005 Microchip Technology Inc.
DS21881C-page 21
MCP6231/2/4
NOTES:
DS21881C-page 22
© 2005 Microchip Technology Inc.
MCP6231/2/4
APPENDIX A: REVISION HISTORY
Revision C (March 2005)
The following is the list of modifications:
1. Added the MCP6234 quad op amp.
2. Corrected plots in Section 2.0 “Typical Perfor-
mance Curves”.
3. Added Section 3.0 “Pin Descriptions”.
4. Added new SC-70 package markings. Added
PDIP-14, SOIC-14, and TSSOP-14 packages
and corrected package marking information
(Section 6.0 “Packaging Information”).
5. Added Appendix A: “Revision History”.
Revision B (August 2004)
Revision A (March 2004)
• Original Release of this Document.
© 2005 Microchip Technology Inc.
DS21881C-page 23
MCP6231/2/4
NOTES:
DS21881C-page 24
© 2005 Microchip Technology Inc.
MCP6231/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
-X
/XX
a) MCP6231-E/SN:
Extended Temp.,
8LD SOIC package.
Extended Temp.,
8LD MSOP package.
Extended Temp.,
8LD PDIP package.
Tape and Reel
and/or
Alternate Pinout
Temperature Package
Range
b) MCP6231-E/MS:
c) MCP6231-E/P:
Device:
MCP6231:
MCP6231T:
Single Op Amp (MSOP, PDIP, SOIC)
Single Op Amp (Tape and Reel)
(MSOP, SOIC, SOT-23)
Single Op Amp (Tape and Reel)
(SOT-23)
d) MCP6231RT-E/OT: Tape and Reel,
Extended Temp.,
MCP6231RT:
5LD SOT-23 package
MCP6231UT: Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
MCP6232:
e) MCP6231UT-E/OT: Tape and Reel,
Extended Temp.,
Dual Op Amp
Dual Op Amp (Tape and Reel)
(MSOP, SOIC)
MCP6232T:
5LD SOT-23 package.
f)
MCP6231UT-E/LT: Tape and Reel,
Extended Temp.,
MCP6234:
MCP6234T:
Quad Op Amp
Quad Op Amp (Tape and Reel)
(TSSOP, SOIC)
5LD SC-70 package.
a) MCP6232-E/SN:
b) MCP6232-E/MS:
c) MCP6232-E/P:
Extended Temp.,
8LD SOIC package.
Extended Temp.,
8LD MSOP package.
Extended Temp.,
8LD PDIP package.
Temperature Range:
Package:
E
=
-40°C to +125°C
LT
MS
P
=
=
=
=
Plastic Package (SC-70), 5-lead (MCP6231U only)
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6231, MCP6231R, MCP6231U)
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP (4.4 mil Body), 14-lead
OT
d) MCP6232T-E/SN: Tape and Reel,
Extended Temp.,
SN
SL
ST
=
=
=
8LD SOIC package.
a) MCP6234-E/P:
b) MCP6234-E/SL:
c) MCP6234-E/ST:
Extended Temp.,
14LD PDIP package.
Extended Temp.,
14LD SOIC package.
Extended Temp.,
14LD TSSOP
package.
d) MCP6234T-E/SL: Tape and Reel,
Extended Temp.,
14LD SOIC package.
e) MCP6234T-E/ST: Tape and Reel,
Extended Temp.,
14LD TSSOP
package.
© 2005 Microchip Technology Inc.
DS21881C-page 25
MCP6231/2/4
NOTES:
DS21881C-page 26
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance and WiperLock are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21881C-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Tel: 61-2-9868-6733
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Tel: 91-80-2229-0061
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Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
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Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
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03/01/05
DS21881C-page 28
© 2005 Microchip Technology Inc.
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