MCP6271_06 [MICROCHIP]
170 レA, 2 MHz Rail-to-Rail Op Amp; 170 μA ， 2 MHz的轨至轨运算放大器
| 型号： | MCP6271_06 |
| 厂家： | 
MICROCHIP |
| 描述： | 170 レA, 2 MHz Rail-to-Rail Op Amp |
| 文件： | 总34页 (文件大小：1242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6271/1R/2/3/4/5
170 µA, 2 MHz Rail-to-Rail Op Amp
Description
Features
• Gain Bandwidth Product: 2 MHz (typ.)
• Supply Current: IQ = 170 µA (typ.)
• Supply Voltage: 2.0V to 5.5V
• Rail-to-Rail Input/Output
The Microchip Technology Inc. MCP6271/1R/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 2 MHz
Gain Bandwidth Product (GBWP) and a 65° Phase
Margin. This family also operates from a single supply
voltage as low as 2.0V, while drawing 170 µA (typ.)
quiescent current. The MCP6271/1R/2/3/4/5 supports
rail-to-rail input and output swing, with a common mode
input voltage range of VDD + 300 mV to VSS – 300 mV.
This family of op amps is designed with Microchip’s
advanced CMOS process.
• Extended Temperature Range: –40°C to +125°C
• Available in Single, Dual and Quad Packages
• Parts with Chip Select (CS)
- Single (MCP6273)
- Dual (MCP6275)
The MCP6275 has a Chip Select input (CS) for dual op
amps in an 8-pin package and is manufactured by
cascading two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
CS input puts the device in low power mode.
Applications
• Automotive
• Portable Equipment
• Photodiode Amplifier
• Analog Filters
The MCP6271/1R/2/3/4/5 family operates over the
Extended Temperature Range of –40°C to +125°C,
with a power supply range of 2.0V to 5.5V.
• Notebooks and PDAs
• Battery Powered Systems
Available Tools
• SPICE Macro Model (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
Package Types
MCP6271
MCP6271
MCP6271R
MCP6272
PDIP, SOIC, MSOP
SOT-23-5
SOT-23-5
PDIP, SOIC, MSOP
NC 1
8 NC
VOUT
VSS
1
2
5
VOUT
VDD
1
5
VOUTA
VINA
1
2
8
7
VDD
VSS
VDD
2
7
2
-
+
VIN
VIN+ 3
VSS
–
-
VDD
–
VOUTB
-
-
+
6 VOUT
5 NC
VIN+ 3
4 VIN
VIN+ 3
4 VIN
VINA+ 3
VSS
+
6 VINB
5 VINB
–
–
–
+
-
4
4
MCP6273
MCP6273
MCP6274
PDIP, SOIC, TSSOP
MCP6275
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
SOT-23-6
NC 1
8 CS
VOUT
VSS
1
2
6
5
VOUTA
1
2
14
13
VOUTA/VINB+ 1
8
7
VDD
CS
VOUTD
VDD
VOUTB
-
2
3
4
7
2
VIN
–
+
VINA
–
VINA
VINA+ 3
VSS
–
- +
VDD
VIND
–
+
+ -
- +
-
+
VIN
6
VOUT VIN+ 3
4 VIN
–
VINA+ 3
VDD
INB+ 5
12 VIND
11 VSS
10 VINC
+
-
6 VINB
5 CS
–
VSS
5 NC
4
4
V
+
–
-
-
+
+
VINB
–
VINC
6
7
9
8
VOUTB
VOUTC
© 2006 Microchip Technology Inc.
DS21810E-page 1
MCP6271/1R/2/3/4/5
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Analog Input Pins (VIN+ and VIN–)...............±2 mA
Analog Inputs (VIN+ and VIN–) †† .. VSS – 1.0V to VDD + 1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Difference Input Voltage ...................................... |VDD – VSS
|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Junction Temperature (TJ) ..........................................+150°C
ESD Protection On All Pins (HBM/MM) ................ ≥ 4 kV/400V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset (Note 1)
Input Offset Voltage
VOS
VOS
–3.0
–5.0
—
—
+3.0
+5.0
mV VCM = VSS
Input Offset Voltage
mV TA = –40°C to +125°C, VCM = VSS
(Extended Temperature)
Input Offset Temperature Drift
Power Supply Rejection Ratio
Input Bias Current and Impedance
Input Bias Current
ΔVOS/ΔTA
—
±1.7
90
—
—
µV/°C TA = –40°C to +125°C, VCM = VSS
PSRR
70
dB
VCM = VSS
IB
IB
—
—
—
—
—
—
±1.0
50
—
200
5
pA
pA
nA
pA
Note 2
At Temperature
TA= +85°C (Note 2)
TA= +125°C (Note 2)
Note 3
At Temperature
IB
2
Input Offset Current
IOS
ZCM
ZDIFF
±1.0
1013||6
1013||3
—
—
—
Common Mode Input Impedance
Differential Input Impedance
Common Mode (Note 4)
Common Mode Input Voltage Range
Ω||pF Note 3
Ω||pF Note 3
VCMR
VCMR
VSS − 0.15
VSS − 0.30
70
—
—
85
VDD + 0.15
VDD + 0.30
—
V
V
VDD = 2.0V (Note 5)
VDD = 5.5V (Note 5)
Common Mode Rejection Ratio
Common Mode Rejection Ratio
CMRR
dB
VCM = –0.3V to 2.5V, VDD = 5V
(Note 6)
CMRR
AOL
65
90
80
—
—
dB
dB
VCM = –0.3V to 5.3V, VDD = 5V
(Note 6)
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
110
VOUT = 0.2V to VDD – 0.2V,
V
CM = VSS (Note 1)
Note 1: The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6275’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
4: The MCP6275’s VINB– pin (op amp B) has a common mode input voltage range (VCMR) of VSS + 100 mV to
DD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B)
V
has a voltage range specified by VOH and VOL
5: Set by design and characterization.
.
6: Does not apply to op amp B of the MCP6275.
DS21810E-page 2
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Output
Maximum Output Voltage Swing
Output Short Circuit Current
Power Supply
VOL, VOH VSS + 15
—
VDD − 15
mV 0.5V output overdrive (Note 4)
ISC
—
±25
—
mA
Supply Voltage
VDD
IQ
2.0
—
5.5
V
Quiescent Current per Amplifier
100
170
240
µA
IO = 0
Note 1: The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6275’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
4: The MCP6275’s VINB– pin (op amp B) has a common mode input voltage range (VCMR) of VSS + 100 mV to
DD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B)
V
has a voltage range specified by VOH and VOL
5: Set by design and characterization.
.
6: Does not apply to op amp B of the MCP6275.
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2, CL = 60 pF and and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
2.0
65
—
—
—
MHz
°
G = +1
Slew Rate
SR
0.9
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Eni
eni
ini
—
—
—
4.6
20
3
—
—
—
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 kHz
fA/√Hz f = 1 kHz
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 6L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
TA
–40
–40
–65
—
—
—
+125
+125
+150
°C
°C
°C
Note
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
—
—
—
—
—
—
—
—
256
230
85
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
163
206
70
120
100
Note:
The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
© 2006 Microchip Technology Inc.
DS21810E-page 3
MCP6271/1R/2/3/4/5
MCP6273/MCP6275 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2, CL = 60 pF and and CS is tied low.
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
CS Input Current, Low
VIL
VSS
—
—
0.2VDD
—
V
ICSL
0.01
µA
CS = VSS
CS High Specifications
CS Logic Threshold, High
CS Input Current, High
VIH
ICSH
ISS
0.8VDD
—
—
VDD
2
V
0.7
µA
µA
µA
CS = VDD
CS = VDD
CS = VDD
GND Current per Amplifier
Amplifier Output Leakage
Dynamic Specifications (Note 1)
—
–0.7
0.01
—
—
—
—
CS Low to Valid Amplifier
Output, Turn on Time
tON
—
4
10
µs
CS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output
High-Z
tOFF
—
—
0.01
0.6
—
—
µs
V
CS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
Hysteresis
VHYST
VDD = 5V
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6275. The dynamic
specification is tested at the output of op amp B (VOUTB).
CS
VIL
tON
VIH
tOFF
High-Z
High-Z
VOUT
-0.7 µA (typ.)
ISS
-0.7 µA (typ.)
0.7 µA (typ.)
-170 µA (typ.)
10 nA (typ.)
Timing Diagram for the
0.7 µA (typ.)
ICS
FIGURE 1-1:
Chip Select (CS) pin on the MCP6273 and
MCP6275.
DS21810E-page 4
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF and CS is tied low.
18%
16%
14%
12%
10%
8%
14%
12%
10%
8%
832 Samples
CM = VSS
832 Samples
CM = VSS
TA = -40°C to +125°C
V
V
6%
6%
4%
4%
2%
2%
0%
0%
Input Offset Voltage (mV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage Drift.
32%
22%
422 Samples
TA = +125°C
422 Samples
A = 85°C
20%
18%
16%
14%
12%
10%
8%
28%
24%
20%
16%
12%
8%
T
6%
4%
4%
2%
0%
0%
0
10 20 30 40 50 60 70 80 90 100
Input Bias Current (pA)
Input Bias Current (nA)
FIGURE 2-2:
Input Bias Current at
FIGURE 2-5:
Input Bias Current at
T = +85°C.
T = +125°C.
A
A
300
300
VDD = 2.0V
VDD = 5.5V
250
200
150
100
50
250
200
150
100
50
TA = +125°C
TA = +125°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
TA = +85°C
TA = +25°C
TA = -40°C
0
0
-50
-100
-50
-100
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage, with V = 2.0V.
Common Mode Input Voltage, with V = 5.5V.
DD
DD
© 2006 Microchip Technology Inc.
DS21810E-page 5
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
-0.45
-0.50
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Typical lower (VCM – VSS) limit
VDD = 5.5V
VDD = 2.0V
VDD = 2.0V
VDD = 5.5V
Typical upper (VCM – VDD) limit
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-7:
Common Mode Input
FIGURE 2-10:
Common Mode Input
Voltage Range Lower Limit vs. Temperature.
Voltage Range Upper Limit vs. Temperature.
300
10,000
VCM = VSS
Representative Part
VCM = VDD
250
VDD = 5.5V
1,000
200
150
100
50
Input Bias Current
100
10
1
0
VDD = 2.0V
VDD = 5.5V
Input Offset Current
-50
-100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
Input Bias, Input Offset
Output Voltage.
Currents vs. Temperature.
120
110
110
100
90
80
70
60
50
40
30
20
CMRR
100
90
80
70
60
CMRR
PSRR–
PSRR+
PSRR
(VCM = VSS
)
-50
-25
0
25
50
75
100
125
1
10
100
1k
10k
100k
1M
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
CMRR, PSRR vs.
Frequency.
Temperature.
DS21810E-page 6
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
2.5
55
2.0
1.5
45
35
25
15
5
Input Bias Current
Input Offset Current
Input Bias Current
Input Offset Current
1.0
0.5
0.0
-5
TA = 125°C
DD = 5.5V
TA = 85°C
VDD = 5.5V
-0.5
-1.0
-15
-25
V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias, Offset Currents
FIGURE 2-16:
Input Bias, Offset Currents
vs. Common Mode Input Voltage, with
vs. Common Mode Input Voltage, with
T = +85°C.
T = +125°C.
A
A
250
200
150
100
50
1000
100
10
TA = +125°C
A = +85°C
TA = +25°C
A = -40°C
T
VOL – VSS
T
VDD – VOH
1
0
0.01
0.1
1
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Output Current Magnitude (mA)
FIGURE 2-14:
Quiescent Current vs.
FIGURE 2-17:
Output Voltage Headroom
Supply Voltage.
vs. Output Current Magnitude.
120
100
80
0
3.0
2.5
80
75
70
65
60
55
50
-30
Gain
-60
GBWP, VDD = 5.5V
VDD = 2.0V
2.0
1.5
1.0
0.5
0.0
60
-90
Phase
40
20
0
-120
-150
-180
-210
PM, VDD = 5.5V
VDD = 2.0V
-20
0.1
1
10 100 1k 10k 100k 1M10M 100M
-50 -25
0
25
50
75 100 125
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-15:
Open-Loop Gain, Phase vs.
FIGURE 2-18:
Gain Bandwidth Product,
Frequency.
Phase Margin vs. Temperature.
© 2006 Microchip Technology Inc.
DS21810E-page 7
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
10
1
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VDD = 5.5V
VDD = 5.5V
VDD = 2.0V
Falling Edge
VDD = 2.0V
Rising Edge
0.1
1k
10k
100k
1M
10M
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-19:
Maximum Output Voltage
FIGURE 2-22:
Slew Rate vs. Temperature.
Swing vs. Frequency.
25
20
15
10
1,000
100
5
0
f = 1 kHz
VDD = 5.0V
10
0.1
1
10
100 1k
10k 100k 1M
05 06
1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+
01 Freq02uenc0y3(Hz)04
Common Mode Input Voltage (V)
01
00
FIGURE 2-23:
Input Noise Voltage Density
FIGURE 2-20:
Input Noise Voltage Density
vs. Common Mode Input Voltage, with f = 1 kHz.
vs. Frequency.
140
130
120
110
100
35
30
25
20
15
10
5
TA = +125°C
T
T
A = +85°C
A = +25°C
T
A = -40°C
0
1
10
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Frequency (kHz)
FIGURE 2-24:
Channel-to-Channel
FIGURE 2-21:
Output Short Circuit Current
Separation vs. Frequency (MCP6272 and
MCP6274).
vs. Supply Voltage.
DS21810E-page 8
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
250
200
150
100
50
700
600
500
400
300
200
100
0
VDD = 5.5V
VDD = 2.0V
Op Amp turns Off
Hysteresis
Hysteresis
Op Amp turns On
CS swept
Low-to-High
Op Amp
turns
On/Off
CS swept
High-to-Low
CS swept
Low-to-High
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Chip Select Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
FIGURE 2-25:
Quiescent Current vs. Chip
FIGURE 2-28:
Quiescent Current vs. Chip
Select (CS) Voltage, with V = 2.0V (MCP6273
Select (CS) Voltage, with V = 5.5V (MCP6273
DD
DD
and MCP6275 only).
and MCP6275 only).
5.0
5.0
G = -1 V/V
G = +1 V/V
DD = 5.0V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
VDD = 5.0V
V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Time (5 µs/div)
Time (5 µs/div)
FIGURE 2-26:
Large Signal Non-inverting
FIGURE 2-29:
Large Signal Inverting Pulse
Pulse Response.
Response.
G = -1 V/V
G = +1 V/V
Time (2 µs/div)
Time (2 µs/div)
FIGURE 2-27:
Small Signal Non-inverting
FIGURE 2-30:
Small Signal Inverting Pulse
Pulse Response.
Response.
© 2006 Microchip Technology Inc.
DS21810E-page 9
MCP6271/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (Continued)
Note: Unless otherwise indicated, TA = +25°C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2, CL = 60 pF, and CS is tied low.
2.5
2.0
1.5
1.0
0.5
0.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 2.0V
G = +1 V/V
VDD = 5.5V
G = +1 V/V
VIN = VSS
CS
CS
VIN = VSS
VOUT
Output On
VOUT
Output High-Z
Output High-Z
Output On
Time (5 µs/div)
Time (5 µs/div)
FIGURE 2-31:
Chip Select (CS) to
FIGURE 2-33:
Chip Select (CS) to
Amplifier Output Response Time, with
= 2.0V (MCP6273 and MCP6275 only).
Amplifier Output Response Time, with
V
V
= 5,5V (MCP6273 and MCP6275 only).
DD
DD
1.E-02
10m
1.E-03
1m
6
VDD = 5.0V
5
4
G = +2 V/V
1.E- 4
100µ
1.E1-05µ
1.E-06
1µ
3
100n
1.E- 7
10n
1.E- 8
2
+125°C
+85°C
+25°C
-40°C
1n
1.E-09
VIN
100p
1.E-10
10p
1.E-11
1p
1.E-12
1
VOUT
0
-1
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Time (1 ms/div)
FIGURE 2-32:
Input Current vs. Input
FIGURE 2-34:
The MCP6271/1R/2/3/4/5
Voltage.
Show no Phase Reversal.
DS21810E-page 10
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6271
(PDIP, SOIC, MSOP)
MCP6271
(SOT-23-5) (SOT-23-5)
MCP6271R
MCP6273
(PDIP, SOIC, MSOP)
MCP6273
(SOT-23-6)
Symbol
Description
Inverting Input
2
3
4
3
4
3
2
3
4
3
VIN
–
+
VIN
Non-inverting Input
Negative Power Supply
Analog Output
4
2
5
4
2
VSS
VOUT
VDD
CS
6
1
1
6
1
7
5
2
7
6
Positive Power Supply
Chip Select
—
1,5,8
—
—
—
—
8
5
1,5
—
NC
No Internal Connection
TABLE 3-2:
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6272
MCP6274
MCP6275
Symbol
Description
1
2
1
2
—
2
VOUTA
Analog Output (op amp A)
Inverting Input (op amp A)
VINA
–
+
3
3
3
VINA
Non-inverting Input (op amp A)
Positive Power Supply
8
4
8
VDD
5
5
—
6
VINB
+
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Analog Output (op amp B)
Analog Output (op amp C)
Inverting Input (op amp C)
Non-inverting Input (op amp C)
Negative Power Supply
6
6
VINB
–
7
7
7
VOUTB
VOUTC
—
—
—
4
8
—
—
—
4
9
VINC
–
+
10
11
12
13
14
—
—
VINC
VSS
—
—
—
—
—
—
—
—
1
VIND
+
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Analog Output (op amp D)
VIND
–
VOUTD
VOUTA / VINB
CS
+
Analog Output (op amp A)/Non-inverting Input (op amp B)
Chip Select
5
3.1
Analog Outputs
3.4
CS Digital Input
The output pins are low impedance voltage sources.
This is a CMOS, Schmitt triggered input that places the
part into a low power mode of operation.
3.2
Analog Inputs
3.5
Power Supply (VSS and VDD)
The non-inverting and inverting inputs are high
impedance CMOS inputs with low bias currents.
The positive power supply (VDD) is 2.0V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
3.3
MCP6275’s VOUTA/VINB+ Pin
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts need
to use a bulk capacitor (within 100 mm), which can be
shared with nearby analog parts.
For the MCP6275 only, the output of op amp A is
connected directly to the non-inverting input of op amp
B; this is the VOUTA/VINB+ pin. This connection makes
it possible to provide a CS pin for duals in 8-pin
packages.
© 2006 Microchip Technology Inc.
DS21810E-page 11
MCP6271/1R/2/3/4/5
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute Maxi-
mum Ratings † at the beginning of Section 1.0 “Elec-
trical Characteristics”). Figure 4-2 shows the
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
4.0
APPLICATION INFORMATION
The MCP6271/1R/2/3/4/5 family of op amps is
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low cost, low power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
make the MCP6271/1R/2/3/4/5 ideal for battery
powered applications.
4.1
Rail-to-Rail Inputs
The input stage of the MCP6271/1R/2/3/4/5 op amps
uses two differential CMOS input stages in parallel.
One operates at low common mode input voltage (VCM
,
which is aproximately equal to VIN+ and VIN– in normal
operation) and the other at high VCM. With this topol-
ogy, the input operates with VCM up to 0.3V past either
supply rail (see Figure 2-7 and Figure 2-10). The input
offset voltage (VOS) is measured at VCM = VSS – 0.3V
and VDD + 0.3V to ensure proper operation.
VDD
D1
R1
V1
The transition between the two input stage occurs
when VCM ≈ VDD – 1.1V (see Figure 2-3 and Figure 2-
6). For the best distortion and gain linearity, with non-
inverting gains, avoid this region of operation.
D2
VOUT
MCP627X
V2
R2
VSS – (minimum expected V1)
4.1.1
PHASE REVERSAL
R1 >
R2 >
2 mA
VSS – (minimum expected V2)
2 mA
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-34 shows an input voltage
exceeding both supplies with no phase inversion.
FIGURE 4-2:
Protecting the Analog
Inputs.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-32. Applications that are high impedance may
need to limit the useable voltage range.
Bond
VDD
4.2
Rail-to-Rail Output
Pad
The output voltage range of the MCP6271/1R/2/3/4/5
op amps is VDD – 15 mV (min.) and VSS + 15 mV
(max.) when RL = 10 kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to Figure 2-17 for more information.
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
Bond
Pad
VSS
FIGURE 4-1:
Simplified Analog Input ESD
Structures.
DS21810E-page 12
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
4.3
Capacitive Loads
4.4
MCP6273/5 Chip Select (CS)
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
The MCP6273 and MCP6275 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typ.)
and flows through the CS pin to VSS. When this
happens, the amplifier output is put into a high
impedance state. By pulling CS low, the amplifier is
enabled. The CS pin has a 5 MΩ (typ.) pull-down
resistor connected to VSS, so it will go low if the CS pin
is left floating. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
4.5
Cascaded Dual Op Amps
(MCP6275)
The MCP6275 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This pin is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
device in low power mode. Refer to Section 4.4
“MCP6273/5 Chip Select (CS)”.
–
RISO
VOUT
MCP627X
VIN
+
CL
VINB
–
VOUTA/VINB
1
+
FIGURE 4-3:
stabilizes large capacitive loads.
Output Resistor, R
ISO
6
2
3
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., –1 V/V gives GN = +2 V/V).
7
VINA
VINA
–
VOUTB
B
A
+
MCP6275
5
CS
1,000
FIGURE 4-5:
Cascaded Gain Amplifier.
The output of op amp A is loaded by the input
impedance of op amp B, which is typically
1013Ω⎟⎟6 pF, as specified in the DC specification table
(Refer to Section 4.3 “Capacitive Loads” for further
details regarding capacitive loads).
100
GN = 1 V/V
GN = 2 V/V
GN t 4 V/V
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
VSS + 20 mV and VDD – 20 mV.
10
10
100
1,000
10,000
Normalized Load Capacitance; CL / GN (pF)
FIGURE 4-4:
for Capacitive Loads.
Recommended R
Values
ISO
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6271/1R/2/3/4/5 SPICE
macro model are helpful.
© 2006 Microchip Technology Inc.
DS21810E-page 13
MCP6271/1R/2/3/4/5
4.6
Unused Amplifiers
VIN–
VIN+
VSS
An unused op amp in a quad package (MCP6274)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. In Circuit A, R1 and R2 produce a voltage
within its output voltage range (VOH, VOL). The op amp
buffers this voltage, which can be used elsewhere in
the circuit. Circuit B uses the minimum number of
components and operates as a comparator.
Guard Ring
Example Guard Ring Layout
¼ MCP6274 (A)
¼ MCP6274 (B)
FIGURE 4-7:
for Inverting Gain.
VDD
VDD
1. For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
VDD
R1
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
R2
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
FIGURE 4-6:
Unused Op Amps.
2. Non-inverting Gain and Unity Gain Buffer:
4.7
Supply Bypass
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
4.8
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6271/1R/2/3/4/5 family’s bias current at 25°C
(1 pA, typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is illustrated in
Figure 4-7.
DS21810E-page 14
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
4.9.2
LOSSY NON-INVERTING
INTEGRATOR
4.9
Application Circuits
4.9.1
ACTIVE FULL-WAVE RECTIFIER
The non-inverting integrator shown in Figure 4-9 is
easy to build. It saves one op amp over the typical
Miller integrator plus inverting amplifier configuration.
The phase accuracy of this integrator depends on the
matching of the input and feedback resistor-capacitor
time constants. RF makes this a lossy integrator (it has
finite gain at DC), and makes this integrator stable by
itself.
The MCP6271/1R/2/3/4/5 family of amplifiers can be
used in applications such as an Active Full-Wave
Rectifier or an Absolute Value circuit, as shown in
Figure 4-8. The amplifier and feedback loops in this
active voltage rectifier circuit eliminate the diode drop
problem that exists in a passive voltage rectifier. This
circuit behaves as a follower (the output follows the
input) as long as the input signal is more positive than
the reference voltage. If the input signal is more
negative than the reference voltage, however, the
circuit behaves as an inverting amplifier. Therefore, the
output voltage will always be above the reference
voltage, regardless of the input signal.
R1
VIN
+
VOUT
MCP6271
_
C1
RF
C2
R2
R1
VIN
–
R2
RF ≈ R2
Op Amp B
R3
VOUT
R5
+
R1C1 = (R2||RF)C2
1/2
MCP6272
R4
D2
VOUT
------------- --------------------
1
1
---------------------------------------------------
≈
,
f ≈
VREF
VIN
s(R1C1)
2πR1C1(1 + RF ⁄ R2)
D1
FIGURE 4-9:
Non-Inverting Integrator.
R1 = R2 = R3
–
VD1
⎛
⎞
⎠
R4 < R3 1 –
---------------------------
⎝
VREF – VSS
Op Amp A
R2R4
R5 = ------------
2R3
+
1/2
MCP6272
VREF
Input
Output
VREF
VREF
time
time
FIGURE 4-8:
Active Full-wave Rectifier.
The design equations give a gain of ±1 from VIN to
VOUT, and produce rail-to-rail outputs.
© 2006 Microchip Technology Inc.
DS21810E-page 15
MCP6271/1R/2/3/4/5
4.9.3
CASCADED OP AMP
APPLICATIONS
R4
R3
R2
R1
The MCP6275 provides the flexibility of Low power
mode for dual op amps in an 8-pin package. The
MCP6275 eliminates the added cost and space in a
battery powered application by using two single op
amps with Chip Select (CS) lines or a 10-pin device
with one CS line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with a CS
line becomes suitable. The circuits below show
possible applications for this device.
VOUT
B
A
VIN
MCP6275
CS
FIGURE 4-11:
Configuration.
Cascaded Gain Circuit
4.9.3.3
Difference Amplifier
4.9.3.1
Load Isolation
Figure 4-12 shows op amp A configured as a difference
amplifier with Chip Select. In this configuration, it is
recommended that well matched resistors (e.g., 0.1%)
be used to increase the Common Mode Rejection Ratio
(CMRR). Op amp B can be used to provide additional
gain and isolate the load from the difference amplifier.
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In
applications where op amp A is driving capacitive or
low resistive loads in the feedback loop (such as an
integrator or filter circuit) the op amp may not have
sufficient source current to drive the load. In this case,
op amp B can be used as a buffer.
R2
R1
R4
R3
VIN2
VOUTB
B
VOUT
B
A
R2
A
Load
MCP6275
VIN1
MCP6275
R1
CS
CS
FIGURE 4-10:
Buffer.
Isolating the Load with a
FIGURE 4-12:
4.9.3.4
Difference Amplifier Circuit.
Inverting Integrator with Active
Compensation and Chip Select
4.9.3.2
Cascaded Gain
Figure 4-11 shows a cascaded gain circuit configura-
tion with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this
configuration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of op amp
A and B, as shown below:
Figure 4-13 uses an active compensator (op amp B) to
compensate for the non-ideal op amp characteristics
introduced at higher frequencies. This circuit uses
op amp B as a unity gain buffer to isolate the
integration capacitor C1 from op amp A and drives the
capacitor with a low impedance source. Since both op
amps are matched very well, they provide a high quality
integrator.
VOUT = VINGAGB + VOSAGAGB + VOSBGB
Where:
GA
GB
=
=
=
=
op amp A gain
C1
R1
VIN
B
op amp B gain
VOSA
VOSB
op amp A input offset voltage
op amp B input offset voltage
VOUT
A
MCP6275
Therefore, it is recommended that you set most of the
gain with op amp A and use op amp B with relatively
small gain (e.g., a unity gain buffer).
CS
FIGURE 4-13:
Integrator Circuit with Active
Compensation.
DS21810E-page 16
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
4.9.3.5
Second Order MFB with an Extra
Pole-Zero Pair
4.9.3.7
Capacitorless Second Order
Low-Pass filter with Chip Select
Figure 4-14 is a second order multiple feedback low-
pass filter with Chip Select. Use the FilterLab® software
from Microchip Technology Inc. to determine the R and
C values for op amp A’s second order filter. Op amp B
can be used to add a pole-zero pair using C3, R6 and
R7.
The low-pass filter shown in Figure 4-16 does not
require external capacitors and uses only three
external resistors; the op amp’s GBWP sets the corner
frequency. R1 and R2 are used to set the circuit gain. R3
is used to set the Q. To avoid gain peaking in the
frequency response, Q needs to be low (lower values
need to be selected for R3). Note that the amplifier
bandwidth varies greatly over temperature and
process. This configuration, however, provides a low
cost solution for applications with high bandwidth
requirements.
C3
R7
R6
R1
C1
R1
R2
R3
R2
R5
VOUT
B
VIN
VIN
R3
A
A
VDD
MCP6275
VOUT
B
VREF
R4
MCP6275
CS
FIGURE 4-14:
Feedback Low-Pass Filter with an Extra Pole-
Zero Pair.
Second Order Multiple
CS
FIGURE 4-16:
Capacitorless Second Order
Low-Pass Filter with Chip Select.
4.9.3.6
Second Order Sallen-Key with an
Extra Pole-Zero Pair
Figure 4-15 is a second order Sallen-Key low-pass
filter with Chip Select. Use the Filterlab® software from
Microchip to determine the R and C values for
op amp A’s second order filter. Op amp B can be used
to add a pole-zero pair using C3, R5 and R6.
C3
R6
R5
R1
R2
VOUT
B
R4
R3
C2
A
VIN
MCP6275
C1
CS
FIGURE 4-15:
Second Order Sallen-Key
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
© 2006 Microchip Technology Inc.
DS21810E-page 17
MCP6271/1R/2/3/4/5
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6271/1R/2/3/4/5 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the
MCP6271/1R/2/3/4/5 op amps is available on our web
site at www.microchip.com. This model is intended to
be an initial design tool that works well in the op amp’s
linear region of operation at room temperature. See the
macro model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab software is an innovative tool that
simplifies analog active filter (using op amps) design. It
is available free of charge from our web site at
www.microchip.com. The FilterLab software tool
provides full schematic diagrams of the filter circuit with
component values. It also outputs the filter circuit in
SPICE format, which can be used with the macro
model to simulate actual filter performance.
DS21810E-page 18
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
Example:
5-Lead SOT-23 (MCP6271 and MCP6271R)
Device
Code
MCP6271
CGNN
ETNN
XXNN
CG25
MCP6271R
Note: Applies to 5-Lead SOT-23
Example:
6-Lead SOT-23 (MCP6273)
XXNN
CK25
8-Lead MSOP
Example:
XXXXXX
YWWNNN
6271E
644256
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP6271
E/P256
0437
MCP6271
E/P^ 256
0644
e3
^
OR
YYWW
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
MCP6271
E/SN0437
MCP6271E
e
3
SN^0644
OR
NNN
256
256
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS21810E-page 19
MCP6271/1R/2/3/4/5
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6274)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP6274-E/P
0437256
YYWWNNN
OR
MCP6274
e
3
E/P^
0644256
14-Lead SOIC (150 mil) (MCP6274)
Example:
XXXXXXXXXX
XXXXXXXXXX
MCP6274ESL
0437256
YYWWNNN
OR
MCP6274
e
3
E/SL^
0644256
Example:
14-Lead TSSOP (MCP6274)
XXXXXX
YYWW
6274EST
0437
NNN
256
DS21810E-page 20
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
B
p1
D
n
1
α
c
A
A2
φ
L
A1
β
Units
INCHES
NOM
*
MILLIMETERS
NOM
5
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
5
.038
0.95
p1
Outside lead pitch (basic)
Overall Height
.075
.046
.043
.003
.110
.064
.116
.018
1.90
A
A2
A1
E
.035
.057
0.90
1.18
1.45
1.30
0.15
3.00
1.75
3.10
0.55
Molded Package Thickness
Standoff
.035
.000
.102
.059
.110
.014
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
1.10
0.08
Overall Width
2.80
Molded Package Width
Overall Length
E1
D
1.63
2.95
Foot Length
L
f
0.45
Foot Angle
0
5
0
5
10
c
Lead Thickness
Lead Width
.004
.014
.006
.017
.008
.020
10
0.09
0.35
0.15
0.43
0.20
0.50
B
a
Mold Draft Angle Top
Mold Draft Angle Bottom
0
0
5
5
0
5
5
10
10
b
10
0
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-091
© 2006 Microchip Technology Inc.
DS21810E-page 21
MCP6271/1R/2/3/4/5
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
B
p1
D
n
1
α
c
A
φ
A2
A1
β
L
Units
INCHES
*
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
MIN
NOM
6
MAX
n
p
Number of Pins
Pitch
6
.038 BSC
.075 BSC
0.95 BSC
1.90 BSC
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
p1
Outside lead pitch
Overall Height
A
A2
A1
E
.035
.035
.000
.102
.059
.110
.014
.046
.043
.003
.110
.064
.116
.018
.057
0.90
1.45
Molded Package Thickness
Standoff
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
1.30
0.15
3.00
1.75
3.10
0.55
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
φ
Foot Angle
0
5
0
10
c
Lead Thickness
Lead Width
.004
.014
.006
.017
.008
.020
10
0.09
0.35
0.15
0.43
5
0.20
0.50
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
0
5
5
0
0
10
10
10
5
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
Revised 09-12-05
DS21810E-page 22
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
2
b
1
e
c
ϕ
A2
A
L1
L
A1
Units
MILLIMETERS
Dimension Limits
NOM
8
MAX
MIN
Number of Pins
Pitch
N
e
0.65 BSC
—
—
Overall Height
A
1.10
0.95
0.15
0.75
0.00
0.85
Molded Package Thickness
Standoff
A2
A1
E
—
4.90 BSC
3.00 BSC
3.00 BSC
0.60
Overall Width
Molded Package Width
Overall Length
Foot Length
E1
D
0.40
L
0.80
0.95 REF
—
Footprint
L1
0°
Foot Angle
ϕ
8°
0.08
0.22
—
Lead Thickness
Lead Width
c
0.23
0.40
—
b
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
© 2006 Microchip Technology Inc.
DS21810E-page 23
MCP6271/1R/2/3/4/5
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21810E-page 24
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
© 2006 Microchip Technology Inc.
DS21810E-page 25
MCP6271/1R/2/3/4/5
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.145
3.68
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS21810E-page 26
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
14
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
A2
A1
E
.052
.004
.228
.150
.337
.010
.016
0
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
Standoff
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
Revised 7-20-06
© 2006 Microchip Technology Inc.
DS21810E-page 27
MCP6271/1R/2/3/4/5
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
A1
A2
Units
INCHES
NOM
MILLIMETERS
NOM
14
*
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
14
.026 BSC
.041
0.65 BSC
1.05
Overall Height
A
A2
A1
E
.039
.033
.002
.246
.169
.193
.020
.043
1.00
1.10
Molded Package Thickness
Standoff
.035
.004
.251
.173
.197
.024
.037
.006
.256
.177
.201
.028
0.85
0.05
6.25
4.30
4.90
0.50
0.90
0.95
0.15
6.50
4.50
5.10
0.70
0.10
Overall Width
6.38
Molded Package Width
Molded Package Length
Foot Length
E1
D
4.40
5.00
L
0.60
φ
Foot Angle
0°
4°
8°
0°
4°
0.15
0.25
12° REF
12° REF
8°
c
Lead Thickness
.004
.007
.006
.010
.008
.012
0.09
0.19
0.20
0.30
Lead Width
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
12° REF
12° REF
β
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
Revised: 08-17-05
DS21810E-page 28
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
APPENDIX A: REVISION HISTORY
Revision E (December 2006)
The following is the list of modifications:
1. Updated specifications (Section 1.0 “Electrical
Characteristics”):
a) Clarified Absolute Maximum Analog Input
Voltage and Current specifications.
b) Clarified VCMR
specifications.
,
VOL
,
VOH
,
and PM
c) Corrected the typical Eni.
2. Added plots on Common Mode Input Range
behavior vs. temperature and supply voltage
(Section 2.0 “Typical Performance Curves”).
3. Added applications writeup on unused op amps
and corrected description of floating CS pin
behavior (Section 4.0 “Application Informa-
tion”).
4. Updated package information (Section 6.0
“Packaging Information”):
a) Corrected package markings.
b) Added disclaimer to package outline
drawings.
Revision D (December 2004)
The following is the list of modifications:
1. Added SOT-23-5 packages for the DSTEMP
and MCP6271R single op amps.
2. Added SOT-23-6 packages for the DSTEMP
single op amp.
3. Added Section 3.0 “Pin Descriptions”.
4. Corrected application circuits
(Section 4.9 “Application Circuits”).
5. Added SOT-23-5 and SOT-23-6 packages and
corrected
package
marking
information
(Section 6.0 “Packaging Information”).
6. Added Appendix A: Revision History.
Revision C (June 2004)
Revision B (October 2003)
Revision A (June 2003)
• Original data sheet release.
© 2006 Microchip Technology Inc.
DS21810E-page 29
MCP6271/1R/2/3/4/5
NOTES:
DS21810E-page 30
© 2006 Microchip Technology Inc.
MCP6271/1R/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
–
a)
b)
c)
d)
MCP6271-E/SN:
Extended Temperature,
8LD SOIC package.
Temperature
Range
Package
MCP6271-E/MS: Extended Temperature,
8LD MSOP package.
MCP6271-E/P:
Extended Temperature,
8LD PDIP package.
Device:
MCP6271:
MCP6271T:
Single Op Amp
Single Op Amp
(Tape and Reel)
(SOIC, MSOP, SOT-23-5)
Single Op Amp
(Tape and Reel) (SOT-23-5)
Dual Op Amp
Dual Op Amp
MCP6271T-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
MCP6271RT:
a)
MCP6271RT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
MCP6272:
MCP6272T:
(Tape and Reel) (SOIC, MSOP)
Single Op Amp with Chip Select
Single Op Amp with Chip Select
(Tape and Reel)
(SOIC, MSOP, SOT-23-6)
Quad Op Amp
a)
b)
c)
d)
MCP6272-E/SN:
Extended Temperature,
8LD SOIC package.
MCP6273:
MCP6273T:
MCP6272-E/MS: Extended Temperature,
8LD MSOP package.
MCP6272-E/P:
Extended Temperature,
8LD PDIP package.
MCP6274:
MCP6274T:
Quad Op Amp
MCP6272T-E/SN: Tape and Reel,
Extended Temperature,
(Tape and Reel) (SOIC, TSSOP)
Dual Op Amp with Chip Select
Dual Op Amp with Chip Select
(Tape and Reel) (SOIC, MSOP)
MCP6275:
MCP6275T:
8LD SOIC package.
a)
b)
c)
d)
MCP6273-E/SN:
Extended Temperature,
8LD SOIC package.
Temperature Range:
Package:
E
=
-40°C to +125°C
MCP6273-E/MS: Extended Temperature,
8LD MSOP package.
MCP6273-E/P:
Extended Temperature,
8LD PDIP package.
OT
CH
=
=
Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6271, MCP6271R)
Plastic Small Outline Transistor (SOT-23), 6-lead
(MCP6273)
MCP6273T-E/CH: Extended Temperature,
6LD SOT-23 package.
MS
P
SN
SL
ST
=
=
=
=
=
Plastic MSOP, 8-lead
a)
b)
MCP6274-E/P:
Extended Temperature,
14LD PDIP package.
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC, (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP (4.4 mm Body), 14-lead
MCP6274T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC package.
Extended Temperature,
14LD SOIC package.
Extended Temperature,
14LD TSSOP package.
c)
d)
MCP6274-E/SL:
MCP6274-E/ST:
a)
b)
c)
d)
MCP6275-E/SN:
Extended Temperature,
8LD SOIC package.
MCP6275-E/MS: Extended Temperature,
8LD MSOP package.
MCP6275-E/P:
Extended Temperature,
8LD PDIP package.
MCP6275T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
© 2006 Microchip Technology Inc.
DS21810E-page 31
MCP6271/1R/2/3/4/5
NOTES:
DS21810E-page 32
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21810E-page 33
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS21810E-page 34
© 2006 Microchip Technology Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明