MCP631_14 [MICROCHIP]
Unity-Gain Stable;
| 型号： | MCP631_14 |
| 厂家： | 
MICROCHIP |
| 描述： | Unity-Gain Stable |
| 文件： | 总60页 (文件大小：1906K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP631/2/3/4/5/9
24 MHz, 2.5 mA Rail-to-Rail Output (RRO) Op Amps
Features:
Description:
• Gain-Bandwidth Product: 24 MHz
• Slew Rate: 10 V/µs
The Microchip Technology Inc. MCP631/2/3/4/5/9
family of operational amplifiers features high gain
bandwidth product (24 MHz, typical) and high output
short-circuit current (70 mA, typical). Some also
provide a Chip Select (CS) pin that supports a
low-power mode of operation. These amplifiers are
optimized for high speed, low noise and distortion,
single-supply operation with rail-to-rail output and an
input that includes the negative rail.
• Noise: 10 nV/Hz at 1 MHz)
• Low Input Bias Current: 4 pA (typical)
• Ease of Use:
- Unity-Gain Stable
- Rail-to-Rail Output
- Input Range including Negative Rail
- No Phase Reversal
This family is offered in single (MCP631), single with
CS pin (MCP633), dual (MCP632), dual with two CS
pins (MCP635), quad (MCP634) and quad with two
Chip Select pins (MCP639). All devices are fully
specified from -40°C to +125°C.
• Supply Voltage Range: +2.5V to +5.5V
• High Output Current: ±70 mA
• Supply Current: 2.5 mA/ch (typical)
• Low-Power Mode: 1 µA/ch
• Small Packages: SOT23-5, DFN
• Extended Temperature Range: -40°C to +125°C
Typical Application Circuit
MCP63X
0A – 20 A
Typical Applications:
+5V
• Fast Low-Side Current Sensing
• Point-of-Load Control Loops
• Power Amplifier Control Loops
• Barcode Scanners
51.1
+
VOUT
-
0V – 4V
0.005
• Optical Detector Amplifier
• Multi-Pole Active Filter
51.1
2.0 k
Design Aids:
• SPICE Macro Models
• FilterLab® Software
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
High Gain-Bandwidth Op Amp Portfolio
Model Family
Channels/Package
Gain-Bandwidth
VOS (max.)
IQ/Ch (typ.)
MCP621/1S/2/3/4/5/9
MCP631/2/3/4/5/9
1, 2, 4
1, 2, 4
20 MHz
24 MHz
50 MHz
60 MHz
0.2 mV
8.0 mV
0.2 mV
8.0 mV
2.5 mA
2.5 mA
6.0 mA
6.0 mA
MCP651/1S/2/3/4/5/9
MCP660/1/2/3/4/5/9
1, 2, 4
1, 2, 3, 4
2009-2014 Microchip Technology Inc.
DS20002197C-page 1
MCP631/2/3/4/5/9
Package Types
MCP631
MCP631
MCP631
MCP634
SOIC
2x3 TDFN*
SOT-23-5
SOIC, TSSOP
1
2
3
4
8
NC
NC
V
V
NC
NC
V
1
2
8
7
V
OUTA
1
2
3
4
5
6
7
14
13
12
11
10
9
OUTD
V
V
V
1
2
3
5
4
DD
OUT
7
6
5
V
–
V
V
V
-
V
-
V
–
IN
IN
DD
INA
IND
EP
9
IN
DD
V
V
+
SS
V
+
V
OUT
+
INA
V
+
V
IND
3
4
6
5
IN
OUT
V
V
NC
DD
SS
V
NC
SS
SS
V
+
-
IN
IN
V
+
V
V
V
+
INB
INC
V
-
-
INB
INC
V
8
OUTB
OUTC
MCP632
SOIC
MCP632
3x3 DFN*
MCP633
SOT-23-6
MCP633
SOIC
V
1
2
3
4
8
7
6
5
V
V
DD
1
2
3
4
8
7
6
5
NC
CS
V
1
2
3
4
8
7
6
5
V
DD
OUTA
V
6
5
4
OUTA
V
OUT
1
DD
V
V
V
V
–
+
V
V
V
V
–
V
–
+
OUTB
INA
OUTB
IN
IN
DD
EP
9
INA
CS
2
3
V
SS
V
+
V
OUT
-
V
–
V
INA
INB
INB
INA
+
V
NC
V
V
+
INB
SS
SS
SS
INB
V
-
V
+
IN
IN
MCP639
4x4 QFN*
MCP635
MSOP
MCP635
3x3 DFN*
16 15 14 13
V
10
V
1
2
3
DD
OUTA
V
-
V
+
1
10
9
8
7
6
1
12
11
10
9
V
V
V
V
DD
INA
IND
OUTA
V
–
+
V
OUTB
9
8
7
6
INA
2
3
4
5
–
+
V
V
V
INA
OUTB
V
+
V
V
V
2
3
4
INA
SS
EP
17
V
EP
11
V
V
-
-
+
INA
INB
INA
INB
+
-
V
INC
INC
DD
V
V
+
SS
INB
SS 4
INB
V
+
INB
CSA
CSB
CSA
CSB
5
5
6
7
8
* Includes Exposed Thermal Pad (EP); see Table 3-1.
DS20002197C-page 2
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
– V
.......................................................................6.5V
SS
DD
Current at Input Pins ....................................................±2 mA
Analog Inputs (V + and V –) †† . V – 1.0V to V + 1.0V
†† See Section 4.1.2 “Input Voltage and Current Limits”.
IN
IN
SS
DD
All other Inputs and Outputs .......... V – 0.3V to V + 0.3V
SS
DD
Output Short-Circuit Current ................................Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Maximum Junction Temperature ................................+150°C
ESD protection on all pins (HBM, MM) 1 kV, 200V
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /3,
DD
A
DD
SS
CM
V
V /2, V = V /2, R = 2 k to V and CS = V (refer to Figure 1-2).
OUT
DD
L
DD
L
L
SS
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset
Input Offset Voltage
Input Offset Voltage Drift
V
-8
—
61
±1.8
±2.0
76
+8
—
—
mV
OS
V /T
µV/°C T = -40°C to +125°C
OS
A
A
Power Supply Rejection Ratio
Input Current and Impedance
Input Bias Current
PSRR
dB
I
I
I
—
—
—
—
—
—
4
—
—
pA
B
B
B
Across Temperature
100
1500
±2
pA
pA
T = +85°C
A
Across Temperature
5000
—
T = +125°C
A
Input Offset Current
I
pA
OS
13
Common-Mode Input Impedance
Differential Input Impedance
Common Mode
Z
10 ||9
—
||pF
||pF
CM
13
Z
10 ||2
—
DIFF
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
V
V
0.3
—
78
81
V
1.3
DD
V
Note 1
CMR
SS
CMRR
63
66
—
dB
dB
V
V
= 2.5V, V
= 5.5V, V
= -0.3V to 1.2V
= -0.3V to 4.2V
DD
DD
CM
—
CM
Open-Loop Gain
DC Open-Loop Gain (large signal)
A
88
94
115
124
—
—
dB
dB
V
V
= 2.5V, V
= 5.5V, V
= 0.3V to 2.2V
= 0.3V to 5.2V
OL
DD
DD
OUT
OUT
Output
Maximum Output Voltage Swing
V
, V
V
V
+ 20
—
—
V
V
20
mV
mV
V
= 2.5V, G = +2,
DD
OL
OH
SS
DD
DD
0.5V Input Overdrive
V = 5.5V, G = +2,
DD
+ 40
40
SS
0.5V Input Overdrive
Output Short-Circuit Current
I
I
±40
±85
±70
±130
±110
mA
mA
V
V
= 2.5V (Note 2)
= 5.5V (Note 2)
SC
SC
DD
DD
±35
Power Supply
Supply Voltage
V
2.5
1.2
—
5.5
3.6
V
DD
Quiescent Current per Amplifier
I
2.5
mA
No Load Current
Q
Note 1: See Figure 2-5 for temperature effects.
2: The I specifications are for design guidance only; they are not tested.
SC
2009-2014 Microchip Technology Inc.
DS20002197C-page 3
MCP631/2/3/4/5/9
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2,
DD
A
DD
SS
CM
V
V /2, V = V /2, R = 2 k to V , C = 50 pF and CS = V (refer to Figure 1-2).
DD L DD L L L SS
OUT
Parameters
Sym.
Min.
Typ. Max. Units
Conditions
AC Response
Gain-Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
24
65
20
—
—
—
MHz
°
G = +1
Open-Loop Output Impedance
AC Distortion
R
OUT
Total Harmonic Distortion plus Noise
THD + N
—
0.0015
—
%
G = +1, V
= 2V , f = 1 kHz,
OUT P-P
V
= 5.5V, BW = 80 kHz
DD
Step Response
Rise Time, 10% to 90%
Slew Rate
t
—
—
20
10
—
—
ns
G = +1, V
= 100 mV
OUT P-P
r
SR
V/µs G = +1
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
E
e
—
—
16
10
4
—
—
—
µV
f = 0.1 Hz to 10 Hz
ni
P-P
nV/Hz f = 1 MHz
fA/Hz f = 1 kHz
ni
i
ni
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /2,
DD
A
DD
SS
CM
V
V /2, V = V /2, R = 2 k to V , C = 50 pF and CS = V (refer to Figures 1-1 and 1-2).
OUT
DD L DD L L L SS
Parameters
Sym.
Min.
Typ.
Max. Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
CS Input Current, Low
CS High Specifications
CS Logic Threshold, High
CS Input Current, High
GND Current
V
V
—
0.2V
—
V
IL
SS
DD
I
—
0.1
nA
CS = 0V
CSL
V
0.8V
V
DD
V
IH
DD
I
—
-2
0.7
-1
—
µA
µA
M
nA
CS = V
DD
CSH
I
—
—
—
SS
CS Internal Pull-Down Resistor
Amplifier Output Leakage
CS Dynamic Specifications
CS Input Hysteresis
R
—
—
5
PD
O(LEAK)
I
50
CS = V , T = +125°C
DD A
—
—
—
—
V
0.25
200
V
HYST
CS High to Amplifier Off Time
(output goes High Z)
t
ns
G = +1 V/V, V = V
CS = 0.8V to V
,
OFF
L
SS
= 0.1(V /2)
DD
DD
OUT
G = +1 V/V, V = V ,
SS
CS Low to Amplifier On Time
t
—
2
10
µs
L
ON
CS = 0.2V to V
= 0.9(V /2)
DD
DD
OUT
DS20002197C-page 4
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V = +2.5V to +5.5V, V = GND.
DD
SS
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max. Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
T
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
A
T
Note 1
A
T
A
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 6L-SOT-23
Thermal Resistance, 8L-2x3 TDFN
Thermal Resistance, 8L-3x3 DFN
Thermal Resistance, 8L-SOIC
θ
θ
θ
θ
θ
θ
θ
θ
θ
θ
—
—
—
—
—
—
—
—
—
—
201.0
190.5
52.5
56.7
149.5
54.0
202
—
—
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
JA
JA
JA
JA
JA
JA
JA
JA
JA
JA
°C/W Note 2
°C/W
Thermal Resistance, 10L-3x3 DFN
Thermal Resistance, 10L-MSOP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
Thermal Resistance, 16L-4x4-QFN
°C/W Note 2
°C/W
90.8
100
°C/W
°C/W
52.1
°C/W Note 2
Note 1: Operation must not cause T to exceed Maximum Junction Temperature specification (+150°C).
J
2: Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.
EQUATION 1-1:
1.3
Timing Diagram
RF
GDM = ------
0.1 nA
(typical)
RG
0.7 µA
(typical)
0.7 µA
(typical)
ICS
CS
GN = 1 + GDM
1
GN
1
VIH
VIL
VCM = V 1 – ------- + V
P
-------
REF
GN
tON
tOFF
VOST = VIN- – VIN+
VOUT
High Z
High Z
On
VOUT = VREF + VP – VMGDM + VOSTGN
-2.5 mA
(typical)
-1 µA
(typical)
-1 µA
(typical)
ISS
Where:
GDM = Differential Mode Gain
GN = Noise Gain
(V/V)
(V/V)
(V)
FIGURE 1-1:
Timing Diagram.
1.4 Test Circuits
VCM = Op Amp’s Common-Mode
Input Voltage
The circuit used for most DC and AC tests is shown in
Figure 1-2. It independently sets VCM and VOUT; see
Equation 1-1. The circuit’s Common-Mode voltage is
(VP + VM)/2, not VCM. VOST includes VOS plus the
VOST = Op Amp’s Total Input Offset
Voltage
(mV)
effects of temperature, CMRR, PSRR and AOL
.
2009-2014 Microchip Technology Inc.
DS20002197C-page 5
MCP631/2/3/4/5/9
CF
6.8 pF
RG
RF
10 k
10 k
VREF = VDD/2
VDD
VP
VIN+
CB1
CB2
MCP63X
100 nF
2.2 µF
VIN-
VOUT
VM
RL
CL
RG
RF
2 k
50 pF
10 k
10 k
CF
6.8 pF
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Specifications.
DS20002197C-page 6
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
2.1
DC Signal Inputs
14%
12%
10%
8%
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
-2.2
-2.4
-2.6
-2.8
-3.0
396 Samples
TA = +25°C
VDD = 2.5V and 5.5V
Representative Part
VDD = 2.5V
VDD = 5.5V
6%
4%
2%
0%
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (mV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Output Voltage.
16%
0.0
398 Samples
1 Lot
VDD = 2.5V and 5.5V
TA = -40°C to +125°C
14%
12%
10%
8%
Low (VCMR_L – VSS
)
-0.1
-0.2
-0.3
-0.4
-0.5
6%
VDD = 2.5V and 5.5V
4%
2%
0%
-8 -7 -6 -5 -4 -3 -2 -1
0 1 2 3 4 5 6 7 8
-50
-25
0
25
50
75
100 125
Input Offset Voltage Drift (µV/°C)
Ambient Temperature (°C)
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5:
Low-Input Common-Mode
Voltage Headroom vs. Ambient Temperature.
-2.0
-2.2
-2.4
-2.6
-2.8
-3.0
-3.2
-3.4
-3.6
-3.8
-4.0
1.3
Representative Part
1 Lot
High (VDD – VCMR_H
VCM = VSS
)
1.2
1.1
1.0
0.9
VDD = 2.5V
+125°C
+85°C
+25°C
-40°C
VDD = 5.5V
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
High-Input Common-Mode
Power Supply Voltage with VCM = 0V.
Voltage Headroom vs. Ambient Temperature.
2009-2014 Microchip Technology Inc.
DS20002197C-page 7
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
2.0
130
125
120
115
110
105
100
VDD = 2.5V
Representative Part
1.5
1.0
+125°C
+85°C
+25°C
-40°C
VDD = 5.5V
VDD = 2.5V
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Input Common Mode Voltage (V)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
DC Open-Loop Gain vs.
Common-Mode Voltage with VDD = 2.5V.
Ambient Temperature.
2.0
130
VDD = 5.5V
VDD = 5.5V
Representative Part
1.5
125
120
115
110
105
100
95
1.0
+125°C
+85°C
+25°C
-40°C
0.5
0.0
VDD = 2.5V
-0.5
-1.0
-1.5
-2.0
100
1k
1.E+03
Load Resistance (Ω)
10k
1.E+04
100k
1.E+05
1.E+02
Input Common Mode Voltage (V)
FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
DC Open-Loop Gain vs.
Common-Mode Voltage with VDD = 5.5V.
Load Resistance.
110
105
100
1.E1-008n
VDD = 5.5V
VCM = VCMR_H
1n
1.E-09
95
CMRR, VDD = 2.5V
90
85
80
75
70
65
60
CMRR, VDD = 5.5V
IB
100p
1.E-10
10p
1.E-11
PSRR
| IOS
|
1p
1.E-12
-50
-25
0
25
50
75
100
125
25
45
65
85
105
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-9:
CMRR and PSRR vs.
FIGURE 2-12:
Input Bias and Offset
Ambient Temperature.
Currents vs. Ambient Temperature with
DD = 5.5V.
V
DS20002197C-page 8
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
1.E-10m3
1.E10-004µ
1.E1-005µ
1µ
1.E-06
100n
1.E-07
10n
1.E- 8
1n
1.E-09
+125°C
+85°C
+25°C
-40°C
100p
1.E-10
10p
1.E-11
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-13:
Input Bias Current vs. Input
Voltage (below VSS).
200
150
100
50
IB
0
IOS
-50
-100
-150
-200
Representative Part
A = +85°C
VDD = 5.5V
T
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common-Mode Input Voltage with
TA = +85°C.
2000
IB
1500
1000
500
IOS
0
-500
Representative Part
T
A = +125°C
-1000
-1500
VDD = 5.5V
Common Mode Input Voltage (V)
FIGURE 2-15:
Input Bias and Offset
Currents vs. Common-Mode Input Voltage with
TA = +125°C.
2009-2014 Microchip Technology Inc.
DS20002197C-page 9
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
2.2
Other DC Voltages and Currents
1000
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.5V
100
10
1
+125°C
+85°C
+25°C
-40°C
VDD = 2.5V
VOL – VSS
VDD – VOH
0.1
1
10
100
Output Current Magnitude (mA)
Power Supply Voltage (V)
FIGURE 2-16:
Output Voltage Headroom
FIGURE 2-19:
Supply Current vs. Power
vs. Output Current.
Supply Voltage.
20
3.5
3.0
2.5
2.0
RL = 2 kΩ
18
VDD = 5.5V
16
14
12
VOL – VSS
VDD = 2.5V
VDD = 5.5V
10
1.5
1.0
0.5
0.0
8
6
4
2
0
VDD = 2.5V
VDD – VOH
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Common Mode Input Voltage (V)
FIGURE 2-17:
Output Voltage Headroom
FIGURE 2-20:
Supply Current vs.
vs. Ambient Temperature.
Common-Mode Input Voltage.
100
80
60
+125°C
+85°C
+25°C
-40°C
40
20
0
-20
-40
-60
-80
-100
Power Supply Voltage (V)
FIGURE 2-18:
Output Short-Circuit Current
vs. Power Supply Voltage.
DS20002197C-page 10
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
2.3
Frequency Response
100
90
80
70
60
50
40
30
20
10
36
34
32
30
28
26
24
22
20
80
75
70
65
60
55
50
45
40
PM
VDD = 5.5V
VDD = 2.5V
CMRR
PSRR+
PSRR-
GBWP
100
11.Ek+3
10k
100k
1M
10M
1.E+7
1.E+2
1.E+4
1.E+5
1.E+6
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-21:
CMRR and PSRR vs.
FIGURE 2-24:
Gain-Bandwidth Product
Frequency.
and Phase Margin vs. Common-Mode Input
Voltage.
140
120
100
80
0
36
34
32
30
28
26
24
22
20
80
-30
75
70
65
60
55
50
45
40
PM
-60
-90
AOL
VDD = 5.5V
VDD = 2.5V
60
-120
-150
-180
-210
-240
40
| AOL
|
20
0
GBWP
-20
1
10 100 1k 10k 100k 11.EM+6 10M 100M
1.E+7 1.E+8
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Frequency (Hz)
FIGURE 2-22:
Open-Loop Gain vs.
FIGURE 2-25:
Gain-Bandwidth Product
Frequency.
and Phase Margin vs. Output Voltage.
36
34
32
30
80
75
70
65
60
55
50
45
40
100
PM
G = 101 V/V
G = 11 V/V
G = 1 V/V
10
VDD = 5.5V
VDD = 2.5V
28
26
24
22
20
1
GBWP
0.1
10k
100k
1.0E+05
1M
10M
1.0E+07
100M
-50 -25
0
25
50
75 100 125
1.0E+04
1.0E+06
1.0E+08
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-23:
Gain-Bandwidth Product
FIGURE 2-26:
Closed-Loop Output
and Phase Margin vs. Ambient Temperature.
Impedance vs. Frequency.
2009-2014 Microchip Technology Inc.
DS20002197C-page 11
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
10
9
150
140
130
120
110
100
90
RS = 0Ω
RS = 100Ω
RS = 1 kΩ
8
GN = 1 V/V
GN = 2 V/V
7
GN 4 V/V
6
5
4
3
2
1
0
VCM = VDD/2
G = +1 V/V
80
70
RS = 10 kΩ
RS = 100 kΩ
60
50
1k
10k
1.E+04
100k
1.E+05
1M
1.E+06
10M
1.E+07
10p
1.0E-11
100p
1.0E-10
1n
1.0E-09
1.E+03
Normalized Capacitive Load; CL/GN (F)
Frequency (Hz)
FIGURE 2-27:
Gain Peaking vs.
FIGURE 2-28:
Channel-to-Channel
Normalized Capacitive Load.
Separation vs. Frequency.
DS20002197C-page 12
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
2.4
Noise and Distortion
1.E+4
10µ
20
15
10
5
Representative Part
1.E+3
1µ
0
110.E0+n2
11.E0+n1
-5
-10
-15
-20
Analog NPBW = 0.1 Hz
Sample Rate = 2 SPS
VOS = -3150 µV
1n
1.E+0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
0.1
1
10 100 1k 10k 100k 11.EM+6 10M
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+7
Frequency (Hz)
Time (min)
FIGURE 2-29:
Input Noise Voltage Density
FIGURE 2-32:
Input Noise vs. Time with
vs. Frequency.
0.1 Hz Filter.
200
180
1
VDD = 2.5V
160
140
120
100
80
0.1
G = 1 V/V
G = 11 V/V
BW = 22 Hz to > 500 kHz
VDD = 5.5V
0.01
0.001
60
40
BW = 22 Hz to 80 kHz
VDD = 5.0V
20
f = 100 Hz
VOUT = 2 VP-P
0
0.0001
100
1.E+2
1k
1.E+3
10k
1.E+4
100k
1.E+5
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-30:
Input Noise Voltage Density
FIGURE 2-33:
THD+N vs. Frequency.
vs. Input Common-Mode Voltage with
f = 100 Hz.
20
18
16
VDD = 2.5V
14
12
VDD = 5.5V
10
8
6
4
2
f = 1 MHz
0
Common Mode Input Voltage (V)
FIGURE 2-31:
Input Noise Voltage Density
vs. Input Common-Mode Voltage with f = 1 MHz.
2009-2014 Microchip Technology Inc.
DS20002197C-page 13
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
2.5
Time Response
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.5V
G = 1
VDD = 5.5V
G = -1
RF = 1 kΩ
VIN
VIN
VOUT
VOUT
0.0
0.1
0.2
0.3
0.4
Time (µs)
0.5
0.6
0.7
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (µs)
FIGURE 2-34:
Non-Inverting Small Signal
FIGURE 2-37:
Inverting Large Signal Step
Step Response.
Response.
5.5
5.0
4.5
4.0
3.5
3.0
7
6
VDD = 5.5V
G = 2
VDD = 5.5V
G = 1
VOUT
5
VIN
4
3
2.5
VIN
VOUT
2
2.0
1.5
1.0
0.5
0.0
1
0
-1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (µs)
0
1
2
3
4
5
6
7
8
9
10
Time (ms)
FIGURE 2-35:
Step Response.
Non-Inverting Large Signal
FIGURE 2-38:
Family Shows No Input Phase Reversal With
Overdrive.
The MCP631/2/3/4/5/9
24
22
Falling Edge
VIN
20
18
VDD = 5.5V
16
VDD = 5.5V
G = -1
RF = 1 kΩ
VDD = 2.5V
14
12
10
8
6
4
2
Rising Edge
VOUT
0
-50
-25
0
25
50
75
100
125
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Ambient Temperature (°C)
Time (µs)
FIGURE 2-39:
Slew Rate vs. Ambient
FIGURE 2-36:
Inverting Small Signal Step
Temperature.
Response.
DS20002197C-page 14
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
10
VDD = 5.5V
VDD = 2.5V
1
0.1
100k
1M
1.E+06
10M
1.E+07
100M
1.E+08
1.E+05
Frequency (Hz)
FIGURE 2-40:
Maximum Output Voltage
Swing vs. Frequency.
2009-2014 Microchip Technology Inc.
DS20002197C-page 15
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
2.6
Chip Select Response
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
CS = VDD
VDD = 5.5V
VDD = 2.5V
-50
-25
0
25
50
75
100
125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-41:
CS Current vs. Power
FIGURE 2-44:
CS Hysteresis vs. Ambient
Supply Voltage.
Temperature.
3.0
5
4
3
2
1
0
VDD = 2.5V
G = 1
VL = 0V
2.5
CS
2.0
1.5
1.0
0.5
VDD = 2.5V
VOUT
On
VDD = 5.5V
0.0
Off
Off
-0.5
-50
-25
0
25
50
75
100
125
0
2
4
6
8
10 12 14 16 18 20
Time (µs)
Ambient Temperature (°C)
FIGURE 2-42:
CS and Output Voltages vs.
FIGURE 2-45:
CS Turn-On Time vs.
Time with VDD = 2.5V.
Ambient Temperature.
6
8
VDD = 5.5V
G = 1
VL = 0V
Representative Part
CS
7
6
5
4
3
2
1
0
5
4
3
VOUT
2
On
1
0
Off
Off
-1
-50
-25
0
25
50
75
100
125
0
2
4
6
8
10 12 14 16 18 20
Time (µs)
Ambient Temperature (°C)
FIGURE 2-43:
CS and Output Voltages vs.
FIGURE 2-46:
CS Pull-Down Resistor
Time with VDD = 5.5V.
(RPD) vs. Ambient Temperature.
DS20002197C-page 16
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS
.
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
1.E-016µ
1.E10-007n
CS = VDD
CS = VDD = 5.5V
+125°C
+85°C
10n
1.E-08
-1.2
-1.4
-40°C
+25°C
1n
1.E-09
-1.6
-1.8
-2.0
-2.2
+85°C
+125°C
100p
1.E-10
+25°C
10p
1.E-11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
Power Supply Voltage (V)
FIGURE 2-47:
Quiescent Current in
FIGURE 2-48:
Output Leakage Current vs.
Shutdown vs. Power Supply Voltage.
Output Voltage.
2009-2014 Microchip Technology Inc.
DS20002197C-page 17
MCP631/2/3/4/5/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Description
SOT 2x3
-23 TDFN
3x3
DFN
SOT-
23
3x3
DFN
SOIC
2
SOIC
2
SOIC
2
SOIC TSSOP MSOP
QFN
1
4
2
2
4
2
3
2
3
2
3
2
VIN-,
VINA
VIN+, Non-Inverting Input (op
Inverting Input (op amp A)
-
3
3
3
3
3
3
3
3
2
VINA
VDD
VINB
+
amp A)
7
5
7
8
5
8
5
7
6
4
5
4
5
10
7
10
7
3
4
Positive Power Supply
—
—
—
—
—
+
Non-Inverting Input (op
amp B)
—
—
—
—
—
—
—
—
—
6
7
6
7
—
—
—
—
—
—
6
7
6
7
8
9
8
9
5
6
7
VINB
-
Inverting Input (op amp B)
VOUTB Output (op amp B)
—
—
—
—
—
—
CSBC Chip Select Digital Input
(op amp B and C)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
9
8
9
—
—
—
—
—
—
8
9
VOUTC Output (op amp C)
VINC
-
Inverting Input (op amp C)
10
10
10
VINC
+
Non-Inverting Input (op
amp C)
4
2
4
4
4
4
2
11
12
11
12
4
4
11
12
VSS
VIND
Negative Power Supply
—
—
—
—
—
—
—
—
—
+
Non-Inverting Input (op
amp D)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
14
—
13
14
—
—
—
—
—
—
—
13
14
15
VIND
-
Inverting Input (op amp D)
VOUTD Output (op amp D)
CSAD Chip Select Digital Input
(op amp A and D)
6
1
6
9
1
1
9
6
1
1
1
1
1
16
17
VOUT
VOUTA
,
Output (op amp A)
—
—
—
—
—
—
—
—
11
EP
Exposed Thermal Pad
(EP); must be connected to
VSS
—
—
—
—
—
—
—
8
5
—
—
5
5
—
CS, CSA Chip Select Digital Input
(op amp A)
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
—
—
CSB
Chip Select Digital Input
(op amp B)
1,5,
8
1, 5,
8
1, 5
—
—
NC
No Internal Connection
DS20002197C-page 18
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
3.1
Analog Outputs
3.4
Chip Select Digital Input (CS)
This input (CS) is a CMOS, Schmitt-triggered input that
places the part into a low-power mode of operation.
The analog output pins (VOUT) are low-impedance
voltage sources.
3.5
Exposed Thermal Pad (EP)
3.2
Analog Inputs
There is an internal connection between the exposed
thermal pad (EP) and the VSS pin; they must be
connected to the same potential on the printed circuit
board (PCB).
The non-inverting and inverting inputs (VIN+, VIN-, …)
are high-impedance CMOS inputs with low bias
currents.
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (JA).
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
Typically, these parts are used in a single (positive)
supply configuration. In that case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
2009-2014 Microchip Technology Inc.
DS20002197C-page 19
MCP631/2/3/4/5/9
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
4.0
APPLICATIONS
The MCP631/2/3/4/5/9 family is manufactured using
the Microchip state-of-the-art CMOS process. It is
designed for low-cost, low-power and high-speed
applications. Its low supply voltage, low quiescent
VDD
D1
R1
D2
current
MCP631/2/3/4/5/9
applications.
and
wide
ideal
bandwidth
for
make
battery-powered
the
MCP63X
VOUT
V1
V2
4.1
Input
PHASE REVERSAL
R2
4.1.1
VSS – minimum expected V1
R1 ------------------------------------------------------------------------
The input devices are designed to exhibit no phase
inversion when the input pins exceed the supply
voltages. Figure 2-38 shows an input voltage
exceeding both supplies with no phase inversion.
2 mA
VSS – minimum expected V2
R2 ------------------------------------------------------------------------
2 mA
FIGURE 4-2:
Inputs.
Protecting the Analog
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
It is also possible to connect the diodes to the left of the
resistors R1 and R2. If so, the currents through the
diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN-) should be very small.
The electrostatic discharge (ESD) protection on the
inputs can be depicted as shown in Figure 4-1. This
structure was chosen to protect the input transistors
and to minimize input bias current (IB). The input ESD
diodes clamp the inputs when they try to go more than
one diode drop below VSS. They also clamp any
voltages that go too far above VDD; their breakdown
voltage is high enough to allow normal operation and
low enough to bypass quick ESD events within the
specified limits.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the
Common-Mode voltage (VCM) is below ground (VSS);
see Figure 2-13. Applications that are high-impedance
may need to limit the usable voltage range.
4.1.3
NORMAL OPERATION
Bond
VDD
Pad
The input stage of the MCP631/2/3/4/5/9 op amps uses
a differential PMOS input stage. It operates at low
Common-Mode input voltages (VCM), with VCM
between VSS – 0.3V and VDD – 1.3V. To ensure proper
operation, the input offset voltage (VOS) is measured at
both VCM = VSS – 0.3V and VCM = VDD – 1.3V. See
Figures 2-5 and 2-6 for temperature effects.
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN-
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
(< VDD – 1.3V); see Figure 4-3.
Bond
Pad
VSS
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
VDD
MCP63X
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-2 shows
the recommended approach to protecting these inputs.
VIN
+
-
VOUT
VSS VIN
VOUT VDD – 1.3V
FIGURE 4-3: Unity-Gain Voltage
Limitations for Linear Operation.
The internal ESD diodes prevent the input pins (VIN+
and VIN-) from going too far below ground, while the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN-) from going too far above VDD and
dump any currents onto VDD
.
DS20002197C-page 20
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Figure 4-5 shows the power calculations used for a
single op amp:
4.2
Rail-to-Rail Output
4.2.1
MAXIMUM OUTPUT VOLTAGE
• RSER is 0 in most applications and can be used
to limit IOUT
.
The maximum output voltage (see Figures 2-16
and 2-17) describes the output range for a given load.
For instance, the output voltage swings to within 50 mV
of the negative rail with a 1 k load tied to VDD/2.
• VOUT is the op amp’s output voltage.
• VL is the voltage at the load.
• VLG is the load’s ground point.
• VSS is usually ground (0V).
4.2.2
OUTPUT CURRENT
The input currents are assumed to be negligible. The
currents shown in Figure 4-5 can be approximated
using Equation 4-1:
Figure 4-4 shows the possible combinations of output
voltage (VOUT) and output current (IOUT), when
VDD = 5.5V.
IOUT is positive when it flows out of the op amp into the
external circuit.
EQUATION 4-1:
VOUT – VLG
IOUT = IL = -----------------------------
R
SER + RL
6.0
5.5
5.0
VOH Limited
(VDD = 5.5V)
IDD IQ + max0, IOUT
4.5
RL = 1 kΩ
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
RL = 100Ω
RL = 10Ω
ISS –IQ + min0, IOUT
Where:
IQ = Quiescent supply current
VOL Limited
The instantaneous op amp power (POA(t)), RSER power
(PRSER(t)) and load power (PL(t)) are:
IOUT (mA)
EQUATION 4-2:
FIGURE 4-4:
Output Current.
POA(t) = IDD (VDD – VOUT) + ISS (VSS – VOUT
)
4.2.3 POWER DISSIPATION
2
PRSER(t) = IOUT RSER
Since the output short-circuit current (ISC) is specified
at ±70 mA (typical), these op amps are capable of both
delivering and dissipating significant power.
PL(t) = IL2RL
The maximum op amp power, for resistive loads,
occurs when VOUT is halfway between VDD and VLG or
halfway between VSS and VLG
.
VDD
VOUT
EQUATION 4-3:
IDD
max2VDD – VLG VLG – VSS
IOUT
RSER
+
POAmax -------------------------------------------------------------------------
4RSER + RL
VL
-
MCP63X
IL
RL
The maximum ambient to junction temperature rise
(TJA) and junction temperature (TJ) can be calculated
using POAmax, the ambient temperature (TA), the
ISS
VLG
VSS
package thermal resistance (JA, found in the
Temperature Specifications table) and the number of
op amps in the package (assuming equal power
dissipations), as shown in Equation 4-4:
FIGURE 4-5:
Calculations.
Diagram for Power
EQUATION 4-4:
TJA = POAtJA nPOAmaxJA
TJ = TA + TJA
Where:
n = Number of op amps in the package (1, 2)
2009-2014 Microchip Technology Inc.
DS20002197C-page 21
MCP631/2/3/4/5/9
The power derating across temperature for an op amp
in a particular package can be easily calculated
(assuming equal power dissipations):
Figure 4-7 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
EQUATION 4-5:
TJmax – TA
POAmax --------------------------
nJA
1,000
Where:
TJmax = Absolute maximum junction temperature
Several techniques are available to reduce TJA for a
100
given POAmax
:
• Lower JA
GN = +1
- Use another package
- PCB layout (ground plane, etc.)
- Heat sinks and air flow
• Reduce POAmax
GN +2
10
10p
100p
1.E-11
1n
1.E-09
10n
1.E-08
1.E-12
1.E-10
Normalized Capacitance; CL/GN (F)
FIGURE 4-7:
for Capacitive Loads.
Recommended RISO Values
- Increase RL
- Limit IOUT (using RSER
)
After selecting RISO
, double-check the resulting
- Decrease VDD
frequency response peaking and step response
overshoot. Modify the value of RISO until the response
is reasonable. Bench evaluation and simulations with
the MCP631/2/3/4/5/9 SPICE macro model are helpful.
4.3
Improving Stability
4.3.1
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the phase margin (stability) of
the feedback loop decreases and the closed-loop
bandwidth is reduced. This produces gain peaking in
the frequency response, with overshoot and ringing in
the step response. A unity-gain buffer (G = +1) is the
most sensitive to capacitive loads, though all gains
show the same general behavior.
4.3.2
GAIN PEAKING
Figure 4-8 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common-Mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
When driving large capacitive loads with these op
amps (e.g., > 20 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-6) improves the
phase margin of the feedback loop by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
CN
RN
MCP63X
+
VP
VOUT
-
VM
RG
RF
CG
RISO
CL
RG
RF
VOUT
-
FIGURE 4-8:
Amplifier with Parasitic
Capacitance.
+
MCP63X
Output Resistor, RISO
RN
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF.
FIGURE 4-6:
,
Stabilizes Large Capacitive Loads.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2RNCN).
DS20002197C-page 22
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
The largest value of RF that should be used depends
on the noise gain (see GN in Section 4.3.1
“Capacitive Loads”), CG and the open-loop gain’s
phase shift. Figure 4-9 shows the maximum
recommended RF for several CG values. Some
applications may modify these values to reduce either
output loading or gain peaking (step response
overshoot).
4.4
MCP633, MCP635 and MCP639
Chip Select
The MCP633 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to 1 µA (typical) and flows through the CS pin to VSS
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 M (typical)
pull-down resistor connected to VSS, so it will go low if
the CS pin is left floating. Figures 1-1, 2-42 and 2-43
show the output voltage and supply current response to
a CS pulse.
.
1.E+05
100k
CG = 10 pF
CG = 32 pF
CG = 100 pF
CG = 320 pF
CG = 1 nF
1.E+1004k
The MCP635 is a dual amplifier with two CS pins; CSA
controls op amp A and CSB controls op amp B. These
op amps are controlled independently, with an enabled
quiescent current (IQ) of 2.5 mA/amplifier (typical) and
a disabled IQ of 1 µA/amplifier (typical). The IQ seen at
the supply pins is the sum of the two op amps’ IQ; the
typical value for the IQ of the MCP635 will be 2 µA,
2.5 mA or 5 mA when there are 0, 1 or 2 amplifiers
enabled, respectively.
1k
1.E+03
GN > +1 V/V
100
1.E+02
1
10
100
Noise Gain; GN (V/V)
FIGURE 4-9:
RF vs. Gain.
Maximum Recommended
The MCP639 is a quad amplifier with two CS pins; CSB
controls op amp B and CSD controls op amp D.
Figures 2-34 and 2-35 show the small signal and large
signal step responses at G = +1 V/V. The unity-gain
buffer usually has RF = 0 and RG open.
4.5
Power Supply
With this family of operational amplifiers, the Power
Supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
Figures 2-36 and 2-37 show the small signal and large
signal step responses at G = -1 V/V. Since the noise
gain is 2 V/V and CG 10 pF, the resistors were
chosen to be RF = RG = 1 k and RN = 500.
It is also possible to add a capacitor (CF) in parallel with
RF to compensate for the destabilizing effect of CG.
This makes it possible to use larger values of RF. The
conditions for stability are summarized in Equation 4-6.
These op amps require a bulk capacitor (i.e., 2.2 µF or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
EQUATION 4-6:
Given:
RF
GN1 = 1 + ------
RG
CG
GN2 = 1 + ------
CF
1
fF = --------------------
2RFCF
GN1
fZ = fF ---------
GN2
We need:
fGBWP
fF --------------- , GN1 GN2
2GN2
fGBWP
G
N1 GN2
fF --------------- ,
4GN1
2009-2014 Microchip Technology Inc.
DS20002197C-page 23
MCP631/2/3/4/5/9
4.7.2
OPTICAL DETECTOR AMPLIFIER
4.6
High-Speed PCB Layout
Figure 4-11 shows a transimpedance amplifier, using
the MCP63X op amp, in a photo detector circuit. The
photo detector is a capacitive current source. RF
provides enough gain to produce 10 mV at VOUT. CF
stabilizes the gain and limits the transimpedance
bandwidth to about 1.1 MHz. The parasitic capacitance
of RF (e.g., 0.2 pF for a 0805 SMD) acts in parallel with
CF.
These op amps are fast enough that a little extra care
in the printed circuit board (PCB) layout can make a
significant difference in performance. Good PCB layout
techniques will help achieve the performance shown in
the specifications and typical performance curves; it
will also help minimize electromagnetic compatibility
(EMC) issues.
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
CF
1.5 pF
Separate digital from analog, low-speed from
high-speed, and low-power from high-power. This will
reduce interference.
Photo
Detector
RF
100 k
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high-frequency (low rise time)
signals.
VOUT
ID
100 nA
CD
30 pF
-
+
MCP632
Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim trace
and as close as possible. Connect guard traces to
ground plane at both ends and in the middle for long
traces.
VDD/2
FIGURE 4-11:
for an Optical Detector.
Transimpedance Amplifier
Use coax cables, or low-inductance wiring, to route
signal and power to and from the PCB. Mutual and
self-inductance of power wires is often a cause of
crosstalk and unusual behavior.
4.7.3
H-BRIDGE DRIVER
Figure 4-12 shows the MCP632 dual op amp used as
a H-bridge driver. The load could be a speaker or a DC
motor.
4.7
Typical Applications
½ MCP633
VIN
+
-
4.7.1
POWER DRIVER WITH HIGH GAIN
Figure 4-10 shows a power driver with high gain
(1 + R2/R1). The short-circuit current of the
MCP631/2/3/4/5/9 op amps makes it possible to drive
significant loads. The calibrated input offset voltage
supports accurate response at high gains. R3 should
be small and equal to R1||R2 in order to minimize the
bias current induced offset.
VOT
RF
RF
RF
RL
RGT
RGB
VOB
-
R1
R3
R2
+
VDD/2
VDD/2
VOUT
RL
½ MCP633
-
FIGURE 4-12:
H-Bridge Driver.
+
MCP63X
VIN
This circuit automatically makes the noise gains (GN)
equal when the gains are set properly, so that the
frequency responses match well (in magnitude and in
phase). Equation 4-7 shows how to calculate RGT and
RGB so that both op amps have the same DC gains;
FIGURE 4-10:
Power Driver.
GDM needs to be selected first.
DS20002197C-page 24
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
EQUATION 4-7:
VOT – VOB
GDM -------------------------- 1 V /V
VDD
V
IN – ----------
2
RF
RGT = --------------------
GDM
----------- – 1
2
RF
RGB = -----------
GDM
-----------
2
Equation 4-8 gives the resulting Common-Mode and
Differential mode output voltages.
EQUATION 4-8:
VOT + VOB
--------------------------- = ----------
VDD
2
2
VDD
VOT – VOB = GDM
V
IN – ----------
2
2009-2014 Microchip Technology Inc.
DS20002197C-page 25
MCP631/2/3/4/5/9
5.4
Analog Demonstration and
Evaluation Boards
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP631/2/3/4/5/9 family of op amps.
Microchip offers
a
broad spectrum of analog
demonstration and evaluation boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
5.1
SPICE Macro Model
The latest SPICE macro model for the
MCP631/2/3/4/5/9 op amps is available on the
Microchip web site at www.microchip.com. This model
is intended to be an initial design tool that works well in
the linear region of operation over the temperature
range of the op amp. See the model file for information
on its capabilities.
visit
the
Microchip
web
site
at
www.microchip.com/analog tools.
Some boards that are especially useful are:
• MCP6XXX Amplifier Evaluation Board 1,
part number: MCP6XXXEV-AMP1
• MCP6XXX Amplifier Evaluation Board 2,
part number: MCP6XXXEV-AMP2
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
• MCP6XXX Amplifier Evaluation Board 3,
part number: MCP6XXXEV-AMP3
• MCP6XXX Amplifier Evaluation Board 4,
part number: MCP6XXXEV-AMP4
®
5.2
FilterLab Software
• Active Filter Demo Board Kit,
part number: MCP6XXXDM-FLTR
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation
Board, part number: SOIC8EV
5.5
Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip.com/appnotes and are
recommended as supplemental reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
5.3
Microchip Advanced Part Selector
(MAPS)
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
MAPS is a software tool that helps efficiently identify
Microchip devices that fit particular design
a
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
requirement. Available at no cost from the Microchip
web site at www.microchip.com/maps, the MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a filter can be defined to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
Some of these application notes, and others, are listed
in the “Signal Chain Design Guide”, DS21825.
DS20002197C-page 26
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SOT-23 (MCP631)
Example
YV25
XXNN
6-Lead SOT-23 (MCP633)
Example
JC25
XXNN
8-Lead TDFN (2x3x0.75 mm) (MCP631)
Example
ABK
425
25
8-Lead DFN (3x3x0.9 mm) (MCP632)
Example
DABM
1425
256
Device
Code
DABM
Note 1: Applies to 8-lead 3x3 DFN
MCP632T-E/MF
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2014 Microchip Technology Inc.
DS20002197C-page 27
MCP631/2/3/4/5/9
8-Lead SOIC (3.90 mm) (MCP631, MCP632)
Example
MCP631E
e
3
SN^425
256
NNN
10-Lead DFN (3x3x0.9 mm) (MCP635)
Example
BAFB
1425
256
Device
MCP635T-E/MF
Code
BAFB
Note 1: Applies to 10-lead 3x3 DFN
10-Lead MSOP (3x3 mm) (MCP635)
Example
665EUN
425256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20002197C-page 28
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
14-Lead SOIC (3.90 mm) (MCP634)
Example
MCP634
e
3
E/SL
1425256
14-Lead TSSOP (4.4 mm) (MCP634)
Example
XXXXXXXX
YYWW
634E/ST
1425
256
NNN
16-Lead QFN (4x4x0.9 mm) (MCP639)
Example
PIN 1
PIN 1
639
e
3
E/ML^
1425256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2014 Microchip Technology Inc.
DS20002197C-page 29
MCP631/2/3/4/5/9
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ꢀꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀꢘꢙꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀꢞꢁꢟꢕꢁ
ꢠꢜꢡꢢ ꢠꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉꢣꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏꢤꢉꢅꢖꢊꢎꢍꢉꢥꢊꢏꢐꢅꢉꢇꢒꢈꢦꢆꢉꢦꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ ꢣꢅꢎꢒꢆꢈꢏꢈꢚꢤ ꢂꢓꢊꢦꢃꢆꢚ ꢡꢗꢞꢼꢗꢴꢀꢠ
DS20002197C-page 30
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 31
MCP631/2/3/4/5/9
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
c
A
φ
A2
L
A1
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
6
0.95 BSC
Outside Lead Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Foot Angle
Lead Thickness
Lead Width
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
0.00
2.20
1.30
2.70
0.10
0.35
0°
–
–
–
–
–
–
–
–
–
–
–
1.45
1.30
0.15
3.20
1.80
3.10
0.60
0.80
30°
L1
I
c
b
0.08
0.20
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-028B
DS20002197C-page 32
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 33
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 34
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 35
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 36
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 37
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 38
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢛꢖꢆMꢆꢛꢄꢓꢓꢔ"#ꢆꢙ$%&ꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗꢍꢏ+,ꢚ
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ
2009-2014 Microchip Technology Inc.
DS20002197C-page 39
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 40
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 41
MCP631/2/3/4/5/9
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ.ꢐꢄꢈꢆ/ꢈꢄꢊ#ꢆꢛꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ0ꢄ1ꢃꢆꢕ4ꢛꢖꢆMꢆꢘ5ꢙ5&$7ꢀꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗꢒ./ꢛꢚ
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ
DS20002197C-page 42
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 43
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 44
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 45
MCP631/2/3/4/5/9
UN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 46
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
UN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 47
MCP631/2/3/4/5/9
10-Lead Plastic Micro Small Outline Package (UN) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 48
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 49
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 50
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ
2009-2014 Microchip Technology Inc.
DS20002197C-page 51
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 52
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002197C-page 53
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 54
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
89ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ;ꢐꢄꢅꢆ/ꢈꢄꢊ#ꢆꢛꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ0ꢄ1ꢃꢆꢕ4ꢂꢖꢆMꢆ<5<5&$%ꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗ;/ꢛꢚ
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
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D
D2
EXPOSED
PAD
e
E
E2
2
1
2
b
1
K
N
N
NOTE 1
L
TOP VIEW
BOTTOM VIEW
A3
A
A1
ꢬꢆꢃꢍꢇꢕꢭꢮꢮꢭꢕꢌꢣꢌꢯꢜ
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉꢮꢃꢄꢃꢍꢇ
ꢕꢭꢰ
ꢰꢱꢕ
ꢕꢛꢲ
ꢰꢐꢄꢳꢅꢓꢉꢈꢑꢉꢪꢃꢆꢇꢰ
ꢪꢃꢍꢎꢒ
ꢱꢥꢅꢓꢊꢏꢏꢉꢵꢅꢃꢚꢒꢍ
ꢜꢍꢊꢆꢋꢈꢑꢑꢉ
ꢡꢈꢆꢍꢊꢎꢍꢉꢣꢒꢃꢎꢨꢆꢅꢇꢇ
ꢱꢥꢅꢓꢊꢏꢏꢉꢹꢃꢋꢍꢒ
ꢌꢖꢔꢈꢇꢅꢋꢉꢪꢊꢋꢉꢹꢃꢋꢍꢒ
ꢱꢥꢅꢓꢊꢏꢏꢉꢮꢅꢆꢚꢍꢒ
ꢌꢖꢔꢈꢇꢅꢋꢉꢪꢊꢋꢉꢮꢅꢆꢚꢍꢒ
ꢡꢈꢆꢍꢊꢎꢍꢉꢹꢃꢋꢍꢒ
ꢡꢈꢆꢍꢊꢎꢍꢉꢮꢅꢆꢚꢍꢒ
ꢀꢺ
ꢅ
ꢗꢁꢺꢟꢉꢠꢜꢡ
ꢗꢁꢴꢗ
ꢗꢁꢗꢘ
ꢗꢁꢘꢗꢉꢯꢌꢧ
ꢞꢁꢗꢗꢉꢠꢜꢡ
ꢘꢁꢺꢟ
ꢞꢁꢗꢗꢉꢠꢜꢡ
ꢘꢁꢺꢟ
ꢛ
ꢗꢁꢷꢗ
ꢗꢁꢗꢗ
ꢀꢁꢗꢗ
ꢗꢁꢗꢟ
ꢛꢀ
ꢛꢸ
ꢌ
ꢌꢘ
ꢂ
ꢂꢘ
ꢳ
ꢮ
ꢘꢁꢟꢗ
ꢘꢁꢷꢗ
ꢘꢁꢟꢗ
ꢗꢁꢘꢟ
ꢗꢁꢸꢗ
ꢗꢁꢘꢗ
ꢘꢁꢷꢗ
ꢗꢁꢸꢟ
ꢗꢁꢟꢗ
ꢶ
ꢗꢁꢸꢗ
ꢗꢁꢞꢗ
ꢶ
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{
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ ꢪꢃꢆꢉꢀꢉꢥꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊꢤꢉꢥꢊꢓꢤꢩꢉꢳꢐꢍꢉꢄꢐꢇꢍꢉꢳꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉꢦꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ
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ꢠꢜꢡꢢ ꢠꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉꢣꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏꢤꢉꢅꢖꢊꢎꢍꢉꢥꢊꢏꢐꢅꢉꢇꢒꢈꢦꢆꢉꢦꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢯꢌꢧꢢ ꢯꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢩꢉꢐꢇꢐꢊꢏꢏꢤꢉꢦꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢩꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏꢤꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ ꢣꢅꢎꢒꢆꢈꢏꢈꢚꢤ ꢂꢓꢊꢦꢃꢆꢚ ꢡꢗꢞꢼꢀꢘꢙꢠ
2009-2014 Microchip Technology Inc.
DS20002197C-page 55
MCP631/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 56
2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
APPENDIX A: REVISION HISTORY
Revision C (July 2014)
The following is the list of modifications:
1. Updated the Features: list.
2. Added the High Gain-Bandwidth Op Amp
Portfolio table in the Features: section.
3. Updated Figures 4-6 and 4-11.
4. Updated
Section 6.0
“Packaging
Information” and Section 6.1 “Package
Marking Information”.
5. Minor typographical changes.
Revision B (November 2011)
The following is the list of modifications:
1. Added the MCP634 and MCP639 amplifiers to
the product family and the related information
throughout the document.
2. Added the 2x3 TDFN (8L), SOT23 (5L) package
option for MCP631, SOT23 (6L) package option
for MCP633, 4x4 QFN (16L) package option for
MCP639, SOIC and TSSOP (14L) package
options for MCP634 and the related information
throughout the document. Updated package
types drawing with pin designation for each new
package.
3. Updated the Temperature Specifications table to
show the temperature specifications for new
packages.
4. Updated Table 3-1 to show all the pin functions.
5. Updated Section 6.0 “Packaging Informa-
tion” with markings for the new additions.
Added the corresponding SOT23 (5L), SOT23
(6L), TDFN (8L), SOIC, TSSOP (14L), and 4x4
QFN (16L) package options and related infor-
mation.
6. Updated table description and examples in the
Product Identification System section.
Revision A (August 2009)
• Original Release of this Document.
2009-2014 Microchip Technology Inc.
DS20002197C-page 57
MCP631/2/3/4/5/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
-X
/XX
a)
MCP631T-E/OT: Tape and Reel
Extended temperature,
5LD SOT-23 package
MCP631T-E/MNY:Tape and Reel
Temperature
Range
Package
b)
Extended temperature,
8LD TDFN package
Device:
MCP631
Single Op Amp
MCP631T
Single Op Amp (Tape and Reel)
(SOIC, SOT-23, TDFN)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(DFN and SOIC)
Single Op Amp with CS
Single Op Amp with CS (Tape and Reel)
(SOIC, SOT-23)
Quad Op Amp
Quad Op Amp (Tape and Reel)
(TSSOP and SOIC)
Dual Op Amp with CS
Dual Op Amp with CS (Tape and Reel)
(DFN and MSOP)
c)
d)
e)
f)
MCP631T-E/SN: Tape and Reel
Extended temperature,
8LD SOIC package
MCP632
MCP632T
MCP632T-E/MF: Tape and Reel
Extended temperature,
8LD DFN package
MCP633
MCP633T
MCP632T-E/SN: Tape and Reel
MCP634
MCP634T
Extended temperature,
8LD SOIC package
MCP633T-E/SN: Tape and Reel
MCP635
MCP635T
Extended temperature,
8LD SOIC package
g)
h)
i)
MCP633T-E/CHY: Tape and Reel
MCP639
MCP639T
Quad Op Amp
Quad Op Amp (Tape and Reel)
(QFN)
Extended temperature,
6LD SOT package
MCP634T-E/SL: Tape and Reel
Extended temperature,
14LD SOIC package
Temperature
Range:
E
=
=
-40°C to +125°C
MCP634T-E/ST: Tape and Reel
Extended temperature,
14LD TSSOP package
Package:
OT
Plastic Small Outline (SOT-23), 5-lead
j)
MCP635T-E/MF: Tape and Reel
CHY = Plastic Small Outline (SOT-23), 6-lead
Extended temperature,
10LD DFN package
MNY= Plastic Dual Flat, No Lead (2x3 TDFN), 8-lead
MF
=
Plastic Dual Flat, No Lead (3×3 DFN),
8-lead, 10-lead
k)
l)
MCP635T-E/UN: Tape and Reel
SN
UN
SL
=
=
=
Plastic Small Outline (3.90 mm), 8-lead
Plastic Micro Small Outline (MSOP), 10-lead
Plastic Small Outline, Narrow, (3.90 mm SOIC),
14-lead
Extended temperature,
10LD MSOP package
MCP639T-E/ML: Tape and Reel
Extended temperature,
16LD QFN package.
ST
ML
=
=
Plastic Thin Shrink Small Outline, (4.4 mm TSSOP),
14-lead
Plastic Quad Flat, No Lead Package (4x4 QFN),
(4x4x0.9 mm), 16-lead
DS20002197C-page 58
2009-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-382-2
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2009-2014 Microchip Technology Inc.
DS20002197C-page 59
Worldwide Sales and Service
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ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
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Tel: 852-2943-5100
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Tel: 91-80-3090-4444
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Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
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Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
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Tel: 33-1-69-53-63-20
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Tel: 91-20-3019-1500
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Tel: 678-957-9614
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Tel: 86-10-8569-7000
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Tel: 49-89-627-144-0
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Tel: 81-3-6880- 3770
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
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Tel: 86-571-8792-8115
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Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Shenzhen
Tel: 86-755-8864-2200
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Taiwan - Taipei
Tel: 886-2-2508-8600
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Los Angeles
China - Wuhan
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Fax: 86-27-5980-5118
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Thailand - Bangkok
Tel: 66-2-694-1351
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Fax: 86-756-3210049
03/25/14
DS20002197C-page 60
2009-2014 Microchip Technology Inc.
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