MCP651T-E/UN [MICROCHIP]
50 MHz, 6 mA Op Amps with mCal; 50兆赫, 6毫安运算放大器, MCAL型号: | MCP651T-E/UN |
厂家: | MICROCHIP |
描述: | 50 MHz, 6 mA Op Amps with mCal |
文件: | 总44页 (文件大小:1232K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MCP651/2/5
50 MHz, 6 mA Op Amps with mCal
Features
Description
• Gain Bandwidth Product: 50 MHz (typical)
• Short Circuit Current: 100 mA (typical)
• Noise: 7.5 nV/√Hz (typical, at 1 MHz)
• Calibrated Input Offset: ±200 µV (maximum)
• Rail-to-Rail Output
The Microchip Technology, Inc. MCP651/2/5 family of
operational amplifiers features low offset. At power up,
these op amps are self-calibrated using mCal. Some
package options also provide a calibration/chip select
pin (CAL/CS) that supports a low power mode of oper-
ation, with offset calibration at the time normal opera-
tion is re-started. These amplifiers are optimized for
high speed, low noise and distortion, single-supply
operation with rail-to-rail output and an input that
includes the negative rail.
• Slew Rate: 30 V/µs (typical)
• Supply Current: 6.0 mA (typical)
• Power Supply: 2.5V to 5.5V
• Extended Temperature Range: -40°C to +125°C
This family is offered in single with CAL/CS pin
(MCP651), dual (MCP652) and dual with CAL/CS pins
(MCP655). All devices are fully specified from -40°C to
+125°C.
Typical Applications
• Driving A/D Converters
• Power Amplifier Control Loops
• Barcode Scanners
Typical Application Circuit
• Optical Detector Amplifier
R1
R2
VDD/2
VOUT
RL
Design Aids
R3
• SPICE Macro Models
• FilterLab® Software
MCP65X
VIN
• Mindi™ Circuit Designer & Simulator
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Power Driver with High Gain
Package Types
MCP651
MCP652
MCP655
SOIC
3×3 DFN *
3×3 DFN *
1
2
3
4
8
7
6
5
NC
CAL/CS
VDD
VOUTA
V
DD
VOUTA
VDD
1
2
3
10
9
1
8
7
VIN
–
+
VINA
–
+
VOUTB
VINA
–
+
VOUTB
2
EP
9
EP
11
VIN
VOUT
VCAL
VINA
VINB
VINB
–
+
VINA
VINB
VINB
–
+
8
3
4
6
5
VSS
VSS
VSS
4
5
7
6
CALA/CSA
CALB/CSB
MCP652
MCP655
SOIC
MSOP
VDD
8
V
DD
VOUTA
1
VOUTA
1
10
VOUTB
VINA
–
VOUTB
2
3
4
7
6
5
2
3
9
8
7
6
VINA
–
+
VINA
+
VINB
VINB
–
+
VINA
VINB
VINB
–
+
VSS 4
CALA/CSA
VSS
CALB/CSB
5
* Includes Exposed Thermal Pad (EP); see Table 3-1.
© 2009 Microchip Technology Inc.
DS22146A-page 1
MCP651/2/5
NOTES:
DS22146A-page 2
© 2009 Microchip Technology Inc.
MCP651/2/5
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
VDD – VSS .......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V
Difference Input voltage ...................................... |VDD – VSS
|
†† See Section 4.2.2 “Input Voltage and Current Limits”.
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................+150°C
ESD protection on all pins (HBM, MM) ................≥ 1 kV, 200V
1.2
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
Input Offset Voltage
VOS
-200
—
—
37
+200
200
—
µV
µV
After calibration (Note 1)
Input Offset Voltage Trim Step
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Current and Impedance
Input Bias Current
VOSTRM
ΔVOS/ΔTA
PSRR
—
±2.5
76
µV/°C TA= -40°C to +125°C
dB
61
—
IB
IB
—
—
—
—
—
—
6
—
—
pA
Across Temperature
130
pA
pA
TA= +85°C
Across Temperature
IB
1700
±1
1013||9
1013||2
5,000
—
TA= +125°C
Input Offset Current
IOS
ZCM
ZDIFF
pA
Common Mode Input Impedance
Differential Input Impedance
Common Mode
—
Ω||pF
Ω||pF
—
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
VCMR
CMRR
CMRR
VSS − 0.3
—
81
84
VDD − 1.3
V
(Note 2)
65
68
—
—
dB
dB
VDD = 2.5V, VCM = -0.3 to 1.2V
VDD = 5.5V, VCM = -0.3 to 4.2V
Open-Loop Gain
DC Open-Loop Gain (large signal)
AOL
AOL
88
94
114
123
—
—
dB
dB
VDD = 2.5V, VOUT = 0.3V to 2.2V
VDD = 5.5V, VOUT = 0.3V to 5.2V
Output
Maximum Output Voltage Swing
VOL, VOH VSS + 25
VOL, VOH VSS + 50
—
—
VDD − 25
VDD − 50
mV
mV
VDD = 2.5V, G = +2,
0.5V Input Overdrive
VDD = 5.5V, G = +2,
0.5V Input Overdrive
Output Short Circuit Current
ISC
ISC
±50
±50
±95
±145
±150
mA
mA
VDD = 2.5V (Note 3)
VDD = 5.5V (Note 3)
±100
Note 1: Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus,
1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.
2: See Figure 2-6 and Figure 2-7 for temperature effects.
3: The ISC specifications are for design guidance only; they are not tested.
© 2009 Microchip Technology Inc.
DS22146A-page 3
MCP651/2/5
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Calibration Input
Calibration Input Voltage Range
Internal Calibration Voltage
Input Impedance
VCALRNG VSS + 0.1
—
VDD – 1.4
mV
VCAL pin externally driven
VCAL pin open
VCAL
ZCAL
0.31VDD 0.33VDD 0.35VDD
—
100 || 5
—
kΩ||pF
Power Supply
Supply Voltage
VDD
IQ
2.5
3
—
6
5.5
9
V
Quiescent Current per Amplifier
POR Input Threshold, Low
mA
IO = 0
VPRL
1.15
1.40
—
V
V
POR Input Threshold, High
VPRH
—
1.40
1.65
Note 1: Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus,
1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.
2: See Figure 2-6 and Figure 2-7 for temperature effects.
3: The ISC specifications are for design guidance only; they are not tested.
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
50
65
20
—
—
—
MHz
°
G = +1
Open-Loop Output Impedance
AC Distortion
ROUT
Ω
Total Harmonic Distortion plus Noise
THD+N
—
0.0012
—
%
G = +1, VOUT = 4VP-P, f = 1 kHz,
DD = 5.5V, BW = 80 kHz
V
Step Response
Rise Time, 10% to 90%
Slew Rate
tr
—
—
6
—
—
ns
G = +1, VOUT = 100 mVP-P
G = +1
SR
30
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Eni
eni
ini
—
—
17
7.5
4
—
—
—
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 MHz
fA/√Hz f = 1 kHz
DS22146A-page 4
© 2009 Microchip Technology Inc.
MCP651/2/5
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2).
Parameters
Sym
Min
Typ
Max Units
Conditions
CAL/CS Low Specifications
CAL/CS Logic Threshold, Low
CAL/CS Input Current, Low
CAL/CS High Specifications
CAL/CS Logic Threshold, High
CAL/CS Input Current, High
GND Current
VIL
VSS
—
—
0
0.2VDD
—
V
ICSL
nA
CAL/CS = 0V
VIH
ICSH
ISS
0.8VDD
—
VDD
—
V
0.7
-1.8
-4
µA
µA
µA
µA
µA
MΩ
nA
CAL/CS = VDD
-3.5
-8
—
Single, CAL/CS = VDD = 2.5V
Single, CAL/CS = VDD = 5.5V
Dual, CAL/CS = VDD = 2.5V
Dual, CAL/CS = VDD = 5.5V
ISS
—
ISS
-5
-2.5
-5
—
ISS
-10
—
—
CAL/CS Internal Pull Down Resistor
RPD
IO(LEAK)
5
—
Amplifier Output Leakage
—
50
—
CAL/CS = VDD
POR Dynamic Specifications
VDD Low to Amplifier Off Time
(output goes High-Z)
tPOFF
tPON
—
200
200
—
ns
G = +1 V/V, VL = VSS,
V
DD = 2.5V to 0V step to VOUT = 0.1 (2.5V)
VDD High to Amplifier On Time
(including calibration)
100
300
ms
G = +1 V/V, VL = VSS,
V
DD = 0V to 2.5V step to VOUT = 0.9 (2.5V)
CAL/CS Dynamic Specifications
—
1
—
—
CAL/CS Input Hysteresis
VHYST
tCSU
0.25
—
V
CAL/CS Setup Time
µs
G = +1 V/V, VL = VSS (Notes 2, 3)
(between CAL/CS edges)
CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2)
CAL/CS High to Amplifier Off Time
(output goes High-Z)
tCOFF
tCON
—
—
200
3
—
4
ns
G = +1 V/V, VL = VSS
CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2)
G = +1 V/V, VL = VSS
CAL/CS = 0.2VDD to VOUT = 0.9 (VDD/2)
,
CAL/CS Low to Amplifier On Time
(including calibration)
,
ms
Note 1: The MCP652 has its CAL/CS input internally pulled down to VSS (0V).
2: This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised
before the calibration is complete, the calibration will be aborted and the part will return to low power mode.
3: For the MCP655 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously
(within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are tog-
gled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in
calibration mode; allow more than the maximum tCON time (4 ms) before the other side is toggled.
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
(Note 1)
Thermal Package Resistances
Thermal Resistance, 8L-3×3 DFN
Thermal Resistance, 8L-SOIC
θJA
θJA
—
—
63
—
—
°C/W (Note 2)
163
°C/W
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (150°C).
2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
© 2009 Microchip Technology Inc.
DS22146A-page 5
MCP651/2/5
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.
Parameters
Sym
θJA
Min
—
Typ
71
Max Units
Conditions
Thermal Resistance, 10L-3×3 DFN
Thermal Resistance, 10L-MSOP
—
—
°C/W (Note 2)
°C/W
θJA
—
202
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (150°C).
2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
1.3
Timing Diagram
CAL/CS
VIL
VIH
VDD
VPRH
VPRL
tPOFF
tCSU
tPON
High-Z
tCOFF
tCON
High-Z
VOUT
High-Z
On
-6 mA (typical)
On
-6 mA (typical)
ISS -3 µA (typical)
-3 µA (typical)
-3 µA (typical)
0 nA (typical)
ICS
0 nA (typical)
0.7 µA (typical)
FIGURE 1-1:
Timing Diagram.
1.4
Test Circuits
CF
6.8 pF
The circuit used for most DC and AC tests is shown in
Figure 1-2. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s common mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
RG
10 kΩ
RF
10 kΩ
VDD/2
VP
error, VOST) of temperature, CMRR, PSRR and AOL
.
VDD
VIN+
EQUATION 1-1:
CB1
100 nF
CB2
2.2 µF
GDM = RF ⁄ RG
MCP65X
VCM = (VP + VDD ⁄ 2) ⁄ 2
VOST = VIN– – VIN+
VIN–
VOUT = (VDD ⁄ 2) + (VP – VM) + VOST(1 + GDM
Where:
)
VOUT
VM
RL
CL
RG
RF
GDM = Differential Mode Gain
(V/V)
(V)
1 kΩ
20 pF
10 kΩ
10 kΩ
VCM = Op Amp’s Common Mode
Input Voltage
CF
VL
VOST = Op Amp’s Total Input Offset (mV)
6.8 pF
Voltage
FIGURE 1-2:
AC and DC Test Circuit for
Most Specifications.
DS22146A-page 6
© 2009 Microchip Technology Inc.
MCP651/2/5
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
2.1
DC Signal Inputs
35%
30%
25%
20%
15%
10%
5%
700
600
500
400
300
200
100
0
80 Samples
TA = +25°C
Representative Part
Calibrated at VDD = 6.5V
VDD = 2.5V and 5.5V
Calibrated at +25°C
+125°C
+85°C
+25°C
-40°C
0%
-100
-100 -80 -60 -40 -20
0
20 40 60 80 100
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
Input Offset Voltage (µV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Power Supply Voltage.
20%
50
80 Samples
VDD = 2.5V and 5.5V
A = -40°C to +125°C
Representative Part
VDD = 2.5V
18%
16%
14%
12%
10%
8%
40
30
T
Calibrated at +25°C
20
10
0
-10
-20
-30
-40
-50
VDD = 5.5V
6%
4%
2%
0%
-10 -8 -6 -4 -2
0
2
4
6
8
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5:
Input Offset Voltage vs.
Output Voltage.
55%
0.0
1 Lot
Low (VCMR_L – VSS
80 Samples
TA = +25°C
VDD = 2.5V and 5.5V
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
)
-0.1
-0.2
-0.3
-0.4
-0.5
No Change
(includes noise)
VDD = 2.5V
Calibration
Changed
Calibration
Changed
VDD = 5.5V
0%
-100 -80 -60 -40 -20
0
20 40 60 80 100
-50
-25
0
25
50
75
100 125
Input Offset Voltage Repeatability (µV)
Ambient Temperature (°C)
FIGURE 2-3:
Input Offset Voltage
FIGURE 2-6:
Low Input Common Mode
Repeatability (repeated calibration).
Voltage Headroom vs. Ambient Temperature.
© 2009 Microchip Technology Inc.
DS22146A-page 7
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
1.4
110
105
100
95
1 Lot
High (VDD – VCMR_H
)
PSRR
1.3
1.2
1.1
1.0
VDD = 2.5V
90
85
CMRR, VDD = 5.5V
CMRR, VDD = 2.5V
80
75
VDD = 5.5V
70
65
60
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-7:
High Input Common Mode
FIGURE 2-10:
CMRR and PSRR vs.
Voltage Headroom vs. Ambient Temperature.
Ambient Temperature.
1000
130
VDD = 2.5V
Representative Part
800
VDD = 5.5V
125
120
115
110
105
100
95
600
400
200
0
VDD = 2.5V
-200
-40°C
+25°C
+85°C
+125°C
-400
-600
-800
-1000
-50
-25
0
25
50
75
100
125
Input Common Mode Voltage (V)
Ambient Temperature (°C)
FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
DC Open-Loop Gain vs.
Common Mode Voltage with V = 2.5V.
Ambient Temperature.
DD
1000
10,000
VDD = 5.5V
VDD = 5.5V
Representative Part
800
VCM = VCMR_H
600
400
200
0
1,000
100
10
IB
-200
-400
-600
-40°C
+25°C
+85°C
+125°C
-IOS
-800
-1000
1
25
45
65
85
105
125
Input Common Mode Voltage (V)
Ambient Temperature (°C)
FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Input Bias and Offset
Common Mode Voltage with V = 5.5V.
Currents vs. Ambient Temperature with
= +5.5V.
DD
V
DD
DS22146A-page 8
© 2009 Microchip Technology Inc.
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
160
1.E-10m3
1.E10-004µ
TA = +85°C
140
V
DD = 5.5V
120
100
80
10µ
1.E-05
IB
1µ
1.E-06
100n
1.E- 7
60
40
10n
1.E- 8
20
0
-20
-40
-60
1n
1.E-09
+125°C
+85°C
+25°C
-40°C
IOS
100p
1.E-10
10p
1.E-11
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias and Offset
FIGURE 2-15:
Input Bias Current vs. Input
Currents vs. Common Mode Input Voltage with
Voltage (below V ).
SS
T = +85°C.
A
2000
1500
1000
500
TA = +125°C
VDD = 5.5V
IB
0
IOS
-500
-1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
T = +125°C.
A
© 2009 Microchip Technology Inc.
DS22146A-page 9
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
2.2
Other DC Voltages and Currents
14
8
7
6
5
4
3
2
1
0
VDD = 5.5V
VOL – VSS
-IOUT
12
10
8
+125°C
+85°C
+25°C
-40°C
6
VDD – VOH
IOUT
4
VDD = 2.5V
2
0
1
10
100
Output Current Magnitude (mA)
Power Supply Voltage (V)
FIGURE 2-16:
Ratio of Output Voltage
FIGURE 2-19:
Supply Current vs. Power
Headroom to Output Current.
Supply Voltage.
14
9
8
7
6
5
RL = 1 kΩ
VDD = 5.5V
VOL – VSS
12
10
8
VDD = 5.5V
VDD = 2.5V
4
3
2
1
0
6
VDD – VOH
4
VDD = 2.5V
2
0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Common Mode Input Voltage (V)
FIGURE 2-17:
Output Voltage Headroom
FIGURE 2-20:
Supply Current vs. Common
vs. Ambient Temperature.
Mode Input Voltage.
100
80
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
+125°C
+85°C
+25°C
-40°C
60
VPRH
40
20
VPRL
0
-20
-40
-60
-80
-100
-50
-25
0
25
50
75
100
125
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-18:
Output Short Circuit Current
FIGURE 2-21:
Power On Reset Voltages
vs. Power Supply Voltage.
vs. Ambient Temperature.
DS22146A-page 10
© 2009 Microchip Technology Inc.
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
30%
140
120
100
80
144 Samples
VDD = 2.5V and 5.5V
25%
20%
15%
10%
5%
60
40
0%
20
0
Normalized Internal Calibration Voltage;
-50
-25
0
25
50
75
100
125
VCAL/VDD
Ambient Temperature (°C)
FIGURE 2-22:
Normalized Internal
FIGURE 2-23:
V
Input Resistance vs.
CAL
Calibration Voltage.
Temperature.
© 2009 Microchip Technology Inc.
DS22146A-page 11
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
2.3
Frequency Response
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
70
60
50
40
30
20
10
PM
PSRR+
PSRR-
CMRR
VDD = 5.5V
VDD = 2.5V
GBWP
11.E0+02
1.1Ek+3
11.E0+k4
110.E0+k5
11.EM+6
11.0EM+7
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-24:
CMRR and PSRR vs.
FIGURE 2-27:
Gain Bandwidth Product
Frequency.
and Phase Margin vs. Common Mode Input
Voltage.
120
100
80
0
60
50
40
30
20
10
0
90
80
70
60
50
40
30
-30
VDD = 5.5V
-60
-90
GBWP
∠AOL
60
VDD = 2.5V
40
-120
-150
-180
-210
| AOL
|
20
PM
0
-20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8 1.E+9
10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz)
FIGURE 2-25:
Open-Loop Gain vs.
FIGURE 2-28:
Gain Bandwidth Product
Frequency.
and Phase Margin vs. Output Voltage.
1000
100
90
80
70
60
50
40
30
70
60
50
40
30
20
10
PM
G = 101 V/V
G = 11 V/V
G = 1 V/V
VDD = 5.5V
VDD = 2.5V
10
1
GBWP
0.1
-50 -25
0
25
50
75 100 125
1k
10k
100k
Frequency (Hz)
1M
10M
100M
1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08
Ambient Temperature (°C)
FIGURE 2-26:
Gain Bandwidth Product
FIGURE 2-29:
Closed-Loop Output
and Phase Margin vs. Ambient Temperature.
Impedance vs. Frequency.
DS22146A-page 12
© 2009 Microchip Technology Inc.
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
10
9
8
7
6
150
140
130
120
110
100
90
RS = 0Ω
RS = 1 kΩ
RTI
VCM = VDD/2
G = +1 V/V
G = 1 V/V
5
G = 2 V/V
4
3
2
1
0
G ꢀ 4 V/V
80
70
RS = 10 kΩ
RS = 100 kΩ
60
50
10p
100p
1n
10n
1.0E-09
1k
10k
1.E+04
100k
1.E+05
Frequency (Hz)
1M
1.E+06
10M
1.0E-11
1.0E-10
1.E+03
1.E+07
Normalized Capacitive Load; CL/G (F)
FIGURE 2-30:
Gain Peaking vs.
FIGURE 2-31:
Channel-to-Channel
Normalized Capacitive Load.
Separation vs. Frequency.
© 2009 Microchip Technology Inc.
DS22146A-page 13
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
2.4
Input Noise and Distortion
1.E+4
10μ
20
15
10
5
Representative Part
NPBW = 0.1 Hz
1.E+3
1μ
0
1.E+2
100n
-5
-10
-15
-20
1.E+1
10n
1n
1.E+00.1
1
10
100 1k 10k 100k 1M 10M
0
5
10 15 20 25 30 35 40 45 50
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7
Time (min)
Frequency (Hz)
FIGURE 2-32:
Input Noise Voltage Density
FIGURE 2-35:
Input Noise plus Offset vs.
vs. Frequency.
Time with 0.1 Hz Filter.
160
1
VDD = 5.0V
VDD = 2.5V
140
120
100
80
0.1
VDD = 5.5V
BW = 22 Hz to > 500 kHz
G = 1 V/V
G = 11 V/V
0.01
60
40
0.001
BW = 22 Hz to 80 kHz
20
f = 100 Hz
0
0.0001
1.E+2
100
1.E+3
1k
1.E+4
10k
1.E+5
100k
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-33:
Input Noise Voltage Density
FIGURE 2-36:
THD+N vs. Frequency.
vs. Input Common Mode Voltage with f = 100 Hz.
12
11
10
9
VDD = 2.5V
8
7
VDD = 5.5V
6
5
4
3
2
1
f = 1 MHz
0
Common Mode Input Voltage (V)
FIGURE 2-34:
Input Noise Voltage Density
vs. Input Common Mode Voltage with f = 1 MHz.
DS22146A-page 14
© 2009 Microchip Technology Inc.
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
2.5
Time Response
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.5V
G = 1
VDD = 5.5V
G = -1
RF = 499Ω
VIN
VIN
VOUT
VOUT
0
20 40 60 80 100 120 140 160 180 200
Time (ns)
0
100 200 300 400 500 600 700 800
Time (ns)
FIGURE 2-37:
Non-inverting Small Signal
FIGURE 2-40:
Inverting Large Signal Step
Step Response.
Response.
5.5
5.0
4.5
4.0
3.5
3.0
7
6
VDD = 5.5V
G = 1
VDD = 5.5V
G = 2
VIN
5
VOUT
4
3
2.5
VIN
VOUT
2
2.0
1.5
1.0
0.5
0.0
1
0
-1
0
1
2
3
4
5
6
7
8
9
10
0
100 200 300 400 500 600 700 800
Time (ns)
Time (ms)
FIGURE 2-38:
Non-inverting Large Signal
FIGURE 2-41:
The MCP651/2/5 family
Step Response.
shows no input phase reversal with overdrive.
60
Falling Edge
VDD = 5.5V
55
50
45
40
35
30
25
20
15
10
5
VIN
VDD = 5.5V
G = -1
RF = 499Ω
VDD = 2.5V
Rising Edge
VOUT
0
-50
-25
0
25
50
75
100
125
0
50
100 150 200 250 300 350 400
Time (ns)
Ambient Temperature (°C)
FIGURE 2-39:
Inverting Small Signal Step
FIGURE 2-42:
Slew Rate vs. Ambient
Response.
Temperature.
© 2009 Microchip Technology Inc.
DS22146A-page 15
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
10
VDD = 5.5V
VDD = 2.5V
1
0.1
100k
1M
1.E+06
10M
1.E+07
100M
1.E+08
1.E+05
Frequency (Hz)
FIGURE 2-43:
Maximum Output Voltage
Swing vs. Frequency.
DS22146A-page 16
© 2009 Microchip Technology Inc.
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
2.6
Calibration and Chip Select Response
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
CAL/CS = VDD
VDD = 5.5V
VDD = 2.5V
-50
-25
0
25
50
75
100
125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-44:
CAL/CS Current vs. Power
FIGURE 2-47:
CAL/CS Hysteresis vs.
Supply Voltage.
Ambient Temperature.
8
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 2.5V
G = 1
VL = 0V
6
4
IDD
2
0
-2
Op Amp
turns off
Op Amp
turns on
Calibration
starts
CAL/CS
3
2
1
VOUT
0
-1
-50
-25
0
25
50
75
100
125
0
1
2
3
4
5
6
7
8
9
10
Time (ms)
Ambient Temperature (°C)
FIGURE 2-45:
CAL/CS Voltage, Output
FIGURE 2-48:
CAL/CS Turn On Time vs.
Voltage and Supply Current (for Side A) vs. Time
Ambient Temperature.
with V = 2.5V.
DD
8
10
8
6
4
2
Representative Part
VDD = 5.5V
7
6
5
4
3
2
1
0
G = 1
6
5
4
3
2
1
VL = 0V
IDD
0
Op Amp
turns on
Calibration
starts
-2
Op Amp
turns off
CAL/CS
VOUT
0
-1
0
1
2
3
4
5
6
7
8
9
10
-50
-25
0
25
50
75
100
125
Time (ms)
Ambient Temperature (°C)
FIGURE 2-46:
CAL/CS Voltage, Output
FIGURE 2-49:
CAL/CS’s Pull-down
Voltage and Supply Current (for Side A) vs. Time
Resistor (R ) vs. Ambient Temperature.
PD
with V = 5.5V.
DD
© 2009 Microchip Technology Inc.
DS22146A-page 17
MCP651/2/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF, and CAL/CS = VSS
.
0
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
CAL/CS = VDD = 5.5V
CAL/CS = VDD
-1
-2
-3
+125°C
+85°C
-4
+125°C
+85°C
+25°C
-40°C
-5
-6
+25°C
-7
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
Power Supply Voltage (V)
FIGURE 2-50:
Quiescent Current in
FIGURE 2-51:
Output Leakage Current vs.
Shutdown vs. Power Supply Voltage.
Output Voltage.
DS22146A-page 18
© 2009 Microchip Technology Inc.
MCP651/2/5
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP652 MCP655
SOIC DFN MSOP DFN
MCP651
Symbol
VOUT, VOUTA
Description
SOIC
6
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
Output (op amp A)
VIN–, VINA
VIN+, VINA
VSS
–
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Negative Power Supply
+
8
—
—
5
5
CAL/CS, CALA/CSA
CALB/CSB
Calibrate/Chip Select Digital Input (op amp A)
—
—
—
—
7
—
5
—
5
6
7
6
7
8
9
Calibrate/Chip Select Digital Input (op amp B)
Non-inverting Input (op amp B)
Inverting Input (op amp B)
VINB
VINB
+
–
6
6
8
7
7
9
VOUTB
Output (op amp B)
8
8
10
—
—
—
10 VDD
Positive Power Supply
5
—
—
—
—
—
9
—
—
VCAL
NC
Calibration Common Mode Voltage Input
No Internal Connection
1
—
11 EP
Exposed Thermal Pad (EP);
must be connected to VSS
3.1
Analog Outputs
3.5
Calibrate/Chip Select Digital Input
The analog output pins (VOUT) are low-impedance
voltage sources.
This input (CAL/CS, …) is a CMOS, Schmitt-triggered
input that affects the calibration and low power modes
of operation. When this pin goes high, the part is placed
into a low power mode and the output is high-Z. When
this pin goes low, a calibration sequence is started
(which corrects VOS). At the end of the calibration
sequence, the output becomes low impedance and the
part resumes normal operation.
3.2
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
An internal POR triggers a calibration event when the
part is powered on, or when the supply voltage drops
too low. Thus, the MCP652 parts are calibrated, even
though they do not have a CAL/CS pin.
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
3.6
Exposed Thermal Pad (EP)
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be con-
nected to the same potential on the Printed Circuit
Board (PCB).
3.4
Calibration Common Mode
Voltage Input
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).
A low impedance voltage placed at this input (VCAL
)
analog input will set the op amps’ common mode input
voltage during calibration. If this pin is left open, the
common mode input voltage during calibration is
approximately VDD/3. The internal resistor divider is
disconnected from the supplies whenever the part is
not in calibration.
© 2009 Microchip Technology Inc.
DS22146A-page 19
MCP651/2/5
NOTES:
DS22146A-page 20
© 2009 Microchip Technology Inc.
MCP651/2/5
4.1.3
INTERNAL POR
4.0
APPLICATIONS
This part includes an internal Power On Reset (POR)
to protect the internal calibration memory cells. The
POR monitors the power supply voltage (VDD). When
the POR detects a low VDD event, it places the part into
the low power mode of operation. When the POR
detects a normal VDD event, it starts a delay counter,
then triggers an calibration event. The additional delay
gives a total POR turn on time of 200 ms (typical); this
is also the power up time (since the POR is triggered at
power up).
The MCP651/2/5 family of self-zeroed op amps is man-
ufactured using Microchip’s state of the art CMOS
process. It is designed for low cost, low power and high
precision applications. Its low supply voltage, low
quiescent current and wide bandwidth makes the
MCP651/2/5 ideal for battery-powered applications.
4.1
Calibration and Chip Select
These op amps include circuitry for dynamic calibration
of the offset voltage (VOS).
4.1.4
PARITY DETECTOR
4.1.1
mCal CALIBRATION CIRCUITRY
A parity error detector monitors the memory contents
for any corruption. In the rare event that a parity error is
detected (e.g., corruption from an alpha particle), a
POR event is automatically triggered. This will cause
the input offset voltage to be re-corrected, and the op
amp will not return to normal operation for a period of
time (the POR turn on time, tPON).
The internal mCal circuitry, when activated, starts a
delay timer (to wait for the op amp to settle to its new
bias point), then calibrates the input offset voltage
(VOS). The mCal circuitry is triggered at power-up (and
after some power brown out events) by the internal
POR, and by the memory’s Parity Detector. The power
up time, when the mCal circuitry triggers the calibration
sequence, is 200 ms (typical).
4.1.5
CALIBRATION INPUT PIN
A VCAL pin is available in some options (e.g., the single
MCP651) for those applications that need the calibra-
tion to occur at an internally driven common mode
voltage other than VDD/3.
4.1.2
CAL/CS PIN
The CAL/CS pin gives the user a means to externally
demand a low power mode of operation, then to
calibrate VOS. Using the CAL/CS pin makes it possible
to correct VOS as it drifts over time (1/f noise and aging;
see Figure 2-35) and across temperature.
Figure 4-1 shows the reference circuit that internally
sets the op amp’s common mode reference voltage
(VCM_INT) during calibration (the resistors are discon-
nected from the supplies at other times). The 5 kΩ
resistor provides over-current protection for the buffer.
The CAL/CS pin performs two functions: it places the
op amp(s) in a low power mode when it is held high,
and starts a calibration event (correction of VOS) after a
rising edge.
To op amp during
VDD
calibration
While in the low power mode, the quiescent current is
quite small (ISS = -3 µA, typical). The output is also is in
a High-Z state.
VCM_INT
300 kΩ
5 kΩ
During the calibration event, the quiescent current is
near, but smaller than, the specified quiescent current
(6 mA, typical). The output continues in the High-Z
state, and the inputs are disconnected from the
external circuit, to prevent internal signals from
affecting circuit operation. The op amp inputs are inter-
nally connected to a common mode voltage buffer and
feedback resistors. The offset is corrected (using a
digital state machine, logic and memory), and the
calibration constants are stored in memory.
VCAL
BUFFER
150 kΩ
VSS
FIGURE 4-1:
Input Circuitry.
Common-Mode Reference’s
When the VCAL pin is left open, the internal resistor
divider generates a VCM_INT of approximately VDD/3,
which is near the center of the input common mode
voltage range. It is recommended that an external
capacitor from VCAL to ground be added to improve
noise immunity.
Once the calibration event is completed, the amplifier is
reconnected to the external circuitry. The turn on time,
when calibration is started with the CAL/CS pin, is 3 ms
(typical).
There is an internal 5 MΩ pull-down resistor tied to the
CAL/CS pin. If the CAL/CS pin is left floating, the ampli-
fier operates normally.
When the VCAL pin is driven by an external voltage
source, which is within its specified range, the op amp
will have its input offset voltage calibrated at that com-
mon mode input voltage. Make sure that VCAL is within
its specified range.
© 2009 Microchip Technology Inc.
DS22146A-page 21
MCP651/2/5
It is possible to use an external resistor voltage divider
to modify VCM_INT; see Figure 4-2. The internal circuitry
at the VCAL pin looks like 100 kΩ tied to VDD/3. The
parallel equivalent of R1 and R2 should be much
smaller than 100 kΩ to minimize differences in match-
ing and temperature drift between the internal and
external resistors. Again, make sure that VCAL is within
its specified range.
Bond
Pad
VDD
VIN+
VSS
Bond
Pad
Bond
Pad
Input
Stage
VIN–
VDD
Bond
Pad
MCP65X
R1
FIGURE 4-3:
Structures.
Simplified Analog Input ESD
VCAL
C1
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-4 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
R2
VSS
FIGURE 4-2:
Resistors.
Setting V
with External
CM
For instance, a design goal to set VCM_INT = 0.1V when
VDD = 2.5V could be met with: R1 = 24.3 kΩ,
R2 = 1.00 kΩ and C1 = 100 nF. This will keep VCAL
within its range for any VDD, and should be close
enough to 0V for ground based applications.
4.2
Input
VDD
4.2.1
PHASE REVERSAL
D1
R1
D2
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-41 shows an input voltage
exceeding both supplies with no phase inversion.
MCP65X
V1
V2
VOUT
R2
4.2.2
INPUT VOLTAGE AND CURRENT
LIMITS
VSS – (minimum expected V1)
R1 >
R2 >
2 mA
VSS – (minimum expected V2)
2 mA
The ESD protection on the inputs can be depicted as
shown in Figure 4-3. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-4:
Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-15. Applications that are high impedance may
need to limit the usable voltage range.
DS22146A-page 22
© 2009 Microchip Technology Inc.
MCP651/2/5
4.2.3
NORMAL OPERATION
4.3.0.3
Power Dissipation
The input stage of the MCP651/2/5 op amps uses a dif-
ferential PMOS input stage. It operates at low common
mode input voltage (VCM), with VCM up to VDD – 1.3V
Since the output short circuit current (ISC) is specified
at ±100 mA (typical), these op amps are capable of
both delivering and dissipating significant power. Two
common loads, and their impact on the op amp’s power
dissipation, will be discussed.
and down to VSS – 0.3V. The input offset voltage (VOS
)
is measured at VCM = VSS – 0.3V and VDD – 1.3V to
ensure proper operation. See Figure 2-6 and
Figure 2-7 for temperature effects.
Figure 4-7 shows a resistive load (RL) with a DC output
voltage (VOUT). VL is RL’s ground point, VSS is usually
ground (0V) and IOUT is the output current. The input
currents are assumed to be negligible.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
(< VDD – 1.3V); see Figure 4-5
VDD
VDD
IDD
IOUT
MCP65X
VIN
VOUT
VOUT
MCP65X
RL
ISS
VSS < VIN, VOUT ≤ VDD – 1.3V
VSS
VL
FIGURE 4-5:
Unity Gain Voltage
Limitations for Linear Operation.
FIGURE 4-7:
Diagram for Resistive Load
Power Calculations.
4.3
Rail-to-Rail Output
The DC currents are:
4.3.0.1
Maximum Output Voltage
EQUATION 4-1:
The Maximum Output Voltage (see Figure 2-16 and
Figure 2-17) describes the output range for a given
load. For instance, the output voltage swings to within
15 mV of the negative rail with a 1 kΩ load tied to
VDD/2.
VOUT – VL
IOUT = -------------------------
RL
IDD ≈ IQ + max(0, IOUT
ISS ≈ –IQ + min(0, IOUT
)
)
Where:
4.3.0.2
Output Current
IQ = Quiescent supply current for one
Figure 4-6 shows the possible combinations of output
voltage (VOUT) and output current (IOUT). IOUT is
positive when it flows out of the op amp into the
external circuit.
op amp (mA/amplifier)
VOUT = A DC value (V)
The DC op amp power is:
6.0
VOH Limited
EQUATION 4-2:
5.5
(VDD = 5.5V)
5.0
4.5
POA = IDD(VDD – VOUT) + ISS(VSS – VOUT
)
RL = 1 kΩ
RL = 100Ω
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
RL = 10Ω
The maximum op amp power, for resistive loads at DC,
occurs when VOUT is halfway between VDD and VL or
halfway between VSS and VL:
VOL Limited
EQUATION 4-3:
max(POA) = IDD(VDD – VSS
)
IOUT (mA)
max2(VDD – VL, VL – VSS
)
+ -----------------------------------------------------------------
FIGURE 4-6:
Output Current.
4RL
© 2009 Microchip Technology Inc.
DS22146A-page 23
MCP651/2/5
Figure 4-7 shows a capacitive load (CL), which is
driven by a sine wave with DC offset. The capacitive
load causes the op amp to output higher currents at
EQUATION 4-7:
n
PPKG
=
POA
∑
higher frequencies. Because the output rectifies IOUT
,
k = 1
the op amp’s dissipated power increases (even though
the capacitor does not dissipate power).
Where:
n = Number of op amps in package (1 or 2)
VDD
The maximum ambient to junction temperature rise
(ΔTJA) and junction temperature (TJ) can be calculated
using the maximum expected package power (PPKG),
ambient temperature (TA) and the package thermal
resistance (θJA) found in Table 1-4:
IDD
IOUT
VOUT
MCP65X
CL
ISS
EQUATION 4-8:
VSS
ΔTJA = PPKGθJA
TJ = TA + ΔTJA
FIGURE 4-8:
Power Calculations.
Diagram for Capacitive Load
The output voltage is assumed to be:
The worst case power de-rating for the op amps in a
particular package can be easily calculated:
EQUATION 4-4:
EQUATION 4-9:
VOUT = VDC + VAC sin(ωt)
Where:
TJmax – TA
--------------------------
≤
PPKG
θJA
VDC = DC offset (V)
Where:
VAC = Peak output swing (VPK
)
ω = Radian frequency (2π f) (rad/s)
TJmax = Absolute maximum junction
temperature (°C)
TA = Ambient temperature (°C)
The op amp’s currents are:
EQUATION 4-5:
Several techniques are available to reduce ΔTJA for a
given package:
dVOUT
----------------
dt
IOUT = CL ⋅
= VACωCL cos(ωt)
• Reduce θJA
- Use another package
IDD ≈ IQ + max(0, IOUT
ISS ≈ –IQ + min(0, IOUT
Where:
)
)
- Improve the PCB layout (ground plane, etc.)
- Add heat sinks and air flow
• Reduce max(PPKG
- Increase RL
)
IQ = Quiescent supply current for one
op amp (mA/amplifier)
- Decrease CL
- Limit IOUT using RISO (see Figure 4-9)
- Decrease VDD
The op amp’s instantaneous power, average power
and peak power are:
EQUATION 4-6:
POA = IDD(VDD – VOUT) + ISS(VSS – VOUT
)
4VAC fCL
⎛
⎞
⎠
ave(POA) = (VDD – VSS) IQ + -----------------------
⎝
π
max(POA) = (VDD – VSS)(IQ + 2VAC fCL)
The power dissipated in a package depends on the
powers dissipated by each op amp in that package:
DS22146A-page 24
© 2009 Microchip Technology Inc.
MCP651/2/5
4.4.2
GAIN PEAKING
4.4
Improving Stability
Figure 4-11 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
4.4.1
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. See Figure 2-30. A unity gain buffer (G = +1)
is the most sensitive to capacitive loads, though all
gains show the same general behavior.
CN
RN
When driving large capacitive loads with these op
amps (e.g., > 20 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-9) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
MCP65X
VP
VOUT
VM
RG
RF
CG
FIGURE 4-11:
Amplifier with Parasitic
RISO
CL
RG
RF
Capacitance.
VOUT
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF.
MCP65X
RN
FIGURE 4-9:
Output Resistor, R
ISO
CN and RN form a low-pass filter that affects the signal
Stabilizes Large Capacitive Loads.
at VP. This filter has a single real pole at 1/(2πRNCN).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.4.1 “Capacitive
Loads”) and CG. Figure 4-12 shows the maximum
recommended RF for several CG values.
Figure 4-10 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
1.E+05
100k
GN > +1 V/V
CG = 10 pF
CG = 32 pF
CG = 100 pF
CG = 320 pF
CG = 1 nF
100
1.E+04
10k
1.E+013k
1.E+10020
10
GN = +1
GN ≥ +2
1
10
100
Noise Gain; GN (V/V)
1
10p
100p
1.E-10
1n
1.E-09
10n
1.E-11
1.E-08
FIGURE 4-12:
R vs. Gain.
Maximum Recommended
Normalized Capacitance; CL/GN (F)
F
FIGURE 4-10:
for Capacitive Loads.
Recommended R
Values
ISO
Figure 2-37 and Figure 2-38 show the small signal and
large signal step responses at G = +1 V/V. The unity
gain buffer usually has RF = 0Ω and RG open.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP651/2/5 SPICE macro model
are helpful.
Figure 2-39 and Figure 2-40 show the small signal and
large signal step responses at G = -1 V/V. Since the
noise gain is 2 V/V and CG ≈ 10 pF, the resistors were
chosen to be RF = RG = 499Ω and RN = 249Ω.
© 2009 Microchip Technology Inc.
DS22146A-page 25
MCP651/2/5
It is also possible to add a capacitor (CF) in parallel with
RF to compensate for the de-stabilizing effect of CG.
This makes it possible to use larger values of RF. The
conditions for stability are summarized in
Equation 4-10.
Use coax cables, or low inductance wiring, to route
signal and power to and from the PCB. Mutual and self
inductance of power wires is often a cause of crosstalk
and unusual behavior.
4.7
Typical Applications
EQUATION 4-10:
4.7.1
POWER DRIVER WITH HIGH GAIN
Given:
Figure 4-13 shows a power driver with high gain
(1 + R2/R1). The MCP651/2/5 op amp’s short circuit
current makes it possible to drive significant loads. The
calibrated input offset voltage supports accurate
response at high gains. R3 should be small, and equal
to R1||R2, in order to minimize the bias current induced
offset.
GN1 = 1 + RF ⁄ RG
GN2 = 1 + CG ⁄ CF
fF = 1 ⁄ (2πRFCF)
fZ = fF(GN1 ⁄ GN2
We need:
)
fF ≤ fGBWP ⁄ (2GN2), GN1 < GN2
fF ≤ fGBWP ⁄ (4GN1), GN1 > GN2
R1
R3
R2
VDD/2
VOUT
RL
4.5
Power Supply
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
VIN
MCP65X
FIGURE 4-13:
Power Driver.
4.7.2
OPTICAL DETECTOR AMPLIFIER
These op amps require a bulk capacitor (i.e., 2.2 µF or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
Figure 4-14 shows a transimpedance amplifier, using
the MCP651 op amp, in a photo detector circuit. The
photo detector is a capacitive current source. The op
amp’s input common mode capacitance (5 pF, typical)
acts in parallel with CD. RF provides enough gain to
produce 10 mV at VOUT. CF stabilizes the gain and lim-
its the transimpedance bandwidth to about 1.1 MHz.
RF’s parasitic capacitance (e.g., 0.2 pF for a 0805
SMD) acts in parallel with CF.
4.6
High Speed PCB Layout
These op amps are fast enough that a little extra care
in the PCB (Printed Circuit Board) layout can make a
significant difference in performance. Good PC board
layout techniques will help you achieve the
performance shown in the specifications and Typical
Performance Curves; it will also help you minimize
EMC (Electro-Magnetic Compatibility) issues.
CF
1.5 pF
Photo
Detector
RF
100 kΩ
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
VOUT
ID
CD
100 nA
30pF
Separate digital from analog, low speed from high
speed, and low power from high power. This will reduce
interference.
MCP651
VDD/2
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
FIGURE 4-14:
for an Optical Detector.
Transimpedance Amplifier
Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect guard traces
to ground plane at both ends, and in the middle for long
traces.
DS22146A-page 26
© 2009 Microchip Technology Inc.
MCP651/2/5
4.7.3
H-BRIDGE DRIVER
Figure 4-15 shows the MCP652 dual op amp used as
a H-bridge driver. The load could be a speaker or a DC
motor.
½ MCP652
VIN
VOT
RF
RF
RF
RL
RGT
RGB
VOB
VDD/2
½ MCP652
H-Bridge Driver.
FIGURE 4-15:
This circuit automatically makes the noise gains (GN)
equal, when the gains are set properly, so that the fre-
quency responses match well (in magnitude and in
phase). Equation 4-11 shows how to calculate RGT and
RGB so that both op amps have the same DC gains;
GDM needs to be selected first.
EQUATION 4-11:
V
– VOB
--------O---T---------------------
≥ 2 V/V
GDM
≡
VIN – VDD ⁄ 2
RF
RGT = --------------------------------
(GDM ⁄ 2) – 1
RF
RGB = ------------------
GDM ⁄ 2
Equation 4-12 gives the resulting common mode and
differential mode output voltages.
EQUATION 4-12:
VOT + VOB
-------------------------- = ----------
VDD
2
2
VDD
⎛
⎞
⎠
VOT – VOB = GDM VIN – ----------
⎝
2
© 2009 Microchip Technology Inc.
DS22146A-page 27
MCP651/2/5
NOTES:
DS22146A-page 28
© 2009 Microchip Technology Inc.
MCP651/2/5
5.5
Analog Demonstration and
Evaluation Boards
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP651/2/5 family of op amps.
Microchip offers a broad spectrum of Analog Demon-
stration and Evaluation Boards that are designed to
help customers achieve faster time to market. For a
complete listing of these boards and their correspond-
ing user’s guides and technical information, visit the
Microchip web site at www.microchip.com/analog
tools.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP651/2/5 op
amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Some boards that are especially useful are:
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the Micro-
chip web site at www.microchip.com/filterlab, the Fil-
ter-Lab design tool provides full schematic diagrams of
the filter circuit with component values. It also outputs
the filter circuit in SPICE format, which can be used
with the macro model to simulate actual filter perfor-
mance.
5.6
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
5.3
Mindi™ Circuit Designer &
Simulator
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams, and
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
Some of these application notes, and others, are listed
in the design guide:
• “Signal Chain Design Guide”, DS21825
5.4
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design require-
ment. Available at no cost from the Microchip website
at www.microchip.com/maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for Data sheets, Purchase and Sampling of
Microchip parts.
© 2009 Microchip Technology Inc.
DS22146A-page 29
MCP651/2/5
NOTES:
DS22146A-page 30
© 2009 Microchip Technology Inc.
MCP651/2/5
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
Example:
8-Lead DFN (3x3) (MCP652)
Device
MCP652
Code
XXXX
DABP
0913
256
DABP
YYWW
NNN
Note: Applies to 8-Lead
3x3 DFN
8-Lead SOIC (150 mil) (MCP651, MCP652)
Example:
MCP651E
XXXXXXXX
e
3
SN 0910
XXXXYYWW
256
NNN
10-Lead DFN (3x3) (MCP655)
Example:
XXXX
YYWW
NNN
BAFC
0910
256
Example:
10-Lead MSOP (MCP655)
655EUN
XXXXXX
YWWNNN
910256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS22146A-page 31
MCP651/2/5
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ꢑꢒꢊꢃꢉ%
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ
ꢏꢁ ꢂꢇꢍ*ꢇꢐꢉꢅ&ꢇꢋꢅꢎꢇꢆꢉꢅꢌꢄꢉꢅꢌꢊꢅ&ꢌꢊꢉꢅꢉ#ꢑꢌ ꢉ"ꢅ%ꢃꢉꢅ(ꢇꢊ ꢅꢇ%ꢅꢉꢄ" ꢁ
+ꢁ ꢂꢇꢍ*ꢇꢐꢉꢅꢃ ꢅ ꢇ)ꢅ ꢃꢄꢐ!ꢈꢇ%ꢉ"ꢁ
ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ
/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ
ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ
ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ:ꢏ/
DS22146A-page 32
© 2009 Microchip Technology Inc.
MCP651/2/5
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$
ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ
ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ
© 2009 Microchip Technology Inc.
DS22146A-page 33
MCP651/2/5
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ& ꢄꢈꢈꢆ'ꢎꢊꢈꢋ(ꢃꢆꢕ&ꢑꢗꢆMꢆꢑꢄ))ꢒ*ꢐꢆꢘꢛꢜꢚꢆ ꢆ!ꢒꢅ"ꢆ#&'+,$
ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ
ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
c
φ
A2
A
L
A1
L1
β
4ꢄꢃ%
ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ
ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%
ꢖꢙ6
67ꢖ
ꢖꢔ8
6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ
ꢂꢃ%ꢍꢎ
6
ꢉ
9
ꢀꢁꢏꢞꢅ/ꢕ0
7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%
ꢔ
M
ꢀꢁꢏ.
ꢚꢁꢀꢚ
M
M
M
ꢀꢁꢞ.
M
ꢚꢁꢏ.
ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅꢗꢎꢃꢍ*ꢄꢉ
ꢕ%ꢇꢄ"ꢌ$$ꢅꢅ
ꢔꢏ
ꢔꢀ
,
ꢝ
7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ
:ꢁꢚꢚꢅ/ꢕ0
ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅ<ꢃ"%ꢎ
7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ
0ꢎꢇ&$ꢉꢊꢅ@ꢌꢑ%ꢃꢌꢄꢇꢈA
2ꢌꢌ%ꢅ5ꢉꢄꢐ%ꢎ
,ꢀ
ꢓ
ꢎ
+ꢁꢛꢚꢅ/ꢕ0
ꢒꢁꢛꢚꢅ/ꢕ0
ꢚꢁꢏ.
ꢚꢁꢒꢚ
M
M
ꢚꢁ.ꢚ
ꢀꢁꢏꢞ
5
2ꢌꢌ%ꢑꢊꢃꢄ%
2ꢌꢌ%ꢅꢔꢄꢐꢈꢉ
5ꢉꢇ"ꢅꢗꢎꢃꢍ*ꢄꢉ
5ꢉꢇ"ꢅ<ꢃ"%ꢎ
ꢖꢌꢈ"ꢅꢓꢊꢇ$%ꢅꢔꢄꢐꢈꢉꢅꢗꢌꢑ
ꢖꢌꢈ"ꢅꢓꢊꢇ$%ꢅꢔꢄꢐꢈꢉꢅ/ꢌ%%ꢌ&
5ꢀ
ꢀ
ꢀꢁꢚꢒꢅꢘ,2
ꢚꢟ
ꢚꢁꢀꢞ
ꢚꢁ+ꢀ
.ꢟ
M
M
M
M
M
9ꢟ
ꢍ
(
ꢁ
ꢚꢁꢏ.
ꢚꢁ.ꢀ
ꢀ.ꢟ
ꢂ
.ꢟ
ꢀ.ꢟ
ꢑꢒꢊꢃꢉ%
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ
ꢏꢁ ꢝꢅꢕꢃꢐꢄꢃ$ꢃꢍꢇꢄ%ꢅ0ꢎꢇꢊꢇꢍ%ꢉꢊꢃ %ꢃꢍꢁ
+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢓꢅꢇꢄ"ꢅ,ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢖꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢚꢁꢀ.ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ
ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ
/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ
ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ
ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ.ꢞ/
DS22146A-page 34
© 2009 Microchip Technology Inc.
MCP651/2/5
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ& ꢄꢈꢈꢆ'ꢎꢊꢈꢋ(ꢃꢆꢕ&ꢑꢗꢆMꢆꢑꢄ))ꢒ*ꢐꢆꢘꢛꢜꢚꢆ ꢆ!ꢒꢅ"ꢆ#&'+,$
ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ
ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ
© 2009 Microchip Technology Inc.
DS22146A-page 35
MCP651/2/5
-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$
ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ
ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ
D
e
b
N
N
L
K
E
E2
EXPOSED
PAD
NOTE 1
NOTE 1
2
1
1
2
D2
BOTTOM VIEW
TOP VIEW
A
A1
A3
NOTE 2
4ꢄꢃ%
ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ
ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%
ꢖꢙ6
67ꢖ
ꢀꢚ
ꢚꢁ.ꢚꢅ/ꢕ0
ꢚꢁꢛꢚ
ꢖꢔ8
6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ
ꢂꢃ%ꢍꢎ
7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%
ꢕ%ꢇꢄ"ꢌ$$ꢅ
0ꢌꢄ%ꢇꢍ%ꢅꢗꢎꢃꢍ*ꢄꢉ
7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ
,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ5ꢉꢄꢐ%ꢎ
7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ
6
ꢉ
ꢔ
ꢔꢀ
ꢔ+
ꢓ
ꢓꢏ
,
ꢚꢁ9ꢚ
ꢚꢁꢚꢚ
ꢀꢁꢚꢚ
ꢚꢁꢚ.
ꢚꢁꢚꢏ
ꢚꢁꢏꢚꢅꢘ,2
+ꢁꢚꢚꢅ/ꢕ0
ꢏꢁ+.
+ꢁꢚꢚꢅ/ꢕ0
ꢀꢁ.9
ꢚꢁꢏ.
ꢚꢁꢒꢚ
M
ꢏꢁꢏꢚ
ꢏꢁꢒ9
,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ<ꢃ"%ꢎ
0ꢌꢄ%ꢇꢍ%ꢅ<ꢃ"%ꢎ
0ꢌꢄ%ꢇꢍ%ꢅ5ꢉꢄꢐ%ꢎ
0ꢌꢄ%ꢇꢍ%ꢜ%ꢌꢜ,#ꢑꢌ ꢉ"ꢅꢂꢇ"
,ꢏ
(
5
ꢀꢁꢒꢚ
ꢚꢁꢀ9
ꢚꢁ+ꢚ
ꢚꢁꢏꢚ
ꢀꢁꢞ.
ꢚꢁ+ꢚ
ꢚꢁ.ꢚ
M
>
ꢑꢒꢊꢃꢉ%
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ
ꢏꢁ ꢂꢇꢍ*ꢇꢐꢉꢅ&ꢇꢋꢅꢎꢇꢆꢉꢅꢌꢄꢉꢅꢌꢊꢅ&ꢌꢊꢉꢅꢉ#ꢑꢌ ꢉ"ꢅ%ꢃꢉꢅ(ꢇꢊ ꢅꢇ%ꢅꢉꢄ" ꢁ
+ꢁ ꢂꢇꢍ*ꢇꢐꢉꢅꢃ ꢅ ꢇ)ꢅ ꢃꢄꢐ!ꢈꢇ%ꢉ"ꢁ
ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ
/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ
ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ
ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ:+/
DS22146A-page 36
© 2009 Microchip Technology Inc.
MCP651/2/5
-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$
ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ
ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ
© 2009 Microchip Technology Inc.
DS22146A-page 37
MCP651/2/5
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DS22146A-page 38
© 2009 Microchip Technology Inc.
MCP651/2/5
APPENDIX A: REVISION HISTORY
Revision A (April 2009)
• Original Release of this Document.
© 2009 Microchip Technology Inc.
DS22146A-page 39
MCP651/2/5
NOTES:
DS22146A-page 40
© 2009 Microchip Technology Inc.
MCP651/2/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
a) MCP651T-E/SN:
Tape and Reel,
Extended Temperature,
8LD SOIC package.
Temperature
Range
Package
a) MCP652T-E/MF:
b) MCP652T-E/SN:
Tape and Reel,
Extended Temperature,
8LD DFN package.
Tape and Reel,
Extended Temperature,
8LD SOIC package.
Device:
MCP651:
MCP651T:
Single Op Amp
Single Op Amp (Tape and Reel)
(DFN and SOIC)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(DFN and SOIC)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(DFN and MSOP)
MCP652:
MCP652T:
a) MCP655T-E/MF:
b) MCP655T-E/UN:
Tape and Reel,
MCP655:
MCP655T:
Extended Temperature,
10LD DFN package.
Tape and Reel,
Extended Temperature,
10LD MSOP package.
Temperature Range:
Package:
E
=
=
-40°C to +125°C
MF
Plastic Dual Flat, No Lead (3x3 DFN),
8-lead, 10-lead
SN
UN
=
=
Plastic Small Outline, (3.90 mm), 8-lead
Plastic Micro Small Outline, (MSOP), 10-lead
© 2009 Microchip Technology Inc.
DS22146A-page 41
MCP651/2/5
NOTES:
DS22146A-page 42
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS22146A-page 43
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Cleveland
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS22146A-page 44
© 2009 Microchip Technology Inc.
相关型号:
MCP652-E/ML
DUAL OP-AMP, 200 uV OFFSET-MAX, 50 MHz BAND WIDTH, PQCC16, 4 X 4 MM, 0.90 MM HEIGHT, PLASTIC, QFN-16
MICROCHIP
MCP652-E/SL
DUAL OP-AMP, 200 uV OFFSET-MAX, 50 MHz BAND WIDTH, PDSO14, 3.90 MM, PLASTIC, SOIC-14
MICROCHIP
MCP652-E/ST
DUAL OP-AMP, 200 uV OFFSET-MAX, 50 MHz BAND WIDTH, PDSO14, 4.40 MM, PLASTIC, TSSOP-14
MICROCHIP
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