MCP6543-E/SL [MICROCHIP]
Push-Pull Output Sub-Microamp Comparators; 推挽输出亚微安比较型号: | MCP6543-E/SL |
厂家: | MICROCHIP |
描述: | Push-Pull Output Sub-Microamp Comparators |
文件: | 总34页 (文件大小:1169K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MCP6541/1R/1U/2/3/4
Push-Pull Output Sub-Microamp Comparators
Description
Features
• Low Quiescent Current: 600 nA/comparator (typ.)
• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
• CMOS/TTL-Compatible Output
The Microchip Technology Inc. MCP6541/2/3/4 family
of comparators is offered in single (MCP6541,
MCP6541R, MCP6541U), single with Chip Select (CS)
(MCP6543), dual (MCP6542) and quad (MCP6544)
configurations. The outputs are push-pull (CMOS/TTL-
compatible) and are capable of driving heavy DC or
capacitive loads.
• Propagation Delay: 4 µs (typ., 100 mV Overdrive)
• Wide Supply Voltage Range: 1.6V to 5.5V
• Available in Single, Dual and Quad
• Single available in SOT-23-5, SC-70-5 * packages
• Chip Select (CS) with MCP6543
• Low Switching Current
These comparators are optimized for low power, single-
supply operation with greater than rail-to-rail input
operation.
The
push-pull
output
of
the
MCP6541/1R/1U/2/3/4 family supports rail-to-rail output
swing and interfaces with TTL/CMOS logic. The internal
input hysteresis eliminates output switching due to inter-
nal input noise voltage, reducing current draw. The out-
put limits supply current surges and dynamic power
consumption while switching. This product family oper-
ates with a single-supply voltage as low as 1.6V and
draws less than 1 µA/comparator of quiescent current.
• Internal Hysteresis: 3.3 mV (typ.)
• Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Typical Applications
• Laptop Computers
• Mobile Phones
The related MCP6546/7/8/9 family of comparators from
Microchip has an open-drain output. Used with a pull-up
resistor, these devices can be used as level-shifters for
any desired voltage up to 10V and in wired-OR logic.
• Metering Systems
• Hand-held Electronics
• RC Timers
* SC-70-5 E-Temp parts not available at this release of
the data sheet.
• Alarm and Monitoring Circuits
• Windowed Comparators
• Multi-vibrators
MCP6541U SOT-23-5 is E-Temp only.
Related Devices
• Open-Drain Output: MCP6546/7/8/9
Package Types
MCP6541
MCP6541R
MCP6542
MCP6544
PDIP, SOIC, MSOP
PDIP, SOIC, TSSOP
PDIP, SOIC, MSOP
SOT-23-5
VDD
OUTA
14 OUTD
OUTA
1
2
3
4
VSS
5
1
2
3
4
8
7
6
5
NC
1
2
3
4
8 NC
OUT
VDD
1
VINA
–
+
- + + 13 VIND
-
–
+
VINA
–
+
OUTB
-
+
V –
-
+
VDD
7
-
2
3
IN
VINA
12 VIND
VINA
+
VINB
VINB
–
+
-
V +
6
5
OUT
NC
VIN+
VIN–
4
IN
VDD
V
11
VSS
VSS
SS
VINB
+
–
10 VINC
+
–
5
6
7
MCP6541
SOT-23-5, SC-70-5
MCP6541U
MCP6543
PDIP, SOIC, MSOP
-
-
+ +
VINB
9 VINC
SOT-23-5
OUTB
8 OUTC
NC
VIN–
VIN+
VSS
CS
VDD
VDD
VDD
5
1
2
3
4
8
7
6
5
OUT
VSS
VIN–
VSS
1
2
3
5
1
-
+
-
+
-
2
3
OUT
NC
VIN+
VIN– VIN+
OUT
4
4
© 2006 Microchip Technology Inc.
DS21696E-page 1
MCP6541/1R/1U/2/3/4
† Notice: Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at those or any other conditions above those indicated
in the operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
Current at Analog Input Pin (VIN+, VIN-.........................±2 mA
Analog Input (VIN) †† ...................... VSS - 1.0V to VDD + 1.0V
All other Inputs and Outputs........... VSS - 0.3V to VDD + 0.3V
†† See Section 4.1.2 “Input Voltage and Current
Limits”
Difference Input voltage ....................................... |VDD - VSS
|
Output Short-Circuit Current .................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD protection on all pins (HBM;MM) ...................4 kV; 400V
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C,VIN+ = VDD/2,
VIN– = VSS, and RL = 100 kΩ to VDD/2 (Refer to Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Power Supply
Supply Voltage
VDD
IQ
1.6
0.3
—
5.5
1.0
V
Quiescent Current per comparator
Input
0.6
µA
IOUT = 0
Input Voltage Range
VCMR
CMRR
CMRR
CMRR
PSRR
VOS
VSS−0.3
55
—
70
VDD+0.3
—
V
Common Mode Rejection Ratio
Common Mode Rejection Ratio
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Input Offset Voltage
dB
dB
dB
dB
mV
VDD = 5V, VCM = -0.3V to 5.3V
VDD = 5V, VCM = 2.5V to 5.3V
VDD = 5V, VCM = -0.3V to 2.5V
VCM = VSS
50
65
—
55
70
—
63
80
—
-7.0
—
±1.5
±3
+7.0
—
VCM = VSS (Note 1)
Drift with Temperature
ΔVOS/ΔTA
VHYST
TC1
µV/°C TA = -40°C to +125°C, VCM = VSS
mV VCM = VSS (Note 1)
Input Hysteresis Voltage
Linear Temp. Co. (Note 2)
Quadratic Temp. Co. (Note 2)
Input Bias Current
1.5
—
3.3
6.5
—
6.7
µV/°C TA = -40°C to +125°C, VCM = VSS
µV/°C2 TA = -40°C to +125°C, VCM = VSS
TC2
—
-0.035
1
—
IB
—
—
pA
pA
VCM = VSS
At Temperature (I-Temp parts)
At Temperature (E-Temp parts)
Input Offset Current
IB
—
25
100
5000
—
TA = +85°C, VCM = VSS (Note 3)
TA = +125°C, VCM = VSS (Note 3)
VCM = VSS
IB
—
1200
pA
IOS
—
±1
pA
Common Mode Input Impedance
Differential Input Impedance
ZCM
—
1013||4
1013||2
—
Ω||pF
Ω||pF
ZDIFF
—
—
Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
2:
V
HYST at different temperatures is estimated using VHYST (TA) = VHYST + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
3: Input bias current at temperature is not tested for SC-70-5 package.
4: Limit the output current to Absolute Maximum Rating of 30 mA.
DS21696E-page 2
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C,VIN+ = VDD/2,
VIN– = VSS, and RL = 100 kΩ to VDD/2 (Refer to Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Push-Pull Output
High-Level Output Voltage
Low-Level Output Voltage
Short-Circuit Current
VOH
VOL
ISC
VDD−0.2
—
—
—
VSS+0.2
—
V
V
I
I
= -2 mA, V = 5V
DD
OUT
—
—
—
= 2 mA, V = 5V
OUT
DD
-2.5, +1.5
±30
mA
mA
VDD = 1.6V (Note 4)
VDD = 5.5V (Note 4)
ISC
—
Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
2: VHYST at different temperatures is estimated using VHYST (TA) = VHYST + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
3: Input bias current at temperature is not tested for SC-70-5 package.
4: Limit the output current to Absolute Maximum Rating of 30 mA.
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2,
Step = 200 mV, Overdrive = 100 mV, and CL = 36 pF (Refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Rise Time
Fall Time
tR
—
—
—
—
—
—
—
—
0.85
0.85
4
—
—
8
µs
µs
µs
µs
µs
tF
Propagation Delay (High-to-Low)
Propagation Delay (Low-to-High)
Propagation Delay Skew
tPHL
tPLH
tPDS
fMAX
fMAX
Eni
4
8
±0.2
160
120
200
—
—
—
—
(Note 1)
Maximum Toggle Frequency
kHz VDD = 1.6V
kHz VDD = 5.5V
Input Noise Voltage
µVP-P 10 Hz to 100 kHz
Note 1: Propagation Delay Skew is defined as: tPDS = tPLH - tPHL
.
MCP6543 CHIP SELECT (CS) CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = VSS
,
and CL= 36 pF (Refer to Figures 1-1 and 1-3).
Parameters
Sym
Min
Typ
Max Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
VIL
VSS
—
—
0.2 VDD
—
V
CS Input Current, Low
ICSL
5.0
pA
CS = VSS
CS High Specifications
CS Logic Threshold, High
VIH
ICSH
IDD
0.8 VDD
—
1
VDD
—
V
CS Input Current, High
—
—
—
—
pA
pA
pA
pA
CS = VDD
CS = VDD
CS = VDD
CS Input High, VDD Current
CS Input High, GND Current
Comparator Output Leakage
CS Dynamic Specifications
18
–20
1
—
ISS
—
IO(LEAK)
—
VOUT = VDD, CS = VDD
CS Low to Comparator Output Low
Turn-on Time
tON
tOFF
—
—
—
2
50
—
—
ms
µs
V
CS = 0.2 VDD to VOUT = VDD/2,
V
IN– = VDD
CS = 0.8 VDD to VOUT = VDD/2,
IN– = VDD
VDD = 5V
CS High to Comparator Output
High Z Turn-off Time
10
0.6
V
CS Hysteresis
VCS_HYST
© 2006 Microchip Technology Inc.
DS21696E-page 3
MCP6541/1R/1U/2/3/4
CS
VIL
VIH
VIN–
100 mV
tON
Hi-Z
tOFF
VIN+ = VDD/2
tPHL
100 mV
VOUT
Hi-Z
tPLH
VOH
-0.6 µA (typ.)
-20 pA (typ.)
1 pA (typ.)
-20 pA (typ.)
1 pA (typ.)
ISS
ICS
VOUT
VOL
VOL
FIGURE 1-1:
Timing Diagram for the CS
FIGURE 1-2:
Propagation Delay Timing
Pin on the MCP6543.
Diagram.
DS21696E-page 4
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SC-70
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
TA
-40
-40
-65
—
—
—
+85
+125
+150
°C
°C Note
°C
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
—
—
—
—
—
—
—
—
331
256
85
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
163
206
70
120
100
Note:
The MCP6541/2/3/4 I-Temp parts operate over this extended temperature range, but with reduced perfor-
mance. In any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification
of +150°C.
1.1
Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
VDD
200 kΩ
MCP654X
200 kΩ
VOUT
36 pF
200 kΩ
VIN = VSS
200 kΩ
VSS = 0V
FIGURE 1-3:
AC and DC Test Circuit for
the Push-Pull Output Comparators.
© 2006 Microchip Technology Inc.
DS21696E-page 5
MCP6541/1R/1U/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
14%
12%
10%
8%
18%
16%
14%
12%
10%
8%
1200 Samples
CM = VSS
1200 Samples
CM = VSS
V
V
6%
6%
4%
4%
2%
2%
0%
0%
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
Input Hysteresis Voltage (mV)
Input Offset Voltage (mV)
FIGURE 2-1:
Input Offset Voltage at
FIGURE 2-4:
Input Hysteresis Voltage at
V
= V
.
V
= V
.
CM
SS
CM
SS
25%
20%
15%
10%
5%
16%
14%
596 Samples
1200 Samples
CM = VSS
V
CM = VSS
V
TA = -40°C to +125°C
12% TA= -40°C to +125°C
10%
8%
6%
4%
2%
0%
VDD = 5.5V
VDD = 1.6V
0%
Input Hysteresis Voltage –
Linear Temp. Co.; TC1 (µV/°C)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Input Offset Voltage Drift at
FIGURE 2-5:
Input Hysteresis Voltage
V
= V
.
Linear Temp. Co. (TC ) at V
= V
.
CM
SS
1
CM
SS
20%
18%
7
6
596 Samples
VDD = 5.5V
VCM = VSS
16%
14%
12%
10%
8%
TA = -40°C to +125°C
VOUT
5
VDD = 5.5V
4
3
VDD = 1.6V
6%
4%
2%
0%
2
1
VIN–
0
-1
Input Hysteresis Voltage –
Quadratic Temp. Co.; TC2 (µV/°C2)
0
1
2
3
4
5
6
7
8
9
10
Time (1 ms/div)
FIGURE 2-3:
The MCP6541/1R/1U/2/3/4
FIGURE 2-6:
Input Hysteresis Voltage
comparators show no phase reversal.
Quadratic Temp. Co. (TC ) at V
= V
.
2
CM
SS
DS21696E-page 6
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
1.0
0.8
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
VCM = VSS
VCM = VSS
0.6
0.4
VDD = 1.6V
VDD = 5.5V
0.2
0.0
VDD = 1.6V
VDD = 5.5V
-0.2
-0.4
-0.6
-0.8
-1.0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
Input Hysteresis Voltage vs.
Ambient Temperature at V
= V
.
Ambient Temperature at V
= V
.
CM
SS
CM
SS
2.0
6.0
VDD = 1.6V
VDD = 1.6V
TA = +125°C
5.5
1.5
T
T
A = +85°C
A = +25°C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
TA = +125°C
0.0
T
T
A = +85°C
A = +25°C
TA = +125°C
-0.5
-1.0
-1.5
-2.0
TA = -40°C
TA = -40°C
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
Input Hysteresis Voltage vs.
Common Mode Input Voltage at V = 1.6V.
Common Mode Input Voltage at V = 1.6V.
DD
DD
2.0
6.0
VDD = 5.5V
1.5
VDD = 5.5V
TA = +125°C
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
T
T
A = +85°C
A = +25°C
TA = -40°C
A = +25°C
1.0
T
TA = -40°C
0.5
0.0
-0.5
-1.0
-1.5
-2.0
TA = +85°C
A = +125°C
T
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Input Hysteresis Voltage vs.
Common Mode Input Voltage at V = 5.5V.
Common Mode Input Voltage at V = 5.5V.
DD
DD
© 2006 Microchip Technology Inc.
DS21696E-page 7
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
90
85
80
75
70
65
60
55
100100n
10010n
VDD = 5.5V
Input Referred
IB, TA = +125°C
IB, TA = +85°C
100p
1 0
PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V
CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V
10p
10
IOS, TA = +125°C
IOS, TA = +85°C
1p
1
100f
0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-13:
CMRR,PSRR vs. Ambient
FIGURE 2-16:
Input Bias Current, Input
Temperature.
Offset Current vs. Common Mode Input Voltage.
1000
0.7
0.6
0.5
0.4
VDD = 5.5V
VCM = VDD
100
10
1
IB
TA = +125°C
A = +85°C
TA = +25°C
A = -40°C
0.3
0.2
0.1
0.0
| IOS
|
T
T
0.1
55
65
75
85
95 105 115 125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-14:
Input Bias Current, Input
FIGURE 2-17:
Quiescent Current vs.
Offset Current vs. Ambient Temperature.
Power Supply Voltage.
0.7
0.7
VDD = 1.6V
VDD = 5.5V
0.6
0.5
0.4
0.3
0.6
0.5
0.4
0.3
0.2
0.2
Sweep VIN+, VIN– = VDD/2
Sweep VIN+, VIN– = VDD/2
0.1
0.0
0.1
Sweep VIN–, VIN+ = VDD/2
Sweep VIN–, VIN+ = VDD/2
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Common Mode Input Voltage (V)
FIGURE 2-15:
Quiescent Current vs.
FIGURE 2-18:
Quiescent Current vs.
Common Mode Input Voltage at V = 1.6V.
Common Mode Input Voltage at V = 5.5V.
DD
DD
DS21696E-page 8
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
35
10
TA = -40°C
TA = +25°C
A = +85°C
A = +125°C
100 mV Overdrive
CM = VDD/2
RL = infinity
30
25
20
15
10
5
V
T
T
1
VDD = 5.5V
VDD = 1.6V
0
0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
0.1
1
10
100
Toggle Frequency (kHz)
FIGURE 2-19:
Supply Current vs. Toggle
FIGURE 2-22:
Output Short Circuit Current
Frequency.
Magnitude vs. Power Supply Voltage.
1.0
0.8
VOL – VSS
TA = +125°C
TA = +85°C
:
VDD = 1.6V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VOL–VSS
:
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
TA = +125°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
TA = +25°C
TA = -40°C
VDD – VOH
:
VDD–VOH
:
TA = +125°C
TA = +85°C
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
T
T
A = +25°C
A = -40°C
VDD = 5.5V
10
0
5
15
20
25
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Output Current (mA)
Output Current (mA)
FIGURE 2-20:
Output Voltage Headroom
FIGURE 2-23:
Output Voltage Headroom
vs. Output Current at V = 1.6V.
vs. Output Current at V = 5.5V.
DD
DD
45%
45%
600 Samples
100 mV Overdrive
600 Samples
100 mV Overdrive
VCM = VDD/2
40%
40%
35%
30%
25%
20%
15%
10%
5%
35%
V
CM = VDD/2
30%
25%
20%
15%
10%
5%
VDD = 1.6V
VDD = 5.5V
VDD = 1.6V
VDD = 5.5V
0%
0%
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
High-to-Low Propagation Delay (µs)
Low-to-High Propagation Delay (µs)
FIGURE 2-21:
High-to-Low Propagation
FIGURE 2-24:
Low-to-High Propagation
Delay.
Delay.
© 2006 Microchip Technology Inc.
DS21696E-page 9
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
45%
40%
35%
30%
25%
20%
15%
10%
5%
8
7
6
5
4
3
2
1
0
100 mV Overdrive
CM = VDD/2
600 Samples
100 mV Overdrive
V
V
CM = VDD/2
tPLH @ VDD = 5.5V
tPHL @ VDD = 5.5V
VDD = 1.6V
VDD = 5.5V
tPLH @ VDD = 1.6V
tPHL @ VDD = 1.6V
0%
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Propagation Delay Skew (µs)
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-25:
Propagation Delay Skew.
FIGURE 2-28:
Propagation Delay vs.
Ambient Temperature.
14
100
VCM = VDD/2
tPLH @ 10 mV Overdrive
13
12
11
10
9
VCM = VDD/2
tPHL @ VDD = 5.5V
t
t
PLH @ VDD = 1.6V
PHL @ VDD = 1.6V
8
7
tPHL @ 10 mV Overdrive
tPLH @ 100 mV Overdrive
10
6
5
4
tPLH @ VDD = 5.5V
3
tPHL @ 100 mV Overdrive
2
1
0
1
1.5
2.0
2.5
3.0 3.5
4.0
4.5
5.0 5.5
1
10
100
1000
Power Supply Voltage (V)
Input Overdrive (mV)
FIGURE 2-26:
Propagation Delay vs.
FIGURE 2-29:
Propagation Delay vs. Input
Power Supply Voltage.
Overdrive.
8
8
VDD = 1.6V
100 mV Overdrive
VDD = 5.5V
7
7
100 mV Overdrive
6
5
4
3
2
1
0
6
5
4
3
2
1
0
tPHL
tPLH
tPLH
tPHL
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-27:
Propagation Delay vs.
FIGURE 2-30:
Propagation Delay vs.
Common Mode Input Voltage at V = 1.6V.
Common Mode Input Voltage at V = 5.5V.
DD
DD
DS21696E-page 10
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
6.0
50
VDD = 5.5V
100 mV Overdrive
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
45
40
35
30
25
20
15
10
5
VCM = VDD/2
tPHL @ VDD = 1.6V
tPLH @ VDD = 1.6V
VOUT
CS
tPHL @ VDD = 5.5V
tPLH @ VDD = 5.5V
0
0
10 20 30 40 50 60 70 80 90
Load Capacitance (nF)
0
1
2
3
4
5
6
7
8
9
10
Time (ms)
FIGURE 2-31:
Propagation Delay vs. Load
FIGURE 2-34:
Chip Select (CS) Step
Capacitance.
Response (MCP6543 only).
1.E-10m3
1.E-03
1m
Comparator
Turns On
Comparator
Shuts Off
Comparator
Turns On
Comparator
Shuts Off
100µ
1.E-04
1.E- 4
100µ
10µ
1.E-05
10µ
1.E- 5
1µ
1.E-06
1µ
1.E-06
CS Hysteresis
CS
Hysteresis
100n
1.E-07
100n
1.E- 7
10n
1.E-08
10n
1.E- 8
CS
High-to-Low
CS
CS
CS
1n
1.E-09
1n
1.E-09
Low-to-High
High-to-Low
Low-to-High
100p
1.E-10
100p
1.E-10
VDD = 1.6V
VDD = 5.5V
10p
1.E-11
10p
1.E-11
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Chip Select (CS) Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select (CS) Voltage (V)
FIGURE 2-32:
Supply Current (shoot
FIGURE 2-35:
Supply Current (shoot
through current) vs. Chip Select (CS) Voltage at
through current) vs. Chip Select (CS) Voltage at
V
= 1.6V (MCP6543 only).
V
= 5.5V (MCP6543 only).
DD
DD
6
1.6
VOUT
CS
3
0.0
VOUT
0
CS
140
20
120
VDD = 1.6V
Start-up IDD
100
80
60
40
20
0
15
VDD = 5.5V
Start-up
IDD
Charging output
capacitance
10
5
Charging output
capacitance
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Time (0.5 ms/div)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
Time (1 ms/div)
FIGURE 2-33:
Supply Current (charging
FIGURE 2-36:
Supply Current (charging
current) vs. Chip Select (CS) pulse at V = 1.6V
current) vs. Chip Select (CS) pulse at V = 5.5V
DD
DD
(MCP6543 only).
(MCP6543 only).
© 2006 Microchip Technology Inc.
DS21696E-page 11
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
1.E-02
10m
1.E-03
1m
1.E-04
100µ
1.E1-005µ
1.E-016µ
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
+125°C
+85°C
+25°C
-40°C
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-37:
Input Bias Current vs. Input
Voltage
DS21696E-page 12
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6541
(PDIP,
SOIC,
MCP6541
(SOT-23-5,
MSOP)
SC-70-5)
Symbol
Description
6
2
1
1
4
1
2
6
2
1
2
OUT, OUTA Digital Output (comparator A)
VIN–, VINA– Inverting Input (comparator A)
VIN+, VINA+ Non-inverting Input (comparator A)
4
4
1
3
3
3
3
3
3
3
7
5
2
5
8
7
4
VDD
Positive Power Supply
—
—
—
—
—
—
4
—
—
—
—
—
—
2
—
—
—
—
—
—
5
—
—
—
—
—
—
2
5
—
—
—
—
—
—
4
5
VINB
+
Non-inverting Input (comparator B)
Inverting Input (comparator B)
Digital Output (comparator B)
Digital Output (comparator C)
Inverting Input (comparator C)
Non-inverting Input (comparator C)
Negative Power Supply
6
6
VINB
–
7
7
OUTB
OUTC
—
—
—
4
8
9
VINC
–
+
10
11
12
13
14
—
—
VINC
VSS
—
—
—
—
1, 5, 8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
VIND
VIND
+
Non-inverting Input (comparator D)
Inverting Input (comparator D)
Digital Output (comparator D)
Chip Select
–
OUTD
CS
1, 5
NC
No Internal Connection
3.1
Analog Inputs
3.4
Power Supply (VSS and VDD)
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
The positive power supply pin (VDD) is 1.6V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD
.
3.2
CS Digital Input
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These can share a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
3.3
Digital Outputs
The comparator outputs are CMOS, push-pull digital
outputs. They are designed to be compatible with
CMOS and TTL logic and are capable of driving heavy
DC or capacitive loads.
© 2006 Microchip Technology Inc.
DS21696E-page 13
MCP6541/1R/1U/2/3/4
the resistors R1 and R2 limit the possible current drawn
out of the input pin. Diodes D1 and D2 prevent the input
4.0
APPLICATIONS INFORMATION
The MCP6541/2/3/4 family of push-pull output compar-
ators are fabricated on Microchip’s state-of-the-art
CMOS process. They are suitable for a wide range of
applications requiring very low power consumption.
pin (VIN+ and VIN–) from going too far above VDD
.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
VDD
4.1
Comparator Inputs
4.1.1
PHASE REVERSAL
D1
The MCP6541/1R/1U/2/3/4 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
+
V1
R1
VOUT
MCP6G0X
–
D2
V2
R2
R3
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
VSS – (minimum expected V1)
2 mA
R1 ≥
R2 ≥
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to pro-
tect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
VSS – (minimum expected V2)
2 mA
FIGURE 4-2:
Protecting the Analog Inputs.
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
Bond
VDD
Pad
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-37. Applications that are
high impedance may need to limit the useable voltage
range.
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
4.1.3
NORMAL OPERATION
Bond
Pad
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages. With
this topology, the input voltage is 0.3V above VDD and
0.3V below VSS. Therefore, the input offset voltage is
measured at both VSS - 0.3V and VDD + 0.3V to ensure
proper operation.
VSS
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
The MCP6541/1R/1U/2/3/4 family has internally-set
hysteresis that is small enough to maintain input offset
accuracy (<7 mV) and large enough to eliminate output
chattering caused by the comparator’s own input noise
voltage (200 µVp-p). Figure 4-3 depicts this behavior.
DS21696E-page 14
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
4.4
Externally Set Hysteresis
25
20
15
10
5
VDD = 5.0V
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
VIN–
5
Input offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points. Hysteresis reduces output
chattering when one input is slowly moving past the
other and thus reduces dynamic supply current. It also
helps in systems where it is best not to cycle between
states too frequently (e.g., air conditioner thermostatic
control).
VOUT
4
3
0
2
-5
Hysteresis
1
-10
-15
-20
-25
-30
0
Time (100 ms/div)
FIGURE 4-3:
comparators’ internal hysteresis eliminates
output chatter caused by input noise voltage.
The MCP6541/2/3/4
4.4.1
NON-INVERTING CIRCUIT
Figure 4-4 shows a non-inverting circuit for single-
supply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
4.2
Push-Pull Output
The push-pull output is designed to be compatible with
CMOS and TTL logic, while the output transistors are
configured to give rail-to-rail output performance. They
are driven with circuitry that minimizes any switching
current (shoot-through current from supply-to-supply)
when the output is transitioned from high-to-low, or from
low-to-high (see Figures 2-15, 2-18, 2-32 through 2-36
for more information).
VDD
VREF
-
VOUT
MCP654X
+
VIN
R1
RF
Non-inverting circuit with
4.3
MCP6543 Chip Select (CS)
The MCP6543 is a single comparator with Chip Select
(CS). When CS is pulled high, the total current
consumption drops to 20 pA (typ.); 1 pA (typ.) flows
through the CS pin, 1 pA (typ.) flows through the out-
put pin and 18 pA (typ.) flows through the VDD pin, as
shown in Figure 1-1. When this happens, the
comparator output is put into a high-impedance state.
By pulling CS low, the comparator is enabled. If the CS
pin is left floating, the comparator will not operate
properly. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
FIGURE 4-4:
hysteresis for single-supply.
VOUT
VDD
VOH
High-to-Low
Low-to-High
VIN
VOL
VSS
The internal CS circuitry is designed to minimize
glitches when cycling the CS pin. This helps conserve
power, which is especially important in battery-powered
applications.
VSS
VTHL VTLH
VDD
FIGURE 4-5:
Hysteresis Diagram for the
Non-Inverting Circuit.
The trip points for Figures 4-4 and 4-5 are:
EQUATION 4-1:
R
R
⎛
⎜
⎝
⎞
⎛
⎞
⎟
⎠
1
1
------
⎜
V
= V
1 +------ – V
⎟
TLH
REF
OL
R
R
⎠
⎝
F
F
R
R
⎞
⎛
⎜
⎝
⎛
⎜
⎝
⎞
⎟
⎠
1
1
------
V
= V
1 +------ – V
⎟
THL
REF
OH
R
F
R
⎠
F
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
© 2006 Microchip Technology Inc.
DS21696E-page 15
MCP6541/1R/1U/2/3/4
Where:
4.4.2
INVERTING CIRCUIT
Figure 4-6 shows an inverting circuit for single-supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
R2R3
R23 = ------------------
R2 + R3
R3
------------------
VDD
V23
=
× VDD
R2 + R3
VIN
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
VDD
VOUT
MCP654X
R2
R3
EQUATION 4-2:
R23
RF
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎝
⎞
⎠
----------------------
---------------------
R23 + RF
VTHL = VOH
+ V
+ V
RF
23
R
23 + R
F
R23
RF
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎝
⎞
⎠
----------------------
---------------------
VTLH = VOL
23
R
23 + R
R23 + RF
F
FIGURE 4-6:
Hysteresis.
Inverting Circuit With
V
TLH = trip voltage from low to high
VTHL = trip voltage from high to low
VOUT
Figure 2-20 and Figure 2-23 can be used to determine
typical values for VOH and VOL
VDD
VOH
.
Low-to-High
High-to-Low
4.5
Bypass Capacitors
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
VIN
VOL
VSS
VSS
VTLH VTHL
VDD
FIGURE 4-7:
Hysteresis Diagram for the
Inverting Circuit.
4.6
Capacitive Loads
In order to determine the trip voltages (VTHL and VTLH
)
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-31).
The supply current increases with increasing toggle
frequency (Figure 2-19), especially with higher
capacitive loads.
for the circuit shown in Figure 4-6, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-8.
VDD
4.7
Battery Life
-
MCP654X
In order to maximize battery life in portable
applications, use large resistors and small capacitive
loads. Avoid toggling the output more than necessary.
Do not use Chip Select (CS) frequently to conserve
start-up power. Capacitive loads will draw additional
power at start-up.
VOUT
+
VSS
V23
R23
RF
Thevenin Equivalent Circuit.
FIGURE 4-8:
DS21696E-page 16
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
4.8
PCB Surface Leakage
4.9
Unused Comparators
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6541/1R/1U/2/3/4 family’s bias current at 25°C
(1 pA, typ.).
An unused amplifier in a quad package (MCP6544)
should be configured as shown in Figure 4-10. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-18).
¼ MCP6544
VDD
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
–
+
VIN-
VIN+
VSS
FIGURE 4-10:
Unused Comparators.
Guard Ring
Example Guard Ring Layout
FIGURE 4-9:
for Inverting Circuit.
1. Inverting Configuration (Figures 4-6 and 4-9):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
pad without touching the guard ring.
2. Non-inverting Configuration (Figure 4-4):
a. Connect the non-inverting pin (VIN+) to the
input pad without touching the guard ring.
b. Connect the guard ring to the inverting input
pin (VIN–).
© 2006 Microchip Technology Inc.
DS21696E-page 17
MCP6541/1R/1U/2/3/4
4.10.3
BISTABLE MULTI-VIBRATOR
4.10 Typical Applications
A simple bistable multi-vibrator design is shown in
Figure 4-13. VREF needs to be between the power
supplies (VSS = GND and VDD) to achieve oscillation.
4.10.1
PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041) to gain-up the input signal
before it reaches the comparator. Figure 4-11 shows an
example of this approach.
The output duty cycle changes with VREF
.
R1
R2
VREF
VDD
VDD
VREF
VOUT
MCP6541
MCP6041
VDD
MCP654X
VIN
C1
R3
R1
R2
VREF
VOUT
FIGURE 4-13:
Bistable Multi-vibrator.
FIGURE 4-11:
Precise Inverting
Comparator.
4.10.2
WINDOWED COMPARATOR
Figure 4-12 shows one approach to designing a win-
dowed comparator. The AND gate produces a logic ‘1’
when the input voltage is between VRB and VRT (where
VRT > VRB).
VRT
1/2
MCP6542
VIN
1/2
MCP6542
VRB
FIGURE 4-12:
Windowed Comparator.
DS21696E-page 18
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SC-70 (MCP6541)
Example:
I-Temp
Code
E-Temp
Code
Device
XXNN Front)
YWW (Back)
AB25 Front)
636 (Back)
MCP6541U
ABNN
Note 2
Note 1: I-Temp parts prior to March
2005 are marked “ABN”
2: SC-70-5 E-Temp parts not
available at this release of
this data sheet.
Example:
5-Lead SOT-23 (MCP6541, MCP6541R, MCP6541U)
I-Temp
Code
E-Temp
Code
Device
MCP6541
MCP6541R
MCP6541U
Note:
ABNN
AGNN
—
GTNN
GUNN
ATNN
XXNN
AB25
Applies to 5-Lead SOT-23
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP6541
I/P256
0636
MCP6541
E/P^256
0636
e
3
OR
YYWW
8-Lead SOIC (150 mil)
Example:
MCP6542
XXXXXXXX
XXXXYYWW
MCP6541E
I/SN0636
SN^0636
e
3
OR
NNN
256
256
Example:
8-Lead MSOP
XXXXXX
YWWNNN
6543I
636256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS21696E-page 19
MCP6541/1R/1U/2/3/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6544)
Example:
MCP6544-I/P
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
0636256
e
3
MCP6544E/P
OR
OR
0636256
MCP6544
I/P^
e
3
0636256
14-Lead SOIC (150 mil) (MCP6544)
Example:
MCP6544ISL
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
0636256
MCP6544
e
3
E/SL^
OR
0636256
Example:
14-Lead TSSOP (MCP6544)
XXXXXXXX
YYWW
MCP6544I
0636
NNN
256
DS21696E-page 20
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
5-Lead Plastic Small Outline Transistor (LT) (SC-70)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
D
p
B
n
1
Q1
A2
A
c
A1
L
Units
INCHES
NOM
MILLIMETERS
NOM
*
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
5
5
.026 (BSC)
0.65 (BSC)
Overall Height
A
A2
A1
E
.031
.043
0.80
1.10
Molded Package Thickness
Standoff
.031
.000
.071
.045
.071
.004
.039
.004
.094
.053
.087
.012
0.80
0.00
1.80
1.15
1.80
0.10
1.00
0.10
2.40
1.35
2.20
0.30
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
Top of Molded Pkg to
Lead Shoulder
Q1
.004
.016
0.10
0.40
c
Lead Thickness
Lead Width
.004
.006
.007
.012
0.10
0.15
0.18
0.30
B
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (EIAJ) Standard: SC-70
Revised 07-19-05
Drawing No. C04-061
© 2006 Microchip Technology Inc.
DS21696E-page 21
MCP6541/1R/1U/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
B
p1
D
n
1
α
c
A
A2
φ
L
A1
β
Units
INCHES
NOM
*
MILLIMETERS
NOM
5
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
5
.038
0.95
p1
A
Outside lead pitch (basic)
Overall Height
.075
.046
.043
.003
.110
.064
.116
.018
1.90
.035
.057
0.90
1.18
1.45
1.30
0.15
3.00
1.75
3.10
0.55
Molded Package Thickness
Standoff
A2
A1
E
.035
.000
.102
.059
.110
.014
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
1.10
0.08
Overall Width
2.80
Molded Package Width
Overall Length
E1
D
1.63
2.95
Foot Length
L
f
0.45
Foot Angle
0
5
0
5
10
c
Lead Thickness
Lead Width
.004
.014
.006
.017
.008
.020
10
0.09
0.35
0.15
0.43
0.20
0.50
B
a
Mold Draft Angle Top
Mold Draft Angle Bottom
0
0
5
5
0
5
5
10
10
b
10
0
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-091
DS21696E-page 22
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
8
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.155
.130
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2006 Microchip Technology Inc.
DS21696E-page 23
MCP6541/1R/1U/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
8
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.050
1.27
Overall Height
A
.053
.061
.056
.007
.237
.154
.193
.015
.025
4
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21696E-page 24
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
2
b
1
e
c
ϕ
A2
A
L1
L
A1
Units
MILLIMETERS
Dimension Limits
NOM
8
MAX
MIN
Number of Pins
Pitch
N
e
0.65 BSC
—
—
Overall Height
A
1.10
0.95
0.15
0.75
0.00
0.85
Molded Package Thickness
Standoff
A2
A1
E
—
4.90 BSC
3.00 BSC
3.00 BSC
0.60
Overall Width
Molded Package Width
Overall Length
Foot Length
E1
D
0.40
L
0.80
0.95 REF
—
Footprint
L1
0°
Foot Angle
ϕ
8°
0.08
0.22
—
Lead Thickness
Lead Width
c
0.23
0.40
—
b
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
© 2006 Microchip Technology Inc.
DS21696E-page 25
MCP6541/1R/1U/2/3/4
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
14
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.155
.130
.170
3.56
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.145
3.68
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS21696E-page 26
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
14
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
A2
A1
E
.052
.004
.228
.150
.337
.010
.016
0
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
Standoff
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
Revised 7-20-06
© 2006 Microchip Technology Inc.
DS21696E-page 27
MCP6541/1R/1U/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
A1
A2
Units
INCHES
NOM
MILLIMETERS
NOM
14
*
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
14
.026 BSC
.041
0.65 BSC
1.05
Overall Height
A
A2
A1
E
.039
.033
.002
.246
.169
.193
.020
.043
1.00
1.10
Molded Package Thickness
Standoff
.035
.004
.251
.173
.197
.024
.037
.006
.256
.177
.201
.028
0.85
0.05
6.25
4.30
4.90
0.50
0.90
0.95
0.15
6.50
4.50
5.10
0.70
0.10
Overall Width
6.38
Molded Package Width
Molded Package Length
Foot Length
E1
D
4.40
5.00
L
0.60
φ
Foot Angle
0°
4°
8°
0°
4°
0.15
0.25
12° REF
12° REF
8°
c
Lead Thickness
.004
.007
.006
.010
.008
.012
0.09
0.19
0.20
0.30
Lead Width
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
12° REF
12° REF
β
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
Revised: 08-17-05
DS21696E-page 28
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
APPENDIX A: REVISION HISTORY
Revision E (September 2006)
The following is the list of modifications:
1. Added MCP6541U pinout for the SOT-23-5
package.
2. Clarified Absolute Maximum Analog Input
Voltage and Current Specifications.
3. Added applications writeups on unused
comparators.
4. Added disclaimer to package outline drawings.
Revision D (May 2006)
The following is the list of modifications:
1. Added E-temp parts.
2. Changed VHYST temperature specification to
linear and quadratic temperature coefficients.
3. Changed specifications and plots for E-Temp.
4. Added Section 3.0 Pin Descriptions
5. Corrected package marking (See Section 5.1
“Package Marking Information”)
6. Added Appendix A: Revision History.
Revision C (September 2003)
Revision B (November 2002)
Revision A (March 2002)
• Original Release of this Document.
© 2006 Microchip Technology Inc.
DS21696E-page 29
MCP6541/1R/1U/2/3/4
NOTES:
DS21696E-page 30
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
-X
/XX
a)
b)
MCP6541T-I/LT: Tape and Reel,
Temperature Package
Range
Industrial Temperature,
5LD SC-70.
MCP6541T-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT-23.
Device:
MCP6541:
MCP6541T:
Single Comparator
Single Comparator (Tape and Reel)
(SC-70, SOT-23, SOIC, MSOP)
c)
d)
MCP6541-E/P:
Extended Temperature,
8LD PDIP.
MCP6541RT: Single Comparator (Rotated - Tape and
Reel) (SOT-23 only)
MCP6541UT: Single Comparator (Tape and Reel)
(SOT-23-5 is E-Temp only)
MCP6541RT-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT23.
MCP6541-E/SN: Extended Temperature,
8LD SOIC.
MCP6542:
MCP6542T:
Dual Comparator
Dual Comparator
e)
f)
(Tape and Reel for SOIC and MSOP)
Single Comparator with CS
Single Comparator with CS
(Tape and Reel for SOIC and MSOP)
Quad Comparator
MCP6543:
MCP6543T:
MCP6541UT-E/OT:Tape and Reel,
Extended Temperature,
MCP6544:
MCP6544T:
5LD SOT23.
Quad Comparator
(Tape and Reel for SOIC and TSSOP)
a)
b)
MCP6542-I/MS: Industrial Temperature,
8LD MSOP.
Temperature Range:
Package:
I
=
=
-40°C to +85°C
-40°C to +125°C
MCP6542T-I/MS: Tape and Reel,
Industrial Temperature,
8LD MSOP.
E *
* SC-70-5 E-Temp parts not available at this release of the
data sheet.
c)
d)
MCP6542-I/P:
Industrial Temperature,
8LD PDIP.
LT
=
=
=
=
=
=
=
Plastic Package (SC-70), 5-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
Plastic MSOP, 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead (MCP6544)
Plastic TSSOP (4.4mm Body), 14-lead (MCP6544)
OT
MS
P
SN
SL
ST
MCP6542-E/SN: Extended Temperature,
8LD SOIC.
a)
b)
MCP6543-I/SN: Industrial Temperature,
8LD SOIC.
MCP6543T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC.
c)
d)
MCP6543-I/P:
Industrial Temperature,
8LD PDIP.
MCP6543-E/SN: Extended Temperature,
8LD SOIC.
a)
b)
MCP6544T-I/SL: Tape and Reel,
Industrial Temperature,
14LD SOIC.
MCP6544T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC.
c)
d)
MCP6544-I/P:
Industrial Temperature,
14LD PDIP.
MCP6544T-E/ST: Tape and Reel,
Extended Temperature,
14LD TSSOP.
© 2006 Microchip Technology Inc.
DS21696E-page 31
MCP6541/1R/1U/2/3/4
NOTES:
DS21696E-page 32
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21696E-page 33
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08/29/06
DS21696E-page 34
© 2006 Microchip Technology Inc.
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