概述
规格参数
数据手册MCP6548-E/LT 概述
Open-Drain Output Sub-Microamp Comparators 漏极开路输出亚微安比较 比较器
MCP6548-E/LT 规格参数
| 生命周期： | Active | 包装说明： | , |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.67 |
| Is Samacsys： | N | 放大器类型： | COMPARATOR |
| JESD-609代码： | e3 | 湿度敏感等级： | 3 |
| 子类别： | Comparator | 端子面层： | Matte Tin (Sn) |
| Base Number Matches： | 1 |
MCP6548-E/LT 数据手册
通过下载MCP6548-E/LT数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载MCP6546/6R/6U/7/8/9
Open-Drain Output Sub-Microamp Comparators
Features
Description
• Low Quiescent Current: 600 nA/comparator (typ.)
• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
• Open-Drain Output: VOUT ≤ 10V
• Propagation Delay: 4 µs (typ., 100 mV Overdrive)
• Wide Supply Voltage Range: 1.6V to 5.5V
• Single available in SOT-23-5, SC-70-5 * packages
• Available in Single, Dual and Quad
• Chip Select (CS) with MCP6548
• Low Switching Current
The Microchip Technology Inc. MCP6546/7/8/9 family
of comparators is offered in single (MCP6546,
MCP6546R, MCP6546U), single with chip select
(MCP6548), dual (MCP6547) and quad (MCP6549)
configurations. The outputs are open-drain and are
capable of driving heavy DC or capacitive loads.
These comparators are optimized for low power,
single-supply application with greater than rail-to-rail
input operation. The output limits supply current surges
and dynamic power consumption while switching. The
open-drain output of the MCP6546/7/8/9 family can be
used as a level-shifter for up to 10V using a pull-up
resistor. It can also be used as a wired-OR logic. The
internal Input hysteresis eliminates output switching
due to internal noise voltage, reducing current draw.
These comparators operate with a single-supply
voltage as low as 1.6V and draw a quiescent current of
less than 1 µA/comparator.
• Internal Hysteresis: 3.3 mV (typ.)
• Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Typical Applications
• Laptop Computers
• Mobile Phones
The related MCP6541/2/3/4 family of comparators from
Microchip has a push-pull output that supports rail-to-
rail output swing and interfaces with CMOS/TTL logic.
• Metering Systems
• Hand-held Electronics
• RC Timers
* SC-70-5 E-Temp parts not avaliable at this release of
the data sheet.
• Alarm and Monitoring Circuits
• Windowed Comparators
• Multi-vibrators
MCP6546U SOT-23-5 is E-Temp only.
Related Devices
• CMOS/TTL-Compatible Output: MCP6541/2/3/4
Package Types
MCP6549
MCP6547
PDIP, SOIC, TSSOP
PDIP, SOIC, MSOP
MCP6546
MCP6546R
PDIP, SOIC, MSOP
SOT-23-5
OUTA 1
14 OUTD
VDD
OUTA 1
1
VSS
8
7
6
5
NC
8
7
6
5
OUT
VDD
NC
1
2
3
5
VINA– 2 - + + 13 VIND
–
+
-
+
OUTB
VINA–
+
-
2
3
4
VIN– 2
VIN+ 3
VSS
4
-
+
VDD
OUT
NC
-
VINA+ 3
12 VIND
VINA
+
VINB
VINB
–
+
-
VIN+
4 VIN–
VSS
VDD
4
V
11
SS
VINB+ 5
VINB– 6
10 VINC
-
9 VINC
+
MCP6546
SOT-23-5, SC-70-5
MCP6546U
MCP6548
PDIP, SOIC, MSOP
-
+ +
–
SOT-23-5
OUTB
8
OUTC
7
NC 1
VIN– 2
VIN+ 3
8
7
CS
VDD
VDD
VDD
OUT
VIN–
VSS
1
2
3
1
2
3
5
5
4
-
+
-
+
VSS
-
6 OUT
5 NC
VIN+
4 VIN– VIN+
OUT
VSS
4
© 2006 Microchip Technology Inc.
DS21714E-page 1
MCP6546/6R/6U/7/8/9
† Notice: Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at those or any other conditions above those indicated
in the operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
Open-Drain output............................................... VSS + 10.5V
Analog Input (VIN+, VIN-)††............. VSS - 1.0V to VDD + 1.0V
All other inputs and outputs ........... VSS – 0.3V to VDD + 0.3V
†† See Section 4.1.2 “Input Voltage and Current
Limits”
Difference Input voltage ...................................... |VDD – VSS
|
Output Short-Circuit Current .................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD protection on all pins:
(HBM;MM) .....................................2 kV;200V (MCP6546U)
(HBM;MM) ................................ 4 kV; 200V (all other parts)
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS
PU = 2.74 kΩ to VPU = VDD (Refer to Figure 1-3).
,
R
Parameters
Sym
Min
Typ
Max
Units
Conditions
Power Supply
Supply Voltage
VDD
IQ
1.6
0.3
—
5.5
1
V
VPU ≥ VDD
Quiescent Current
(per comparator)
0.6
µA IOUT = 0
Input
Input Voltage Range
VCMR
CMRR
CMRR
CMRR
PSRR
VOS
VSS − 0.3
55
—
70
VDD + 0.3
—
V
Common Mode Rejection Ratio
Common Mode Rejection Ratio
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Input Offset Voltage
dB VDD = 5V, VCM = -0.3V to 5.3V
dB VDD = 5V, VCM = 2.5V to 5.3V
dB VDD = 5V, VCM = -0.3V to 2.5V
dB VCM = VSS
50
65
—
55
70
—
63
80
—
-7.0
—
±1.5
±3
+7.0
—
mV VCM = VSS (Note 1)
Drift with Temperature
ΔVOS/ΔTA
VHYST
TC1
µV/°C TA = -40°C to +125°C, VCM = VSS
mV VCM = VSS (Note 1)
Input Hysteresis Voltage
Linear Temp. Co.
1.5
—
3.3
6.5
—
6.7
µV/°C TA = -40°C to +125°C, VCM = VSS (Note 2)
µV/°C2 TA = -40°C to +125°C, VCM = VSS (Note 2)
pA VCM = VSS
Quadratic Temp. Co.
TC2
—
-0.035
1
—
Input Bias Current
IB
—
—
At Temperature (I-Temp parts)
At Temperature (E-Temp parts)
Input Offset Current
IB
—
25
100
5000
—
pA TA = +85°C, VCM = VSS (Note 3)
pA TA = +125°C, VCM = VSS (Note 3)
pA VCM = VSS
IB
—
1200
±1
IOS
—
Common Mode Input Impedance
Differential Input Impedance
ZCM
—
1013||4
1013||2
—
Ω||pF
ZDIFF
—
—
Ω||pF
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
2:
V
HYST at differential temperatures is estimated using: VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.
3: Input bias current at temperature is not tested for the SC-70-5 package
4: Do not short the output above VSS + 10V. Limit the output current to Absolute Maximum Rating of 30 mA. The minimum
V
PU test limit was VDD before Dec. 2004 (week code 52).
DS21714E-page 2
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS
PU = 2.74 kΩ to VPU = VDD (Refer to Figure 1-3).
,
R
Parameters
Sym
Min
Typ
Max
Units
Conditions
Open-Drain Output
Output Pull-Up Voltage
High-Level Output Current
Low-Level Output Voltage
Short-Circuit Current
VPU
IOH
1.6
-100
VSS
—
—
—
10
V
(Note 4)
—
nA VDD = 1.6V to 5.5V, VPU = 10V (Note 4)
IOUT = 2 mA, VPU = VDD = 5V
VOL
ISC
—
VSS + 0.2
V
±1.5
30
8
—
—
—
mA VPU = VDD = 1.6V (Note 4)
mA VPU = VDD = 5.5V (Note 4)
pF
ISC
–
Output Pin Capacitance
COUT
—
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
2:
V
HYST at differential temperatures is estimated using: VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.
3: Input bias current at temperature is not tested for the SC-70-5 package
4: Do not short the output above VSS + 10V. Limit the output current to Absolute Maximum Rating of 30 mA. The minimum
V
PU test limit was VDD before Dec. 2004 (week code 52).
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,
Step = 200 mV, Overdrive = 100 mV, RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF (Refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Fall Time
tF
—
—
—
—
—
—
—
0.7
4.0
—
8.0
8.0
—
µs
µs
µs
µs
(Note 1)
Propagation Delay (High-to-Low)
Propagation Delay (Low-to-High)
Propagation Delay Skew
tPHL
tPLH
tPDS
fMAX
fMAX
Eni
3.0
(Note 1)
-1.0
225
165
200
(Notes 1 and 2)
Maximum Toggle Frequency
—
kHz VDD = 1.6V
kHz VDD = 5.5V
—
Input Noise Voltage
—
µVP-P 10 Hz to 100 kHz
Note 1: tR and tPLH depend on the load (RL and CL); these specifications are valid for the indicated load only.
2: Propagation Delay Skew is defined as: tPDS = tPLH - tPHL
.
MCP6548 CHIP SELECT (CS) CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS
,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF (Refer to Figures 1-1 and 1-3).
Parameters
Sym
Min
Typ
Max Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
VIL
VSS
—
—
5
0.2 VDD
—
V
CS Input Current, Low
ICSL
pA
CS = VSS
CS High Specifications
CS Logic Threshold, High
VIH
ICSH
IDD
0.8 VDD
—
1
VDD
—
V
CS Input Current, High
—
—
—
—
pA
pA
pA
pA
CS = VDD
CS = VDD
CS = VDD
CS Input High, VDD Current
CS Input High, GND Current
Comparator Output Leakage
CS Dynamic Specifications
18
-20
1
—
ISS
—
IO(LEAK)
—
VOUT = VSS+10V, CS = V
DD
CS Low to Comparator Output Low
Turn-on Time
tON
tOFF
—
—
—
2
50
—
—
ms
µs
V
CS = 0.2VDD to VOUT = VDD/2,
IN– = VDD
CS = 0.8VDD to VOUT = VDD/2,
IN– = VDD
VDD = 5V
V
CS High to Comparator Output
High Z Turn-off Time
10
0.6
V
CS Hysteresis
VCS_HYST
© 2006 Microchip Technology Inc.
DS21714E-page 3
MCP6546/6R/6U/7/8/9
VIL
tON
VIH
tOFF
High-Z
CS
V –
IN
100 mV
V + = V /2
t
PHL
100 mV
IN
DD
VOUT
High-Z
t
PLH
V
OH
V
ISS
OUT
-20 pA (typ.) -0.6 µA (typ.)
-20 pA (typ.)
1 pA (typ.)
V
V
OL
OL
ICS
1 pA (typ.)
5 pA (typ.)
FIGURE 1-2:
Propagation Delay Timing
Diagram.
FIGURE 1-1:
Timing Diagram for the CS
pin on the MCP6548.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SC-70
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
TA
-40
-40
-65
—
—
—
+85
+125
+150
°C
°C Note
°C
θJA
θJA
θJA
θJA
θJA
θJA
θJA
θJA
—
—
—
—
—
—
—
—
331
256
85
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
163
206
70
120
100
Note:
The MCP6546/7/8/9 I-temp family operates over this extended temperature range, but with reduced
performance. In any case, the Junction Temperature (TJ) must not exceed the absolute maximum
specification of +150°C.
1.1
Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
VDD
VPU = VDD
200 kΩ
200 kΩ
RPU
(2 mA)/ VDD
=
MCP654X
VOUT
36 pF
100 kΩ
VSS = 0V
VIN = VSS
FIGURE 1-3:
AC and DC Test Circuit for
the Open-Drain Output Comparators.
DS21714E-page 4
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
14%
18%
16%
14%
12%
10%
8%
1200 Samples
VCM = VSS
1200 Samples
CM = VSS
12%
10%
8%
V
6%
6%
4%
4%
2%
2%
0%
0%
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
Input Hysteresis Voltage (mV)
Input Offset Voltage (mV)
FIGURE 2-1:
Input Offset Voltage at
FIGURE 2-4:
Input Hysteresis Voltage at
V
= V
.
V
= V
.
CM
SS
CM
SS
25%
20%
15%
10%
5%
16%
14%
12%
10%
8%
596 Samples
VCM = VSS
TA = -40°C to +125°C
1200 Samples
VCM = VSS
TA = -40°C to +125°C
VDD = 5.5V
VDD = 1.6V
6%
4%
2%
0%
0%
Input Hysteresis Voltage –
Linear Temp. Co.; TC1 (µV/°C)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Input Offset Voltage Drift at
FIGURE 2-5:
Input Hysteresis Voltage
V
= V
.
Linear Temp. Co. (TC ) at V
= V
.
CM
SS
1
CM
SS
20%
7
6
596 Samples
18%
VDD = 5.5V
VCM = VSS
16%
14%
12%
10%
8%
TA = -40°C to +125°C
VOUT
5
VDD = 5.5V
4
3
VDD = 1.6V
6%
4%
2%
0%
2
1
VIN–
0
-1
Input Hysteresis Voltage –
Quadratic Temp. Co.; TC2 (µV/°C2)
0
1
2
3
4
5
6
7
8
9
10
Time (1 ms/div)
FIGURE 2-3:
The MCP6546/6R/6U/7/8/9
FIGURE 2-6:
Input Hysteresis Voltage
comparators show no phase reversal.
Quadratic Temp. Co. (TC ) at V
= V
.
2
CM
SS
© 2006 Microchip Technology Inc.
DS21714E-page 5
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
1.0
6.5
VCM = VSS
VCM = VSS
0.8
0.6
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
0.4
VDD = 1.6V
VDD = 5.5V
0.2
0.0
VDD = 1.6V
VDD = 5.5V
-0.2
-0.4
-0.6
-0.8
-1.0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
Input Hysteresis Voltage vs.
Ambient Temperature at V
= V
.
Ambient Temperature at V
= V
.
CM
SS
CM
SS
2.0
6.5
6.0
VDD = 1.6V
VDD = 1.6V
TA = +125°C
A = +85°C
1.5
5.5
5.0
4.5
4.0
3.5
3.0
2.5
T
1.0
0.5
TA = +125°C
0.0
T
T
T
A = +85°C
A = +25°C
A = -40°C
-0.5
TA = +125°C
-1.0
TA = +25°C
A = -40°C
-1.5
-2.0
T
2.0
1.5
TA = +125°C
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
Input Hysteresis Voltage vs.
Common Mode Input Voltage at V = 1.6V.
Common Mode Input Voltage at V = 1.6V.
DD
DD
2.0
6.5
VDD = 5.5V
1.5
VDD = 5.5V
TA = +125°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
T
T
T
A = +85°C
A = +25°C
A = -40°C
TA = -40°C
A = +25°C
1.0
T
0.5
0.0
-0.5
-1.0
-1.5
-2.0
TA = +85°C
A = +125°C
T
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Input Hysteresis Voltage vs.
Common Mode Input Voltage at V = 5.5V.
Common Mode Input Voltage at V = 5.5V.
DD
DD
DS21714E-page 6
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
10n
10000
90
85
80
75
70
65
60
55
VDD = 5.5V
Input Referred
IB, TA = +125°C
IB, TA = +85°C
1n
1000
100p
100
PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V
CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V
10p
10
IOS, TA = +125°C
IOS, TA = +85°C
11p
100.01f
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-13:
CMRR,PSRR vs. Ambient
FIGURE 2-16:
Input Bias Current, Input
Temperature.
Offset Current vs. Common Mode Input Voltage.
1000
0.7
0.6
0.5
0.4
VDD = 5.5V
CM = VDD
V
100
10
1
IB
TA = +125°C
0.3
0.2
0.1
0.0
| IOS
|
T
T
A = +85°C
A = +25°C
T
A = -40°C
0.1
55
65
75
85
95
105 115 125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-14:
Input Bias Current, Input
FIGURE 2-17:
Quiescent Current vs.
Offset Current vs. Ambient Temperature.
Power Supply Voltage.
0.8
0.8
IQ does not include pull-up resistor current
IQ does not include pull-up resistor current
0.7
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VDD = 1.6V
VDD = 5.5V
0.6
0.5
0.4
0.3
0.2
Sweep VIN+, VIN– = VDD/2
Sweep VIN+, VIN– = VDD/2
0.1
Sweep VIN–, VIN+ = VDD/2
Sweep VIN–, VIN+ = VDD/2
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Common Mode Input Voltage (V)
FIGURE 2-15:
Quiescent Current vs.
FIGURE 2-18:
Quiescent Current vs.
Common Mode Input Voltage at V = 1.6V.
Common Mode Input Voltage at V = 5.5V.
DD
DD
© 2006 Microchip Technology Inc.
DS21714E-page 7
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
10
10
IDD spike near VPU = 1.3V
VDD = 5.6V VPU = 1.6V to 10.5V
VDD = 4.6V
VDD = 2.1V
VDD = 2.6V
VDD = 3.6V
VDD = 4.6V
VDD = 5.6V
V
DD = 3.6V
VDD = 2.6V
1
1
VDD = 1.6V
VDD = 2.1V
VDD = 1.6V
0.1
-4 -3 -2 -1
Pull-up to Supply Voltage Difference,
PU – VDD (V)
0
1
2
3
4
5
6
7
8
9
0.1
0
1
2
3
4
5
6
7
8
9
10 11
Pull-Up Voltage, VPU (V)
V
FIGURE 2-19:
Supply Current vs. Pull-Up
FIGURE 2-22:
Supply Current vs. Pull-Up
Voltage.
to Supply Voltage Difference.
35
10
TA = -40°C
100 mV Overdrive
VCM = VDD/2
IDD does not include
pull-up resistor current
30
25
20
15
10
5
TA = +25°C
TA = +85°C
TA = +125°C
1
VDD = 5.5V
DD = 1.6V
V
0
0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
0.1
1
10
100
Toggle Frequency (kHz)
FIGURE 2-20:
Supply Current vs. Toggle
FIGURE 2-23:
Output Short Circuit Current
Frequency.
Magnitude vs. Power Supply Voltage.
1.0
0.8
VDD = 5.5V
0.9
VDD = 1.6V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VOL–VSS:
0.8
0.7
0.6
T
A = +125°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
VOL – VSS
:
0.5
0.4
0.3
0.2
0.1
0.0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
5
10
15
20
25
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Output Current (mA)
Output Current (mA)
FIGURE 2-21:
Output Voltage Headroom
FIGURE 2-24:
Output Voltage Headroom
vs. Output Current at V = 1.6V.
vs. Output Current at V = 5.5V.
DD
DD
DS21714E-page 8
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
65%
60%
55%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
408 Samples
100 mV Overdrive
VCM = VDD/2
408 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 1.6V
VDD = 5.5V
VDD = 1.6V
VDD = 5.5V
0%
0%
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
High-to-Low Propagation Delay (µs)
Low-to-High Propagation Delay (µs)
FIGURE 2-25:
High-to-Low Propagation
FIGURE 2-28:
Low-to-High Propagation
Delay.
Delay.
50%
45%
8
100 mV Overdrive
VCM = VDD/2
408 Samples
100 mV Overdrive
7
6
5
4
3
2
1
0
VDD = 5.5V
40%
35%
30%
25%
20%
15%
10%
5%
VCM = VDD/2
tPHL
VDD = 5.5V
VDD = 1.6V
VDD = 1.6V
tPLH
0%
-50
-25
0
25
50
75
100
125
Propagation Delay Skew (µs)
Ambient Temperature (°C)
FIGURE 2-26:
Propagation Delay Skew.
FIGURE 2-29:
Propagation Delay vs.
Ambient Temperature.
100
14
VCM = VDD/2
VCM = VDD/2
13
12
11
10
9
tPHL
8
7
10
VDD = 5.5V
6
10 mV Overdrive
tPHL
5
4
3
2
tPLH
VDD = 1.6V
1
tPLH
1000
100 mV Overdrive
0
1
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1
10
100
Power Supply Voltage (V)
Input Overdrive (mV)
FIGURE 2-27:
Propagation Delay vs.
FIGURE 2-30:
Propagation Delay vs. Input
Power Supply Voltage.
Overdrive.
© 2006 Microchip Technology Inc.
DS21714E-page 9
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
VDD = 1.6V
100 mV Overdrive
VDD = 5.5V
100 mV Overdrive
tPHL
tPLH
tPHL
tPLH
0.8
0.0
0.2
0.4
0.6
1.0
1.2
1.4
1.6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-31:
Propagation Delay vs.
FIGURE 2-34:
Propagation Delay vs.
Common Mode Input Voltage at V = 1.6V.
Common Mode Input Voltage at V = 5.5V.
DD
DD
8
200
VIN– = 100 mV Overdrive
100 mV Overdrive
VCM = VDD/2
180
160
140
120
100
80
tPLH
7
VCM = VDD/2
VIN+ = VCM
tPLH
VDD = 5.5V
6
5
4
3
2
1
0
VDD = 5.5V
tPHL
60
VDD = 1.6V
40
tPHL
VDD = 1.6V
20
0
0
10 20 30 40 50 60 70 80 90
Load Capacitance (nF)
0
10 20 30 40 50 60 70 80 90 100
Pull-up Resistor, RPU (k:)
FIGURE 2-32:
Propagation Delay vs.
FIGURE 2-35:
Propagation Delay vs. Load
Pull-up Resistor.
Capacitance.
10n
1.E+04
8
VIN– = 100 mV Overdrive
VCM = VDD/2
IN+ = VCM
TA = +125°C
TA = +85°C
7
6
5
4
3
2
1
0
1n
1.E+03
V
tPHL
100p
1.E+02
VDD = 5.5V
CS = VDD
VIN+ = VDD/2
IN– = VSS
1.E+01
10p
V
1.E+00
1p
TA = +25°C
VDD = 1.6V
tPLH
1.E-01
100f
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
3
4
5
6
7
8
9
10 11
Pull-up Voltage (V)
Output Voltage (V)
FIGURE 2-33:
Propagation Delay vs.
FIGURE 2-36:
Output Leakage Current
Pull-up Voltage.
(CS = V ) vs. Output Voltage (MCP6548 only).
DD
DS21714E-page 10
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF.
1.E-10m3
1.E10-004µ
1.E1-005µ
1.E-10m3
Comparator
Turns On
Comparator
Shuts Off
Comparator
Turns On
Comparator
Shuts Off
1.E-04
100µ
1.E1-005µ
1.E-016µ
1.1E0-07n
1µ
1.E-06
CS Hysteresis
CS
Hysteresis
100n
1.E-07
10n
1.E-08
1.E- 8
10n
CS
High-to-Low
CS
CS
CS
1n
1.E-09
1.E-09
1n
Low-to-High
High-to-Low
Low-to-High
100p
1.E-10
1.E-10
100p
VDD = 1.6V
VDD = 5.5V
10p
1.E-11
1.E1-101p
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Chip Select (CS) Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select (CS) Voltage (V)
FIGURE 2-37:
Supply Current (shoot
FIGURE 2-40:
Supply Current (shoot
through current) vs. Chip Select (CS) Voltage at
through current) vs. Chip Select (CS) Voltage at
V
= 1.6V (MCP6548 only).
V
= 5.5V (MCP6548 only).
DD
DD
20
1.6
6
VOUT
CS
3
0.0
VOUT
0
CS
140
120
VDD = 1.6V
15
Start-up IDD
100
80
60
40
20
0
VDD = 5.5V
Start-up
IDD
10
Charging output
capacitance
Charging output
capacitance
5
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Time (0.5 ms/div)
Time (1 ms/div)
FIGURE 2-38:
Supply Current (charging
FIGURE 2-41:
Supply Current (charging
current) vs. Chip Select (CS) pulse at V = 1.6V
current) vs. Chip Select (CS) pulse at V = 5.5V
DD
DD
(MCP6548 only).
(MCP6548 only).
6.0
1.E-02
10m
1.E-03
1m
1.E-04
100µ
1.E1-005µ
1.E-016µ
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
VDD = 5.5V
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
VOUT
CS
+125°C
+85°C
+25°C
-40°C
10p
1.E-11
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
0
1
2
3
4
5
6
7
8
9
10
Time (ms)
FIGURE 2-39:
Response (MCP6548 only).
Chip Select (CS) Step
FIGURE 2-42:
Voltage.
Input Bias Current vs. Input
© 2006 Microchip Technology Inc.
DS21714E-page 11
MCP6546/6R/6U/7/8/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6546
(PDIP,
SOIC,
MCP6546
(SOT-23-5,
SC-70-5)
Symbol
Description
MSOP)
6
2
1
1
4
1
2
6
2
1
2
OUT, OUTA Digital Output (comparator A)
VIN–, VINA– Inverting Input (comparator A)
VIN+, VINA+ Non-inverting Input (comparator A)
4
4
1
3
3
3
3
3
3
3
7
5
2
5
8
7
4
VDD
Positive Power Supply
—
—
—
—
—
—
4
—
—
—
—
—
—
2
—
—
—
—
—
—
5
—
—
—
—
—
—
2
5
—
—
—
—
—
—
4
5
VINB
+
Non-inverting Input (comparator B)
Inverting Input (comparator B)
Digital Output (comparator B)
Digital Output (comparator C)
Inverting Input (comparator C)
Non-inverting Input (comparator C)
Negative Power Supply
6
6
VINB
–
7
7
OUTB
OUTC
—
—
—
4
8
9
VINC
–
+
10
11
12
13
14
—
—
VINC
VSS
—
—
—
—
1, 5, 8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
VIND
VIND
+
Non-inverting Input (comparator D)
Inverting Input (comparator D)
Digital Output (comparator D)
Chip Select
–
OUTD
CS
1, 5
NC
No Internal Connection
3.1
Analog Inputs
3.4
Power Supply (VSS and VDD)
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
The positive power supply pin (VDD) is 1.6V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD, except the output pins which
3.2
CS Digital Input
can be as high as 10V above VSS
.
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These can share a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
3.3
Digital Outputs
The comparator outputs are CMOS, open-drain digital
outputs. They are designed to make level shifting and
wired-OR easy to implement.
DS21714E-page 12
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
4.0
APPLICATIONS INFORMATION
VDD
The MCP6546/7/8/9 family of push-pull output
comparators are fabricated on Microchip’s state-of-the-
art CMOS process. They are suitable for a wide range
of applications requiring very low power consumption.
D1
+
V1
R1
VOUT
MCP6G0X
–
4.1
Comparator Inputs
D2
4.1.1
PHASE REVERSAL
V2
The MCP6546/6R/6U/7/8/9 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
R2
R3
VSS – (minimum expected V1)
2 mA
R1 ≥
R2 ≥
VSS – (minimum expected V2)
2 mA
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
FIGURE 4-2:
Protecting the Analog Inputs.
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to pro-
tect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-42. Applications that are
high impedance may need to limit the useable voltage
range.
Bond
VDD
Pad
4.1.3
NORMAL OPERATION
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages.
With this topology, the input voltage is 0.3V above VDD
and 0.3V below VSS. The input offset voltage is
measured at both VSS - 0.3V and VDD + 0.3V to ensure
proper operation.
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
Bond
Pad
VSS
The MCP6546/6R/6U/7/8/9 family has internally-set
hysteresis that is small enough to maintain input offset
accuracy (<7 mV), and large enough to eliminate
output chattering caused by the comparator’s own
input noise voltage (200 µVP-P). Figure 4-3 illustrates
this capability.
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pin. Diodes D1 and D2 prevent the input
pin (VIN+ and VIN–) from going too far above VDD
.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
© 2006 Microchip Technology Inc.
DS21714E-page 13
MCP6546/6R/6U/7/8/9
4.4.1
INVERTING CIRCUIT
25
20
15
10
5
Figure 4-4 shows an inverting circuit for a single-supply
application using three resistors, besides the pull-up
resistor. The resulting hysteresis diagram is shown in
Figure 4-5.
VDD = 5.0V
VIN
–
5
VOUT
4
3
0
2
-5
VDD
VPU
RPU
Hysteresis
1
-10
-15
-20
-25
-30
0
I
PU
VIN
VOUT
MCP654X
VDD
R2
I
Time (100 ms/div)
OL
I
RF
FIGURE 4-3:
comparators’ internal hysteresis eliminates
output chatter caused by input noise voltage.
The MCP6546/7/8/9
RF
R3
4.2
Open-Drain Output
The open-drain output is designed to make level-
shifting and wired-OR logic easy to implement. The
output can go as high as 10V for 9V battery-powered
applications. The output stage minimizes switching cur-
rent (shoot-through current from supply-to-supply)
when the output changes state. See Figures 2-15, 2-18
and 2-37 through 2-41, for more information.
FIGURE 4-4:
hysteresis.
Inverting circuit with
VOUT
VPU
VOH
4.3
MCP6548 Chip Select (CS)
Low-to-High
High-to-Low
The MCP6548 is a single comparator with a Chip
Select (CS) pin. When CS is pulled high, the total
current consumption drops to 20 pA (typ.). 1 pA (typ.)
flows through the CS pin, 1 pA (typ.) flows through the
output pin and 18 pA (typ.) flows through the VDD pin,
as shown in Figure 1-1. When this happens, the
comparator output is put into a high-impedance state.
By pulling CS low, the comparator is enabled. If the CS
pin is left floating, the comparator will not operate
properly. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
VIN
VOL
VSS
VSS
VTLH VTHL
VDD
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
FIGURE 4-5:
inverting circuit.
Hysteresis diagram for the
In order to determine the trip voltages (VTHL and VTLH
)
The internal CS circuitry is designed to minimize
glitches when cycling the CS pin. This helps conserve
power, which is especially important in battery-powered
applications.
for the circuit shown in Figure 4-4, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-6.
VPU
4.4
Externally Set Hysteresis
RPU
VOUT
Greater flexibility in selecting hysteresis, or input trip
points, is achieved by using external resistors.
-
MCP654X
Input offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points. Hysteresis reduces output
chattering when one input is slowly moving past the
other, thus reducing dynamic supply current. It also
helps in systems where it is best not to cycle between
states too frequently (e.g., air conditioner thermostatic
control).
+
V23
R23
RF
FIGURE 4-6:
Thevenin Equivalent Circuit.
DS21714E-page 14
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
EQUATION 4-1:
4.6
Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-27).
The supply current increases with increasing toggle
frequency (Figure 2-30), especially with higher
capacitive loads.
R2R3
R23 = ------------------
R2 + R3
R3
------------------
V23
=
× VDD
R2 + R3
4.7
Battery Life
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
In order to maximize battery life in portable
applications, use large resistors and small capacitive
loads. Avoid toggling the output more than necessary.
Do not use Chip Select (CS) too frequently in order to
conserve power. Capacitive loads will draw additional
power at start-up.
EQUATION 4-2:
R23
RF + RPU
---------------------------------------
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎝
⎞
----------------------------------------
VTHL = VPU
+ V
+ V
23
23
⎠
R23 + RF + RPU
R
23 + R + RPU
F
R23
RF
---------------------
R23 + RF
4.8
PCB Surface Leakage
⎛
⎞
⎟
⎠
⎛
⎝
⎞
⎠
----------------------
VTLH = VOL
⎜
⎝
R
23 + R
F
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low-humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference
would cause 5 pA of current to flow. This is greater
than the MCP6546/6R/6U/7/8/9 family’s bias current at
25°C (1 pA, typ.).
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
Figure 2-21 and Figure 2-24 can be used to determine
typical values for VOL. This voltage is dependent on the
output current IOL as shown in Figure 4-4. This current
can be determined using the equation below:
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
EQUATION 4-3:
IOL = IPU + IRF
VPU – VOL
--------------------------
RPU
V23 – VOL
⎛
⎝
⎞
⎠
⎛
⎝
⎞
⎠
------------------------
IOL
=
+
R
23 + RF
VIN-
VIN+
VSS
VOH can be calculated using the equation below:
EQUATION 4-4:
R
23 + RF
⎛
⎝
⎞
⎠
--------------------------------------
VOH = (VPU – V23) ×
R
23 + RF + RPU
Guard Ring
Example Guard Ring Layout
As explained in Section 4.1 “Comparator Inputs”, it
is important to keep the non-inverting input below
FIGURE 4-7:
VDD+0.3V when VPU > VDD
.
for Inverting Circuit.
4.5
Supply Bypass
1. Inverting Configuration (Figures 4-4 and 4-7):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
b. Connect the inverting pin (VIN–) to the input
pad without touching the guard ring.
© 2006 Microchip Technology Inc.
DS21714E-page 15
MCP6546/6R/6U/7/8/9
4.9
Unused Comparators
4.10 Typical Applications
An unused amplifier in a quad package (MCP6549)
should be configured as shown in Figure 4-8. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-18).
4.10.1
PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041) to gain-up the input signal
before it reaches the comparator. Figure 4-9 shows an
example of this approach.
¼ MCP6549
VDD
VDD
VREF
MCP6041
VPU
VDD
–
+
RPU
VOUT
VIN
R1
R2
VREF
MCP6546
FIGURE 4-9:
Precise Inverting
Comparator.
FIGURE 4-8:
Unused Comparators.
4.10.2
WINDOWED COMPARATOR
Figure 4-10 shows one approach to designing a
windowed comparator. The wired-OR connection
produces a high output (logic 1) when the input voltage
is between VRB and VRT (where VRT > VRB).
VPU
1/2
MCP6547
RPU
VRT
VOUT
VIN
VRB
1/2
MCP6547
FIGURE 4-10:
Windowed Comparator.
DS21714E-page 16
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SC-70 (MCP6546)
Example: (I-temp)
I-Temp
Code
E-Temp
Code
Device
XXNN (Front)
YWW (Back)
AC25(Front)
636 (Back)
MCP6546
ACNN
Note 2
Note 1: I-Temp parts prior to March
2005 are marked “ACN”
2: SC-70-5 E-Temp parts not
available at this release of
the data sheet.
Example: (I-temp)
5-Lead SOT-23 (MCP6546, MCP6546R, MCP6546U)
I-Temp
Code
E-Temp
Code
Device
MCP6546
ACNN
AHNN
—
GWNN
GXNN
AWNN
XXNN
AC25
MCP6546R
MCP6546U
Note: Applies to 5-Lead SOT-23
8-Lead PDIP (300 mil)
Example:
MCP6546
I/P^^256
0636
XXXXXXXX
XXXXXNNN
MCP6546
I/P256
0636
e
3
OR
YYWW
8-Lead SOIC (150 mil)
Example:
MCP6546I
XXXXXXXX
XXXXYYWW
MCP6546
I/SN0636
e
3
SN0636
OR
256
NNN
256
Example:
8-Lead MSOP
XXXXXX
YWWNNN
6546I
636256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS21714E-page 17
MCP6546/6R/6U/7/8/9
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6549)
Example:
MCP6549-I/P
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
0636256
e
3
MCP6549E/P
OR
OR
0636256
MCP6549
I/P^
e
3
0636256
14-Lead SOIC (150 mil) (MCP6549)
Example:
MCP6549ISL
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
0636256
MCP6549
e
3
E/SL^
OR
0636256
Example:
14-Lead TSSOP (MCP6549)
XXXXXXXX
YYWW
MCP6549I
0636
NNN
256
DS21714E-page 18
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
5-Lead Plastic Package (LT) (SC-70)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
D
p
B
n
1
Q1
A2
A
c
A1
L
Units
INCHES
NOM
MILLIMETERS
NOM
*
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
Overall Height
5
5
.026 (BSC)
0.65 (BSC)
A
A2
A1
E
.031
.043
0.80
1.10
Molded Package Thickness
Standoff
.031
.000
.071
.045
.071
.004
.039
.004
.094
.053
.087
.012
0.80
0.00
1.80
1.15
1.80
0.10
1.00
0.10
2.40
1.35
2.20
0.30
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
Top of Molded Pkg to
Lead Shoulder
Q1
.004
.016
0.10
0.40
c
Lead Thickness
Lead Width
.004
.006
.007
.012
0.10
0.15
0.18
0.30
B
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (EIAJ) Standard: SC-70
Revised 07-19-05
Drawing No. C04-061
© 2006 Microchip Technology Inc.
DS21714E-page 19
MCP6546/6R/6U/7/8/9
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
B
p1
D
n
1
α
c
A
φ
A2
A1
β
L
Units
INCHES
NOM
*
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
6
MAX
n
p
Number of Pins
Pitch
6
.038 BSC
.075 BSC
0.95 BSC
1.90 BSC
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
p1
Outside lead pitch
Overall Height
A
A2
A1
E
.035
.035
.000
.102
.046
.043
.003
.110
.064
.116
.018
.057
0.90
1.45
Molded Package Thickness
Standoff
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
1.30
0.15
3.00
1.75
3.10
0.55
Overall Width
Molded Package Width
Overall Length
E1
D
.059
.110
.014
Foot Length
L
φ
Foot Angle
0
5
0
10
c
Lead Thickness
Lead Width
.004
.014
.006
.017
.008
.020
10
0.09
0.35
0.15
0.43
5
0.20
0.50
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
0
5
5
0
0
10
10
10
5
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
Revised 09-12-05
DS21714E-page 20
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
INCHES*
NOM
8
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.155
.130
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2006 Microchip Technology Inc.
DS21714E-page 21
MCP6546/6R/6U/7/8/9
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
8
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.050
1.27
Overall Height
A
.053
.061
.056
.007
.237
.154
.193
.015
.025
4
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21714E-page 22
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
n
1
B
α
c
φ
A2
A
L
F
A1
β
Units
INCHES
NOM
MILLIMETERS
*
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.026 BSC
0.65 BSC
Overall Height
A
A2
A1
E
-
-
.043
-
-
1.10
0.95
0.15
Molded Package Thickness
Standoff
.030
.033
.037
.006
0.75
0.85
.000
-
0.00
-
Overall Width
.193 BSC
4.90 BSC
Molded Package Width
Overall Length
E1
D
.118 BSC
.118 BSC
3.00 BSC
3.00 BSC
Foot Length
L
.016
.024
.037 REF
.031
0.40
0.60
0.95 REF
0.80
Footprint (Reference)
Foot Angle
F
φ
0°
-
8°
0°
-
-
-
-
-
8°
c
Lead Thickness
Lead Width
.003
.009
.006
.012
.009
.016
0.08
0.22
0.23
0.40
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
5°
5°
-
15°
15°
5°
5°
15°
15°
-
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
Revised 07-21-05
JEDEC Equivalent: MO-187
Drawing No. C04-111
© 2006 Microchip Technology Inc.
DS21714E-page 23
MCP6546/6R/6U/7/8/9
14-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
14
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.155
.130
.170
3.56
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.145
3.68
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS21714E-page 24
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
1
B
n
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
14
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.052
.004
.228
.150
.337
.010
.016
0
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
A2
A1
E
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
Standoff
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
© 2006 Microchip Technology Inc.
DS21714E-page 25
MCP6546/6R/6U/7/8/9
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
A1
A2
Units
INCHES
NOM
MILLIMETERS
NOM
14
*
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
14
.026 BSC
.041
0.65 BSC
1.05
Overall Height
A
A2
A1
E
.039
.033
.002
.246
.169
.193
.020
.043
1.00
1.10
Molded Package Thickness
Standoff
.035
.004
.251
.173
.197
.024
.037
.006
.256
.177
.201
.028
0.85
0.05
6.25
4.30
4.90
0.50
0.90
0.95
0.15
6.50
4.50
5.10
0.70
0.10
Overall Width
6.38
Molded Package Width
Molded Package Length
Foot Length
E1
D
4.40
5.00
L
0.60
φ
Foot Angle
0°
4°
8°
0°
4°
0.15
0.25
12° REF
12° REF
8°
c
Lead Thickness
.004
.007
.006
.010
.008
.012
0.09
0.19
0.20
0.30
Lead Width
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
12° REF
12° REF
β
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
Revised: 08-17-05
DS21714E-page 26
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
APPENDIX A: REVISION HISTORY
Revision E (September 2006)
The following is the list of modifications:
1. Added MCP6546U pinout for the SOT-23-5
package.
2. Clarified Absolute Maximum Analog Input
Voltage and Current Specifications.
3. Added applications writeups on unused
comparators.
4. Added disclaimer to package outline drawings.
Revision D (May 2006)
The following is the list of modifications:
1. Added E-temp parts.
2. Changed minimum pull-up voltage specification
(VPU) to 1.6V for parts starting Dec. 2004 (week
code 52); previous parts are specified at a
minimum of VDD
.
3. Changed VHYST temperature specifications to
linear and quadratic temperature coefficients.
4. Changed specifications and plots to include E-
Temp parts.
5. Added Section 3.0 “Pin Descriptions”.
6. Corrected package markings (Section 5.1
“Package Marking Information”).
7. Added Appendix A: “Revision History”.
Revision C (May 2003)
Revision B (December 2002)
Revision A (February 2002)
• Original Release of this Document.
© 2006 Microchip Technology Inc.
DS21714E-page 27
MCP6546/6R/6U/7/8/9
NOTES:
DS21714E-page 28
© 2006 Microchip Technology Inc.
MCP6546/6R/6U/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
–X
/XX
a)
b)
MCP6546T-I/LT: Tape and Reel,
Temperature Package
Range
Industrial Temperature,
5LD SC-70.
MCP6546T-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT-23.
Device:
MCP6546: Single Comparator
MCP6546T: Single Comparator (Tape and Reel)
(SC-70, SOT-23, SOIC, MSOP)
MCP6546RT: Single Comparator (Rotated - Tape and
Reel) (SOT-23 only)
MCP6546UT: Single Comparator (Tape and Reel)
(SOT-23-5 is E-Temp only)
c)
d)
MCP6546-E/P:
Extended Temperature,
8LD PDIP.
MCP6546RT-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT23.
MCP6546-E/SN: Extended Temperature,
8LD SOIC.
MCP6547: Dual Comparator
MCP6547T: Dual Comparator
e)
f)
(Tape and Reel for SOIC and MSOP)
MCP6548: Single Comparator with CS
MCP6548T: Single Comparator with CS
(Tape and Reel for SOIC and MSOP)
MCP6549: Quad Comparator
MCP6546UT-E/OT:Tape and Reel,
Extended Temperature,
5LD SOT23.
MCP6549T: Quad Comparator
(Tape and Reel for SOIC and TSSOP)
a)
b)
MCP6547-I/MS: Industrial Temperature,
8LD MSOP.
MCP6547T-I/MS: Tape and Reel,
Industrial Temperature,
8LD MSOP.
Temperature Range:
Package:
I
=
=
-40°C to +85°C
-40°C to +125°C
E *
* SC-70-5 E-Temp parts not available at this release of the
data sheet.
c)
d)
MCP6547-I/P:
Industrial Temperature,
8LD PDIP.
LT
=
=
=
=
=
=
=
Plastic Package (SC-70), 5-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
Plastic MSOP, 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead (MCP6549)
Plastic TSSOP (4.4mm Body), 14-lead (MCP6549)
MCP6547-E/SN: Extended Temperature,
8LD SOIC.
OT
MS
P
SN
SL
ST
a)
b)
MCP6548-I/SN: Industrial Temperature,
8LD SOIC.
MCP6548T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC.
c)
d)
MCP6548-I/P:
Industrial Temperature,
8LD PDIP.
MCP6548-E/SN: Extended Temperature,
8LD SOIC.
a)
b)
MCP6549T-I/SL: Tape and Reel,
Industrial Temperature,
14LD SOIC.
MCP6549T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC.
c)
d)
MCP6549-I/P:
Industrial Temperature,
14LD PDIP.
MCP6549-E/ST: Extended Temperature,
14LD TSSOP.
© 2006 Microchip Technology Inc.
DS21714E-page 29
MCP6546/6R/6U/7/8/9
NOTES:
DS21714E-page 30
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21714E-page 31
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-3910
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
08/29/06
DS21714E-page 32
© 2006 Microchip Technology Inc.
MCP6548-E/LT 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MCP6548-E/MS | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
| MCP6548-E/OT | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
| MCP6548-E/P | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
| MCP6548-E/SL | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
| MCP6548-E/SN | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
| MCP6548-E/ST | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
| MCP6548-I/LT | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
| MCP6548-I/MS | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
| MCP6548-I/OT | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
| MCP6548-I/P | MICROCHIP | Open-Drain Output Sub-Microamp Comparators | 获取价格 |
|
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