MCP6N11-001E/SN [MICROCHIP]
INSTRUMENTATION AMPLIFIER, 3000 uV OFFSET-MAX, 35 MHz BAND WIDTH, PDSO8, 3.90 MM, PLASTIC, SOIC-8;
| 型号： | MCP6N11-001E/SN |
| 厂家： | 
MICROCHIP |
| 描述： | INSTRUMENTATION AMPLIFIER, 3000 uV OFFSET-MAX, 35 MHz BAND WIDTH, PDSO8, 3.90 MM, PLASTIC, SOIC-8 放大器 光电二极管 |
| 文件： | 总50页 (文件大小：5450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6N11
500 kHz, 800 µA Instrumentation Amplifier
Features
Description
• Rail-to-Rail Input and Output
Microchip Technology Inc. offers the single MCP6N11
instrumentation amplifier (INA) with Enable/VOS Cali-
bration pin (EN/CAL) and several minimum gain
options. It is optimized for single-supply operation with
rail-to-rail input (no common mode crossover distor-
tion) and output performance.
• Gain Set by 2 External Resistors
• Minimum Gain (GMIN) Options:
1, 2, 5, 10 or 100 V/V
• Common Mode Rejection Ratio (CMRR): 115 dB
(typical, GMIN = 100)
Two external resistors set the gain, minimizing gain
error and drift-over temperature. The reference voltage
(VREF) shifts the output voltage (VOUT).
• Power Supply Rejection Ratio (PSRR): 112 dB
(typical, GMIN = 100)
• Bandwidth: 500 kHz (typical, Gain = GMIN
• Supply Current: 800 μA/channel (typical)
• Single Channel
)
The supply voltage range (1.8V to 5.5V) is low enough
to support many portable applications. All devices are
fully specified from -40°C to +125°C.
• Enable/VOS Calibration pin: (EN/CAL)
• Power Supply: 1.8V to 5.5V
These parts have five minimum gain options (1, 2, 5, 10
and 100 V/V). This allows the user to optimize the input
offset voltage and input noise for different applications.
• Extended Temperature Range: -40°C to +125°C
Typical Applications
Typical Application Circuit
• High Side Current Sensor
• Wheatstone Bridge Sensors
• Difference Amplifier with Level Shifting
• Power Control Loops
VBAT
+1.8V
to
10 Ω
IDD
VDD
U1
+5.5V
MCP6N11
VOUT
Design Aids
RF
• Microchip Advanced Part Selector (MAPS)
• Demonstration Board
200 kΩ
VFG
RG
10 kΩ
• Application Notes
VREF
Block Diagram
Package Types
VDD VSS
VOUT
MCP6N11
MCP6N11
2×3 TDFN *
VOUT
RM4
SOIC
I4
RF
VFG
V
V
EN/CAL
V
EN/CAL
1
2
8
7
1
2
8
7
FG
FG
GM2
RG
Σ
V
V
V
V
EP
9
IM
DD
IM
DD
VREF
I2
I3
VREF
VIP
V
V
3
4
6
5
V
V
3
4
6
5
IP
OUT
IP
OUT
I1
V
V
SS
REF
V
SS
REF
GM3
VTR
Low Power
VIP
VIM
GM1
POR
* Includes Exposed Thermal Pad (EP); see Table 3-1.
VIM
VOS Calibration
EN/CAL
© 2011 Microchip Technology Inc.
DS25073A-page 1
MCP6N11
Minimum Gain Options
Table 1 shows key specifications that differentiate
between the different minimum gain (GMIN) options.
See Section 1.0 “Electrical Characteristics”,
Section 6.0 “Packaging Information” and Product
Identification System for further information on GMIN
.
TABLE 1:
Part No.
KEY DIFFERENTIATING SPECIFICATIONS
Eni
(µVP-P
Nom.
eni
(nV/√Hz)
Nom.
GMIN
VOS ∆VOS/∆TA CMRR (dB) PSRR VDMH GBWP
)
(V/V) (±mV) (±µV/°C)
Min.
(dB)
(V)
Max.
(MHz)
Nom.
Nom. Max.
Typ.
VDD = 5.5V Min.
(f = 0.1 to 10 Hz) (f = 10 kHz)
MCP6N11-001
MCP6N11-002
MCP6N11-005
1
2
5
3.0
2.0
90
45
70
78
80
81
88
62
68
75
81
86
2.70
1.35
0.54
0.27
0.027
0.50
1.0
2.5
5.0
35
570
285
114
57
950
475
190
95
0.85
0.50
0.35
18
MCP6N11-010 10
MCP6N11-100 100
9.0
2.7
18
35
DS25073A-page 2
© 2011 Microchip Technology Inc.
MCP6N11
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
– V
.......................................................................6.5V
SS
DD
Current at Input Pins †† ...............................................±2 mA
Analog Inputs (V and V ) †† ..... V – 1.0V to V + 1.0V
IP
IM
SS
DD
†† See Section 4.2.1.2 “Input Voltage Limits” and
Section 4.2.1.3 “Input Current Limits”.
All Other Inputs and Outputs ......... V – 0.3V to V + 0.3V
SS
DD
Difference Input Voltage....................................... |V – V
|
DD
SS
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................+150°C
ESD protection on all pins (HBM, CDM, MM).≥ 2 kV, 1.5 kV, 300V
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
TABLE 1-1:
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = 1.8V to 5.5V, V = GND, EN/CAL = V ,
DD
A
DD
SS
V
= V /2, V
= 0V, V
= V /2, V = V /2, R = 10 kΩ to V and G
= G ; see Figure 1-6 and Figure 1-7.
CM
DD
DM
REF
DD
L
DD
L
L
DM MIN
Parameters
Sym
Min
Typ
Max
Units GMIN
Conditions
Input Offset
Input Offset Voltage,
Calibrated
VOS
-3.0
-2.0
-0.85
-0.50
-0.35
—
—
—
+3.0
+2.0
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
1
2
(Note 2)
—
+0.85
+0.50
+0.35
—
5
—
10
100
1
—
Input Offset Voltage
Trim Step
VOSTRM
0.36
0.21
0.077
0.045
0.014
—
—
2
—
—
5
—
—
10
100
—
—
Input Offset Voltage
Drift
ΔVOS/ΔTA
—
±90/GMIN
±2.7
82
—
µV/°C 1 to 10 TA= -40°C to +125°C
(Note 3)
—
—
µV/°C
dB
100
1
Power Supply
PSRR
62
—
Rejection Ratio
68
88
—
dB
2
75
96
—
dB
5
81
102
112
—
dB
10
100
86
—
dB
Note 1:
V
= (V + V ) / 2, V
= (V – V ) and G
= 1 + R /R .
CM
IP
IM
DM
IP
IM
DM F G
2: The V spec limits include 1/f noise effects.
OS
3: This is the input offset drift without V re-calibration; toggle EN/CAL to minimize this effect.
OS
4: These specs apply to both the V , V input pair (use V ) and to the V
, V input pair (V
takes V ’s place).
IP IM
CM
REF FG
REF
CM
5: This spec applies to the V , V , V
and V pins individually.
IP IM
REF
FG
6: Figure 2-11 and Figure 2-19 show the V
and V
variation over temperature.
IVR
DMR
7: See Section 1.5 “Explanation of DC Error Specs”.
© 2011 Microchip Technology Inc.
DS25073A-page 3
MCP6N11
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = 1.8V to 5.5V, V = GND, EN/CAL = V ,
DD
A
DD
SS
V
= V /2, V
= 0V, V
= V /2, V = V /2, R = 10 kΩ to V and G
= G ; see Figure 1-6 and Figure 1-7.
DM MIN
CM
DD
DM
REF
DD
L
DD
L
L
Parameters
Sym
Min
Typ
Max
Units GMIN
Conditions
Input Current and Impedance (Note 4)
Input Bias Current
Across Temperature
Across Temperature
Input Offset Current
Across Temperature
Across Temperature
IB
—
—
0
10
80
—
—
5
pA
pA
all
TA= +85°C
2
nA
TA= +125°C
IOS
—
—
-1
—
±1
—
—
+1
—
pA
±5
pA
TA= +85°C
±0.05
1013||6
nA
TA= +125°C
Common Mode Input
Impedance
ZCM
Ω||pF
Differential Input
Impedance
ZDIFF
—
1013||3
—
Ω||pF
Input Common Mode Voltage (VCM or VREF) (Note 4)
Input Voltage Range
VIVL
VIVH
—
VDD + 0.15
62
—
—
VSS − 0.2
—
V
all
(Note 5, Note 6)
V
Common Mode
Rejection Ratio
CMRR
79
—
dB
1
2
VCM = VIVL to VIVH
VDD = 1.8V
,
,
,
69
87
—
dB
75
101
107
119
94
—
dB
5
79
—
dB
10
100
1
86
—
dB
70
—
dB
VCM = VIVL to VIVH
VDD = 5.5V
78
100
108
114
115
±115
±27
±11
±6
—
dB
2
80
—
dB
5
81
—
dB
10
100
1
88
—
dB
Common Mode
Non-Linearity
INLCM
-1000
-570
-230
-125
-50
+1000
+570
+230
+125
+50
+400
+220
+100
+50
+30
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
VCM = VIVL to VIVH
VDM = 0V,
2
VDD = 1.8V (Note 7)
5
10
100
1
±2
-400
-220
-100
-50
±42
±10
±4
VCM = VIVL to VIVH
VDM = 0V,
V
,
2
DD = 5.5V (Note 7)
5
±2
10
100
-30
±1
Note 1:
V
= (V + V ) / 2, V
= (V – V ) and G
= 1 + R /R .
CM
IP
IM
DM
IP
IM
DM F G
2: The V spec limits include 1/f noise effects.
OS
3: This is the input offset drift without V re-calibration; toggle EN/CAL to minimize this effect.
OS
4: These specs apply to both the V , V input pair (use V ) and to the V
, V input pair (V
takes V ’s place).
REF CM
IP IM
CM
REF FG
5: This spec applies to the V , V , V
and V pins individually.
IP IM
REF
FG
6: Figure 2-11 and Figure 2-19 show the V
and V
variation over temperature.
IVR
DMR
7: See Section 1.5 “Explanation of DC Error Specs”.
DS25073A-page 4
© 2011 Microchip Technology Inc.
MCP6N11
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = 1.8V to 5.5V, V = GND, EN/CAL = V ,
DD
A
DD
SS
V
= V /2, V
= 0V, V
= V /2, V = V /2, R = 10 kΩ to V and G
= G ; see Figure 1-6 and Figure 1-7.
DM MIN
CM
DD
DM
REF
DD
L
DD
L
L
Parameters
Sym
Min
Typ
Max
Units GMIN
Conditions
Input Differential Mode Voltage (VDM) (Note 4)
Differential Input
Voltage Range
VDML
VDMH
gE
-2.7/GMIN
—
—
—
—
V
V
all
VREF = (VDD – GDMVDM)/2
(Note 6)
+2.7/GMIN
+1
Differential Gain Error
Differential Gain Drift
-1
±0.13
±0.0006
±30
±40
±100
84
%
VDM = VDML to VDMH,
ΔgE/ΔTA
INLDM
—
—
%/°C
ppm
ppm
VREF = (VDD – GDMVDM)/2
Differential
Non-Linearity
-500
-800
-2000
61
+500
+800
+2000
—
1
(Note 7)
2, 5
ppm 10, 100
DC Open-Loop Gain
AOL
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
1
2
VDD = 1.8V,
68
90
—
VOUT = 0.2V to 1.6V
76
98
—
5
78
104
116
94
—
10
100
1
86
—
70
—
VDD = 5.5V,
77
100
108
114
125
—
2
VOUT = 0.2V to 5.3V
84
—
5
90
—
10
100
97
—
Output
Minimum Output
Voltage Swing
VOL
VOH
ISC
—
—
—
—
—
VSS + 15
VSS + 25
—
mV
mV
mV
mV
all
VDM = -VDD/(2GDM),
VDD = 1.8V,
VREF = VDD/2 – 1V
—
VDM = -VDD/(2GDM),
VDD = 5.5V,
VREF = VDD/2 – 1V
Maximum Output
Voltage Swing
VDD − 15
VDD − 25
VDM = VDD/(2GDM),
VDD = 1.8V,
VREF = VDD/2 + 1V
—
VDM = VDD/(2GDM),
VDD = 5.5V,
VREF = VDD/2 + 1V
Output Short Circuit
Current
—
—
±8
—
—
mA
mA
VDD = 1.8V
VDD = 5.5V
±30
Power Supply
Supply Voltage
VDD
IQ
1.8
0.5
—
5.5
1.1
V
all
Quiescent Current
per Amplifier
0.8
mA
IO = 0
POR Trip Voltage
VPRL
VPRH
1.1
—
1.4
1.4
—
V
V
1.7
Note 1:
V
= (V + V ) / 2, V
= (V – V ) and G
= 1 + R /R .
CM
IP
IM
DM
IP
IM
DM F G
2: The V spec limits include 1/f noise effects.
OS
3: This is the input offset drift without V re-calibration; toggle EN/CAL to minimize this effect.
OS
4: These specs apply to both the V , V input pair (use V ) and to the V
, V input pair (V
takes V ’s place).
IP IM
CM
REF FG
REF
CM
5: This spec applies to the V , V , V
and V pins individually.
IP IM
REF
FG
6: Figure 2-11 and Figure 2-19 show the V
and V
variation over temperature.
IVR
DMR
7: See Section 1.5 “Explanation of DC Error Specs”.
© 2011 Microchip Technology Inc.
DS25073A-page 5
MCP6N11
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = 1.8V to 5.5V, VSS = GND,
EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN
see Figure 1-6 and Figure 1-7.
;
Parameters
Sym Min
Typ
Max Units
GMIN
Conditions
AC Response
Gain Bandwidth
Product
GBWP
—
—
—
—
—
—
0.50 GMIN
—
—
—
—
—
—
MHz
MHz
°
1 to 10
100
35
70
Phase Margin
PM
all
Open-Loop Output
Impedance
ROL
0.9
0.6
94
kΩ
kΩ
dB
1 to 10
100
Power Supply
Rejection Ratio
PSRR
CMRR
all
f < 10 kHz
Common Mode
Rejection Ratio
—
—
104
94
—
—
dB
dB
1 to 10 f < 10 kHz
100 f < 10 kHz
Step Response
Slew Rate
SR
—
—
—
—
—
3
9
—
—
—
—
—
V/µs
V/µs
V/µs
V/µs
µs
1 to 10 VDD = 1.8V
VDD = 5.5V
2
100 VDD = 1.8V
VDD = 5.5V
6
Overdrive Recovery,
Input Common Mode
tIRC
tIRD
10
all
VCM = VSS – 1V (or VDD + 1V) to VDD/2,
DMVDM = ±0.1V, 90% of VOUT change
VDM = VDML – (0.5V)/GMIN
(or VDMH + (0.5V)/GMIN) to 0V,
REF = (VDD – GDMVDM)/2,
G
Overdrive Recovery,
Input Differential
Mode
—
5
8
—
µs
V
90% of VOUT change
Overdrive Recovery,
Output
tOR
—
—
µs
GDM = 2GMIN, GDMVDM = 0.5VDD to 0V,
VREF = 0.75VDD (or 0.25VDD),
90% of VOUT change
Noise
Input Noise Voltage
Eni
eni
ini
—
—
—
—
—
570/GMIN
—
—
—
—
—
µVP-P 1 to 10 f = 0.1 Hz to 10 Hz
µVP-P 100
nV/√Hz 1 to 10 f = 100 kHz
18
Input Noise Voltage
Density
950/GMIN
35
1
nV/√Hz
fA/√Hz
100
all
Input Current Noise
Density
f = 1 kHz
DS25073A-page 6
© 2011 Microchip Technology Inc.
MCP6N11
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD
,
V
CM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN
;
see Figure 1-6 and Figure 1-7.
Parameters
Sym
Min
Typ
Max Units GMIN
Conditions
EN/CAL Low Specifications
EN/CAL Logic
Threshold, Low
VIL
VSS
—
—
0.2 VDD
—
V
all
EN/CAL Input Current,
Low
IENL
-0.1
nA
EN/CAL = 0V
GND Current
ISS
-7
-2.5
10
—
—
µA
nA
EN/CAL = 0V, VDD = 5.5V
EN/CAL = 0V
Amplifier Output Leakage
IO(LEAK)
—
EN/CAL High Specifications
EN/CAL Logic
Threshold, High
VIH
0.8 VDD
—
VDD
—
V
all
all
EN/CAL Input Current,
High
IENH
-0.01
nA
EN/CAL = VDD
EN/CAL Dynamic Specifications
—
—
—
EN/CAL Input Hysteresis VHYST
0.2
3
V
EN/CAL Low to Amplifier
Output High-Z Turn-off
Time
tOFF
10
µs
EN/CAL = 0.2VDD to VOUT = 0.1(VDD/2),
VDMGDM = 1 V, VL = 0V
EN/CAL High to
Amplifier Output
On Time
tON
12
20
28
ms
EN/CAL = 0.8VDD to VOUT = 0.9(VDD/2),
VDMGDM = 1 V, VL = 0V
EN/CAL Low to
EN/CAL High low time
tENLH
tENOL
100
—
—
—
—
µs
µs
Minimum time before externally
releasing EN/CAL (Note 1)
Amplifier On to
EN/CAL Low Setup Time
100
POR Dynamic Specifications
VDD ↓ to Output Off
tPHL
—
10
—
µs
all VL = 0V, VDD = 1.8V to
VPRL – 0.1V step,
90% of VOUT change
VDD ↑ to Output On
tPLH
VL = 0V, VDD = 0V to VPRH + 0.1V step,
90% of VOUT change
140
250
360
ms
Note 1: For design guidance only; not tested.
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = 1.8V to 5.5V, VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max Units
Conditions
Specified Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
Operating Temperature Range
Storage Temperature Range
(Note 1)
Thermal Package Resistances
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-TDFN (2×3)
θJA
θJA
—
—
150
53
—
—
°C/W
°C/W
Note 1: Operation must not cause T to exceed the Absolute Maximum Junction Temperature specification (+150°C).
J
© 2011 Microchip Technology Inc.
DS25073A-page 7
MCP6N11
1.3
Timing Diagrams
tENLH
±(1V)/GDM
EN/CAL
VDM
tENOL
tOFF
tON
VCM
High-Z
VOUT
tIRC
FIGURE 1-5:
EN/CAL Timing Diagram.
VOUT
FIGURE 1-1:
Common Mode Input
Overdrive Recovery Timing Diagram.
VDD/2
VCM
VDM
tIRD
VOUT
FIGURE 1-2:
Differential Mode Input
Overdrive Recovery Timing Diagram.
VDD/2
VCM
VDM
tOR
VOUT
FIGURE 1-3:
Output Overdrive Recovery
Timing Diagram.
1.8V
VPRH + 0.1V
VPRL – 0.1V
VDD
0V
tPHL
tPLH
High-Z
VOUT
FIGURE 1-4:
POR Timing Diagram.
DS25073A-page 8
© 2011 Microchip Technology Inc.
MCP6N11
1.4.2
DIFFERENTIAL GAIN TEST CIRCUIT
1.4
DC Test Circuits
Figure 1-7 is used for testing the INA’s differential gain
error, non-linearity and input voltage range (gE, INLDM
1.4.1
INPUT OFFSET TEST CIRCUIT
,
Figure 1-6 is used for testing the INA’s input offset
errors and input voltage range (VE, VIVL and VIVH; see
Section 1.5.1 “Input Offset Related Errors” and
Section 1.5.2 “Input Offset Common Mode Non-
linearity”). U2 is part of a control loop that forces VOUT
to equal VCNT; U1 can be set to any bias point.
VDML and VDMH; see Section 1.5.3 “Differential Gain
Error and Non-linearity”). RF and RG are 0.01% for
accurate gain error measurements.
VDD
VL
2.2 µF
100 nF
VCM + VDM/2
VDD
RL
VOUT
VL
2.2 µF
VCM
1 kΩ
100 nF
U1
VOUT
RL
MCP6N11
RF
0.01%
6.34 kΩ
1 kΩ
1 kΩ
+
VM
–
1 kΩ
U1
100 nF
RG
0.01%
MCP6N11
VFG
VCM – VDM/2
6.34 kΩ
VREF
RG
RF
VREF
Test Circuit for Differential
U2
MCP6H01 63.4 kΩ
FIGURE 1-7:
Mode.
RCNT
63.4 kΩ
The output voltages are (where VE is the sum of input
offset errors and gE is the gain error):
12.7 kΩ
VM
CCNT
10 nF
100 nF
EQUATION 1-2:
VCNT
GDM = 1 + RF ⁄ RG
FIGURE 1-6:
Mode (Input Offset).
Test Circuit for Common
VOUT = VREF + GDM(1 + gE)(VDM + VE)
VM = VOUT – VREF
When MCP6N11 is in its normal range of operation, the
DC output voltages are (where VE is the sum of input
offset errors and gE is the gain error):
= GDM(1 + gE)(VDM + VE)
To keep VREF, VFG and VOUT within their ranges, set:
EQUATION 1-1:
EQUATION 1-3:
GDM = 1 + RF ⁄ RG
VOUT = VCNT
VREF = (VDD – GDMVDM) ⁄ 2
VM = VREF + GDM(1 + gE)VE
Table 1-6 shows the recommended RF and RG. They
produce a 10 kΩ load; VL can usually be left open.
Table 1-5 gives the recommended RF and RG values
for different GMIN options.
TABLE 1-6:
SELECTING RF AND RG
TABLE 1-5:
SELECTING RF AND RG
GMIN
(V/V)
Nom.
RF
(Ω)
Nom.
RG
(Ω)
Nom.
GDM
(V/V)
Nom.
GMIN
(V/V)
RF
(Ω)
RG
GDM GDMVOS BW
(Ω)
(V/V)
(±V)
(kHz)
Nom.
Nom. Nom. Nom. Nom.
Max.
1
2
0
Open
4.99k
2.00k
1.00k
100
1.000
2.000
5.030
10.09
101.0
4.99k
8.06k
9.09k
10.0k
1
2
100k
100k
499
100
201.4
1001
0.60
0.40
0.85
0.50
0.35
2.5
5.0
2.5
5.0
35
5
10
100
5
10
100
© 2011 Microchip Technology Inc.
DS25073A-page 9
MCP6N11
Based on the measured VE data, we obtain the
following linear fit:
1.5
Explanation of DC Error Specs
1.5.1
INPUT OFFSET RELATED ERRORS
EQUATION 1-6:
The input offset error (VE) is extracted from input offset
measurements (see Section 1.4.1 “Input Offset Test
Circuit”), based on Equation 1-1:
VCM – VDD ⁄ 2
VE_LIN = VOS + ----------------------------------
CMRR
Where:
EQUATION 1-4:
VOS = V2
V3 – V1
VM – VREF
1
---------------- = -----------------------------
VE = --------------------------------
CMRR
VIVH – VIVL
GDM(1 + gE)
The remaining error (ΔVE) is described by the Common
Mode Non-Linearity spec:
VE has several terms, which assume a linear response
to changes in VDD, VSS, VCM, VOUT and TA (all of which
are in their specified ranges):
EQUATION 1-7:
EQUATION 1-5:
max ΔVE
INLCM = -----------------------------
ΔVDD – ΔVSS ΔVCM ΔVREF
VIVH – VIVL
VE = VOS + --------------------------------- + ---------------- + ----------------
Where:
PSRR
CMRR CMRR
ΔVE = VE – VE_LIN
ΔVOUT
ΔVOS
+ ----------------- + ΔTA ⋅ -------------
AOL
ΔTA
The same common mode behavior applies to VE when
VREF is swept, instead of VCM, since both input stages
are designed the same:
Where:
PSRR, CMRR and AOL are in units of V/V
ΔTA is in units of °C
EQUATION 1-8:
VDM = 0
VREF – VDD ⁄ 2
VE_LIN = VOS + ------------------------------------
Equation 1-2 shows how VE affects VOUT
.
CMRR
max ΔVE
1.5.2
INPUT OFFSET COMMON MODE
NON-LINEARITY
INLCM = -----------------------------
VIVH – VIVL
The input offset error (VE) changes non-linearly with
VCM. Figure 1-8 shows VE vs. VCM, as well as a linear
fit line (VE_LIN) based on VOS and CMRR. The op amp
is in standard conditions (ΔVOUT = 0, VDM = 0, etc.).
VCM is swept from VIVL to VIVH. The test circuit is in
Section 1.4.1 “Input Offset Test Circuit” and VE is
calculated using Equation 1-4.
1.5.3
DIFFERENTIAL GAIN ERROR AND
NON-LINEARITY
The differential errors are extracted from differential
gain measurements (see Section 1.4.2 “Differential
Gain Test Circuit”), based on Equation 1-2. These
errors are the differential gain error (gE) and the input
offset error (VE, which changes non-linearly with VDM):
VE, VE_LIN (V)
VE_LIN
VE
EQUATION 1-9:
V3
V2
GDM = 1 + RF ⁄ RG
VM = GDM(1 + gE)(VDM + VE)
These errors are adjusted for the expected output, then
referred back to the input, giving the differential input
error (VED) as a function of VDM
:
V1
ΔVE
VCM (V)
EQUATION 1-10:
VIVL
FIGURE 1-8:
VDD/2
VIVH
VM
VED = ----------- – VDM
GDM
Input Offset Error vs.
Common Mode Input Voltage.
DS25073A-page 10
© 2011 Microchip Technology Inc.
MCP6N11
Figure 1-9 shows VED vs. VDM, as well as a linear fit
line (VED_LIN) based on VE and gE. The op amp is in
standard conditions (ΔVOUT = 0, etc.). VDM is swept
from VDML to VDMH
.
VED, VED_LIN (V)
VED_LIN
VED
V3
V2
V1
ΔVED
VDM (V)
VDML
0
VDMH
FIGURE 1-9:
Differential Input Error vs.
Differential Input Voltage.
Based on the measured VED data, we obtain the
following linear fit:
EQUATION 1-11:
VED_LIN = (1 + gE)VE + gEVDM
Where:
V3 – V1
gE = ----------------------------------- – 1
V
DMH – VDML
V2
VE = ---------------
1 + gE
Note that the VE value measured here is not as
accurate as the one obtained in Section 1.5.1 “Input
Offset Related Errors”.
The remaining error (ΔVED) is described by the
Differential Mode Non-Linearity spec:
EQUATION 1-12:
max ΔVED
INLDM = -----------------------------------
VDMH – VDML
Where:
ΔVED = VED – VED_LIN
© 2011 Microchip Technology Inc.
DS25073A-page 11
MCP6N11
NOTES:
DS25073A-page 12
© 2011 Microchip Technology Inc.
MCP6N11
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
REF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
V
2.1
DC Voltages and Currents
25%
20%
15%
10%
5%
35%
No VOS Re-calibration
330 Samples
GMIN = 1 to 10
VDD = 5.5V
330 Samples
TA = +25°C
30%
25%
20%
15%
10%
5%
V
DD = 1.8V and 5.5V
RTO
RTO
GMIN = 1
MIN
0%
0%
Normalized Input Offset Voltage Drift;
MIN(ꢀVOS/ꢀTA) (μV/°C)
Normalized Input Offset Voltage; GMINVOS (mV)
G
FIGURE 2-1:
Normalized Input Offset
FIGURE 2-3:
Normalized Input Offset
Voltage, with GMIN = 1 to 10.
Voltage Drift, with GMIN = 1 to 10.
14%
12%
10%
8%
18%
16%
14%
12%
10%
330 Samples
MIN = 100
No VOS Re-calibration
G
330 Samples
TA = +25°C
VDD = 1.8V and 5.5V
RTO
GMIN = 100
VDD = 5.5V
RTO
6%
6%
2%
0%
4%
0%
Normalized Input Offset Voltage Drift;
GMIN(ꢀVOS/ꢀTA) (μV/°C)
Normalized Input Offset Voltage; GMINVOS (mV)
FIGURE 2-2:
Normalized Input Offset
FIGURE 2-4:
Normalized Input Offset
Voltage, with GMIN = 100.
Voltage Drift, with GMIN = 100.
© 2011 Microchip Technology Inc.
DS25073A-page 13
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
2.5
2.0
10
8
6
Representative Part
VCM = VDD
GMIN = 100
RTO
1.5
1.0
4
0.5
2
0.0
0
-2
-4
-6
-8
-10
-0.5
-1.0
-1.5
-2.0
-2.5
-40°C
+25°C
+85°C
+125°C
-40°C
Representative Part
VCM = VSS
GMIN = 1 to 10
RTO
+25°C
+85°C
+125°C
Power Supply Voltage
Power Supply Voltage
FIGURE 2-5:
Normalized Input Offset
FIGURE 2-8:
Normalized Input Offset
Voltage vs. Power Supply Voltage, with
Voltage vs. Power Supply Voltage, with
VCM = 0V and GMIN = 1 to 10.
V
CM = VDD and GMIN = 100.
25
20
15
5
2.0
1.5
Representative Part
GMIN = 1 to 10
RTO
VDD = 1.8V
1.0
0.5
0.0
VDD = 5.5V
0
-5
-10
-15
-20
-25
-0.5
-1.0
-1.5
-2.0
-40°C
Representative Part
VCM = VSS
GMIN = 100
RTO
25°C
85°C
125°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Power Supply Voltage
FIGURE 2-6:
Normalized Input Offset
FIGURE 2-9:
Normalized Input Offset
Voltage vs. Power Supply Voltage, with
Voltage vs. Output Voltage, with GMIN = 1 to 10.
VCM = 0V and GMIN = 100.
6
5
4
3
2
1
0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Representative Part
VCM = VDD
Representative Part
GMIN = 100
GMIN = 1 to 10
RTO
RTO
VDD = 1.8V
-40°C
+25°C
+85°C
+125°C
VDD = 5.5V
-0.2
-0.6
-0.8
-1.0
-1.2
-1
-2
-3
-4
-5
-6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Power Supply Voltage
FIGURE 2-7:
Normalized Input Offset
FIGURE 2-10:
Normalized Input Offset
Voltage vs. Power Supply Voltage, with
CM = VDD and GMIN = 1 to 10.
Voltage vs. Output Voltage, with GMIN = 100.
V
DS25073A-page 14
© 2011 Microchip Technology Inc.
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
0.5
0.4
0.3
0.1
2.0
1.5
1 Wafer Lot
VDD = 5.5V
VIVH – VDD
Representative Part
GMIN = 1 to 10
RTO
1.0
0.5
VDD = 1.8V
VDD = 5.5V
0.0
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
+125°C
+85°C
+25°C
-40°C
-0.5
-1.0
-1.5
-2.0
VIVL – VSS
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Input Common Mode Voltage (V)
FIGURE 2-11:
Input Common Mode
FIGURE 2-14:
Normalized Input Offset
Voltage Headroom vs. Ambient Temperature.
Voltage vs. Common Mode Voltage, with
V
DD = 5.5V and GMIN = 1 to 10.
2.0
15
10
5
VDD = 1.8V
VDD = 5.5V
Representative Part
GMIN = 100
RTO
Representative Part
1.5
GMIN = 1 to 10
RTO
1.0
0.5
0.0
0
-0.5
-5
+125°C
+125°C
-1.0
+85°C
+85°C
+25°C
-40°C
-10
-15
+25°C
-1.5
-40°C
-2.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
Input Common Mode Voltage (V)
Input Common Mode Voltage (V)
FIGURE 2-12:
Normalized Input Offset
FIGURE 2-15:
Normalized Input Offset
Voltage vs. Common Mode Voltage, with
Voltage vs. Common Mode Voltage, with
VDD = 1.8V and GMIN = 1 to 10.
V
DD = 5.5V and GMIN = 100.
15
10
5
110
VDD = 1.8V
Representative Part
GMIN = 100
RTO
CMRR / GMIN, VDD = 5.5V:
MIN
CMRR / GMIN, VDD = 1.8V:
105
MIN = 1,
GMIN = 100
GMIN = 2 to 10
100
95
90
85
80
75
70
65
0
-5
+125°C
+85°C
-10
MIN
+25°C
GMIN = 1 to 10
GMIN = 100
-40°C
-15
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
-50
-25
0
25
50
75
100 125
Input Common Mode Voltage (V)
Ambient Temperature (°C)
FIGURE 2-13:
Voltage vs. Common Mode Voltage, with
DD = 1.8V and GMIN = 100.
Normalized Input Offset
FIGURE 2-16:
PSRR vs. Ambient Temperature.
Normalized CMRR and
V
© 2011 Microchip Technology Inc.
DS25073A-page 15
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
5
4
3
2
1
110
105
100
90
85
80
75
70
65
Representative Part
VED = (VOUT – VREF)/GDM – VDM
GMIN = 1
VDD = 5.5V
DD = 1.8V
V
RTO
VDD = 1.8V
0
-1
-3
-4
-5
VDD = 5.5V
GMIN = 1 to 10
GMIN = 100
60
-5 -4 -3 -2 -1
Normalized Differential Input Voltage;
MINVDM (V)
0
1
2
3
4
5
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
G
FIGURE 2-17:
Normalized DC Open-Loop
FIGURE 2-20:
Normalized Differential Input
Gain vs. Ambient Temperature.
Error vs. Differential Voltage, with GMIN = 1.
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
1.5
1.0
0.5
0.0
5
4
3
2
1
-1
-3
-5
Representative Part
Representative Part
VDD = 5.5V
ED OUT REFDM DM
GMIN = 2 to 100
RTO
DM
GDM
=
1
VIM = -0.20V
VIM = VDD + 0.15V
Normalized Differential Input Voltage;
Non-inverting Input Voltage; VIP (V)
GMINVDM (V)
FIGURE 2-18:
The MCP6N11 Shows No
FIGURE 2-21:
Normalized Differential Input
Phase Reversal vs. Common Mode Voltage.
Error vs. Differential Voltage, with
G
MIN = 2 to 100.
4.0
5.5
1 Wafer Lot
Representative Part
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.8
3.6
3.2
3.0
2.8
2.6
2.4
2.2
2.0
G
MINVDMH = -GMINVDML
VDD = 5.5V
RTO
VREF = (VDD – GDMVDM)/2
GMIN = 1
GMIN = 2
GMIN = 5
Note: For GMIN = 1,
VDMH = minimum of plot value and VDD
G
MIN = 10
GMIN = 100
-50
-25
0
25
Axis Title
50
75
100
125
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
Differential Input Voltage (V)
FIGURE 2-19:
Mode Voltage Range vs. Ambient Temperature.
Normalized Differential
FIGURE 2-22:
Phase Reversal vs. Differential Voltage, with
DD = 5.5V.
The MCP6N11 Shows No
V
DS25073A-page 16
© 2011 Microchip Technology Inc.
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
2.5
2.0
1.E
10n
Representative Part
TA = +125°C
VDD = 5.5V
VDD = 5.5V
VCM = VDD
1.5
1.E-
1n
1.0
IB
0.5
IB
0.0
1.
100p
IOS
-0.5
-1.0
-1.5
-2.0
-2.5
1.E
10p
| IOS
|
1.E-
1p
25
45
65
85
105
125
Common Mode Input Voltage (V)
Ambient Temperature (°C)
FIGURE 2-23:
Input Bias and Offset
FIGURE 2-26:
Input Bias and Offset
Currents vs. Ambient Temperature, with
Currents vs. Common Mode Input Voltage, with
TA = +125°C.
VDD = +5.5V.
1000
1.E1m
1.100μ
1.E10μ
1.E-1μ
1100n
1.E10n
1.E-019n
1100p
1.E10p
VDD = 5.5V
VDD = 1.8V
+125°C
+85°C
+25°C
-40°C
100
VDD – VOH
VOL – VSS
1p
1.E-
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
0.1
1
10
Input Voltage (V)
Output Current Magnitude (mA)
FIGURE 2-24:
Input Bias Current vs.
FIGURE 2-27:
Output Voltage Headroom
Input Voltage (below VSS).
vs. Output Current.
100
10
9
8
6
5
4
3
2
1
Representative Part
TA = +85°C
VDD = 5.5V
80
60
VDD – VOH
VDD = 5.5V
40
IB
20
0
IOS
-20
-40
-60
-80
-100
VDD = 1.8V
VOL – VSS
-50
-25
0
25
50
75
100
125
Common Mode Input Voltage (V)
Ambient Temperature (°C)
FIGURE 2-25:
Input Bias and Offset
FIGURE 2-28:
Output Voltage Headroom
Currents vs. Common Mode Input Voltage, with
TA = +85°C.
vs. Ambient Temperature.
© 2011 Microchip Technology Inc.
DS25073A-page 17
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
50
40
1100
1000
900
800
700
600
500
400
300
200
100
0
30
VDD = 5.5V
20
10
+125°C
+85°C
+25°C
-40°C
VDD = 1.8V
0
-10
-20
-30
-40
-50
Power Supply Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-29:
Output Short Circuit Current
FIGURE 2-31:
Supply Current vs. Common
vs. Power Supply Voltage.
Mode Input Voltage.
1100
1000
900
800
700
600
500
400
300
200
100
0
+125°C
+85°C
+25°C
-40°C
Power Supply Voltage (V)
FIGURE 2-30:
Supply Current vs. Power
Supply Voltage.
DS25073A-page 18
© 2011 Microchip Technology Inc.
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
2.2
Frequency Response
100
90
80
70
60
50
40
30
20
10
0
0.50
0.45
0.40
0.30
0.25
0.20
0.15
0.10
0.05
0.00
150
140
130
110
100
90
VDD = 5.5V
GMIN = 1
G
MIN = 2
PM
GMIN = 5
GMIN = 10
GMIN = 100
MIN
GMIN = 2
80
G
MIN = 5
70
GMIN = 10
GMIN = 100
60
50
1k
1.03
10k
14
100k
15
1M
1.6
-50 -25
0
25
50
75 100 125
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-32:
CMRR vs. Frequency.
FIGURE 2-35:
Normalized Gain Bandwidth
Product and Phase Margin vs. Ambient
Temperature.
120
110
100
90
80
70
1.E
10k
VDD = 5.5V
GMIN = 1 to 10
DMMIN
1.E+
1k
60
50
GMIN = 100
1.E+ 2
100
GMIN = 1
30
10
0
GMIN = 2
GMIN = 5
GMIN = 10
GMIN = 100
GDM/GMIN = 1
1k
10k
14
100k
15
1M
1.6
1.03
1k
10k
14
100k
1M
16
10M
17
1.03
15
Frequency (Hz)
Frequency (Hz)
FIGURE 2-33:
PSRR vs. Frequency.
FIGURE 2-36:
Closed-Loop Output
Impedance vs. Frequency.
7
120
100
80
-60
GMIN = 10
GDM = 20
= 50
-90
GMIN = GDM = 1
6
-AOL/GMIN
= 2
-120
= 5
= 10
4
3
2
1
= 100
40
| AOL/GMIN
|
-180
-210
-240
-270
-300
-330
-360
20
GMIN = 100
GDM = 200
= 500
0
-20
-40
-60
-80
GMIN = 1
G
MIN = 2
MIN
GMIN = 10
MIN = 100
G
10k
100k
1M
1.E+6
10M
1.E+7
10p
1.E+1
100p
1.E+2
1n
1.E+4
1.E+5
1.E+3
Frequency (Hz)
Normalized Capacitive Load; CL(GMIN/GDM) (F)
FIGURE 2-34:
Normalized Open-Loop
FIGURE 2-37:
Gain Peaking vs.
Gain vs. Frequency.
Normalized Capacitive Load.
© 2011 Microchip Technology Inc.
DS25073A-page 19
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
2.3
Noise
0.5
0.4
1000
1m
Analog NPBW = 0.1 Hz
Sample Rate = 4 SPS
Representative Part
MIN = 1 to 10
RTO
RTO
G
0.3
100
100μ
GMIN = 100
0.1
1100μ
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
GMIN = 10
1
1μ
GMIN = 5
MIN
GMIN = 1
100n
0.1
0.1
1
10
100
1k
10k 100k 1M
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6
Frequency (Hz)
0
5
10
15
20
25
30
35
Time (min)
FIGURE 2-38:
Normalized Input Noise
FIGURE 2-41:
Normalized Input Noise
Voltage Density vs. Frequency.
Voltage vs. Time, with GMIN = 1 to 10.
2.0
14
12
Analog NPBW = 0.1 Hz
Sample Rate = 4 SPS
Representative Part
MIN = 100
RTO
G
1.0
10
GMIN = 100
GMIN = 10
VDD = 1.8V
DD = 5.5V
0.5
G
MIN = 5
8
6
4
0
V
MIN
GMIN = 1
0.0
-0.5
-1.0
-1.5
-2.0
f = 100 Hz
RTO
0
5
10
15
20
25
30
35
Common Mode Input Voltage (V)
Time (min)
FIGURE 2-39:
Normalized Input Noise
FIGURE 2-42:
Normalized Input Noise
Voltage Density vs. Input Common Mode
Voltage, with f = 100 Hz.
Voltage vs. Time, with GMIN = 100.
4.0
3.5
3.0
GMIN = 100
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 1.8V
DD = 5.5V
G
MIN = 10
V
GMIN = 5
GMIN = 2
GMIN = 1
f = 10 kHz
RTO
Common Mode Input Voltage (V)
FIGURE 2-40:
Normalized Input Noise
Voltage Density vs. Input Common Mode
Voltage, with f = 10 kHz.
DS25073A-page 20
© 2011 Microchip Technology Inc.
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
2.4
Time Response
10
1
VDD = 5.5V
GDM = GMIN
RF + RG = 10 kꢁ
VDD = 5.5V
VDD = 1.8V
MIN
GMIN = 100
GMIN = 1 to 10
GMIN = 100
10k
100k
Frequency (Hz)
1M
1.E+6
0
2
4
6
8
10
12
14
16
18
20
1.E+4
1.E+5
Time (μs)
FIGURE 2-43:
Small Signal Step
FIGURE 2-46:
Maximum Output Voltage
Response.
Swing vs. Frequency.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
1000
VDD = 5.5V
GDM = GMIN
RF + RG = 10 kꢁ
GDMVDM = 1V
VDD = 5.5V
100
1
VDD = 1.8V
GMIN = 1 to 10
MIN = 100
G
GMIN = 100
GMIN = 10
GMIN = 1
1
10
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Time (μs)
Normalized Gain; GDM/GMIN
FIGURE 2-44:
Large Signal Step
FIGURE 2-47:
Common Mode Input
Response.
Overdrive Recovery Time vs. Normalized Gain.
10
9
8
6
5
4
3
2
1
1000
VDD = 5.5V
100
VDD = 1.8V
VDD = 5.5V
GMIN = 1 to 10
GMIN = 100
VDD = 1.8V
GMIN = 100
GMIN = 10
GMIN = 1
1
0
1
10
100
-50
-25
0
25
50
75
100
125
Normalized Gain; GDM/GMIN
Ambient Temperature (°C)
FIGURE 2-45:
Slew Rate vs. Ambient
FIGURE 2-48:
Differential Input Overdrive
Temperature.
Recovery Time vs. Normalized Gain.
© 2011 Microchip Technology Inc.
DS25073A-page 21
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
1000
100
4
3
GDM = 2GMIN
VDD = 5.5V
VIP
VREF = 0.75VDD
2
VDD = 5.5V
VDD = 1.8V
VOUT, GMIN = 1
OUT, GMIN = 100
1
GMIN = 1
GMIN = 10
V
0
-1
-2
-3
-4
GMIN = 100
VIM
1
1
10
Normalized Gain; GDM/GMIN
100
0
10 20 30 40 50 60 70 80 90 100
Time (μs)
FIGURE 2-49:
Output Overdrive Recovery
FIGURE 2-51:
The MCP6N11 Shows No
Time vs. Normalized Gain.
Phase Reversal vs. Differential Input Overdrive,
with VDD = 5.5V.
6
VDD = 5.5V
GDMVDM = +0.1V
f = 10 kHz
VCM
5
4
3
2
VOUT, GMIN = 1
VOUT, GMIN = 100
1
0
-1
0
10 20 30 40 50 60 70 80 90 100
Time (μs)
FIGURE 2-50:
The MCP6N11 Shows No
Phase Reversal vs. Common Mode Input
Overdrive, with VDD = 5.5V.
DS25073A-page 22
© 2011 Microchip Technology Inc.
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
2.5
Enable/Calibration and POR Responses
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
30
25
20
15
10
VDD = 1.8V
VL = 0V
VDD = 5.5V
VDD = 1.8V
INA
turns off
Calibration
Starts
INA
turns on
EN/CAL
VOUT
0
-50
-25
0
25
50
75
100
125
0
10 20 30 40 50 60 70 80 90 100
Time (ms)
Ambient Temperature (°C)
FIGURE 2-52:
EN/CAL and Output Voltage
FIGURE 2-55:
EN/CAL Turn On Time vs.
vs. Time, with VDD = 1.8V.
Ambient Temperature.
6.0
1.8
1.6
1.4
1.0
0.8
VDD = 5.5V
5.5
VL = 0V
VL = 0V
5.0
4.5
4.0
INA
turns off
Calibration
3.5
INA
turns on
Starts
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
0.6
0.4
0.2
0.0
-0.2
VDD
VOUT
EN/CAL
VOUT
Off
Off
Calibrating
0
10 20 30 40 50 60 70 80 90 100
Time (ms)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Time (s)
FIGURE 2-53:
EN/CAL and Output Voltage
FIGURE 2-56:
Power Supply On and Off
vs. Time, with VDD = 5.5V
and Output Voltage vs. Time.
0.60
0.55
0.50
1.7
1.6
1.5
1.4
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.05
0.00
VDD = 5.5V
VPRH – VPRL
1.3
1.2
1.1
1.0
0.9
0.8
VPRH
VDD = 1.8V
VPRL
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-57:
Hysteresis vs. Temperature.
POR Trip Voltages and
FIGURE 2-54:
Ambient Temperature.
EN/CAL Hysteresis vs.
© 2011 Microchip Technology Inc.
DS25073A-page 23
MCP6N11
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
1.E-07
100n
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
EN/CAL = 0V
VDD = 5.5V
EN/CAL = 0V
1.E-08
10n
+125°C
+85°C
1.E-09
1n
1.E-10
100p
+125°C
+25°C
-40°C
1.E-11
10p
+25°C
1.E-12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
FIGURE 2-58:
Quiescent Current in
FIGURE 2-59:
Output Leakage Current vs.
Shutdown vs. Power Supply Voltage.
Output Voltage.
DS25073A-page 24
© 2011 Microchip Technology Inc.
MCP6N11
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP6N11
PIN FUNCTION TABLE
Symbol
Description
SOIC
TDFN
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
VFG
VIM
Feedback Input
Inverting Input
VIP
Non-inverting Input
Negative Power Supply
Reference Input
Output
VSS
VREF
VOUT
VDD
Positive Power Supply
EN/CAL
EP
Enable/VOS Calibrate Digital Input
Exposed Thermal Pad (EP); must be connected to VSS
—
9
3.1
Analog Signal Inputs
3.5
Power Supply Pins
The non-inverting and inverting inputs (VIP, and VIM
are high-impedance CMOS inputs with low bias
currents.
)
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply; VDD will
need bypass capacitors.
3.2
Analog Feedback Input
The analog feedback input (VFG) is the inverting input
of the second input stage. The external feedback
components (RF and RG) are connected to this pin. It is
a high-impedance CMOS input with low bias current.
3.6
Digital Enable and V Calibration
OS
Input
3.3
Analog Reference Input
This input (EN/CAL) is a CMOS, Schmitt-triggered
input that controls the active, low power and VOS
calibration modes of operation. When this pin goes low,
the part is placed into a low power mode and the output
is high-Z. When this pin goes high, the amplifier’s input
offset voltage is corrected by the calibration circuitry,
then the output is re-connected to the VOUT pin, which
becomes low impedance, and the part resumes normal
operation.
The analog reference input (VREF) is the non-inverting
input of the second input stage; it shifts VOUT to its
desired range. The external gain resistor (RG) is
connected to this pin. It is a high-impedance CMOS
input with low bias current.
3.4
Analog Output
The analog output (VOUT) is a low-impedance voltage
output. It represents the differential input voltage
(VDM = VIP – VIM), with gain GDM and is shifted by
3.7
Exposed Thermal Pad (EP)
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be
connected to the same potential on the Printed Circuit
Board (PCB).
VREF. The external feedback resistor (RF) is connected
to this pin.
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).
© 2011 Microchip Technology Inc.
DS25073A-page 25
MCP6N11
NOTES:
DS25073A-page 26
© 2011 Microchip Technology Inc.
MCP6N11
The input offset voltage (VOS) is corrected by the
voltage VTR. Each time a VOS Calibration event occurs,
VTR is updated to the best value (at that moment).
These events are triggered by either powering up
(monitored by the POR) or by toggling the EN/CAL pin
4.0
APPLICATIONS
The MCP6N11 instrumentation amplifier (INA) is
manufactured using Microchip’s state of the art CMOS
process. It is low cost, low power and high speed,
making it ideal for battery-powered applications.
high. The current out of G
(I ) is constant and very
M3
3
small (assumed to be zero in the following discussion).
4.1
Basic Performance
The input signal is applied to GM1. Equation 4-2 shows
the relationships between the input voltages (V and
IP
4.1.1
STANDARD CIRCUIT
V
) and the common mode and differential voltages
(V and V ).
CM
IM
Figure 4-1 shows the standard circuit configuration for
these INAs. When the inputs and output are in their
specified ranges, the output voltage is approximately:
DM
EQUATION 4-2:
VIP = VCM + VDM ⁄ 2
EQUATION 4-1:
VOUT ≈ VREF + GDMVDM
VIM = VCM – VDM ⁄ 2
VCM = (VIP + VIM) ⁄ 2
VDM = VIP – VIM
Where:
GDM = 1 + RF / RG
The negative feedback loop includes GM2, RM4, RF and
RG. These blocks set the DC open-loop gain (AOL) and
the nominal differential gain (GDM):
VDD
U1
MCP6N11
VIP
VOUT
EQUATION 4-3:
RF
VIM
VFG
AOL = GM2RM4
GDM = 1 + RF ⁄ RG
RG
VREF
Standard Circuit.
AOL is very high, so I4 is very small and I + I ≈ 0. This
1
2
makes the differential inputs to GM1 and GM2 equal in
FIGURE 4-1:
magnitude and opposite in polarity. Ideally, this gives:
For normal operation, keep:
• VIP, VIM, VREF and VFG between VIVL and VIVH
• VIP – VIM (i.e., VDM) between VDML and VDMH
• VOUT between VOL and VOH
EQUATION 4-4:
(VFG – VREF) = VDM
VOUT = VDMGDM + VREF
4.1.2
ARCHITECTURE
For an ideal part, changing VCM, VSS or VDD produces
no change in VOUT. VREF shifts VOUT as needed.
Figure 4-2 shows the block diagram for these INAs.
The different GMIN options change GM1, GM2 and the
internal compensation capacitor. This results in the
performance trade-offs shown in Table 1.
VDD VSS
VOUT
VOUT
RM4
I4
RF
VFG
GM2
RG
Σ
VREF
I2
I3
VREF
VIP
I1
GM3
VTR
Low Power
VIP
VIM
GM1
POR
VIM
VOS Calibration
EN/CAL
FIGURE 4-2:
MCP6N11 Block Diagram.
© 2011 Microchip Technology Inc.
DS25073A-page 27
MCP6N11
4.1.3
DC ERRORS
EQUATION 4-6:
ΔVIP = –IBPRIP
ΔVIM = –IBMRIM
Section 1.5 “Explanation of DC Error Specs”
defines some of the DC error specifications. These
errors are internal to the INA, and can be summarized
as follows:
IOS
⎛
⎝
⎞
– IB – ------- RIP
=
⎠
2
IOS
⎛
⎞
– IB + ------- RIM
=
⎝
⎠
2
ΔVIP + ΔVIM
EQUATION 4-5:
ΔVCM = --------------------------------
2
VOUT = VREF + GDM(1 + gE)(VDM + ΔVED
+ GDM(1 + gE)(VE + ΔVE)
)
RIP + RIM
–IOS –RIP + RIM
⎛
⎞
⎛
⎞
⎠
= –IB ------------------------ + ---------- ----------------------------
⎝
⎠
⎝
2
2
2
Where:
ΔVDM = ΔVIP – ΔVIM
ΔVDD – ΔVSS ΔVCM ΔVREF
IOS
VE = VOS + --------------------------------- + ---------------- + ----------------
PSRR
CMRR CMRR
= IB(–RIP + RIM) – -------(RIP + RIM
)
2
ΔVOUT
ΔVOS
ΔVCM
+ ----------------- + ΔTA ⋅ -------------
⎛
⎞
AOL
ΔTA
ΔVOUT = GDM ΔVDM + ----------------
⎝
⎠
CMRR
ΔVED ≤ INLDM(VDMH – VDML
)
Where:
ΔVE ≤ INLCM(VIVH – VIVL
Where:
)
CMRR is in units of V/V
The best design results when RIP and RIM are equal
and small:
PSRR, CMRR and AOL are in units of V/V
ΔTA is in units of °C
EQUATION 4-7:
The non-linearity specs (INLCM and INLDM) describe
errors that are non-linear functions of VCM and VDM
,
ΔVOUT ≈ GDMΔVDM
≈ GDM(±2IBεRTOL – IOS)RIP
Where:
respectively. They give the maximum excursion from
linear response over the entire common mode and
differential ranges.
RIP = RIM
The input bias current and offset current specs (IB and
IOS), together with a circuit’s external input resistances,
give an additional DC error. Figure 4-3 shows the
resistors that set the DC bias point.
ε
RTOL = tolerance of RIP and RIM
The resistors at the feedback input (RR, RF and RG)
and its input bias currents (IBR and IBF) give the
following changes in the INA’s bias voltages:
VDD
U1
IBP
RIP
MCP6N11
EQUATION 4-8:
VIP
VIM
VOUT
IOS2
⎛
⎝
⎞
ΔVREF = –IBRRR
ΔVFG ≈ ΔVREF
=
– IB2 – ---------- RR
RF
IBF
⎠
2
RIM
due to high AOL
,
IBM
VFG
RG
IOS2
RR
ΔVOUT ≈ IB2(RF – GDMRR) + ---------- (RF + GDMRR)
IBR
2
Where:
VREF
IB2 meets the IB spec, but is not equal to IB
IOS2 meets the IOS spec, but is not equal to IOS
FIGURE 4-3:
DC Bias Resistors.
The resistors at the main input (RIP and RIM) and its
input bias currents (IBP and IBM) give the following
changes in the INA’s bias voltages:
The best design results when G RR and RF are equal
DM
and small:
EQUATION 4-9:
ΔVOUT ≈ (±(2IB2εRTOL + IOS2))RF
Where:
GDMRR = RF
ε
RTOL = tolerance of RR, RF and RG
DS25073A-page 28
© 2011 Microchip Technology Inc.
MCP6N11
4.1.4
The bandwidth of these amplifiers depends on GDM
and GMIN
AC PERFORMANCE
4.2
Functional Blocks
4.2.1
RAIL-TO-RAIL INPUTS
:
Each input stage uses one PMOS differential pair at the
input. The output of each differential pair is processed
using current mode circuitry. The inputs show no
crossover distortion vs. common mode voltage.
EQUATION 4-10:
fGBWP
fBW ≈ ---------------
GDM
With this topology, the inputs (VIP and VIM) operate
normally down to VSS – 0.2V and up to VDD + 0.15V at
room temperature (see Figure 2-11). The input offset
voltage (VOS) is measured at VCM = VSS – 0.2V and
≈ (0.50 MHz)(GMIN ⁄ GDM),
≈ (0.35 MHz)(GMIN ⁄ GDM),
Where:
fBW = -3 dB bandwidth
GMIN = 1, …, 10
GMIN = 100
VDD + 0.15V (at +25°C), to ensure proper operation.
fGBWP = Gain bandwidth product
4.2.1.1 Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figures 2-18 and 2-50 show an input voltage
exceeding both supplies with no phase inversion.
The bandwidth at the maximum output swing is called
the Full Power Bandwidth (fFPBW). It is limited by the
Slew Rate (SR) for many amplifiers, but is close to fBW
for these parts:
The input devices also do not exhibit phase inversion
when the differential input voltage exceeds its limits;
see Figures 2-22 and 2-51.
EQUATION 4-11:
SR
fFPBW ≈ ----------
πVO
4.2.1.2
Input Voltage Limits
,
for these parts
≈ fBW
Where:
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”). This requirement is independent of the
current limits discussed later on.
VO = Maximum output voltage swing
≈ VOH – VOL
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize input bias
current (IB).
CMRR is constant from DC to about 1 kHz.
4.1.5
NOISE PERFORMANCE
As shown in Figures 2-41 and 2-42, the 1/f noise
causes an apparent wander in the DC output voltage.
Changing the measurement time or bandwidth has little
effect on this noise.
Bond
VDD
Pad
We recommend re-calibrating VOS periodically, to
reduce 1/f noise wander. For example, VOS could be
re-calibrated at least once every 15 minutes; more
often when temperature or VDD change significantly.
Bond
Pad
Bond
Pad
Input
Stage
of
VIP
VIM
INA Input
Bond
Pad
VSS
FIGURE 4-4:
Simplified Analog Input ESD
Structures.
© 2011 Microchip Technology Inc.
DS25073A-page 29
MCP6N11
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go too far above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
overvoltage (beyond VDD) events. Very fast ESD
events (that meet the spec) are limited so that damage
does not occur.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIP and VIM
)
should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-25.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs.
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode-
connected FETs for low leakage.
4.2.1.4
Input Voltage Ranges
Figure 4-7 shows possible input voltage values
(VSS = 0V). Lines with a slope of +1 have constant VDM
(e.g., the VDM = 0 line). Lines with a slope of -1 have
constant VCM (e.g., the VCM = VDD/2 line).
VDD
For normal operation, VIP and VIM must be kept within
the region surrounded by the thick blue lines. The
horizontal and vertical blue lines show the limits on the
individual inputs. The blue lines with a slope of +1 show
the limits on VDM; the larger GMIN is, the closer they are
to the VDM = 0 line.
U1
D1
MCP6N11
V1
D2
V2
The input voltage range specs (VIVL and VIVH) change
with the supply voltages (VSS and VDD, respectively).
FIGURE 4-5:
Protecting the Analog Inputs
The differential input range specs (VDML and VDMH
)
Against High Voltages.
change with minimum gain (GMIN). Temperature also
affects these specs.
4.2.1.3
Input Current Limits
To take full advantage of VDML and VDMH, set VREF
(see Figure 1-6 and Figure 1-7) so that the output
(VOUT) is centered between the supplies (VSS and
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute Maxi-
mum Ratings †”). This requirement is independent of
the voltage limits previously discussed.
VDD).
VIP
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
VIVH
VDD
The diode currents will dump onto VDD
.
VDD
U1
D1
R1
MCP6N11
V1
V2
D2
VIM
R2
0
VIVL
VSS – min(V1, V2)
min(R1, R2) >
2 mA
max(V1, V2) – VDD
min(R1, R2) >
FIGURE 4-7:
Input Voltage Ranges.
2 mA
FIGURE 4-6:
Protecting the Analog Inputs
Against High Currents.
DS25073A-page 30
© 2011 Microchip Technology Inc.
MCP6N11
4.2.2
ENABLE/VOS CALIBRATION
(EN/CAL)
4.3
Applications Tips
4.3.1
MINIMUM STABLE GAIN
These parts have a Normal mode, a Low Power mode
and a VOS Calibration mode.
There are different options for different Minimum Stable
Gains (1, 2, 5, 10 and 100 V/V; see Table 1-1). The
differential gain (GDM) needs to be greater than or
equal to GMIN in order to maintain stability.
When the EN/CAL pin is high and the internal POR
(with delay) indicates that power is good, the part
operates in its Normal mode.
Picking a part with higher GMIN has the advantages of
lower Input Noise Voltage Density (eni), lower Input
Offset Voltage (VOS) and increased Gain Bandwidth
Product (GBWP); see Table 1. The Differential Input
Voltage Range (VDMR) is lower for higher GMIN, but the
output voltage range would limit VDMR anyway, when
GDM ≥ 2.
When the EN/CAL pin is low, the part operates in its
Low Power mode. The quiescent current (at VSS) drops
to -2.5 µA (typical), the amplifier output is put into a
high-impedance state. Signals at the input pins can
feed through to the output pin.
When the EN/CAL pin goes high and the internal POR
(with delay) indicates that power is good, the amplifier
internally corrects its input offset voltage (VOS) with the
internal common mode voltage at mid-supply (VDD/2)
and the output tri-stated (after tOFF). Once VOS Calibra-
tion is completed, the amplifier is enabled and normal
operation resumes.
4.3.2
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for amplifiers. As the load capacitance
increases, the feedback loop’s phase margin
decreases, and the closed-loop bandwidth is reduced.
This produces gain peaking in the frequency response,
with overshoot and ringing in the step response. Lower
gains (GDM) exhibit greater sensitivity to capacitive
loads.
The EN/CAL pin does not operate normally when left
floating. Either drive it with a logic output, or tie it high
so that the part is always on.
4.2.3
POR WITH DELAY
When driving large capacitive loads with these
instrumentation amps (e.g., > 100 pF), a small series
resistor at the output (RISO in Figure 4-8) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
The internal POR makes sure that the input offset
voltage (VOS) is calibrated whenever the supply
voltage goes from low voltage (< VPRL) to high voltage
(> VPRH). This prevents corruption of the VOS trim reg-
isters after a low-power event.
After the POR goes high, the internal circuitry adds a
fixed delay (tPLH), before telling the VOS Calibration
circuitry (see Figure 4-2) to start. If the EN/CAL pin is
toggled during this time, the fixed delay is restarted
(takes an additional time tPLH).
U1
VDD
MCP6N11
RISO
CL
V1
V2
VOUT
4.2.4
PARITY DETECTOR
RF
A parity error detector monitors the memory contents
for any corruption. In the rare event that a parity error is
detected (e.g., corruption from an alpha particle), a
POR event is automatically triggered. This will cause
the input offset voltage to be re-corrected, and the op
amp will not return to normal operation for a period of
time (the POR turn on time, tPLH).
VFG
RG
VREF
FIGURE 4-8:
Output Resistor, RISO
stabilizes large capacitive loads.
4.2.5
RAIL-TO-RAIL OUTPUT
Figure 4-9 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL GMIN/GDM), where
GDM is the circuit’s differential gain (1 + RF / RG) and
The Minimum Output Voltage (VOL) and Maximum
Output Voltage (VOH) specs describe the widest output
swing that can be achieved under the specified load
conditions.
GMIN is the minimum stable gain.
The output can also be limited when VIP or VIM exceeds
VIVL or VIVH, or when VDM exceeds VDML or VDMH.
© 2011 Microchip Technology Inc.
DS25073A-page 31
MCP6N11
In this data sheet, RF + RG = 10 kΩ for most gains (0Ω
for GDM = 1); see Table 1-6. This choice gives good
Phase Margin. In general, RF (Figure 4-10) needs to
meet the following limits to maintain stability:
1.E10k
EQUATION 4-12:
For GDM = 1:
RF = 0
1.E+
1k
GMIN = 1 to 10
GMIN = 100
1.E
100
For GDM > 1:
100p
1n
1.9
10n
18
100n
1
1μ
1.6
Normalized Load Capacitance;
CL GMIN/GDM (F)
αG2DM
RF < ------------------------------
2πfGBWPCG
FIGURE 4-9:
Recommended RISO Values
for Capacitive Loads.
Where:
α ≤ 0.25
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot on the bench. Modify RISO’s value
until the response is reasonable.
GDM ≥ GMIN
fGBWP = Gain Bandwidth Product
CG = CDM + CCM + (PCB stray capacitance)
4.3.3
GAIN RESISTORS
Figure 4-10 shows a simple gain circuit with the INA’s
input capacitances at the feedback inputs (VREF and
VFG). These capacitances interact with RG and RF to
modify the gain at high frequencies. The equivalent
capacitance acting in parallel to RG is CG = CDM + CCM
plus any board capacitance in parallel to RG. CG will
cause an increase in GDM at high frequencies, which
reduces the phase margin of the feedback loop (i.e.,
reduce the feedback loop's stability).
4.3.4
SUPPLY BYPASS
With these INAs, the power supply pin (VDD for single
supply) should have a local bypass capacitor (i.e.,
0.01 µF to 0.1 µF) within 2 mm for good high frequency
performance. Surface mount, multilayer ceramic
capacitors, or their equivalent, should be used.
These INAs require a bulk capacitor (i.e., 1.0 µF or
larger) within 100 mm, to provide large, slow currents.
This bulk capacitor can be shared with other nearby
analog parts as long as crosstalk through the supplies
does not prove to be a problem.
VDD
U1
V1
V2
MCP6N11
VOUT
RF
VFG
CCM
CDM
CCM
RG
VREF
FIGURE 4-10:
Simple Gain Circuit with
Parasitic Capacitances.
DS25073A-page 32
© 2011 Microchip Technology Inc.
MCP6N11
4.4.3
HIGH SIDE CURRENT DETECTOR
4.4
Typical Applications
Figure 4-13 shows the MCP6N11 INA used as to detect
and amplify the high side current in a battery powered
design. The INA gain is set at 21 V/V, so VOUT changes
210 mV for every 1 mA of IDD current. The best GMIN
option to pick would be a gain of 10 (MCP6N11-010).
4.4.1
HIGH INPUT IMPEDANCE
DIFFERENCE AMPLIFIER
Figure 4-11 shows the MCP6N11 used as a difference
amplifier. The inputs are high impedance and give good
CMRR performance.
VBAT
10 Ω
VDD
U1
+1.8V
to
+5.5V
IDD
VDD
U1
MCP6N11
VIP
MCP6N11
VOUT
VOUT
RF
VIM
RF
200 kΩ
VFG
VFG
RG
RG
VREF
Difference Amplifier.
10 kΩ
VREF
FIGURE 4-11:
(VBAT – VDD
)
IDD
=
=
4.4.2
DIFFERENCE AMPLIFIER FOR
VERY LARGE COMMON MODE
SIGNALS
(10 Ω)
(VOUT – VREF
(10 Ω) (21.0 V/V)
)
Figure 4-12 shows the MCP6N11 INA used as a
difference amplifier for signals with a very large
common mode component. The input resistor dividers
(R1 and R2) ensure that the voltages at the INA’s inputs
are within their range of normal operation. The
capacitors C1, with the parasitic capacitances C2 (the
resistors’ parasitic capacitance plus the INA’s input
common mode capacitance, CCM), set the same
division ratio, so that high-frequency signals (e.g., a
step in voltage) have the same gain. Select the INA
gain to compensate for R1 and R2’s attenuation. Select
R1 and R2’s tolerances for good CMRR.
FIGURE 4-13:
High Side Current Detector.
4.4.4
WHEATSTONE BRIDGE
shows the MCP6N11
Figure 4-14
single
instrumentation amp used to condition the signal from
a Wheatstone bridge (e.g., strain gage). The overall
INA gain is set at 201 V/V. The best GMIN option to pick,
for this gain, is 100 V/V (MCP6N11-100).
VDD
U1
RW1
RW2
R1
C1
R2
C2
MCP6N11
V1
VOUT
RW2
RW1
RF
VDD
U1
200 kΩ
VFG
MCP6N11
RG
1 kΩ
VOUT
RF
VREF
VFG
FIGURE 4-14:
Amplifier.
Wheatstone Bridge
C1
R1
C2
R2
RG
V2
VREF
FIGURE 4-12:
Difference Amplifier with
Very Large Common Mode Component.
© 2011 Microchip Technology Inc.
DS25073A-page 33
MCP6N11
NOTES:
DS25073A-page 34
© 2011 Microchip Technology Inc.
MCP6N11
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6N11 instrumentation amplifiers.
5.1
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit particular design
a
requirement. Available at no cost from the Microchip
website at www.microchip.com/maps, the MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a customer can define a filter to sort features
for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for Data sheets, Purchase and
Sampling of Microchip parts.
5.2
Analog Demonstration Board
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time
to market. For a complete listing of these boards
and their corresponding user’s guides and technical
information, visit the Microchip web site at
www.microchip.com/analog tools.
5.3
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
Some of these application notes, and others, are listed
in the design guide:
• “Signal Chain Design Guide”, DS21825
© 2011 Microchip Technology Inc.
DS25073A-page 35
MCP6N11
NOTES:
DS25073A-page 36
© 2011 Microchip Technology Inc.
MCP6N11
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
8-Lead SOIC (150 mil) (MCP6N11)
Example
6N11001E
SN^
e
^
3
1121
256
NNN
Note:
The example is for
MCP6N11-001 part.
a
8-Lead TDFN (2×3) (MCP6N11)
Example
Device
Code
MCP6N11-001
MCP6N11-002
MCP6N11-005
MCP6N11-010
MCP6N11-100
AAQ
AAR
AAS
AAT
AAU
AAQ
121
25
Note:
Applies to 8-Lead 2x3 TDFN
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2011 Microchip Technology Inc.
DS25073A-page 37
MCP6N11
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS25073A-page 38
© 2011 Microchip Technology Inc.
MCP6N11
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2011 Microchip Technology Inc.
DS25073A-page 39
MCP6N11
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢍꢓꢔꢆꢕꢆꢓꢄꢖꢖꢗꢘꢙꢆꢚꢛꢜꢝꢆꢎꢎꢆꢞꢗꢅꢟꢆꢠꢍꢏꢡꢢꢣ
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ
DS25073A-page 40
© 2011 Microchip Technology Inc.
MCP6N11
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2011 Microchip Technology Inc.
DS25073A-page 41
MCP6N11
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS25073A-page 42
© 2011 Microchip Technology Inc.
MCP6N11
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢥꢐꢄꢈꢆꢦꢈꢄꢊꢙꢆꢓꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌꢧꢄꢨꢃꢆꢒꢩꢓꢔꢆꢕꢆꢪꢫꢚꢫꢝꢛꢬꢭꢆꢎꢎꢆꢞꢗꢅꢟꢆꢠꢮꢥꢦꢓꢣ
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ
© 2011 Microchip Technology Inc.
DS25073A-page 43
MCP6N11
NOTES:
DS25073A-page 44
© 2011 Microchip Technology Inc.
MCP6N11
APPENDIX A: REVISION HISTORY
Revision A (October 2011)
• Original Release of this Document.
© 2011 Microchip Technology Inc.
DS25073A-page 45
MCP6N11
NOTES:
DS25073A-page 46
© 2011 Microchip Technology Inc.
MCP6N11
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
–X
X
/XX
Examples:
a)
b)
MCP6N11T-001E/MNY: Tape and Reel,
Gain
Option
Temperature
Range
Package
Minimum gain = 1,
Extended temperature,
8LD 2×3 TDFN.
MCP6N11-002E/SN:
Minimum gain = 2,
Extended temperature,
8LD SOIC.
Device:
MCP6N11
Single Instrumentation Amplifier
MCP6N11T Single Instrumentation Amplifier
(Tape and Reel)
Gain Option:
001 = Minimum gain of 1 V/V
002 = Minimum gain of 2 V/V
005 = Minimum gain of 5 V/V
010 = Minimum gain of 10 V/V
100 = Minimum gain of 100 V/V
Temperature Range:
Package:
E
= -40°C to +125°C
MNY
SN
=
=
2×3 TDFN, 8-lead *
Plastic SOIC (150mil Body), 8-lead
* Y = nickel palladium gold manufacturing designator. Only
available on the TDFN package.
© 2011 Microchip Technology Inc.
DS25073A-page 47
MCP6N11
NOTES:
DS25073A-page 48
© 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-685-3
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2011 Microchip Technology Inc.
DS25073A-page 49
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Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
Los Angeles
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
08/02/11
DS25073A-page 50
© 2011 Microchip Technology Inc.
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