MCP6S92-E/MS [MICROCHIP]
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| 型号： | MCP6S92-E/MS |
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MICROCHIP |
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MCP6S91/2/3
Single-Ended, Rail-to-Rail I/O, Low-Gain PGA
Description
Features
• Multiplexed Inputs: 1 or 2 channels
• 8 Gain Selections:
The Microchip Technology Inc. MCP6S91/2/3 are
analog Programmable Gain Amplifiers (PGAs). They
can be configured for gains from +1 V/V to +32 V/V and
the input multiplexer can select one of up to two chan-
nels through a SPI port. The serial interface can also
put the PGA into shutdown to conserve power. These
PGAs are optimized for high-speed, low offset voltage
and single-supply operation with rail-to-rail input and
output capability. These specifications support single-
supply applications needing flexible performance or
multiple inputs.
- +1, +2, +4, +5, +8, +10, +16 or +32 V/V
• Serial Peripheral Interface (SPI™)
• Rail-to-Rail Input and Output
• Low Gain Error: ±1% (max.)
• Offset Mismatch Between Channels: 0 µV
• High Bandwidth: 1 to 18 MHz (typ.)
• Low Noise: 10 nV/√Hz @ 10 kHz (typ.)
• Low Supply Current: 1.0 mA (typ.)
• Single Supply: 2.5V to 5.5V
The one-channel MCP6S91 and the two-channel
MCP6S92 are available in 8-pin PDIP, SOIC and MSOP
packages. The two-channel MCP6S93 is available in a
10-pin MSOP package. All parts are fully specified from
-40°C to +125°C.
• Extended Temperature Range: -40°C to +125°C
Typical Applications
• A/D Converter Driver
• Multiplexed Analog Applications
• Data Acquisition
Package Types
MCP6S91
PDIP, SOIC, MSOP
MCP6S93
MSOP
• Industrial Instrumentation
• Test Equipment
V
1
V
DD
8
7
OUT
V
OUT
V
1
10
9
DD
SCK
• Medical Instrumentation
CH0 2
CH0
CH1
2
3
4
5
SCK
SO
SI
V
3
4
6 SI
REF
8
Block Diagram
V
5 CS
SS
V
7
REF
V
6
CS
VDD
SS
MCP6S92
PDIP, SOIC, MSOP
CH0
V
1
V
DD
8
7
OUT
MUX
CH1
VOUT
SCK
CH0 2
CH1
3
4
6 SI
5
CS
SI
SPI™
Logic
V
SS
CS
SO
RF
SCK
8
Gain
Switches
RG
VREF
VSS
2004 Microchip Technology Inc.
DS21908A-page 1
MCP6S91/2/3
1.0
ELECTRICAL
PIN FUNCTION TABLE
CHARACTERISTICS
Name
Function
VOUT
Analog Output
Absolute Maximum Ratings †
CH0, CH1 Analog Inputs
V
– V ........................................................................7.0V
SS
DD
VREF
VSS
External Reference Pin
Negative Power Supply
SPI Chip Select
All inputs and outputs..................... V – 0.3V to V + 0.3V
SS
DD
Difference Input voltage ....................................... |V – V
|
SS
DD
CS
SI
Output Short Circuit Current ..................................continuous
Current at Input Pin .............................................................±2 mA
Current at Output and Supply Pins................................ ±30 mA
Storage temperature .....................................-65°C to +150°C
Junction temperature ..................................................+150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 200V
SPI Serial Data Input
SPI Serial Data Output
SPI Clock Input
SO
SCK
VDD
Positive Power Supply
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V , G = +1 V/V,
SS
A
DD
SS
REF
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R = 10 kΩ to V /2, SI and SCK are tied low and CS is tied high.
L
DD
Parameters
Amplifier Inputs (CH0, CH1)
Input Offset Voltage
Sym
Min
Typ
Max
Units
Conditions
V
-4
—
—
70
—
—
—
—
—
0
+4
—
—
—
—
—
—
—
mV
µV
G = +1
Between inputs (CH0, CH1)
= -40°C to +125°C
OS
Input Offset Voltage Mismatch
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Bias Current
∆V
OS
∆V /∆T
±1.8
90
µV/°C
dB
T
A
OS
A
PSRR
G = +1 (Note 1)
CHx = V /2
I
I
I
±1
pA
B
B
B
DD
Input Bias Current at
Temperature
30
pA
CHx = V /2, T = +85°C
DD A
600
pA
CHx = V /2, T = +125°C
DD A
13
Input Impedance
Z
10 ||7
Ω||pF
V
IN
Input Voltage Range
V
V
− 0.3
—
V + 0.3
DD
(Note 2)
IVR
SS
Reference Input (V
Input Impedance
Voltage Range
Amplifier Gain
Nominal Gains
DC Gain Error
)
REF
Z
—
(5/G)||6
—
—
kΩ||pF
IN_REF
V
V
V
DD
V
(Note 2)
IVR_REF
SS
G
—
-0.2
-1.0
—
1 to 32
—
—
+0.2
+1.0
—
V/V
%
+1, +2, +4, +5, +8, +10, +16 or +32
G = +1
G ≥ +2
G = +1
G ≥ +2
g
g
V
V
≈ 0.3V to V − 0.3V
DD
E
E
OUT
OUT
—
%
≈ 0.3V to V − 0.3V
DD
DC Gain Drift
∆G/∆T
±0.0002
±0.0004
%/°C
%/°C
T
= -40°C to +125°C
T = -40°C to +125°C
A
A
A
∆G/∆T
—
—
A
Note 1:
R
(R +R in Figure 4-1) connects V
, V
and the inverting input of the internal amplifier. The MCP6S92 has
LAD
F
G
REF OUT
V
tied internally to V , so V is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is
REF
SS SS
recommended that the MCP6S92’s V pin be tied directly to ground to avoid noise problems.
SS
2: The MCP6S92’s V
and V
are not tested in production; they are set by design and characterization.
IVR
IVR_REF
3:
I
includes current in R
(typically 60 µA at V
= 0.3V). Both I and I
exclude digital switching currents.
Q_SHDN
Q
LAD
OUT
Q
2004 Microchip Technology Inc.
DS21908A-page 2
MCP6S91/2/3
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V , G = +1 V/V,
SS
A
DD
SS
REF
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R = 10 kΩ to V /2, SI and SCK are tied low and CS is tied high.
L
DD
Parameters
Ladder Resistance
Ladder Resistance
Sym
Min
Typ
Max
Units
Conditions
R
3.4
—
4.9
6.4
—
kΩ
(Note 1)
= -40°C to +125°C (Note 1)
LAD
Ladder Resistance across
Temperature
∆R
/∆T
+0.028
%/°C
T
A
LAD
A
Amplifier Output
DC Output Non-linearity G = +1
G ≥ +2
V
—
—
±0.18
±0.050
—
—
—
% of FSR
% of FSR
mV
V
V
≈ 0.3V to V − 0.3V, V = 5.0V
DD DD
ONL
OUT
OUT
V
≈ 0.3V to V − 0.3V, V = 5.0V
DD DD
ONL
Maximum Output Voltage Swing
V
V
,
V
V
+ 20
V – 100
DD
G ≥ +2; 0.5V output overdrive
G ≥ +2; 0.5V output overdrive,
OH_ANA
SS
SS
OL_ANA
+ 60
—
V
– 60
DD
V
= V /2
DD
REF
Short Circuit Current
Power Supply
I
—
±25
—
mA
SC
Supply Voltage
V
2.5
—
—
0.4
1.0
30
5.5
2.0
1.6
—
V
V
DD
Minimum Valid Supply Voltage
Quiescent Current
V
Register data still valid
DD_VAL
I
0.4
—
mA
pA
I
I
= 0 (Note 3)
= 0 (Note 3)
Q
O
O
Quiescent Current, Shutdown
Mode
I
Q_SHDN
Note 1:
R
(R +R in Figure 4-1) connects V
, V
and the inverting input of the internal amplifier. The MCP6S92 has
LAD
F
G
REF OUT
V
tied internally to V , so V is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is
REF
SS SS
recommended that the MCP6S92’s V pin be tied directly to ground to avoid noise problems.
SS
2: The MCP6S92’s V
and V are not tested in production; they are set by design and characterization.
IVR_REF
IVR
3:
I
includes current in R
(typically 60 µA at V
= 0.3V). Both I and I
exclude digital switching currents.
Q_SHDN
Q
LAD
OUT
Q
2004 Microchip Technology Inc.
DS21908A-page 3
MCP6S91/2/3
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V , G = +1 V/V,
SS
A
DD
SS
REF
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R = 10 kΩ to V /2, C = 60 pF, SI and SCK are tied low and CS is tied high.
L
DD
L
Parameters
Frequency Response
-3 dB Bandwidth
Sym
Min
Typ
Max Units
Conditions
BW
—
—
1 to 18
0
—
—
MHz All gains; V
< 100 mV
< 100 mV
(Note 1)
OUT
OUT
P-P
P-P
Gain Peaking
GPK
dB
All gains; V
Total Harmonic Distortion plus Noise
f = 20 kHz, G = +1 V/V THD+N
f = 20 kHz, G = +1 V/V THD+N
f = 20 kHz, G = +4 V/V THD+N
f = 20 kHz, G = +16 V/V THD+N
—
—
—
—
0.0011
0.0089
0.0045
0.028
—
—
—
—
%
%
%
%
V
= 1.5V ± 1.0 V , V = 5.0V,
OUT PK DD
BW = 80 kHz, R = 10 kΩ to 1.5V
L
V
= 2.5V ± 1.0 V , V = 5.0V,
PK DD
OUT
BW = 80 kHz
V
= 2.5V ± 1.0 V , V = 5.0V,
OUT
PK
DD
BW = 80 kHz
V
= 2.5V ± 1.0 V , V = 5.0V,
OUT
PK
DD
BW = 80 kHz
Step Response
Slew Rate
SR
—
—
—
4.0
11
—
—
—
V/µs G = 1, 2
V/µs G = 4, 5, 8, 10
V/µs G = 16, 32
22
Noise
Input Noise Voltage
E
—
—
—
—
4.5
30
10
4
—
—
—
—
µV
f = 0.1 Hz to 10 Hz (Note 2)
f = 0.1 Hz to 200 kHz (Note 2)
ni
P-P
Input Noise Voltage Density
Input Noise Current Density
e
nV/√Hz f = 10 kHz (Note 2)
fA/√Hz f = 10 kHz
ni
i
ni
Note 1: See Table 4-1 for a list of typical numbers and Figure 2-25 for the frequency response versus gain.
2: and e include ladder resistance noise. See Figure 2-12 for e versus G data.
E
ni
ni
ni
2004 Microchip Technology Inc.
DS21908A-page 4
MCP6S91/2/3
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = 25°C, V = +2.5V to +5.5V, V = GND, V
= V , G = +1 V/V,
SS
A
DD
SS
REF
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R = 10 kΩ to V /2, C = 60 pF, SI and SCK are tied low and CS is tied high.
L
DD
L
Parameters
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
Sym
Min
Typ
Max Units
Conditions
V
0
—
—
—
—
0.3V
V
µA
V
IL
DD
Input Leakage Current
Logic Threshold, High
Amplifier Output Leakage Current
SPI Output (SO, for MCP6S93)
Logic Threshold, Low
I
-1.0
+1.0
IL
V
0.7 V
V
DD
IH
DD
—
-1.0
1.0
µA
In Shutdown mode
V
V
—
—
V
+0.4
V
V
I
I
= 2.1 mA, V = 5V
OL_DIG
SS
SS
OL
DD
Logic Threshold, High
SPI Timing
V
V
– 0.5
V
= -400 µA
OH_DIG
DD
DD
OH
Pin Capacitance
C
—
10
—
5
—
pF
µs
ns
ns
All digital I/O pins
(Note 1)
PIN
Input Rise/Fall Times (CS, SI, SCK)
Output Rise/Fall Times (SO)
CS High Time
t
—
—
2
RFI
t
t
—
—
—
—
10
—
—
—
—
—
—
80
80
MCP6S93
RFO
CSH
40
10
40
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK Edge to CS Fall Setup Time
CS Fall to First SCK Edge Setup Time
SCK Frequency
t
ns
SCK edge when CS is high
CS0
t
ns
CSSC
f
MHz
ns
V
= 5V (Note 2)
DD
SCK
SCK High Time
t
40
40
30
100
40
10
—
HI
SCK Low Time
t
ns
LO
SCK Last Edge to CS Rise Setup Time
CS Rise to SCK Edge Setup Time
SI Setup Time
t
ns
SCCS
t
ns
SCK edge when CS is high
CS1
t
ns
SU
HD
DO
SI Hold Time
t
ns
SCK to SO Valid Propagation Delay
CS Rise to SO Forced to Zero
Channel and Gain Select Timing
Channel Select Time
t
ns
MCP6S93
MCP6S93
t
—
ns
SOZ
t
—
—
1.5
1
—
—
µs
µs
CHx = 0.6V, CHy = 0.3V, G = 1,
CHx to CHy select,
CH
CS = 0.7 V to V
90% point
DD
OUT
Gain Select Time
t
CHx = CHy = 0.3V,
G
G = 5 to G = 1 select,
CS = 0.7 V to V
90% point
DD
OUT
Shutdown Mode Timing
Out of Shutdown mode (CS goes high)
to Amplifier Output Turn-on Time
t
—
—
3.5
1.5
10
—
µs
µs
CS = 0.7 V to V
90% point
90% point
ON
DD
OUT
OUT
Into Shutdown mode (CS goes high) to
Amplifier Output High-Z Turn-off Time
t
CS = 0.7 V to V
DD
OFF
Note 1: Not tested in production. Set by design and characterization.
2: When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (t ≤ 80 ns), data input set-up time (t ≥ 40 ns), SCK high time (t ≥ 40 ns) and SCK rise and
DO
SU
HI
fall times of 5 ns. Maximum f
is therefore ≈ 5.8 MHz.
SCK
2004 Microchip Technology Inc.
DS21908A-page 5
MCP6S91/2/3
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 10L-MSOP
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
(Note 1)
θJA
θJA
θJA
θJA
—
—
—
—
85
—
—
—
—
°C/W
°C/W
°C/W
°C/W
163
206
143
Note 1: Operation in this range must not cause TJ to exceed Maximum Junction Temperature (+150°C).
2004 Microchip Technology Inc.
DS21908A-page 6
MCP6S91/2/3
CS
CS
tCH
tG
0.6V
1.5V
0.3V
VOUT
VOUT
0.3V
FIGURE 1-1:
Channel Select Timing
FIGURE 1-3:
Gain Select Timing
Diagram.
Diagram.
CS
tON
tOFF
Hi-Z
Hi-Z
VOUT
0.3V
1.0 mA (typ.)
ISS
30 pA (typ.)
FIGURE 1-2:
PGA Shutdown Timing
Diagram (must enter correct commands before
CS goes high).
tCSH
CS
tCSSC
tSCCS tCS1
tCS0
tLO tHI
SCK
SI
1/fSCK
tHD
tSU
tSOZ
tDO
SO
(first 16 bits out are always zeros)
Detailed SPI™ Serial Interface Timing; SPI 0,0 Mode.
FIGURE 1-4:
2004 Microchip Technology Inc.
DS21908A-page 7
MCP6S91/2/3
tCSH
CS
SCK
SI
tCSSC
tSCCS tCS1
tCS0
tHI tLO
1/fSCK
tSU tHD
tSOZ
tDO
SO
(first 16 bits out are always zeros)
Detailed SPI™ Serial Interface Timing; SPI 1,1 Mode.
FIGURE 1-5:
The end points of this line are at VO_ID = 0.3V and
VDD – 0.3V. Figure 1-6 shows the relationship between
the gain and offset specifications referred to in the
electrical specifications as follows:
1.1
DC Output Voltage Specs / Model
IDEAL MODEL
1.1.1
The ideal PGA output voltage (VOUT) is:
EQUATION 1-3:
EQUATION 1-1:
V2 – V1
-------------------------------------
gE = 100%
VO_ID = GVIN
VREF = VSS = 0V
G(VDD – 0.6V)
Where:
V1
------------------------
VOS
=
G = +1
G(1 + gE)
G is the nominal gain
(see Figure 1-6). This equation holds when there are
no gain or offset errors and when the VREF pin is tied to
a low-impedance source (<< 0.1Ω) at ground potential
(VSS = 0V).
The DC Gain Drift (∆G/∆TA) can be calculated from the
change in gE across temperature. This is shown in the
following equation:
EQUATION 1-4:
1.1.2
LINEAR MODEL
∆gE
The PGA’s linear region of operation, including offset
and gain errors, is modeled by the line VO_LIN shown in
Figure 1-6.
---------
=
∆G ⁄ ∆TA
∆TA
EQUATION 1-2:
0.3V
G
----------
VO_LIN = G(1 + gE) VIN
–
+ VOS + 0.3V
VREF = VSS = 0V
2004 Microchip Technology Inc.
DS21908A-page 8
MCP6S91/2/3
1.1.4
DIFFERENT VREF CONDITIONS
VOUT (V)
Some of the plots in Section 2.0 “Typical Performance
Curves”, have the conditions VREF = VDD/2 or
VREF = VDD. The equations and figures above are easily
modified for these conditions. The ideal VOUT equation
becomes:
VDD
V2
VDD – 0.3
EQUATION 1-7:
VO_ID = VREF + G(VIN – VREF
VDD ≥ VREF > VSS = 0V
)
V1
VIN (V)
The complete linear model is:
EQUATION 1-8:
0.3
0
0.3
G
VDD – 0.3 VDD
0
VON_LIN = G(1 + gE)(VIN – VIN_L + VOS) + 0.3V
VREF = VSS = 0V
G
G
FIGURE 1-6:
Output Voltage Model with
the standard condition VREF = VSS = 0V.
where the new VIN end points are:
1.1.3 OUTPUT NON-LINEARITY
Figure 1-7 shows the Integral Non-Linearity (INL) of the
output voltage.
EQUATION 1-9:
0.3V – VREF
------------------------------
+ VREF
VIN_L
=
G
EQUATION 1-5:
VDD – 0.3V – VREF
-----------------------------------------------
G
INL = VOUT – VO_LIN
VIN_H
=
+ VREF
The output non-linearity specification in the Electrical
Specifications (with units of: % of FSR) is related to
Figure 1-7 by:
The equations for extracting the specifications do not
change.
EQUATION 1-6:
max(V3, V4)
------------------------------
100%
VONL
=
V
DD – 0.6V
The Full-Scale Range (FSR) is VDD – 0.6V
(0.3V to VDD – 0.3V).
INL (V)
V4
0
V3
VIN (V)
0.3
G
VDD – 0.3 VDD
0
G
G
FIGURE 1-7:
Output Voltage INL with the
standard condition VREF = VSS = 0 V.
2004 Microchip Technology Inc.
DS21908A-page 9
MCP6S91/2/3
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
35%
30%
25%
20%
15%
10%
5%
24%
22%
600 Samples
G = +1
TA = -40 to +125°C
600 Samples
20% G = +1
18%
16%
14%
12%
10%
8%
6%
4%
0%
2%
0%
DC Gain Error (%)
DC Gain Drift (%/°C)
FIGURE 2-1:
DC Gain Error, G = +1.
FIGURE 2-4:
DC Gain Drift, G = +1.
18%
26%
600 Samples
G ≥ +2
600 Samples
G ≥ +2
TA = -40 to +125°C
24%
22%
20%
18%
16%
14%
12%
10%
8%
16%
14%
12%
10%
8%
6%
6%
4%
4%
2%
0%
2%
0%
DC Gain Drift (%/°C)
DC Gain Error (%)
FIGURE 2-2:
DC Gain Error, G ≥ +2.
FIGURE 2-5:
DC Gain Drift, G ≥ +2.
-10
16%
VDD = 5.0V
G = +32 V/V
CH0 selected
597 Samples
A = -40 to +125°C
RS = 10 kΩ
14%
12%
10%
8%
-20
-30
-40
-50
-60
-70
-80
-90
-100
T
RS = 1 kΩ
6%
4%
RS = 100 Ω
2%
0%
RS = 0 Ω
1.E+05
1.E+06
1.E+07
1.E+08
100k
1M
10M
100M
Ladder Resistance Drift (%/°C)
Frequency (Hz)
FIGURE 2-3:
Ladder Resistance Drift.
FIGURE 2-6:
Crosstalk vs. Frequency
(circuit in Figure 6-4).
2004 Microchip Technology Inc.
DS21908A-page 10
MCP6S91/2/3
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
30%
25%
20%
15%
10%
5%
24%
22%
20%
18%
16%
14%
12%
10%
8%
600 Samples
G = +1
VDD = 4.0V
600 Samples
TA = -40 to +125°C
G = +1
6%
4%
2%
0%
0%
-3
-2
-1
0
1
2
3
Input Offset Voltage (mV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-7:
Input Offset Voltage,
FIGURE 2-10:
Input Offset Voltage Drift.
VDD = 4.0V.
35%
3.0
2.5
2.0
1.5
1.0
32 Samples
DD = 5.5V
VIN = 0.3V
G = +1
IN = VREF
σ = 10.0 µVRMS
30%
25%
20%
15%
10%
5%
V
V
Measurement
Repeatability:
10.4 µVRMS
VDD = 5.5V
0.5
0.0
VDD = 2.5V
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VREF Voltage (V)
Input Offset Voltage Mismatch (µV)
FIGURE 2-8:
Input Offset Voltage
FIGURE 2-11:
Input Offset Voltage vs.
Mismatch.
VREF Voltage.
1000
100
10
13
12
11
10
9
8
7
6
5
f = 10 kHz
4
3
2
1
0
0.1
1
10
100
1000
10000
100000
1
1
2
4
5
8
10
16
32
0.1
1
10 100
Frequency (Hz)
1k
10k
100k
Gain (V/V)
FIGURE 2-9:
Input Noise Voltage Density
FIGURE 2-12:
Input Noise Voltage Density
vs. Frequency.
vs. Gain.
2004 Microchip Technology Inc.
DS21908A-page 11
MCP6S91/2/3
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
100
90
80
70
60
50
40
30
20
120
110
100
90
VDD = 2.5V
Input Referred
VDD = 5.5V
80
70
10
100
1000
10000
100000
1000000
-50
-25
0
25
50
75
100 125
10
100
1k
10k
100k
1M
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-13:
PSRR vs. Ambient
FIGURE 2-16:
PSRR vs. Frequency.
Temperature.
1,000
10,000
VDD = 5.5V
CH0 = 5.0V
MCP6S92/3
VDD = 5.5V
1,000
100
10
100
10
1
MCP6S91
TA = +125°C
TA = +85°C
MCP6S92/3
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-14:
Input Bias Current vs.
FIGURE 2-17:
Input Bias Current vs. Input
Ambient Temperature.
Voltage.
25%
1.E-07
100n
39 Samples
VDD = 5.5V
CH0 = VDD/2
In Shutdown Mode
CH0 = VDD/2
1.E1-00n8
1.E-10n9
1.1E0-01p0
20%
15%
10%
5%
VDD = 5.5V
VDD = 2.5V
10p
1.E-11
1p
1.E-12
0%
100f
1.E-13
-50 -25
0
25
50
75
100 125
Ambient Temperature (°C)
Quiescent Current in Shutdown (pA)
FIGURE 2-15:
Quiescent Current in
FIGURE 2-18:
Quiescent Current in
Shutdown Mode vs. Ambient Temperature.
Shutdown Mode.
2004 Microchip Technology Inc.
DS21908A-page 12
MCP6S91/2/3
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
35
30
25
20
15
10
5
TA = +125°C
TA = +125°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-19:
Quiescent Current vs.
FIGURE 2-22:
Output Short Circuit Current
Supply Voltage.
vs. Supply Voltage.
1
0.1
1
VOUT = 0.3V to VDD - 0.3V
VDD = 5.5V
0.1
VONL/G:
G = +1
G = +2
G ≥ +4
0.01
0.01
VONL/G, G = +1
G = +2
G ≥ +4
0.001
2.5
0.001
1
3.0
3.5
4.0
4.5
5.0
5.5
10
Output Voltage Swing (VP-P
)
Power Supply Voltage (V)
FIGURE 2-20:
DC Output Non-Linearity vs.
FIGURE 2-23:
DC Output Non-Linearity vs.
Supply Voltage.
Output Swing.
10
1000
100
10
VDD = 5.5V
VDD = 5.5V
VDD = 2.5V
VDD = 2.5V
1
G = 1, 2
G = 4 to 10
G = 16, 32
1
1.E+05
1.E+06
1.E+07
0.1
100k
1M
10M
0.1
1
10
Output Plus Ladder Current Magnitude (mA)
Frequency (Hz)
FIGURE 2-21:
Output Voltage Headroom
vs. Output Plus Ladder Current (circuit in
Figure 4-2).
FIGURE 2-24:
Frequency.
Output Voltage Swing vs.
2004 Microchip Technology Inc.
DS21908A-page 13
MCP6S91/2/3
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
40
30
20
10
0
7
6
5
4
3
2
1
0
G = +32
G = +16
G = +16
G = +4
G = +1
G = +10
G = +8
G = +5
G = +4
G = +2
G = +1
-10
-20
1.E+05
1.E+06
1.E+07
1.E+08
10
100
1000
100k
1M
10M
100M
Capacitive Load (pF)
Frequency (Hz)
FIGURE 2-25:
Gain vs. Frequency.
FIGURE 2-28:
Gain Peaking vs. Capacitive
Load.
100
10
6
5
4
3
2
1
0
VIN
VDD = 5.0V
G = +1 V/V
VOUT
G = +1
G = +4
G = +16
1
0
1
2
3
4
5
6
7
8
9
10
-1
10
100
1000
Capacitive Load (pF)
Time (1 µs/div)
FIGURE 2-26:
Bandwidth vs. Capacitive
FIGURE 2-29:
The MCP6S91/2/3 family
Load.
shows no phase reversal under overdrive.
1
1
Measurement BW = 80 kHz
Measurement BW = 80 kHz
VOUT = 4 VP-P
V
OUT = 2.0VP-P
VDD = 5.0V
0.1
VDD = 5.0V
0.1
G = +16
G = +16
0.01
G = +1
G = +4
0.01
0.001
0.001
G = +4
G = +1
G = +1, RL = 10 kΩ to 1.5V
0.0001 1.E+02
1.E+03
1.E+04
1.E+05
1.E+02
1.E+03
1.E+04
1.E+05
0.0001
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
FIGURE 2-27:
THD plus Noise vs.
FIGURE 2-30:
THD plus Noise vs.
Frequency, VOUT = 2 VP-P
.
Frequency, VOUT = 4 VP-P.
2004 Microchip Technology Inc.
DS21908A-page 14
MCP6S91/2/3
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
60
300
250
200
150
100
50
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
7.5
6.5
5.5
4.5
3.5
2.5
1.5
0.5
-0.5
-1.5
-2.5
VDD = 5.0V
50
VDD = 5.0V
40
30
20
GVIN
10
0
0
GVIN
-10
-20
-30
-40
-50
-60
-50
VOUT
VOUT
-100
-150
-200
-250
-300
G = +1
G = +5
G = +32
G = +1
G = +5
G = +32
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.000
0.200
0.400
0.600
0.800
1.000
1.200
1.400
1.600
1.800
2.000
Time (200 ns/div)
Time (500 ns/div)
FIGURE 2-31:
Small-Signal Pulse
FIGURE 2-34:
Large-Signal Pulse
Response.
Response.
20
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
20
15
10
5
VOUT
VOUT
(CH0 = 0.6V,
G = +1)
15
10
5
(CH0 = 0.3V, G = +5)
5
0
CS
CS
CS
CS
0
0
-5
-5
-10
-15
-20
-10
-15
-20
VOUT
VOUT
(CH1 = 0.3V, G = +1)
(CH0 = 0.3V, G = +1)
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
0.25
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
0.0
Time (500 ns/div)
Time (500 ns/div)
FIGURE 2-32:
Channel Select Timing.
FIGURE 2-35:
Gain Select Timing.
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
3.0
32 Samples
1st Wafer Lot
VDD = 5.0V
Shutdown
Shutdown
CS
CH0 = 0.3V
2.5
G = +1
2.0
5
CS
1.5
0
1.0
VOUT is "ON"
0.5
0.0 0.E+00
1.E+00
2.E+00
3.E+00
4.E+00
5.E+00
6.E+00
7.E+00
8.E+00
9.E+00
1.E+01
1.E+01
1.E+01
Minimum Valid Supply Voltage (V)
Time (1 µs/div)
FIGURE 2-33:
Shutdown Mode.
Output Voltage vs.
FIGURE 2-36:
Voltage (register data still valid).
Minimum Valid Supply
2004 Microchip Technology Inc.
DS21908A-page 15
MCP6S91/2/3
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
G = 1 V/V
DD = 2.5V
G = 1 V/V
VDD = 5.5V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Input Voltage (V)
FIGURE 2-37:
Input Offset Voltage vs.
FIGURE 2-39:
Input Offset Voltage vs.
Input Voltage, VDD = 2.5V.
Input Voltage, VDD = 5.5V.
35
VREF = VSS
30
VDD = 5.5V: VDD–VOH
25
20
15
10
5
VOL–VSS
VDD = 2.5V: VDD–VOH
VOL–VSS
0
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
FIGURE 2-38:
Output Voltage Headroom
vs. Ambient Temperature.
2004 Microchip Technology Inc.
DS21908A-page 16
MCP6S91/2/3
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6S91 MCP6S92 MCP6S93
Symbol
VOUT
CH0
Description
1
2
1
2
1
2
3
4
5
6
Analog Output
Analog Input
—
3
3
CH1
Analog Input
—
4
VREF
VSS
External Reference Pin
Negative Power Supply
SPI™ Chip Select
4
5
5
CS
SI
6
—
7
6
—
7
7
8
SPI Serial Data Input
SPI Serial Data Output
SPI Clock Input
SO
9
SCK
VDD
8
8
10
Positive Power Supply
3.1
Analog Output
3.4
Power Supply (V and V
)
DD
SS
The output pin (VOUT) is a low-impedance voltage
source. The selected gain (G), selected input (CH0,
CH1) and voltage at VREF determine its value.
The Positive Power Supply Pin (VDD) is 2.5V to 5.5V
higher than the Negative Power Supply Pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD
.
3.2
Analog Inputs (CH0, CH1)
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts can
share a bulk capacitor with analog parts (typically
2.2 µF to 10 µF) within 100 mm of the VDD pin.
The inputs CH0 and CH1 connect to the signal
sources. They are high-impedance CMOS inputs with
low bias currents. The internal MUX selects which one
is amplified to the output.
3.3
External Reference Voltage (V
)
REF
3.5
Digital Inputs
The VREF pin, which is an analog input, should be at a
voltage between VSS and VDD (the MCP6S92 has
VREF tied internally to VSS). The voltage at this pin
shifts the output voltage.
The SPI interface inputs are: Chip Select (CS), Serial
Input (SI) and Serial Clock (SCK). These are Schmitt-
triggered, CMOS logic inputs.
3.6
Digital Output
The MCP6S93 device has a SPI interface Serial Output
(SO) pin. This is a CMOS push-pull output and does
not ever go High-Z. Once the device is deselected (CS
goes high), SO is forced low. This feature supports
daisy-chaining, as explained in Section 5.3 “Daisy-
Chain Configuration”.
2004 Microchip Technology Inc.
DS21908A-page 17
MCP6S91/2/3
4.2
Internal Op Amp
4.0
ANALOG FUNCTIONS
The internal op amp gives the right combination of
bandwidth, accuracy and flexibility.
The MCP6S91/2/3 family of Programmable Gain
Amplifiers (PGA) is based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following subsections.
4.2.1
COMPENSATION CAPACITORS
The internal op amp has three compensation capaci-
tors (comp. caps.) connected to a switching network.
They are selected to give good small-signal bandwidth
at high gains and good slew rates (full-power band-
width) at low gains. The change in bandwidth as gain
changes is between 2 and 12 MHz. Refer to Table 4-1
for more information.
VDD
CH0
MUX
CH1
VOUT
CS
SI
SPI™
Logic
SO
RF
TABLE 4-1:
GAIN VS. INTERNAL
COMPENSATION
CAPACITOR
SCK
8
Gain
Switches
RG
Internal GBWP
SR
FPBW
BW
Gain
(V/V)
Comp.
(MHz) (V/µs) (MHz) (MHz)
Cap.
Typ.
12
12
20
20
20
20
64
64
Typ.
4.0
4.0
11
Typ.
0.30
0.30
0.70
0.70
0.70
0.70
1.6
Typ.
12
6
1
2
Large
VREF
MCP6S91 – One input (CH0), no SO pin
VSS
Large
4
Medium
Medium
Medium
Medium
Small
10
7
MCP6S92 – Two inputs (CH0, CH1), VREF tied
5
11
internally to VSS, no SO pin
8
11
2.4
2.0
5
MCP6S93 – Two inputs (CH0, CH1)
10
16
32
11
22
FIGURE 4-1:
PGA Block Diagram.
Small
22
1.6
2.0
4.1 Input MUX
Note 1: FPBW is the Full-Power Bandwidth.
These numbers are based on VDD = 5.0V.
The MCP6S91 has one input, while the MCP6S92 and
MCP6S93 have two inputs (see Figure 4-1).
2: No changes in DC performance
(e.g., VOS) accompany a change in
compensation capacitor.
For the lowest input current, float unused inputs. Tying
these pins to a voltage near the active channel’s bias
voltage also works well. For simplicity, they can be tied
to VSS or VDD, but the input current may increase.
3: BW is the closed-loop, small signal -3 dB
bandwidth.
The one-channel MCP6S91 has approximately the
same input bias current as the two-channel MCP6S92
and MCP6S93.
4.2.2
RAIL-TO-RAIL CHANNEL INPUTS
The input stage of the internal op amp uses two differ-
ential input stages in parallel; one operates at low VIN
(input voltage), while the other operates at high VIN.
With this topology, the internal inputs can operate to
0.3V past either supply rail. The input offset voltage is
measured at both VIN = VSS – 0.3V and VDD + 0.3V to
ensure proper operation.
The input offset voltage mismatch between channels
(∆VOS) is, ideally, 0 µV. The input MUX uses CMOS
transmission gates that have drain-source (channel)
resistance, but no offset voltage. The histogram in
Figure 2-8 reflects the measurement repeatability
(i.e., noise power bandwidth) rather than the actual
mismatch. Reducing the measurement bandwidth will
produce a more narrow histogram and give an aver-
age closer to 0 µV.
The transition between the two input stages occurs
when VIN ≈ VDD – 1.5V. For the best distortion and gain
linearity, avoid this region of operation.
2004 Microchip Technology Inc.
DS21908A-page 18
MCP6S91/2/3
4.2.3
RAIL-TO-RAIL OUTPUT
MCP6S9X
The maximum output voltage swing is the maximum
swing possible under a particular amplifier load current.
The amplifier load current is the sum of the external
load current (IOUT) and the current through the ladder
resistance (ILAD); see Figure 4-2.
RIN
VOUT
VIN
CHx
EQUATION 4-1:
(Maximum expected VIN) – VDD
2 mA
RIN
RIN
≥
≥
Amplifier Load Current = IOUT + ILAD
VSS – (Maximum expected VIN)
Where:
2 mA
(VOUT – VREF
)
-------------------------------------
=
ILAD
RLAD
FIGURE 4-3:
into an input pin.
RIN limits the current flow
4.3
Resistor Ladder
IOUT
The
resistor
ladder
shown
in
Figure 4-1
VOUT
(RLAD = RF + RG) sets the gain. Placing the gain
switches in series with the inverting input reduces the
parasitic capacitance, distortion and gain mismatch.
ILAD
RLAD
RLAD is an additional load on the output of the PGA and
causes additional current draw from the supplies. It is
also a load (ZIN_REF) on the external circuitry driving
the VREF pin.
VREF
FIGURE 4-2:
Amplifier Load Current.
In Shutdown mode, RLAD is still attached to the VOUT
and VREF pins. Thus, these pins and the internal ampli-
fier’s inverting input are all connected through RLAD
and the output is not High-Z (unlike the internal op
amp).
See Figure 2-21 for the typical output headroom
(VDD – VOH or VOL – VSS) as a function of amplifier
load current.
The specification table states the output can reach
within 60 mV of either supply rail when RL = 10 kΩ and
VREF = VDD/2.
While RLAD contributes to the output noise, its effect is
small. Refer to Figure 2-12.
4.2.4
INPUT VOLTAGE AND PHASE
REVERSAL
The MCP6S91/2/3 amplifier family is designed with
CMOS input devices. It is designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-29 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
The maximum voltage that can be applied to the input
pins (CHx) is VSS – 0.3V to VDD + 0.3V. Voltages on
the inputs that exceed this absolute maximum rating
can cause excessive current to flow into or out of the
input pins. Current beyond ±2 mA can cause possible
reliability problems. Applications that exceed this rating
must be externally limited with an input resistor, as
shown in Figure 4-3.
2004 Microchip Technology Inc.
DS21908A-page 19
MCP6S91/2/3
4.4
Rail-to-Rail V
Input
REF
The VREF input is intended to be driven by a low-
impedance voltage source. The source driving the
VREF pin should have an output impedance less than
0.1Ω to maintain reasonable gain accuracy. The supply
voltage VSS and VDD usually meet this requirement.
RLAD presents a load at the VREF pin to the external
circuit (ZIN_REF ≈ (5 kΩ/G)||(6 pF)), which depends on
the gain. Any source driving the VREF pin must be
capable of driving a load as heavy as 0.16 kΩ||6 pF
(G = 32).
The absolute maximum voltages that can be applied to
the reference input pin (VREF) are VSS – 0.3V and
VDD + 0.3V. Voltages on the inputs that exceed this
absolute maximum rating can cause excessive current
to flow into or out of this pin. Current beyond ±2 mA can
cause possible reliability problems. Because an
external series resistor cannot be used (for low gain
error), the external circuit must ensure that VREF is
between VSS – 0.3V and VDD + 0.3V.
The VIVR_REF spec shows the region of normal
operation for the VREF pin (VSS to VDD). Staying within
this region ensures proper operation of the PGA and its
surrounding circuitry.
4.5
Shutdown Mode
These PGAs use a software shutdown command.
When the SPI interface sends a shutdown command,
the internal op amp is shut down and its output placed
in a High-Z state.
The resistive ladder is always connected between
VREF and VOUT; even in shutdown. This means that the
output resistance will be on the order of 5 kΩ, with a
path for output signals to appear at the input.
2004 Microchip Technology Inc.
DS21908A-page 20
MCP6S91/2/3
Chain Configuration”, covers applications using
multiple 16-bit words. SO goes low after CS goes
high; it has a push-pull output that does not go into a
high-Z state.
5.0
DIGITAL FUNCTIONS
The MCP6S91/2/3 PGAs use
a standard SPI
compatible serial interface to receive instructions from
a controller. This interface is configured to allow daisy-
chaining with other SPI devices.
The MCP6S91/2/3 devices operate in SPI modes 0,0
and 1,1. In 0,0 mode, the clock idles in the low state
(Figure 5-1). In 1,1 mode, the clock idles in the high
state (Figure 5-2). In both modes, SI data is loaded into
the PGA on the rising edge of SCK, while SO data is
clocked out on the falling edge of SCK. In 0,0 mode, the
falling edge of CS also acts as the first falling edge of
SCK (see Figure 5-1). There must be multiples of 16
clocks (SCK) while CS is low or commands will abort
(see Section 5.3 “Daisy-Chain Configuration”).
5.1
SPI Timing
Chip Select (CS) toggles low to initiate communica-
tion with these devices. The first byte of each SI word
(two bytes long) is the instruction byte, which goes
into the Instruction register. The Instruction register
points the second byte to its destination. In a typical
application, CS is raised after one word (16 bits) to
implement the desired changes. Section 5.3 “Daisy-
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
SI
Instruction Byte
Data Byte
SO
(first 16 bits out are always zeros)
Serial Bus Sequence for the PGA; SPI™ 0,0 Mode (see Figure 1-4).
FIGURE 5-1:
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
SI
Instruction Byte
Data Byte
SO
(first 16 bits out are always zeros)
Serial Bus Sequence for the PGA; SPI™ 1,1 Mode (see Figure 1-5).
FIGURE 5-2:
2004 Microchip Technology Inc.
DS21908A-page 21
MCP6S91/2/3
After power-up, and when the power supply voltage
dips below the minimum valid VDD (VDD_VAL), the inter-
nal register data and state machine may need to be
reset. This is accomplished as described before. Use
an external system supervisor to detect these events
so that the microcontroller will reset the PGA state and
registers.
5.2
Registers
The analog functions are programmed through the SPI
interface using 16-bit words (see Figure 5-1 and
Figure 5-2). This data is sent to two of three 8-bit regis-
ters: Instruction register (Register 5-1), Gain register
(Register 5-2) and Channel register (Register 5-3).
There are no power-up defaults for these three
registers.
A 0.1 µF bypass capacitor mounted as close as
possible to the VDD pin provides additional transient
immunity.
5.2.1
ENSURING VALID DATA IN THE
REGISTERS
5.2.2
INSTRUCTION REGISTER
After power up, the registers contain random data that
must be initialized. Sending valid gain and channel
selection commands to the internal registers puts valid
data into those registers. Also, the internal state
machine starts in an arbitrary state. Toggling the Chip
Select pin (CS) from high to low, then back to high
again, puts the internal state machine in a known, valid
condition (this can be done by entering any valid
command).
The Instruction register has 3 command bits and 1 indi-
rect address bit; see Register 5-1. The command bits
include a NOP (000) to support daisy-chaining (see
Section 5.3 “Daisy-Chain Configuration”); the other
NOP commands shown should not be used (they are
reserved for future use). The device is brought out of
Shutdown mode when a valid command, other than
NOPor Shutdown, is sent and CS is raised.
REGISTER 5-1:
W-0
M2
bit 7
INSTRUCTION REGISTER
W-0
M1
W-0
M0
U-x
—
U-x
—
U-x
—
U-x
—
W-0
A0
bit 0
bit 7-5
M2-M0: Command bits
000= NOP(Note 1)
001= PGA enters Shutdown mode as soon as a full 16-bit word is sent and CS is raised.
(Notes 1 and 2)
010= Write to register.
011= NOP(reserved for future use) (Note 1)
1XX= NOP(reserved for future use) (Note 1)
bit 4-1
bit 0
Unimplemented: Read as ‘0’ (reserved for future use)
A0: Indirect Address bit
1= Addresses the Channel register
0= Addresses the Gain register
Note 1: All other bits in the 16-bit word (including A0) are “don’t cares.”
2: The device exits Shutdown mode when a valid command (other than NOPor
Shutdown) is sent and CS is raised; that valid command will be executed.
Shutdown does not toggle.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
DS21908A-page 22
MCP6S91/2/3
5.2.3
SETTING THE GAIN
The amplifier can be programmed to produce binary
and decimal gain settings between +1 V/V and +32 V/V.
Register 5-2 shows the details. At the same time, differ-
ent compensation capacitors are selected to optimize
the bandwidth vs. slew rate trade-off (see Table 4-1).
REGISTER 5-2:
U-x
GAIN REGISTER
U-x
—
U-x
U-x
—
U-x
—
W-0
G2
W-0
G1
W-0
G0
—
—
bit 7
bit 0
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’ (reserved for future use)
G2-G0: Gain Select bits
000= Gain of +1
001= Gain of +2
010= Gain of +4
011= Gain of +5
100= Gain of +8
101= Gain of +10
110= Gain of +16
111= Gain of +32
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
DS21908A-page 23
MCP6S91/2/3
5.2.4
CHANGING THE CHANNEL
If the Instruction register is programmed to address the
Channel register, the multiplexed inputs of the
MCP6S92 and MCP6S93 can be changed using
Register 5-3.
REGISTER 5-3:
U-x
CHANNEL REGISTER
U-x
—
U-x
—
U-x
—
U-x
—
U-x
—
U-x
—
W-0
C0
—
bit 7
bit 0
bit 7-1
bit 0
Unimplemented: Read as ‘0’ (reserved for future use)
C0: Channel Select bit
MCP6S91
MCP6S92
CH0
MCP6S93
CH0
0=
1=
CH0
CH0
CH1
CH1
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
2004 Microchip Technology Inc.
DS21908A-page 24
MCP6S91/2/3
The example in Figure 5-3 shows a daisy-chain
configuration with two devices, although any number of
devices can be configured this way. The MCP6S91 and
MCP6S92 can only be used at the far end of the daisy-
chain, because they do not have a serial data out (SO)
pin. As shown in Figure 5-4 and Figure 5-5, both SI and
SO data are sent in 16-bit (2 byte) words. These
devices abort any command that is not a multiple of 16
bits.
5.2.5
The software shutdown command allows the user to
put the amplifier into low-power mode (see
Register 5-1). In this Shutdown mode, most pins are
high-impedance (Section 4.5 “Shutdown Mode” and
Section 5.1 “SPI Timing” cover the exceptions at pins
VREF, VOUT and SO).
SHUTDOWN COMMAND
a
Once the PGA has entered Shutdown mode, it will
remain in this mode until either a valid command is sent
to the device (other than NOP or Shutdown) or the
device is powered down and back up again. The
internal registers maintain their values while in
shutdown.
When using the daisy-chain configuration, the maxi-
mum clock speed possible is reduced to ≈ 5.8 MHz due
to the SO pin’s propagation delay (see Electrical
Specifications).
The internal SPI shift register is automatically loaded
with zeros whenever CS goes high (a command is
executed). Thus, the first 16-bits out of the SO pin after
the CS line goes low are always zeros. This means that
the first command loaded into the next device in the
daisy-chain is a NOP. This feature makes it possible to
send shorter command and data byte strings when the
farthest devices do not need to change. For example, if
there were three devices on the chain, and only the
middle device needed changing, then only 32 bytes of
data need to be transmitted (for the first and middle
devices). The last device on the chain would receive a
NOP when the CS pin is raised to execute the
command.
Once brought out of Shutdown mode, the part returns
to its previous state (see Section 5.2.1 “Ensuring
Valid Data in the Registers” for exceptions to this
rule). This makes it possible to bring the device out of
shutdown mode using one command; send a com-
mand to select the current channel (or gain) and the
device will exit shutdown with the same state that
existed before shutdown.
5.3
Daisy-Chain Configuration
Multiple MCP6S91/2/3 devices can be connected in a
daisy-chain configuration by connecting the SO pin
from one device to the SI pin on the next device and
using common SCK and CS lines (Figure 5-3). This
approach reduces PCB layout complexity and uses
fewer PICmicro® microcontroller I/O pins.
CS
SCK
SO
CS
CS
PICmicro®
SCK
SCK
SI
SO
SI
SO
Microcontroller
Device 1
Device 2
1. Set CS low.
2. Clock out the instruction and data
for device 2 (16 clocks) to Device 1.
3. Device 1 automatically clocks out all
zeros (first 16 clocks) to Device 2.
Device 1
Device 2
00100000 00000000
00000000 00000000
4. Clock out the instruction and data
for Device 1 (16 clocks) to Device 1.
5. Device 1 automatically shifts data
from Device 1 to Device 2 (16 clocks).
6. Raise CS.
Device 1
Device 2
01000001 00000111
00100000 00000000
FIGURE 5-3:
Daisy-Chain Configuration.
2004 Microchip Technology Inc.
DS21908A-page 25
MCP6S91/2/3
CS
1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516
SCK
SI
Instruction Byte
for Device 2
Data Byte
for Device 2
Instruction Byte
for Device 1
Data Byte
for Device 1
SO
(first 16 bits out are always zeros)
Instruction Byte
for Device 2
Data Byte
for Device 2
FIGURE 5-4:
Serial Bus Sequence for Daisy-Chain Configuration; SPI™ 0,0 Mode.
CS
1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516
SCK
SI
Instruction Byte
for Device 2
Data Byte
for Device 2
Instruction Byte
for Device 1
Data Byte
for Device 1
SO
(first 16 bits out are always zeros)
Instruction Byte
for Device 2
Data Byte
for Device 2
FIGURE 5-5:
Serial Bus Sequence for Daisy-Chain Configuration; SPI™ 1,1 Mode.
2004 Microchip Technology Inc.
DS21908A-page 26
MCP6S91/2/3
6.0
6.1
APPLICATIONS INFORMATION
RISO
Changing External Reference
Voltage
VOUT
VIN
MCP6S9X
CL
Figure 6-1 shows a MCP6S91 with the VREF pin at
2.5V and VDD = 5.0V. This allows the PGA to amplify
signals centered on 2.5V, instead of ground-referenced
signals. The voltage reference MCP1525 is buffered by
a MCP6021, which gives a low output impedance
reference voltage from DC to high frequencies. The
source driving the VREF pin should have an output
impedance less than 0.1Ω to maintain reasonable gain
accuracy.
FIGURE 6-2:
Capacitive Loads.
PGA Circuit for Large
Figure 6-3 gives recommended RISO values for
different capacitive loads. After selecting RISO for your
circuit, double-check the resulting frequency response
peaking and step response overshoot on the bench.
Modify RISO’s value until the response is reasonable at
all gains.
VDD
1,000
VOUT
VIN
MCP6S91
VREF
VDD
100
VDD
MCP1525
2.5V
REF
1µF
10
100
1,000
10,000
10
10
MCP6021
p
100
p
1n
10n
L
oad Capacitance (F)
FIGURE 6-3:
Recommended RISO.
FIGURE 6-1:
Reference Voltage.
PGA with Different External
6.3 Layout Considerations
Good PC board layout techniques will help achieve the
performance shown in the Electrical Characteristics
and Typical Performance Curves. It will also help
minimize Electromagnetic Compatibility (EMC) issues.
6.2
Capacitive Load and Stability
Large capacitive loads can cause stability problems
and reduced bandwidth for the MCP6S91/2/3 family of
PGAs (Figure 2-26 and Figure 2-28). As the load
capacitance increases, there is a corresponding
increase in frequency response peaking and step
response overshoot and ringing. This happens
because a large load capacitance decreases the
internal amplifier’s phase margin and bandwidth.
6.3.1
COMPONENT PLACEMENT
Separate different circuit functions: digital from analog,
low-speed from high-speed, and low-power from high-
power. This will reduce crosstalk.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high-frequency (low rise time)
signals.
When driving large capacitive loads with these PGAs
(i.e., > 60 pF), a small series resistor at the output
(RISO in Figure 6-2) improves the internal amplifier’s
stability by making the load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
2004 Microchip Technology Inc.
DS21908A-page 27
MCP6S91/2/3
6.3.2
SUPPLY BYPASS
6.3.4
SIGNAL COUPLING
Use a local bypass capacitor (0.01 µF to 0.1 µF) within
2 mm of the VDD pin. It must connect directly to the
ground plane. A multi-layer ceramic chip capacitor, or
high-frequency equivalent, works best.
The input pins of the MCP6S91/2/3 family of PGAs are
high-impedance. This makes them especially suscepti-
ble to capacitively-coupled noise. Using a ground plane
helps reduce this problem.
Use a bulk bypass capacitor (2.2 µF to 10 µF) within
100 mm of the VDD pin. It needs to connect to the
ground plane. A multi-layer ceramic chip capacitor,
tantalum or high-frequency equivalent, works best.
This capacitor may be shared with other nearby analog
parts.
When noise is capacitively coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.
Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of, and as close as possible to, the victim trace.
Connect the guard traces to the ground plane at both
ends. Also connect long guard traces to the ground
plane in the middle.
6.3.3
INPUT SOURCE IMPEDANCE
The sources driving the inputs of the PGAs need to
have reasonably low source impedance at higher
frequencies. Figure 6-4 shows how the external source
impedance (RS), PGA package pin capacitance (CP1
)
and PGA package pin-to-pin capacitance (CP2) form a
positive feedback voltage divider network. Feedback to
the selected channel may cause frequency response
peaking and step response overshoot and ringing.
Feedback to an unselected channel will produce
crosstalk.
6.3.5
HIGH-FREQUENCY ISSUES
Because the MCP6S91/2/3 PGAs’ frequency response
reaches unity gain at 64 MHz when G = 16 and 32, it is
important to use good PCB layout techniques. Any
parasitic-coupling at high-frequency might cause
undesired peaking. Filtering high-frequency signals
(i.e., fast edge rates) can help. To minimize high-
frequency problems:
CP2
• Use complete ground and power planes
• Use HF, surface-mount components
• Provide clean supply voltages and bypassing
• Keep traces short and straight
RS
VIN
VOUT
MCP6S9X
CP1
• Try a linear power supply (e.g., a LDO)
FIGURE 6-4:
Positive Feedback Path.
Figure 2-6 shows the crosstalk (referred to input) that
results when a hostile signal is connected to CH1, input
CH0 is selected and RS is connected from CH0 to
GND. A gain of +32 was chosen for this plot because it
demonstrates the worst-case behavior. Increasing RS
increases the crosstalk as expected. At a source
impedance of 10 kΩ, there is noticeable peaking in the
response; this is due to positive feedback.
Most designs should use a source resistance (RS) no
larger than 10 kΩ. Careful attention to layout parasitics
and proper component selection will help minimize this
effect. When a source impedance larger than 10 kΩ
must be used, place a capacitor in parallel to CP1 to
reduce the positive feedback. This capacitor needs to
be large enough to overcome gain (or crosstalk) peak-
ing, yet small enough to allow a reasonable signal
bandwidth.
2004 Microchip Technology Inc.
DS21908A-page 28
MCP6S91/2/3
6.4
Typical Applications
VIN
6.4.1
GAIN RANGING
MCP6291
Figure 6-5 shows a circuit that measures the current IX.
The circuit’s performance benefits from changing the
gain on the PGA. Just as a hand-held multimeter uses
different measurement ranges to obtain the best
results, this circuit makes it easy to set a high gain for
small signals and a low gain for large signals. As a
result, the required dynamic range at the PGA’s output
is less than at its input (by up to 30 dB).
10.0 kΩ
VOUT
MCP6S91
1.11 kΩ
FIGURE 6-7:
Range.
PGA with Lower Gain
VOUT
MCP6S9X
IX
RS
6.4.3
EXTENDED GAIN RANGE PGA
Figure 6-8 gives a +1 V/V to +1024 V/V gain range,
which is much greater than the range for a single PGA
(+1 V/V to +32 V/V). The first PGA provides input
multiplexing capability, while the second PGA only
needs one input. These devices can be daisy-chained
(Section 5.3 “Daisy-Chain Configuration”).
FIGURE 6-5:
Current Measurement Circuit.
Wide Dynamic Range
6.4.2
SHIFTED GAIN RANGE PGA
Figure 6-6 shows a circuit using a MCP6291 at a gain
of +10 in front of a MCP6S91. This shifts the overall
gain range to +10 V/V to +320 V/V (from +1 V/V to
+32 V/V).
VOUT
VIN
MCP6S92
MCP6S91
VIN
FIGURE 6-8:
Range.
PGA with Extended Gain
VOUT
MCP6291
MCP6S91
6.4.4
MULTIPLE SENSOR AMPLIFIER
The multiple-channel PGAs (MCP6S92 and MCP6S93)
allow the user to select which sensor appears on the
output (see Figure 6-9). These devices can also change
the gain to optimize performance for each sensor.
10.0 kΩ
1.11 kΩ
FIGURE 6-6:
Range.
PGA with Higher Gain
Sensor # 0
MCP6S93
VOUT
It is also easy to shift the gain range to lower gains (see
Figure 6-7). The MCP6291 acts as a unity gain buffer,
and the resistive voltage divider shifts the gain range
down to +0.1 V/V to +3.2 V/V (from +1 V/V to +32 V/V).
Sensor # 1
FIGURE 6-9:
Inputs.
PGA with Multiple Sensor
2004 Microchip Technology Inc.
DS21908A-page 29
MCP6S91/2/3
6.4.5
EXPANDED INPUT PGA
6.4.7
ADC DRIVER
Figure 6-10 shows cascaded MCP6S28 and
MCP6S92s PGAs that provide up to 9 input channels.
Obviously, Sensors #1-8 have a high total gain range
available, as explained in Section 6.4.3 “Extended
Gain Range PGA”. These devices can be daisy-
chained (Section 5.3 “Daisy-Chain Configuration”).
This family of PGAs is well suited for driving Analog-to-
Digital Converters (ADCs). The binary gains (1, 2, 4, 8,
16 and 32) effectively add five more bits to the input
range (see Figure 6-12). This works well for applica-
tions needing relative accuracy more than absolute
accuracy (e.g., power monitoring).
Low-pass
Filter
Sensor
# 0
MCP3201
12-bit
ADC
3
MCP6S92
VOUT
VIN
MCP6S92
OUT
Sensors
# 1-8
MCP6S28
FIGURE 6-12:
PGA as an ADC driver.
At low gains, the ADC’s Signal-to-Noise Ratio (SNR)
will dominate since the PGA’s input noise voltage
density is so low (10 nV/√Hz @ 10 kHz, typ.). At high
gains, the PGA’s noise will dominate the SNR, but it is
low enough to support most applications. These PGAs
add the flexibility of selecting the best gain for an
application.
FIGURE 6-10:
PGA with Expanded Inputs.
6.4.6
PICmicro® MCU WITH EXPANDED
INPUT CAPABILITY
Figure 6-11 shows a MCP6S93 driving an analog input
to a PICmicro microcontroller. This greatly expands the
input capacity of the microcontroller, while adding the
ability to select the appropriate gain for each source.
The low-pass filter in the block diagram reduces the
integrated noise at the MCP6S92’s output and serves
as an anti-aliasing filter. This filter may be designed
using Microchip’s FilterLab® software, available at
www.microchip.com.
PICmicro®
Microcontroller
VIN
MCP6S93
SPI™
Expanded Input for a
FIGURE 6-11:
PICmicro® Microcontroller.
2004 Microchip Technology Inc.
DS21908A-page 30
MCP6S91/2/3
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil) (MCP6S91, MCP6S92)
Example:
XXXXXXXX
XXXXXNNN
MCP6S91
E/P256
YYWW
0424
8-Lead SOIC (150 mil) (MCP6S91, MCP6S92)
Example:
XXXXXXXX
XXXXYYWW
MCP6S91
E/SN0424
NNN
256
Example:
8-Lead MSOP (MCP6S91, MCP6S92)
6S91E
XXXXX
424256
YWWNNN
Example:
10-Lead MSOP (MCP6S93)
XXXXX
6S93E
YWWNNN
424256
Legend: XX...X Customer specific information*
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office.
2004 Microchip Technology Inc.
DS21908A-page 31
MCP6S91/2/3
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.100
.155
.130
2.54
3.94
3.30
Top to Seating Plane
A
.140
.170
3.56
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
2.92
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
3.68
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
2004 Microchip Technology Inc.
DS21908A-page 32
MCP6S91/2/3
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
Overall Height
A
.053
.069
1.35
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.32
0.10
5.79
3.71
4.80
0.25
0.48
0
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
2004 Microchip Technology Inc.
DS21908A-page 33
MCP6S91/2/3
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
p
E1
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.026
0.65
Overall Height
A
A2
A1
E
.044
1.18
Molded Package Thickness
Standoff
.030
.034
.038
.006
.200
.122
.122
.028
.039
0.76
0.86
0.97
0.15
.5.08
3.10
3.10
0.70
1.00
§
.002
.184
.114
.114
.016
.035
0.05
4.67
2.90
2.90
0.40
0.90
Overall Width
.193
.118
.118
.022
.037
4.90
3.00
3.00
0.55
0.95
Molded Package Width
Overall Length
E1
D
Foot Length
L
Footprint (Reference)
Foot Angle
F
φ
0
6
0
6
c
Lead Thickness
Lead Width
.004
.010
.006
.012
.008
.016
0.10
0.25
0.15
0.30
0.20
0.40
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
7
7
β
7
7
*Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
Drawing No. C04-111
2004 Microchip Technology Inc.
DS21908A-page 34
MCP6S91/2/3
10-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
1
B
n
α
A
φ
c
A2
A1
L
(F)
β
L1
Units
Dimension Limits
INCHES
MILLIMETERS*
MIN
NOM
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
10
10
.020 TYP
0.50 TYP.
Overall Height
Molded Package Thickness
Standoff
A
A2
A1
E
-
-
.033
-
.043
-
-
1.10
.030
.000
.037
.006
0.75
0.00
0.85
0.95
0.15
-
Overall Width
.193 BSC
4.90 BSC
Molded Package Width
Overall Length
Foot Length
E1
D
.118 BSC
3.00 BSC
.118 BSC
3.00 BSC
L
.016
.024
.031
0.40
0.60
0.80
Footprint
F
.037 REF
0.95 REF
φ
c
Foot Angle
0°
.003
.006
5°
-
8°
.009
.012
15°
0°
0.08
0.15
5°
-
8°
0.23
0.30
15°
Lead Thickness
Lead Width
-
-
B
α
β
.009
0.23
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
-
-
-
-
5°
15°
5°
15°
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-021
2004 Microchip Technology Inc.
DS21908A-page 35
MCP6S91/2/3
NOTES:
2004 Microchip Technology Inc.
DS21908A-page 36
MCP6S91/2/3
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
-X
/XX
a)
b)
c)
MCP6S91-E/P:
One-channel PGA,
PDIP package.
Temperature Package
Range
MCP6S91-E/SN: One-channel PGA,
SOIC package.
MCP6S91-E/MS: One-channel PGA,
MSOP package.
Device:
MCP6S91: One-channel PGA
MCP6S91T: One-channel PGA
(Tape and Reel for SOIC and MSOP-8)
MCP6S92: Two-channel PGA
MCP6S92T: Two-channel PGA
a)
b)
MCP6S92-E/MS: Two-channel PGA,
MSOP-8 package.
MCP6S92T-E/MS: Tape and Reel,
Two-channel PGA,
(Tape and Reel for SOIC and MSOP-8)
MSOP-8 package.
MCP6S93: Two-channel PGA
MCP6S93T: Two-channel PGA
a)
b)
MCP6S93-E/UN: Two-channel PGA,
MSOP-10 package.
MCP6S93T-E/UN: Tape and Reel,
Two-channel PGA,
(Tape and Reel for MSOP-10)
Temperature Range:
Package:
E
=
-40°C to +125°C
MSOP-10 package.
MS
P
SN
UN
=
=
=
=
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic Micro Small Outline (MSOP), 10-lead
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21908A-page 37
MCP6S91/2/3
NOTES:
DS21908A-page 38
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21908A-page 39
2004 Microchip Technology Inc.
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http:\\support.microchip.com
Web Address:
www.microchip.com
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Denmark - Ballerup
Tel: 45-4420-9895
Fax: 45-4420-9910
India - New Delhi
Tel: 91-11-5160-8632
Fax: 91-11-5160-8632
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
France - Massy
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Kanagawa
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Atlanta
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Tel: 86-591-750-3506
Fax: 86-591-750-3521
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
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Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
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Tel: 39-0331-742611
Fax: 39-0331-466781
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Tel: 852-2401-1200
Fax: 852-2401-3431
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Tel: 65-6334-8870
Fax: 65-6334-8850
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Tel: 978-692-3848
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Tel: 86-24-2334-2829
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Fax: 886-7-536-4803
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Tel: 44-118-921-5869
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Fax: 886-2-2508-0102
Dallas
Addison, TX
China - Shenzhen
Tel: 86-755-8203-2660
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Tel: 972-818-7423
Fax: 972-818-2924
Taiwan - Hsinchu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shunde
Detroit
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Qingdao
Tel: 86-532-502-7355
Fax: 86-532-502-7205
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
09/27/04
DS21908A-page 40
2004 Microchip Technology Inc.
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