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MCP6V03T-E/SN [MICROCHIP]

300 μA, Auto-Zeroed Op Amps; 300 μA ，自动调零运算放大器
MCP6V03T-E/SN
型号： MCP6V03T-E/SN
厂家： MICROCHIP    MICROCHIP
描述：

300 μA, Auto-Zeroed Op Amps
300 μA ，自动调零运算放大器

运算放大器
文件： 总44页 (文件大小：1034K)
中文：  中文翻译
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MCP6V01/2/3  
300 µA, Auto-Zeroed Op Amps  
Features  
Description  
• High DC Precision:  
The Microchip Technology Inc. MCP6V01/2/3 family of  
operational amplifiers has input offset voltage  
correction for very low offset and offset drift. These  
devices have a wide gain bandwidth product (1.3 MHz,  
typical) and strongly reject switching noise. They are  
unity gain stable, have no 1/f noise, and have good  
PSRR and CMRR. These products operate with a  
single supply voltage as low as 1.8V, while drawing  
300 µA/amplifier (typical) of quiescent current.  
- VOS Drift: ±50 nV/°C (maximum)  
- VOS: ±2 µV (maximum)  
- AOL: 130 dB (minimum)  
- PSRR: 130 dB (minimum)  
- CMRR: 130 dB (minimum)  
- Eni: 2.5 µVP-P (typical), f = 0.1 Hz to 10 Hz  
- Eni: 0.79 µVp-p (typical), f = 0.01 Hz to 1 Hz  
• Low Power and Supply Voltages:  
- IQ: 300 µA/amplifier (typical)  
- Wide Supply Voltage Range: 1.8V to 5.5V  
• Easy to Use:  
The Microchip Technology Inc. MCP6V01/2/3 op amps  
are offered in single (MCP6V01), single with Chip  
Select (CS) (MCP6V03), and dual (MCP6V02). They  
are designed in an advanced CMOS process.  
- Rail-to-Rail Input/Output  
Package Types (top view)  
- Gain Bandwidth Product: 1.3 MHz (typical)  
- Unity Gain Stable  
MCP6V01  
SOIC  
MCP6V01  
2x3 TDFN *  
- Available in Single and Dual  
- Single with Chip Select (CS): MCP6V03  
• Extended Temperature Range: -40°C to +125°C  
NC  
NC  
NC  
NC  
1
8
7
1
2
8
7
VIN  
–
+
VDD  
2
VIN–  
VDD  
EP  
9
VIN  
VOUT  
NC  
3
4
6
5
VIN  
+
VOUT  
NC  
3
4
6
5
VSS  
VSS  
Typical Applications  
• Portable Instrumentation  
• Sensor Conditioning  
MCP6V02  
4x4 DFN *  
MCP6V02  
SOIC  
• Temperature Measurement  
• DC Offset Correction  
VDD  
1
2
3
4
8
7
6
5
VOUTA  
VOUTA  
VDD  
1
8
7
VOUTB  
VINA  
–
+
VINA  
–
+
VOUTB  
2
EP  
9
• Medical Instrumentation  
VINB  
VINB  
–
+
VINA  
VINA  
VINB  
VINB  
–
+
3
4
6
5
VSS  
VSS  
Design Aids  
MCP6V03  
SOIC  
MCP6V03  
2x3 TDFN *  
• SPICE Macro Models  
• FilterLab® Software  
NC  
CS  
1
2
8
7
NC  
CS  
1
2
8
7
• Mindi™ Circuit Designer & Simulator  
• Microchip Advanced Part Selector (MAPS)  
• Analog Demonstration and Evaluation Boards  
• Application Notes  
VIN  
–
+
VDD  
VIN  
VIN  
VSS  
–
VDD  
EP  
9
VIN  
VOUT  
NC  
3
4
6
5
+
VOUT  
NC  
3
4
6
5
VSS  
* Includes Exposed Thermal Pad (EP); see Table 3-1.  
Related Parts  
• MCP6V06/7/8: Non-spread clock, lower noise  
© 2008 Microchip Technology Inc.  
DS22058C-page 1  
MCP6V01/2/3  
Typical Application Circuit  
R1  
R3  
VIN  
VOUT  
R2  
C2  
MCP6XXX  
3 kΩ  
R2  
VDD/2  
MCP6V01  
Offset Voltage Correction for Power Driver  
DS22058C-page 2  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
1.0  
1.1  
ELECTRICAL CHARACTERISTICS  
Absolute Maximum Ratings †  
VDD – VSS .......................................................................6.5V  
† Notice: Stresses above those listed under “Absolute  
Maximum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional operation of  
the device at those or any other conditions above those  
indicated in the operational listings of this specification is not  
implied. Exposure to maximum rating conditions for extended  
periods may affect device reliability.  
Current at Input Pins ....................................................±2 mA  
Analog Inputs (VIN+ and VIN–) †† ... VSS – 1.0V to VDD+1.0V  
All other Inputs and Outputs ............ VSS – 0.3V to VDD+0.3V  
Difference Input voltage ...................................... |VDD – VSS  
|
Output Short Circuit Current ................................Continuous  
Current at Output and Supply Pins ............................±30 mA  
Storage Temperature ...................................-65°C to +150°C  
Max. Junction Temperature ........................................+150°C  
ESD protection on all pins (HBM, MM) ................≥ 4 kV, 300V  
†† See Section 4.2.1 “Rail-to-Rail Inputs”.  
1.2  
Specifications  
TABLE 1-1:  
DC ELECTRICAL SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,  
V
OUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).  
Parameters  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Input Offset  
Input Offset Voltage  
VOS  
TC1  
-2.0  
-50  
—
—
+2.0  
+50  
µV  
TA = +25°C (Note 1)  
Input Offset Voltage Drift with Temperature  
(linear Temp. Co.)  
nV/°C TA = -40 to +125°C  
(Note 1)  
Input Offset Voltage Quadratic Temp. Co.  
Power Supply Rejection  
TC2  
—
±0.1  
143  
—
—
nV/°C2 TA = -40 to +125°C  
PSRR  
130  
dB  
(Note 1)  
Input Bias Current and Impedance  
Input Bias Current  
IB  
IB  
—
—
±1  
60  
—
—
pA  
pA  
Input Bias Current across Temperature  
TA = +85°C  
IB  
—
600  
5000  
—
pA  
TA = +125°C  
Input Offset Current  
IOS  
IOS  
IOS  
ZCM  
ZDIFF  
—
-30  
pA  
Input Offset Current across Temperature  
—
-50  
—
pA  
TA = +85°C  
-1000  
—
-75  
1000  
—
pA  
TA = +125°C  
Common Mode Input Impedance  
Differential Input Impedance  
Common Mode  
1013||6  
1013||6  
Ω||pF  
Ω||pF  
—
—
Common-Mode Input Voltage Range  
Common-Mode Rejection  
VCMR  
VSS − 0.20  
—
VDD + 0.20  
—
V
(Note 2)  
CMRR  
130  
142  
dB  
VDD = 1.8V,  
V
CM = -0.2V to 2.0V  
(Note 1, Note 2)  
CMRR  
140  
152  
—
dB  
VDD = 5.5V,  
V
CM = -0.2V to 5.7V  
(Note 1, Note 2)  
Open-Loop Gain  
DC Open-Loop Gain (large signal)  
AOL  
AOL  
130  
140  
145  
156  
—
—
dB  
dB  
VDD = 1.8V,  
V
OUT = 0.2V to 1.6V (Note 1)  
VDD = 5.5V,  
OUT = 0.2V to 5.3V (Note 1)  
V
Note 1: Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts  
can only be screened in production (except TC1; see Appendix B: “Offset Related Test Screens”).  
2: Figure 2-18 shows how VCMR changed across temperature for the first three production lots.  
© 2008 Microchip Technology Inc.  
DS22058C-page 3  
MCP6V01/2/3  
TABLE 1-1:  
DC ELECTRICAL SPECIFICATIONS (CONTINUED)  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,  
V
OUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).  
Parameters  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Output  
Maximum Output Voltage Swing  
Output Short Circuit Current  
V
OL, VOH VSS + 15  
—
±7  
VDD − 15  
mV  
mA  
mA  
G = +2, 0.5V input overdrive  
VDD = 1.8V  
ISC  
ISC  
—
—
—
—
±22  
VDD = 5.5V  
Power Supply  
Supply Voltage  
VDD  
IQ  
1.8  
200  
1.15  
—
300  
—
5.5  
400  
1.65  
V
µA  
V
Quiescent Current per amplifier  
POR Trip Voltage  
IO = 0  
VPOR  
Note 1: Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts  
can only be screened in production (except TC1; see Appendix B: “Offset Related Test Screens”).  
2: Figure 2-18 shows how VCMR changed across temperature for the first three production lots.  
TABLE 1-2:  
AC ELECTRICAL SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,  
OUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).  
V
Parameters  
Sym Min Typ Max Units  
Conditions  
Amplifier AC Response  
Gain Bandwidth Product  
Slew Rate  
GBWP  
SR  
—
—
—
1.3  
0.5  
65  
—
—
—
MHz  
V/µs  
°
Phase Margin  
PM  
G = +1  
Amplifier Noise Response  
Input Noise Voltage  
Eni  
Eni  
eni  
eni  
ini  
—
—
—
—
—
0.79  
2.5  
120  
45  
—
—
—
—
—
µVP-P f = 0.01 Hz to 1 Hz  
µVP-P f = 0.1 Hz to 10 Hz  
nV/√Hz f < 2.5 kHz  
nV/√Hz f = 100 kHz  
fA/√Hz  
Input Noise Voltage Density  
Input Noise Current Density  
Amplifier Distortion (Note 1)  
Intermodulation Distortion (AC)  
0.6  
IMD  
IMD  
—
—
<1  
<1  
—
—
µVPK VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 1.8V  
µVPK VCM tone = 50 mVPK at 1 kHz, GN = 1, VDD = 5.5V  
Amplifier Step Response  
Start Up Time  
tSTR  
tSTL  
—
—
500  
300  
—
—
µs  
µs  
VOS within 50 µV of its final value  
G = +1, VIN step of 2V,  
Offset Correction Settling Time  
V
OS within 50 µV of its final value  
G = -100, ±0.5V input overdrive to VDD/2,  
IN 50% point to VOUT 90% point (Note 2)  
Output Overdrive Recovery Time  
tODR  
—
100  
—
µs  
V
Note 1: These parameters were characterized using the circuit in Figure 1-7. Figure 2-37 and Figure 2-38 show both an IMD  
tone at DC and a residual tone at1 kHz; all other IMD and clock tones are spread by the randomization circuitry.  
2:  
tODR includes some uncertainty due to clock edge timing.  
DS22058C-page 4  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
TABLE 1-3:  
DIGITAL ELECTRICAL SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,  
OUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6).  
V
Parameters  
Sym  
Min  
Typ  
Max Units  
Conditions  
CS Pull-Down Resistor (MCP6V03)  
CS Pull-Down Resistor  
RPD  
3
5
—
MΩ  
CS Low Specifications (MCP6V03)  
CS Logic Threshold, Low  
VIL  
VSS  
—
—
5
0.3VDD  
—
V
CS Input Current, Low  
ICSL  
pA  
CS = VSS  
CS = VDD  
CS High Specifications (MCP6V03)  
CS Logic Threshold, High  
VIH  
0.7VDD  
—
—
VDD  
—
V
CS Input Current, High  
ICSH  
VDD/RPD  
pA  
CS Input High, GND Current per  
amplifier  
ISS  
ISS  
—
—
—
-0.7  
-2.3  
20  
—
—
—
µA  
µA  
pA  
CS = VDD, VDD = 1.8V  
CS = VDD, VDD = 5.5V  
CS = VDD  
Amplifier Output Leakage, CS High IO_LEAK  
CS Dynamic Specifications (MCP6V03)  
CS Low to Amplifier Output On  
Turn-on Time  
tON  
—
—
—
11  
10  
100  
—
µs  
µs  
V
CS Low = VSS+0.3 V, G = +1 V/V,  
VOUT = 0.9 VDD/2  
CS High to Amplifier Output High-Z  
tOFF  
CS High = VDD – 0.3 V, G = +1 V/V,  
VOUT = 0.1 VDD/2  
Internal Hysteresis  
VHYST  
0.25  
—
TABLE 1-4:  
TEMPERATURE SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND.  
Parameters  
Temperature Ranges  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Specified Temperature Range  
Operating Temperature Range  
Storage Temperature Range  
TA  
TA  
TA  
-40  
-40  
-65  
—
—
—
+125  
+125  
+150  
°C  
°C  
°C  
(Note 1)  
Thermal Package Resistances  
Thermal Resistance, 8L-2x3 TDFN  
Thermal Resistance, 8L-4x4 DFN  
Thermal Resistance, 8L-SOIC  
θJA  
θJA  
θJA  
—
—
—
41  
44  
—
—
—
°C/W  
°C/W (Note 2)  
150  
°C/W  
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (150°C).  
2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.  
© 2008 Microchip Technology Inc.  
DS22058C-page 5  
MCP6V01/2/3  
1.3  
Timing Diagrams  
1.4  
Test Circuits  
The circuits used for the DC and AC tests are shown in  
Figure 1-5 and Figure 1-6. Lay the bypass capacitors  
out as discussed in Section 4.3.8 “Supply Bypassing  
and Filtering”. RN is equal to the parallel combination  
of RF and RG to minimize bias current effects.  
1.8V to 5.5V  
VOS + 50 µV  
1.8V  
0V  
VDD  
tSTR  
VOS  
VDD  
VOS – 50 µV  
1 µF  
RN  
MCP6V0X  
VDD/3  
VIN  
RISO  
CL  
VOUT  
FIGURE 1-1:  
Amplifier Start Up.  
RL  
100 nF  
RF  
VIN  
VL  
RG  
tSTL  
VOS + 50 µV  
VOS + 50 µV  
FIGURE 1-5:  
Most Non-Inverting Gain Conditions.  
AC and DC Test Circuit for  
VOS  
VDD  
1 µF  
FIGURE 1-2:  
Time.  
Offset Correction Settling  
RN  
VDD/3  
MCP6V0X  
VIN  
RISO  
CL  
VOUT  
RL  
VIN  
100 nF  
RF  
tODR  
VL  
RG  
VDD  
FIGURE 1-6:  
AC and DC Test Circuit for  
Most Inverting Gain Conditions.  
tODR  
VOUT  
The circuit in Figure 1-7 tests the op amp input’s  
dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The  
potentiometer balances the resistor network (VOUT  
should equal VREF at DC). The op amp’s common  
mode input voltage is VCM = VIN/2. The error at the  
input (VERR) appears at VOUT with a noise gain of  
10 V/V.  
VDD/2  
VSS  
FIGURE 1-3:  
Output Overdrive Recovery.  
CS  
VIL  
VIH  
tON  
tOFF  
20.0 kΩ 20.0 kΩ 50Ω  
0.1%  
0.1% 25 turn  
VREF  
VOUT  
High-Z  
1 µA  
High-Z  
1 µA  
VDD  
1 µF  
(typical)  
(typical)  
300 µA  
IDD  
(typical)  
300 µA  
RISO  
CL  
VOUT  
RL  
VIN  
(typical)  
-2 µA  
(typical)  
-2 µA  
100 nF  
ISS  
(typical)  
5 pA  
(typical)  
MCP6V0X  
VL  
ICS  
VDD/5 MΩ  
(typical)  
VDD/5 MΩ  
(typical)  
20.0 kΩ  
0.1%  
20.0 kΩ 24.9 Ω  
0.1%  
FIGURE 1-4:  
Chip Select (MCP6V03).  
FIGURE 1-7:  
Test Circuit for Dynamic  
Input Behavior.  
DS22058C-page 6  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
2.0  
TYPICAL PERFORMANCE CURVES  
Note:  
The graphs and tables provided following this note are a statistical summary based on a limited number of  
samples and are provided for informational purposes only. The performance characteristics listed herein  
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified  
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
2.1  
DC Input Precision  
4
3
20%  
VCM = VCMR_L  
Representative Part  
78 Samples  
A = +25°C  
VDD = 1.8V and 5.5V  
Soldered on PCB  
18%  
16%  
14%  
12%  
10%  
8%  
T
2
1
0
-1  
-2  
-3  
-4  
6%  
+125°C  
+85°C  
+25°C  
-40°C  
4%  
2%  
0%  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5  
Power Supply Voltage (V)  
Input Offset Voltage (µV)  
FIGURE 2-1:  
Input Offset Voltage.  
FIGURE 2-4:  
Input Offset Voltage vs.  
Power Supply Voltage with V  
= V  
.
CM  
CMR_L  
22%  
4
3
78 Samples  
VDD = 1.8V and 5.5V  
Soldered on PCB  
VCM = VCMR_H  
Representative Part  
20%  
18%  
16%  
14%  
12%  
10%  
8%  
6%  
4%  
2%  
0%  
2
1
0
-1  
+125°C  
+85°C  
+25°C  
-40°C  
-2  
-3  
-4  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5  
Power Supply Voltage (V)  
Input Offset Voltage Drift; TC1 (nV/°C)  
FIGURE 2-2:  
Input Offset Voltage Drift.  
FIGURE 2-5:  
Input Offset Voltage vs.  
Power Supply Voltage with V  
= V  
.
CM  
CMR_H  
22%  
4
78 Samples  
VDD = 1.8V and 5.5V  
Soldered on PCB  
Representative Part  
20%  
18%  
16%  
14%  
12%  
10%  
8%  
3
2
VDD = 1.8V  
VDD = 5.5V  
1
0
6%  
4%  
2%  
0%  
-1  
-2  
-3  
-4  
Input Offset Voltage's Quadratic Temp Co;  
TC2 (nV/°C2)  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Output Voltage (V)  
FIGURE 2-3:  
Quadratic Temp Co.  
Input Offset Voltage  
FIGURE 2-6:  
Output Voltage.  
Input Offset Voltage vs.  
© 2008 Microchip Technology Inc.  
DS22058C-page 7  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
4
3
14%  
12%  
10%  
8%  
VDD = 1.8V  
Representative Part  
40 Samples  
A = +25°C  
Soldered on PCB  
T
2
1
0
6%  
+125°C  
+85°C  
+25°C  
-40°C  
-1  
-2  
-3  
-4  
4%  
2%  
0%  
1/PSRR (µV/V)  
Input Common Mode Voltage (V)  
FIGURE 2-7:  
Input Offset Voltage vs.  
FIGURE 2-10:  
PSRR.  
Common Mode Voltage with V = 1.8V.  
DD  
4
55%  
VDD = 5.5V  
+125°C  
40 Samples  
TA = +25°C  
50%  
45%  
40%  
35%  
30%  
25%  
20%  
15%  
10%  
5%  
3
2
Representative Part  
+85°C  
+25°C  
-40°C  
VDD = 5.5V  
1
0
-1  
-2  
-3  
-4  
VDD = 1.8V  
0%  
1/AOL (µV/V)  
Input Common Mode Voltage (V)  
FIGURE 2-8:  
Input Offset Voltage vs.  
FIGURE 2-11:  
DC Open-Loop Gain.  
Common Mode Voltage with V = 5.5V.  
DD  
160  
35%  
VDD = 5.5V  
VDD = 1.8V  
39 Samples  
155  
150  
145  
140  
135  
130  
125  
120  
TA = +25°C  
30%  
25%  
20%  
15%  
10%  
5%  
VDD = 5.5V  
Soldered on PCB  
PSRR  
CMRR  
VDD = 1.8V  
0%  
-50  
-25  
0
25  
50  
75  
100  
125  
1/CMRR (µV/V)  
Ambient Temperature (°C)  
FIGURE 2-9:  
CMRR.  
FIGURE 2-12:  
CMRR and PSRR vs.  
Ambient Temperature.  
DS22058C-page 8  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
160  
155  
150  
145  
140  
135  
130  
125  
120  
1,000  
100  
10  
VDD = 5.5V  
VDD = 5.5V  
VDD = 1.8V  
-IOS  
IB  
1
-50  
-25  
0
25  
50  
75  
100  
125  
25 35 45 55 65 75 85 95 105 115 125  
Ambient Temperature (°C)  
Ambient Temperature (°C)  
FIGURE 2-13:  
Ambient Temperature.  
DC Open-Loop Gain vs.  
FIGURE 2-16:  
Currents vs. Ambient Temperature with  
= +5.5V.  
Input Bias and Offset  
V
DD  
160  
140  
120  
100  
80  
1.E1-00m2  
TA = +85°C  
VDD = 5.5V  
1.E-10m3  
1.E10-004µ  
10µ  
1.E-05  
1µ  
1.E-06  
100n  
1.E- 7  
IB  
60  
40  
10n  
1.E-08  
20  
0
-20  
-40  
-60  
+125°C  
+85°C  
+25°C  
-40°C  
1n  
1.E-09  
100p  
1.E-10  
10p  
1.E-11  
IOS  
1p  
1.E-12  
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0  
Input Voltage (V)  
Common Mode Input Voltage (V)  
FIGURE 2-14:  
Input Bias and Offset  
FIGURE 2-17:  
Input Bias Current vs. Input  
Currents vs. Common Mode Input Voltage with  
Voltage (below V ).  
SS  
T = +85°C.  
A
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
TA = +125°C  
VDD = 5.5V  
IB  
IOS  
-200  
-400  
Common Mode Input Voltage (V)  
FIGURE 2-15:  
Input Bias and Offset  
Currents vs. Common Mode Input Voltage with  
T = +125°C.  
A
© 2008 Microchip Technology Inc.  
DS22058C-page 9  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
2.2  
Other DC Voltages and Currents  
0.05  
40  
30  
3 Lots  
-40°C  
+25°C  
+85°C  
+125°C  
0.00  
-0.05  
-0.10  
-0.15  
20  
10  
0
Lower (VCMR – VSS  
)
-10  
-20  
-30  
-40  
-0.20  
-0.25  
-0.30  
-0.35  
+125°C  
+85°C  
+25°C  
-40°C  
Upper ( VDD – VCMR  
)
-50  
-25  
0
25  
50  
75  
100 125  
Ambient Temperature (°C)  
Power Supply Voltage (V)  
FIGURE 2-18:  
Input Common Mode  
FIGURE 2-21:  
Output Short Circuit Current  
Voltage Headroom (Range) vs. Ambient  
Temperature.  
vs. Power Supply Voltage.  
1000  
450  
400  
350  
300  
250  
VDD = 5.5V  
VDD = 1.8V  
100  
+125°C  
200  
150  
100  
50  
+85°C  
+25°C  
-40°C  
VDD – VOH  
VOL – VSS  
0
10  
0.1  
1
10  
Power Supply Voltage (V)  
Output Current Magnitude (mA)  
FIGURE 2-22:  
Supply Current vs. Power  
FIGURE 2-19:  
Output Voltage Headroom  
Supply Voltage.  
vs. Output Current.  
30%  
12  
11  
93 Samples  
3 Lots  
RL = 20 kΩ  
25%  
20%  
15%  
10%  
5%  
TA = +25°C  
10  
9
8
7
6
5
4
3
2
VDD = 5.5V  
VOL – VSS  
VDD – VOH  
VDD = 1.8V  
1
0
0%  
-50  
-25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
POR Trip Voltage (V)  
FIGURE 2-23:  
Power On Reset Trip  
FIGURE 2-20:  
Output Voltage Headroom  
Voltage.  
vs. Ambient Temperature.  
DS22058C-page 10  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
-50  
-25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
FIGURE 2-24:  
Power On Reset Voltage vs.  
Ambient Temperature.  
© 2008 Microchip Technology Inc.  
DS22058C-page 11  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
2.3  
Frequency Response  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
130  
120  
110  
100  
90  
VDD = 5.5V  
GBWP  
CMRR  
80  
70  
60  
PM  
VDD = 1.8V  
PSRR+  
PSRR-  
50  
40  
-50 -25  
0
25  
50  
75 100 125  
10  
100  
1k  
10k  
100k  
1M  
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06  
Frequency (Hz)  
Ambient Temperature (°C)  
FIGURE 2-25:  
CMRR and PSRR vs.  
FIGURE 2-28:  
Gain Bandwidth Product  
Frequency.  
and Phase Margin vs. Ambient Temperature.  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
130  
120  
110  
100  
90  
60  
50  
40  
30  
20  
10  
0
0
GBWP  
VDD = 1.8V  
CL = 60 pF  
-30  
-60  
-90  
VDD = 5.5V  
∠AOL  
-120  
-150  
-180  
-210  
-240  
-270  
VDD = 1.8V  
80  
| AOL  
|
70  
60  
-10  
-20  
50  
PM  
40  
-30  
1k  
10k  
1.E+04  
100k  
1.E+05  
Frequency (Hz)  
1M  
1.E+06  
10M  
1.E+03  
1.E+07  
Common Mode Input Voltage (V)  
FIGURE 2-26:  
Open-Loop Gain vs.  
FIGURE 2-29:  
Gain Bandwidth Product  
Frequency with V = 1.8V.  
and Phase Margin vs. Common Mode Input  
Voltage.  
DD  
60  
50  
40  
30  
20  
10  
0
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
130  
120  
110  
100  
90  
VDD = 5.5V  
CL = 60 pF  
GBWP  
-30  
-60  
-90  
∠AOL  
VDD = 5.5V  
-120  
-150  
-180  
-210  
-240  
-270  
VDD = 1.8V  
80  
| AOL  
|
70  
0
-10  
-20  
-30  
60  
50  
PM  
40  
1k  
10k  
1.E+04  
100k  
1.E+05  
Frequency (Hz)  
1M  
1.E+06  
10M  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Output Voltage (V)  
1.E+03  
1.E+07  
FIGURE 2-27:  
Open-Loop Gain vs.  
FIGURE 2-30:  
Gain Bandwidth Product  
Frequency with V = 5.5V.  
and Phase Margin vs. Output Voltage.  
DD  
DS22058C-page 12  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
1+00k4  
RTI  
VDD = 1.8V  
1k  
+03  
VDD = 5.5V  
100  
+02  
VDD = 1.8V  
G = 1 V/V  
G = 10 V/V  
G = 100 V/V  
10  
+01  
1
+00  
100k  
1M  
1.0E+06  
10M  
1.0E+07  
100M  
1.0E+08  
100k  
1M  
10M  
1.0E+05  
1.E+05  
1.E+06  
Frequency (Hz)  
1.E+07  
Frequency (Hz)  
FIGURE 2-31:  
Closed-Loop Output  
FIGURE 2-33:  
Channel-to-Channel  
Impedance vs. Frequency with V = 1.8V.  
Separation vs. Frequency.  
DD  
+1004k  
10  
VDD = 5.5V  
VDD = 5.5V  
1k  
+03  
VDD = 1.8V  
100  
+02  
1
G = 1 V/V  
G = 10 V/V  
G = 100 V/V  
10  
+01  
1
+00  
0.1  
1k  
10k  
1.E+04  
100k  
Frequency (Hz)  
1M  
100k  
1M  
1.0E+06  
10M  
1.0E+07  
100M  
1.0E+08  
1.0E+05  
1.E+03  
1.E+05  
1.E+06  
Frequency (Hz)  
FIGURE 2-32:  
Closed-Loop Output  
FIGURE 2-34:  
Maximum Output Voltage  
Impedance vs. Frequency with V = 5.5V.  
Swing vs. Frequency.  
DD  
© 2008 Microchip Technology Inc.  
DS22058C-page 13  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
2.4  
Input Noise and Distortion  
1000  
1000  
100  
10  
100  
10  
1
GDM = 1 V/V  
VDD tone = 50 mVP-P, f = 1 kHz  
IMD tone at DC  
VDD = 5.5V  
1 kHz tone  
eni  
100  
10  
VDD = 1.8V  
VDD = 1.8V  
VDD = 5.5V  
Eni(0 Hz to f)  
10  
100  
1k  
10k  
100k  
100  
1k  
1.E+03  
10k  
1.E+04  
100k  
1.E+05  
1.E+02  
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05  
Frequency (Hz)  
Frequency (Hz)  
FIGURE 2-35:  
Input Noise Voltage Density  
FIGURE 2-38:  
Inter-Modulation Distortion  
vs. Frequency.  
vs. Frequency with V Disturbance (see  
DD  
Figure 1-7).  
160  
140  
120  
VDD = 1.8V  
VDD = 5.5V  
VDD = 1.8V  
100  
80  
60  
40  
20  
0
NPBW = 10 Hz  
NPBW = 1 Hz  
0
10 20 30 40 50 60 70 80 90 100  
t (s)  
Common Mode Input Voltage (V)  
FIGURE 2-36:  
Input Noise Voltage Density  
FIGURE 2-39:  
Input Noise vs. Time with  
vs. Input Common Mode Voltage.  
1 Hz and 10 Hz Filters and V =1.8V.  
DD  
100  
VDD = 5.5V  
IMD tone at DC  
GDM = 1 V/V  
VCM tone = 50 mVPK, f = 1 kHz  
residual 1 kHz tone  
10  
NPBW = 10 Hz  
NPBW = 1 Hz  
VDD = 1.8V  
VDD = 5.5V  
1
100  
1k  
1.E+03  
10k  
1.E+04  
100k  
1.E+05  
0
10 20 30 40 50 60 70 80 90 100  
t (s)  
1.E+02  
Frequency (Hz)  
FIGURE 2-37:  
vs. Frequency with V  
Figure 1-7).  
Inter-Modulation Distortion  
FIGURE 2-40:  
1 Hz and 10 Hz Filters and V =5.5V.  
Input Noise vs. Time with  
Disturbance (see  
CM  
DD  
DS22058C-page 14  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
2.5  
Time Response  
5
4
70  
65  
60  
55  
50  
45  
40  
35  
30  
25  
20  
VDD = 5.5V  
G = 1  
Temperature increased by  
using heat gun for 8 seconds.  
TPCB  
3
2
1
0
-1  
-2  
-3  
-4  
-5  
VOS  
0
20 40 60 80 100 120 140 160 180  
Time (s)  
0
2
4
6
8
10 12 14 16 18 20  
Time (µs)  
FIGURE 2-41:  
Input Offset Voltage vs.  
FIGURE 2-44:  
Non-inverting Small Signal  
Time with Temperature Change.  
Step Response.  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
10  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
VDD = 5.5V  
G = 1  
POR Trip  
Point  
8
6
VDD  
4
2
0
-2  
VOS  
-4  
-6  
-8  
-10  
0
5
10 15 20 25 30 35 40 45 50  
Time (µs)  
0.0 0.2 0.4 0T.6im0e.8(210.0 µ1s.2/di1v.)4 1.6 1.8 2.0  
FIGURE 2-42:  
Time at Power Up.  
Input Offset Voltage vs.  
FIGURE 2-45:  
Step Response.  
Non-inverting Large Signal  
7
6
5
VDD = 5.5V  
G = -1  
VDD = 5.5V  
G = 1  
VIN  
VOUT  
4
3
2
1
0
-1  
0
1
2
3
4
5
6
7
8
9
10  
0
1
2
3
4
5
6
7
8
9
10  
Time (ms)  
Time (µs)  
FIGURE 2-43:  
shows no input phase reversal with overdrive.  
The MCP6V01/2/3 family  
FIGURE 2-46:  
Response.  
Inverting Small Signal Step  
© 2008 Microchip Technology Inc.  
DS22058C-page 15  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
6.0  
6
5
4
3
2
1
0
-1  
5.5  
5.0  
VDD = 5.5V  
G = -1  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
G VIN  
VOUT  
4.0  
3.0  
2.0  
1.0  
0.0  
-1.0  
VOUT  
G VIN VDD = 5.5V  
G = -100 V/V  
0.5V Overdrive  
0
5
10 15 20 25 30 35 40 45 50  
Time (µs)  
Time (50 µs/div)  
FIGURE 2-49:  
vs. Time with G = -100 V/V.  
Output Overdrive Recovery  
FIGURE 2-47:  
Response.  
Inverting Large Signal Step  
1000  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.5V Output Overdrive  
VDD = 5.5V  
Rising Edge  
VDD = 5.5V  
100  
tODR, high  
VDD = 1.8V  
Falling Edge  
10  
0.3  
0.2  
0.1  
0.0  
VDD = 1.8V  
tODR, low  
1
1
10  
100  
1000  
-50  
-25  
0
25  
50  
75  
100  
125  
Inverting Gain Magnitude (V/V)  
Ambient Temperature (°C)  
FIGURE 2-50:  
Time vs. Inverting Gain.  
Output Overdrive Recovery  
FIGURE 2-48:  
Temperature.  
Slew Rate vs. Ambient  
DS22058C-page 16  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
2.6  
Chip Select Response (MCP6V03 only)  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
VDD = 5.5V  
CS = VDD  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Chip Select Voltage (V)  
Power Supply Voltage (V)  
FIGURE 2-51:  
Chip Select Current vs.  
FIGURE 2-54:  
Chip Select Current vs. Chip  
Power Supply Voltage.  
Select Voltage.  
400  
350  
1.8  
1.6  
1.4  
VDD = 1.8V  
G = 1  
VOUT On  
V
IN = 0.9V  
300  
250  
200  
150  
100  
50  
Op Amp  
turns on  
here  
Op Amp  
turns off  
here  
VL = 0V  
1.2  
VOUT Off  
VOUT Off  
1.0  
0.8  
VDD = 1.8V  
G = +1 V/V  
VIN= VDD  
RL = 10 kΩ tied to VDD/2  
0.6  
0.4  
Hysteresis  
0.2  
2
1
0
0.0  
CS  
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8  
Chip Select Voltage (V)  
Time (5 µs/div)  
FIGURE 2-52:  
Power Supply Current vs.  
FIGURE 2-55:  
Chip Select Voltage, Output  
Chip Select Voltage with V = 1.8V.  
Voltage vs. Time with V = 1.8V.  
DD  
DD  
600  
5.5  
5.0  
4.5  
4.0  
39  
VDD = 5.5V  
G = 1  
VOUT On  
500  
V
IN = 2.75V  
Op Amp  
turns off  
Op Amp  
here  
VL = 0V  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
VOUT Off  
VOUT Off  
400  
turns on  
here  
300  
200  
100  
0
VDD = 5.5V  
G = +1 V/V  
VIN= VDD  
Hysteresis  
RL = 10 kΩ tied to VDD/2  
6
3
0
CS  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Chip Select Voltage (V)  
0
5
10 15 20 25 30 35 40 45 50  
Time (5 µs/div)  
FIGURE 2-53:  
Power Supply Current vs.  
FIGURE 2-56:  
Chip Select Voltage, Output  
Chip Select Voltage with V = 5.5V.  
Voltage vs. Time with V = 5.5V.  
DD  
DD  
© 2008 Microchip Technology Inc.  
DS22058C-page 17  
MCP6V01/2/3  
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 20 kΩ to VL, CL = 60 pF, and CS = GND.  
70%  
65%  
60%  
55%  
50%  
45%  
40%  
35%  
30%  
7
6
5
4
3
2
1
0
VIH/VDD  
VDD = 5.5V  
VIL/VDD  
VDD = 1.8V  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100 125  
Ambient Temperature (°C)  
Ambient Temperature (°C)  
FIGURE 2-57:  
Chip Select Relative Logic  
FIGURE 2-60:  
Chip Select’s Pull-down  
Thresholds vs. Ambient Temperature.  
Resistor (R ) vs. Ambient Temperature.  
PD  
2.0  
0.40  
0.35  
0.30  
CS = VDD  
Representative Part  
1.8  
1.6  
1.4  
VDD = 5.5V  
+125°C  
0.25  
0.20  
0.15  
0.10  
0.05  
0.00  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
+85°C  
+25°C  
-40°C  
VDD = 1.8V  
-50  
-25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
Power Supply Voltage (V)  
FIGURE 2-58:  
Chip Select Hysteresis.  
FIGURE 2-61:  
Quiescent Current in  
Shutdown vs. Power Supply Voltage.  
16  
14  
12  
10  
8
VDD = 5.5V  
VDD = 1.8V  
6
4
2
0
-50  
-25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
FIGURE 2-59:  
Chip Select Turn On Time  
vs. Ambient Temperature.  
DS22058C-page 18  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
3.0  
PIN DESCRIPTIONS  
Descriptions of the pins are listed in Table 3-1.  
TABLE 3-1:  
MCP6V01  
PIN FUNCTION TABLE  
MCP6V02  
MCP6V03  
Symbol  
VOUT, VOUTA  
Description  
TDFN  
SOIC  
DFN  
SOIC  
TDFN  
SOIC  
6
2
3
6
2
3
1
2
3
1
2
3
6
2
3
6
2
3
Output (op amp A)  
VIN–, VINA  
–
+
Inverting Input (op amp A)  
VIN+, VINA  
Non-inverting Input  
(op amp A)  
4
4
4
5
4
5
4
4
VSS  
Negative Power Supply  
—
—
—
—
VINB  
+
Non-inverting Input  
(op amp B)  
—
—
7
—
—
7
6
7
6
7
—
—
7
—
—
7
VINB  
–
Inverting Input (op amp B)  
Output (op amp B)  
VOUTB  
VDD  
8
8
Positive Power Supply  
—
—
—
—
—
8
CS  
Chip Select (op amp A)  
No Internal Connection  
1, 5, 8  
9
1, 5, 8  
—
—
9
—
—
1, 5, 8  
9
1, 5  
—
NC  
EP  
Exposed Thermal Pad (EP);  
must be connected to VSS  
3.1  
Analog Outputs  
3.4  
Chip Select (CS) Digital Input  
The analog output pins (VOUT) are low-impedance  
voltage sources.  
This pin (CS) is a CMOS, Schmitt-triggered input that  
places the MCP6V03 op amps into a low power mode  
of operation.  
3.2  
Analog Inputs  
3.5  
Exposed Thermal Pad (EP)  
The non-inverting and inverting inputs (VIN+, VIN–, …)  
are high-impedance CMOS inputs with low bias  
currents.  
There is an internal connection between the Exposed  
Thermal Pad (EP) and the VSS pin; they must be con-  
nected to the same potential on the Printed Circuit  
Board (PCB).  
3.3  
Power Supply Pins  
This pad can be connected to a PCB ground plane to  
provide a larger heat sink. This improves the package  
thermal resistance (θJA).  
The positive power supply (VDD) is 1.8V to 5.5V higher  
than the negative power supply (VSS). For normal  
operation, the other pins are between VSS and VDD  
.
Typically, these parts are used in a single (positive)  
supply configuration. In this case, VSS is connected to  
ground and VDD is connected to the supply. VDD will  
need bypass capacitors.  
© 2008 Microchip Technology Inc.  
DS22058C-page 19  
MCP6V01/2/3  
NOTES:  
DS22058C-page 20  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
4.1  
Overview of Auto-zeroing  
Operation  
4.0  
APPLICATIONS  
The MCP6V01/2/3 family of auto-zeroed op amps is  
manufactured using Microchip’s state of the art CMOS  
process. It is designed for low cost, low power and high  
precision applications. Its low supply voltage, low  
quiescent current and wide bandwidth makes the  
MCP6V01/2/3 ideal for battery-powered applications.  
Figure 4-1 shows  
a
simplified diagram of the  
MCP6V01/2/3 auto-zeroed op amps. This will be used  
to explain how the DC voltage errors are reduced in this  
architecture.  
VIN+  
VIN–  
Main  
Amp.  
NC  
Output  
Buffer  
VOUT  
CFW  
VREF  
Null  
Input  
Switches  
Null  
Output  
Switches  
φ1  
Null  
Amp.  
CH  
POR  
Oscillator  
Null  
Correct  
Switches  
φ1  
φ2  
Digital  
Control  
Clock  
Randomization  
φ2  
CS  
FIGURE 4-1:  
Simplified Auto-zeroed Op Amp Functional Diagram.  
The internal POR ensures the part starts up in a known  
good state. It also provides protection against power  
supply brown out events.  
4.1.1  
BUILDING BLOCKS  
The Null Amp. and Main Amp. are designed for high  
gain and accuracy using a differential topology. They  
have an auxiliary input (bottom left) used for correcting  
the offset voltages. Both inputs are added together  
internally. The capacitors at the auxiliary inputs (CFW  
and CH) hold the corrected values during normal  
operation.  
The Chip Select input places the op amp in a low power  
state when it is high. When it goes low, it powers the op  
amp at its normal level and starts operation properly.  
The Digital Control circuitry takes care of all of the  
housekeeping details of the switching operation. It also  
takes care of Chip Select and POR events.  
The Output Buffer is designed to drive external loads at  
the VOUT pin. It also produces a single ended output  
voltage (VREF is an internal reference voltage).  
All of these switches are make-before-break in order to  
minimize glitch-induced errors. They are driven by two  
clock phases (φ1 and φ2) that select between normal  
mode and auto-zeroing mode.  
The clock is derived from an internal R-C oscillator  
running at a rate of fOSC1 = 300 kHz. The oscillator’s  
output is divided down to the desired rate. It is also  
randomized to minimize (spread) undesired clock  
tones in the output.  
© 2008 Microchip Technology Inc.  
DS22058C-page 21  
MCP6V01/2/3  
offset voltage on overall performance. Essentially, the  
Null Amplifier and Main Amplifier behave as a regular  
op amp with very high gain (AOL) and very low offset  
voltage (VOS).  
4.1.2  
AUTO-ZEROING ACTION  
Figure 4-2 shows the connections between amplifiers  
during the Normal Mode of operation (φ1). The hold  
capacitor (CH) corrects the Null Amplifier’s input offset.  
Since the Null Amplifier has very high gain, it  
dominates the signal seen by the Main Amplifier. This  
greatly reduces the impact of the Main Amplifier’s input  
VIN+  
VIN–  
Main  
Amp.  
NC  
Output  
Buffer  
VOUT  
CFW  
VREF  
Null  
Amp.  
CH  
FIGURE 4-2:  
Normal Mode of Operation (φ ); Equivalent Amplifier Diagram.  
1
Figure 4-3 shows the connections between amplifiers  
during the Auto-zeroing Mode of operation (φ2). The  
signal goes directly through the Main Amplifier, and the  
flywheel capacitor (CFW) maintains a constant correc-  
tion on the Main Amplifier’s offset.  
Since these corrections happen every 100 µs, or so,  
we also minimize slow errors, including offset drift with  
temperature (ΔVOS/ΔTA), 1/f noise, and input offset  
aging.  
The Null Amplifier uses its own high open loop gain to  
drive the voltage across CH to the point where its input  
offset voltage is almost zero. Because the principal  
input is connected to VIN+, the auto-zeroing action  
corrects the offset at the current common mode input  
voltage (VCM) and supply voltage (VDD). This makes  
the DC CMRR and PSRR very high also.  
VIN+  
VIN–  
Main  
Amp.  
NC  
Output  
Buffer  
VOUT  
CFW  
VREF  
Null  
Amp.  
CH  
FIGURE 4-3:  
Auto-zeroing Mode of Operation (φ ); Equivalent Diagram.  
2
response to produce IMD tones at sum and difference  
frequencies. IMD distortion tones are generated about  
all of the square wave clock’s harmonics.  
4.1.3 INTERMODULATION DISTORTION  
(IMD)  
The MCP6V01/2/3 op amps will show intermodulation  
distortion (IMD), products when an AC signal is  
present.  
Clock randomization spreads the IMD tones across the  
frequency spectrum, but cannot eliminate them. The  
spread energy is low and is not correlated with the sig-  
nal of interest, so it is not of concern for most precision  
applications. See Figure 2-37 and Figure 2-38.  
The signal and clock can be decomposed into sine  
wave tones (Fourier series components). These tones  
interact with the auto-zeroing circuitry’s non-linear  
DS22058C-page 22  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
pins (VIN+ and VIN–) from going too far above VDD, and  
dump any currents onto VDD. When implemented as  
shown, resistors R1 and R2 also limit the current  
through D1 and D2.  
4.2  
Other Functional Blocks  
4.2.1  
RAIL-TO-RAIL INPUTS  
The input stage of the MCP6V01/2/3 op amps uses two  
differential CMOS input stages in parallel. One  
operates at low common mode input voltage (VCM  
,
VDD  
which is approximately equal to VIN+ and VIN– in nor-  
mal operation) and the other at high VCM. With this  
topology, the input operates with VCM up to 0.2V past  
either supply rail at +25°C (see Figure 2-18). The input  
offset voltage (VOS) is measured at VCM = VSS – 0.2V  
and VDD + 0.2V to ensure proper operation.  
D1  
R1  
V1  
D2  
VOUT  
MCP6V0X  
V2  
The transition between the input stages occurs when  
VCM ≈ VDD – 0.9V (see Figure 2-7 and Figure 2-8). For  
the best distortion and gain linearity, with non-inverting  
gains, avoid this region of operation.  
R2  
VSS – (minimum expected V1)  
R1 >  
R2 >  
2 mA  
VSS – (minimum expected V2)  
2 mA  
4.2.1.1  
Phase Reversal  
The input devices are designed to not exhibit phase  
inversion when the input pins exceed the supply  
voltages. Figure 2-43 shows an input voltage  
exceeding both supplies with no phase inversion.  
FIGURE 4-5:  
Inputs.  
Protecting the Analog  
It is also possible to connect the diodes to the left of the  
resistor R1 and R2. In this case, the currents through  
the diodes D1 and D2 need to be limited by some other  
mechanism. The resistors then serve as in-rush current  
limiters; the DC current into the input pins (VIN+ and  
VIN–) should be very small.  
4.2.1.2  
Input Voltage and Current Limits  
The ESD protection on the inputs can be depicted as  
shown in Figure 4-4. This structure was chosen to  
protect the input transistors, and to minimize input bias  
current (IB). The input ESD diodes clamp the inputs  
when they try to go more than one diode drop below  
VSS. They also clamp any voltages that go too far  
above VDD; their breakdown voltage is high enough to  
allow normal operation, and low enough to bypass  
quick ESD events within the specified limits.  
A significant amount of current can flow out of the  
inputs (through the ESD diodes) when the common  
mode voltage (VCM) is below ground (VSS); see  
Figure 2-17. Applications that are high impedance may  
need to limit the usable voltage range.  
4.2.2  
RAIL-TO-RAIL OUTPUT  
Bond  
VDD  
The output voltage range of the MCP6V01/2/3  
auto-zeroed op amps is VDD – 15 mV (minimum) and  
Pad  
VSS + 15 mV (maximum) when RL = 20 kΩ is  
connected to VDD/2 and VDD = 5.5V. Refer to  
Figure 2-19 and Figure 2-20 for more information.  
Bond  
Pad  
Bond  
Pad  
Input  
Stage  
VIN+  
VIN–  
These op amps are designed to drive light loads; use  
another amplifier to buffer the output from heavy loads.  
Bond  
Pad  
4.2.3  
CHIP SELECT (CS)  
VSS  
The single MCP6V03 has a Chip Select (CS) pin.  
When CS is pulled high, the supply current for the  
corresponding op amp drops to about 1 µA (typical),  
and is pulled through the CS pin to VSS. When this  
happens, the amplifier is put into a high impedance  
state. By pulling CS low, the amplifier is enabled. If the  
CS pin is left floating, the internal pull-down resistor  
(about 5 MΩ) will keep the part on. Figure 1-4 shows  
the output voltage and supply current response to a CS  
pulse.  
FIGURE 4-4:  
Structures.  
Simplified Analog Input ESD  
In order to prevent damage and/or improper operation  
of these amplifiers, the circuit must limit the currents  
(and voltages) at the input pins (see Section 1.1  
“Absolute Maximum Ratings †”). Figure 4-5 shows  
the recommended approach to protecting these inputs.  
The internal ESD diodes prevent the input pins (VIN+  
and VIN–) from going too far below ground, and the  
resistors R1 and R2 limit the possible current drawn out  
of the input pins. Diodes D1 and D2 prevent the input  
© 2008 Microchip Technology Inc.  
DS22058C-page 23  
MCP6V01/2/3  
4.3.4  
SOURCE CAPACITANCE  
4.3  
Application Tips  
The capacitances seen by the two inputs should be  
small and matched. The internal switches connected to  
the inputs dump charges on these capacitors; an offset  
can be created if the capacitances do not match.  
4.3.1  
INPUT OFFSET VOLTAGE OVER  
TEMPERATURE  
Table 1-1 gives both the linear and quadratic tempera-  
ture coefficients (TC1 and TC2) of input offset voltage.  
The input offset voltage, at any temperature in the  
specified range, can be calculated as follows:  
4.3.5  
CAPACITIVE LOADS  
Driving large capacitive loads can cause stability  
problems for voltage feedback op amps. As the load  
capacitance increases, the feedback loop’s phase  
margin decreases and the closed-loop bandwidth is  
reduced. This produces gain peaking in the frequency  
response, with overshoot and ringing in the step  
response. These auto-zeroed op amps have a different  
output impedance than most op amps, due to their  
unique topology.  
EQUATION 4-1:  
VOS(TA) = VOS + TC1ΔT + TC2ΔT2  
Where:  
ΔT  
OS(TA)  
VOS  
=
=
=
=
=
TA – 25°C  
V
input offset voltage at TA  
input offset voltage at +25°C  
linear temperature coefficient  
When driving a capacitive load with these op amps, a  
series resistor at the output (RISO in Figure 4-6)  
improves the feedback loop’s phase margin (stability)  
by making the output load resistive at higher frequen-  
cies. The bandwidth will be generally lower than the  
bandwidth with no capacitive load.  
TC1  
TC2  
quadratic temperature  
coefficient  
4.3.2  
DC GAIN PLOTS  
Figure 2-9, Figure 2-10 and Figure 2-11 are histograms  
of the reciprocals (in units of µV/V) of CMRR, PSRR  
and AOL, respectively. They represent the change in  
input offset voltage (VOS) with a change in common  
RISO  
VOUT  
CL  
mode input voltage (VCM), power supply voltage (VDD  
)
MCP6V0X  
and output voltage (VOUT).  
The 1/AOL histogram is centered near 0 µV/V because  
the measurements are dominated by the op amp’s  
input noise. The negative values shown represent  
noise, not unstable behavior. We validate the op amps’  
FIGURE 4-6:  
Stabilizes Capacitive Loads.  
Output Resistor, R  
,
ISO  
Figure 4-7 gives recommended RISO values for  
different capacitive loads and is independent of the  
gain.  
stability by making multiple measurements of VOS  
instability would manifest itself as a greater unex-  
plained variability in VOS or as the railing of the output.  
;
4.3.3  
SOURCE RESISTANCES  
10000  
10k  
The input bias currents have two significant  
components; switching glitches that dominate at room  
temperature and below, and input ESD diode leakage  
currents that dominate at +85°C and above.  
GN < 2  
1k  
1000  
Make the resistances seen by the inputs small and  
equal. This minimizes the output offset caused by the  
input bias currents.  
100  
100  
GN  
= 5  
G
N = 10  
The inputs should see a resistance on the order of 10Ω  
to 1 kΩ at high frequencies (i.e., above 1 MHz). This  
helps minimize the impact of switching glitches, which  
are very fast, on overall performance. In some cases, it  
may be necessary to add resistors in series with the  
inputs to achieve this improvement in performance.  
10  
10  
1p  
10p  
1.E-11  
100p  
1.E-10  
1n  
1.E-09  
10n  
1.E-08  
100n  
1.E-12  
1.E-07  
CL (F)  
FIGURE 4-7:  
for Capacitive Loads.  
Recommended R  
values  
ISO  
DS22058C-page 24  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
After selecting RISO for your circuit, double check the  
resulting frequency response peaking and step  
response overshoot. Modify RISO's value until the  
response is reasonable. Bench evaluation and  
simulations with the MCP6V01 SPICE macro model  
(good for all of the MCP6V01/2/3 op amps) are helpful.  
4.3.7  
REDUCING UNDESIRED NOISE  
AND SIGNALS  
Reduce undesired noise and signals with:  
• Low bandwidth signal filters:  
- Minimizes random analog noise  
- Reduces interfering signals  
• Good PCB layout techniques:  
- Minimizes crosstalk  
4.3.6  
STABILIZING OUTPUT LOADS  
This family of auto-zeroed op amps has an output  
impedance (Figure 2-31 and Figure 2-32) that has a  
double zero when the gain is low. This can cause a  
large phase shift in feedback networks that have low  
resistance near the part’s bandwidth. This large phase  
shift can cause stability problems.  
- Minimizes parasitic capacitances and  
inductances that interact with fast switching  
edges  
• Good power supply design:  
- Isolation from other parts  
Figure 4-8 shows one circuit example that has low  
resistance near the part’s bandwidth. RF and CF set a  
pole at 0.16 kHz, so the noise gain (GN) is 1 V/V at the  
circuit’s bandwidth (roughly 1.3 MHz). The load seen  
by the op amp’s output at 1.3 MHz is RG||RL (99Ω).  
This is low enough to be a real concern.  
- Filtering of interference on supply line(s)  
4.3.8  
SUPPLY BYPASSING AND  
FILTERING  
With this family of operational amplifiers, the power  
supply pin (VDD for single supply) should have a local  
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm  
of the pin for good high-frequency performance.  
VIN  
RN  
100Ω  
VOUT  
MCP6V0X  
These parts also need a bulk capacitor (i.e., 1 µF or  
larger) within 100 mm to provide large, slow currents.  
This bulk capacitor can be shared with other low noise,  
analog parts.  
RL  
10.0 kΩ  
RG  
RF  
Additional filtering of high frequency power supply  
noise (e.g., switched mode power supplies) can be  
achieved using resistors. The resistors need to be  
small enough to prevent a large drop in VDD for the op  
amp, which would cause a reduced output range and  
possible load-induced power supply noise. The resis-  
tors also need to be large enough to dissipate little  
power when VDD is turned on and off quickly. The cir-  
cuit in Figure 4-10 gives good rejection out to 1 MHz for  
switched mode power supplies. Smaller resistors and  
capacitors are a better choice for designs where the  
power supply is reasonably quiet.  
100Ω  
10.0 kΩ  
CF  
0.1 µF  
FIGURE 4-8:  
Output Load Issue.  
To solve this problem, increase the resistive load to at  
least 3 kΩ. Methods to accomplish this task include:  
• Increase RG  
• Remove CF (relocate the filter)  
• Add a 3 kΩ resistor at the op amp’s output that is  
not in the signal path; see Figure 4-9  
VS_ANA  
143Ω  
143Ω  
VIN  
1/4W  
1/10W  
RN  
100Ω  
MCP6V0X  
RX  
3.01 kΩ  
0.1 µF  
100 µF  
100 µF  
VOUT  
MCP6V0X  
RG  
100Ω  
RF  
10.0 kΩ  
RL  
10.0 kΩ  
to other analog parts  
CF  
0.1 µF  
FIGURE 4-10:  
Additional Supply Filtering.  
FIGURE 4-9:  
One Solution To Output  
Load Issue.  
© 2008 Microchip Technology Inc.  
DS22058C-page 25  
MCP6V01/2/3  
4.3.9  
PCB DESIGN FOR DC PRECISION  
4.3.9.2  
Non-inverting and Inverting Amplifier  
Layout for Thermo-junctions  
In order to achieve DC precision on the order of ±1 µV,  
many physical errors need to be minimized. The design  
of the Printed Circuit Board (PCB), the wiring, and the  
thermal environment has a strong impact on the  
precision achieved. A poor PCB design can easily be  
more than 100 times worse than the MCP6V01/2/3 op  
amps minimum and maximum specifications.  
Figure 4-11 shows the recommended non-inverting  
and inverting gain amplifier circuits on one schematic.  
Usually, to minimize the input bias current related off-  
set, R1 is chosen to be R2||R3.  
The guard traces (with ground vias at the ends) help  
minimize the thermal gradients. The resistor layout  
cancels the resistor thermal voltages, assuming the  
temperature gradient is constant near the resistors:  
4.3.9.1  
Thermo-junctions  
Any time two dissimilar metals are joined together, a  
temperature dependent voltage appears across the  
junction (the Seebeck or thermo-junction effect). This  
effect is used in thermocouples to measure tempera-  
ture. The following are examples of thermo-junctions  
on a PCB:  
EQUATION 4-2:  
VOUT ≈ VPGP,  
VM = GND  
≈ -VMGM, VP = GND  
Where:  
• Components (resistors, op amps, …) soldered to  
a copper pad  
GM  
GP  
=
=
R3/R2, inverting gain magnitude  
1 + GM, non-inverting gain  
magnitude  
• Wires mechanically attached to the PCB  
• Jumpers  
VOS is neglected  
• Solder joints  
• PCB vias  
Typical thermo-junctions have temperature to voltage  
conversion coefficients of 10 to 100 µV/°C (sometimes  
higher).  
VOUT  
R3  
U1  
R2  
There are three basic approaches to minimizing  
thermo-junction effects:  
VM  
VP  
R1  
• Minimize thermal gradients  
• Cancel thermo-junction voltages  
• Minimize difference in thermal potential between  
metals  
R2  
R3  
VM  
VP  
U1  
MCP6V01  
VOUT  
R1  
FIGURE 4-11:  
PCB Layout and Schematic  
for Single Non-inverting and Inverting Amplifiers.  
Note:  
Changing the orientation of the resistors  
will usually cause a significant decrease in  
the cancellation of the thermal voltages.  
DS22058C-page 26  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
4.3.9.3  
Difference Amplifier Layout for  
Thermo-junctions  
4.3.9.4  
Dual Non-inverting Amplifier Layout  
for Thermo-junctions  
Figure 4-12 shows the recommended difference ampli-  
fier circuit. Usually, we choose R1 = R2 and R3 = R4.  
The dual op amp amplifiers shown in Figure 4-16 and  
Figure 4-17 produce a non-inverting difference gain  
greater than 1, and a common mode gain of 1 .They  
can use the layout shown in Figure 4-13. The gain set-  
ting resistors (R2) between the two sides are not com-  
bined so that the thermal voltages can be canceled.  
The guard traces (with ground vias at the ends) help  
minimize the thermal gradients. The resistor layout  
cancels the resistor thermal voltages, assuming the  
temperature gradient is constant near the resistors:  
The guard traces (with ground vias at the ends) help  
minimize the thermal gradients. The resistor layout  
cancels the resistor thermal voltages, assuming the  
temperature gradient is constant near the resistors:  
EQUATION 4-3:  
VOUT ≈ VREF + (VP – VM)GDM  
Where:  
EQUATION 4-4:  
Thermal voltages are approximately equal  
(VOA – VOB) ≈ (VIA – VIB)GDM  
(VOA + VOB)/2 ≈ (VIA + VIB)/2  
GDM  
=
R3/R1 = R4/R2, difference gain  
VOS is neglected  
Where:  
Thermal voltages are approximately equal  
GDM  
GCM  
=
=
1 + R3/R2, differential mode gain  
1, common mode gain  
VOS is neglected  
VOUT  
R4  
R2  
U1  
VM  
VP  
R1  
R3  
VREF  
VOB  
VOA  
U1  
R3  
R2  
R1  
R2  
R4  
R3  
R2  
R1  
VM  
U1  
VOUT  
VREF  
MCP6V01  
VP  
R1  
R3  
VIA VIB  
R1  
FIGURE 4-12:  
PCB Layout and Schematic  
VIA  
for Single Difference Amplifier.  
VOA  
½ MCP6V02  
U1  
Note:  
Changing the orientation of the resistors  
will usually cause a significant decrease in  
the cancellation of the thermal voltages.  
R2  
R2  
R3  
R3  
U1  
½ MCP6V02  
VOB  
VIB  
R1  
FIGURE 4-13:  
PCB Layout and Schematic  
for Dual Non-inverting Amplifier.  
Note: Changing the orientation of the resistors  
will usually cause a significant decrease in  
the cancellation of the thermal voltages.  
© 2008 Microchip Technology Inc.  
DS22058C-page 27  
MCP6V01/2/3  
4.3.9.5  
Other PCB Thermal Design Tips  
4.3.9.6  
Crosstalk  
In cases where an individual resistor needs to have its  
thermo-junction voltage cancelled, it can be split into  
two equal resistors as shown in Figure 4-14. To keep  
the thermal gradients near the resistors as small as  
possible, the layouts are symmetrical with a ring of  
metal around the outside. Make R1A = R1B = R1/2 and  
R2A = R2B = 2R2.  
DC crosstalk causes offsets that appear as a larger  
input offset voltage. Common causes include:  
• Common mode noise (remote sensors)  
• Ground loops (current return paths)  
• Power supply coupling  
Interference from the mains (usually 50 Hz or 60 Hz),  
and other AC sources, can also affect the DC perfor-  
mance. Non-linear distortion can convert these signals  
to multiple tones, included a DC shift in voltage. When  
the signal is sampled by an ADC, these AC signals can  
also be aliased to DC, causing an apparent shift in  
offset.  
R1A R1B  
R2A  
R2B  
R2A  
To reduce interference:  
R1A  
R1B  
- Keep traces and wires as short as possible  
- Use shielding (e.g., encapsulant)  
- Use ground plane (at least a star ground)  
- Place the input signal source near to the DUT  
- Use good PCB layout techniques  
R2B  
FIGURE 4-14:  
PCB Layout for Individual  
- Use a separate power supply filter (bypass  
capacitors) for these auto-zeroed op amps  
Resistors.  
Note:  
Changing the orientation of the resistors  
will usually cause a significant decrease in  
the cancellation of the thermal voltages.  
4.3.9.7  
Miscellaneous Effects  
Keep the resistances seen by the input pins as small  
and as near to equal as possible to minimize bias cur-  
rent related offsets.  
Minimize temperature gradients at critical components  
(resistors, op amps, heat sources, etc.):  
• Minimize exposure to gradients  
- Small components  
Make the (trace) capacitances seen by the input pins  
small and equal. This is helpful in minimizing switching  
glitch-induced offset voltages.  
- Tight spacing  
Bending a coax cable with a radius that is too small  
causes a small voltage drop to appear on the center or  
(the tribo-electric effect). Make sure the bending radius  
is large enough to keep the conductors and insulation  
in full contact.  
- Shield from air currents  
• Align with constant temperature (contour) lines  
- Place on PCB center line  
• Minimize magnitude of gradients  
- Select parts with lower power dissipation  
Mechanical stresses can make some capacitor types  
(such as ceramic) to output small voltages. Use more  
appropriate capacitor types in the signal path and  
minimize mechanical stresses and vibration.  
- Use same metal junctions on thermo-junc-  
tions that need to match  
- Use metal junctions with low temperature to  
voltage coefficients  
Humidity can cause electro-chemical potential voltages  
to appear in a circuit. Proper PCB cleaning helps, as  
does the use of encapsulants.  
- Large distance from heat sources  
- Ground plane underneath (large area)  
- FR4 gaps (no copper for thermal insulation)  
- Series resistors inserted into traces (adds  
thermal and electrical resistance)  
- Use heat sinks  
Make the temperature gradient point in one direction:  
• Add guard traces  
- Constant temperature curves follow the  
traces  
- Connect to ground plane  
• Shape any FR4 gaps  
- Constant temperature curves follow the  
edges  
DS22058C-page 28  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
4.4.2  
RTD SENSOR  
4.4  
Typical Applications  
The ratiometric circuit in Figure 4-17 conditions a three  
wire RTD. It corrects for the sensor’s wiring resistance  
by subtracting the voltage across the middle RW. The  
top R1 does not change the output voltage; it balances  
the op amp inputs. Failure (open) of the RTD is  
detected by an out of range voltage.  
4.4.1  
WHEATSTONE BRIDGE  
Many sensors are configured as Wheatstone bridges.  
Strain gauges and pressure sensors are two common  
examples. These signals can be small and the  
common mode noise large. Amplifier designs with high  
differential gain are desirable.  
Figure 4-15 shows how to interface to a Wheatstone  
bridge with a minimum of components. Because the  
circuit is not symmetric, the ADC input is single ended,  
and there is a minimum of filtering, the CMRR is good  
enough for moderate common mode noise.  
½ MCP6V02  
2.49 kΩ  
VDD  
100 nF  
RT  
20 kΩ  
R3  
100 kΩ  
RW  
0.01C  
100R  
VDD  
VDD  
3 kΩ  
3 kΩ  
VDD  
R
R
R1  
ADC  
R2  
2.55 kΩ  
0.2R  
0.2R  
10 nF  
10 nF  
2.49 kΩ  
1 µF  
RRTD  
100Ω  
ADC  
R
R
R2  
2.55 kΩ  
R1  
MCP6V01  
2.49 kΩ  
3 kΩ  
R3  
100 kΩ  
FIGURE 4-15:  
Simple Design.  
RW  
RW  
RB  
20 kΩ  
Figure 4-16 shows a higher performance circuit for  
Wheatstone bridges. This circuit is symmetric and has  
high CMRR. Using a differential input to the ADC helps  
with the CMRR.  
100 nF  
2.49 kΩ  
½ MCP6V02  
½ MCP6V02  
200 Ω  
FIGURE 4-17:  
RTD Sensor.  
The voltages at the input of the ADC can be calculated  
with the following:  
VDD  
1 µF  
R
R
R
R
20 kΩ  
3 kΩ  
10 nF  
GRTD = 1 + 2 ⋅ R3 ⁄ R2  
GW = GRTD – R3 ⁄ R1  
VDM = GRTD(VT – VB) + GWVW  
VDD  
200Ω  
1 µF  
ADC  
VT + VB + (GRTD + 1 – GW)VW  
VCM = ------------------------------------------------------------------------------  
2
Where:  
200Ω  
3 kΩ  
10 nF  
20 kΩ  
VT  
VB  
=
=
=
Voltage at the top of RRTD  
Voltage at the bottom of RRTD  
1 µF  
VW  
Voltage across top and middle  
RW’s  
200 Ω  
VCM  
VDM  
=
=
ADC’s common mode input  
ADC’s differential mode input  
½ MCP6V02  
High Performance Design.  
FIGURE 4-16:  
© 2008 Microchip Technology Inc.  
DS22058C-page 29  
MCP6V01/2/3  
The MCP9700A senses the temperature at its physical  
location. It needs to be at the same temperature as the  
cold junction (TCJ), and produces V3 (Figure 4-16).  
4.4.3  
THERMOCOUPLE SENSOR  
Figure 4-18 shows a simplified diagram of an amplifier  
and temperature sensor used in a thermocouple  
application. The type K thermocouple senses the  
temperature at the hot junction (THJ), and produces a  
voltage at V1 proportional to THJ (in °C). The amplifier’s  
gain is is set so that V4/THJ is 10 mV/°C. V3 represents  
the output of a temperature sensor, which produces a  
voltage proportional to the temperature (in °C) at the  
cold junction (TCJ), and with a 0.50V offset. V2 is set so  
that V4 is 0.50V when THJ – TCJ is 0°C.  
The MCP1541 produces a 4.10V output, assuming  
VDD is at 5.0V. This voltage, tied to a resistor ladder of  
4.100(RTH) and 1.3224(RTH), would produce a Theve-  
nin equivalent of 1.00V and 250(RTH). The  
1.3224(RTH) resistor is combined in parallel with the  
top right RTH resistor (in Figure 4-18), producing the  
0.5696(RTH) resistor.  
V4 should be converted to digital, then corrected for the  
thermocouple’s non-linearity. The ADC can use the  
MCP1541 as its voltage reference. Alternately, an  
absolute reference inside a PICmicro® can be used  
instead of the MCP1541.  
EQUATION 4-5:  
V1 ≈ THJ(40 µV/°C)  
V2 = (1.00V)  
4.4.4  
OFFSET VOLTAGE CORRECTION  
V3 = TCJ(10 mV/°C) + (0.50V)  
V4 = 250V1 + (V2 – V3)  
≈ (10 mV/°C) (THJ – TCJ) + (0.50V)  
Figure 4-20 shows a MCP6V01 correcting the input  
offset voltage of another op amp. R2 and C2 integrate  
the offset error seen at the other op amp’s input; the  
integration needs to be slow enough to be stable (with  
the feedback provided by R1 and R3).  
RTH = Thevenin Equivalent Resistance  
(hot junction  
at THJ  
)
(RTH  
)
(RTH  
)
R1  
R2  
R3  
V2  
V1  
V3  
40 µV/°C  
Type K  
Thermocouple  
VIN  
VOUT  
C
(RTH)/250  
(RTH)/250  
C2  
MCP6V01  
MCP6XXX  
V4  
3 kΩ  
MCP6V01  
R2  
(cold junction  
C
VDD/2  
at TCJ  
)
(RTH  
)
(RTH  
)
FIGURE 4-20:  
Offset Correction.  
FIGURE 4-18:  
Simplified Circuit.  
Thermocouple Sensor;  
4.4.5 PRECISION COMPARATOR  
Use high gain before a comparator to improve the  
latter’s performance. Do not use MCP6V01/2/3 as a  
comparator by itself; the VOS correction circuitry does  
not operate properly without a feedback loop.  
Figure 4-19 shows a more complete implementation of  
this circuit. The dashed red arrow indicates a thermally  
conductive connection between the thermocouple and  
the MCP9700A; it needs to be very short and have low  
thermal resistance.  
MCP6V01  
VIN  
RTH = Thevenin Equivalent Resistance (e.g.: 10 kΩ)  
R1  
VDD  
0.5696(RTH  
C
)
4.100(RTH  
)
MCP1541  
R3  
R4  
R2  
1 kΩ  
R5  
VOUT  
(RTH)/250  
(RTH)/250  
Type K  
VDD/2  
MCP6V01  
V1  
MCP6541  
VDD  
C
FIGURE 4-21:  
Precision Comparator.  
MCP9700A  
V4  
(RTH  
)
3 kΩ  
(RTH  
)
FIGURE 4-19:  
Thermocouple Sensor.  
DS22058C-page 30  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
5.5  
Analog Demonstration and  
Evaluation Boards  
5.0  
DESIGN AIDS  
Microchip provides the basic design aids needed for  
the MCP6V01/2/3 family of op amps.  
Microchip offers a broad spectrum of Analog Demon-  
stration and Evaluation Boards that are designed to  
help customers achieve faster time to market. For a  
complete listing of these boards and their correspond-  
ing user’s guides and technical information, visit the  
Microchip web site at www.microchip.com/analog  
tools.  
5.1  
SPICE Macro Model  
The latest SPICE macro model for the MCP6V01/2/3  
op amps is available on the Microchip web site at  
www.microchip.com. This model is intended to be an  
initial design tool that works well in the op amp’s linear  
region of operation over the temperature range. See  
the model file for information on its capabilities.  
Some boards that are especially useful are:  
• MCP6V01 Thermocouple Auto-Zeroed Reference  
Design  
Bench testing is a very important part of any design and  
cannot be replaced with simulations. Also, simulation  
results using this macro model need to be validated by  
comparing them to the data sheet specifications and  
characteristic curves.  
• MCP6XXX Amplifier Evaluation Board 1  
• MCP6XXX Amplifier Evaluation Board 2  
• MCP6XXX Amplifier Evaluation Board 3  
• MCP6XXX Amplifier Evaluation Board 4  
• Active Filter Demo Board Kit  
5.2  
FilterLab® Software  
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP  
Evaluation Board  
Microchip’s FilterLab® software is an innovative  
software tool that simplifies analog active filter (using  
op amps) design. Available at no cost from the Micro-  
chip web site at www.microchip.com/filterlab, the Fil-  
ter-Lab design tool provides full schematic diagrams of  
the filter circuit with component values. It also outputs  
the filter circuit in SPICE format, which can be used  
with the macro model to simulate actual filter perfor-  
mance.  
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP  
Evaluation Board  
5.6  
Application Notes  
The following Microchip Application Notes are  
available on the Microchip web site at www.microchip.  
com/appnotes and are recommended as supplemental  
reference resources.  
5.3  
Mindi™ Circuit Designer &  
Simulator  
ADN003: “Select the Right Operational Amplifier for  
your Filtering Circuits”, DS21821  
AN722: “Operational Amplifier Topologies and DC  
Specifications”, DS00722  
Microchip’s Mindi™ Circuit Designer & Simulator aids  
in the design of various circuits useful for active filter,  
amplifier and power management applications. It is a  
free online circuit designer & simulator available from  
the Microchip web site at www.microchip.com/mindi.  
This interactive circuit designer & simulator enables  
designers to quickly generate circuit diagrams, and  
simulate circuits. Circuits developed using the Mindi  
Circuit Designer & Simulator can be downloaded to a  
personal computer or workstation.  
AN723: “Operational Amplifier AC Specifications and  
Applications”, DS00723  
AN884: “Driving Capacitive Loads With Op Amps”,  
DS00884  
AN990: “Analog Sensor Conditioning Circuits – An  
Overview”, DS00990  
These application notes and others are listed in the  
design guide:  
5.4  
Microchip Advanced Part Selector  
(MAPS)  
“Signal Chain Design Guide”, DS21825  
MAPS is a software tool that helps efficiently identify  
Microchip devices that fit a particular design require-  
ment. Available at no cost from the Microchip website  
at www.microchip.com/maps, the MAPS is an overall  
selection tool for Microchip’s product portfolio that  
includes Analog, Memory, MCUs and DSCs. Using this  
tool, a customer can define a filter to sort features for a  
parametric search of devices and export side-by-side  
technical comparison reports. Helpful links are also  
provided for Data sheets, Purchase and Sampling of  
Microchip parts.  
© 2008 Microchip Technology Inc.  
DS22058C-page 31  
MCP6V01/2/3  
NOTES:  
DS22058C-page 32  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
6.0  
6.1  
PACKAGING INFORMATION  
Package Marking Information  
8-Lead DFN (4x4) (MCP6V02)  
Example  
XXXXXX  
XXXXXX  
YYWW  
6V02  
e
3
E/MD^
0750  
256  
NNN  
8-Lead SOIC (150 mil)  
Example:  
MCP6VO1E  
XXXXXXXX  
e
3
SN 0750  
XXXXYYWW  
256  
NNN  
Example:  
8-Lead TDFN (2x3) (MCP6V01, MCP6V03)  
Device  
Code  
XXX  
AAA  
838  
25  
MCP6V01  
AAA  
AAB  
YWW  
NN  
MCP6V03  
Note: Applies to 8-Lead  
2x3 TDFN  
Legend: XX...X Customer-specific information  
Y
YY  
WW  
NNN  
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
e
3
Pb-free JEDEC designator for Matte Tin (Sn)  
*
This package is Pb-free. The Pb-free JEDEC designator (  
can be found on the outer packaging for this package.  
)
e3  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
© 2008 Microchip Technology Inc.  
DS22058C-page 33  
MCP6V01/2/3  
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$ꢃꢖꢐꢕꢖꢘꢃꢜ +ꢌꢖꢘꢄꢕꢊꢕꢛꢒ !ꢐꢉꢗꢃꢄꢛ )6 ;ꢀꢝꢀ)  
DS22058C-page 34  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ& ꢄꢈꢈꢆ'ꢎꢊꢈꢋ(ꢃꢆꢕ&ꢑꢗꢆMꢆꢑꢄ))ꢒ*ꢐꢆ+ꢛꢜꢚꢆ  ꢆ!ꢒꢅ"ꢆ#&',-$  
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ꢙꢁ ꢞꢅ#ꢃꢛꢄꢃꢎꢃꢖꢉꢄꢏꢅ)ꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ  
ꢝꢁ !ꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅ!ꢅꢉꢄꢋꢅ%ꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅ$ꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅ6ꢁꢀ'ꢅꢑꢑꢅꢜꢌꢐꢅꢇꢃꢋꢌꢁ  
 ꢁ !ꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢛꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢛꢅꢜꢌꢐꢅ"#$%ꢅ&ꢀ ꢁ'$ꢁ  
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,%-* ,ꢌꢎꢌꢐꢌꢄꢖꢌꢅ!ꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢜꢈꢐꢜꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ  
$ꢃꢖꢐꢕꢖꢘꢃꢜ +ꢌꢖꢘꢄꢕꢊꢕꢛꢒ !ꢐꢉꢗꢃꢄꢛ )6 ;6'?(  
© 2008 Microchip Technology Inc.  
DS22058C-page 35  
MCP6V01/2/3  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ& ꢄꢈꢈꢆ'ꢎꢊꢈꢋ(ꢃꢆꢕ&ꢑꢗꢆMꢆꢑꢄ))ꢒ*ꢐꢆ+ꢛꢜꢚꢆ  ꢆ!ꢒꢅ"ꢆ#&',-$  
ꢑꢒꢊꢃ% -ꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢚꢉꢛꢌꢅꢋꢐꢉꢗꢃꢄꢛꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅ$ꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢚꢉꢛꢃꢄꢛꢅ#ꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢜ*..ꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑ.ꢜꢉꢖꢚꢉꢛꢃꢄꢛ  
DS22058C-page 36  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢑꢗꢆMꢆ.ꢙ+ꢙꢚꢛ/0ꢆ  ꢆ!ꢒꢅ"ꢆ#1ꢍꢏꢑ$  
ꢑꢒꢊꢃ% -ꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢚꢉꢛꢌꢅꢋꢐꢉꢗꢃꢄꢛꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅ$ꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢚꢉꢛꢃꢄꢛꢅ#ꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢜ*..ꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑ.ꢜꢉꢖꢚꢉꢛꢃꢄꢛ  
© 2008 Microchip Technology Inc.  
DS22058C-page 37  
MCP6V01/2/3  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢑꢗꢆMꢆ.ꢙ+ꢙꢚꢛ/0ꢆ  ꢆ!ꢒꢅ"ꢆ#1ꢍꢏꢑ$  
ꢑꢒꢊꢃ% -ꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢚꢉꢛꢌꢅꢋꢐꢉꢗꢃꢄꢛꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅ$ꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢚꢉꢛꢃꢄꢛꢅ#ꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢜ*..ꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑ.ꢜꢉꢖꢚꢉꢛꢃꢄꢛ  
DS22058C-page 38  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
APPENDIX A: REVISION HISTORY  
Revision C (December 2008)  
The following is the list of modifications:  
1. Added the 8-lead, 2x3 TDFN package for the  
MCP6V01 and MCP6V03 devices.  
2. Corrected the IMD specification in Table 1-2.  
3. Added 8-lead, 2x3 TDFN package information to  
Thermal Characteristic table.  
4. Added information on the Exposed Thermal Pad  
(EP) for the 8-lead, 2x3 TDFN and 8-lead, 4x4  
DFN packages.  
5. Added Section 4.3.6 “Stabilizing Output  
Loads”  
6. Other minor typographical corrections.  
Revision B (June 2008)  
The following is the list of modifications:  
1. Updated the specifications and their conditions.  
2. Corrected the Timing Diagrams.  
3. Added to the Test Circuits.  
4. Added RISO (see Figure 4-6) to all circuit  
diagrams.  
5. Added the Typical Performance Curves.  
6. Corrected  
Information.  
and  
expanded  
Applications  
7. Minor edits due to change in production status.  
8. Added Appendix B, Offset Related Test  
Screens.  
Revision A (September 2007)  
• Original Release of this Document.  
© 2008 Microchip Technology Inc.  
DS22058C-page 41  
MCP6V01/2/3  
We use production screens to ensure the quality of our  
outgoing products. These screens are set at wider lim-  
its to eliminate any fliers; see Table B-1.  
APPENDIX B: OFFSET RELATED  
TEST SCREENS  
Input offset voltage related specifications in the DC  
spec table (Table 1-1) are based on bench measure-  
ments (see Section 2.1 “DC Input Precision”). These  
measurements are much more accurate because:  
• More compact circuit  
• Soldered parts on the PCB  
• More time spent averaging (reduces noise)  
• Better temperature control  
- Reduced temperature gradients  
- Greater accuracy  
TABLE B-1:  
OFFSET RELATED TEST SCREENS  
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,  
V
OUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).  
Parameters  
Sym Min Max Units  
Conditions  
Input Offset  
Input Offset Voltage  
VOS  
-10  
—
+10  
—
µV  
TA = +25°C (Note 1, Note 2)  
Input Offset Voltage Drift with Temperature TC1  
(linear Temp. Co.)  
nV/°C TA = -40 to +125°C (Note 3)  
Power Supply Rejection  
Common Mode  
PSRR 115  
—
dB  
(Note 1)  
Common Mode Rejection  
CMRR 106  
CMRR 116  
—
—
dB  
dB  
VDD = 1.8V, VCM = -0.2V to 2.0V (Note 1)  
VDD = 5.5V, VCM = -0.2V to 5.7V (Note 1)  
Open-Loop Gain  
DC Open-Loop Gain (large signal)  
AOL  
AOL  
114  
122  
—
—
dB  
dB  
VDD = 1.8V, VOUT = 0.2V to 1.6V (Note 1)  
VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1)  
Note 1: Due to thermal junctions and other errors in the production environment, these specifications are only screened in  
production.  
2:  
VOS is also sample screened at +125°C.  
3: TC1 is not measured in production.  
DS22058C-page 42  
© 2008 Microchip Technology Inc.  
MCP6V01/2/3  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
Examples:  
PART NO.  
Device  
–X  
/XXX  
a)  
MCP6V01T-E/SN: Extended temperature,  
Temperature  
Range  
Package  
8LD SOIC package.  
MCP6V01-E/MNY:Extended temperature,  
8LD 2x3 TDFN package.  
b)  
a)  
b)  
MCP6V02-E/MD: Extended temperature,  
8LD 4x4 DFN package.  
MCP6V02T-E/SN: Tape and Reel,  
Extended temperature,  
Device:  
MCP6V01  
Single Op Amp  
MCP6V01T Single Op Amp  
(Tape and Reel for 2x3 TDFN andSOIC)  
Dual Op Amp  
MCP6V02T Dual Op Amp  
(Tape and Reel for 4×4 DFN and SOIC)  
Single Op Amp with Chip Select  
MCP6V02  
8LD SOIC package.  
a)  
b)  
MCP6V03-E/SN: Extended temperature,  
8LD SOIC package.  
MCP6V03-E/MNY:Extended temperature,  
8LD 2x3 TDFN package.  
MCP6V03  
MCP6V03T Single Op Amp with Chip Select  
(Tape and Reel for SOIC)  
Temperature Range:  
Package:  
E
= -40°C to +125°C  
MD  
=
=
=
Plastic Dual Flat, No-Lead (4×4x0.9 mm), 8-lead  
(MCP6V02 only)  
Plastic Dual Flat No Lead (2x3x0.75 mm), 8-lead  
(MCP6V01, MCP6V03)  
MNY *  
SN  
Plastic SOIC (150mil Body), 8-lead  
* Y = nickel palladium gold manufacturing designator. Only  
available on the TDFN package.  
© 2008 Microchip Technology Inc.  
DS22058C-page 43  
MCP6V01/2/3  
NOTES:  
DS22058C-page 44  
© 2008 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights.  
Trademarks  
The Microchip name and logo, the Microchip logo, Accuron,  
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,  
PICSTART, rfPIC, SmartShunt and UNI/O are registered  
trademarks of Microchip Technology Incorporated in the  
U.S.A. and other countries.  
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,  
SEEVAL, SmartSensor and The Embedded Control Solutions  
Company are registered trademarks of Microchip Technology  
Incorporated in the U.S.A.  
Analog-for-the-Digital Age, Application Maestro, CodeGuard,  
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,  
ECONOMONITOR, FanSense, In-Circuit Serial  
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB  
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,  
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,  
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total  
Endurance, WiperLock and ZENA are trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2008, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
Printed on recycled paper.  
Microchip received ISO/TS-16949:2002 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
© 2008 Microchip Technology Inc.  
DS22058C-page 45  
WORLDWIDE SALES AND SERVICE  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
Asia Pacific Office  
Suites 3707-14, 37th Floor  
Tower 6, The Gateway  
Harbour City, Kowloon  
Hong Kong  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
India - Bangalore  
Tel: 91-80-4182-8400  
Fax: 91-80-4182-8422  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
2355 West Chandler Blvd.  
Chandler, AZ 85224-6199  
Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://support.microchip.com  
Web Address:  
www.microchip.com  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
India - New Delhi  
Tel: 91-11-4160-8631  
Fax: 91-11-4160-8632  
France - Paris  
Tel: 33-1-69-53-63-20  
Fax: 33-1-69-30-90-79  
India - Pune  
Tel: 91-20-2566-1512  
Fax: 91-20-2566-1513  
Australia - Sydney  
Tel: 61-2-9868-6733  
Fax: 61-2-9868-6755  
Atlanta  
Duluth, GA  
Tel: 678-957-9614  
Fax: 678-957-1455  
Germany - Munich  
Tel: 49-89-627-144-0  
Fax: 49-89-627-144-44  
Japan - Yokohama  
Tel: 81-45-471- 6166  
Fax: 81-45-471-6122  
China - Beijing  
Tel: 86-10-8528-2100  
Fax: 86-10-8528-2104  
Italy - Milan  
Tel: 39-0331-742611  
Fax: 39-0331-466781  
Korea - Daegu  
Tel: 82-53-744-4301  
Fax: 82-53-744-4302  
Boston  
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Tel: 86-28-8665-5511  
Fax: 86-28-8665-7889  
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Tel: 774-760-0087  
Fax: 774-760-0088  
Netherlands - Drunen  
Tel: 31-416-690399  
Fax: 31-416-690340  
Korea - Seoul  
China - Hong Kong SAR  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
Tel: 82-2-554-7200  
Fax: 82-2-558-5932 or  
82-2-558-5934  
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Itasca, IL  
Tel: 630-285-0071  
Fax: 630-285-0075  
Spain - Madrid  
Tel: 34-91-708-08-90  
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Tel: 86-25-8473-2460  
Fax: 86-25-8473-2470  
Malaysia - Kuala Lumpur  
Tel: 60-3-6201-9857  
Fax: 60-3-6201-9859  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
UK - Wokingham  
Tel: 44-118-921-5869  
Fax: 44-118-921-5820  
China - Qingdao  
Tel: 86-532-8502-7355  
Fax: 86-532-8502-7205  
Malaysia - Penang  
Tel: 60-4-227-8870  
Fax: 60-4-227-4068  
Detroit  
Farmington Hills, MI  
Tel: 248-538-2250  
Fax: 248-538-2260  
China - Shanghai  
Tel: 86-21-5407-5533  
Fax: 86-21-5407-5066  
Philippines - Manila  
Tel: 63-2-634-9065  
Fax: 63-2-634-9069  
Kokomo  
Kokomo, IN  
Tel: 765-864-8360  
Fax: 765-864-8387  
China - Shenyang  
Tel: 86-24-2334-2829  
Fax: 86-24-2334-2393  
Singapore  
Tel: 65-6334-8870  
Fax: 65-6334-8850  
China - Shenzhen  
Tel: 86-755-8203-2660  
Fax: 86-755-8203-1760  
Taiwan - Hsin Chu  
Tel: 886-3-572-9526  
Fax: 886-3-572-6459  
Los Angeles  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
China - Wuhan  
Tel: 86-27-5980-5300  
Fax: 86-27-5980-5118  
Taiwan - Kaohsiung  
Tel: 886-7-536-4818  
Fax: 886-7-536-4803  
Santa Clara  
Santa Clara, CA  
Tel: 408-961-6444  
Fax: 408-961-6445  
China - Xiamen  
Tel: 86-592-2388138  
Fax: 86-592-2388130  
Taiwan - Taipei  
Tel: 886-2-2500-6610  
Fax: 886-2-2508-0102  
Toronto  
Mississauga, Ontario,  
Canada  
Tel: 905-673-0699  
Fax: 905-673-6509  
China - Xian  
Tel: 86-29-8833-7252  
Fax: 86-29-8833-7256  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Fax: 66-2-694-1350  
China - Zhuhai  
Tel: 86-756-3210040  
Fax: 86-756-3210049  
01/02/08  
DS22058C-page 46  
© 2008 Microchip Technology Inc.  

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