MCP6V67-E/MS_技术文档

MCP6V66/6U/7/9

80 µA, 1 MHz Zero-Drift Op Amps

Features

General Description

• High DC Precision:

The Microchip Technology Inc. MCP6V66/6U/7/9

family of operational amplifiers provides input offset

voltage correction for very low offset and offset drift.

These devices have a gain bandwidth product of

1 MHz (typical). They are unity-gain stable, have

virtually no 1/f noise and have good Power Supply

Rejection Ratio (PSRR) and Common Mode Rejection

Ratio (CMRR). These products operate with a single

supply voltage as low as 1.8V, while drawing

80 µA/amplifier (typical) of quiescent current.

- V_OSDrift: ±150 nV/°C (maximum)

- V_OS: ±25 µV (maximum)

- A_OL: 110 dB (minimum, V_DD= 5.5V)

- PSRR: 110 dB (minimum, V_DD= 5.5V)

- CMRR: 111 dB (minimum, V_DD= 5.5V)

- E_ni: 0.54 µV_P-P(typical), f = 0.1 Hz to 10 Hz

- E_ni: 0.17 µV_P-P(typical), f = 0.01 Hz to 1 Hz

• Enhanced EMI Protection:

The Microchip Technology Inc. MCP6V66/6U/7/9 op

amps are offered in single (MCP6V66 and

MCP6V66U), dual (MCP6V67) and quad (MCP6V69)

packages. They were designed using an advanced

CMOS process.

- Electromagnetic Interference Rejection Ratio

(EMIRR) at 1.8 GHz: 101 dB

• Low Power and Supply Voltages:

- I_Q: 80 µA/amplifier (typical)

- Wide Supply Voltage Range: 1.8V to 5.5V

• Small Packages:

Package Types

- Singles in SC70, SOT-23

MCP6V66

SOT-23

MCP6V67

MSOP

- Duals in MSOP-8, 2x3 TDFN

- Quads in TSSOP-14

V_DD

1

V_DDV_OUTA

8

7

6

5

V_OUT

V_SS

• Easy to Use:

1

5

4

V_OUTB

2

3

4

- Rail-to-Rail Input/Output

V_INA

–

+

2

3

V_INB

–

+

- Gain Bandwidth Product: 1 MHz (typical)

- Unity Gain Stable

V_IN+

V_IN–

V_SS

• Extended Temperature Range: -40°C to +125°C

MCP6V66U

SC70, SOT-23

MCP6V67

2×3 TDFN *

Typical Applications

• Portable Instrumentation

• Sensor Conditioning

V_OUTA

V_DD

1

8

V_IN+

V_SS

V_DD

1

2

3

5

V_INA–

V_OUTB

2

3

4

7

6

5

EP

9

• Temperature Measurement

• DC Offset Correction

V_INA+

V_INB

–

+

V_IN–

V_OUT

4

V_SS

• Medical Instrumentation

Design Aids

MCP6V69

TSSOP

• SPICE Macro Models

• FilterLab^®Software

V

1

14

13

12

11

10

9

V_OUTA

OUTD

V

–

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

2

3

4

5

6

7

V_INA

V_DD

V_INB

–

+

IND

+

IND

SS

V

+

–

INC

Related Parts

V_INC

–

• MCP6V11/1U/2/4: Zero-Drift, Low Power

• MCP6V31/1U/2/4: Zero-Drift, Low Power

• MCP6V71/1U/2/4: Zero-Drift, 2 MHz

• MCP6V81/1U: Zero-Drift, 5 MHz

V_OUTC

V_OUTB

8

* Includes Exposed Thermal Pad (EP); see Table 3-1.

• MCP6V91/1U: Zero-Drift, 10 MHz

 2019 Microchip Technology Inc.

DS20006266A-page 1

MCP6V66/6U/7/9

Typical Application Circuit

R₁

R₃

V

V_OUT

IN

-

R₂

R₄

R₅

C₂

+

U₁

MCP6XXX

V_DD/2

-

R₂

V_DD/2

+

U₂

MCP6V66

Offset Voltage Correction for Power Driver

DS20006266A-page 2

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

1.0

1.1

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V_DD– V_SS.................................................................................................................................................................6.5V

Current at Input Pins ..............................................................................................................................................±2 mA

Analog Inputs (V_IN+ and V_IN-) (Note 1).....................................................................................V_SS– 1.0V to V_DD+ 1.0V

All Other Inputs and Outputs ....................................................................................................V_SS– 0.3V to V_DD+ 0.3V

Difference Input Voltage .................................................................................................................................|V_DD– V_SS

|

Output Short Circuit Current ...........................................................................................................................Continuous

Current at Output and Supply Pins ......................................................................................................................±30 mA

Storage Temperature .............................................................................................................................-65°C to +150°C

Maximum Junction Temperature .......................................................................................................................... +150°C

ESD protection on all pins (HBM, CDM, MM)

MCP6V66/6U 4 kV, 1.5 kV, 400V

MCP6V67/9  4 kV, 1.5 kV, 300V

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only, and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note 1: See Section 4.2.1 “Rail-to-Rail Inputs”.

1.2

Specifications

DC ELECTRICAL SPECIFICATIONS

TABLE 1-1:

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to +5.5V, V_SS= GND,

V_CM= V_DD/3, V_OUT= V_DD/2, V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF (refer to Figures 1-4 and 1-5).

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Input Offset

Input Offset Voltage

V_OS

TC₁

-25

—

+25

µV

T_A= +25°C

Input Offset Voltage Drift with

Temperature (Linear Temp. Co.)

-150

+150

nV/°C T_A= -40 to +125°C,

(Note 1)

Input Offset Voltage Quadratic

Temp. Co.

TC₂

—

-30

—

pV/°C²T_A= -40 to +125°C

Input Offset Voltage Aging

∆V_OS

±0.45

µV

dB

408 hours Life Test at

+150°,

measured at +25°C.

Power Supply Rejection Ratio

Input Bias Current and Impedance

Input Bias Current

PSRR

110

134

—

I_B

-50

—

±1

+20

+50

—

pA

Input Bias Current across

Temperature

T_A= +85°C

I_B

0

+0.2

±60

+1.5

+200

—

nA

T_A= +125°C

Input Offset Current

I_OS

Z_CM

-200

—

pA

Input Offset Current across

Temperature

±50

pA

T_A= +85°C

-800

—

±50

10¹³||8

+800

—

pA

T_A= +125°C

Common Mode Input Impedance

Ω||pF

Note 1: For design guidance only; not tested.

 2019 Microchip Technology Inc.

DS20006266A-page 3

MCP6V66/6U/7/9

TABLE 1-1:

DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to +5.5V, V_SS= GND,

V_CM= V_DD/3, V_OUT= V_DD/2, V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF (refer to Figures 1-4 and 1-5).

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Differential Input Impedance

Z_DIFF

—

10¹³||8

—

Ω||pF

Common Mode

Input Voltage Range Low

V_CML

—

V_SS-0.2

V

Common Mode

Input Voltage Range High

V_CMHV_DD+0.3

—

Common Mode Rejection Ratio

CMRR

101

111

128

134

dB

V_DD= 1.8V,

V_CM= -0.2V to 2.1V

V

_DD= 5.5V,

V_CM= -0.2V to 5.8V

Open-Loop Gain

DC Open-Loop Gain (Large Signal)

A_OL

95

146

158

—

dB

V_DD= 1.8V,

_OUT= 0.3V to 1.6V

V

110

V_DD= 5.5V,

V_OUT= 0.3V to 5.3V

Output

Minimum Output Voltage Swing

V_OL

V_SS

—

V_SS+35

V_SS+3.5

V_DD–35

V_DD–3.5

V_SS+121

—

mV

R_L= 2 kΩ, G = +2,

0.5V input overdrive

R_L= 20 kΩ, G = +2,

0.5V input overdrive

Maximum Output Voltage Swing

Output Short Circuit Current

V_OHV_DD-121

V_DD

—

R_L= 2 kΩ, G = +2,

0.5V input overdrive

V_OH

—

R_L= 20 kΩ, G = +2,

0.5V input overdrive

I_SC

—

±7

—

mA

V_DD= 1.8V

V_DD= 5.5V

±23

Power Supply

Supply Voltage

V_DD

I_Q

1.8

40

—

80

—

5.5

130

1.6

V

µA

V

Quiescent Current per Amplifier

Power-on Reset (POR) Trip Voltage

I_O= 0

V_POR

0.9

Note 1: For design guidance only; not tested.

DS20006266A-page 4

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

TABLE 1-2:

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to +5.5V, V_SS= GND,

V_CM= V_DD/3, V_OUT= V_DD/2, V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF (refer to Figures 1-4 and 1-5).

Parameters

Sym. Min. Typ. Max. Units

Conditions

Amplifier AC Response

Gain Bandwidth Product

Slew Rate

GBWP

SR

—

1

—

MHz

V/µs

°C

0.45

60

Phase Margin

PM

G = +1

Amplifier Noise Response

Input Noise Voltage

E_ni

e_ni

i_ni

—

0.17

0.54

26

—

µV_P-Pf = 0.01 Hz to 1 Hz

µV_P-Pf = 0.1 Hz to 10 Hz

nV/√Hz f < 2 kHz

Input Noise Voltage Density

Input Noise Current Density

Amplifier Distortion (Note 1)

Intermodulation Distortion (AC)

5

fA/√Hz

IMD

—

48

—

µV_PKV_CMtone = 50 mV_PKat 1 kHz,

G_N= 11, RTI

Amplifier Step Response

Start-Up Time

t_STR

t_STL

—

250

30

—

µs

G = +1, 0.1% V_OUTsettling (Note 2)

Offset Correction Settling Time

G = +1, V_INstep of 2V,

V_OSwithin 100 µV of its final value

Output Overdrive Recovery Time

t_ODR

—

60

—

µs

G = -10, ±0.5V input overdrive to V_DD/2,

V_IN50% point to V_OUT90% point (Note 3)

EMI Protection

EMI Rejection Ratio

EMIRR

—

80

96

—

dB

V_IN= 0.1 V_PK, f = 400 MHz

V_IN= 0.1 V_PK, f = 900 MHz

V_IN= 0.1 V_PK, f = 1800 MHz

V_IN= 0.1 V_PK, f = 2400 MHz

101

102

Note 1: These parameters were characterized using the circuit in Figure 1-6. In Figures 2-36 and 2-37, there is an

IMD tone at DC, a residual tone at 1 kHz and other IMD tones and clock tones. IMD is Referred to

Input (RTI).

2: High gains behave differently; see Section 4.3.2 “Offset at Power-Up”.

3:

TABLE 1-3:

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V_DD= +1.8V to +5.5V, V_SS= GND

t

_{STL and}t_ODRinclude some uncertainty due to clock edge timing.

TEMPERATURE SPECIFICATIONS

Parameters

Temperature Ranges

Sym.

Min.

Typ.

Max.

Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

T_A

-40

-65

—

+125

+150

°C

Note 1

Thermal Package Resistances

Thermal Resistance, 5LD-SC70

_JA

—

209

201

53

—

°C/W

Thermal Resistance, 5LD-SOT-23

Thermal Resistance, 8L-2x3 TDFN

Thermal Resistance, 8L-MSOP

Thermal Resistance, 14L-TSSOP

211

100

Note 1: Operation must not cause T_Jto exceed the Maximum Junction Temperature specification (+150°C).

 2019 Microchip Technology Inc.

DS20006266A-page 5

MCP6V66/6U/7/9

1.3

Timing Diagrams

1.4

Test Circuits

The circuits used for most DC and AC tests are shown

in Figures 1-4 and 1-5. Lay the bypass capacitors out

as discussed in Section 4.3.9 “Supply Bypassing

and Filtering”. R_Nis equal to the parallel combination

of R_Fand R_Gto minimize bias current effects.

1.8V to 5.5V

1.8V

0V

V_DD

t_STR

1.001(V_DD/3)

0.999(V_DD/3)

V_OUT

V_DD

1 µF

R_N

V_IN

FIGURE 1-1:

Amplifier Start-Up.

R_ISO

C_L

V_OUT

+

-

MCP6V6X

V_IN

R_L

100 nF

R_F

V_DD/3

t_STL

V_OS+ 100 µV

_OS– 100 µV

V_L

R_G

V_OS

V

FIGURE 1-4:

AC and DC Test Circuit for

Most Noninverting Gain Conditions.

FIGURE 1-2:

Offset Correction Settling

Time.

V_DD

1 µF

R_N

V_DD/3

V_IN

R_ISO

C_L

V_OUT

+

-

MCP6V6X

t_ODR

R_L

100 nF

R_F

V_IN

V_DD

V_L

R_G

t_ODR

V_OUT

V_DD/2

FIGURE 1-5:

AC and DC Test Circuit for

Most Inverting Gain Conditions.

V_SS

The circuit in Figure 1-6 tests the input’s dynamic

FIGURE 1-3:

Output Overdrive Recovery.

behavior (i.e., IMD, t_STR, t_STLand t_ODR). The

potentiometer balances the resistor network (V_OUT

should equal V_REFat DC). The op amp’s Common

Mode Input Voltage is V_CM= V_IN/2. The error at the

input (V_ERR) appears at V_OUTwith a noise gain of

10 V/V.

11.0 kΩ 100 kΩ 500Ω

0.1%

0.1% 25 turn

V_REF= V_DD/3

V_DD

R_ISO

0Ω

1 µF

V_OUT

V_IN

100 nF

C_L

30 pF

R_L

open

MCP6V6X

V_L

11.0 kΩ

100 kΩ 249Ω

1%

0.1%

FIGURE 1-6:

Test Circuit for Dynamic

Input Behavior.

DS20006266A-page 6

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF.

2.1

DC Input Precision

8

6

50%

45%

40%

35%

30%

25%

20%

15%

10%

5%

Representative Part

V_CM= V_CML

28 Samples

T_A= 25ºC

4

V_DD= 5.5V

2

V_DD= 1.8V

0

-2

-4

-6

-8

T_A= -40°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

0%

-2 -1.5 -1 -0.5 0 0.5

1

1.5

2

2.5

3

3.5

4

Input Offset Voltage (µV)

Power Supply Voltage (V)

FIGURE 2-1:

Input Offset Voltage.

FIGURE 2-4:

Input Offset Voltage vs.

Power Supply Voltage with V_CM= V_CML

.

8

60%

Representative Part

V_CM= V_CMH

28 Samples

_A= -40°C to +125°C

6

4

T

50%

40%

30%

20%

10%

0%

T_A= -40°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

V_DD= 5.5V

2

V_DD= 1.8V

0

-2

-4

-6

-8

-12 -10 -8 -6 -4 -2

0

2

4

6

8

10 12

Input Offset Voltage Drift; TC₁(nV/°C)

Power Supply Voltage (V)

FIGURE 2-2:

Input Offset Voltage Drift.

FIGURE 2-5:

Input Offset Voltage vs.

Power Supply Voltage with V_CM= V_CMH

.

8

45%

Representative Part

V_DD= 1.8V

28 Samples

T_A= -40°C to +125°C

6

4

40%

35%

30%

25%

20%

15%

10%

5%

2

V

_DD= 5.5V

0

V_DD= 1.8V

-2

-4

-6

-8

T_A

=

- 40°C

+25°C

+85°C

0%

T_A= +125°C

-80 -60 -40 -20

0

20

40

60

80

Input Offset Voltage Quadratric Temp Co;

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Output Voltage (V)

TC₂(pV/°C²)

FIGURE 2-3:

Input Offset Voltage

FIGURE 2-6:

Input Offset Voltage vs.

Quadratic Temp. Co.

Output Voltage with V_DD= 1.8V.

 2019 Microchip Technology Inc.

DS20006266A-page 7

MCP6V66/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF.

8

6

160

150

140

130

120

110

Representative Part

V_DD= 5.5V

4

T_A

=

- 40°C

+25°C

+85°C

2

T_A= +125°C

0

-2

-4

-6

-8

PSRR

CMRR @ V_DD= 5.5V

@ V_DD= 1.8V

-50

-25

0

25

50

75

100

125

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Ambient Temperature (°C)

FIGURE 2-7:

Input Offset Voltage vs.

FIGURE 2-10:

CMRR and PSRR vs.

Output Voltage with V_DD= 5.5V.

Ambient Temperature.

170

8

6

V_DD= 5.5V

160

150

140

4

T_A= +125°C

T_A

=

+85°C

+25°C

- 40°C

2

0

V_DD=1.8V

-2

-4

-6

-8

130

120

110

Representative Part

V_DD= 1.8V

-50

-25

0

25

50

75

100

125

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

Ambient Temperature (°C)

Common Mode Input Voltage (V)

FIGURE 2-11:

Ambient Temperature.

DC Open-Loop Gain vs.

FIGURE 2-8:

Common Mode Voltage with V_DD= 1.8V.

Input Offset Voltage vs.

8

6

500

V_DD= 5.5 V

400

T_A= +85 ºC

300

4

2

T_A= +125°C

200

100

0

-100

-200

-300

-400

-500

T_A

=

+85°C

+25°C

- 40°C

Input Offset Current

0

Input Bias Current

-2

-4

-6

-8

Representative Part

V_DD= 5.5V

Input Common Mode Voltage (V)

Common Mode Input Voltage (V)

FIGURE 2-12:

Input Bias and Offset

FIGURE 2-9:

Input Offset Voltage vs.

Currents vs. Common Mode Input Voltage with

T_A= +85°C.

Common Mode Voltage with V_DD= 5.5V.

DS20006266A-page 8

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

500

400

300

200

100

0

V_DD= 5.5 V

T_A= +125 ºC

Input Bias Current

Input Offset Current

-100

-200

-300

-400

-500

Input Common Mode Voltage (V)

FIGURE 2-13:

Input Bias and Offset

Currents vs. Common Mode Input Voltage with

T_A= +125°C.

1n

V_DD= 5.5 V

100p

Input Offset Current

10p

Input Bias Current

1p

0.1p

Ambient Temperature (°C)

FIGURE 2-14:

Currents vs. Ambient Temperature with

_DD= 5.5V.

Input Bias and Offset

V

10000

1m

1000

100µ

100

10µ

10

1µ

1

100n

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

0.1

10n

0.01

1n

0.001

100p

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

FIGURE 2-15:

Input Bias Current vs. Input

Voltage (Below V_SS).

 2019 Microchip Technology Inc.

DS20006266A-page 9

MCP6V66/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF.

2.2

Other DC Voltages and Currents

40

30

0.7

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

1 Wafer Lot

0.6

0.5

Upper (V_CMH– V_DD

)

20

0.4

0.3

10

0.2

Representative Part

0

0.1

0.0

-10

-20

-30

-40

-0.1

-0.2

-0.3

-0.4

-0.5

T_A= +125°C

T

_A= +85°C

Lower (V_CML– V_SS

)

T_A= +25°C

_A= -40°C

T

0

0.5

1

1.5

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5

-50

-25

0

25

50

75

100 125

Ambient Temperature (°C)

Power Supply Voltage (V)

FIGURE 2-16:

Input Common Mode

FIGURE 2-19:

Output Short Circuit Current

Voltage Headroom (Range) vs. Ambient

Temperature.

vs. Power Supply Voltage.

120

1000

Representative Part

100

80

60

40

20

0

V_DD= 1.8V

V_DD– V_OH

100

V_DD= 5.5V

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

10

V_OL– V_SS

1

0.1

1

10

0

0.5

1

1.5

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5

Power Supply Voltage (V)

Output Current Magnitude (mA)

FIGURE 2-17:

Output Voltage Headroom

FIGURE 2-20:

Supply Current vs. Power

vs. Output Current.

Supply Voltage.

1.6

1.5

1.4

1.3

1.2

1.1

1

90

R_L= 2 kΩ

80

V_DD– V_OH

70

60

V_DD= 5.5V

50

40

30

V_OL– V_SS

20

V_DD= 1.8V

10

V_DD– V_OH

615 Samples

1 Wafer Lot

0

0.9

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-18:

Output Voltage Headroom

FIGURE 2-21:

Power-On Reset Voltage vs.

vs. Ambient Temperature.

Ambient Temperature.

DS20006266A-page 10

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF.

2.3

Frequency Response

140

130

120

110

100

90

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

80

70

60

50

40

30

20

10

0

Representative Part

PM

CMRR

V_DD= 5.5V

V_DD= 1.8V

80

70

GBWP

60

50

PSRR-

40

PSRR+

30

20

10

100

1000

10000

100000

-50 -25

0

25

50

75 100 125

10

100

1k

10k

100k

Frequency (Hz)

Ambient Temperature (°C)

FIGURE 2-22:

CMRR and PSRR vs.

FIGURE 2-25:

Gain Bandwidth Product

Frequency.

and Phase Margin vs. Ambient Temperature.

40

30

20

10

-60

1.4

1.2

1

100

90

80

70

60

50

40

30

PM

-90

Open-Loop Phase

-120

-150

-180

-210

-240

-270

0.8

0.6

0.4

0.2

0

Open-Loop Gain

GBWP

0

-10

-20

-30

V_DD= 5.5V

_DD= 1.8V

V

V_DD= 1.8V

C_L= 30 pF

-1

0

1

2

3

4

5

6

7

1.E+04

1.E+05

100k

1.E+06

1M

1.E+07

10M

10k

f (Hz)

Common Mode Input Voltage (V)

FIGURE 2-23:

Open-Loop Gain vs.

FIGURE 2-26:

Gain Bandwidth Product

Frequency with V_DD= 1.8V.

and Phase Margin vs. Common Mode Input

Voltage.

3

2.5

2

80

40

30

20

-60

-90

70

60

50

40

30

20

Open-Loop Phase

-120

-150

-180

-210

-240

-270

V_DD= 5.5V

PM

10

Open-Loop Gain

1.5

1

GBWP

0

V_DD= 1.8V

-10

0.5

0

V_DD= 5.5V

_L= 30 pF

-20

C

-30

1.E+04

0

1

2

3

4

5

6

10k

100k

1.E+05

1M

1.E+06

10M

1.E+07

f (Hz)

Output Voltage (V)

FIGURE 2-24:

Open-Loop Gain vs.

FIGURE 2-27:

Gain Bandwidth Product

Frequency with V_DD= 5.5V.

and Phase Margin vs. Output Voltage.

 2019 Microchip Technology Inc.

DS20006266A-page 11

MCP6V66/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF.

100000

100k

120

110

100

90

80

70

60

50

40

30

20

10

0

V_DD= 1.8V

10000

10k

1000

1k

G_N= 101 V/V

G_N= 11 V/V

G_N= 1 V/V

100

10

V_IN= 100 mV_PK

V_DD= 5.5V

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

10

100

1000

10000

10M

100M

1G

10G

1k

10k

100k

1M

10M

Frequency (Hz)

FIGURE 2-28:

Closed-Loop Output

FIGURE 2-31:

EMIRR vs. Frequency.

Impedance vs. Frequency with V_DD= 1.8V.

100000

100k

120

100

80

V_DD= 5.5V

10000

10k

60

1000

1k

EMIRR @ 2400 MHz

EMIRR @ 1800 MHz

EMIRR @ 900 MHz

EMIRR @ 400 MHz

40

20

0

G_N= 101 V/V

100

G_N= 11 V/V

G_N= 1 V/V

10

1.0E+03

1.0E+05

1.0E+06

1.0E+07

10

1k

¹1^.0E0⁺k⁰⁴

100k

1M

10M

0.01

0.1

1

)

Input Voltage (V_PK

Frequency (Hz)

FIGURE 2-29:

Closed-Loop Output

FIGURE 2-32:

EMIRR vs. Input Voltage.

Impedance vs. Frequency with V_DD= 5.5V.

130

120

110

100

90

10

V_DD= 5.5V

V_DD= 1.8V

1

80

70

60

0.1

1000

10000

100000

1000000

10k

100k

Frequency (Hz)

1M

1.E+06

1.E+04

1.E+05

1k

10k

100k

1M

Frequency (Hz)

FIGURE 2-33:

Separation vs. Frequency.

Channel-to-Channel

FIGURE 2-30:

Swing vs. Frequency.

Maximum Output Voltage

DS20006266A-page 12

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF.

2.4

Input Noise and Distortion

1000

100

10

1.E-3

1m

VDD = 1.8V

V_DD= 1.8V

VDD = 5.5V

V_DD= 5.5V

G = 11 V/V

V_DD= 1.8V

V_DD= 5.5V

V_DDtone = 100 mV_PK, f = 1 kHz

1.E-4

100µ

100

10

1

e_ni

Residual

1 kHz tone

1.E-5

10µ

DC tone

1.E-6

1µ

Δf = 2 Hz

1.E-7

100n

Δf = 64 Hz

E_ni(0 Hz to f)

1

100k

1.E-8

10n

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5

1

1.E+0

10

1.E+1

100

1.E+2

1k

1.E+3

10k

1.E+4

100k

1.E+5

1

10

100

1k

10k

Frequency (Hz)

FIGURE 2-34:

Input Noise Voltage Density

FIGURE 2-37:

Inter-Modulation Distortion

and Integrated Input Noise Voltage vs.

Frequency.

vs. Frequency with V_DDDisturbance

(see Figure 1-6).

35

f < 2 kHz

9_''ꢊ ꢊꢁꢎꢈ9ꢊ

V_DD= 1.8V

30

13%:ꢊ ꢊꢁꢀꢊ+]ꢊ

25

V_DD= 5.5V

20

15

10

5

13%:ꢊ ꢊꢁꢊ+]ꢊ

0

-1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

Common Mode Input Voltage (V)

ꢀ

ꢁꢀ ꢂꢀ ꢃꢀ ꢄꢀ ꢅꢀ ꢆꢀ ꢇꢀ ꢈꢀ ꢉꢀ ꢁꢀꢀ

7LPHꢊꢌVꢍꢊ

FIGURE 2-35:

Input Noise Voltage Density

FIGURE 2-38:

Input Noise vs. Time with

vs. Input Common Mode Voltage.

1 Hz and 10 Hz Filters and V_DD= 1.8V.

1.E-3

1m

G = 11 V/V

V_CMtone = 100 mV_PK, f = 1 kHz

V_DD= 5.5V

V_DD= 1.8V

V_DD= 5.5V

NPBW = 10 Hz

1.E-4

100µ

Residual

1 kHz tone

(due to resistor

mismatch)

1.E-5

10µ

DC tone

1.E-6

1µ

Δf = 2 Hz

1.E-7

100n

NPBW = 1 Hz

Δf = 64 Hz

1.E-8

10n

0

10 20 30 40 50 60 70 80 90 100

Time (s)

1

10

1.E+1

100

1.E+2

1k

1.E+3

10k

1.E+4

100k

1.E+5

1.E+0

Frequency (Hz)

FIGURE 2-36:

Intermodulation Distortion

FIGURE 2-39:

Input Noise vs. Time with

vs. Frequency with V_CMDisturbance (see

Figure 1-6).

1 Hz and 10 Hz Filters and V_DD= 5.5V.

 2019 Microchip Technology Inc.

DS20006266A-page 13

MCP6V66/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF.

2.5

Time Response

30

25

20

15

10

5

6

5

4

3

2

1

0

V_DD= 5.5 V

G = +1 V/V

5

V_DD

4

V_DDBypass = 1 µF

V_DD= 5.5V

G = 1 V/V

3

2

1

V_OS

0

-5

-1

-2

POR Trip Point

-10

0

5

10 15 20 25 30 35 40 45 50

Time (µs)

0

1

2

3

4

5

6

7

8

9

10

Time (ms)

FIGURE 2-40:

Time at Power-Up.

Input Offset Voltage vs.

FIGURE 2-43:

Step Response.

Noninverting Large Signal

6

V_DD= 5.5 V

G = 1 V/V

5

V_IN

V_OUT

4

3

2

1

V_DD= 5.5 V

G = -1 V/V

0

-1

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Time (0.1 ms/div)

Time (µs)

FIGURE 2-41:

The MCP6V66/6U/7/9

FIGURE 2-44:

Inverting Small Signal Step

Family Shows No Input Phase Reversal with

Overdrive.

Response.

V_DD= 5.5V

G = +1 V/V

0

1

2

3

4

5

6

7

8

9

10

Time (µs)

FIGURE 2-42:

Noniverting Small Signal

Step Response.

DS20006266A-page 14

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 20 kΩ to V_Land C_L= 30 pF.

6

5

4

3

2

1

0

GV_IN

V_OUT

V_DD= 5.5V

G = -10 V/V

0.5V Overdrive

4

3

2

1

GV_IN

V_OUT

V_DD= 5.5 V

G = -1 V/V

0

5

10 15 20 25 30 35 40 45 50

-1

Time (μs)

Time (50 µs/div)

FIGURE 2-45:

Inverting Large Signal Step

FIGURE 2-47:

Output Overdrive Recovery

Response.

vs. Time with G = -10 V/V.

1.0

0.9

10m

0.5V Input Overdrive

Falling Edge, V_DD= 5.5V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Rising Edge, V_DD= 5.5V

V_DD= 1.8V

t_ODR, high

1m

100µ

10µ

1µ

Falling Edge, V_DD= 1.8V

Rising Edge, V_DD= 1.8V

t_ODR, low

V_DD= 5.5V

-50

-25

0

25

50

75

100

125

1

10

100

1000

Ambient Temperature (°C)

Inverting Gain Magnitude (V/V)

FIGURE 2-46:

Slew Rate vs. Ambient

FIGURE 2-48:

Output Overdrive Recovery

Temperature.

Time vs. Inverting Gain.

 2019 Microchip Technology Inc.

DS20006266A-page 15

MCP6V66/6U/7/9

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6V66 MCP6V66U

MCP6V67

MCP6V69

TSSOP

Symbol

Description

SOT-23,

SOT-23

2×3 TDFN MSOP

SC-70

1

4

1

4

1

4

1

11

3

V_OUT, V_OUTAOutput (Op Amp A)

2

V_SS

Negative Power Supply

3

1

3

V_IN+, V_INA

V_IN-, V_INA

V_DD

+

Noninverting Input (Op Amp A)

Inverting Input (Op Amp A)

Positive Power Supply

4

3

2

-

5

8

4

—

5

V_INB

V_OUTB

V_OUTC

V_INC

+

Noninverting Input (Op Amp B)

Inverting Input (Op Amp B)

Output (Op Amp B)

6

-

7

—

9

—

8

Output (Op Amp C)

9

-

Inverting Input (Op Amp C)

Noninverting Input (Op Amp C)

Noninverting Input (Op Amp D)

Inverting Input (Op Amp D)

Output (Op Amp D)

10

12

13

14

—

V_INC

+

V_IND

-

V_OUTD

EP

Exposed Thermal Pad (EP); must be

connected to V_SS

3.1

Analog Outputs

3.4

Exposed Thermal Pad (EP)

The analog output pins (V_OUT) are low-impedance

voltage sources.

There is an internal connection between the exposed

thermal pad (EP) and the V_SSpin; they must be

connected to the same potential on the printed circuit

board (PCB).

3.2

Analog Inputs

This pad can be connected to a PCB ground plane to

provide a larger heat sink. This improves the package

thermal resistance (θ_JA).

The noninverting and inverting inputs (V_IN+, V_IN-, …)

are high-impedance CMOS inputs with low bias

currents.

3.3

Power Supply Pins

The positive power supply (V_DD) is 1.8V to 5.5V higher

than the negative power supply (V_SS). For normal

operation, the other pins are between V_SSand V_DD

.

Typically, these parts are used in a single (positive)

supply configuration. In this case, V_SSis connected to

ground and V_DDis connected to the supply. V_DDwill

need bypass capacitors.

DS20006266A-page 16

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

The Low-Pass Filter reduces high-frequency content,

including harmonics of the chopping clock.

4.0

APPLICATIONS

The MCP6V66/6U/7/9 family of zero-drift op amps is

manufactured using Microchip’s state-of-the-art CMOS

process. It is designed for applications with

requirements for small packages and low power. Its low

supply voltage and low quiescent current make the

MCP6V66/6U/7/9 devices ideal for battery-powered

applications.

The Output Buffer drives external loads at the V_OUTpin

(V_REFis an internal reference voltage).

The Oscillator runs at f_OSC1= 200 kHz. Its output is

divided by two to produce the chopping clock rate of

f_CHOP= 100 kHz.

The internal Power-on Reset (POR) starts the part in a

known good state, protecting against power supply

brown-outs.

4.1

Overview of Zero-Drift Operation

The Digital Control block controls switching and POR

events.

Figure 4-1 shows

a

simplified diagram of the

MCP6V66/6U/7/9 zero-drift op amps. This diagram will

be used to explain how slow voltage errors are reduced

in this architecture (much better V_OS, V_OS/T_A(TC₁),

CMRR, PSRR, A_OLand 1/f noise).

4.1.2

CHOPPING ACTION

Figure 4-2 shows the amplifier connections for the first

phase of the chopping clock, and Figure 4-3 shows the

connections for the second phase. Its slow voltage

errors alternate in polarity, making the average error

small.

V_REF

-

Output

Buffer

V_OUT

V_IN+

+

V_IN+

V_IN–

+

-

+

-

+

-

Main

Amp.

+

-

V_IN–

Main

Amp.

NC

+

-

NC

+

-

Low-Pass

Filter

Low-Pass

Filter

+

-

+

-

Aux.

Amp.

Chopper

Input

Switches

Chopper

Output

Switches

+

-

+

-

Aux.

Amp.

FIGURE 4-2:

First Chopping Clock Phase;

Equivalent Amplifier Diagram.

Oscillator

Digital Control

POR

V_IN+

FIGURE 4-1:

Simplified Zero-Drift Op

+

-

Amp Functional Diagram.

+

-

Main

V_IN–

Amp.

NC

4.1.1

BUILDING BLOCKS

+

-

The Main Amplifier is designed for high gain and

bandwidth, with a differential topology. Its main input

pair (+ and - pins at the top left) is used for the higher

frequency portion of the input signal. Its auxiliary input

pair (+ and - pins at the bottom left) is used for the

low-frequency portion of the input signal, and corrects

the op amp’s input offset voltage. Both inputs are

added together internally.

Low-Pass

Filter

+

-

+

-

Aux.

Amp.

The Auxiliary Amplifier, Chopper Input Switches and

Chopper Output Switches provide a high DC gain to the

input signal. DC errors are modulated to higher

frequencies, while white noise is modulated to low

frequency.

FIGURE 4-3:

Phase; Equivalent Amplifier Diagram.

Second Chopping Clock

 2019 Microchip Technology Inc.

DS20006266A-page 17

MCP6V66/6U/7/9

4.1.3

INTERMODULATION DISTORTION

(IMD)

Bond

Pad

V_DD

V_IN+

V_SS

These op amps will show intermodulation distortion

(IMD) products when an AC signal is present.

The signal and clock can be decomposed into sine

wave tones (Fourier series components). These tones

interact with the zero-drift circuitry’s nonlinear response

to produce IMD tones at sum and difference

frequencies. Each of the square wave clock’s

harmonics has a series of IMD tones centered on it.

See Figures 2-36 and 2-37.

Bond

Pad

Bond

Pad

Input

Stage

V_IN–

Bond

Pad

4.2

Other Functional Blocks

FIGURE 4-4:

Simplified Analog Input ESD

Structures.

4.2.1

RAIL-TO-RAIL INPUTS

The input ESD diodes clamp the inputs when they try

to go more than one diode drop below V_SS. They also

clamp any voltages well above V_DD; their breakdown

voltage is high enough to allow normal operation but

not low enough to protect against slow overvoltage

(beyond V_DD) events. Very fast ESD events (that meet

the specification) are limited so that damage does not

occur.

The input stage of the MCP6V66/6U/7/9 op amps uses

two differential CMOS input stages in parallel. One

operates at low Common Mode Input Voltage (V_CM

,

which is approximately equal to V_IN+ and V_IN- in normal

operation) and the other at high V_CM. With this

topology, the input operates with V_CMup to V_DD+ 0.3V

and down to V_SS– 0.2V, at +25°C (see Figure 2-16).

The input offset voltage (V_OS) is measured at

V_CM= V_SS– 0.2V and V_DD+ 0.3V to ensure proper

operation.

In some applications, it may be necessary to prevent

excessive voltages from reaching the op amp inputs;

Figure 4-5 shows one approach to protecting these

inputs. D₁and D₂may be small signal silicon diodes,

Schottky diodes for lower clamping voltages or

diode-connected FETs for low leakage.

4.2.1.1

Phase Reversal

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages. Figure 2-41 shows an input voltage

exceeding both supplies with no phase inversion.

V_DD

4.2.1.2

Input Voltage Limits

U₁

D₁

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the voltages at

the input pins (see Section 1.1 “Absolute Maximum

Ratings †”). This requirement is independent of the

current limits discussed later on.

MCP6V6X

V₁

V₂

+

-

D₂

V_OUT

The ESD protection on the inputs can be depicted as

shown in Figure 4-4. This structure was chosen to

protect the input transistors against many (but not all)

overvoltage conditions and to minimize input bias

current (I_B).

FIGURE 4-5:

Against High Voltages.

Protecting the Analog Inputs

DS20006266A-page 18

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

4.2.1.3

Input Current Limits

4.3

Application Tips

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

into the input pins (see Section 1.1 “Absolute

Maximum Ratings †”). This requirement is

independent of the voltage limits discussed previously.

4.3.1

INPUT OFFSET VOLTAGE OVER

TEMPERATURE

Table 1-1 gives both the linear and quadratic

temperature coefficients (TC₁and TC₂) of input offset

voltage. The input offset voltage, at any temperature in

the specified range, can be calculated as follows:

Figure 4-6 shows one approach to protecting these

inputs. The R₁and R₂resistors limit the possible

current in or out of the input pins (and into D₁and D₂).

EQUATION 4-1:

The diode currents will dump onto V_DD

.

V_OST_A = V_OS+ TC₁T + TC₂T²

V_DD

Where:

T

V_OS(T_A)

V_OS

=

T_A– 25°C

U₁

D₁

R₁

R₂

Input offset voltage at T_A

Input offset voltage at +25°C

Linear temperature coefficient

Quadratic temperature coefficient

MCP6V6X

V₁

V₂

+

-

D₂

V_OUT

TC₁

TC₂

4.3.2

OFFSET AT POWER-UP

V_SS– min(V₁, V₂)

2 mA

max(V₁, V₂) – V_DD

2 mA

min(R₁, R₂) >

When these parts power up, the input offset (V_OS

)

starts at its uncorrected value. Circuits with high DC

gain can cause the output to reach one of the two rails.

In this case, the time to a valid output is delayed by an

output overdrive time (like t_ODR) in addition to the

start-up time (like t_STR).

FIGURE 4-6:

Against High Currents.

Protecting the Analog Inputs

It can be simple to avoid this extra start-up time.

Reducing the gain is one method. Adding a capacitor

across the feedback resistor (R_F) is another method.

It is also possible to connect the diodes to the left of the

R₁and R₂resistors. In this case, the currents through

the D₁and D₂diodes need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (V_IN+ and

V_IN-) should be very small.

A significant amount of current can flow out of the inputs

(through the ESD diodes) when the Common Mode

Voltage (V_CM) is below ground (V_SS) (see Figure 2-15).

4.2.2

RAIL-TO-RAIL OUTPUT

The Output Voltage Range of the MCP6V66/6U/7/9

zero-drift op amps is V_DD– 5.9 mV (typical) and

V_SS+ 4.7 mV (typical) when R_L= 20 kΩ is connected to

V_DD/2 and V_DD= 5.5V. Refer to Figures 2-17 and 2-18

for more information.

This op amp is designed to drive light loads; use

another amplifier to buffer the output from heavy loads.

 2019 Microchip Technology Inc.

DS20006266A-page 19

MCP6V66/6U/7/9

G_Nis the circuit’s noise gain. For noninverting gains,

G_Nand the Signal Gain are equal. For inverting gains,

G_Nis 1+|Signal Gain| (e.g., -1 V/V gives G_N= +2 V/V).

4.3.3

SOURCE RESISTANCES

The input bias currents have two significant

components: switching glitches that dominate at room

temperature and below and input ESD diode leakage

currents that dominate at +85°C and above.

10000

V_DD= 5.5V

R_L= 20 kȍ

Make the resistances seen by the inputs small and

equal. This minimizes the output offset caused by the

input bias currents.

1000

100

The inputs should see a resistance on the order of 10Ω

to 1 kΩ at high frequencies (i.e., above 1 MHz). This

helps minimize the impact of switching glitches, which

are very fast, on overall performance. In some cases it

may be necessary to add resistors in series with the

inputs to achieve this improvement in performance.

G_N:

1 V/V

10 V/V

10

1

100 V/V

1.E1-0100p

1.E1-n09

1.E1-00n8

1.1E0-07n

1.E1-µ06

Small input resistances may be needed for high gains.

Without them, parasitic capacitances might cause

positive feedback and instability.

Normalized Load Capacitance; C_L/G_N(F)

FIGURE 4-8:

Recommended R_ISOValues

for Capacitive Loads.

4.3.4

SOURCE CAPACITANCE

After selecting R_ISOfor your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify the R_ISOvalue until the

response is reasonable. Bench evaluation is helpful.

The capacitances seen by the two inputs should be

small. Large input capacitances and source

resistances, together with high gain, can lead to

positive feedback and instability.

4.3.6

STABILIZING OUTPUT LOADS

4.3.5

CAPACITIVE LOADS

This family of zero-drift op amps has an output

impedance (Figures 2-28 and 2-29) that has a double

zero when the gain is low. This can cause a large phase

shift in feedback networks that have low-impedance

near the part’s bandwidth. This large phase shift can

cause stability problems.

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. These zero-drift op amps have a different

output impedance than most op amps, due to their

unique topology.

Figure 4-9 shows that the load on the output is

(R_L+ R_ISO)||(R_F+ R_G), where R_ISOis before the load

(like Figure 4-7). This load needs to be large enough to

maintain stability; it should be at least 10 kΩ.

When driving a capacitive load with these op amps, a

series resistor at the output (R_ISOin Figure 4-7)

improves the feedback loop’s phase margin (stability)

by making the output load resistive at higher

frequencies. The bandwidth will be generally lower

than the bandwidth with no capacitive load.

R_ISO

R_G

R_F

V_OUT

-

R_L

C_L

+

U₁

MCP6V6X

Output Load.

R_ISO

V_OUT

FIGURE 4-9:

-

C_L

U₁

+

MCP6V6X

FIGURE 4-7:

Output Resistor, R_ISO,

Stabilizes Capacitive Loads.

Figure 4-8 gives recommended R_ISOvalues for

different capacitive loads and gains. The x-axis is the

load capacitance (C_L). The y-axis is the resistance

(R_ISO).

DS20006266A-page 20

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

4.3.7

GAIN PEAKING

4.3.8

REDUCING UNDESIRED NOISE

AND SIGNALS

Figure 4-10 shows an op amp circuit that represents

noninverting amplifiers (V_Mis a DC voltage and V_Pis

the input) or inverting amplifiers (V_Pis a DC voltage

and V_Mis the input). The C_Nand C_Gcapacitances

represent the total capacitance at the input pins; they

include the op amp’s Common Mode Input

Capacitance (C_CM), board parasitic capacitance and

any capacitor placed in parallel. The C_FPcapacitance

represents the parasitic capacitance coupling the

output and noninverting input pins.

Reduce undesired noise and signals with:

• Low bandwidth signal filters:

- Minimize random analog noise

- Reduce interfering signals

• Good PCB layout techniques:

- Minimize crosstalk

- Minimize parasitic capacitances and

inductances that interact with fast switching

edges

• Good power supply design:

- Isolation from other parts

C_N

C_FP

R_N

- Filtering of interference on supply line(s)

V_P

4.3.9

SUPPLY BYPASSING AND

FILTERING

U₁

+

MCP6V6X

-

With this family of operational amplifiers, the power

supply pin (V_DDfor single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

of the pin for good high-frequency performance.

V_M

V_OUT

R_G

R_F

C_G

These parts also need a bulk capacitor (i.e., 1 µF or

larger) within 100 mm to provide large, slow currents.

This bulk capacitor can be shared with other low-noise

analog parts.

FIGURE 4-10:

Capacitance.

Amplifier with Parasitic

C_Gacts in parallel with R_G(except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

C_Galso reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing C_Gor R_F||R_G.

In some cases, high-frequency power supply noise

(e.g., switched mode power supplies) may cause

undue intermodulation distortion with a DC offset shift;

this noise needs to be filtered. Adding a small resistor

into the supply connection can be helpful.

C_Nand R_Nform a low-pass filter that affects the signal

4.3.10

PCB DESIGN FOR DC PRECISION

at V_P. This filter has a single real pole at 1/(2πR_NC_N).

The largest value of R_Fthat should be used depends

on noise gain (see G_Nin Section 4.3.5 “Capacitive

Loads”), C_Gand the open-loop gain’s phase shift. An

approximate limit for R_Fis:

In order to achieve DC precision on the order of ±1 µV,

many physical errors need to be minimized. The design

of the Printed Circuit Board (PCB), the wiring and the

thermal environment have a strong impact on the

precision achieved. A poor PCB design can easily be

more than 100 times worse than the MCP6V66/6U/7/9

op amps’ minimum and maximum specifications.

EQUATION 4-2:

3.5 pF

R_F 10 k  ---------------  G _N²

C_G

4.3.10.1

PCB Layout

Any time two dissimilar metals are joined together, a

temperature-dependent voltage appears across the

junction (the Seebeck or thermojunction effect). This

effect is used in thermocouples to measure

temperature. The following are examples of

thermojunctions on a PCB:

Some applications may modify these values to reduce

either output loading or gain peaking (step-response

overshoot).

At high gains, R_Nneeds to be small in order to prevent

positive feedback and oscillations. Large C_Nvalues

can also help.

• Components (resistors, op amps, …) soldered to

a copper pad

• Wires mechanically attached to the PCB

• Jumpers

• Solder joints

• PCB vias

 2019 Microchip Technology Inc.

DS20006266A-page 21

MCP6V66/6U/7/9

Typical thermojunctions have temperature-to-voltage

conversion coefficients of 1 to 100 µV/°C (sometimes

higher).

4.4

Typical Applications

4.4.1

WHEATSTONE BRIDGE

Microchip’s AN1258 (“Op Amp Precision Design: PCB

Layout Techniques”) contains in-depth information on

PCB layout techniques that minimize thermojunction

effects. It also discusses other effects, such as

crosstalk, impedances, mechanical stresses and

humidity.

Many sensors are configured as Wheatstone bridges.

Strain gauges and pressure sensors are two common

examples. These signals can be small and the

Common mode noise large. Amplifier designs with high

differential gain are desirable.

Figure 4-11 shows how to interface to a Wheatstone

bridge with a minimum of components. Because the

circuit is not symmetric, the ADC input is single-ended

and there is a minimum of filtering; the CMRR is good

enough for moderate Common mode noise.

4.3.10.2

Crosstalk

DC crosstalk causes offsets that appear as a larger

input offset voltage. Common causes include:

• Common mode noise (remote sensors)

• Ground loops (current return paths)

• Power supply coupling

0.01C

100R

V_DD

1 kΩ

V_DD

R

+

-

ADC

Interference from the mains (usually 50 Hz or 60 Hz)

and other AC sources can also affect the DC

performance. Nonlinear distortion can convert these

signals to multiple tones, including a DC shift in voltage.

When the signal is sampled by an ADC, these AC

signals can also be aliased to DC, causing an apparent

shift in offset.

0.2R

U₁

MCP6V66

-

R

+

FIGURE 4-11:

4.4.2 RTD SENSOR

The ratiometric circuit in Figure 4-12 conditions a

Simple Design.

To reduce interference:

- Keep traces and wires as short as possible

- Use shielding

two-wire RTD for applications with limited

a

temperature range. U₁acts as a difference amplifier

with a low-frequency pole. The sensor’s wiring

resistance (R_W) is corrected in firmware. Failure (open)

of the RTD is detected by an out-of-range voltage.

- Use ground plane (at least a star ground)

- Place the input signal source near the DUT

- Use good PCB layout techniques

- Use a separate power supply filter (bypass

capacitors) for these zero-drift op amps

V_DD

4.3.10.3

Miscellaneous Effects

R_T

34.8 kΩ

R_N

10.0 kΩ

Keep the resistances seen by the input pins as small

and as near to equal as possible to minimize bias

current-related offsets.

10 nF

R_F

2.00 MΩ

+

R_W

Make the (trace) capacitances seen by the input pins

small and equal. This is helpful in minimizing switching

glitch-induced offset voltages.

U₁

R_RTD

100Ω

MCP6V66

-

Bending a coax cable with a radius that is too small

causes a small voltage drop to appear on the center

conductor (the triboelectric effect). Make sure the

bending radius is large enough to keep the conductors

and insulation in full contact.

1.00 kΩ

R_G

R_F

R_W

10.0 kΩ 2.00 MΩ

100 nF

V_DD

R_B

4.99 kΩ

10 nF

1.0 µF

Mechanical stresses can make some capacitor types

(such as some ceramics) output small voltages. Use

more appropriate capacitor types in the signal path and

minimize mechanical stresses and vibration.

+

ADC

-

FIGURE 4-12:

RTD Sensor.

Humidity can cause electrochemical potential voltages

to appear in a circuit. Proper PCB cleaning helps, as

does the use of encapsulants.

DS20006266A-page 22

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

4.4.3

OFFSET VOLTAGE CORRECTION

Figure 4-13 shows MCP6V66 (U₂) correcting the input

offset voltage of another op amp (U₁). R₂and C₂

integrate the offset error seen at U₁’s input; the

integration needs to be slow enough to be stable (with

the feedback provided by R₁and R₃). R₄and R₅

attenuate the integrator’s output; this shifts the

integrator pole down in frequency.

R₁

R₂

R₃

V_IN

V_OUT

-

R₄

R₅

C₂

+

U₁

MCP6XXX

V_DD/2

-

R₂

V_DD/2

+

U₂

MCP6V66

FIGURE 4-13:

Offset Correction.

4.4.4 PRECISION COMPARATOR

Use high gain before a comparator to improve the

latter’s performance. Do not use MCP6V66/6U/7/9 as

a comparator by itself; the V_OScorrection circuitry does

not operate properly without a feedback loop.

U₁

V_IN

MCP6V66

+

-

R₁

R₂

R₃

R₄

R₅

V_OUT

V_DD/2

+

-

U₂

MCP6541

FIGURE 4-14:

Precision Comparator.

 2019 Microchip Technology Inc.

DS20006266A-page 23

MCP6V66/6U/7/9

5.3

Analog Demonstration and

Evaluation Boards

5.0

DESIGN AIDS

Microchip provides the basic design aids needed for

the MCP6V66/6U/7/9 family of op amps.

Microchip offers

a

broad spectrum of Analog

Demonstration and Evaluation Boards that are

designed to help customers achieve faster time to

market. For a complete listing of these boards and their

corresponding user’s guides and technical information,

5.1

SPICE Macro Model

The latest SPICE macro model for the

MCP6V66/6U/7/9 op amps is available on the

Microchip web site at www.microchip.com. This model

is intended to be an initial design tool that works well in

the op amp’s linear region of operation over the

temperature range. See the model file for information

on its capabilities.

visit

the

Microchip

web

site

at

www.microchip.com/analog tools.

Some boards that are especially useful are:

• MCP6V01 Thermocouple Auto-Zeroed Reference

Design (P/N MCP6V01RD-TCPL)

• MCP6XXX Amplifier Evaluation Board 2 (P/N

DS51668)

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristics curves.

• MCP6XXX Amplifier Evaluation Board 3 (P/N

DS51673)

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board

(P/N SOIC8EV)

5.2

Microchip Advanced Part Selector

(MAPS)

• 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N

SOIC14EV)

MAPS is a software tool that helps efficiently identify

Microchip devices that fit particular design

5.4

Application Notes

a

requirement. Available at no cost from the Microchip

web site at www.microchip.com/maps, MAPS is an

overall selection tool for Microchip’s product portfolio

that includes Analog, Memory, MCUs and DSCs. Using

this tool, a customer can define a filter to sort features

for a parametric search of devices and export

side-by-side technical comparison reports. Helpful links

are also provided for data sheets, purchase and

sampling of Microchip parts.

The following Microchip Application Notes are

available on the Microchip web site at www.microchip.

com/appnotes and are recommended as supplemental

reference resources.

ADN003: “Select the Right Operational Amplifier for

your Filtering Circuits”, DS21821

AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

AN723: “Operational Amplifier AC Specifications and

Applications”, DS00723

AN884: “Driving Capacitive Loads With Op Amps”,

DS00884

AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

AN1177: “Op Amp Precision Design: DC Errors”,

DS01177

AN1228: “Op Amp Precision Design: Random Noise”,

DS01228

AN1258: “Op Amp Precision Design: PCB Layout

Techniques”, DS01258

These Application Notes and others are listed in the

design guide:

“Signal Chain Design Guide”, DS21825

DS20006266A-page 24

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

6.0

6.1

PACKAGING INFORMATION

Package Marking Information

5-Lead SC70 (MCP6V66U)

Example

FT56

Device

MCP6V66UT-E/LTY

Code

FTNN

5-Lead SOT-23 (MCP6V66, MCP6V66U)

Example

Device

Code

RBBEC

35256

MCP6V66T-E/OT

MCP6V66UT-E/OT

RBBEC

RBBED

8-Lead MSOP (3x3 mm) (MCP6V67)

Example

6V67E

935256

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2019 Microchip Technology Inc.

DS20006266A-page 25

MCP6V66/6U/7/9

8-Lead TDFN (2x3x0.75 mm) (MCP6V67)

Example

Device

MCP6V67T-E/MNY

Code

DM7

935

25

Note:

Applies to 8-Lead 2x3 TDFN.

14-Lead TSSOP (4.4 mm) (MCP6V69)

Example

XXXXXXXX

YYWW

6V69E/ST

1935

256

NNN

DS20006266A-page 26

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

5-Lead Plastic Small Outine Transistor (LTY) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

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Microchip Technology Drawing C04-083B

ꢕꢃꢎꢓꢈꢎꢒꢃꢔ &ꢅꢎꢒꢆꢈꢏꢈꢚ' ꢂꢓꢊ*ꢃꢆꢚ $ꢗ!<ꢗ4ꢀ#

 2019 Microchip Technology Inc.

DS20006266A-page 27

MCP6V66/6U/7/9

5-Lead Plastic Small Outine Transistor (LTY) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006266A-page 28

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

0.20 C 2X

D

e1

A

D

N

E/2

E1/2

E1

E

(DATUM D)

(DATUM A-B)

0.15 C D

2X

NOTE 1

1

2

e

B

NX b

0.20

C A-B D

TOP VIEW

A

A2

A1

A

0.20 C

SEATING PLANE

A

SEE SHEET 2

C

SIDE VIEW

Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2

 2019 Microchip Technology Inc.

DS20006266A-page 29

MCP6V66/6U/7/9

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

c

T

L

L1

VIEW A-A

SHEET 1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

5

0.95 BSC

Outside lead pitch

Overall Height

Molded Package Thickness

Standoff

Overall Width

Molded Package Width

Overall Length

Foot Length

e1

A

A2

A1

E

E1

D

L

1.90 BSC

0.90

0.89

-

1.45

1.30

0.15

2.80 BSC

1.60 BSC

2.90 BSC

0.30

-

0.60

Footprint

Foot Angle

Lead Thickness

Lead Width

L1

0.60 REF

I

0°

0.08

0.20

-

10°

0.26

0.51

c

b

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

protrusions shall not exceed 0.25mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2

DS20006266A-page 30

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

X

SILK SCREEN

5

Y

Z

C

G

1

2

E

GX

RECOMMENDED LAND PATTERN

Units

MILLIMETERS

Dimension Limits

MIN

NOM

0.95 BSC

2.80

MAX

Contact Pitch

E

C

Contact Pad Spacing

Contact Pad Width (X5)

Contact Pad Length (X5)

Distance Between Pads

Overall Width

X

Y

G

GX

Z

0.60

1.10

1.70

0.35

3.90

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2091-OT Rev F

 2019 Microchip Technology Inc.

DS20006266A-page 31

MCP6V66/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006266A-page 32

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2019 Microchip Technology Inc.

DS20006266A-page 33

MCP6V66/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006266A-page 34

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]

With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

(DATUM A)

(DATUM B)

NOTE 1

2X

0.15 C

2X

1

2

0.15 C

TOP VIEW

0.10 C

(A3)

C

A

SEATING

PLANE

8X

A1

L

0.08 C

C A B

SIDE VIEW

0.10

D2

1

2

0.10

C A B

NOTE 1

E2

K

N

8X b

0.10

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 1 of 2

 2019 Microchip Technology Inc.

DS20006266A-page 35

MCP6V66/6U/7/9

8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]

With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Pins

Pitch

Overall Height

Standoff

Contact Thickness

Overall Length

Overall Width

Exposed Pad Length

Exposed Pad Width

Contact Width

Contact Length

N

8

e

0.50 BSC

0.75

A

A1

A3

D

0.70

0.00

0.80

0.05

0.02

0.20 REF

2.00 BSC

3.00 BSC

1.40

E

D2

E2

b

L

K

1.35

1.25

0.20

0.25

0.20

1.45

1.35

0.30

0.45

-

1.30

0.25

0.30

-

Contact-to-Exposed Pad

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Package is saw singulated

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 2 of 2

DS20006266A-page 36

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]

With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

X2

EV

8

ØV

C

Y2

EV

Y1

1

2

SILK SCREEN

X1

E

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.50 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

X2

Y2

C

1.60

1.50

2.90

Contact Pad Width (X8)

Contact Pad Length (X8)

Thermal Via Diameter

Thermal Via Pitch

X1

Y1

V

0.25

0.85

0.30

1.00

EV

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

Microchip Technology Drawing No. C04-129-MNY Rev. B

 2019 Microchip Technology Inc.

DS20006266A-page 37

MCP6V66/6U/7/9

Note: ForꢝtheꢝmostꢝcurrentꢝpackageꢝdrawingsꢞꢝpleaseꢝseeꢝtheꢝꢟicrochipꢝPackagingꢝSpecificationꢝlocatedꢝatꢝ

httpꢠꢡꢡwwwꢢmicrochipꢢcomꢡpackaging

DS20006266A-page 38

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

Note: ForꢝtheꢝmostꢝcurrentꢝpackageꢝdrawingsꢞꢝpleaseꢝseeꢝtheꢝꢟicrochipꢝPackagingꢝSpecificationꢝlocatedꢝatꢝ

httpꢠꢡꢡwwwꢢmicrochipꢢcomꢡpackaging

 2019 Microchip Technology Inc.

DS20006266A-page 39

MCP6V66/6U/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006266A-page 40

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

APPENDIX A: REVISION HISTORY

Revision A (October 2019)

• Original release of this document.

 2019 Microchip Technology Inc.

DS20006266A-page 41

MCP6V66/6U/7/9

NOTES:

DS20006266A-page 42

 2019 Microchip Technology Inc.

MCP6V66/6U/7/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(1)

Examples:

[X]

PART NO.

–X

/XX

a)

MCP6V66T-E/OT:

Tape and Reel,

Extended temperature,

5LD SOT-23 package

Device Tape and Reel

Temperature

Range

Package

a)

b)

MCP6V66UT-E/LTY: Tape and Reel,

Extended temperature,

5LD SC70 package

Device:

MCP6V66T: Single Op Amp (Tape and Reel)

(SOT-23 only)

MCP6V66UT: Single Op Amp (Tape and Reel)

(SC70, SOT-23)

MCP6V66UT-E/OT:

Tape and Reel,

Extended temperature,

5LD SOT-23 package

MCP6V67:

Dual Op Amp (MSOP, 2x3 TDFN)

MCP6V67T: Dual Op Amp (Tape and Reel) (MSOP,

2x3 TDFN)

a)

b)

MCP6V67-E/MS:

MCP6V67T-E/MS:

Extended temperature,

8LD MSOP package

MCP6V69:

Quad Op Amp (TSSOP)

MCP6V69T: Quad Op Amp (Tape and Reel) (TSSOP)

Tape and Reel,

Extended temperature,

8LD MSOP package

Temperature Range:

Package:

E

= -40°C to +125°C (Extended)

c)

MCP6V67T-E/MNY:

Tape and Reel,

Extended temperature,

8LD 2x3 TDFN package

LTY*

OT

=

Plastic Small Outline Transistor, 5-lead SC70

= Plastic Small Outline Transistor, 5-lead SOT-23

a)

b)

MCP6V69-E/ST:

MCP6V69T-E/ST:

Extended temperature,

14LD TSSOP package

MNY* = Plastic Dual Flat, No-Lead - 2×3×0.8 mm Body,

8-lead, TDFN

MS

ST

Tape and Reel,

Extended temperature,

14LD TSSOP package

= Plastic Micro Small Outline, 8-lead, MSOP

= Plastic Thin Shrink Small Outline - 4.4 mm

Body, 14-lead, TSSOP

*Y

=

Nickel palladium gold manufacturing designator.

Only available on the SC70 and TDFN package.

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This

identifier is used for ordering purposes and is

not printed on the device package. Check with

your Microchip Sales Office for package

availability with the Tape and Reel option.

 2019 Microchip Technology Inc.

DS20006266A-page 43

MCP6V66/6U/7/9

NOTES:

DS20006266A-page 44

 2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec,

AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,

chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,

flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,

LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,

Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,

PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,

Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,

SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA

are registered trademarks of Microchip Technology Incorporated in

the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company,

EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,

IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision

Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,

SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,

TimePictra, TimeProvider, Vite, WinPath, and ZL are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,

CryptoAuthentication, CryptoAutomotive, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple

Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,

USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and

ZENA are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage

Technology, and Symmcom are registered trademarks of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany

II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-5177-8

For information regarding Microchip’s Quality Management Systems,

please visit www.microchip.com/quality.

 2019 Microchip Technology Inc.

DS20006266A-page 45

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

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Tel: 61-2-9868-6733

India - Bangalore

Tel: 91-80-3090-4444

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

China - Beijing

Tel: 86-10-8569-7000

India - New Delhi

Tel: 91-11-4160-8631

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

China - Chengdu

Tel: 86-28-8665-5511

India - Pune

Tel: 91-20-4121-0141

Finland - Espoo

Tel: 358-9-4520-820

China - Chongqing

Tel: 86-23-8980-9588

Japan - Osaka

Tel: 81-6-6152-7160

Web Address:

www.microchip.com

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

China - Dongguan

Tel: 86-769-8702-9880

Japan - Tokyo

Tel: 81-3-6880- 3770

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

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Tel: 86-20-8755-8029

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Tel: 82-53-744-4301

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Korea - Seoul

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Tel: 512-257-3370

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Tel: 852-2943-5100

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Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

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Malaysia - Penang

Tel: 60-4-227-8870

Germany - Karlsruhe

Tel: 49-721-625370

China - Qingdao

Philippines - Manila

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shanghai

Tel: 86-21-3326-8000

Singapore

Tel: 65-6334-8870

Germany - Rosenheim

Tel: 49-8031-354-560

China - Shenyang

Tel: 86-24-2334-2829

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

China - Shenzhen

Tel: 86-755-8864-2200

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7288-4388

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

DS20006266A-page 46

 2019 Microchip Technology Inc.

05/14/19


型号：	MCP6V67-E/MS
厂家：	MICROCHIP
描述：	80 Î¼A, 1 MHz Zero-Drift Op Amps
文件：	总46页 (文件大小：1265K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP6V67-E/MS [MICROCHIP]

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