MCV14ATI/SL_技术文档

MCV14A

Data Sheet

14-Pin, 8-Bit Flash Microcontroller

Preliminary

DS41338B

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,

Omniscient Code Generation, PICC, PICC-18, PICkit,

32

PICDEM, PICDEM.net, PICtail, PIC logo, REAL ICE, rfLAB,

Select Mode, Total Endurance, TSHARC, WiperLock and

ZENA are trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS41338B-page ii

Preliminary

MCV14A

14-Pin, 8-Bit Flash Microcontroller

High-Performance RISC CPU:

Low-Power Features/CMOS Technology:

• Only 33 Single-Word Instructions

• Standby current:

- 100 nA @ 2.0V, typical

• Operating current:

• All Single-Cycle Instructions except for Program

Branches which are Two-Cycle

- 15 μA @ 32 kHz, 2.0V, typical

- 170 μA @ 4 MHz, 2.0V, typical

• Watchdog Timer current:

- 1 μA @ 2.0V, typical

- 7 μA @ 5.0V, typical

• Two-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

for Data and Instructions

• Operating Speed:

- DC – 20 MHz crystal oscillator

- DC – 200 ns instruction cycle

• On-chip Flash Program Memory

- 1024 x 12

• General Purpose Registers (SRAM)

- 67 x 8

• High Endurance Program and Flash Data Memory

cells

- 100,000 write Program Memory endurance

- 1,000,000 write Flash Data Memory endurance

- Program and Flash Data retention: >40 years

• Fully static design

• Flash Data Memory

- 64 x 8

• Wide operating voltage range: 2.0V to 5.5V

- Wide temperature range

- Industrial: -40°C to +85°C

Special Microcontroller Features:

Peripheral Features:

• 8 MHz precision internal oscillator

- Factory calibrated to ±1%

• 12 I/O Pins

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) Support

• Power-On Reset (POR)

- 11 I/O pins with individual direction control

- 1 input-only pin

- High current sink/source for direct LED drive

- Wake-up on change

- Weak pull-ups

• 8-bit Real-time Clock/Counter (TMR0) with 8-bit

Programmable Prescaler

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with Dedicated On-Chip

RC Oscillator for Reliable Operation

• Programmable Code Protection

• Multiplexed MCLR Input Pin

• Two Analog Comparators

- Comparator inputs and output accessible

externally

- One comparator with 0.6V fixed on-chip

absolute voltage reference (VREF)

- One comparator with programmable on-chip

voltage reference (VREF)

• Internal Weak Pull-ups on I/O Pins

• Power-Saving Sleep mode

• Wake-Up from Sleep on Pin Change

• Selectable Oscillator Options:

- INTRC: 4 MHz or 8 MHz precision Internal

RC oscillator

• Analog-to-Digital (A/D) Converter

- 8-bit resolution

- EXTRC: External low-cost RC oscillator

- 3-channel external programmable inputs

- XT:

- HS:

- LP:

- EC:

Standard crystal/resonator

- 1-channel internal input to internal absolute

0.6 voltage reference

High-speed crystal/resonator

Power-saving, low-frequency crystal

High-speed external clock input

Program

Memory

Data Memory

8-bit A/D

Channels

Device

I/O

Comparators Timers 8-bit

Flash

(bytes)

Flash (words) SRAM (bytes)

MCV14A

1024

67

64

12

2

1

3

Preliminary

DS41338B-page 1

MCV14A

FIGURE 1:

14-PIN PDIP AND SOIC DIAGRAM

VSS

VDD

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

RB3/MCLR/VPP

RC5/T0CKI

1

2

3

4

5

6

7

14

13

12

11

10

9

RB0/C1IN+/AN0/ICSPDAT

RB1/C1IN-/AN1/ICSPCLK

RB2/C1OUT/AN2

RC0/C2IN+

RC1/C2IN-

RC4/C2OUT

8

RC2/CVREF

RC3

DS41338B-page 2

Preliminary

MCV14A

Table of Contents

1.0 General Description..................................................................................................................................................................... 5

2.0 Architectural Overview ................................................................................................................................................................ 9

3.0 Memory Organization................................................................................................................................................................ 11

4.0 Flash Data Memory................................................................................................................................................................... 19

5.0 I/O Port...................................................................................................................................................................................... 23

6.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 29

7.0 Special Features of the CPU..................................................................................................................................................... 35

8.0 Analog-to-Digital (A/D) Converter.............................................................................................................................................. 49

9.0 Comparator(s) ........................................................................................................................................................................... 53

10.0 Comparator Voltage Reference Module.................................................................................................................................... 59

11.0 Electrical Characteristics........................................................................................................................................................... 61

12.0 Packaging Information............................................................................................................................................................... 75

The Microchip Web Site...................................................................................................................................................................... 97

Index ................................................................................................................................................................................................... 79

Product Identification System ............................................................................................................................................................. 81

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Micro-

chip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined

and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.

We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Customer Notification System

Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.

Preliminary

DS41338B-page 3

MCV14A

NOTES:

DS41338B-page 4

Preliminary

MCV14A

1.1

Applications

1.0

GENERAL DESCRIPTION

The MCV14A device fits in applications ranging from

personal care appliances and security systems to low-

power remote transmitters/receivers. The Flash tech-

nology makes customizing application programs

(transmitter codes, appliance settings, receiver fre-

quencies, etc.) extremely fast and convenient. The

small footprint packages, for through hole or surface

mounting, make these microcontrollers perfect for

applications with space limitations. Low cost, low

power, high performance, ease of use and I/O flexibility

make the MCV14A device very versatile even in areas

where no microcontroller use has been considered

before (e.g., timer functions, logic and PLDs in larger

systems and coprocessor applications).

The MCV14A device from Microchip Technology is

low-cost, high-performance, 8-bit, fully-static, Flash-

based CMOS microcontrollers. It employs a RISC

architecture with only 33 single-word/single-cycle

instructions. All instructions are single cycle (200 μs)

except for program branches, which take two cycles.

The MCV14A device delivers performance an order of

magnitude higher than their competitors in the same

price category. The 12-bit wide instructions are highly

symmetrical, resulting in a typical 2:1 code compres-

sion over other 8-bit microcontrollers in its class. The

easy-to-use and easy to remember instruction set

reduces development time significantly.

The MCV14A product is equipped with special features

that reduce system cost and power requirements. The

Power-on Reset (POR) and Device Reset Timer (DRT)

eliminate the need for external Reset circuitry. There

are four oscillator configurations to choose from,

including INTRC Internal Oscillator mode and the

power-saving LP (Low-Power) Oscillator mode. Power-

Saving Sleep mode, Watchdog Timer and code protec-

tion features improve system cost, power and reliability.

The MCV14A device is available in the cost-effective

Flash programmable version, which is suitable for

production in any volume. The customer can take full

advantage of Microchip’s price leadership in Flash

programmable microcontrollers, while benefiting from

the Flash programmable flexibility.

The MCV14A product is supported by a full-featured

macro assembler, a software simulator, an in-circuit

emulator, a ‘C’ compiler, a low-cost development pro-

grammer and a full featured programmer. All the tools

are supported on PC and compatible machines.

TABLE 1-1:

FEATURES AND MEMORY OF MCV14A

MCV14A

Clock

Maximum Frequency of Operation (MHz)

Flash Program Memory

SRAM Data Memory (bytes)

Flash Data Memory

20

Memory

1024

67

64

Peripherals

Features

Timer Module(s)

TMR0

Wake-up from Sleep on Pin Change

I/O Pins

Yes

11

Input Pins

1

Internal Pull-ups

Yes

In-Circuit Serial Programming™

Number of Instructions

Packages

Yes

33

14-pin PDIP and SOIC

The MCV14A device has Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and

precision internal oscillator.

The MCV14A device uses serial programming with data pin RB0 and clock pin RB1.

Preliminary

DS41338B-page 5

MCV14A

NOTES:

DS41338B-page 6

Preliminary

MCV14A

The MCV14A device contains an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

register file.

2.0

ARCHITECTURAL OVERVIEW

The high performance of the MCV14A device can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the MCV14A device uses a Harvard architecture

in which program and data are accessed on separate

buses. This improves bandwidth over traditional von

Neumann architectures where program and data are

fetched on the same bus. Separating program and

data memory further allows instructions to be sized

differently than the 8-bit wide data word. Instruction

opcodes are 12 bits wide, making it possible to have

all single-word instructions. A 12-bit wide program

memory access bus fetches a 12-bit instruction in a

single cycle. A two-stage pipeline overlaps fetch and

execution of instructions. Consequently, all

instructions (33) execute in a single cycle (200 ns @

The ALU is 8 bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two’s

complement in nature. In two-operand instructions, one

operand is typically the W (working) register. The other

operand is either a file register or an immediate

constant. In single operand instructions, the operand is

either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC) and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

20 MHz, 1 μs

branches.

@

4 MHz) except for program

Table 2-1 below lists memory supported by the

MCV14A device.

A simplified block diagram is shown in Figure 2-2, with

the corresponding device pins described in Table 2-2.

TABLE 2-1:

Device

MCV14A MEMORY

Program

Data Memory

Memory

Flash

SRAM

Flash

(words)

(bytes)

MCV14A

1024

67

64

The MCV14A device can directly or indirectly address

its register files and data memory. All Special Function

Registers (SFR), including the PC, are mapped in the

data memory. The MCV14A device has a highly orthog-

onal (symmetrical) instruction set that makes it possible

to carry out any operation, on any register, using any

Addressing mode. This symmetrical nature and lack of

“special optimal situations” make programming with the

MCV14A device simple, yet efficient. In addition, the

learning curve is reduced significantly.

Preliminary

DS41338B-page 7

MCV14A

FIGURE 2-1:

MCV14A BLOCK DIAGRAM

11

8

PORTB

Data Bus

Flash Program

Memory

Program Counter

RB0/ICSPDAT

RB1/ICSPCLK

RB2

RB3/MCLR/VPP

RB4/OSC2/CLKOUT

RB5/OSC1/CLKIN

1K x 12

RAM

67

bytes

Flash Data

Memory

64x8

STACK1

STACK2

File

Registers

Program

Bus

12

RAM Addr ⁽¹⁾

9

PORTC

Addr MUX

Instruction Reg

RC0

Indirect

Addr

RC1

RC2

5

Direct Addr

5-7

RC3

RC4

FSR Reg

RC5/T0CKI

STATUS Reg

8

C1IN+

C1IN-

C1OUT

Comparator 1

3

MUX

Device Reset

Timer

VREF

Instruction

Decode and

Control

Power-on

Reset

C2IN+

C2IN-

C2OUT

ALU

Comparator 2

8

Watchdog

Timer

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

W Reg

Internal RC

Clock

CVREF

Timer0

MCLR

AN0

AN1

AN2

VDD, VSS

8-bit ADC

VREF

DS41338B-page 8

Preliminary

MCV14A

TABLE 2-2:

Name

MCV14A PINOUT DESCRIPTION

Input Output

Function

Description

Type

RB0//C1IN+/AN0/

ICSPDAT

RB0

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.

C1IN+

AN0

AN

ST

—

Comparator 1 input.

ADC channel input.

ICSPDAT

RB1

CMOS ICSP™ mode Schmitt Trigger.

RB1/C1IN-/AN1/

ICSPCLK

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.

C1IN-

AN1

AN

ST

—

Comparator 1 input.

ADC channel input.

ICSPCLK

RB2

CMOS ICSP mode Schmitt Trigger.

CMOS Bidirectional I/O pin.

RB2/C1OUT/AN2

RB3/MCLR/VPP

TTL

—

C1OUT

AN2

CMOS Comparator 1 output.

AN

TTL

—

ADC channel input.

RB3

Input pin. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

MCLR

ST

—

Master Clear (Reset). When configured as MCLR, this pin is

an active-low Reset to the device. Voltage on MCLR/VPP must

not exceed VDD during normal device operation or the device

will enter Programming mode. Weak pull-up always on if

configured as MCLR.

VPP

RB4

HV

TTL

—

Programming voltage input.

RB4/OSC2/CLKOUT

RB5/OSC1/CLKIN

CMOS Bidirectional I/O pin.

OSC2

XTAL Oscillator crystal output. Connections to crystal or resonator in

Crystal Oscillator mode (XT, HS and LP modes only, PORTB

in other modes).

CLKOUT

RB5

—

TTL

XTAL

ST

CMOS EXTRC/INTRC CLKOUT pin (FOSC/4).

CMOS Bidirectional I/O pin.

OSC1

CLKIN

RC0

—

Oscillator crystal input.

External clock source input.

RC0/C2IN+

RC1/C2IN-

RC2/CVREF

TTL

AN

TTL

AN

TTL

—

CMOS Bidirectional I/O port.

Comparator 2 input.

CMOS Bidirectional I/O port.

Comparator 2 input.

CMOS Bidirectional I/O port.

C2IN+

RC1

—

C2IN-

RC2

—

CVREF

RC3

AN

Programmable Voltage Reference output.

RC3

TTL

—

CMOS Bidirectional I/O port.

CMOS Comparator 2 output.

CMOS Bidirectional I/O port.

RC4/C2OUT

RC4

C2OUT

RC5

RC5/T0CKI

TTL

ST

T0CKI

VDD

—

P

Timer0 Schmitt Trigger input pin.

VDD

VSS

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

VSS

—

P

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input, HV = High Voltage

Preliminary

DS41338B-page 9

MCV14A

2.1

Clocking Scheme/Instruction

Cycle

2.2

Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the PC to change (e.g., GOTO), then two cycles

are required to complete the instruction (Example 2-1).

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC

is incremented every Q1 and the instruction is fetched

from program memory and latched into the instruction

register in Q4. It is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution flow is shown in Figure 2-2 and Example 2-1.

A fetch cycle begins with the PC incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 2-2:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

PC

Internal

Phase

Clock

PC

PC + 1

PC + 2

Fetch INST (PC)

Execute INST (PC – 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 2-1:

INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

Fetch 1

Execute 1

Fetch 2

2. MOVWF PORTB

3. CALL SUB_1

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTB, BIT1

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

DS41338B-page 10

Preliminary

MCV14A

FIGURE 3-1:

MEMORY MAP

3.0

MEMORY ORGANIZATION

The MCV14A memories are organized into program

memory and data memory (SRAM).The self-writable

portion of the program memory called Flash data mem-

ory is located at addresses at 400h-43Fh. All Program

mode commands that work on the normal Flash mem-

ory work on the Flash data memory. This includes bulk

erase, row/column/cycling toggles, Load and Read

data commands (Refer to Section 4.0 “Flash Data

Memory” for more details). For devices with more than

512 bytes of program memory, a paging scheme is

used. Program memory pages are accessed using one

STATUS register bit. For the MCV14A, with data mem-

ory register files of more than 32 registers, a banking

scheme is used. Data memory banks are accessed

using the File Select Register (FSR).

000h

On-chip User

Program

Memory (Page 0)

1FFh

200h

On-chip User

Program

Memory (Page 1)

3FEh

3FFh

400h

Reset Vector

Flash Data Memory

User ID Locations

43Fh

440h

443h

444h

447h

Backup OSCCAL

Locations

3.1

Program Memory Organization for

the MCV14A

448h

Reserved

The MCV14A device has an 11-bit Program Counter

(PC) capable of addressing a 2K x 12 program memory

space. Program memory is partitioned into user memory,

data memory and configuration memory spaces.

49Fh

4A0h

Unimplemented

7FEh

7FFh

The user memory space is the on-chip user program

memory. As shown in Figure 3-1, it extends from 0x000

to 0x3FF and partitions into pages, including Reset

vector at address 0x3FF.

Configuration Word

The data memory space is the Flash data memory

block and is located at addresses PC = 400h-43Fh. All

Program mode commands that work on the normal

Flash memory work on the Flash data memory block.

This includes bulk erase, Load and Read data

commands.

The Configuration Memory Space extends from 0x440

to 0x7FF. Locations from 0x448 through 0x49F are

reserved. The User I.D. locations extend from 0x440

through 0x443. The Backup OSCCAL locations extend

from 0x444 through 0x447. The Configuration Word is

physically located at 0x7FF.

Preliminary

DS41338B-page 11

MCV14A

3.2.1

GENERAL PURPOSE REGISTER

FILE

3.2

Data Memory (SRAM and FSRs)

Data memory is composed of registers or bytes of

SRAM. Therefore, data memory for a device is

specified by its register file. The register file is divided

into two functional groups: Special Function Registers

(SFR) and General Purpose Registers (GPR).

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 3.8 “Indirect Data Addressing:

INDF and FSR Registers”.

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling

desired operations of the MCV14A. See Figure 3-2 for

details.

3.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the

operation of the device (Table 3-1).

The MCV14A register file is composed of 13 Special

Function Registers and 41 General Purpose Registers

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

FIGURE 3-2:

REGISTER FILE MAP

FSR<6:5>

File Address

00

01

10

11

20h

40h

60h

INDF⁽¹⁾

TMR0

INDF⁽¹⁾

EECON

PCL

INDF⁽¹⁾

TMR0

INDF⁽¹⁾

EECON

PCL

00h

01h

02h

03h

04h

05h

06h

PCL

STATUS

FSR

STATUS

FSR

STATUS

FSR

EEDATA

OSCCAL

PORTB

EEDATA

OSCCAL

PORTB

EEADR

PORTC

EEADR

PORTC

07h

08h

09h

0Ah

0Bh

0Ch

PORTC

CM1CON0

ADCON0

PORTC

CM1CON0

ADCON0

CM1CON0

ADCON0

CM1CON0

ADCON0

ADRES

CM2CON0

ADRES

CM2CON0

VRCON

0Dh

General

Purpose

Registers

Addresses map back to

addresses in Bank 0.

2Fh

30h

4Fh

6Fh

70h

0Fh

10h

50h

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

1Fh

3Fh

5Fh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Note 1: Not a physical register. See Section 3.8 “Indirect Data Addressing: INDF and FSR Registers”.

DS41338B-page 12

Preliminary

MCV14A

3.2.3

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the

operation of the device (Table 3-1).

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

TABLE 3-1:

SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Value on

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Power-on

Reset

Page #

N/A

TRIS

—

I/O Control Register (PORTB, PORTC)

--11 1111

1111 1111

xxxx xxxx

1111 1111

23

15

18

29

17

N/A

00h

OPTION

INDF

Contains control bits to configure Timer0 and Timer0/WDT prescaler

Uses contents of FSR to Address Data Memory (not a physical register)

Timer0 Module Register

01h/41h TMR0

02h⁽¹⁾

PCL

Low order 8 bits of PC

03h

04h

STATUS

FSR

RBWUF

CWUF

PA0

TO

PD

Z

DC

C

0001 1xxx

100x xxxx

1111 111-

--xx xxxx

14

18

16

23

24

Indirect Data Memory Address Pointer

05h/45h OSCCAL

06h/46h PORTB

CAL6

—

CAL5

—

CAL4

RB5

CAL3

RB4

CAL2

RB3

CAL1

RB2

CAL0

RB1

—

RB0

RC0

07h

08h

PORTC

—

RC5

RC4

RC3

RC2

RC1

CM1CON0

C1OUT

ANS1

C1OUTEN

ANS0

C1POL

ADCS1

C1T0CS

ADCS0

C1ON

CHS1

C1NREF

CHS0

C1PREF

C1WU

ADON

1111 1111

53

09h

0Ah

ADCON0

ADRES

GO/DONE

1111 1100

xxxx xxxx

51

52

ADC Conversion Result

0Bh

0Ch

CM2CON0

VRCON

C2OUT

VREN

—

C2OUTEN

VROE

—

C2POL

VRR

—

C2PREF2

—

C2ON

VR3

C2NREF C2PREF1

C2WU

VR0

RD

1111 1111

000- 0000

---0 0000

xxxx xxxx

--xx xxxx

54

59

20

19

VR2

VR1

WR

21h/61h EECON

25h/65h EEDATA

26h/66h EEADR

FREE

WRERR

WREN

SELF READ/WRITE DATA

SELF READ/WRITE ADDRESS

—

Legend:

x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable). Shaded cells = unimplemented or unused

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 3.6 “Program Counter” for an explanation of how to

access these bits.

Preliminary

DS41338B-page 13

MCV14A

For example, CLRF STATUS,will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

3.3

STATUS Register

This register contains the arithmetic status of the ALU,

the Reset status and the page preselect bit.

Therefore, it is recommended that only BCF, BSF and

MOVWF instructions be used to alter the STATUS

register. These instructions do not affect the Z, DC or C

bits from the STATUS register.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

REGISTER 3-1:

STATUS: STATUS REGISTER

R/W-0

RBWUF

bit 7

R/W-0

CWUF

R/W-0

PA0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

RBWUF: Wake-up from Sleep on Pin Change bit

1= Reset due to wake-up from Sleep on pin change

0= After power-up or other Reset

CWUF: Wake-up from Sleep on Comparator Change bit

1= Reset due to wake-up from Sleep on comparator change

0= After power-up or other Reset

PA0: Program Page Preselect bit

1= Page 1 (000h-1FFh)

0= Page 0 (200h-3FFh)

TO: Time-out bit

1= After power-up, CLRWDTinstruction, or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)

ADDWF:

1= A carry from the 4th low-order bit of the result occurred

0= A carry from the 4th low-order bit of the result did not occur

SUBWF:

1= A borrow from the 4th low-order bit of the result did not occur

0= A borrow from the 4th low-order bit of the result occurred

bit 0

C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)

ADDWF:

1= A carry occurred

SUBWF:

1= A borrow did not occur

RRF or RLF:

Load bit with LSb or MSb, respectively

0= A carry did not occur 0= A borrow occurred

DS41338B-page 14

Preliminary

MCV14A

3.4

OPTION Register

The OPTION register is a 8-bit wide, write-only register,

which contains various control bits to configure the

Timer0/WDT prescaler and Timer0.

Note:

If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled

for that pin (i.e., note that TRIS overrides

Option control of RBPU and RBWU).

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION

register. A Reset sets the OPTION<7:0> bits.

REGISTER 3-2:

OPTION: OPTION REGISTER

W-1

PSA

W-1

PS2

W-1

PS1

W-1

PS0

RBWU

bit 7

RBPU

T0CS⁽¹⁾

T0SE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RBWU: Enable Wake-up On Pin Change bit

1= Disabled

0= Enabled

RBPU: Enable Weak Pull-ups bit

1= Disabled

0= Enabled

T0CS: Timer0 Clock Source Select bit⁽¹⁾

1= Transition on T0CKI pin

0= Internal instruction cycle clock (CLKOUT)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler assigned to the WDT

0= Prescaler assigned to Timer0

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Note 1: If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin.

Preliminary

DS41338B-page 15

MCV14A

3.5

OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used

to calibrate the 8 MHz internal oscillator macro. It

contains 7 bits of calibration that uses a two’s

complement scheme for controlling the oscillator speed.

See Register 3-3 for details.

REGISTER 3-3:

OSCCAL: OSCILLATOR CALIBRATION REGISTER

R/W-1

CAL6

R/W-1

CAL5

R/W-1

CAL4

R/W-1

CAL3

R/W-1

CAL2

R/W-1

CAL1

R/W-1

CAL0

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

CAL<6:0>: Oscillator Calibration bits

0111111= Maximum frequency

•

0000001

0000000= Center frequency

1111111

•

1000000= Minimum frequency

bit 0

Unimplemented: Read as ‘0’

DS41338B-page 16

Preliminary

MCV14A

3.6.1

EFFECTS OF RESET

3.6

Program Counter

The PC is set upon a Reset, which means that the PC

addresses the last location in the last page (i.e., the

oscillator calibration instruction). After executing

MOVLW XX, the PC will roll over to location 00h and

begin executing user code.

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

The STATUS register page preselect bits are cleared

upon a Reset, which means that page 0 is pre-selected.

For a GOTOinstruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The Program Counter

(PCL) is mapped to PC<7:0>. Bit 5 of the STATUS

register provides page information to bit 9 of the PC

(Figure 3-3).

Therefore, upon a Reset, a GOTO instruction will

automatically cause the program to jump to page 0 until

the value of the page bits is altered.

For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are

provided by the instruction word. However, PC<8>

does not come from the instruction word, but is always

cleared (Figure 3-3).

3.7

Stack

The MCV14A device has a 2-deep, 12-bit wide

hardware PUSH/POP stack.

A CALLinstruction will PUSH the current value of Stack

1 into Stack 2 and then PUSH the current PC value,

incremented by one, into Stack Level 1. If more than two

sequential CALLs are executed, only the most recent two

return addresses are stored.

Instructions where the PCL is the destination, or modify

PCL instructions, include MOVWF PC, ADDWF PCand

BSF PC,5.

Note:

Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction,

all subroutine calls or computed jumps are

limited to the first 256 locations of any

program memory page (512 words long).

A RETLW instruction will POP the contents of Stack

Level 1 into the PC and then copy Stack Level 2

contents into Stack Level 1. If more than two sequential

RETLWs are executed, the stack will be filled with the

address previously stored in Stack Level 2. Note that

the W register will be loaded with the literal value

specified in the instruction. This is particularly useful for

the implementation of data look-up tables within the

program memory.

FIGURE 3-3:

LOADING OF PC

BRANCH INSTRUCTIONS

GOTOInstruction

10 9 8 7

0

Note 1: There are no Status bits to indicate Stack

PC

PCL

Overflows or Stack Underflow conditions.

2: There are no instruction mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL

and RETLWinstructions.

Instruction Word

PA0

7

0

Status

CALLor Modify PCL Instruction

10 9 8 7

0

PC

PCL

Instruction Word

Reset to ‘0’

PA0

7

0

Status

Preliminary

DS41338B-page 17

MCV14A

FSR<7> is unimplemented and read as ‘1’.

3.8

Indirect Data Addressing: INDF

and FSR Registers

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 3-1.

The INDF Register is not

a physical register.

Addressing INDF actually addresses the register

whose address is contained in the FSR Register (FSR

is a pointer). This is indirect addressing.

EXAMPLE 3-1:

HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF Register indirectly results in a

no-operation (although Status bits may be affected).

MOVLW

MOVWF

0x10

;initialize pointer

;to RAM

FSR

INDF

;clear INDF

The FSR is 8-bit wide register. It is used in conjunction

with the INDF Register to indirectly address the data

memory area.

;register

;inc pointer

;all done?

INCF

BTFSC

GOTO

FSR,F

FSR,4

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

CONTINUE

:

;YES, continue

FSR<6:5> are the bank select bits and are used to

select the bank to be addressed (00 = Bank 0,

01= Bank 1, 10= Bank 2, 11= Bank 3).

FIGURE 3-4:

DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

(FSR)

(opcode)

(FSR)

3

2

1

4

0

5

3

2

1

0

6

4

5

6

bank select

bank

select

location select

00

01

10

11

00h

Data

Memory

0Ch

0Dh

(1)

Addresses map back to

addresses in Bank 0.

0Fh

10h

2Fh

4Fh

6Fh

1Fh

3Fh

Bank 1

5Fh

7Fh

Bank 0

Bank 2

Bank 3

Note 1: For register map detail see Figure 3-2.

DS41338B-page 18

Preliminary

MCV14A

EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEDATA location

being accessed. The effective program counter is

EEADR + 400h with only the lower 8 bits of each word

being readable or writable.

4.0

FLASH DATA MEMORY

The data memory is the Flash data memory block,

which attaches to the user Flash program memory. It is

located at addresses 0x400-0x43F, as shown in Figure

5-1.

• EEADR = 00h, PC = 400h

• EEADR = 01h, PC = 401h

This Flash data memory block consists of 8 rows and

has self-write capability of up to 64 bytes. This memory

block is not directly mapped in the register file space.

Instead, it is indirectly addressed through the Special

Function Registers. There are three SFRs used to read

and write this memory:

The Flash data memory allows byte read and write, and

during the operations of read and write cycles, the CPU

stalls.

The timing for all self-writes and erases is controlled by

the internal timing block of the program memory (see

• EEDATA (Register 4-1)

• EEADR (Register 4-2)

• EECON (Register 4-3)

Section 11.0

“Electrical

Characteristics”,

Table 11-11). The write/erase voltages are generated

by an on-chip charge pump rated to operate over the

voltage range of the device for byte or word operations.

When the device is code-protected, the CPU may

continue to read and write the Flash data memory and

read the program memory. When code-protected, the

device programmer can no longer access data or

program memory.

REGISTER 4-1:

EEDATA: FLASH DATA REGISTER

R/W-x

EEDATA7

bit 7

R/W-x

EEDATA6

EEDATA5

EEDATA4

EEDATA3

EEDATA2

EEDATA1

EEDATA0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-0

EEDATA<7:0>: 8-bits of data to be read from/written to data Flash

REGISTER 4-2:

EEADR: FLASH ADDRESS REGISTER

U-0

—

U-0

—

R/W-x

EEADR5

EEADR4

EEADR3

EEADR2

EEADR1

EEADR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Do not use

EEADR<5:0>: 6-bits of data to be read from/written to data Flash

Preliminary

DS41338B-page 19

MCV14A

REGISTER 4-3:

EECON: FLASH CONTROL REGISTER

R/W-0

RD

U-0

—

U-0

—

R/W-0

FREE

R/W-0

WREN

R/W-0

WR

—

WRERR

bit 0

bit 7

Legend:

S = Bit can only be set

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-5

bit 4

Unimplemented: Do not use

FREE: Flash Data Memory Row Erase Enable Bit

1= Program memory row being pointed to by EEADR will be erased on the next write cycle. No write

will be performed. This bit is cleared at the completion of the erase operation.

0= Perform write only

bit 3

bit 2

bit 1

bit 0

WRERR: Write Error Flag bit

1= A write operation terminated prematurely (by device Reset)

0= Write operation completed successfully

WREN: Write Enable bit

1= Allows write cycle to Flash data memory

0= Inhibits write cycle to Flash data memory

WR: Write Control bit

1= Initiate a erase or write cycle

0= Write/Erase cycle is complete

RD: Read Control bit

1= Initiate a read of Flash data memory

0= Do not read Flash data memory

DS41338B-page 20

Preliminary

MCV14A

EXAMPLE 4-2:

ERASE DATA MEMORY

ROW

4.1

Reading Data Memory

To read a memory location, the user must write the

address to be read into the EEADR register and then

set the RD bit in the EECON register. The data will be

available in the next instruction cycle.

BSF

FSR,5

;SWITCH TO BANK 1

MOVLW EE_ADR_ERASE ;LOAD ADDRESS TO ERASE

MOVWF EEADR

;LOAD ADDRESS TO SFR

;SELECT ERASE

;ENABL FLASH PROG’ING

;INITITATE ERASE

BSF

EECON,FREE

EECON,WREN

EECON,WR

EXAMPLE 4-1:

FLASH DATA MEMORY

READ

xxx

;NEXT INSTRUCTION

BSF

FSR,5

;SWITCH TO BANK 1

MOVLW

BSF

EE_ADR_READ;LOAD ADDRESS TO READ

EECON,RD

;INITITATE THE READ

INSTRUCTION

Note: The FREE bit may be set by any command

normally used by the core. However, the

WREN and WR bits can only be set using a

series of BSF commands, as documented in

Example 4-2. No other sequence of

commands will work, no exceptions.

;IS DECODED

;GET NEW DATA

MOVF EEDATA,W

Note: Only a BSF command will work to enable the

Flash data memory read documented in

Example 4-1. No other sequence of com-

mands will work, no exceptions.

4.3

Writing a Data Memory Word

To write a memory location, the user must write the

address to be written to into the EEADR register. He

must then load the data to be written into the EEDATA

register. Once the data and address have been

loaded, a specific sequence must be executed to

initiate the write to the program memory. The

sequence is as follows:

4.2

Erasing a Data Memory Row

In order to write new data to the Flash data memory,

the program memory row that is being addressed by

EEADR<5:0> must be erased.

To prevent a spurious row erasure, a specific

sequence must be executed to initiate the erase to the

program memory. The sequence is as follows:

• Set the WREN bit (enable writes to the Flash data

memory array)

- Set the FREE bit (enable Flash data memory

row erase)

• Set the WR bit (initiates the write to the Flash data

memory array)

- Set the WREN bit (enable writes to the Flash

data memory array)

If the WR bit is not set in the instruction cycle after the

WREN bit is set, the WREN bit will be cleared in

hardware.

- Set the WR bit (initiates the row erase of the

Flash data memory array)

This sequence is to prevent an accidental write to the

Flash memory.

If the WREN bit is not set in the instruction cycle after

the FREE bit is set, the FREE bit will be cleared in

hardware.

If the WR bit is not set in the instruction cycle after the

WREN bit is set, the WREN bit will be cleared in

hardware.

Both of these sequences is to prevent an accidental

erase of the Flash data memory.

Preliminary

DS41338B-page 21

MCV14A

EXAMPLE 4-3:

DATA MEMORY WRITE

4.4

DATA MEMORY OPERATION

DURING CODE-PROTECT

BSF

FSR,5

;SWITCH TO BANK 1

MOVLW EE_ADR_WRITE

;LOAD ADDRESS TO

;WRITE

;INTO EEADR

;REGISTER

Data memory can be code-protected by programming

the CPDF bit in the Configuration Word (Register 7-1)

to ‘0’.

MOVWF EEADR

MOVLW EE_DATA_TO_WRITE;LOAD DATA TO

MOVWF EEDATA

;INTO EEDATA

;REGISTER

BSF

EECON,WREN

EECON,WR

;ENABLE WRITES

;START WRITE

;SEQUENCE

NOP

;WAIT AS READ

;INSTRUCTION

;IS DECODED

;INSTRUCTION

NOP

IGNORED

Note 1: Only a series of BSF commands will work

to enable the memory write sequence

documented in Example 4-3. No other

sequence of commands will work, no

exceptions.

2: For reads, erases and writes to the Flash

data memory, there is no need to insert a

NOP into the user code as is done on

mid-range devices. The instruction imme-

diately following the “BSF EECON,WR/RD”

will be fetched and executed properly.

DS41338B-page 22

Preliminary

MCV14A

5.2

PORTC

5.0

I/O PORT

PORTC is a 6-bit I/O register. Only the low-order 6 bits

are used (RC<5:0>). Bits 7 and 6 are unimplemented

and read as ‘0’s.

As with any other register, the I/O register(s) can be

written and read under program control. However, read

instructions (e.g., MOVF PORTB,W) always read the I/O

pins independent of the pin’s Input/Output modes. On

Reset, all I/O ports are defined as input (inputs are at high-

impedance) since the I/O control registers are all set.

5.3

TRIS Register

The Output Driver Control register is loaded with the

contents of the W register by executing the TRIS f

instruction. A ‘1’ from a TRIS register bit puts the corre-

sponding output driver in a High-Impedance mode. A

‘0’ puts the contents of the output data latch on the

selected pins, enabling the output buffer. The excep-

tions are RB3, which is input only and the T0CKI pin,

which may be controlled by the OPTION register. See

Register 3-2 and Register 3-3.

5.1

PORTB

PORTB is a 6-bit I/O register. Only the low-order 6 bits

are used (RB<5:0>). Bits 7 and 6 are unimplemented

and read as ‘0’s. Please note that RB3 is an input only

pin. The Configuration Word can set several I/O’s to

alternate functions. When acting as alternate functions,

the pins will read as ‘0’ during a port read. Pins RB0,

RB1, RB3 and RB4 can be configured with weak pull-

ups and also for wake-up on change. The wake-up on

change and weak pull-up functions are not pin select-

able. If RB3/MCLR is configured as MCLR, weak pull-

up is always on and wake-up on change for this pin is

not enabled.

The TRIS register is “write-only” and is set (output

drivers disabled) upon Reset.

TABLE 5-1:

Device

MCV14A

Note 1: When MCLREN = 1, the weak pull-up on RB3/MCLR is always enabled.

WEAK PULL-UP ENABLED PINS

RB0 Weak Pull-up RB1 Weak Pull-up RB3 Weak Pull-up⁽¹⁾RB4 Weak Pull-up

Yes Yes Yes Yes

REGISTER 5-1:

PORTB: PORTB REGISTER

U-0

—

R/W-x

RB5

R/W-x

RB4

R/W-x

RB3

R/W-x

RB2

R/W-x

RB1

R/W-x

RB0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘1’

RB<5:0>: PORTB I/O Pin bits

1= Port pin is >VIH min.

0= Port pin is <VIL max.

Preliminary

DS41338B-page 23

MCV14A

REGISTER 5-2:

PORTC: PORTC REGISTER

U-0

—

U-0

R/W-x

RC5

R/W-x

RC4

R/W-x

RC3

R/W-x

RC2

R/W-x

RC1

R/W-x

RC0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘1’

RC<5:0>: PORTC I/O Pin bits

1= Port pin is >VIH min.

0= Port pin is <VIL max.

DS41338B-page 24

Preliminary

MCV14A

FIGURE 5-1:

MCV14A EQUIVALENT

CIRCUIT FOR A SINGLE

I/O PIN

5.4

I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All port pins, except RB3 which is input only,

may be used for both input and output operations. For

input operations, these ports are non-latching. Any

input must be present until read by an input instruction

(e.g., MOVF PORTB, W). The outputs are latched and

remain unchanged until the output latch is rewritten. To

use a port pin as output, the corresponding direction

control bit in TRIS must be cleared (= 0). For use as an

input, the corresponding TRIS bit must be set. Any I/O

pin (except RB3) can be programmed individually as

input or output.

Data

Bus

D

Q

Data

Latch

VDD

P

VDD

WR

Port

CK

N

I/O

W

Reg

D

Q

TRIS

Latch

VSS VSS

TRIS ‘f’

CK

Reset

RD Port

Preliminary

DS41338B-page 25

MCV14A

TABLE 5-2:

SUMMARY OF PORT REGISTERS

Value on

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On

Reset

Value on

All Other

Resets

Addr Name

Bit 7

Bit 6

Bit 5

N/A

TRIS

—

I/O Control Register (PORTB, PORTC)

--11 1111 --11 1111

N/A

03h

06h

07h

OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111

STATUS RBWUF CWUF PA0

TO

PD

RB3 RB2 RB1 RB0 --xxxxxx

RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu

Z

DC

C

0001 1xxx q00q quuu⁽¹⁾

PORTB

PORTC

—

RB5

RC5

RB4

RC4

--uu uuuu

Legend: Shaded cells are not used by PORT registers, read as ‘0’. – = unimplemented, read as ‘0’, x= unknown,

u= unchanged,

q= depends on condition.

Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

TABLE 5-3:

Priority

I/O PINS ORDER OF PRECEDENCE

RB0

RB1

RB2

RB3

RC0

RC1

RC2

RC4

RC5

1

2

3

AN0

C1IN+

TRISB

AN1

C1IN-

TRISB

AN2

C1OUT

TRISB

RB3/MCLR

C2IN+

TRISC

—

C2IN-

TRISC

—

CVREF

TRISC

—

C2OUT

TRISC

—

T0CKI

TRISC

—

DS41338B-page 26

Preliminary

MCV14A

EXAMPLE 5-1:

READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT(e.g., MCV14A)

5.5

I/O Programming Considerations

5.5.1

BIDIRECTIONAL I/O PORTS

Some instructions operate internally as read followed

by write operations. The BCFand BSFinstructions, for

example, read the entire port into the CPU, execute the

bit operation and rewrite the result. Caution must be

used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

example, a BSFoperation on bit 5 of PORTB will cause

all eight bits of PORTB to be read into the CPU, bit 5 to

be set and the PORTB value to be written to the output

latches. If another bit of PORTB is used as a bidirec-

tional I/O pin (say bit 0) and it is defined as an input at

this time, the input signal present on the pin itself would

be read into the CPU and rewritten to the data latch of

this particular pin, overwriting the previous content. As

long as the pin stays in the Input mode, no problem

occurs. However, if bit 0is switched into Output mode

later on, the content of the data latch may now be

unknown.

;Initial PORTB Settings

;PORTB<5:3> Inputs

;PORTB<2:0> Outputs

;

PORTB latch PORTB pins

----------

PORTB, 5 ;--01 -ppp

PORTB, 4 ;--10 -ppp

----------

--11 pppp

BCF

MOVLW 007h;

TRIS PORTB

;--10 -ppp

--11 pppp

;

Note 1: The user may have expected the pin values to

be ‘--00 pppp’. The 2nd BCFcaused RB5 to

be latched as the pin value (High).

5.5.2

SUCCESSIVE OPERATIONS ON

I/O PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle (Figure 5-2).

Therefore, care must be exercised if a write followed by

a read operation is carried out on the same I/O port. The

sequence of instructions should allow the pin voltage to

stabilize (load dependent) before the next instruction

causes that file to be read into the CPU. Otherwise, the

previous state of that pin may be read into the CPU rather

than the new state. When in doubt, it is better to separate

these instructions with a NOP or another instruction not

accessing this I/O port.

Example 5-1 shows the effect of two sequential

Read-Modify-Write instructions (e.g., BCF, BSF, etc.)

on an I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired OR”, “wired

AND”). The resulting high output currents may damage

the chip.

FIGURE 5-2:

SUCCESSIVE I/O OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC + 3

PC

PC + 1

PC + 2

This example shows a write to PORTB

followed by a read from PORTB.

Instruction

Fetched

MOVWFPORTB

MOVFPORTB, W

NOP

Data setup time = (0.25 TCY – TPD)

where: TCY = instruction cycle.

TPD = propagation delay

RB<5:0>

Port pin

written here

Port pin

sampled here

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

Instruction

Executed

MOVWF PORTB

(Write to PORTB)

MOVF PORTB,W

(Read PORTB)

NOP

Preliminary

DS41338B-page 27

MCV14A

NOTES:

DS41338B-page 28

Preliminary

MCV14A

There are two types of Counter mode. The first Counter

mode uses the T0CKI pin to increment Timer0. It is

selected by setting the T0CS bit (OPTION<5>), setting

the C1T0CS bit (CM1CON0<4>) and setting the

C1OUTEN bit (CM1CON0<6>). In this mode, Timer0

will increment either on every rising or falling edge of

pin T0CKI. The T0SE bit (OPTION<4>) determines the

source edge. Clearing the T0SE bit selects the rising

edge. Restrictions on the external clock input are

discussed in detail in Section 6.1 “Using Timer0 with

an External Clock”.

6.0

TIMER0 MODULE AND TMR0

REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module.

The second Counter mode uses the output of the

comparator to increment Timer0. It can be entered in

two different ways. The first way is selected by setting

the T0CS bit (OPTION<5>), and clearing the C1T0CS

bit (CM1CON0<4>) (C1OUTEN [CM1CON0<6>] does

not affect this mode of operation). This enables an

internal connection between the comparator and the

Timer0.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-2 and Figure 6-3).

The user can work around this by writing an adjusted

value to the TMR0 register.

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit, PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4,...,

1:256 are selectable. Section 6.2 “Prescaler” details

the operation of the prescaler.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1:

TIMER0 BLOCK DIAGRAM

Data Bus

FOSC/4

0

1

Comparator

Output

PSOUT

8

0

1

0

Sync with

Internal

Clocks

TMR0 Reg

Programmable

Prescaler

PSOUT

Sync

(2)

(1)

(2 cycle delay)

T0CKI

T0SE

(1)

PSA

T0CS

3

(1)

PS2 , PS1 , PS0

(3)

C1T0CS

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer.

3: The C1T0CS bit is in the CM1CON0 register.

Preliminary

DS41338B-page 29

MCV14A

FIGURE 6-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1

PC

PC + 1

PC + 2

PC + 3

PC + 4

PC + 5

PC + 6

Instruction

Fetch

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

NT0 + 1

T0

T0 + 1

T0 + 2

NT0

NT0 + 2

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

FIGURE 6-3:

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Instruction

Fetch

T0

T0 + 1

NT0

NT0 + 1

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-On

Reset

Value on

All Other

Resets

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

TMR0

Timer0 – 8-bit Real-Time Clock/Counter

xxxx xxxx

1111 1111

uuuu uuuu

08h

CM1CON0

C1OUT C1OUTEN C1POL

C1T0CS

C1ON

C1NREF C1PREF

C2NREF C2PREF1 C2WU

PS2 PS1 PS0

C1WU

uuuu uuuu

0Bh

N/A

CM2CON0

OPTION

TRIS⁽¹⁾

C2OUT C2OUTEN C2POL C2PREF2

C2ON

PSA

1111 1111

--11 1111

RBWU

—

RBPU

—

T0CS

T0SE

1111 1111

--11 1111

I/O Control Register (PORTB, PORTC)

Legend:

Note 1:

Shaded cells are not used by Timer0. – = unimplemented, x = unknown, u= unchanged.

The TRIS of the T0CKI pin is overridden when T0CS = 1.

DS41338B-page 30

Preliminary

MCV14A

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler, so that the prescaler output is symmetrical.

For the external clock to meet the sampling require-

ment, the ripple counter must be taken into account.

Therefore, it is necessary for T0CKI to have a period of

at least 4 TOSC (and a small RC delay of 4 Tt0H)

divided by the prescaler value. The only requirement

on T0CKI high and low time is that they do not violate

the minimum pulse width requirement of Tt0H. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device.

6.1

Using Timer0 with an External

Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.1.1

EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-4).

Therefore, it is necessary for T0CKI to be high for at

least 2 TOSC (and a small RC delay of 2 Tt0H) and low

for at least 2 TOSC (and a small RC delay of 2 Tt0H).

Refer to the electrical specification of the desired

device.

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-4 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 6-4:

TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

misses sampling

External Clock Input or

(2)

Prescaler Output

(1)

External Clock/Prescaler

Output After Sampling

(3)

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

Preliminary

DS41338B-page 31

MCV14A

EXAMPLE 6-1:

CHANGING PRESCALER

(TIMER0 → WDT)

;Clear WDT

;Clear TMR0 & Prescaler

6.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Section 7.6 “Watch-

dog Timer (WDT)”). For simplicity, this counter is

being referred to as “prescaler” throughout this data

sheet.

CLRWDT

CLRF

TMR0

MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7)

OPTION

;are required only if

;desired

;PS<2:0> are 000 or 001

CLRWDT

MOVLW ‘00xx1xxx’b;Set Postscaler to

OPTION ;desired WDT rate

Note:

The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice versa.

To change the prescaler from the WDT to the Timer0

module, use the sequence shown in Example 6-2. This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before

switching the prescaler.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1, x, etc.) will clear the prescaler. When assigned

to WDT, a CLRWDT instruction will clear the prescaler

along with the WDT. The prescaler is neither readable

nor writable. On a Reset, the prescaler contains all ‘0’s.

EXAMPLE 6-2:

CHANGING PRESCALER

(WDT → TIMER0)

;Clear WDT and

;prescaler

CLRWDT

MOVLW ‘xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

6.2.1

SWITCHING PRESCALER

ASSIGNMENT

OPTION

The prescaler assignment is fully under software

control (i.e., it can be changed “on-the-fly” during

program execution). To avoid an unintended device

Reset, the following instruction sequence (Example 6-

1) must be executed when changing the prescaler

assignment from Timer0 to the WDT.

DS41338B-page 32

Preliminary

MCV14A

FIGURE 6-5:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY (= FOSC/4)

Data Bus

8

0

1

M

U

X

Comparator

Output

1

0

1

M

U

X

Sync

2

Cycles

TMR0 Reg

T0CKI

(1)

T0SE

T0CS

(1)

PSA

C1TOCS

0

1

8-bit Prescaler

M

U

X

8

Watchdog

Timer

(1)

8-to-1 MUX

PS<2:0>

(1)

PSA

1

0

WDT Enable bit

(1)

MUX

PSA

WDT

Time-out

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

Preliminary

DS41338B-page 33

MCV14A

NOTES:

DS41338B-page 34

Preliminary

MCV14A

The MCV14A device has a Watchdog Timer, which can

be shut off only through Configuration bit WDTE. It runs

off of its own RC oscillator for added reliability. If using

HS, XT or LP selectable oscillator options, there is

always an 18 ms (nominal) delay provided by the

Device Reset Timer (DRT), intended to keep the chip in

Reset until the crystal oscillator is stable. If using

INTRC or EXTRC, there is a 1 ms delay only on VDD

power-up. With this timer on-chip, most applications

need no external Reset circuitry.

7.0

SPECIAL FEATURES OF THE

CPU

What sets

processors are special circuits that deal with the needs

of real-time applications. The MCV14A

microcontrollers have a host of such features intended

to maximize system reliability, minimize cost through

elimination of external components, provide

power-saving operating modes and offer code

protection. These features are:

a

microcontroller apart from other

The Sleep mode is designed to offer a very low current

Power-Down mode. The user can wake-up from Sleep

through a change on input pins or through a Watchdog

Timer time-out. Several oscillator options are also

made available to allow the part to fit the application,

including an internal 4/8 MHz oscillator. The EXTRC

oscillator option saves system cost while the LP crystal

option saves power. A set of Configuration bits are

used to select various options.

• Oscillator Selection

• Reset:

- Power-on Reset (POR)

- Device Reset Timer (DRT)

- Wake-up from Sleep on Pin Change

• Watchdog Timer (WDT)

• Sleep

• Code Protection

7.1

Configuration Bits

• ID Locations

• In-Circuit Serial Programming™

• Clock Out

The MCV14A Configuration Words consist of 12 bits.

Configuration bits can be programmed to select various

device configurations. Three bits are for the selection of

the oscillator type; one bit is the Watchdog Timer

enable bit, one bit is the MCLR enable bit and one bit is

for code protection (Register 7-1).

Preliminary

DS41338B-page 35

MCV14A

REGISTER 7-1:

CONFIG: CONFIGURATION WORD REGISTER

CPDF

IOSCFS

MCLRE

CP

WDTE

FOSC2

FOSC1

FOSC0

bit 0

bit 7

CPDF: Code Protection bit – Flash Data Memory

1= Code protection off

0= Code protection on

bit 6

bit 5

bit 4

bit 3

IOSCFS: Internal Oscillator Frequency Select bit

1= 8 MHz INTOSC speed

0= 4 MHz INTOSC speed

MCLRE: Master Clear Enable bit

1= RB3/MCLR pin functions as MCLR

0= RB3/MCLR pin functions as RB3, MCLR internally tied to VDD

CP: Code Protection bit – User Program Memory

1= Code protection off

0= Code protection on

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

bit 2-0

FOSC<2:0>: Oscillator Selection bits

000= LP oscillator and 18 ms DRT

001= XT oscillator and 18 ms DRT

010= HS oscillator and 18 ms DRT

011= EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT⁽¹⁾

100= INTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT⁽¹⁾

101= INTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT⁽¹⁾

110= EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT⁽¹⁾

111= EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT⁽¹⁾

Note 1: DRT length (18 ms or 1 ms) is a function of Clock mode selection. It is the responsibility of the application

designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in accept-

able operation. Refer to Section 11.1 “DC Characteristics: MCV14A (Industrial)” and Section 11.2

“DC Characteristics: MCV14A” for VDD rise time and stability requirements for this mode of operation.

DS41338B-page 36

Preliminary

MCV14A

FIGURE 7-1:

CRYSTAL OPERATION

(OR CERAMIC

RESONATOR)

7.2

Oscillator Configurations

7.2.1

OSCILLATOR TYPES

(HS, XT OR LP OSC

CONFIGURATION)

The MCV14A device can be operated in up to six differ-

ent Oscillator modes. The user can program up to three

Configuration bits (FOSC<2:0>). To select one of these

modes:

(1)

C1

OSC1

MCV14A

• LP:

• XT:

• HS:

Low-Power Crystal

Sleep

Crystal/Resonator

XTAL

(3)

RF

To internal

logic

High-Speed Crystal/Resonator

OSC2

• INTRC: Internal 4/8 MHz Oscillator

• EXTRC: External Resistor/Capacitor

(2)

RS

(1)

C2

• EC:

External High-Speed Clock Input

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

7.2.2

CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF approx. value = 10 MΩ.

In HS, XT or LP modes, a crystal or ceramic resonator

is connected to the RB5/OSC1/CLKIN and

RB4/OSC2/CLKOUT pins to establish oscillation

(Figure 7-1). The MCV14A oscillator designs require

the use of a parallel cut crystal. Use of a series cut crys-

tal may give a frequency out of the crystal manufactur-

ers specifications. When in HS, XT or LP modes, the

device can have an external clock source drive the

RB5/OSC1/CLKIN pin (Figure 7-2). This pin should be

left open and unloaded. Also when using this mode, the

external clock should observe the frequency limits for

the Clock mode chosen (HS, XT or LP).

FIGURE 7-2:

EXTERNAL CLOCK INPUT

OPERATION (HS, XT, LP

OR EC OSC

CONFIGURATION)

EC, HS, XT, LP

Clock From

ext. system

RB5/OSC1/CLKIN

MCV14A

Note 1: This device has been designed to per-

form to the parameters of its data sheet.

It has been tested to an electrical

specification designed to determine its

conformance with these parameters.

Due to process differences in the

manufacture of this device, this device

may have different performance charac-

teristics than its earlier version. These

differences may cause this device to

perform differently in your application

than the earlier version of this device.

(1)

OSC2/CLKOUT/RB4

Note 1: RB4 is available in EC mode only.

TABLE 7-1:

CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Osc

Resonator Cap. Range Cap. Range

Type

Freq.

C1

C2

XT

HS

4.0 MHz

16 MHz

30 pF

2: The user should verify that the device

oscillator starts and performs as

expected. Adjusting the loading capacitor

values and/or the Oscillator mode may

be required.

10-47 pF

Note 1: These values are for design guidance

only. Since each resonator has its own

characteristics, the user should consult

the resonator manufacturer for

appropriate values of external

components.

Preliminary

DS41338B-page 37

MCV14A

Figure 7-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a

180-degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

TABLE 7-2:

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR⁽²⁾

Osc

Resonator Cap. Range Cap. Range

Type

Freq.

C1

C2

LP

XT

32 kHz⁽¹⁾

15 pF

200 kHz

1 MHz

4 MHz

47-68 pF

15 pF

47-68 pF

15 pF

FIGURE 7-4:

EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

15 pF

HS

20 MHz

15-47 pF

To Other

Devices

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

330

74AS04

recommended.

74AS04

2: These values are for design guidance

only. Rs may be required to avoid over-

driving crystals with low drive level specifi-

cation. Since each crystal has its own

characteristics, the user should consult

the crystal manufacturer for appropriate

values of external components.

CLKIN

0.1 mF

XTAL

MCV14A

7.2.4

EXTERNAL RC OSCILLATOR

7.2.3

EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the resis-

tor (REXT) and capacitor (CEXT) values, and the operat-

ing temperature. In addition to this, the oscillator

frequency will vary from unit-to-unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to take into account

variation due to tolerance of external R and C

components used.

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Prepackaged oscillators

provide a wide operating range and better stability. A

well-designed crystal oscillator will provide good

performance with TTL gates. Two types of crystal

oscillator circuits can be used: one with parallel

resonance, or one with series resonance.

Figure 7-3 shows implementation of a parallel resonant

oscillator circuit. The circuit is designed to use the fun-

damental frequency of the crystal. The 74AS04 inverter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ potentiome-

ters bias the 74AS04 in the linear region. This circuit

could be used for external oscillator designs.

Figure 7-5 shows how the R/C combination is

connected to the MCV14A device. For REXT values

below 3.0 kΩ, the oscillator operation may become

unstable, or stop completely. For very high REXT values

(e.g., 1 MΩ), the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping

REXT between 5.0 kΩ and 100 kΩ.

FIGURE 7-3:

EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Although the oscillator will operate with no external

capacitor (CEXT = 0pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

+5V

To Other

Devices

10k

74AS04

4.7k

Section 11.0 “Electrical Characteristics” shows RC

frequency variation from part-to-part due to normal

process variation. The variation is larger for larger val-

ues of R (since leakage current variation will affect RC

frequency more for large R) and for smaller values of C

(since variation of input capacitance will affect RC

frequency more).

CLKIN

74AS04

MCV14A

10k

XTAL

10k

20 pF

DS41338B-page 38

Preliminary

MCV14A

Also, see the Electrical Specifications section for

variation of oscillator frequency due to VDD for given

REXT/CEXT values, as well as frequency variation due

to operating temperature for given R, C and VDD

values.

7.2.5

INTERNAL 4/8 MHz RC

OSCILLATOR

The internal RC oscillator provides a fixed 4/8 MHz

(nominal) system clock at VDD = 5V and 25°C, (see

Section 11.0 “Electrical Characteristics” for

information on variation over voltage and temperature).

FIGURE 7-5:

EXTERNAL RC

In addition, a calibration instruction is programmed into

the last address of memory, which contains the

calibration value for the internal RC oscillator. This

location is always non-code protected, regardless of

the code-protect settings. This value is programmed as

a MOVLW XX instruction where XX is the calibration

value, and is placed at the Reset vector. This will load

the W register with the calibration value upon Reset

and the PC will then roll over to the users program at

address 0x000. The user then has the option of writing

the value to the OSCCAL Register (05h) or ignoring it.

OSCILLATOR MODE

VDD

REXT

Internal

clock

OSC1

N

CEXT

VSS

MCV14A

OSC2/CLKOUT

FOSC/4

OSCCAL, when written to with the calibration value, will

“trim” the internal oscillator to remove process variation

from the oscillator frequency.

Note:

Erasing the device will also erase the

pre-programmed internal calibration value

for the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

For the MCV14A device, only bits <7:1> of OSCCAL

are used for calibration. See Register 3-3 for more

information.

Note:

The bit 0 of the OSCCAL register is

unimplemented and should be written as

‘0’ when modifying OSCCAL for

compatibility with future devices.

Preliminary

DS41338B-page 39

MCV14A

Some registers are not reset in any way, they are

unknown on POR and unchanged in any other Reset.

Most other registers are reset to “Reset state” on

Power-on Reset (POR), MCLR, WDT or Wake-up on

pin change Reset during normal operation. They are

not affected by a WDT Reset during Sleep or MCLR

Reset during Sleep, since these Resets are viewed as

resumption of normal operation. The exceptions to this

are TO, PD and RBWUF bits. They are set or cleared

differently in different Reset situations. These bits are

used in software to determine the nature of Reset. See

Table 7-3 for a full description of Reset states of all

registers.

7.3

Reset

The device differentiates between various kinds of

Reset:

• Power-on Reset (POR)

• MCLR Reset during normal operation

• MCLR Reset during Sleep

• WDT Time-out Reset during normal operation

• WDT Time-out Reset during Sleep

• Wake-up from Sleep on pin change

TABLE 7-3:

Register

RESET CONDITIONS FOR REGISTERS

MCLR Reset, WDT Time-out,

Wake-up On Pin Change

Address

Power-on Reset

qqqq qqq0⁽¹⁾

W

—

qqqq qqq0⁽¹⁾

uuuu uuuu

1111 1111

INDF

TMR0

PCL

00h

01h

02h

xxxx xxxx

1111 1111

STATUS

FSR

03h

04h

0001 1xxx

100x xxxx

1111 111-

--xx xxxx

q111 1111

1111 1100

xxxx xxxx

q111 1111

001-1111

qq0q quuu⁽²⁾

1uuu uuuu

uuuu uuu-

--uu uuuu

quuu uuuu

1111 1100

uuuu uuuu

quuu uuuu

uuu-uuuu

OSCCAL

PORTB

PORTC

CMICON0

ADCON0

ADRES

CM2CON0

VRCON

OPTION

TRISB

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

—

1111 1111

--11 1111

---0 x000

xxxx xxxx

--xx xxxx

1111 1111

--11 1111

---0 q000

uuuu uuuu

--uu uuuu

—

TRISC

—

EECON

EEDATA

EEADR

21h/61h

25h/65h

26h/66h

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.

Note 1: Bits <7:1> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of

memory.

2: See Table 7-4 for Reset value for specific conditions.

DS41338B-page 40

Preliminary

MCV14A

TABLE 7-4:

RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h

PCL Addr: 02h

Power-on Reset

0001 1xxx

1111 1111

MCLR Reset during normal operation

MCLR Reset during Sleep

000u uuuu

0001 0uuu

0000 0uuu

0000 uuuu

1001 0uuu

WDT Reset during Sleep

WDT Reset normal operation

Wake-up from Sleep on pin change

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’.

Preliminary

DS41338B-page 41

MCV14A

The Power-on Reset circuit and the Device Reset

Timer (see Section 7.5 “Device Reset Timer (DRT)”)

circuit are closely related. On power-up, the Reset latch

is set and the DRT is reset. The DRT timer begins

counting once it detects MCLR to be high. After the

time-out period, which is typically 18 ms or 1 ms, it will

reset the Reset latch and thus end the on-chip Reset

signal.

7.3.1

MCLR ENABLE

This Configuration bit, when unprogrammed (left in the

‘1’ state), enables the external MCLR function. When

programmed, the MCLR function is tied to the internal

VDD and the pin is assigned to be a I/O. See Figure 7-6.

FIGURE 7-6:

MCLR SELECT

A power-up example where MCLR is held low is shown

in Figure 7-8. VDD is allowed to rise and stabilize before

bringing MCLR high. The chip will actually come out of

Reset TDRT msec after MCLR goes high.

RBWU

RB3/MCLR/VPP

Internal MCLR

In Figure 7-9, the on-chip Power-on Reset feature is

being used (MCLR and VDD are tied together or the pin

is programmed to be RB3. The VDD is stable before the

start-up timer times out and there is no problem in get-

ting a proper Reset. However, Figure 7-10 depicts a

problem situation where VDD rises too slowly. The time

between when the DRT senses that MCLR is high and

when MCLR and VDD actually reach their full value, is

too long. In this situation, when the start-up timer times

out, VDD has not reached the VDD (min) value and the

chip may not function correctly. For such situations, we

recommend that external RC circuits be used to

achieve longer POR delay times (Figure 7-9).

MCLRE

7.4

Power-on Reset (POR)

The MCV14A device incorporates an on-chip

Power-on Reset (POR) circuitry, which provides an

internal chip Reset for most power-up situations.

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. To take advantage of the internal POR,

program the RB3/MCLR/VPP pin as MCLR and tie

through a resistor to VDD, or program the pin as RB3.

An internal weak pull-up resistor is implemented using

a transistor (refer to Table 11-5 for the pull-up resistor

ranges). This will eliminate external RC components

usually needed to create a Power-on Reset. A

maximum rise time for VDD is specified. See

Section 11.0 “Electrical Characteristics” for details.

Note:

When the device starts normal operation

(exit the Reset condition), device operat-

ing parameters (voltage, frequency, tem-

perature, etc.) must be met to ensure

operation. If these conditions are not met,

the device must be held in Reset until the

operating conditions are met.

For additional information, refer to Application Notes

AN522 “Power-Up Considerations” (DS00522) and

AN607 “Power-up Trouble Shooting” (DS00607).

When the device starts normal operation (exit the

Reset condition), device operating parameters

(voltage, frequency, temperature,...) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

parameters are met.

A simplified block diagram of the on-chip Power-on

Reset circuit is shown in Figure 7-7.

DS41338B-page 42

Preliminary

MCV14A

FIGURE 7-7:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

VDD

Power-up

Detect

POR (Power-on Reset)

RB3/MCLR/VPP

MCLR Reset

S

Q

MCLRE

R

Q

Start-up Timer

WDT Reset

WDT Time-out

(10 μs, 1.125 ms

CHIP Reset

or 18 ms)

Pin Change

Sleep

Wake-up on pin Change Reset

FIGURE 7-8:

TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

FIGURE 7-9:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE

TIME

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

Preliminary

DS41338B-page 43

MCV14A

FIGURE 7-10:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

V1

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

Note:

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final

value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

DS41338B-page 44

Preliminary

MCV14A

TABLE 7-5:

TYPICAL DRT PERIODS

7.5

Device Reset Timer (DRT)

Oscillator

Configuration

Subsequent

Resets

On the MCV14A device, the DRT runs any time the

device is powered up. DRT runs from Reset and varies

based on oscillator selection and Reset type (see

Table 7-5).

POR Reset

HS, XT, LP

EC

18 ms

10 μs

1.125 ms

The DRT operates on an internal RC oscillator. The

processor is kept in Reset as long as the DRT is active.

The DRT delay allows VDD to rise above VDD min. and

for the oscillator to stabilize.

INTOSC, EXTRC

7.6.1

WDT PERIOD

Oscillator circuits based on crystals or ceramic

resonators require a certain time after power-up to

establish a stable oscillation. The on-chip DRT keeps

the device in a Reset condition after MCLR has reached

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by

writing to the OPTION register. Thus, a time-out period

of a nominal 2.3 seconds can be realized. These

periods vary with temperature, VDD and part-to-part

process variations (see DC specs).

a

logic high (VIH MCLR) level. Programming

RB3/MCLR/VPP as MCLR and using an external RC

network connected to the MCLR input is not required in

most cases. This allows savings in cost-sensitive and/or

space restricted applications, as well as allowing the use

of the RB3/MCLR/VPP pin as a general purpose input.

Under worst-case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

The Device Reset Time delays will vary from

chip-to-chip due to VDD, temperature and process

variation. See AC parameters for details.

7.6.2

WDT PROGRAMMING

CONSIDERATIONS

The DRT will also be triggered upon a Watchdog Timer

time-out from Sleep. This is particularly important for

applications using the WDT to wake from Sleep mode

automatically.

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from

timing out and generating a device Reset.

Reset sources are POR, MCLR, WDT time-out and

wake-up on pin change. See Section 7.8.2 “Wake-up

from Sleep”, Notes 1, 2 and 3.

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum Sleep time before a WDT wake-up Reset.

7.6

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator, which does not require any external

components. This RC oscillator is separate from the

external RC oscillator of the RB5/OSC1/CLKIN pin and

the internal 4/8 MHz oscillator. This means that the

WDT will run even if the main processor clock has been

stopped, for example, by execution of a SLEEPinstruc-

tion. During normal operation or Sleep, a WDT Reset or

wake-up Reset, generates a device Reset.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer Reset.

The WDT can be permanently disabled by

programming the configuration WDTE as a ‘0’ (see

Section 7.1 “Configuration Bits”). Refer to the

MCV14A Programming Specifications to determine

how to access the Configuration Word.

Preliminary

DS41338B-page 45

MCV14A

FIGURE 7-11:

WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source

(Figure 6-1)

0

M

U

X

Postscaler

1

Watchdog

Time

(1)

8-to-1 MUX

PS<2:0>

PSA

WDT Enable

Configuration

(Figure 6-4)

To Timer0

Bit

0

1

MUX

(1)

PSA

WDT Time-out

Note 1: PSA, PS<2:0> are bits in the OPTION register.

TABLE 7-6:

Address

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

All Other

Resets

Name

Bit 7

Bit 6

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On

Reset

N/A

OPTION

RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer.

DS41338B-page 46

Preliminary

MCV14A

7.8.2

WAKE-UP FROM SLEEP

7.7

Time-out Sequence, Power-down

and Wake-up from Sleep Status

Bits (TO, PD, RBWUF)

The device can wake-up from Sleep through one of

the following events:

1. An external Reset input on RB3/MCLR/VPP pin,

when configured as MCLR.

The TO, PD and RBWUF bits in the STATUS register

can be tested to determine if a Reset condition has

been caused by a power-up condition, a MCLR or

Watchdog Timer (WDT) Reset.

2. A Watchdog Timer Time-out Reset (if WDT was

enabled).

3. A change on input pin RB0, RB1, RB3 or RB4

when wake-up on change is enabled.

TABLE 7-7:

TO/PD/RBWUF STATUS

AFTER RESET

These events cause a device Reset. The TO, PD and

RBWUF bits can be used to determine the cause of

device Reset. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEP is invoked.

The RBWUF bit indicates a change in state while in

Sleep at pins RB0, RB1, RB3 or RB4 (since the last file

or bit operation on RB port).

RBWUF TO PD

Reset Caused By

0

u

WDT wake-up from Sleep

WDT time-out (not from

Sleep)

0

1

u

1

0

1

u

0

MCLR wake-up from Sleep

Power-up

Note:

Caution: Right before entering Sleep,

read the input pins. When in Sleep,

wake-up occurs when the values at the

pins change from the state they were in at

the last reading. If a wake-up on change

occurs and the pins are not read before

re-entering Sleep, a wake-up will occur

immediately even if no pins change while

in Sleep mode.

MCLR not during Sleep

Wake-up from Sleep on pin

change

Legend: u= unchanged

Note 1: The TO, PD and RBWUF bits maintain

their status (u) until a Reset occurs. A

low-pulse on the MCLR input does not

change the TO, PD and RBWUF Status

bits.

The WDT is cleared when the device wakes from

Sleep, regardless of the wake-up source.

7.8

Power-down Mode (Sleep)

A device may be powered down (Sleep) and later

powered up (wake-up from Sleep).

7.8.1

SLEEP

The Power-Down mode is entered by executing a

SLEEPinstruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low or high-impedance).

Note:

A Reset generated by a WDT time-out

does not drive the MCLR pin low.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

RB3/MCLR/VPP pin must be at a logic high level if

MCLR is enabled.

Preliminary

DS41338B-page 47

MCV14A

FIGURE 7-12:

TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

7.9

Program Verification/Code

Protection

If the code protection bit has not been programmed, the

on-chip program memory can be read out for

verification purposes.

To Normal

Connections

External

Connector

Signals

The first 64 locations and the last location (OSCCAL)

can be read, regardless of the code protection bit

setting.

MCV14A

+5V

0V

VDD

The last memory location can be read regardless of the

code protection bit setting on the MCV14A device.

VSS

VPP

MCLR/VPP

7.10 ID Locations

RB1

RB0

CLK

Four memory locations are designated as ID locations

where the user can store checksum or other code

identification numbers. These locations are not

accessible during normal execution, but are readable

and writable during Program/Verify.

Data I/O

VDD

To Normal

Connections

Use only the lower 4 bits of the ID locations and always

program the upper 8 bits as ‘0’s.

7.11 In-Circuit Serial Programming™

The MCV14A microcontroller can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware, or a custom

firmware, to be programmed.

The devices are placed into a Program/Verify mode by

holding the RB1 and RB0 pins low while raising the

MCLR (VPP) pin from VIL to VIHH. RB1 becomes the

programming clock and B0 becomes the programming

data. Both RB1 and RB0 are Schmitt Trigger inputs in

this mode.

After Reset, a 6-bit command is then supplied to the

device. Depending on the command, 14 bits of program

data are then supplied to or from the device, depending

if the command was a Load or a Read.

A typical In-Circuit Serial Programming connection is

shown in Figure 7-12.

DS41338B-page 48

Preliminary

MCV14A

8.0

ANALOG-TO-DIGITAL (A/D)

CONVERTER

Note:

It is the users responsibility to ensure that

use of the ADC and comparator simulta-

neously on the same pin, does not

adversely affect the signal being

monitored or adversely effect device

operation.

The A/D Converter allows conversion of an analog

signal into an 8-bit digital signal.

8.1

Clock Divisors

The ADC has 4 clock source settings ADCS<1:0>.

There are 3 divisor values 16, 8 and 4. The fourth

setting is INTOSC with a divisor of 4. These settings

will allow a proper conversion when using an external

oscillator at speeds from 20 MHz to 350 kHz. Using an

external oscillator at a frequency below 350 kHz

requires the ADC oscillator setting to be INTOSC/4

(ADCS<1:0> = 11) for valid ADC results.

When the CHS<1:0> bits are changed during an ADC

conversion, the new channel will not be selected until

the current conversion is completed. This allows the

current conversion to complete with valid results. All

channel selection information will be lost when the

device enters Sleep.

TABLE 8-1:

CHANNEL SELECT (ADCS)

BITS AFTER AN EVENT

The ADC requires 13 TAD periods to complete a

conversion. The divisor values do not affect the number

of TAD periods required to perform a conversion. The

divisor values determine the length of the TAD period.

Event

ADCS<1:0>

MCLR

11

CS<1:0>

11

When the ADCS<1:0> bits are changed while an ADC

conversion is in process, the new ADC clock source will

not be selected until the next conversion is started. This

clock source selection will be lost when the device

enters Sleep.

Conversion completed

Conversion terminated

Power-on

Wake from Sleep

11

Note:

The ADC clock is derived from the instruc-

tion clock. The ADCS divisors are then

applied to create the ADC clock

8.1.4

THE GO/DONE BIT

The GO/DONE bit is used to determine the status of a

conversion, to start a conversion and to manually halt

a conversion in process. Setting the GO/DONE bit

starts a conversion. When the conversion is complete,

the ADC module clears the GO/DONE bit. A conver-

sion can be terminated by manually clearing the GO/

DONE bit while a conversion is in process. Manual ter-

mination of a conversion may result in a partially con-

verted result in ADRES.

8.1.1

VOLTAGE REFERENCE

There is no external voltage reference for the ADC. The

ADC reference voltage will always be VDD.

8.1.2

ANALOG MODE SELECTION

The ANS<1:0> bits are used to configure pins for

analog input. Upon any Reset, ANS<1:0> defaults to

11. This configures pins AN0, AN1 and AN2 as analog

inputs. The comparator output, C1OUT, will override

AN2 as an input if the comparator output is enabled.

Pins configured as analog inputs are not available for

digital output. Users should not change the ANS bits

while a conversion is in process. ANS bits are active

regardless of the condition of ADON.

The GO/DONE bit is cleared when the device enters

Sleep, stopping the current conversion. The ADC does

not have a dedicated oscillator, it runs off of the instruc-

tion clock. Therefore, no conversion can occur in sleep.

The GO/DONE bit cannot be set when ADON is clear.

8.1.3

ADC CHANNEL SELECTION

The CHS bits are used to select the analog channel to

be sampled by the ADC. The CHS<1:0> bits can be

changed at any time without adversely effecting a con-

version. To acquire an analog signal the CHS<1:0>

selection must match one of the pin(s) selected by the

ANS<1:0> bits. When the ADC is on (ADON = 1) and a

channel is selected that is also being used by the

comparator, then both the comparator and the ADC will

see the analog voltage on the pin.

Preliminary

DS41338B-page 49

MCV14A

8.1.5

SLEEP

This ADC does not have a dedicated ADC clock, and

therefore, no conversion in Sleep is possible. If a

conversion is underway and a Sleep command is

executed, the GO/DONE and ADON bit will be cleared.

This will stop any conversion in process and power-

down the ADC module to conserve power. Due to the

nature of the conversion process, the ADRES may con-

tain a partial conversion. At least 1 bit must have been

converted prior to Sleep to have partial conversion data

in ADRES. The ADCS and CHS bits are reset to their

default condition; ANS<1:0> = 11and CHS<1:0> = 11.

• For accurate conversions, TAD must meet the

following:

• 500 ns < TAD < 50 μs

• TAD = 1/(FOSC/divisor)

Shaded areas indicate TAD out of range for accurate

conversions. If analog input is desired at these

frequencies, use INTOSC/8 for the ADC clock source.

TABLE 8-2:

TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS

ADCS

<1:0>

20

MHz

16

MHz

500

kHz

350

kHz

200

kHz

100

kHz

Source

Divisor

8 MHz 4 MHz 1 MHz

32 kHz

INTOSC

FOSC

11

10

01

00

4

—

.5 μs

1 μs

2 μs

4 μs

—

.2 μs .25 μs .5 μs

4 μs

8 μs

11 μs 20 μs 40 μs 125 μs

8

.4 μs

.8 μs

.5 μs

1 μs

2 μs

16 μs 23 μs 40 μs 80 μs 250 μs

16

16 μs 32 μs 46 μs 80 μs 160 μs 500 μs

TABLE 8-3:

EFFECTS OF SLEEP ON ADCON0

ANS1

ANS0

ADCS1

ADCS0

CHS1

CHS0

GO/DONE

ADON

Entering

Sleep

Unchanged Unchanged

1

0

Wake or

Reset

1

0

DS41338B-page 50

Preliminary

MCV14A

right shifts of the ‘leading one’ have taken place, the

conversion is complete; the ‘leading one’ has been

shifted out and the GO/DONE bit is cleared.

8.1.6

ANALOG CONVERSION RESULT

REGISTER

The ADRES register contains the results of the last

conversion. These results are present during the

sampling period of the next analog conversion process.

After the sampling period is over, ADRES is cleared

(= 0). A ‘leading one’ is then right shifted into the

ADRES to serve as an internal conversion complete

bit. As each bit weight, starting with the MSB, is

converted, the leading one is shifted right and the

converted bit is stuffed into ADRES. After a total of 9

If the GO/DONE bit is cleared in software during a

conversion, the conversion stops. The data in ADRES

is the partial conversion result. This data is valid for the

bit weights that have been converted. The position of

the ‘leading one’ determines the number of bits that

have been converted. The bits that were not converted

before the GO/DONE was cleared are unrecoverable.

REGISTER 8-1:

ADCON0: A/D CONTROL REGISTER

R/W-1

ANS0

R/W-1

CHS1

R/W-1

CHS0

R/W-0

ADON

ANS1

bit 7

ADCS1

ADCS0

GO/DONE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

(1), (2), (5)

bit 7-6

bit 5-4

bit 3-2

bit 1

ANS<1:0>: ADC Analog Input Pin Select bits

00= No pins configured for analog input

01= AN2 configured as an analog input

10= AN2 and AN0 configured as analog inputs

11= AN2, AN1 and AN0 configured as analog inputs

ADCS<1:0>: ADC Conversion Clock Select bits

00= FOSC/16

01= FOSC/8

10= FOSC/4

11= INTOSC/4

(3, 5)

CHS<1:0>: ADC Channel Select bits

00= Channel AN0

01= Channel AN1

10= Channel AN2

11= 0.6V absolute voltage reference

(4)

GO/DONE: ADC Conversion Status bit

1= ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared

by hardware when the ADC is done converting.

0= ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process termi-

nates the current conversion.

bit 0

ADON: ADC Enable bit

1= ADC module is operating

0= ADC module is shut-off and consumes no power

Note 1: When the ANS bits are set, the channels selected will automatically be forced into Analog mode, regardless of the pin

function previously defined. The only exception to this is the comparator, where the analog input to the comparator and

the ADC will be active at the same time. It is the users responsibility to ensure that the ADC loading on the comparator

input does not affect their application.

2: The ANS<1:0> bits are active regardless of the condition of ADON.

3: CHS<1:0> bits default to 11after any Reset.

4: If the ADON bit is clear, the GO/DONE bit cannot be set.

5: C1OUT, when enabled, overrides AN2.

Preliminary

DS41338B-page 51

MCV14A

REGISTER 8-2:

ADRES: ADDRESS REGISTER

R/W-X

ADRES6

R/W-X

ADRES7

ADRES5

ADRES4

ADRES3

ADRES2

ADRES1

ADRES0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

EXAMPLE 8-1:

PERFORMING AN

ANALOG-TO-DIGITAL

CONVERSION

EXAMPLE 8-2:

CHANNEL SELECTION

CHANGE DURING

CONVERSION

MOVLW 0xF1

MOVWF ADCON0

;configure A/D

;Sample code operates out of BANK0

MOVLW 0xF1

;configure A/D

BSF ADCON0, 1 ;start conversion

BSF ADCON0, 2 ;setup for read of

;channel 1

BTFSC ADCON0, 1;wait for ‘DONE’

GOTO loop0

MOVWF ADCON0

BSF ADCON0, 1 ;start conversion

BTFSC ADCON0, 1;wait for ‘DONE’

GOTO loop0

MOVF ADRES, W ;read result

MOVWF result0 ;save result

loop0

loop1

loop2

loop0

MOVF ADRES, W ;read result

MOVWF result0 ;save result

BSF ADCON0, 2 ;setup for read of

;channel 1

BSF ADCON0, 1 ;start conversion

BTFSC ADCON0, 1;wait for ‘DONE’

GOTO loop1

BSF ADCON0, 1 ;start conversion

BSF ADCON0, 3 ;setup for read of

BCF ADCON0, 2 ;channel 2

BTFSC ADCON0, 1;wait for ‘DONE’

GOTO loop1

loop1

loop2

MOVF ADRES, W ;read result

MOVWF result1 ;save result

MOVF ADRES, W ;read result

MOVWF result1 ;save result

BSF ADCON0, 3 ;setup for read of

BCF ADCON0, 2 ;channel 2

BSF ADCON0, 1 ;start conversion

BTFSC ADCON0, 1;wait for ‘DONE’

GOTO loop2

BSF ADCON0, 1 ;start conversion

BTFSC ADCON0, 1;wait for ‘DONE’

GOTO loop2

MOVF ADRES, W ;read result

MOVWF result2 ;save result

CLRF ADCON0

;pins to Digital mode and turns off

;the ADC module

MOVF ADRES, W ;read result

MOVWF result2 ;save result

;optional: returns

DS41338B-page 52

Preliminary

MCV14A

9.0

COMPARATOR(S)

This device contains two comparators and

comparator voltage reference.

a

REGISTER 9-1:

CM1CON0: COMPARATOR C1 CONTROL REGISTER

R-1

C1OUT

bit 7

R/W-1

C1ON

R/W-1

C1PREF

R/W-1

C1WU

C1OUTEN

C1POL

C1T0CS

C1NREF

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

C1OUT: Comparator Output bit

1= VIN+ > VIN-

0= VIN+ < VIN-

C1OUTEN: Comparator Output Enable bit^{(1), (2)}

1= Output of comparator is NOT placed on the C1OUT pin

0= Output of comparator is placed in the C1OUT pin

C1POL: Comparator Output Polarity bit⁽²⁾

1= Output of comparator is not inverted

0= Output of comparator is inverted

C1T0CS: Comparator TMR0 Clock Source bit⁽²⁾

1= TMR0 clock source selected by T0CS control bit

0= Comparator output used as TMR0 clock source

C1ON: Comparator Enable bit

1= Comparator is on

0= Comparator is off

C1NREF: Comparator Negative Reference Select bit⁽²⁾

1= C1IN- pin

0= 0.6V VREF

C1PREF: Comparator Positive Reference Select bit⁽²⁾

1= C1IN+ pin

0= C1IN- pin

C1WU: Comparator Wake-up On Change Enable bit⁽²⁾

1= Wake-up On Comparator Change is disabled

0= Wake-up On Comparator Change is enabled

Note 1: Overrides T0CS bit for TRIS control of RB2.

2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have

precedence.

Preliminary

DS41338B-page 53

MCV14A

REGISTER 9-2:

CM2CON0: COMPARATOR C2 CONTROL REGISTER

R-1

R/W-1

C2OUTEN

R/W-1

C2ON

R/W-1

C2WU

C2OUT

C2POL

C2PREF2

C2NREF

C2PREF1

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

C2OUT: Comparator Output bit

1= VIN+ > VIN-

0= VIN+ < VIN-

C2OUTEN: Comparator Output Enable bit^{(1), (2)}

1= Output of comparator is NOT placed on the C2OUT pin

0= Output of comparator is placed in the C2OUT pin

C2POL: Comparator Output Polarity bit⁽²⁾

1= Output of comparator not inverted

0= Output of comparator inverted

C2PREF2: Comparator Positive Reference Select bit⁽²⁾

1= C1IN+ pin

0= C2IN- pin

C2ON: Comparator Enable bit

1= Comparator is on

0= Comparator is off

C2NREF: Comparator Negative Reference Select bit⁽²⁾

1= C2IN- pin

0= CVREF

C2PREF1: Comparator Positive Reference Select bit⁽²⁾

1= C2IN+ pin

0= C2PREF2 controls analog input selection

C2WU: Comparator Wake-up on Change Enable bit⁽²⁾

1= Wake-up on Comparator change is disabled

0= Wake-up on Comparator change is enabled.

Note 1: Overrides TOCS bit for TRIS control of RC4.

2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have

precedence.

DS41338B-page 54

Preliminary

MCV14A

FIGURE 9-1:

COMPARATORS BLOCK DIAGRAM

RB2/C1OUT

C1OUTEN

C1PREF

C1IN+

C1IN-

1

+

0

C1OUT (Register)

1

-

VREF

(0.6V)

0

C1NREF

C1POL

C1ON

0

1

T0CKI

T0CKI Pin

C1T0CS

Q

D

S

READ

CM1CON0

RC4/C2OUT

C2OUTEN

C2PREF1

C2IN+

1

0

+

-

1

0

C2OUT (Register)

C2PREF2

C2IN-

C2POL

C2ON

1

0

CVREF

C2NREF

Q

D

S

C1WU

C2WU

READ

CM2CON0

CWUF

Preliminary

DS41338B-page 55

MCV14A

9.1

Comparator Operation

Note:

Analog levels on any pin that is defined as

a digital input may cause the input buffer

to consume more current than is specified.

A single comparator is shown in Figure 9-2 along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input VIN-, the output of the comparator

is a digital low level. The shaded area of the output of

the comparator in Figure 9-2 represent the uncertainty

due to input offsets and response time. See Table 11-2

for Common Mode Voltage.

9.5

Comparator Wake-up Flag

The Comparator Wake-up Flag is set whenever all of

the following conditions are met:

• C1WU = 0(CM1CON0<0>) or

C2WU = 0(CM2CON0<0>)

FIGURE 9-2:

SINGLE COMPARATOR

• CM1CON0 or CM2CON0 has been read to latch

the last known state of the C1OUT and C2OUT bit

(MOVF CM1CON0, W)

VIN+

VIN-

+

Result

• Device is in Sleep

–

• The output of a comparator has changed state

The wake-up flag may be cleared in software or by

another device Reset.

9.6

Comparator Operation During

Sleep

VIN-

VIN+

When the comparator is enabled it is active. To

minimize power consumption while in Sleep mode, turn

off the comparator before entering Sleep.

Result

9.7

Effects of Reset

A Power-on Reset (POR) forces the CM2CON0

register to its Reset state. This forces the Comparator

input pins to analog Reset mode. Device current is

minimized when analog inputs are present at Reset

time.

9.2

Comparator Reference

An internal reference signal may be used depending on

the comparator operating mode. The analog signal that

is present at VIN- is compared to the signal at VIN+, and

the digital output of the comparator is adjusted accord-

ingly (Figure 9-2). Please see Section 10.0 “Compar-

ator Voltage Reference Module” for internal

reference specifications.

9.8

Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 9-3. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input, therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

maximum source impedance of 10 kΩ is recom-

mended for the analog sources. Any external compo-

nent connected to an analog input pin, such as a

capacitor or a Zener diode, should have very little

leakage current.

9.3

Comparator Response Time

Response time is the minimum time after selecting a

new reference voltage or input source before the

comparator output is to have a valid level. If the

comparator inputs are changed, a delay must be used

to allow the comparator to settle to its new state.

Please see Table 11-3 for comparator response time

specifications.

9.4

Comparator Output

The comparator output is read through the CM1CON0

or CM2CON0 register. This bit is read-only. The

comparator output may also be used externally, see

Figure 9-2.

DS41338B-page 56

Preliminary

MCV14A

FIGURE 9-3:

ANALOG INPUT MODE

VDD

VT = 0.6V

RIC

RS < 10 K

AIN

ILEAKAGE

±500 nA

CPIN

5 pF

VA

VT = 0.6V

VSS

Legend:

CPIN

VT

= Input Capacitance

= Threshold Voltage

ILEAKAGE = Leakage Current at the Pin

RIC

RS

VA

= Interconnect Resistance

= Source Impedance

= Analog Voltage

TABLE 9-1:

REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Value on All

Other Resets

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on POR

STATUS

RBWUF

C1OUT

CWUF

PA0

TO

PD

Z

DC

C

0001 1xxx

1111 1111

qq0q quuu

uuuu uuuu

CM1CON0

C1OUTEN C1POL

C1T0CS

C1ON

C2ON

C1NREF

C1PREF

C1WU

C2WU

CM2CON0

TRIS

C2OUT

—

C2OUTEN C2POL C2PREF2

C2NREF C2PREF1

1111 1111

--11 1111

uuuu uuuu

--11 1111

—

I/O Control Register (PORTB, PORTC)

Legend:

x= Unknown, u= Unchanged, – = Unimplemented, read as ‘0’, q= Depends on condition.

Preliminary

DS41338B-page 57

MCV14A

NOTES:

DS41338B-page 58

Preliminary

MCV14A

10.2 Voltage Reference Accuracy/Error

10.0 COMPARATOR VOLTAGE

REFERENCE MODULE

The full range of VSS to VDD cannot be realized due to

construction of the module. The transistors on the top

and bottom of the resistor ladder network (Figure 10-1)

keep CVREF from approaching VSS or VDD. The excep-

tion is when the module is disabled by clearing the

VREN bit (VRCON<7>). When disabled, the reference

voltage is VSS when VR<3:0> is ‘0000’ and the VRR

(VRCON<5>) bit is set. This allows the comparator to

detect a zero-crossing and not consume the CVREF

module current.

The Comparator Voltage Reference module also

allows the selection of an internally generated voltage

reference for one of the C2 comparator inputs. The

VRCON register (Register 10-1) controls the Voltage

Reference module shown in Figure 10-1.

10.1 Configuring The Voltage

Reference

The voltage reference can output 32 voltage levels; 16

in a high range and 16 in a low range.

The voltage reference is VDD derived and, therefore,

the CVREF output changes with fluctuations in VDD.

The tested absolute accuracy of the comparator

voltage reference can be found in Section 11.2 “DC

Characteristics: MCV14A”.

Equation 10-1 determines the output voltages:

EQUATION 10-1:

VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD

VRR = 0 (high range):

CVREF = (VDD/4) + (VR<3:0> x VDD/32)

REGISTER 10-1: VRCON: VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

VREN

R/W-0

VROE

R/W-0

VRR

U-0

—

R/W-0

VR3

R/W-0

VR2

R/W-0

VR1

R/W-0

VR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

VREN: CVREF Enable bit

1= CVREF is powered on

0= CVREF is powered down, no current is drawn

VROE: CVREF Output Enable bit⁽¹⁾

1= CVREF output is enabled

0= CVREF output is disabled

VRR: CVREF Range Selection bit

1= Low range

0= High range

bit 4

Unimplemented: Read as ‘0’

bit 3-0

VR<3:0> CVREF Value Selection bit

When VRR = 1: CVREF= (VR<3:0>/24)*VDD

When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD

Note 1: When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the

CVREF pin.

2: CVREF controls for ratio metric reference applies to Comparator 2.

Preliminary

DS41338B-page 59

MCV14A

FIGURE 10-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

8R

R

VDD

8R

VRR

16-1 Analog

MUX

VREN

CVREF to

Comparator 2

Input

VR<3:0>

RC2/CVREF

VREN

VR<3:0> = 0000

VRR

VROE

TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Value on all

other Resets

Name

VRCON

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on POR

VREN

C1OUT

C2OUT

VROE

VRR

—

VR3

VR2

VR1

VR0

000- 0000

1111 1111

000- 0000

uuuu uuuu

CM1CON0

C1OUTEN

C2OUTEN

C1POL

C2POL

C1T0CS

C2PREF2

C1ON

C2ON

C1NREF

C1PREF

C1WU

C2WU

CM2CON0

C2NREF C2PREF1

Legend:

x= unknown, u= unchanged, – = unimplemented, read as ‘0’.

DS41338B-page 60

Preliminary

MCV14A

11.0 ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Ambient temperature under bias............................................................................................................-40°C to +85°C

Storage temperature ............................................................................................................................-65°C to +150°C

Voltage on VDD with respect to VSS ...............................................................................................................0 to +6.5V

Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V

Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾..................................................................................................................................700 mW

Max. current out of VSS pin ................................................................................................................................200 mA

Max. current into VDD pin...................................................................................................................................150 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................±20 mA

Max. output current sunk by any I/O pin ..............................................................................................................25 mA

Max. output current sourced by any I/O pin.........................................................................................................25 mA

Max. output current sourced by I/O port ..............................................................................................................75 mA

Max. output current sunk by I/O port ...................................................................................................................75 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

^†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

Preliminary

DS41338B-page 61

MCV14A

FIGURE 11-1:

MCV14A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C

6.0

5.5

5.0

4.5

VDD

(Volts)

4.0

3.5

3.0

2.5

INTOSC

ONLY

2.0

0

8

4

10

20

25

Frequency (MHz)

FIGURE 11-2:

MAXIMUM OSCILLATOR FREQUENCY TABLE

LP

XT

XTRC

INTOSC

EC

HS

0

200 kHz

4 MHz

20 MHz

8 MHz

Frequency

DS41338B-page 62

Preliminary

MCV14A

11.1 DC Characteristics: MCV14A (Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 40°C ≤ TA ≤ +85°C (industrial)

DC Characteristics

Param

Sym

No.

Characteristic

Supply Voltage

RAM Data Retention Voltage⁽²⁾

Min Typ⁽¹⁾Max Units

Conditions

D001

D002

D003

VDD

2.0

—

5.5

—

V

See Figure 11-1

VDR

1.5*

Vss

Device in Sleep mode

VPOR

VDD Start Voltage to ensure

Power-on Reset

—

See Section 7.4 “Power-on

Reset (POR)” for details

D004

D010

SVDD

IDD

VDD Rise Rate to ensure

Power-on Reset

Supply Current^(3,4)

0.05*

—

V/ms See Section 7.4 “Power-on

Reset (POR)” for details

—

175

400

250

700

μA

FOSC = 4 MHz, VDD = 2.0V

FOSC = 4 MHz, VDD = 5.0V

mA

—

250

0.75

450

1.2

μA

mA

FOSC = 8 MHz, VDD = 2.0V

FOSC = 8 MHz, VDD = 5.0V

—

1.8

2.5

mA

FOSC = 20 MHz, VDD = 5.0V

—

11

38

22

55

μA

FOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 5.0V

D020

D022

IPD

Power-down Current⁽⁵⁾

WDT Current⁽⁵⁾

—

0.1

0.35

1.2

2.2

μA

VDD = 2.0V

VDD = 5.0V

IWDT

—

1.0

7.0

3.0

16.0

μA

VDD = 2.0V

VDD = 5.0V

D023 ICMP Comparator Current⁽⁵⁾

—

15

60

26

76

μA

VDD = 2.0V (per comparator)

VDD = 5.0V (per comparator)

D022

D023

IVREF

IFVR

VREF Current⁽⁵⁾

—

30

75

135

μA

VDD = 2.0V (high range)

VDD = 5.0V (high range)

Internal 0.6V Fixed Voltage

Reference Current⁽⁵⁾

—

100

120

μA

VDD = 2.0V (reference and 1

comparator enabled)

—

175

205

μA

VDD = 5.0V (reference and 1

comparator enabled)

D024

ΔIAD

A/D Conversion Current

—

120

200

150

250

μA

2.0V

5.0V

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

4: The test conditions for all IDD measurements in Active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR =

VDD; WDT enabled/disabled as specified.

5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep

mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.

6: Does not include current through REXT. The current through the resistor can be estimated by the formula:

I = VDD/2REXT (mA) with REXT in kΩ.

Preliminary

DS41338B-page 63

MCV14A

11.2 DC Characteristics: MCV14A

TABLE 11-1: DC CHARACTERISTICS: MCV14A (Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating temperature -40°C ≤ TA ≤ +85°C (industrial)

Operating voltage VDD range as described in DC spec.

DC CHARACTERISTICS

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

VIL

Input Low Voltage

I/O ports

D030

D030A

D031

D032

D033

with TTL buffer

Vss

—

0.8V

V

For all 4.5 ≤ VDD ≤ 5.5V

0.15 VDD

0.3 VDD

0.3

Otherwise

with Schmitt Trigger buffer

MCLR, T0CKI

(1)

OSC1 (EXTRC mode), EC

OSC1 (HS mode)

OSC1 (XT and LP modes)

VIH Input High Voltage

I/O ports

—

D040

with TTL buffer

2.0

VDD

V

4.5 ≤ VDD ≤ 5.5V

D040A

0.25VDD

+ 0.8V

Otherwise

D041

D042

D042A

D043

D070

with Schmitt Trigger buffer

MCLR, T0CKI

0.85VDD

0.7VDD

1.6

—

VDD

400

V

For entire VDD range

(1)

OSC1 (EXTRC mode), EC

OSC1 (HS mode)

—

V

—

V

OSC1 (XT and LP modes)

—

V

(4)

IPUR PORTB weak pull-up current

50

250

μA

VDD = 5V, VPIN = VSS

(2)

IIL

Input Leakage Current

D060

D061

D063

I/O ports

—

±0.7

—

±1

±5

μA

Vss ≤ VPIN ≤ VDD, Pin at high-impedance

Vss ≤ VPIN ≤ VDD

(3)

RB3/MCLR

OSC1

Vss ≤ VPIN ≤ VDD, XT, HS and LP osc

configuration

Output Low Voltage

I/O ports

D080

D083

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V, –40°C to +85°C

IOL = 1.6 mA, VDD = 4.5V, –40°C to +85°C

CLKOUT

Output High Voltage

(2)

D090

D092

I/O ports

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V, –40°C to +85°C

IOH = -1.3 mA, VDD = 4.5V, –40°C to +85°C

CLKOUT

Capacitive Loading Specs on Output Pins

D100

D101

OSC2 pin

—

15

50

pF

In XT, HS and LP modes when external clock is

used to drive OSC1.

All I/O pins and OSC2

—

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

MCV14A be driven with external clock in RC mode.

2: Negative current is defined as coming out of the pin.

3: This spec. applies to RB3/MCLR configured as RB3 with internal pull-up disabled.

4: This spec applies to all weak pull-up devices, including the weak pull-up found on RB3/MCLR. The current value listed will

be the same whether or not the pin is configured as RB3 with pull-up enabled or as MCLR.

DS41338B-page 64

Preliminary

MCV14A

TABLE 11-2: COMPARATOR SPECIFICATIONS.

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C to 85°C

Comparator Specifications

Characteristics

Sym

Min

Typ

Max

Units

Comments

VIVRF

Internal Voltage Reference

0.50

0.60

0.70

V

VOS

Input offset voltage

Input common mode voltage*

CMRR*

—

0

± 5.0

—

± 10

VDD – 1.5

—

mV

V

VCM

CMRR

TRT

55

—

db

Response Time^(1)*

—

150

—

400

10

ns

Comparator Mode Change to

Output Valid*

TMC2COV

μs

*

These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from

VSS to VDD – 1.5V.

TABLE 11-3: COMPARATOR VOLTAGE REFERENCE (VREF) SPECIFICATIONS

Sym

Characteristics

Min

Typ

Max

Units

Comments

CVRES Resolution

—

VDD/24*

VDD/32

—

LSb

Low Range (VRR = 1)

High Range (VRR = 0)

Absolute Accuracy⁽²⁾

—

±1/2*

LSb

Low Range (VRR = 1)

High Range (VRR = 0)

Unit Resistor Value (R)

Settling Time⁽¹⁾

—

2K*

—

Ω

—

10*

μs

*

These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from 0000to 1111.

2: Do not use reference externally when VDD < 2.7V. Under this condition, reference should only be used

with comparator Voltage Common mode observed.

Preliminary

DS41338B-page 65

MCV14A

TABLE 11-4: A/D CONVERTER CHARACTERISTICS:

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

A/D Converter Specifications

Param

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

No.

A01

NR

Resolution

—

8

bit

A03

A04

EINL Integral Error

±1.5

LSb VDD = 5.0V

EDNL Differential Error

-1< EDNL ≤1.7 LSb No missing codes to 8 bits

VDD = 5.0V

A06

A07

A10

A25

EOFF Offset Error

EGN Gain Error

—

-0.7

—

±1.5

+2.2

—

LSb VDD = 5.0V

—

guaranteed⁽¹⁾

—

Monotonicity

—

V

VSS ≤ VAIN ≤ VDD

VAIN Analog Input

Voltage

VSS

VDD

A30

ZAIN Recommended

Impedance of

Analog Voltage

Source

—

10

KΩ

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

TABLE 11-5: PULL-UP RESISTOR RANGES

VDD (Volts)

RB0/RB1

Temperature (°C)

Min

Typ

Max

Units

2.0

-40

25

73K

82K

86K

15K

19K

23K

105K

113K

123K

132k

21K

186K

187K

190K

33K

Ω

85

125

-40

25

5.5

22K

34K

85

26k

35K

125

29K

35K

RB3

2.0

-40

25

63K

77K

82K

86K

16K

24K

26K

81K

93K

96k

96K

116K

119K

22K

Ω

85

125

-40

25

100K

20k

5.5

21K

25k

23K

85

28K

125

27K

29K

DS41338B-page 66

Preliminary

MCV14A

11.3 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

T Time

Lowercase subscripts (pp) and their meanings:

pp

2

to

mc

osc

os

MCLR

ck

cy

drt

io

CLKOUT

Cycle time

Device Reset Timer

I/O port

Oscillator

OSC1

t0

T0CKI

wdt

Watchdog Timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (high-impedance)

Low

Valid

L

High-impedance

FIGURE 11-3:

LOAD CONDITIONS

Legend:

CL

CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

modes when external clock

is used to drive OSC1

VSS

Preliminary

DS41338B-page 67

MCV14A

FIGURE 11-4:

EXTERNAL CLOCK TIMING

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

TABLE 11-6: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),

Operating Voltage VDD range is described in Section 11.1 “DC

Characteristics: MCV14A (Industrial)”

AC CHARACTERISTICS

Param

Sym

Characteristic

Min Typ⁽¹⁾

Max Units

Conditions

No.

1A

FOSC External CLKIN Frequency⁽²⁾DC

—

4

20

200

4

MHz XT Oscillator mode

MHz HS Oscillator mode

DC

kHz LP Oscillator mode

MHz EXTRC Oscillator mode

MHz XT Oscillator mode

MHz HS Oscillator mode

kHz LP Oscillator mode

ns XT Oscillator mode

ns HS Oscillator mode

μs LP Oscillator mode

ns EXTRC Oscillator mode

Oscillator Frequency⁽²⁾

—

0.1

4

20

200

—

1

TOSC

External CLKIN Period⁽²⁾

Oscillator Period⁽²⁾

250

50

5

250

50

5

10,000 ns XT Oscillator mode

250

—

ns HS Oscillator mode

μs LP Oscillator mode

ns

2

3

TCY

Instruction Cycle Time

200 4/FOSC

—

TosL, Clock in (OSC1) Low or High 50*

TosH Time

—

ns XT Oscillator

μs LP Oscillator

ns HS Oscillator

ns XT Oscillator

ns LP Oscillator

ns HS Oscillator

2*

—

10*

—

4

TosR, Clock in (OSC1) Rise or Fall

TosF Time

—

25*

50*

15*

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption. When an external clock

input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

DS41338B-page 68

Preliminary

MCV14A

TABLE 11-7: CALIBRATED INTERNAL RC FREQUENCIES

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),

Operating Voltage VDD range is described in

AC CHARACTERISTICS

Section 11.1 “DC Characteristics: MCV14A (Industrial)”

Param

Freq

Tolerance

Sym

Characteristic

Min Typ†

Max Units

Conditions

No.

F10

FOSC

Internal Calibrated

± 1%

± 5%

7.92 8.00

7.60 8.00

8.08 MHz 3.5V, +25°C

INTOSC Frequency⁽¹⁾

8.40 MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (Ind.)

*

These parameters are characterized but not tested.

†

Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.

Preliminary

DS41338B-page 69

MCV14A

FIGURE 11-5:

I/O TIMING

Q1

Q2

Q3

Q4

OSC1

I/O Pin

(input)

17

18

19

I/O Pin

(output)

New Value

Old Value

20, 21

Note:

All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

TABLE 11-8: TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

AC

CHARACTERISTICS Operating Voltage VDD range is described in Section 11.1 “DC Characteristics: MCV14A

(Industrial)”

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

17

18

19

20

21

TOSH2IOV OSC1↑ (Q1 cycle) to Port Out Valid^{(2), (3)}

TOSH2IOI

OSC1↑ (Q2 cycle) to Port Input Invalid (I/O in hold time)⁽²⁾

TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time)

—

10

100*

—

ns

—

TIOR

TIOF

Port Output Rise Time⁽³⁾

Port Output Fall Time⁽³⁾

50**

58**

Legend: TBD = To Be Determined.

*

These parameters are characterized but not tested.

** These parameters are design targets and are not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: Measurements are taken in EXTRC mode.

3: See Figure 11-3 for loading conditions.

DS41338B-page 70

Preliminary

MCV14A

FIGURE 11-6:

RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING

VDD

MCLR

30

Internal

POR

32

DRT

(2)

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

(1)

I/O pin

Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.

2: Runs in MCLR or WDT Reset only in XT, LP and HS modes.

TABLE 11-9: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage VDD range is described in

AC CHARACTERISTICS

Section 11.1 “DC Characteristics: MCV14A (Industrial)”

Param

Sym

No.

Characteristic

Min Typ⁽¹⁾Max Units

Conditions

30

31

TMCL MCLR Pulse Width (low)

2000*

9*

—

ns

VDD = 5.0V

TWDT Watchdog Timer Time-out Period

(no prescaler)

18*

30*

ms

VDD = 5.0V (Industrial)

32

34

TDRT

TIOZ

Device Reset Timer Period

9*

—

18*

—

30*

ms

ns

I/O High-impedance from MCLR

low

2000*

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

Preliminary

DS41338B-page 71

MCV14A

FIGURE 11-7:

TIMER0 CLOCK TIMINGS

T0CKI

40

41

42

TABLE 11-10: TIMER0 CLOCK REQUIREMENT

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage VDD range is described in

AC CHARACTERISTICS

Section 11.1 “DC Characteristics: MCV14A (Industrial)”

Param

Sym

No.

Characteristic

No Prescaler

Min

Typ⁽¹⁾Max Units

Conditions

40

41

42

Tt0H T0CKI High Pulse

0.5 TCY + 20*

10*

—

ns

Width

With Prescaler

No Prescaler

With Prescaler

Tt0L T0CKI Low Pulse

Width

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40* N

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

DS41338B-page 72

Preliminary

MCV14A

TABLE 11-11: FLASH DATA MEMORY WRITE/ERASE TIME

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage VDD range is described in

AC CHARACTERISTICS

Section 11.1 “DC Characteristics: MCV14A (Industrial)”

Param

Sym

No.

Characteristic

Flash Data Memory

Min Typ⁽¹⁾Max Units

Conditions

43

44

TDW

2

3.5

5

ms

Write Cycle Time

TDE

Flash Data Memory

Erase Cycle Time

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Preliminary

DS41338B-page 73

MCV14A

NOTES:

DS41338B-page 74

Preliminary

MCV14A

12.0 PACKAGING INFORMATION

12.1 Package Marking Information

14-Lead PDIP (300 mil)

Example

XXXXXXXXXXXXXX

MCV14A

-I/PG

0215

e

3

YYWWNNN

0410017

Example

14-Lead SOIC (3.90 mm)

MCV14A-E

/SLG0125

XXXXXXXXXXX

YYWWNNN

0431017

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*

Standard MCV device marking consists of Microchip part number, year code, week code, and traceability

code. For MCV device marking beyond this, certain price adders apply. Please check with your Microchip

Sales Office. For QTP devices, any special marking adders are included in QTP price.

Preliminary

DS41338B-page 75

MCV14A

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

c

A1

b1

b

e

eB

Units

Dimension Limits

INCHES

NOM

14

.100 BSC

–

MIN

MAX

Number of Pins

Pitch

N

e

A

Top to Seating Plane

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

Tip to Seating Plane

Lead Thickness

Upper Lead Width

A2

A1

E

E1

D

L

c

b1

b

eB

.115

.015

.290

.240

.735

.115

.008

.045

.014

–

.130

–

.310

.250

.750

.130

.010

.060

.018

–

.325

.280

.775

.150

.015

.070

.022

.430

Lower Lead Width

Overall Row Spacing §

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-005B

DS41338B-page 76

Preliminary

MCV14A

14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

h

b

α

h

c

φ

A2

A

L

A1

β

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

14

1.27 BSC

Overall Height

Molded Package Thickness

Standoff §

A

–

1.25

0.10

–

1.75

–

0.25

A2

A1

E

Overall Width

6.00 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

3.90 BSC

8.65 BSC

0.25

0.40

–

0.50

1.27

L

Footprint

Foot Angle

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

L1

φ

c

b

α

1.04 REF

0°

0.17

0.31

5°

–

8°

0.25

0.51

15°

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-065B

Preliminary

DS41338B-page 77

MCV14A

APPENDIX A: REVISION HISTORY

Revision A (November 2007)

Original release of this document.

Revision B (June 2009)

Revised Table 7-3: Reset Conditions for Registers;

11.1 DC Characteristics; Table 11-2: Comparator Spec-

ifications; Table 11-4: A/D Converter Characteristics;

Table 11-11: Flash Data Memory Write/Erase Time.

DS41338B-page 78

Preliminary

MCV14A

INDEX

A

P

A/D

POR

Specifications.............................................................. 66

ALU ....................................................................................... 7

Device Reset Timer (DRT) ................................... 35, 45

PD............................................................................... 47

Power-on Reset (POR)............................................... 35

TO............................................................................... 47

B

Block Diagram

PORTB ............................................................................... 23

PORTC ............................................................................... 23

Power-down Mode.............................................................. 47

Prescaler ............................................................................ 32

Program Counter................................................................ 17

Comparator for the MCV14A ...................................... 55

On-Chip Reset Circuit................................................. 43

Timer0......................................................................... 29

TMR0/WDT Prescaler................................................. 33

Watchdog Timer.......................................................... 46

Q

C

Q cycles.............................................................................. 10

Carry ..................................................................................... 7

Clocking Scheme ................................................................ 10

Code Protection ............................................................ 35, 48

CONFIG1 Register.............................................................. 36

Configuration Bits................................................................ 35

R

RC Oscillator....................................................................... 38

Read-Modify-Write.............................................................. 27

Register File Map

MCV14A ..................................................................... 12

Registers

D

Digit Carry............................................................................. 7

CONFIG1 (Configuration Word Register 1)................ 36

Special Function................................................... 12, 13

Reset .................................................................................. 35

E

Errata .................................................................................... 3

S

F

Sleep ............................................................................ 35, 47

Special Features of the CPU .............................................. 35

Special Function Registers........................................... 12, 13

Stack................................................................................... 17

STATUS Register ............................................................... 49

Status Register ............................................................... 7, 14

Flash Data Memory

Code Protection .......................................................... 22

FSR..................................................................................... 18

Fuses. See Configuration Bits

I

T

I/O Interfacing ..................................................................... 25

I/O Ports.............................................................................. 23

I/O Programming Considerations........................................ 27

ID Locations.................................................................. 35, 48

INDF.................................................................................... 18

Indirect Data Addressing..................................................... 18

Instruction Cycle ................................................................. 10

Instruction Flow/Pipelining .................................................. 10

Timer0

Timer0 ........................................................................ 29

Timer0 (TMR0) Module .............................................. 29

TMR0 with External Clock .......................................... 31

Timing Diagrams and Specifications .................................. 68

Timing Parameter Symbology and Load Conditions .......... 67

TRIS Register ..................................................................... 23

L

W

Loading of PC ..................................................................... 17

Wake-up from Sleep........................................................... 47

Watchdog Timer (WDT)................................................ 35, 45

Period ......................................................................... 45

Programming Considerations..................................... 45

WWW, On-Line Support ....................................................... 3

M

Memory Map

MCV14A...................................................................... 11

Memory Organization.......................................................... 11

Flash Data Memory..................................................... 19

Program Memory (MCV14A) ...................................... 11

Z

Zero bit ................................................................................. 7

O

Option Register ................................................................... 15

OSC selection..................................................................... 35

OSCCAL Register............................................................... 16

Oscillator Configurations..................................................... 37

Oscillator Types

HS............................................................................... 37

LP................................................................................ 37

RC............................................................................... 37

XT ............................................................................... 37

Preliminary

DS41338B-page 79

MCV14A

NOTES:

DS41338B-page 80

Preliminary

MCV14A

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

MCV14A-I/SN

package

MCV14A-I/P = Industrial Temp., PDIP package

=

Industrial Temp., SOIC

b)

Device:

MCV14A

MCV14AT⁽¹⁾

Temperature

Range:

I

=

-40°C to +85°C (Industrial)

Package:

Pattern:

P

=

Plastic (PDIP)

SL

=

14L Small Outline, 3.90 mm (SOIC)

Special Requirements

Note 1:

T

= in tape and reel SOIC package only

Preliminary

DS41338B-page 81

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

03/26/09

DS41338B-page 82

Preliminary


型号：	MCV14ATI/SL
厂家：	MICROCHIP
描述：	8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14, 3.90 MM, PLASTIC, SOIC-4 时钟光电二极管外围集成电路
文件：	总84页 (文件大小：1007K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCV14ATI/SL [MICROCHIP]

相关型号：

MCV18E-I/P

MCV18E-I/SO

MCV18ET-I/SO

MCV7805

MCVR1,5/2-ST-3,5RD

MCVR1,5/2-ST-3,5RDBD:5A-5

MCVR1,5/3-ST-3,811CNBD2:X61

MCVR1,5/5-ST-3,81BD:26-22

MCVR1,5/5-ST-3,81CN5BD:26-30

MCVR1,5/6-ST-3,81BD:23-18SO

MCVR1,5/7-ST-3,5CN5BD:14-8

MCVR1,5/7-ST-3,5SVTBD:24-30