MIC4102YM [MICROCHIP]
3A HALF BRDG BASED MOSFET DRIVER, PDSO8;
| 型号： | MIC4102YM |
| 厂家： | 
MICROCHIP |
| 描述： | 3A HALF BRDG BASED MOSFET DRIVER, PDSO8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总28页 (文件大小：989K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MIC4102
100V Half-Bridge MOSFET Driver
with Anti-Shoot-Through Protection
Features
General Description
• Drives High- and Low-Side N-Channel MOSFETs
with Single Input
The MIC4102 is a high frequency, 100V half-bridge
MOSFET driver IC featuring internal anti-shoot-through
protection. The low-side and high-side gate drivers are
controlled by a single input signal to the PWM pin. The
MIC4102 implements adaptive anti-shoot-through
circuitry to optimize the switching transitions for
maximum efficiency. The single input control also
reduces system complexity and greatly simplifies the
overall design.
• Adaptive Anti-Shoot-Through Protection
• Low-Side Drive Disable Pin
• Bootstrap Supply Voltage to 118V DC
• Supply Voltage up to 16V
• TTL Input Thresholds
• On-Chip Bootstrap Diode
• Fast 30 ns Propagation Times
The MIC4102 also features a low-side drive disable
pin. This gives the MIC4102 the capability to operate in
a non-synchronous buck mode. This feature allows the
MIC4102 to start up into applications where a bias
voltage may already be present without pulling the
output voltage down.
• Drives 1000 pF Load with 10 ns Rise and Fall
Times
• Low Power Consumption
• Supply Undervoltage Protection
• 2.5Ω Pull-Up, 1.5Ω Pull-Down Output Resistance
• Space Saving SOIC-8L Package
Undervoltage protection on both the low-side and
high-side supplies forces the outputs low. An on-chip
bootstrap diode eliminates the discrete diode required
with other driver ICs.
• –40°C to +125°C Junction Temperature Range
Applications
The MIC4102 is available in the SOIC-8L package with
a junction operating range from –40°C to +125°C.
• High Voltage Buck Converters
• Networking/Telecom Power Supplies
• Automotive Power Supplies
• Current-Fed Push-Pull Power Topologies
• Ultrasonic Drivers
• Avionic Power Supplies
Typical Application Schematic
MIC4102
SOIC-8L
9V TO 16V BIAS
100V SUPPLY
VDD
HB
MIC4102
HI
HO
HS
PWM
CONTROLLER
VOUT
LS
LO
GND
2016 Microchip Technology Inc.
DS20005575A-page 1
MIC4102
Functional Block Diagram
MIC4102
HV
HB
2
HO
3
DRIVER
LEVEL
SHIFT
UVLO
HS
4
PWM
5
LEVEL
SHIFT
VDD
1
LO
8
UVLO
DRIVER
LS
6
VSS
7
DS20005575A-page 2
2016 Microchip Technology Inc.
MIC4102
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage (VDD, VHB – VHS) .............................................................................................................. –0.3V to +18V
Input Voltages (VPWM, VLS)...............................................................................................................–0.3V to VDD + 0.3V
Voltage on LO (VLO)..........................................................................................................................–0.3V to VDD + 0.3V
Voltage on HO (VHO).................................................................................................................VHS – 0.3V to VHB + 0.3V
Voltage on HS (Continuous).........................................................................................................................–1V to +110V
Voltage on HB .........................................................................................................................................................+118V
Average Current in VDD to HB Diode....................................................................................................................100 mA
ESD Rating .............................................................................................................................................................Note 1
Operating Ratings ‡
Supply Voltage (VDD) .................................................................................................................................... +9V to +16V
Voltage on HS ............................................................................................................................................. –1V to +100V
Voltage on HS (Repetitive Transient).......................................................................................................... –5V to +105V
HS Slew Rate........................................................................................................................................................50 V/ns
Voltage on HB .............................................................................................................................. VHS + 8V to VHS + 16V
and............................................................................................................................................. VDD – 1V to VDD + 100V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
‡ Notice: The device is not guaranteed to function outside its operating ratings.
Note 1: Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ in series
with 100 pF.
2016 Microchip Technology Inc.
DS20005575A-page 3
MIC4102
TABLE 1-1:
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless noted.
Bold values are valid for –40°C ≤ TJ ≤ +125°C. (Note 1).
Parameters
Supply Current
Sym.
Min.
Typ.
Max.
Units
Conditions
—
—
—
—
—
—
—
—
—
—
150
—
450
600
3.5
4.0
150
200
2.5
3
VDD Quiescent Current
VDD Operating Current
IDD
µA
mA
µA
PWM = 0V
f = 500 kHz
3
IDDO
—
25
—
Total HB Quiescent Current
Total HB Operating Current
IHB
PWM = 0V
1.5
—
IHBO
mA
µA
f = 500 kHz
0.05
—
1
HB to VSS Quiescent Current
IHBS
V
HS = VHB = 110V
30
Input Pins (TTL)
Low Level Input Voltage Threshold VIL
High Level Input Voltage Threshold VIH
0.8
—
1.5
1.5
200
—
2.2
500
V
V
—
—
—
Input Pull-Down Resistance
RI
100
kΩ
Undervoltage Protection
V
DD Rising Threshold
VDDR
VDDH
VHBR
VHBH
6.5
—
7.3
0.5
7.0
0.4
8.0
—
V
V
V
V
—
—
—
—
VDD Threshold Hysteresis
HB Rising Threshold
HB Threshold Hysteresis
Bootstrap Diode
6.0
—
8.0
—
—
—
—
—
—
—
0.4
—
0.55
0.70
0.8
Low-Current Forward Voltage
High-Current Forward Voltage
VDL
VDH
RD
V
V
Ω
IVDD-HB = 100 µA
0.7
—
IVDD-HB = 100 mA
IVDD-HB = 100 mA
1.0
1.0
—
1.5
Dynamic Resistance
LO Gate Driver
2.0
—
—
—
—
—
—
0.18
—
0.3
0.4
0.3
0.45
—
Low Level Output Voltage
VOLL
V
V
ILO = 160 mA
0.25
—
ILO = –100 mA,
VOHL = VDD – VLO
High Level Output Voltage
VOHL
Peak Sink Current
IOHL
IOLL
3
A
A
VLO = 0V
Peak Source Current
2
—
VLO = 12V
Note 1: Specification for packaged product only.
2: All voltages relative to Pin 7, VSS, unless otherwise specified.
3: Guaranteed by design. Not production tested.
DS20005575A-page 4
2016 Microchip Technology Inc.
MIC4102
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless noted.
Bold values are valid for –40°C ≤ TJ ≤ +125°C. (Note 1).
Parameters
HO Gate Driver
Sym.
Min.
Typ.
Max.
Units
Conditions
—
—
—
—
—
—
0.22
—
0.3
0.4
0.3
0.45
—
Low Level Output Voltage
High Level Output Voltage
VOLH
V
V
IHO = 160 mA
HO = –100 mA,
0.25
—
I
VOHH
VOHH = VHB – VHO
Peak Sink Current
IOHH
IOLH
3
A
A
VHO = 0V
Peak Source Current
2
—
VHO = 12V
Switching Specifications (Anti-Shoot-Through Circuitry)
—
—
30
—
45
Delay between PWM going high to
LO going low
tLOOFF
VLOOFF
tHOON
ns
V
—
—
—
60
Voltage threshold for LO MOSFET
to be considered OFF
—
1.7
—
—
—
—
—
30
—
45
—
50
60
65
70
Delay between LO OFF to HO
going High
ns
Delay between PWM going Low to
HO going low
tHOOFF
VSWth
tLOON
ns
V
—
—
—
Switch Node Voltage Threshold
when HO turns off
1
2.5
4
—
—
—
—
30
—
36
—
60
70
45
70
Delay between HO MOSFET being
considered off to LO turning ON
ns
Delay between LS going low and
LO turning OFF
tLSOFF
ns
ns
CL = 1000 pF
—
Forced LO ON, if VLOTH is not
detected
tSWTO
120
250
450
Switching Specifications
Either Output Rise Time (3V to 9V) tR
Either Output Fall Time (3V to 9V) tF
—
—
—
—
—
—
10
6
—
—
ns
ns
CL = 1000 pF
CL = 1000 pF
0.33
—
0.6
0.8
0.3
0.4
Either Output Rise Time (3V to 9V) tR
µs
CL = 0.1 µF
0.2
—
Either Output Fall Time (3V to 9V)
tF
µs
ns
CL = 0.1 µF
Minimum Input Pulse Width that
changes the output with LS = 5V
tPW
—
—
40
15
60
CL = 0, Note 3
Minimum Output Pulse Width on
HO with min pulse width on PWM
with LS = 5V
tPW
—
ns
CL = 0, Note 3
Note 1: Specification for packaged product only.
2: All voltages relative to Pin 7, VSS, unless otherwise specified.
3: Guaranteed by design. Not production tested.
2016 Microchip Technology Inc.
DS20005575A-page 5
MIC4102
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless noted.
Bold values are valid for –40°C ≤ TJ ≤ +125°C. (Note 1).
Parameters
Sym.
tPW
Min.
Typ.
Max.
20
Units
Conditions
Minimum Input Pulse Width that
changes the output with LS = 0V
—
13
ns
CL = 0, Note 3
Minimum Output Pulse Width on
HO with min pulse width on PWM
with LS = 0V
—
—
—
20
10
—
—
—
ns
CL = 0, Note 3
—
Bootstrap Diode Turn-On or
Turn-Off Time
tBS
Note 1: Specification for packaged product only.
2: All voltages relative to Pin 7, VSS, unless otherwise specified.
3: Guaranteed by design. Not production tested.
DS20005575A-page 6
2016 Microchip Technology Inc.
MIC4102
TEMPERATURE SPECIFICATIONS
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Max. Junction Temperature Range
Storage Temperature Range
TJ
TS
TJ
–55
–60
–40
—
—
—
+150
+150
+125
°C
°C
°C
Note 1
—
—
Operating Junction Temperature
Range
Package Thermal Resistances
Thermal Resistance, SOIC-8L
JA
—
140
—
°C/W
—
Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.
2016 Microchip Technology Inc.
DS20005575A-page 7
MIC4102
2.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
FIGURE 2-1:
Supply Voltage.
Quiescent Current vs.
Quiescent Current vs.
Operating Current vs.
FIGURE 2-4:
Voltage vs. LS Level.
Supply Current vs. Supply
FIGURE 2-2:
Temperature.
FIGURE 2-5:
Temperature.
Operating Current vs.
FIGURE 2-3:
FIGURE 2-6:
Supply Current vs.
Supply Voltage.
Frequency.
DS20005575A-page 8
2016 Microchip Technology Inc.
MIC4102
FIGURE 2-7:
Supply Current vs.
FIGURE 2-10:
Low Level Output of
Frequency for Pin L and H.
Low-Side Driver vs. Temperature.
FIGURE 2-8:
High Level Output Voltage
FIGURE 2-11:
UVLO Thresholds vs.
vs. Temperature.
Temperature.
FIGURE 2-9:
Low Level Output of
FIGURE 2-12:
UVLO Hysteresis vs.
Low-Side Driver vs. Temperature.
Temperature.
2016 Microchip Technology Inc.
DS20005575A-page 9
MIC4102
FIGURE 2-13:
Bootstrap Diode I-V
Characteristics.
FIGURE 2-14:
Bootstrap Diode Reverse
Current.
DS20005575A-page 10
2016 Microchip Technology Inc.
MIC4102
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Package Type
MIC4102
SOIC-8L (M)
(Top View)
VDD
HB
1
2
3
4
8
7
6
5
LO
VSS
LS
HO
HS
PWM
TABLE 3-1:
Pin Number
PIN FUNCTION TABLE
Pin Name
Description
1
2
VDD
HB
Positive supply to lower gate drivers. Decouple this pin to VSS (Pin 7). Bootstrap diode
connected to HB (Pin 2).
High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive
side of bootstrap capacitor to this pin. Bootstrap diode is on-chip.
3
4
HO
HS
High-Side Output. Connect to gate of high-side power MOSFET.
High-Side Source connection. Connect to source of high-side power MOSFET.
Connect negative side of bootstrap capacitor to this pin.
5
6
PWM
LS
Control Input. PWM high signal makes high-side HO output high and low-side LO
output low. PWM low signal makes high-side HO output low and low-side LO output
high.
Low-Side Disable. When pulled low, this control signal immediately terminates the
low-side LO output drive. The low-side LO output drive will remain low until this signal
is removed. HS drive is not affected by the LS signal. The logic table is below (see
Table 3-2).
7
8
VSS
LO
Chip negative supply. Generally, this will be grounded.
Low-Side Output. Connect to gate of low-side power MOSFET.
TABLE 3-2:
LS PIN LOGIC TABLE
PWM
LS
LO
HO
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
2016 Microchip Technology Inc.
DS20005575A-page 11
MIC4102
4.0
TIMING DIAGRAM
tHOOFF
45ns
70ns
tHOON
30ns
60ns
6
HO
LO
4
tLOON
30ns
70ns
2
8
3 VLOOFF <1.7V
10
Switchnode
(HS Pin)
7 VSWth < (VDD –2.5V)
5
1
PWM
tLOOFF
tLSOFF
36ns
70ns
30ns
60ns
9
LS
FIGURE 4-1:
MIC4102 Timing Diagram.
TABLE 4-1:
Time Point
1-2
TIME POINTS AND ACTIONS FOR Figure 4-1
Action
PWM signal goes high. This initiates the LO signal to go low. The delay between PWM high to
(VLO – 10%) is typically 30 ns (tLOOFF).
2-4
5-7
LO goes low. When LO reaches 1.7V (VLOOFF) the low-side MOSFET is deemed to be off. The
high-side output HO then goes high. The delay between 3 and 4 is typically 30 ns (THOON); this
allows for large turn off delay times of MOSFETs.
PWM goes low; HO goes low, typically within 45 ns, tHOOFF. The switch node (HS pin) is then
monitored; when the switch node is VDD – 2.5V (VSWTH) the high-side MOSFET is deemed to be
off and the LO output goes high within typically 30 ns (tLOON). This is controlled by a one shot
and remains high until PWM goes high. This is because it is possible to have the SW node
oscillate, and could easily bounce through 10V level. If the LO high transition has not happened
within 250 ns, it is forced to happen, unless the LS input is low.
8-10
If at any time after 7 has occurred and LS pin goes low, the LO output will turn off within 36 ns
(VLSOFF). HO will remain off. The LS pin overrides all shoot-through control logic. If LS is low at
the start of the next cycle when PWM signal goes high then HO shall switch transition 1-4 as
normal. (i.e. PWM signal equals HO output, LO = 0V).
DS20005575A-page 12
2016 Microchip Technology Inc.
MIC4102
5.0
FUNCTIONAL DESCRIPTION
VDD
The MIC4102 is
a high voltage, non-inverting,
synchronous MOSFET driver that uses a single PWM
input signal to alternately drive both high-side and
low-side N-Channel MOSFETs. The Functional Block
Diagram of the MIC4102 is shown on page two.
DRIVE
SIGNAL
EXTERNAL
FET
LO
The MIC4102 input is TTL-compatible. The high-side
output buffer includes a high speed level-shifting circuit
that is referenced to the HS pin. An internal diode is
used as part of a bootstrap circuit to provide the drive
voltage for the high-side output.
LS
VSS
5.1
Startup and UVLO
FIGURE 5-1:
Diagram.
Low-Side Driver Block
The UVLO circuit forces both driver outputs low until
the supply voltage exceeds the UVLO threshold. The
low-side UVLO circuit monitors the voltage between
the VDD and VSS pins. The high-side UVLO circuit
monitors the voltage between the HB and HS pins.
Hysteresis in the UVLO circuit prevents noise and finite
circuit impedance from causing chatter during turn-on.
5.4
High-Side Driver and Bootstrap
Circuit
A block diagram of the high-side driver and bootstrap
circuit is shown in Figure 5-2. This driver is designed to
drive a floating N-channel MOSFET, whose source
terminal is referenced to the HS pin.
The VDD pin voltage is supplied to the HS pin through
the internal bootstrap diode. The HB pin voltage will
always be a diode drop less than VDD
.
5.2
Input Stage
VDD
The MIC4102 utilizes a TTL-compatible input stage.
The PWM input pin is referenced to the VSS pin. The
voltage state of the input signal does not change the
quiescent current draw of the driver. The threshold
level is independent of the VDD supply voltage and
there is no dependence between IVDD and the input
signal amplitude. This feature makes the MIC4102 an
excellent level translator that will drive high threshold
MOSFETs from a low voltage PWM IC.
HB
EXTERNAL
FET
CB
HO
5.3
Low-Side Driver
HS
A block diagram of the low-side driver is shown in
Figure 5-1. The low-side driver is designed to drive a
ground (VSS pin) referenced N-channel MOSFET. Low
driver impedances allow the external MOSFET to be
turned on and off quickly. The rail-to-rail drive capability
of the output ensures a low RDS(ON) from the external
MOSFET.
FIGURE 5-2:
Diagram.
High-Side Driver Block
A low-power, high-speed, level-shifting circuit isolates
the low-side (VSS pin) referenced circuitry from the
high-side (HS pin) referenced driver. Power to the
high-side driver and UVLO circuit is supplied by the
bootstrap circuit while the voltage level of the HS pin is
shifted high.
A low level applied to PWM pin will cause the HO
output to go low and the LO output to go high. The
upper driver FET turns on and VDD is applied to the
gate of the external MOSFET. A high level on the PWM
pin forces the LO output low by turning off the upper
driver and turning on the lower driver which ground the
gate of the external MOSFET.
The bootstrap circuit consists of an internal diode and
external capacitor, CB. In a typical application, such as
the synchronous buck converter shown in Figure 5-3,
the HS pin is at ground potential while the low-side
MOSFET is on. The internal diode allows capacitor CB
to charge up to VDD – VD during this time (where VD is
the forward voltage drop of the internal diode). After the
low-side MOSFET is turned off and the HO pin turns
on, the voltage across capacitor CB is applied to the
Pulling the LS pin low disables the LO pin.
2016 Microchip Technology Inc.
DS20005575A-page 13
MIC4102
gate of the upper external MOSFET. As the upper
MOSFET turns on, voltage on the HS pin rises with the
source of the high-side MOSFET until it reaches VIN.
As the HS and HB pin rise, the internal diode is
reverse-biased, preventing capacitor CB from
discharging.
VDD
CB
VIN
VDD
HB
Q1
Q2
CVDD
LOUT
HO
LEVEL
SHIFT
VOUT
COUT
HS
PWM
Q
FF
_
Q
LO
VSS
FIGURE 5-3:
High-Side Driver and
Bootstrap Circuit.
DS20005575A-page 14
2016 Microchip Technology Inc.
MIC4102
by computing the average reverse current due to
reverse recovery charge multiplied by the reverse
voltage across the diode. The average reverse current
and power dissipation due to reverse recovery can be
estimated by:
6.0
6.1
APPLICATION INFORMATION
Power Dissipation Considerations
Power dissipation in the driver can be separated into
three areas:
EQUATION 6-3:
• Internal diode dissipation in the bootstrap circuit
• Internal driver dissipation
IRRAVE = 2 IRRM trr fS
• Quiescent current dissipation used to supply the
internal logic and control functions.
Where:
IRRM
trr
Peak Reverse Recovery Current
Reverse Recovery Time
6.2
Bootstrap Circuit Power
Dissipation
Power dissipation of the internal bootstrap diode
primarily comes from the average charging current of
the CB capacitor times the forward voltage drop of the
diode. Secondary sources of diode power dissipation
are the reverse leakage current and reverse recovery
effects of the diode.
EQUATION 6-4:
PdiodeRR = IRRAVE VREV
The average current drawn by repeated charging of the
high-side MOSFET is calculated by:
The total diode power dissipation is:
EQUATION 6-5:
EQUATION 6-1:
IFAVE = Qgate fS
Pdiodetotal = Pdiodefwd + PdiodeRR
Where:
Qgate
fS
Total Gate Charge at VHB
An optional external bootstrap diode may be used
instead of the internal diode (Figure 6-1). An external
diode may be useful if high gate charge MOSFETs are
being driven and the power dissipation of the internal
diode is contributing to excessive die temperatures.
The voltage drop of the external diode must be less
than the internal diode for this option to work. The
reverse voltage across the diode will be equal to the
input voltage minus the VDD supply voltage. A 100V
Schottky diode will work for most 72V input telecom
applications. The equations above can be used to
calculate power dissipation in the external diode.
However, if the external diode has significant reverse
leakage current, the power dissipated in that diode due
to reverse leakage can be calculated as:
Gate Drive Switching Frequency
The average power dissipated by the forward voltage
drop of the diode equals:
EQUATION 6-2:
Pdiodefwd = IFAVE VF
Where:
VF
Diode Forward Voltage Drop
The value of VF should be taken at the peak current
through the diode. However, this current is difficult to
calculate because of differences in source
impedances. The peak current can either be measured
or the value of VF at the average current can be used
and will yield a good approximation of diode power
dissipation.
EQUATION 6-6:
PdiodeREV = IR VREV 1 – D
Where:
The reverse leakage current of the internal bootstrap
diode is typically 11 µA at a reverse voltage of 100V
and 125°C. Power dissipation due to reverse leakage
is typically much less than 1 mW and can be ignored.
IR
VREV
D
Reverse Current Flow at VREV & TJ
Diode Reverse Voltage
Duty Cycle = tON/fS
Reverse recovery time is the time required for the
injected minority carriers to be swept away from the
depletion region during turn-off of the diode. Power
dissipation due to reverse recovery can be calculated
fS
Switching Freq. of Power Supply
2016 Microchip Technology Inc.
DS20005575A-page 15
MIC4102
The on-time is the time the high-side switch is
conducting. In most power supply topologies, the diode
is reverse-biased during the switching cycle off-time.
MIC4102. RG is the series resistor (if any) between the
driver IC and the MOSFET. RG_FET is the gate
resistance of the MOSFET. RG_FET is usually listed in
the power MOSFET’s specifications. The ESR of
capacitor CB and the resistance of the connecting etch
can be ignored because they are much less than RON
EXTERNAL
DIODE
and RG_FET
The effective capacitance of CGD and CGS is difficult to
calculate because they vary non-linearly with ID, VGS
and VDS Fortunately, most power MOSFET
.
CB
VIN
VDD
HB
,
.
specifications include a typical graph of total gate
charge vs. VGS. Figure 6-3 shows a typical gate charge
curve for an arbitrary power MOSFET. This chart
shows that for a gate voltage of 10V, the MOSFET
requires about 23.5 nC of charge. The energy
dissipated by the resistive components of the gate
drive circuit during turn-on is calculated as:
HO
LEVEL
SHIFT
HS
PWM
Q
FF
_
Q
LO
EQUATION 6-7:
VSS
1
2
2
--
E = CISS VGS
Where:
CISS
FIGURE 6-1:
Optional Bootstrap Diode.
Total Gate Capacitance of MOSFET
6.3
Gate Drive Power Dissipation
but
Power dissipation in the output driver stage is mainly
caused by charging and discharging the gate to source
and gate to drain capacitance of the external MOSFET.
Figure 6-2 shows a simplified equivalent circuit of the
MIC4102 driving an external high-side MOSFET.
EQUATION 6-8:
Q = C V
so
VDD
HB
EXTERNAL
FET
EQUATION 6-9:
CGD
RON
1
2
--
E = QG VGS
CB
HO
RG
RG_FET
CGS
ROFF
HS
FIGURE 6-2:
MIC4102 Driving an
External MOSFET.
6.4
Dissipation During the External
MOSFET Turn-On
Energy from capacitor CB is used to charge up the input
capacitance of the MOSFET (CGD and CGS). The
energy delivered to the MOSFET is dissipated in the
three resistive components, RON, RG, and RG_FET. RON
is the on resistance of the upper driver MOSFET in the
FIGURE 6-3:
Typical Gate Charge vs.
V
.
GS
DS20005575A-page 16
2016 Microchip Technology Inc.
MIC4102
The same energy is dissipated by ROFF, RG, and
RG_FET when the driver IC turns the MOSFET off.
EQUATION 6-13:
Pdisssupply = VDD IDD + VHB IHB
EQUATION 6-10:
1
2
--
Edriver
=
QG VGS
6.6
Total Power Dissipation and
Thermal Considerations
Where:
Edriver
Energy Dissipated during Turn-On
or Turn-Off
Total power dissipation in the MIC4102 equals the
power dissipation caused by driving the external
MOSFETs, the supply current, and the internal
bootstrap diode.
and
EQUATION 6-11:
EQUATION 6-14:
1
--
Pdriver
=
QG VGS fS
2
Where:
Pdisstotal = Pdisssupply + Pdissdrive + Pdiodetotal
Pdriver
Power Dissipated during Turn-On
or Turn-Off
QG
Total Gate Charge at VGS
The die temperature may be calculated once the total
power dissipation is known.
VGS
Gate-to-Source Voltage on the
MOSFET
EQUATION 6-15:
fS
Switching Frequency of the Gate
Drive Circuit
TJ = TA + Pdisstotal JA
The power dissipated inside the MIC4102 equals the
ratio of RON and ROFF to the external resistive losses in
RG and RG_FET. The power dissipated in the MIC4102
due to driving the external MOSFET is:
Where:
TJ
TA
Junction Temperature
Maximum Ambient Temperature
Pdisstotal Power Dissipation of the MIC4102
EQUATION 6-12:
θJA
Thermal Resistance from Junction
to Ambient Air
Pdissdrive
RON
= Pdriver ------------------------------------------------
RON + RG + RG_FET
6.7
Anti-Shoot-Through, Propagation
Delay, and Other Timing
Considerations
ROFF
---------------------------------------------------
+ Pdriver
ROFF + RG + RG_FET
The block diagram on page two illustrates how the
MIC4102 drives the power stage of a synchronous
buck converter. It is important that only one of the two
MOSFETs is on at any given time. If both MOSFETs are
simultaneously on, they will short VIN to ground,
causing high current from the VIN supply to “shoot
through” the MOSFETs and into ground. Excessive
shoot-through causes higher power dissipation in the
MOSFETs, voltage spikes, and ringing in the circuit.
The high current and voltage ringing generate
conducted and radiated EMI.
6.5
Supply Current Power Dissipation
Power is dissipated in the MIC4102 even if there is
nothing being driven. The supply current is drawn by
the bias for the internal circuitry, the level shifting
circuitry, and shoot-through current in the output
drivers. The supply current is proportional to operating
frequency and the VDD and VHB voltages. The typical
characteristic graphs show how supply current varies
with switching frequency and supply voltage.
Minimizing shoot-through can be done passively,
actively, or though a combination of both. Passive
shoot-through protection uses delays between the high
and low gate drivers to prevent both MOSFETs from
being on at the same time. These delays can be
adjusted for different applications. Although simple, the
The power dissipated by the MIC4102 due to supply
current is:
2016 Microchip Technology Inc.
DS20005575A-page 17
MIC4102
disadvantage of this approach is the long delays
required to account for process and temperature
variations in the MOSFET and the MOSFET driver.
voltage settle out. An external resistor between the LO
output and the MOSFET may affect the performance of
the LO pin monitoring circuit and is not recommended.
Active shoot-though monitors voltages on the gate
drive outputs and switch node to determine when to
switch the MOSFETs on and off. This active approach
adjusts the delays to account for some of the
variations, but it also has its disadvantages. High
currents and fast switching voltages in the gate drive
and return paths can cause parasitic ringing that may
turn the MOSFETs back on even though the gate driver
output is low. Another disadvantage is that the driver
cannot monitor the gate voltage inside the MOSFET.
Figure 6-4 shows an equivalent circuit, including
parasitics, of the gate driver section. The internal gate
resistance (RG_GATE) and any external damping
resistor (RG) isolate the MOSFET’s gate from the driver
output. There is a delay between when the driver
output goes low and the MOSFET turns off. This
turn-off delay is usually specified in the MOSFET data
sheet. This delay increases when an external damping
resistor is used.
A low on the PWM pin causes the HO pin to go low after
a short delay (tHOOFF). Before the LO pin can go high,
the voltage on the switching node (HS pin) must have
dropped to 2.5V below the VDD voltage. Monitoring the
switch voltage instead of the HO pin voltage eliminates
timing variations and excessive delays due to the high
side MOSFET turn-off. The LO driver turns on after a
short delay (tLOON). Once the LO driver is turned on, it
is latched on until the PWM signal goes high. This
prevents any ringing or oscillations on the switch node
or HS pin from turning off the LO driver. If the PWM pin
goes low and the voltage on the HS pin does not cross
the VSWth threshold, the LO pin will be forced high after
a short delay (tSWTO), ensuring proper operation.
Fast propagation delay between the input and output
drive waveform is desirable. It improves overcurrent
protection by decreasing the response time between
the control signal and the MOSFET gate drive.
Minimizing propagation delay also minimizes phase
shift errors in power supplies with wide bandwidth
control loops.
VDD
HB
VIN
Care must be taken to ensure the input signal pulse
width is greater than the minimum specified pulse
width. An input signal that is less than the minimum
pulse width may result in no output pulse or an output
pulse whose width is significantly less than the input.
RON
CGD
RG_FET
HO
HS
HS FET
RG
CGS
ROFF
The maximum duty cycle (ratio of high-side on-time to
switching period) is determined by the time required for
the CB capacitor to charge during the off-time.
Adequate time must be allowed for the CB capacitor to
charge up before the high-side driver is turned back on.
SWITCHING
NODE
RON
CGD
RG_FET
LO
LS FET
The anti-shoot-through circuit in the MIC4102 prevents
the driver from turning both MOSFETs on at the same
time; however, other factors outside of the
anti-shoot-through circuit’s control can cause
shoot-through. Some of these include ringing on the
gate drive node and capacitive coupling of the
switching node voltage on the gate of the low-side
MOSFET.
CGS
ROFF
VSS
FIGURE 6-4:
Gate Drive Circuit with
Parasitics.
6.8
Decoupling and Bootstrap
Capacitor Selection
The MIC4102 uses a combination of active sensing
and passive delay to ensure that both MOSFETs are
not on at the same time and to minimize shoot-through
current. The timing diagram helps illustrate how the
anti-shoot-through circuitry works. A high level on the
PWM pin causes the LO pin to go low. The MIC4102
monitors the LO pin voltage and prevents the HO pin
from turning on until the voltage on the LO pin reaches
the VLOOFF threshold. After a short delay, the MIC4102
drives the HO pin high. Monitoring the LO voltage
eliminates any excessive delay due to the MOSFET
drivers turn-off time and the short delay accounts for
the MOSFET turn-off delay as well as letting the LO pin
Decoupling capacitors are required for both the
low-side (VDD) and high-side (HB) supply pins. These
capacitors supply the charge necessary to drive the
external MOSFETs as well as minimize the voltage
ripple on these pins. The capacitor from HB to HS
serves double duty by providing decoupling for the
high-side circuitry as well as providing current to the
high-side circuit while the high-side external MOSFET
is on. Ceramic capacitors are recommended because
of their low impedance and small size. Z5U type
ceramic capacitor dielectrics are not recommended
due to the large change in capacitance over
DS20005575A-page 18
2016 Microchip Technology Inc.
MIC4102
temperature and voltage. A minimum value of 0.1 µF is
required for each of the capacitors, regardless of the
MOSFETs being driven. Larger MOSFETs may require
larger capacitance values for proper operation. The
voltage rating of the capacitors depends on the supply
voltage, ambient temperature, and the voltage derating
used for reliability. 25V rated X5R or X7R ceramic
capacitors are recommended for most applications.
The minimum capacitance value should be increased if
low voltage capacitors are used because even good
quality dielectric capacitors, such as X5R, will lose 40%
to 70% of their capacitance value at the rated voltage.
from CVDD through the internal driver, into the MOSFET
gate, and out the source. The return connection back to
the decoupling capacitor is made through the ground
plane. Any inductance or resistance in the ground
return path causes a voltage spike or ringing to appear
on the source of the MOSFET. This voltage works
against the gate voltage and can either slow down or
turn off the MOSFET during the period where it should
be turned on.
Current in the high-side driver is sourced from
capacitor CB, flows into the HB pin, and out the HO pin,
into the gate of the high-side MOSFET. The return path
for the current is from the source of the MOSFET and
back to capacitor CB. The high-side circuit return path
usually does not have a low impedance ground plane,
so the etch connections in this critical path should be
short and wide to minimize parasitic inductance. As
with the low-side circuit, impedance between the
MOSFET source and the decoupling capacitor causes
negative voltage feedback that fights the turn-on of the
MOSFET.
Placement of the decoupling capacitors is critical. The
bypass capacitor for VDD should be placed as close as
possible between the VDD and VSS pins. The bypass
capacitor (CB) for the HB supply pin must be located as
close as possible between the HB and HS pins. The
etch connections must be short, wide, and direct. The
use of a ground plane to minimize connection
impedance is recommended. Refer to the section on
layout and component placement for more information.
The voltage on the bootstrap capacitor drops each time
it delivers charge to turn on the MOSFET. The voltage
drop depends on the gate charge required by the
MOSFET. Most MOSFET specifications specify gate
charge vs. VGS voltage. Based on this information and
a recommended ∆VHB of less than 0.1V, the minimum
value of bootstrap capacitance is calculated as:
It is important to note that capacitor CB must be placed
close to the HB and HS pins. This capacitor not only
provides all the energy for turn-on, but it must also keep
HB pin noise and ripple low for proper operation of the
high-side drive circuitry.
LOW-SIDE DRIVE
TURN-ON
CURRENT PATH
EQUATION 6-16:
VDD
HB
LO
QG
CVDD
-------------
CB
VHB
GND
PLANE
VSS
Where:
QG
∆VHB
GND
PLANE
_
Q
Total Gate Charge at VHB
Voltage Drop at the HB Pin
FF
HO
HS
Q
PWM
CB
LEVEL
SHIFT
LS
The decoupling capacitor for the VDD input may be
calculated in with the same formula; however, the two
capacitors are usually equal in value.
HIGH-SIDE DRIVE
TURN-ON
CURRENT PATH
FIGURE 6-5:
Turn-On Current Paths.
6.9
Grounding, Component
Placement, and Circuit Layout
Figure 6-6 shows the critical current paths when the
driver outputs go low and turn off the external
MOSFETs. Short, low impedance connections are
important during turn-off for the same reasons given in
the turn-on explanation. Current flowing through the
internal diode replenishes charge in the bootstrap
capacitor, CB.
Nanosecond switching speeds and ampere peak
currents in and around the MIC4102 driver require
proper placement and trace routing of all components.
Improper placement may cause degraded noise
immunity, false switching, excessive ringing, or circuit
latch-up.
Figure 6-5 shows the critical current paths when the
driver outputs go high and turn on the external
MOSFETs. It also shows the need for a low impedance
ground plane. The charge needed to turn-on the
MOSFET gates comes from the decoupling capacitors
CVDD and CB. Current in the low-side gate driver flows
2016 Microchip Technology Inc.
DS20005575A-page 19
MIC4102
LOW-SIDE DRIVE TURN-OFF
CURRENT PATH
CVDD
VDD
HB
LO
V
CHARGE CB THROUGH
INTERNAL DIODE WHEN
HS PIN IS LOW
VSS
V
_
Q
FF
V
HO
HS
PWM
Q
CB
LEVEL
SHIFT
LS
HIGH-SIDE DRIVE
TURN-OFF CURRENT PATH
FIGURE 6-6:
Turn-Off Current Paths.
The following circuit guidelines should be adhered to
for optimum circuit performance:
• The VDD and HB bypass capacitors must be
placed close to the supply and ground pins. It is
critical that the etch length between the high side
decoupling capacitor (CB) and the HB and HS
pins be minimized to reduce lead inductance.
• A ground plane should be used to minimize
parasitic inductance and impedance of the return
paths. The MIC4102 is capable of greater than 3A
peak currents. Any impedance between the
MIC4102, the decoupling capacitors, and the
external MOSFET will degrade the performance
of the driver.
• Trace out the high di/dt and dv/dt paths, as shown
in Figure 6-5 and Figure 6-6 to minimize the etch
length and loop area for these connections.
Minimizing these parameters decreases the
parasitic inductance and the radiated EMI
generated by fast rise and fall times.
FIGURE 6-8:
Synchronous Buck Converter Power Stage.
Typical Layout of a
The circuit is configured as a synchronous buck power
stage. The high-side MOSFET drain connects to the
input supply voltage (drain) and the source connects to
the switching node. The low-side MOSFET drain
connects to the switching node and its source is
connected to ground. The buck converter output
inductor (not shown) would connect to the switching
node. The high-side drive trace, HO, is routed on top
of its return trace, HS, to minimize loop area and
parasitic inductance. The low-side drive trace, LO, is
routed over the ground plane and minimizes the
impedance of that current path. The decoupling
capacitors, CB and CVDD, are placed to minimize etch
length between the capacitors and their respective
pins. This close placement is necessary to efficiently
charge capacitor CB when the HS node is low. All
traces are 0.025” wide or greater to reduce impedance.
CIN is used to decouple the high current path through
the MOSFETs.
A typical layout of a synchronous buck converter power
stage using the MIC4102 (Figure 6-7) is shown in
Figure 6-8.
VDD
CB
VIN
HB
VDD
HIGH-SIDE
FET
CVDD
HO
LEVEL
SHIFT
HS
(SWITCH NODE)
HS
PWM
Q
CIN
LOW-SIDE
FET
FF
_
Q
LO
VSS
FIGURE 6-7:
Typical Converter Power
Stage.
DS20005575A-page 20
2016 Microchip Technology Inc.
MIC4102
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
8-lead SOIC*
Example
XXX
XXXXXX
YYWW
MIC
4102YM
1613
Legend: XX...X Product code or customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
e
3
)
●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle
mark).
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
Underbar (_) symbol may not be to scale.
2016 Microchip Technology Inc.
DS20005575A-page 21
MIC4102
8-Lead SOIC Package Outline and Recommended Land Pattern
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005575A-page 22
2016 Microchip Technology Inc.
MIC4102
APPENDIX A: REVISION HISTORY
Revision A (June 2016)
• Converted Micrel document MIC4102 to Micro-
chip data sheet DS20005575A.
• Minor text changes throughout.
2016 Microchip Technology Inc.
DS20005575A-page 23
MIC4102
NOTES:
DS20005575A-page 24
2016 Microchip Technology Inc.
MIC4102
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
PART NO.
Device
X
X
XX
a)
MIC4102YM:
100V Half-Bridge MOS-
FET Driver with Anti-
Shoot-ThroughProtection,
–40°C to +125°C Temp.
Range,SOIC-8LPackage,
95/Tube
Temperature Package
Media Type
Device:
MIC4102:
100V Half-Bridge MOSFET Driver with
Anti-Shoot-Through Protection
b)
MIC4102YM-TR:
100V Half-Bridge MOS-
FET Driver with Anti-
Shoot-Through Protec-
tion, –40°C to +125°C
Temp. Range, SOIC-8L
Package, 2,500/Reel
Temperature:
Package:
Y
=
=
–40°C to +125°C
M
SOIC-8L
Media Type:
(blank) = 95/Tube
TR 2,500/Reel
=
2016 Microchip Technology Inc.
DS20005575A-page 25
MIC4102
NOTES:
DS20005575A-page 26
2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
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ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
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SQTP is a service mark of Microchip Technology Incorporated
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Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of
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GestIC is a registered trademarks of Microchip Technology
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Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
CERTIFIEDꢀBYꢀDNVꢀ
© 2016, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0717-1
== ISO/TSꢀ16949ꢀ==ꢀ
2016 Microchip Technology Inc.
DS20005575A-page 27
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Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
New York, NY
Tel: 631-435-6000
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
San Jose, CA
Tel: 408-735-9110
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
07/14/15
DS20005575A-page 28
2016 Microchip Technology Inc.
相关型号：
MIC4102_11
100V Half Bridge MOSFET Driver with Anti-Shoot Through Protection PRELIMINARY SPECIFICATIONS
MIC
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