MIC502BN [MICROCHIP]
Brushless DC Motor Controller, 0.025A, CMOS, PDIP8, PLASTIC, DIP-8;
| 型号： | MIC502BN |
| 厂家： | 
MICROCHIP |
| 描述： | Brushless DC Motor Controller, 0.025A, CMOS, PDIP8, PLASTIC, DIP-8 电动机控制 光电二极管 |
| 文件： | 总16页 (文件大小：1163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MIC502
Fan Management IC
General Description
Features
The MIC502 is a thermal and fan management IC that
supports the features for NLX/ATX power supplies and
other control applications.
• Temperature-proportional fan speed control
• Low-cost, efficient PWM fan drive
• 4.5V to 13.2V IC supply range
• Controls any voltage fan
• Overtemperature detection with fault output
• Integrated fan startup timer
• Automatic user-specified sleep mode
• Supports low-cost NTC/PTC thermistors
• 8-pin DIP and SOIC packages
Fan speed is determined by an external temperature
sensor, typically
a
thermistor-resistor divider, and
(optionally) a second signal, such as the NLX “FanC”
signal. The MIC502 produces a low-frequency pulse-width
modulated output for driving an external motor drive
transistor. Low-frequency PWM speed control allows
operation of standard brushless DC fans at low duty-cycle
for reduced acoustic noise and permits the use of a very
small power transistor. The PWM time base is determined
by an external capacitor.
Applications
• NLX and ATX power supplies
• Personal computers
• File servers
An open-collector overtemperature fault output is asserted
if the primary control input is driven above the normal
control range.
• Telecom and networking hardware
• Printers, copiers, and office equipment
• Instrumentation
• Uninterruptible power supplies
• Power amplifiers
The MIC502 features a low-power sleep mode with a user-
determined threshold. Sleep mode completely turns off the
fan and occurs when the system is asleep or off (both
control inputs very low). A complete shutdown or reset can
also be initiated by external circuitry as desired.
The MIC502 is available as 8-pin plastic DIP and SOIC
packages in the –40°C to +85°C industrial temperature
range.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Typical Application
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Revision 3.0
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Micrel, Inc.
MIC502
Ordering Information
Part Number
MIC502YN
MIC502YM
Temperature Range
–40° to +85°C
Package
8-Pin Plastic DIP
8-Pin SOIC
Lead Finish
Pb-Free
–40° to +85°C
Pb-Free
Pin Configuration
8-Pin SOIC (M)
8-Pin DIP (N)
(Top View)
Pin Description
Pin Number
Pin Name
Pin Function
Thermistor 1 (input): Analog input of approximately 30% to 70% of VDD produces active duty cycle
of 0% to 100% at driver output (OUT). Connect to external thermistor network (or other
temperature sensor). Pull low for shutdown.
1
VT1
PWM timing capacitor (external component): Positive terminal for the PWM triangle-wave
generator timing capacitor. The recommended CF is 0.1µF for 30Hz PWM operation.
2
CF
Sleep threshold (input): The voltage on this pin is compared to VT1 and VT2. When VT1 < VSLP
3
4
5
VSLP
GND
VT2
and VT2 < VSLP the MIC502 enters sleep mode until VT1 or VT2 rises above VWAKE. (VWAKE = VSLP
HYST). Grounding VSLP disables the sleep-mode function.
+
V
Ground
Thermistor 2 (input): Analog input of approximately 30% to 70% of VDD produces active duty cycle
of 0% to 100% at driver output (OUT). Connect to motherboard fan control signal or second
temperature sensor.
Overtemperature fault (output): Open-collector output (active-low). Indicates overtemperature
fault condition (VT1 > VOT) when active.
6
/OTF
Driver output: Asymmetrical-drive active-high complimentary PWM output. Typically connect to
base of external NPN motor control transistor.
7
8
OUT
VDD
Power supply (input): IC supply input; may be independent of fan power supply.
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Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD)....................................................+14V
Output Sink Current (IOUT(sink)). ....................................10mA
Output Source Current (IOUT(source))..............................25mA
Input Voltage (any pin)......................... –0.3V to VDD + 0.3V
Junction Temperature (TJ) .......................................+125°C
Lead Temperature (soldering, 5s).............................. 260°C
Storage Temperature (Ts).........................–65°C to +150°C
ESD Rating(3)................................................. ESD Sensitive
Supply Voltage (VDD).................................. +4.0V to +13.2V
Sleep Voltage (VSLP).......................................... GND to VDD
Temperature Range (TA).............................–40°C to +85°C
Power Dissipation at +25°C
SOIC..................................................................800mW
DIP.....................................................................740mW
Derating Factors
SOIC..............................................................8.3mW/°C
Plastic DIP .....................................................7.7mW/°C
Electrical Characteristics(4)
4.5V ≤ VDD ≤ 13.2V(5); TA = 25°C, bold values indicate –40°C≤ TA ≤ +85°C, unless noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VSLP = GND, /OTF, OUT = open,
CF = 0.1µF, VT1 = VT2 = 0.7 VDD
IDD
Supply Current, Operating
1.5
mA
V
T1 = GND, VSLP, /OTF, OUT = open,
IDD(slp)
Supply Current, Sleep
500
µA
CF = 0.1µF
Driver Output
tR
Output Rise Time, Note 6
IOH = 10mA
50
50
µs
µs
tF
Output Fall Time, Note 6
Output Sink Current
IOL = 1mA
0.9
10
10
IOL
VOL = 0.5V
mA
mA
mA
µA
4.5V ≤ VDD ≤ 5.5V, VOH = 2.4V
10.8V ≤ VDD ≤ 13.2V, VOH = 3.2V
VOUT = 0V
IOH
IOS
Output Source Current
Sleep Mode Output Leakage
1
Thermistor and Sleep Inputs
100% PWM Duty Cycle Input
67
73
VPWM(max)
70
%VDD
Voltage
VPWM(span) VPWM(max) – VPWM(min)
37
8
43
14
40
11
%VDD
%VDD
V
VHYST
VIL
Sleep Comparator Hysteresis
0.7
VT1 Shutdown Threshold
VT1 Startup Threshold
1.1
74
VIH
V
VT1 Overtemperature Fault
Threshold
80
VOT
Note 7
77
%VDD
µA
IVT, IVSLP
tRESET
VT1, VT2, VSLP Input Current
Reset Setup Time
-2.5
30
1
Minimum time VT1 < VIL to guarantee reset.
Note 6
µs
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to function outside its operating ratings.
3. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5kΩ in series with 100pF.
4. Specification for packaged product only.
5. Part is functional over this VDD range. However, it is characterized for operation at 4.5V ≤ VDD ≤ 5.5V and 10.8V ≤ VDD ≤ 13.2V ranges. These ranges
correspond to a nominal VDD of 5V and 12V, respectively.
6. Guaranteed by design.
7.
VOT is guaranteed by design to always be higher than VPWM(max).
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Electrical Characteristics(4) (Continued)
4.5V ≤ VDD ≤ 13.2V(5); TA = 25°C, bold values indicate –40°C≤ TA ≤ +85°C, unless noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Oscillator
24
27
15
30
33
90
4.5V ≤ VDD ≤ 5.5V, CF = 0.1µF
10.8V ≤ VDD ≤ 13.2V, CF = 0.1µF
Note 8
27
30
Hz
Hz
Hz
s
f
Oscillator Frequency, Note 8
fMIN, fMAX
tSTARTUP
Oscillator Frequency Range
Startup Interval
64/f
1
Overtemperature Fault Output
VOL
IOH
Active (Low) Output Voltage
Off-State Leakage
IOL = 2mA
0.3
V
V/OTF = VDD
µA
Note:
8. Logic time base and PWM frequency. For other values of CF, f(Hz) = 30Hz × (0.1µF ÷ C), where C is measured in µF.
Timing Diagrams
Figure 1. Typical System Behavior
Note A. Output duty-cycle is initially determined by VT1 because it is greater than VT2.
Note B. PWM duty-cycle follows VT1 as it increases.
Note C. VT1 drops below VT2. VT2 now determines the output duty-cycle.
Note D. The PWM duty-cycle follows VT2 as it increases.
Note E. Both VT1 and VT2 decrease below VSLP, but above VIL. The device enters sleep mode.
Note F. The PWM wakes up because one of the control inputs (VT1 in this case) has risen above VWAKE. The startup timer is triggered, forcing OUT high
for 64 clock periods. (VWAKE = VSLP + VHYST. See the Electrical Characteristics section for details).
Note G. Following the startup interval, the PWM duty-cycle is the higher of VT1 and VT2.
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Timing Diagrams (Continued)
Figure 2. MIC502 Typical Power-Up System Behavior
Note H. At power-on, the startup timer forces OUT on for 64 PWM cycles of the internal timebase (tPWM). This ensures that the fan will start from a dead
stop.
Note I. The PWM duty-cycle follows the higher of VT1 and VT2, in this case, VT1.
Note J. The PWM duty-cycle follows VT1 as it increases.
Note K. PWM duty-cycle is 100% (OUT constantly on) anytime VT1 > VPWM(max)
.
Note L. /OTF is asserted anytime VT1 > VOT. The fan continues to run at 100% duty-cycle.
Note M. /OTF is deasserted when VT1 falls below VOT; duty-cycle once again follows VT1.
Note N. Duty-cycle follows VT1 until VT1 < VT2, at which time VT2 becomes the controlling input signal. Note that VT1 is below VSLP but above VIH; so
normal operation continues. Both VT1 and VT2 must be below VSLP to active sleep mode.
Note O. All functions cease when VT1 < VIL; this occurs regardless of the state of VT2.
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Typical Characteristics
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Typical Characteristics (Continued)
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Typical Characteristics (Continued)
Functional Diagram
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MIC502
Sleep Mode
Functional Description
When VT1 and VT2 fall below VSLP, the system is deemed
capable of operating without fan cooling and the MIC502
enters sleep mode and discontinues fan operation. The
threshold where the MIC502 enters sleep mode is
determined by VSLP. Connecting the VSLP pin to ground
disables sleep mode.
Oscillator
A capacitor connected to CF determines the frequency of
the internal time base which drives the state-machine
logic and determines the PWM frequency. This operating
frequency will be typically 30Hz to 60Hz. (CF = 0.1µF for
30Hz.)
Once in sleep mode, all device functions cease (/OTF
inactive, PWM output off) unless VT1 or VT2 rise above
VWAKE. (VWAKE = VSLP + VHYST). VHYST is a fixed amount of
hysteresis added to the sleep comparator which prevents
erratic operation around the VSLP operating point. The
result is stable and predictable thermostatic action:
whenever possible the fan is shut down to reduce energy
consumption and acoustic noise, but will always be
activated if the system temperature rises.
Pulse-Width Modulation
A
triangle-wave generator and threshold detector
comprise the internal pulse-width modulator (PWM). The
PWM’s output duty-cycle is determined by the higher of
VT1 or VT2. A typical voltage range of 30% to 70% of VDD
applied to the VT1 and VT2 pins corresponds to 0% to
100% duty-cycle. Because at least one of the control
voltage inputs is generally from a thermistor-resistor
divider connected to VDD, the PWM output duty cycle will
not be affected by changes in the supply voltage.
If the device powers-up or exits its reset state, the fan will
not start unless VT1 or VT2 rises above VWAKE
.
Driver Output
System Operation
OUT is a complementary push-pull digital output with
asymmetric drive (approximately 10mA source, 1mA sink,
see “Electrical Characteristics”). It is optimized for directly
driving an NPN transistor switch in the fan’s ground-
return. See “Application Information” for circuit details.
Power Up
•
•
•
•
A complete reset occurs when power is applied.
OUT is off (low) and /OTF is inactive (high/floating).
If VT1 < VIL, the MIC502 remains in shutdown.
Shutdown/Reset
The startup interval begins. OUT will be on (high) for
64 clock cycles (64 × tPWM).
Internal circuitry automatically performs a reset of the
MIC502 when power is applied. The MIC502 may be shut
down at anytime by forcing VT1 below its VIL threshold.
This is typically accomplished by connecting the VT1 pin
to open-drain or open-collector logic and results in an
immediate and asynchronous shutdown of the MIC502.
The OUT and /OTF pins will float while VT1 is below VIL.
•
Following the startup interval, normal operation
begins.
If VT1 then rises above VIH, a device reset occurs. Reset
is equivalent to a power-up condition: the state of /OTF is
cleared, a startup interval is triggered, and normal fan
operation begins.
Startup Interval
Any time the fan is started from the off state (power-on or
coming out of sleep mode or shutdown mode), the PWM
output is automatically forced high for a startup interval of
64 × tPWM. Once the startup interval is complete, PWM
operation will commence and the duty-cycle of the output
will be determined by the higher of VT1 or VT2.
Overtemperature Fault Output
/OTF is an active-low, open-collector logic output. An
over-temperature condition will cause /OTF to be
asserted. An overtemperature condition is determined by
VT1 exceeding the normal operating range of 30% to 70%
of VDD by >7% of VDD. Note that VOT is guaranteed by
design to always be higher than VPWM(max)
.
Figure 3. Power-Up Behavior
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MIC502
Normal Operation
•
Sleep: If VT1 and VT2 fall below VSLP, the device
enters sleep mode. All internal functions cease
Normal operation consists of the PWM operating to
control the speed of the fan according to VT1 and VT2.
Exceptions to this otherwise indefinite behavior can be
caused by any of three conditions: VT1 exceeding VOT, an
overtemperature condition; VT1 being pulled below VIL
initiating a device shutdown and reset; or both VT1 and
VT2 falling below VSLP, activating sleep mode. Each of
these exceptions is treated as follows:
unless VT1 or VT2 rise above VWAKE. (VWAKE = VSLP
+
VHYST). The /OTF output is unconditionally inactive
(high/floating) and the PWM is disabled during sleep
(OUT will float).
Sleep Mode
During normal operation, if VT1 and VT2 fall below VSLP,
the device will go into sleep mode and fan operation will
stop. The MIC502 will exit sleep mode when VT1 or VT2
rise above VSLP by the hysteresis voltage, VHYST.
When this occurs, normal operation will resume. The
resumption of normal operation upon exiting sleep is
indistinguishable from a power-on reset.
Figure 4. Normal System Behavior
•
Overtemperature: If the system temperature rises
typically 7% above the 100% duty-cycle operating
point, /OTF will be activated to indicate an
overtemperature fault. (VT1 > VOT) Overtemperature
detection is essentially independent of other
operations. The PWM continues its normal behavior;
with VT1 > VPWM(max), the output duty-cycle will be
100%. If VT1 falls below VOT, the overtemperature
condition is cleared and /OTF is no longer asserted. It
is assumed that in most systems, the /OTF output will
initiate power supply shutdown.
•
Shutdown/Reset: If VT1 is driven below VIL an
immediate, asynchronous shutdown occurs. While in
shutdown mode, OUT is off (low), and /OTF is
unconditionally inactive (high/floating). If VT1
subsequently rises above VIH, a device reset will
occur. Reset is indistinguishable from a power-up
condition. The state of /OTF is cleared, a startup
interval is triggered, and normal fan operation begins.
Figure 5. Sleep Mode Behavior
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MIC502
assumed that the system will be in sleep mode rather
than operate the fan at a very low duty cycle (<25%).
Operation at very low duty cycle results in relatively little
airflow. Sleep mode should be used to reduce acoustic
noise when the system is cool. For a given minimum
desired fan speed, a corresponding VT1(min) can be
determined via the following observation:
Application Information
The drawing on page 1 illustrates a typical application
circuit for the MIC502. Interfacing the MIC502 with a
system consists of the following steps:
1. Selecting a temperature sensor
2. Interfacing the temperature sensor to the VT1 input
because
3. Selecting a fan-drive transistor and base-drive
current limit resistor
VPWM(max) = 70% of VDD ∝ 100% RPM
and
4. Deciding what to do with the secondary fan-control
input
VPWM(min) = 30% of VDD ∝ 0% RPM
5. Making use of the overtemperature fault output
then
Temperature Sensor Selection
VPWM(span) = 40% of VDD ∝ 100% RPM range.
Temperature sensor T1 is a negative temperature
coefficient (NTC) thermistor. The MIC502 can be
interfaced with either a negative or positive tempco
thermistor; however, a negative temperature coefficient
thermistor typically costs less than its equivalent positive
tempco counterpart. While a variety of thermistors can be
used in this application, the following paragraphs reveal
that those with an R25 rating (resistance at +25°C) of
from about 50kΩ to 100kΩ lend themselves nicely to an
interface network that requires only a modest current
drain. Keeping the thermistor bias current low not only
indicates prudent design; it also prevents self-heating of
the sensor from becoming an additional design
consideration. It is assumed that the thermistor will be
located within the system power supply, which most likely
also houses the speed-controlled fan.
Figure 6 shows the following linear relationship between
the voltage applied to the VT1 input, motor drive duty
cycle, and approximate motor speed.
because
VT1 = 0.7VDD ∝ 100% PWM
then
VT1 = 0.6VDD ∝ 75% PWM
VT1 = 0.5VDD ∝ 50% PWM
VT1 = 0.4VDD ∝ 25% PWM
and
and
Temperature Sensor Interface
In addition to the R25 thermistor rating, sometimes a
datasheet will provide the ratio of R25/R50 (resistance at
+25°C divided by resistance at +50°C) is given.
Sometimes this is given as an R0/R50 ratio. Other
datasheet contents either specify or help the user
determine device resistance at arbitrary temperatures.
The thermistor interface to the MIC502 usually consists of
the thermistor and two resistors.
As shown by the Electrical Characteristics table, the
working voltage for input VT1 is specified as a percentage
of VDD. This conveniently frees the designer from having
to be concerned with interactions resulting from variations
in the supply voltage. By design, the operating range of
VT1 is from about 30% of VDD to about 70% of VDD.
V
PWM(min) = VPWM(min) – VPWM(span)
When VT1 = VPWM(max) ≈ 0.7VDD, a 100% duty-cycle motor-
drive signal is generated. Conversely, when VT1
=
VPWM(min) ≈ 0.3VDD, the motor-drive signal has a 0% duty
cycle. Resistor voltage divider R1 || T1, R2 in the Typical
Application diagram is designed to preset VT1 to a value
of VPWM that corresponds to the slowest desired fan
speed when the resistance of thermistor T1 is at its
highest (cold) value. As temperature rises the resistance
of T1 decreases and VT1 increases because of the
parallel connection of R1 and T1.
Because VT1 = VPWM(min) represents a stopped fan (0%
duty-cycle drive), and because it is foreseen that at least
some cooling will almost always be required, the lowest
voltage applied to the VT1 input will normally be
somewhat higher than 0.3VDD (or >VPWM(min)). It is
Figure 6. Control Voltage vs. Fan Speed
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Design Example
VDD × 33k
100k + 33k
VT
=
The thermistor-resistor interface network is shown in the
Typical Application drawing. The following example
describes the design process: A thermistor datasheet
specifies a thermistor that is a candidate for this design
as having an R25 resistance of 100kΩ. The datasheet
also supports calculation of resistance at arbitrary tem-
peratures, and it was discovered the candidate thermistor
has a resistance of 13.6k at +70°C (R70). Accuracy is
more important at the higher temperature end of the
operating range (+70°C) than the lower end because we
wish the overtemperature fault output (/OTF) to be
reasonably accurate—it may be critical to operating a
power supply crowbar or other shutdown mechanism, for
example. The lower temperature end of the range is less
important because it simply establishes minimum fan
speed, which is when less cooling is required.
Referring to the Typical Application, the following
approach can be used to design the required thermistor
interface network:
VT = 0.248VDD
Recalling the earlier discussion that the desired VT for
+25°C should be about 40% of VDD, the above value of
24.8% is far too low. This would produce a voltage that
would stop the fan (recall from earlier that this occurs
when VT is about 30% of VDD). To choose an appropriate
value for R1, we need to learn what the parallel
combination of RT1 and R1 should be at +25°C:
again
VDD × R2
RT1 || R1+ R2
VT
=
(
)
R2
0.4 =
(
RT1 || R1+ R2
)
0.4(RT1 || R1) + 0.4R2 = R2
0.4(RT1 || R1) = 0.6R2
let
R1 = ∞
and
RT1 = 13.6k (at +70°C)
and
RT1 || R1 = 1.5R2 = 1.5 × 33k = 49.5k
because
VT = 0.7VDD (70% of VDD)
because
R
T1 = 100k
and
let
V
×R2
||R1+ R2
DD
V =
T
R
T1 || R1 = 49.5k ≈ 50k
(
R
)
T1
R2
RT1 + R2
0.7 =
R1 = 100k
(
)
While that solves the low temperature end of the range,
there is a small effect on the other end of the scale. The
new value of VT for +70°C is 0.734, or about 73% of VDD.
This represents only a 3% shift from the design goal of
70% of VDD. In summary, R1 = 100k, and R2 = 33k. The
candidate thermistor used in this design example is the
RL2010-54.1K-138-D1, manufactured by Keystone
Thermometrics.
0.7RT1 + 0.7R2 = R2
0.7RT1 = 0.3R2
and
R2 = 2.33RT1 = 2.33 × 13.6k = 31.7k ≈ 33k
Let’s continue by determining what the temperature-
proportional voltage is at +25°C.
The R25 resistance (100kΩ) of the chosen thermistor is
probably on the high side of the range of potential
thermistor resistances. The result is a moderately high-
impedance network for connecting to the VT1 and/or VT2
input(s). Because these inputs can have up to 1µA of
leakage current, care must be taken if the input network
impedance becomes higher than the example. Leakage
current and resistor accuracy could require consideration
in such designs. Note that the VSLP input has this same
leakage current specification.
let
R1 = ∞
and
R
T1 = 100k (at +25°C)
from
V
×R2
+ R2
DD
V =
T
(
R
)
T1
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Secondary Fan Control Input
Overtemperature Fault Output
The above discussions also apply to the secondary fan-
control input, VT2, pin 5. It is possible that a second
thermistor, mounted at another temperature-critical
location outside the power supply, may be appropriate.
There is also the possibility of accommodating the NLX
“FanC” signal via this input. If a second thermistor is the
desired solution, the VT2 input may be treated exactly like
the VT1 input. The above discussions then apply directly.
If, however, the NLX FanC signal is to be incorporated
into the design then the operating voltage (VDD = 5V vs.
VDD = 12V) becomes a concern. The FanC signal is
derived from a 12V supply and is specified to swing at
least to 10.5V. A minimum implementation of the FanC
signal would provide the capability of asserting full-speed
operation of the fan; this is the case when 10.5V ≤ FanC
≤ 12V. This FanC signal can be applied directly to the VT2
input of the MIC502, but only when its VDD is 12V. If this
signal is required when the MIC502 VDD = 5V a resistor
divider is necessary to reduce this input voltage so it
does not exceed the MIC502 VDD voltage. A good
number is 4V (80%VDD).
The /OTF output, pin 6, is an open-collector NPN output.
It is compatible with CMOS and TTL logic and is intended
for alerting a system about an overtemperature condition
or triggering a power supply crowbar circuit. If VDD for the
MIC502 is 5V the output should not be pulled to a higher
voltage. This output can sink up to 2mA and remain
compatible with the TTL logic-low level.
Timing Capacitors vs. PWM Frequency
The recommended CF is 0.1µF for operation at a PWM
frequency of 30Hz. This frequency is factory trimmed
within ±3Hz using a 0.1% accurate capacitor. If it is
desired to operate at a different frequency, the new value
for CF is calculated as follows:
3
C = , where C is in µF and f is in Hz
f
The composition, voltage rating, ESR, and other
parameters of the capacitor are not critical. However, if
tight control of frequency vs. temperature is an issue, the
temperature coefficient may become a consideration.
Because of input leakage considerations, the impedance
of the resistive divider should be kept at ≤100kΩ. A series
resistor of 120kΩ driven by the FanC signal and a 100kΩ
shunt resistor to ground make a good divider for driving
the VT2 input.
Transistor and Base-Drive Resistor Selection
The OUT motor-drive output, pin 7, is intended for driving
a medium-power device, such as an NPN transistor. A
rather ubiquitous transistor, the 2N2222A, is capable of
switching up to about 400mA. It is also available as the
PN2222A in a plastic TO-92 package. Because 400mA is
about the maximum current for most popular computer
power supply fans (with many drawing substantially less
current) and because the MIC502 provides a minimum of
10mA output current, the PN2222A, with its minimum β of
40, is the chosen motor-drive transistor.
Figure 7. Typical 5V VDD Application Circuit
The design consists solely of choosing the value RBASE in
Figure 7 and Figure 8. To minimize on-chip power
dissipation in the MIC502, the value of RBASE should be
determined by the power supply voltage. The Electrical
Characteristics table specifies a minimum output current
of 10mA. However, different output voltage drops (VDD
–
VOUT) exist for 5V vs.12V operation. The value RBASE
should be as high as possible for a given required
transistor base-drive current in order to reduce on-chip
power dissipation.
Figure 8. Typical 12V VDD Application Circuit
Referring to the Typical Application and to the Electrical
Characteristics table, the value for RBASE is calculated as
follows. For VDD = 5V systems, IOH of OUT (pin 7) is
guaranteed to be a minimum of 10mA with a VOH of 2.4V.
RBASE then equals (2.4V – VBE) ÷ 10mA = 170Ω. For VDD
= 12V systems, RBASE = (3.4 – 0.7) ÷ 0.01 = 250Ω.
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Micrel, Inc.
MIC502
Package Information and Recommended Land Pattern(9)
8-Pin SOIC (M)
Note:
9. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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Micrel, Inc.
MIC502
Package Information and Recommended Land Pattern(9)
8-Pin Plastic DIP (N)
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Micrel, Inc.
MIC502
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