MIC9130BM [MICROCHIP]
Switching Controller, Current-mode, 0.005A, 2500kHz Switching Freq-Max, BCDMOS, PDSO16, SOP-16;
| 型号： | MIC9130BM |
| 厂家： | 
MICROCHIP |
| 描述： | Switching Controller, Current-mode, 0.005A, 2500kHz Switching Freq-Max, BCDMOS, PDSO16, SOP-16 CD 开关 光电二极管 |
| 文件： | 总19页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MIC9130
High-Voltage, High-Speed Telecom DC-to-DC Controller
General Description
Features
TheMIC9130isacurrent-modePWMcontrollerthatefficiently
converts–48Vtelecomvoltagestologiclevels.TheMIC9130
featuresahighvoltagestart-upcircuitthatallowsthedeviceto
beconnectedtoinputvoltagesashighas180V.Thehighinput
voltage capability protects the MIC9130 from line transients
that are common in telecom systems. The start-up circuitry
also saves valuable board space and simplifies designs by
integrating several external components.
• Input voltages up to 180V
• Internal oscillator capable of >2.5MHz operation
• Synchronisation capability to 4MHz
• Current sense delay of 34ns
• Minimum pulse width <25ns
• 90% efficiency
• 1.3mA quiescent current
• 1μA shutdown current
• Soft-start
The MIC9130 is capable of high speed operation. Typically
the MIC9130 can control a sub-25ns pulse width on the gate
out pin. Its internal oscillator can operate over 2.5MHz, with
even higher frequencies available through synchronisation.
The high speed operation of the MIC9130 is made safe by
the very fast, 34ns response from current sense to output,
minimizing power dissipation in a fault condition.
• Resistor programmable current sense threshold
• Selectable soft-start retry
• 4ꢀ sink, 12ꢀ source output driver
• Programmable under-voltage lockout
• Constant-frequency PWM current-mode control
• 16-pin SOIC and 16-pin QSOP
The MIC9130 allows for the designs of high efficiency power
supplies. It can achieve efficiencies over 90% at high output
currents.Itslow1.3mAquiescentcurrentallowshighefficiency
even at light loads.
Applications
• Telecom power supplies
• Line cards
The MIC9130 has a maximum duty cycle of 50%. For de-
signs requiring a high duty cycle, refer to the MIC9131. The
MIC9130 is available in a 16-pin SOP and 16-pin QSOP
package options. The rated junction temperature range is
from –40°C to +125°C.
• ISDN network terminators
• Micro- and pico-cell base stations
• Low power (< 30W) dc-dc converters
Typical Application
MBR0540
40V/0.5A
20Ω
N = 5
12V
T1
1μF
16V
VIN
36V to 72V
VOUT
3.3V @ 4A
2.5μH
0.1μF
N = 20
N = 4
1M
Si4800DY
330μF (x2)
6.3V
B330
38.3k
13
1
2
10
Si4884DY
20k
7
6
FB
COMP
FQD10N20
0.2Ω
200V
1.21k
5
16
SYNC
CPWR
RBIAS
SS
OUT
8
3
MIC9130
Slope
Compensation
332k
12
9
14
ISNS
AGND PGND
332k
VBIAS
0.2Ω
1W
0.1μF
OSC
4
11
15
4.75k
10nF
47pF
OPTO
FEEDBACK
1.5MHz DSL Power Supply
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
November 2008
1
M9999-111108
MIC9130
Micrel, Inc.
Ordering Information
Part Number
Max. Duty Cycle Junction Temp. Range
Package
Standard
Pb-Free
MIC9130BM
MIC9130YM
50%
50%
-40°C to +125°C
-40°C to +125°C
16-Pin SOP
MIC9130BQS
MIC9130YQS
16-Pin QSOP
Pin Configuration
16
15
14
13
12
11
10
9
LINE
OUT
1
2
3
4
5
6
7
8
VCC
RBIAS
OSC
PGND
ISNS
UVLO
SS
SYNC
COMP
FB
AGND
EN
CPWR
VBIAS
16-Pin SOP (M)
16-Pin QSOP (QS)
Pin Description
Pin Number
Pin Name
LINE
Pin Function
1
2
3
4
Line (Input): 180Vdc maximum supply input. May be floated if unused.
Supply (Input): MIC9130 internal supply input.
VCC
RBIAS
OSC
Bias Resistor (External Component): Connect 562Kꢀ to ground.
Oscillator RC Network (External Components): Connect external resistor-
capacitor network to set oscillator frequency.
5
6
SYNC
COMP
Synchronization (Input): External oscillator input for slave operation of
controller. See OSC. Do not float.
Compensation (External Components): Error amplifier output for external
compensation network connection.
7
8
FB
Feedback (Input): Error amplifier inverting input.
CPWR
Current Limit Selection (Input): When CPWR is high, an over-current
condition at the ISNS input will terminate the gate drive and reset the
soft-start latch. If the CPWR pin is low, an over-current condition at the ISNS
input will terminate the gate drive signal, but will not cause a reset of the
soft-start circuit.
9
VBIAS
EN
Reference (Output): Internal 5V supply. Will source 5mA maximum.
10
Enable (Input): Logic level enable/shutdown input; logic high = enabled (on),
logic low = shutdown (off).
11
12
AGND
SS
Analog Ground (Return)
Soft-Start (External Components): Connect external capacitor to slowly ramp
up duty cycle during startup and over-current conditions.
13
14
UVLO
ISNS
Undervoltage Lockout (External Components): Connect to unbiased resistive
divider network to set controller’s minimum operating voltage. Connect to
VBIAS if not needed.
Current Sense (Input): Connect between external switching MOSFET source
and switch current sense resistor.
15
16
PGND
OUT
Power Ground (Return)
Switch Drive Output (Output): Connect to gate of external switching
MOSFET.
M9999-111108
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November 2008
MIC9130
Micrel, Inc.
Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 2)
Line Input Voltage (V
)..........................................+190V
Line Input Voltage (V
)..................V to +180V, Note 4
LINE
LINE CC
V
Input Voltage (V )..............................................+19V
V
Input Voltage (V ).................................. +9V to +18V
CC
CC
CC CC
Current Sense Input Voltage (V
)..............–0.3 to +5.3V
Junction Temperature Range (T ) ............ –40°C to +125°C
ISNS
J
Enable Voltage (V )............................. –0.3 to V + 0.3V
Package Thermal Resistance
EN
CC
16-pin SOP (θ ) ..............................................100°C/W
Feedback Input Voltage (V ) ........................–0.3 to +5.3V
JA
FB
16-pin QSOP (θ ) ............................................163°C/W
JA
Sync Input Voltage (V
)............................–0.3 to +5.3V
SYNC
Soft-Start Voltage (V )..................................–0.3 to +5.3V
SS
UVLO Voltage (V
)...................................–0.3 to +5.3V
UVLO
Storage Temperature (T ) ........................ –65°C to +150°C
S
Power Dissipation (P )
D
16-pin SOP...................................400mW @ T = +85°C
A
16-pin QSOP ................................245mW @ T = +85°C
A
ESD Rating, Note 3
Electrical Characteristics
TA = 25°C, VLINE = 48V, VCC = 10V, Rt = 9.47Kꢀ, Ct = 470pF, RBIAS = 562kꢀ, VEN = 10V, VISNS = 0V, VUVLO = 2V VSYNC = 0V, unless
,
otherwise noted. Bold values indicate –40 °C ≤TJ ≤ +125°C.
Parameter
Condition
Min
Typ
Max
Units
Bias Regulator
Output Voltage
IVBIAS = 0mA; VOSC = 0V (Oscillator OFF)
4.7
4.85
5.0
5.1
40
V
V
4.6
Line Regulation
9V ≤ VCC ≤18V, IVBIAS = 0mA; VOSC = 0V
0mA ≤ IVBIAS ≤ 5mA; VOSC = 0V
24
5
mV
mV
Load Regulation
Oscillator Section
Initial Accuracy (fOSC
30
)
Rt = 9.47Kꢀ, Ct = 470pF
180
200
fOSC/2
50
220
kHz
kHz
%
Oscillator Output Frequency
Maximum Duty Cycle
Voltage Stability (Δf/f)
9V ≤ VCC ≤18V
2.5
%
Temperature Stability
ppm/°C
–40°C ≤ TJ ≤ 125°C
100
Maximum Sync Frequency
Sync Threshold Level
Sync Hysteresis
Note 5
4
MHz
V
2.5
0.7
50
V
Sync Minimum Pulse Width
Error Amp Section
FB Voltage
ns
VCOMP = VFB
2.475
2.5
2.525
V
2.45
2.55
Open Loop Voltage Gain, AVOL
Unity Gain Bandwidth
PSRR
90
4
dB
MHz
dB
9V ≤ VCC ≤ 18V
60
COMP Sink Current
COMP Source Current
VCOMP Low
VFB = 2.7V; VCOMP = 5V
VFB = 2.3V; VCOMP = 0V
VFB = 2.7V; ICOMP = –50μA
VFB = 2.3V; ICOMP = +500μA
VFB = VCOMP
80
1
100
2.5
115
4
μA
mA
mV
V
300
VCOMP High
3.5
Input Bias Current (IFB
)
160
1.5
1.5
nA
Slew Rate
SINK
V/μs
V/μs
SOURCE
November 2008
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M9999-111108
MIC9130
Micrel, Inc.
Parameter
Condition
Min
Typ
Max
Units
Preregulator
Input Leakage Current
VLINE = 180V, VCC = 10V
VLINE = 48V
0.1
7.5
10
μA
V
V
CC Gate Lockout (VGLO(ON)
VCC Gate Lockout Hysteresis
(ΔVGLO
CC Pre-Regulator Off (VPR(OFF)
)
7.2
VLINE = 48V
700
800
mV
)
V
)
VLINE = 48V
V
V
GLO(ON)
+0.5V
7.7
VCC Pre-Regulator Hysteresis
(ΔVPR
VLINE = 48V
500
700
mV
mA
)
Start-up Current
VLINE = 48V, VCC = 7.5V, Note 4
9
12
Supply
Supply Current, IVCC
Enable Input Current
Shutdown Supply Current
Protection and Control
Current Limit Threshold Voltage
Current Limit Delay to Output
Current Limit Source Current
Pin 16 (OUT) = OPEN
1.3
0.1
0.1
1.5
10
10
mA
μA
μA
V
EN = 0V ,10V; VLINE = 48V
–10
VEN = 0V ; VCC = 18V
0.772
0.83
34
0.888
V
ns
μA
V
VISNS = 0V to 5V
VISNS = 0V
30
1
40
50
Enable Input Threshold (Turn-on)
Enable Input Hysteresis
CPWR Input Current
1.6
150
2.2
mV
μA
V
VCPWR = 5V, 0V
VSS = 0V
–1
+1
CPWR Threshold
1.6
4
Soft-Start Current
2.5
6
μA
V
Line UVLO Threshold (Turn-on)
Line UVLO Threshold Hysteresis
Thermal Shutdown
1.16
1.22
140
145
25
1.28
mV
°C
°C
Thermal Shutdown Hysteresis
MOSFET Driver
Output Minimum On-Time
Output Driver Impedance
V
ISNS = 5V
21
8
ns
ꢀ
SOURCE ; ISOURCE = 200mA
SINK ; ISINK = 200mA
COUT = 500pF
12
6
4
ꢀ
Rise Time
Fall Time
12
8
ns
ns
COUT = 500pF
Note 1. Exceeding the absolute maximum rating may damage the device.
Note 2. The device is not guaranteed to function outside its operating rating.
Note 3. Devices are ESD sensitive. Handling precautions recommended.
Note 4. If a substained DC voltage >150V is applied to the LINE pin, a current-limiting 1.8kΩresistor should be used in series with the LINE pin. This
condition does not apply for transient conditions over 150V.
Note 5. For oscillator frequencies above 2.5MHz it may be necessary to power to VBIAS pin from an external power source due to the current limita-
tions of the internal 5V regulator. See Applications Information for details
M9999-111108
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November 2008
MIC9130
Micrel, Inc.
Typical Characteristics
Oscillator Frequency
Oscillator Frequency
vs. Temperature
Error Amp Reference
vs. V
Voltage
Voltage vs. V
Voltage
CC
CC
5
4
2.502
2.501
2.500
2.499
2.0
1.5
1.0
0.5
0
FOSC(NOM)=200kHz
R =9.47K
RBIAS= 560K
3
t
C =470pF
t
2
1
0
-1
-2
-3
-4
-5
VCC= 10V
RBIAS= 560K
-0.5
-1.0
-1.5
-2.0
R = 9.47K
t
C = 470pF
t
-40
0
40
80
120 160
8
9 10 11 12 13 14 15 16 17 18
VCC (V)
8
9 10 11 12 13 14 15 16 17 18
VCC (V)
TEMPERATURE (°C)
Error Amp Reference
Line UVLO Threshold
Line UVLO Threshold
vs. Temperature
Voltage vs. Temperature
vs. V
CC
2.510
2.505
2.500
2.495
2.490
2.485
2.480
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
1.180
1.24
VCC= 10V
BIAS= 560K
VCC=10V
1.23 RBIAS=560K
R
1.22
1.21
1.2
1.19
1.18
-40 -20
0
20 40 60 80 100120140
8
9 10 11 12 13 14 15 16 17 18
VCC (V)
-40
0
40
80
120 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Quiescent Current
Quiescent Current
vs. Frequency
Quiescent Current
vs. Temperature
vs. V
Voltage
CC
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
1.4
1.39
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.31
1.3
10
C = 470pF
t
VCC= 10V
RBIAS= 560K
R = 9.47K
RBIAS= 560K
R = 9.47K
9
8
7
6
5
4
3
2
1
0
t
C = 470pF
t
t
C = 470pF
t
C = 120pF
t
0
200 400 600 800 1000
GATE DRIVE FREQUENCY (kHz)
8
10
12
14
16
18
-40 -20
0
20 40 60 80 100120140
VCC (V)
TEMPERATURE (°C)
ISNS to Gate Output Delay
Quiescent Current
ISNS to Gate Output Delay
vs. Overdrive
vs. R
vs. R
BIAS
BIAS
90
80
70
60
50
40
30
20
10
0
3.5
3
350
VCC = 10V
300
250
200
150
100
50
R = 9.53K
t
C = 470pf
t
fOSC= 200kHz
2.5
2
RBIAS=560K
RBIAS=360K
1.5
1
RBIAS=160K
0
0
200 400 600 800 1000 1200
0
200 400 600 800 1000 1200
RBIAS (kΩ)
RBIAS (kΩ)
OVERDRIVE (mV)
November 2008
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M9999-111108
MIC9130
Micrel, Inc.
Bias Voltage Load
Regulation
5V V
vs. Temperature
Voltage
BIAS
V
vs. V
CC
BIAS
5.010
5.06
5.04
5.02
5
5
4.99
4.98
4.97
4.96
4.95
4.94
VCC= 10V
RBIAS= 560K
5.008
5.006
5.004
5.002
5.000
4.998
4.996
4.994
4.992
4.990
VCC= 10V
RBIAS= 560K
4.98
4.96
4.94
R = 9.47K
t
C = 470pF
t
8
9 10 11 12 13 14 15 16 17 18
VCC (V)
-40 -20
0
20 40 60 80 100120140
0
1
2
3
4
5
TEMPERATURE (°C)
IBIAS (mA)
ISNS Current Limit Threshold
vs. V Voltage
V
Turn On/Off Thresholds
vs. Temperature
ISNS Current Limit Threshold
CC
vs. Temperature
CC
822.0
821.5
821.0
820.5
820.0
819.5
819.0
818.5
818.0
840
7.8
7.6
7.4
7.2
7
VCC=10V
RBIAS=560K
VCC= 10V
Vcc GLO On
RBIAS=560K
RBIAS= 560K
835
830
825
820
815
Vcc GLO Off
6.8
6.6
6.4
8
9 10 11 12 13 14 15 16 17 18
VCC (V)
-40
0
40
80
120 160
-40 -20
0 20 40 60 80 100120140
TEMPERATURE (°C)
TEMPERATURE (°C)
Gate Drive Current
Peak Short Circuit Depletion
FET Current vs. Temperature
80
Enable Threshold
vs. V
vs. V
CC
CC
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
2
1.95
1.9
180VLine
VCC = 0V
75
70
65
60
55
50
45
40
S INK
1.85
1.8
1.75
1.7
48VLine
1.65
1.6
S OURCE
1.55
1.5
8
9 10 11 12 13 14 15 16 17 18
VCC (V)
-40
0
40
80
120 160
TEMPERATURE (°C)
8
9
10 11 12 13 14 15 16 17 18
VCC (V)
Depletion FET Current
Peak Short Circuit Depletion
Depletion FET Current
vs. Low V
Voltage
LINE
FET Current vs. V
vs. V
LINE
LINE
10
80
12
10
8
–40°C
25°C
VCC = 0V
75
9
8
7
6
5
4
3
2
1
0
–40°C
25°C
70
65
125°C
125°C
VCC=7.5V
60
6
–40°C
55
50
45
40
25°C
4
2
125°C
40
0
7
7.5
8
8.5
VLINE (V)
9
9.5 10
0
80
120 160 200
0
40
80
VLINE (V)
120
160
VLINE (V)
M9999-111108
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November 2008
MIC9130
Micrel, Inc.
ISNS Pin Source Current
ISNS Pin Source Current
vs. Temperature
vs. V
CC
42
45
44
43
42
41
40
39
38
37
36
35
RBIAS=560K
RBIAS=560K
41.5
41
VCC=10V
40.5
40
39.5
39
38.5
38
8
10
12
VCC (V)
14
16
18
-40 -20
0 20 40 60 80 100120140
TEMPERATURE (°C)
November 2008
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M9999-111108
MIC9130
Micrel, Inc.
Oscillator Frequency vs.
RC Values
1000000
47pF
100pF
100000 220pF
470pF
680pF
1000pF
10000 2200pF
1000
*See applications section for higher
switching frequencies
10000
100000 1000000 10000000
FREQUENCY (Hz)
Functional Block Diagram
FB
COMP OSC
SYNC
7
6
4
5
Oscillator
2
VCC
SR Latch
Error
Amplifier
1.2V
R
5V
Q
OUT
16
PGND
AGND
15
11
40μA
S1
S2
ISNS 14
VBIAS
PWM
9
5V
0.82V
EN 10
BIAS
REG
RBIAS 3
Peak
Current Limit
1.21V
5V
MAXIMUM DUTY CYCLE
4μA
SS 12
Max.
Duty Cycle
Current
CPWR 8
Limit
Selection
R1
R2
Q
VCC 2
LINE 1
S
1-Shot
VCC
UVLO
UNDERVOLTAGE LOCKOUT
Thermal
Shutdown
LINE
UVLO
13
UVLO
Figure 1
M9999-111108
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November 2008
MIC9130
Micrel, Inc.
• Control loop operation
Functional Description
• Current sensing & overcurrent protection
• Slope compensation
• Error amplifier
Micrel’s MIC9130 is a high voltage, high speed current mode
switching power supply controller. It uses a BiC/DMOS pro-
cess to achieve a high voltage input, low quiescent current
and very fast internal delay times. The MIC9130 is designed
to drive an external low side N-channel MOSFET, which
makes it suitable for controlling Boost, Flyback and Forward
converter topologies. The high voltage startup pin eliminates
the requirement for an external start up circuit. This makes
it ideal for use with Telecom converters.
High Voltage Start Up Circuit
Many conventional Off-Line and Telecom power supplies
use an external bias resistor and zener diode to supply the
initial start-up voltage for the control IC. The control IC gets
its supply voltage from a bias winding once the power sup-
ply is running. This method has the disadvantages of extra
components (diode and power resistor), continuous power
dissipation in the resistor and a large bias capacitor, used to
supply the IC until the bias winding takes over.
Ablock diagram of the MIC9130 is shown in Figure 1. The de-
scription of the controller is divided into 6 basic functions:
• Power and bias circuitry
The MIC9130 eliminates these problems by using an internal
depletion mode MOSFET as a pre-regulator to provide the
start-up bias voltage from the high voltage input of the power
supply. This approach eliminates the need for external start
up components and reduces the size of the controller’s bias
supplycapacitor.TheMOSFETisturnedoffoncetheexternal
bias winding takes over, which eliminates power dissipation
in the start-up circuit. In some cases, the MIC9130 may be
run directly from the input voltage rail, eliminating the need
for an external bias winding.
• High voltage start-up circuit
• V and bias supplies
CC
• Enable and undervoltage monitoring circuits
• V and V UVLO
CC
IN
• Enable
• Oscillator and sync circuitry
• Soft-start and soft-start reset circuits
• MOSFET gate drive circuits
Transformer
Bias
Winding
MIC9130
Internal
Circuitry
1.21V
VCC
2
Line
1
VIN
180V
DEPLETION
FET
VCC
UVLO
THERMAL
SHUTDOWN
VPR(OFF) Depletion FET Pre-Regultor turn-off threshold
∆VPR
Depletion FET turn-on threshold
VGLO(ON) VCC gate lockout turn on threshold
∆VGLO VCC Gate Lockout Hysteresis
V
CC voltage when powered from VLINE
Figure 2
November 2008
9
M9999-111108
MIC9130
Micrel, Inc.
Start-up circuit operation is illustrated in Figure 2. V is ap-
for most topologies since the variation is small (equal to the
IN
pliedandthedepletionFET, whichisnormallyenabledallows
current from V to charge the V bias capacitor. Once the
ΔV hysteresis). The bias regulator in the MIC9130 buffers
PR
the internal circuits from V variations.
IN
CC
CC
V
voltage reaches the V enable threshold, V
(ON) ,
The pre-regulator FET is protected by a thermal shutdown
circuit,whichturnstheMOSFEToffifitstemperatureexceeds
approximately 150 degrees C.
CC
CC
GLO
the gate drive is enabled and the MIC9130 starts switching.
V
continues to increase until the Pre-Regulator turn-off
CC
threshold, (V (OFF)), is reached and the depletion FET is
turned off. The V voltage decreases as energy from the
bias capacitor is used to supply the controller. The deple-
tion FET is turned back on when the pre-regulator turn-on
threshold is reached. A bias winding derived supply voltage,
set higher than the FET turn-off threshold, V (OFF), raises
the V
from turning on.
PR
When operating at input voltages greater than 150V, a fast
inputvoltagerisetimeduringturn-on(whichmayoccurduring
a hot plug operation) may cause a high peak current to flow
through the depletion FET, damaging the MIC9130. A 1.8kΩ
resistor in series between the input voltage and the line pin
(pin 1) is recommended when operating at input voltages
greater than 150V. This resistor limits the maximum peak
CC
PR
voltage over the threshold and prevents the FET
CC
current to 100mA (at 180V ) and protects the part.
IN
IncertaindesignstheMIC9130maybepowereddirectlyfrom
theLinevoltage,eliminatingtheneedforanextratransformer
bias winding. When operating in this fashion the designer
must insure the power dissipation in the IC does not cause
the die temperature to exceed the 125°C maximum. Power
dissipation is calculated by:
The depletion mode MOSFET contains an internal parasitic
diode. The V pin voltage must be greater than the V
IN
CC
voltage or the V voltage will be clamped to a diode drop
CC
greater than the V voltage. Excessive power dissipation in
IN
the parasitic diode will destroy the IC.
V
and Bias Supplies
CC
PDISS= V −V
× I
VCC
IN
CC
The power for the controller and gate drive circuitry is sup-
Where :
plied through the V pin. The gate drive current is returned
CC
V
V
I
is the line input voltage
to ground through the power ground pin (PGND). The rest of
the supply current is returned to ground through the analog
ground pin (AGND). The two ground pins must be connected
together through the PCB ground plane.
IN
is the average V voltage (typically 8.5V)
CC
CC
is the total current drawn by the IC
VCC
I
is the sum of the operating current of the MIC9130 at
VCC
High frequency decoupling is provided at the V pin to sup-
CC
a given frequency and the average current required to drive
the external switching MOSFET. A plot of typical operating
current vs. frequency is given in Figure 3. The average MOS-
FET gate drive current is calculated in the “MOSFET GATE
DRIVE” section of this specification.
ply the gate drive’s peak current requirements. Turn-on of the
external MOSFET causes a voltage glitch on the V pin. If
CC
the glitch is excessive, this disruption can appear as noise or
jitter in the oscillator circuit or the gate drive waveform. The
decoupling capacitor must be able to supply the MOSFET
gate with the charge required to turn it on. A 0.1μF ceramic
capacitor is usually sufficient for most MOSFETs. Larger
FETs, with a higher gate charge requirement may require a
0.22μF ceramic capacitor or a ceramic capacitor paralleled
with a 2.2μF tantalum or 4.7uF aluminum electrolytic. It is
Quiescent Current
vs. Frequency
10
C = 470pF
9
8
7
6
5
4
3
2
1
0
t
recommend that if V
is greater than 150V DC than the
LINE
maximum capacitor recommended on V is 2.2μF.The ca-
C = 120pF
t
CC
pacitor must be located next to the V pin of the MIC9130.
CC
The ground end of the capacitor should be connected to the
ground plane, making a low impedance connection to the
power ground pin (pin 15).
0
200 400 600 800 1000
GATE DRIVE FREQUENCY (kHz)
Theinternalbiasregulatorblockprovidesseveralinternaland
external bias voltages. Referring to Figure 1, a 2.5V refer-
ence is used for the internal error amplifier, a 0.82V bias is
used by the current limit comparator and a 1.21V reference
is used by the Line UVLO circuit. An external 5V bias volt-
Figure 3
The die junction temperature is calculated by
TJ= TA +PDISS × θJA
age (V
) powers the oscillator circuit and may be used
Where: T is the die junction temperature
BIAS
J
as a reference voltage for other external components. The
pin requires a minimum 0.1μf capacitor to ground for
T is the ambient temperature of the circuit
A
V
BIAS
θ
is the junction to ambient thermal resistance
JA
decoupling.
of the MIC9130 (listed in the operating ratings
Enable and Undervoltage Monitoring circuits
The two undervoltage lockout circuits in the MIC9130 are
shown in Figure 4. One monitors the V
other monitors the input line voltage. These signals are OR’d
together and either one can disable the gate drive pin and
discharge the voltage on the soft start capacitor.
section of the specification.
When powered directly from the Line voltage, the V volt-
age will vary between the upper and lower pre-regulator
thresholds. The amplitude of the output gate drive voltage
CC
voltage and the
CC
will vary with the V voltage. This should not be a problem
CC
M9999-111108
10
November 2008
MIC9130
Micrel, Inc.
5V
MIC9130
4μA
12
SS
SET
S
R
Q
2
/Q
VCC
RESET
1.21V
VCC
UVLO
UVLO
16
11
13
OUT
AGND
VIN
R1
UVLO
LINE
UVLO
R2
15
PGND
Figure 4: UVLO and Soft Start Circuits
Enable
V
Undervoltage Lockout
CC
The V voltage is internally divided down and compared to
A low level on the enable pin turns off all the functions of the
MIC9130 and places it in a low quiescent current state. The
output driver is in a low state. When the enable pin is pulled
high, theMIC9130goesthroughitsnormalstartupsequence
includingundervoltagelockoutandsoftstart.Whennotused,
CC
a 1.21V internal bandgap reference. As V rises above the
CC
turn-on threshold, it disables the Vcc undervoltage lockout
circuit.Onceabovetheturn-onthreshold,hysteresisprevents
the lockout circuit from disabling the IC until the V voltage
CC
falls below the lower threshold.
the pin should be connected to V
.
CC
Line Undervoltage Circuit (UVLO)
Oscillator Block
The line voltage is monitored by an external resistor divider
and fed into the negative input of the line UVLO comparator.
Asthecomparatortrippointisexceeded,thelineUVLOcircuit
is disabled. Hysteresis built into the comparator prevents the
circuit from toggling on an off in the presence of noise or a
high input line impedance.
Anexternalresistorandcapacitorsettheoscillatorfrequency.
The MIC9130 contains an internal divide-by-two circuit that
limits the maximum duty cycle at the gate drive to 50%.
The oscillator frequency for the MIC9130 is twice the output
switching frequency.
Oscillator Pin
The line voltage turn-on trip point is:
R1+R2
The operation of the oscillator is shown in Figure 5. The volt-
age waveform at the OSC pin is a sawtooth whose amplitude
VLINE_ON =VTHRESHOLD
×
R2
increasesascapacitorCoscischargedupthroughR
from
OSC
the 5V bias. When the OSC pin voltage reaches the internal
comparator upper threshold, C is quickly discharged to
zero volts by an internal MOSFET. After a brief delay, typi-
where: V
is the voltage level of the internal
comparator reference, typically 1.21V.
THRESHOLD
OSC
The line hysteresis is equal to:
R1+R2
cally 75ns, the internal MOSFET is turned off and the C
OSC
charges, repeating the cycle. Figure 5 show the relationship
betweentheoscillatorandgatedrivewaveforms. Thedelays
in the IC force the duty cycle of the gate drive signal to be
slightly less than 50% duty cycle (typically 48%).
VHYSTERESIS= V
×
HYST
R2
where: V
is the internal hysteresis level, typically
is the hysteresis of the line input
HYST
75mV.
For V
= 5V and a peak oscillator waveform voltage of
BIAS
V
HYSTERESIS
voltage
3V, the design equations simplify to:
Charging
The MIC9130 will be disabled when the line voltage drops
back down to:
tCHARGE = 0.92 ×R t× Ct
VLINE_OFF=VLINE_ON −VHYTERESIS
=
Discharging
tDISCHARGE ≈ 40 ×Ct
R1+R2
V
THRESHOLD − VHYST ×
(
)
R2
November 2008
11
M9999-111108
MIC9130
TP_OSCILLATOR= tCHARGE +tDISCHARGE +tDELAY
Where tDELAY= 75ns
Micrel, Inc.
VCC
SYNC
VBIAS
4.7μF
OSC
2
5
1μF
1
9
2N3904
fS _ OSCILLATOR
=
TP _ OSCILLATOR
3V
ROSC
1.6k
1
4
fS
=
×fS
_
OSCILLATOR
_
OUTPU
4.7μF
4
COSC
33pF
The timing capacitor, C
, should be an NPO ceramic or a
AGND 11
OSC
75ns
1-shot
temperature stable film capacitor. Care must be taken when
usingcapacitorvalueslessthan47pF. Thehighimpedanceof
a small value capacitor makes the OSC pin more susceptible
to switching noise.Also, the input capacitance of the OSC pin
and the stray capacitance of the board will have a noticeable
effect on the oscillator frequency.
Figure 5b
Oscillator Synchronization
TheswitchingfrequencyoftheMIC9130canbesynchronized
to an external oscillator or frequency source. Figure 6 shows
the relationship between the sync input, oscillator waveform
and gate drive output. The external frequency should be set
atleast15%greaterthanthefreerunningoscillatorfrequency
to account for tolerances in the oscillator circuit and external
components. The positive edge of the sync signal resets the
oscillator.Thesyncpulsefrequency,liketheoscillator,istwice
the gate drive frequency. When an external sync signal is
applied, the peak amplitude of the oscillator signal (pin 4) is
less than when it is free running because the oscillator signal
is terminated before it reaches its 3V (typical) amplitude.
When not used, the sync pin should be connected to ground
to prevent noise from erroneously resetting the oscillator.
SYNC
5
VBIAS
9
3V
ROSC
OSC
4
COSC
75ns
1-shot
11
AGND
VOSC
Gate Drive
(pin 16)
tON
tPERIOD
TIME (500ns/div)
Figure 6. Sync Waveform
Soft Start Circuit
Figure 5a
Higher Switching Frequencies
The soft start is programmed by a capacitor on the soft start
pin. A4μAcurrent source charges up the capacitor. At power
up, the SS pin is discharged. Once the UVLO and enable
functions release the soft start circuit, the voltage of the ca-
pacitor increases. The active voltage range of the soft start
pin is from typically from 0.9V to 1.7V. The internal current
source increases the voltage on the soft start capacitor to
approximately 4V. The soft start pin and the current sense
voltage are connected to a comparator in tç
The MIC9130 is capable of very high switching frequencies.
One of the limitations on the maximum frequency is the cur-
rent capability of the 5V regulator supplying the oscillator
and V
. By powering V
with an external source, e.g.
BIAS
BIAS
linear regulator much higher switching frequencies can be
achieved. A simple way of using an external current source
is to set an NPN as an emitter follower. Figure 5b shows the
MIC9130 oscillator frequency set to 4MHz using an external
NPN. The emitter followerj circuit allows the current to be
PMIC9130. The voltage from the soft start pin effectively
limits the peak current through the current sense resistor by
prematurely terminating the on-time of the gate drive output.
Referring to Figure 1, with the soft start voltage low, the duty
cycle of the output is at a minimum. As the soft start voltage
increases, the duty cycle of the gate drive output increases
supplied by V
drop below V
while the voltage is regulated to a diode
CC
. This configuration is quite stable over
BIAS
temperature and voltage variations.
M9999-111108
12
November 2008
MIC9130
Micrel, Inc.
until the error amplifier takes control of the duty cycle. The
soft start capacitor is discharged by an internal MOSFET in
the MIC9130.
A resistor placed in series with the gate drive output attenu-
ates ringing in the etch connection between the MIC9130
and the MOSFET. Figure 8 shows a single resistor in series
between the driver output and the gate of the MOSFET. The
zener value should be greater than the gate drive voltage
to prevent excessive power dissipation, but less than the
maximum gate to source voltage rating.
The soft start circuit is activated by the following events:
1. Line undervoltage pin less than the 1.21V threshold
2. V becomes less than the pre-regulator voltage turn
CC
.................................................................off threshold.
3. The current limit comparator threshold is exceeded.
This can be disabled with a low level on the
Gate Drive
Output
CPWR
pin.
4. A low level on the enable pin.
Calculating the soft capacitor depends on many parameters
such as the current limit of the circuit input voltage, output
powerandoutputloading.Astartingvalueofcapacitorshould
be chosen and the value can be adjusted later in the design.
Recommended starting values of soft start capacitance is
typically 10nF to 100nF. Values below 1nF may be ineffective
in slowing the output voltage turn on time.
GND
Figure 8
Thecircuitryshowninfigure9allowdifferentriseandfalltimes.
R1 and the input capacitance of the MOSFET determine the
rise-time of the gate voltage and therefore the turn-on time of
theMOSFET.Thediode,D1isreversedbiased,whichremoves
R2 from the circuit. At turn-off, D1 is forward biased and the
parallel combination of R1 and R2 controls the turn-off time
of the MOSFET. The turn on-time is slower, which reduces
switching noise and ringing during turn-on. The turn-off time
isfaster,whichminimizesswitchinglossesduringturn-offand
improves efficiency. If the turn-on time is to be faster than
the turn-off time, the diode should be reversed.
CPWR Current Limit Selection
This pin controls whether the soft start circuit is reset if the
voltage on the Isns pin exceeds the overcurrent threshold.
When the CPWR pin is high, an overcurrent condition at the
ISNS pin will terminate the on-time of the gate drive pulse
and discharge the soft start capacitor to zero volts. This delay
in start up contributes to a reduction in the average output
current during an overcurrent or short circuit condition. A
smaller MOSFET may be used since the power dissipation
in the MOSFET is minimized under short circuit or overcur-
rent conditions.
R2
D1
R1
Gate Drive
Output
If the CPWR pin is low an overcurrent or short circuit condi-
tions will not trip the soft start circuit. The pulse-by-pulse
current limit, inherent in current mode control, provides a
“brick wall” or constant current limit. With the power supply
operating in this mode, a smaller soft start capacitor can be
used to increase the turn on speed of the supply.
GND
If the CPWR in is held low during the initial turn on at power
up and then raised high, the power supply can maximize
the turn-on time at start up and still provide a high level of
overcurrent and short circuit protection. The circuit shown
Figure 9
A gate drive transformer is used where an increase in drive
voltage, isolation and/or voltage level shifting are required.
Gatedrivetransformerscanhavemultiplewindingsanddrive
multiple MOSFETs, including MOSFETs that require a drive
signal 180 degrees out of phase with the ICs drive signal.
in Figure 7 performs this function.
MIC9130
VREF
D1
C1
R1
Figure 10 shows a gate drive transformer circuit. The ca-
pacitor, C1 removes DC from the drive circuit and prevents
transformer saturation. R1 provides damping to eliminate
ringing in the circuit. R1 is usually in the 5 to 20Ω range,
depending on the amount of damping necessary. D1 and
D2 form a clamp circuit, which prevents the voltage from
CPWR
AGND
exceeding the V
level. If the gate drive is well damped,
GMAX
the diodes may be removed R2 is used to allow the trans-
former to reset properly.
Figure 7
MOSFET Gate Drive Output
The MIC9130 has the capability to directly drive the gate of
a MOSFET. The output driver consists of a complimentary
P-channel and N-channel pair. The typical switching time
of the output is dependent on the IC supply voltage and the
gate charge required to turn the MOSFET on and off.
November 2008
13
M9999-111108
MIC9130
Micrel, Inc.
Current Sense Circuit
C1
The current sense input of the MIC9130 has three unique
features, which are advantageous in a high speed, high ef-
ficiency power supply.
T1 R1
D2
Gate Drive
Output
1. The overcurrent threshold is nominally 0.82V instead
of the typical 1.0V found in most switching control
ICs.
R2
GND
D1
1:N
2. The current sense pin sources a nominal 40μA of
current out of the pin. This is used to raise the current
limit threshold of the pin, which allows a smaller
current sense resistor to be used. This improves the
efficiency of the power supply, especially in lower
current applications.
Figure 10
The gate impedance of a MOSFET is capacitive and the
power required to drive the gate is proportional to the charge
required to turn on the MOSFET, the peak gate voltage and
the switching frequency. Assuming the total gate charge for
turn on and turn off is equal, the power used to switch the
MOSFET on and off is:
3. The delay from the current sense input to the output
is typically 50ns.
The current limit threshold of the ISNS pin was set at 0.82V,
allowing the use of a smaller current sense resistor. Astable,
bandgap derived 40μAcurrent is sourced from the ISNS pin.
A voltage drop across a series resistor placed between the
pin and the current sense resistor level increases the current
sense signal at the ISNS pin. This allows the use of a smaller
current sense resistor if the full 0.82V peak to peak current
signal is not required. Decreasing the value of the current
senseresistordecreasesthepowerdissipationintheresistor,
which improves the efficiency of the power supply.
PDRIVE = QG ×VGS × fS
where: Q is the total gate charge at V
G
GS
V
is the gate to source voltage of the MOSFET
GS
usually equal to V
CC
f is the output switching frequency
S
The power required to drive the MOSFET is dissipated in the
drive circuitry of the MIC9130. This power must not cause
the die temperature to exceed the maximum rated junction
temperature of 125 degrees C.
The delay between the input of the overcurrent comparator
and the output gate drive is nominally 50ns. This very fast
response time allows the MIC9130 to operate at higher fre-
quencies and still have adequate overcurrent protection.
MOSFETDriver IC’s are used when the drive requirement for
the MOSFETs is greater than the capability of the MIC9130
gate drive output. While the peak current of the MIC9130
gate drive is typically 1.2A at V =12V, a gate driver ICs
The operation of the current sense input is as follows. The
sensed current in the power supply is converted to a volt-
age by a resistor or current sense transformer. Referring to
Figure 1, this voltage is compared to the output of the error
amplifier, which sets the duty cycle of the gate drive output.
The current signal is also connected to an Imax comparator.
Comparing the current sense signal to the reference voltage
setsamaximumcurrentlimit.Ifthemaximumamplitudeofthe
current sense signal exceeds the reference, the comparator
terminates the gate drive output pulse. It aslo discharges the
soft start capacitor when the CPWR pin is high.
IN
will sink or source between 1.2A and 12A of peak current.
The higher peak current allows faster rise and fall times for
larger MOSFETs.
The drive requirements for selecting a MOSFET driver are
determined using the following equation:
QG
IPK= 2 ×
t
where: Q is the total gate charge required to turn on
G
the MOSFET at a specified I , V and V . This
D
G
DS
information is usually given in the MOSFET
specification sheet.
Leading Edge Current Spike
The current signal in a power circuit will often have a leading
edge spike caused by leakage inductance, parasitic induc-
tance and capacitance, diode reverse recovery effects and
snubbers. These spikes can cause premature termination of
the switching cycle if they are not eliminated.
t is the gate voltage transition time (risetime or fall
time)
I
is the peak current requirement of the
PK
MOSFET driver IC.
For example, if a MOSFET is chosen with a Q of 60nC and
it is desired to have a 50nS gate to source risetime/falltime,
the peak current requirement of the MOSFET driver is:
Aresistor may be added in series between the current sense
resistor and the Isns input. The input and board trace ca-
pacitance of the ISNS pin (pin 14) is approximately 25pF. A
1k resistor is a good choice, since it attenuates most of the
ripple without distorting the current sense waveform. It has
a minimal effect on level, offsetting the current sense signal
by only 40mV.
G
2 × 60nC
IPK=
= 2.4A
50ns
A driver such as the MIC4424 will meet this requirement.
For more information on choosing a MOSFET driver, see
the Micrel application note AN-24, “Designing with Low Side
MOSFET Drivers.”
A typical rule of thumb is the bandwidth of the RC filter
should be at least 6 times the switching frequency. This
avoids distorting the current sense waveform and adding
excessive delays in the current loop that will interfering with
overcurrent protection. For a 100kHz switcher, the maximum
M9999-111108
14
November 2008
MIC9130
Micrel, Inc.
Sensing Current with a Current Sense Transformer
seriesresistanceis10K,fora500kHzswitcher,themaximum
series resistance is 2K.
Athigherpowerlevels,thepowerdissipationinacurrentsense
resistor is excessive. A current sense transformer can be
usedtosensethecurrentwhileminimizingpowerdissipation.
See Figure 11. The schematic shows the circuitry necessary
when using a current sense transformer. The resistor, R1,
provides a path to reset the current sense transformer. The
resistor, R2, converts the scaled down current to a voltage,
Sensing Current with a Resistor
The fast transition times of the current signal prohibit the use
of inductive resistors. Standard wire wound power resistors
will not work. Carbon composition or metal film resistors or
lowinductancepowerresistorsmaybeused. Theovercurrent
rangeofthepowersupplyandcomponenttolerancesmustbe
considered when selecting the current sense resistor value.
The power supply specification may call for an overcurrent
limit, which must be accounted for when selecting the cur-
rent sense resistor value. The relationship between the peak
primary current and the current sense resistor is:
which is sent to the ISNS pin.
VIN
Current Sense
V
= IP ×RISENSE + IISNS ×Rf
ISNS
Rf
ISNS
(pin 14)
Transformer
where: Ip is the current in the sense resistor
R2
R1
IPRI
R
I
is the current sense resistance
ISENSE
MIC9130
is the current sourced from the ISNS pin
ISNS
(40μA)
OUT
(pin 16)
R is the series resistor between the ISNS pin and
f
the current sense resistor.
The current sense resistor must not be too small or the cur-
rent sense signal will be susceptible to noise. If noise is a
problem, the current signal level should be increased.
Figure 11
The voltage at the ISNS pin is calculated by:
IP
An example is illustrated below.
V
=
×R2 + IISNS ×Rf
ISNS
N
The maximum peak current, I
and minimum input voltage
= 1Aat 120% overcurrent
PMAX
where: I is the current in the primary of the current sense
P
transformer
The maximum rms current, I
=0.65A
RMS
R2 is the current sense resistance at the
secondary of the current sense transformer
The desired current sense signal amplitude is 500mV at 1A
output current.
N is the turns ratio of the current sense
transformer (N=Nsec/Npri)
The current sense resistor value and power dissipation is:
VSENSE
ISENSE
2
0.5
1
RSENSE
=
=
= 0.5Ω
I
is the current sourced from the ISNS pin
ISNS
(40μA)
PDISS = IRMS ×RSENSE = 0.652 ×0.5 = 0.21W
R is the series resistor between the ISNS pin and
f
the current sense resistor.
A 0.5Ω, non inductive resistor with at least a 1/2W rating
should be selected.
Current Transformer example:
The maximum peak current, I
= 5Aat 120% overcur-
= 3.25A
The series resistor is calculated to allow the 500mV-peak
signal to reach 0.82V.
PMAX
rent and minimum input voltage
The maximum rms current, I
RMS
V
− I ×R
0.82 − 1×0.5
(
)
=
(
)
ISNS
P
ISENSE
Rf
=10.25kΩ
The full 0.82V peak signal a the ISNS input can be used
since very little power is dissipation in the secondary
side sense resistor. The maximum peak to peak volt-
age at the sense pin (pin 14) is 0.82V at the 5A maximum
output current.
IISNS
40μA
The next lower value of 10kꢀ is selected.
The bandwidth of the 10K resistor and the 25pF input capaci-
tance is calculated. The resistor value must be lowered if the
bandwidth is too low for the switching frequency.
1
The current sense resistor value and power dissipation
is:
BW =
= 630kHz
VSENSE × N
IP
2 ×
π
×10k × 25pF
0.82 ×100
5
R2 =
=
=16.4Ω
The maximum switching frequency of this power supply
should be approximately six times less than the BW to pre-
vent current waveform distortion and excessive delays in
the current loop. This limits the switching frequency to the
range of 100kHz.
2
2
I
3.25
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
PRMS
PDISS
=
×R2 =
×16.4 =17.4mW
N
100
November 2008
15
M9999-111108
MIC9130
Micrel, Inc.
A 16.2 ohm, 1%, non inductive resistor with at least a 50mW
rating should be selected. A good choice would be an 0805
size metal film or a 1/8 watt leaded metal film resistor. A
series resistor between the current sense transformer and
the Isns input is not necessary unless it is used for low pass
filtering.
where :
V is the output voltage
O
V is the forward voltage drop of the rectifier diode
D
L is the inductance of the output inductor (or the
secondary winding inductance for the flyback
topology)
If the current sense transformer were not used, the sense
resistor would dissipate 1.7 watts.
M2 is the inductor current downslope
For a boost topology, the inductor downslope is:
VSENSE
ISENSE
2
0.82
5
RSENSE
=
=
= 0.164Ω
VOUT − V +VD
di
dt
IN
M2 =
=
L
PDISS = IRMS ×RSENSE = 3.252 ×0.164 =1.7W
In a transformer isolated topology, the downslope must be
reflected back to the primary by the turns ratio of the trans-
former. The reflected downslope is:
Slope Compensation
Power supplies using peak current mode control techniques
require slope compensation when they are operating in
continuous mode and have a duty cycle greater than 50%.
Withoutslopecompensation,thedutycycleofthepowersup-
ply will alternate wide and narrow pulses commonly referred
to as subharmonic oscillations. Even though the MIC9130
operates below a 50% duty cycle, slope compensation adds
the benefits of improved transient response and greater
noise immunity in the current sense loop (especially when
the current ramp is shallow). Slope compensation can be
implemented by adding an optimum 1/2 of the inductor cur-
rent downslope, reflected back to the current sense input. In
real world applications, 2/3 of the inductor current downslope
is used to allow for component tolerances.
Ns
M2REFLECTED = M2 ×
Np
where : Ns/Np is the turns ratio of the secondary winding
to the primary winding.
M2
is the inductor curent downslope
REFLECTED
reflected to the secondary side of the current
sense transformer.
The reflected downslope is multiplied by the current sense
resistor to obtain the downslope at the current sense input
pin (ISNS).
ISNS _ SLOPE= M2REFLECTED ×RS
where Rs is the value of the current sense resistor.
Slope compensation at the ISNS input may be implemented
by using a resistor and capacitor as shown in Figure 12. The
rectangular waveshape of the gate drive output is integrated
by the resistor/capacitor filter, which results in a ramp used
for the slope compensation signal. When the gate drive and
the current signal at the sense resistor goes low, the capaci-
tor is discharged to 0V.
The required downslope of the compensation ramp at the
ISNS input is:
M3 = ISNS _ SLOPE ×0.67
R1 is know if a value for the resistor between the current
sense resistor and the Isns pin, has already been selected.
If not chose a value of 1k, which will minimize any offset
and signal degradation at the ISNS pin. Select a value of
C1 to minimize signal degradation from the cutoff frequency
of R1/C1. The bandwidth should be at least six times the
switching frequency.
Gate Drive
(pin 16)
R2
MIC9130
ISNS
(pin 14)
R1
1
C1=
2 × π×fS ×R1
C1
RSENSE
where: f is the switching frequency of the power
S
supply (not the oscillator frequency)
The slope of the generated compensation ramp is:
Figure 12
R1
1
M3 = VGATE_DRIVE
×
×
Theprocedureoutlinedbelowdemonstrateshowtocalculate
the component values.
R2 +R1 R2 ×C1
Solving for R2 and assuming R2 is much greater than R1.
Compute the inductor current downslope as seen at the cur-
rent sense input.
VGATE _DRIVE × R1
R2 =
M3 × C1
For a flyback, buck or forward mode topology the
inductor downslope is equal to:
where: V
is the amplitude of the gate
GATE_DRIVE
drive waveform
VO + VD
L
di
dt
M2 =
=
M9999-111108
16
November 2008
MIC9130
Micrel, Inc.
Error Amplifier
provides the reference to limit and control the peak current
of the power supply. There is a 1.2V level shift between the
output of the error amplifier and the PWM comparator. This
allows the output of the error amplifier to operate in a linear
regionandpreventsloadingontheCOMPpinfrominterfering
with proper control of the current signal.
The error amplifier is part of the voltage control loop of the
power supply. The FB pin is the inverting input to the error
amplifier. The non-inverting input is internally connected to
a 2.5V reference. The output of the error amplifier, COMP,
is connected to the PWM comparator. The error amplifier
November 2008
17
M9999-111108
MIC9130
Micrel, Inc.
Package Information
16-Lead SOIC (M)
16-Lead QSOP (QS)
M9999-111108
18
November 2008
MIC9130
Micrel, Inc.
MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's
use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2001 Micrel Incorporated
November 2008
19
M9999-111108
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