MICRF507YML-TR [MICROCHIP]
SPECIALTY TELECOM CIRCUIT, QCC32;
| 型号： | MICRF507YML-TR |
| 厂家： | 
MICROCHIP |
| 描述： | SPECIALTY TELECOM CIRCUIT, QCC32 电信 电信集成电路 |
| 文件： | 总47页 (文件大小：928K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MICRF507
470MHz to 510MHz Low-Power FSK
Transceiver with +10dBm Power Amplifier
General Description
The MICRF507 is a fully-integrated FSK transceiver with
+10dBm power amplifier and transmit/receive switch. The
device is targeted at automated meter reading (AMR)
applications in the China Short Range Device (SRD)
frequency band of 470MHz to 510MHz. The device
supports data rates up to 20kbps with PLL divider
modulation and up to 200kbps with VCO modulation. The
receiver achieves a sensitivity of -113dBm at a data rate of
2.4kbps while only consuming 12mA of supply current.
The integrated power amplifier (PA) delivers +10dBm of
output power while only consuming 21.5mA of supply
current. Power down supply current is a low 0.2µA while
retaining register information and a low 280µA in standby
mode where only the crystal oscillator is enabled.
RadioWire®
Features
• -113dBm sensitivity at 2.4kbps encoded bit rate
• +10dBm power amplifier with seven gain steps
• 12mA receive supply current
• 21.5mA transmit supply current at +10dBm
• 0.2μA power down current (registers retain settings)
• 280µA standby current (crystal oscillator enabled)
• Data rates up to 20kbps with PLL divider modulation
• Data rates up to 200kbps with VCO modulation
• Integrated transmit and receive (T/R) switch
• LNA with bypass mode
The receiver of the MICRF507 utilizes a Zero IF (ZIF) I/Q
architecture, integrating a low-noise amplifier (LNA) with
bypass mode, I/Q quadrature mixers, three-pole Sallen-
Key IF channel pre-filters, and six-pole elliptic switched
capacitor IF filters, providing excellent selectivity, adjacent
channel rejection and blocking performance. FSK
demodulation is implemented digitally and a synchronizer,
when enabled, recovers the received bit clock. A receive
signal strength indicator (RSSI) circuit indicates the
received signal level over a 50dB range. An integrated
Frequency Error Estimator (FEE) and crystal tuning
capability allow fine tuning of the RF frequency.
• Zero IF I/Q receiver architecture
• IF pre-amplifiers with DC-offset removal
• Three-pole Sallen-Key IF channel low-pass pre-filter
• Six-pole elliptic switched capacitor IF low-pass filter
• 50kHz to 350kHz programmable baseband bandwidth
• 59dB blocking at ±1MHz offset
• 53dB adjacent channel rejection at ±500kHz offset
• FSK digital demodulator with clock recovery
• 50dB Received Signal Strength Indicator (RSSI)
• Frequency Error Estimator (FEE)
The transmitter of the MICRF507 consists of an FSK
modulator and power amplifier with output power
adjustable from +10dBm to -3.5dBm in seven steps.
Modulation can be achieved by applying two sets of PLL
divider ratios or through direct VCO modulation by varying
VCO tank capacitance.
• Reference crystal tuning capability
• 2.0 to 2.5V supply voltage range
• -40˚C to +85˚C operating temperature range
• Available in 32-pin QFN package
The MICRF507 requires a 2.0V to 2.5V supply voltage,
operates over the -40˚C to +85˚C temperature range, and
is available in a 32-pin QFN package.
(5.0mm × 5.0mm × 0.85mm)
Applications
• China Short Range Device (SRD) Communications
• Automated Meter Reading (AMR)
• Advanced Metering Infrastructure (AMI)
• Wireless Remote Meter Reading
RadioWire is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Revision 2.2
October 2, 2013
Micrel, Inc.
MICRF507
RadioWire® FSK Transceiver Selection Guide................................................................................................................4
Ordering Information .........................................................................................................................................................4
Pin Configuration ...............................................................................................................................................................4
Pin Description...................................................................................................................................................................4
Block Diagram ....................................................................................................................................................................6
Absolute Maximum Ratings..............................................................................................................................................7
Operating Ratings ..............................................................................................................................................................7
Electrical Characteristics ..................................................................................................................................................7
Functional Description ....................................................................................................................................................10
Control (3-wire) Interface ......................................................................................................................................10
Reading.................................................................................................................................................................13
Control Interface Timing........................................................................................................................................14
Power-on Reset ....................................................................................................................................................14
Clock Generation .............................................................................................................................................................15
Crystal Oscillator (XCO) ..................................................................................................................................................16
BITSYNC_CLK (Receiver Bit Synchronization Clock)..........................................................................................17
BITRATE_CLK (Transmitter Bit Rate Clock) ........................................................................................................17
MODULATOR_CLK (VCO Modulator Clock)........................................................................................................17
Data Interface and Bit Synchronization.........................................................................................................................17
Sync_en = 0 ..........................................................................................................................................................19
Sync_en = 1 ..........................................................................................................................................................19
Additional Considerations in the Use of Synchronizer (Sync_en = 1) ..................................................................19
Frequency Synthesizer....................................................................................................................................................20
VCO.......................................................................................................................................................................22
Charge Pump........................................................................................................................................................22
PLL Filter...............................................................................................................................................................22
Lock Detect ...........................................................................................................................................................23
Receiver ............................................................................................................................................................................24
Front End...............................................................................................................................................................24
Sallen-Key Filters..................................................................................................................................................25
Switched Capacitor Filter ......................................................................................................................................25
RSSI......................................................................................................................................................................25
FEE .......................................................................................................................................................................26
XCOtune Procedure Example .........................................................................................................................................27
Transmitter........................................................................................................................................................................28
Power Amplifier .....................................................................................................................................................28
Frequency Modulation...........................................................................................................................................29
Divider Modulation ................................................................................................................................................30
VCO Modulation and the Modulator......................................................................................................................30
Modulator Filter .....................................................................................................................................................32
System Modes and Initialization.....................................................................................................................................33
Start-up and Initialization.......................................................................................................................................33
Modes of Operation...............................................................................................................................................33
Mode Transitions...................................................................................................................................................33
Message Coding and Formatting ...................................................................................................................................34
DC Balanced Line Coding.....................................................................................................................................34
Message Formatting: Preamble............................................................................................................................34
Typical Application ..........................................................................................................................................................35
Revision 2.2
October 2, 2013
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Micrel, Inc.
MICRF507
Bill of Materials.................................................................................................................................................................36
Layout Considerations ....................................................................................................................................................37
Layer Definition .....................................................................................................................................................37
Grounding..............................................................................................................................................................37
RF Traces..............................................................................................................................................................37
Supply Routing......................................................................................................................................................37
PLL Loop Filter......................................................................................................................................................37
Overview of Programming Bits.......................................................................................................................................38
Detailed Description of Programming Bits....................................................................................................................39
Package Information and Recommended Landing Pattern.........................................................................................46
Revision 2.2
October 2, 2013
3
Micrel, Inc.
MICRF507
RadioWire® FSK Transceiver Selection Guide
Maximum Data
Rate
Receive
Part Number
Frequency Range
Supply Voltage
Transmit Current
Package
Current
13.5mA
13.5mA
12mA
MICRF505
MICRF505L
MICRF506
MICRF507
850MHz to 950MHz
850MHz to 950MHz
410MHz to 450MHz
470MHz to 510MHz
200kbps
200kbps
200kbps
200kbps
2.0 to 2.5V
2.25 to 5.5V
2.0 to 2.5V
2.0 to 2.5V
28mA
28mA
QFN-32
QFN-32
QFN-32
QFN-32
21.5mA
21.5mA
12mA
Ordering Information
Part Number
Junction Temperature Range
Package
MICRF507YML TR
-40° to +85°C
Pb-Free 32-Pin QFN
Pin Configuration
32-Pin QFN
Pin Description
Pin Number
Pin Name
Type
Pin Function
1
2
3
4
5
6
7
RFGND
PTATBIAS
RFVDD
RFGND
ANT
LNA and PA ground.
Connection for bias resistor.
LNA and PA power supply.
LNA and PA ground.
Antenna Input/Output.
LNA and PA ground.
LNA and PA ground.
O
I/O
RFGND
RFGND
Revision 2.2
October 2, 2013
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Micrel, Inc.
MICRF507
Pin Description (Continued)
Pin Number
Pin Name
Type
Pin Function
8, 16, 17, 32
NC
No connect. Leave these pins floating.
Connection for bias resistor.
IF/mixer power supply.
IF/mixer ground.
9
CIBIAS
IFVDD
O
10
11
12
13
14
15
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IFGND
ICHOUT
QCHOUT
RSSI
O
O
O
O
O
I/O
I/O
I
Test pin.
Test pin.
Received signal strength indicator.
PLL lock indicator.
LD
DATACLK
DATAIXO
IO
RX/TX data clock output.
RX/TX data input/output.
3-wire interface data in/output
3-wire interface serial clock.
3-wire interface chip select.
Crystal oscillator input.
Crystal oscillator output or external reference input.
Digital power supply.
SCLK
CS
I
XTALIN
XTALOUT
DIGVDD
DIGGND
CPOUT
GND
I
I/O
Digital ground.
O
I
PLL charge pump output.
Substrate ground.
VARIN
VCO varactor tune voltage input.
VCO ground.
VCOGND
VCOVDD
Exposed Paddle
VCO power supply.
Ground.
Revision 2.2
October 2, 2013
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Micrel, Inc.
MICRF507
Block Diagram
Revision 2.2
October 2, 2013
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Micrel, Inc.
MICRF507
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD)...................................................+2.7V
Voltage on any pin (GND = 0V)..............-0.3V to +2.7V
Lead Temperature (soldering, 4sec.)......................... 300°C
Storage Temperature (Ts) ..........................-55°C to +150°C
ESD Rating(3)..................................................................2kV
Supply Voltage (VIN)..................................+2.0V to +2.5V
RF Frequencies ................................ 470MHz to 510MHz
Encoded Bit Rate.................................................200kbps
Ambient Temperature (TA).......................–40°C to +85°C
Package Thermal Resistance
32-Pin QFN (θJA) .........................................41.7°C/W
Electrical Characteristics(4)
fRF = 490MHz, fXTAL = 16MHz, MICRF507 Development Board, Modulation type = closed-loop VCO modulation, Sync_en bit = 1,
DD = 2.5V; TA = 25°C, the term “bit rate” refers to encoded bit rate throughout the EC table (see Figure 24), bold values indicate
V
–40°C< TA < +85°C, unless noted.
Symbol Parameter
Condition
Min
470
Typ
Max
510
Units
MHz
V
fRF
RF Frequency Operating Range
VDD
Power Supply
2.5
0.2
3
Power Down Current
Standby Current
µA
280
µA
VCO and PLL Section
Reference Frequency
4
40
MHz
ms
490MHz to 490.5MHz
485MHz to 495MHz
490MHz to 490.5MHz
Rx – Tx
0.7
1.3
0.3
1.0
1.0
1.0
1.0
PLL Lock Time, 3kHz Bandwidth
PLL Lock Time, 20kHz Bandwidth
ms
ms
Tx – Rx
Switch Time, 3kHz Loop Bandwidth
ms
Standby to Rx
Standby to Tx
With MICRF507 development
board BOM
Crystal Oscillator Start-Up Time
Charge Pump Current
1.0
ms
100
420
170
680
VCPOUT = 1.1V, CP_HI = 0
125
500
µA
µA
VCPOUT = 1.1V, CP_HI = 1
Transmit Section
10
-3.5
±1
dBm
dBm
dB
R
LOAD = 50Ω, PA[2:0] = 111
POUT
Output Power
RLOAD = 50Ω, PA[2:0] = 001
Over temperature range
VDD = 2.0V
Output Power Variation Relative to
VDD = 2.5V, TA = 25°C
-2
dB
21.5
10.5
8.0
mA
mA
mA
RLOAD = 50Ω, PA[2:0] = 111
RLOAD = 50Ω, PA[2:0] = 001
RLOAD = 50Ω, PA[2:0] = 000
Transmit Mode Current
Consumption
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model; 1.5k in series with 100pF.
4. Specification for packaged product only.
Revision 2.2
October 2, 2013
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Micrel, Inc.
MICRF507
Electrical Characteristics(4) (Continued)
fRF = 490MHz, fXTAL = 16MHz, MICRF507 Development Board, Modulation type = closed-loop VCO modulation, Sync_en bit = 1,
DD = 2.5V; TA = 25°C, the term “bit rate” refers to encoded bit rate throughout the EC table (see Figure 24), bold values indicate
V
–40°C< TA < +85°C, unless noted.
Symbol Parameter
Condition
Min
Typ
Max
Units
Single-Sided Frequency
Deviation(5)
10
250
kHz
VCO modulation
200
20
kbps
kbps
kHz
Maximum Bit Rate
Divider modulation
140
550
800
-43
-59
38.4kbps, β = 2, 20dBc
125kbps, β = 2, 20dBc
200kbps, β = 2, 20dBc
Occupied Bandwidth(5)
kHz
kHz
2nd Harmonic(5)
3rd Harmonic(5)
-36
-36
dBm
dBm
Spurious Emission in Restricted
Bands < 1GHz(5)
-54
dBm
Spurious Emission < 1GHz(5)
Spurious Emission > 1GHz(5)
Receive Section
-36
-30
dBm
dBm
All Functions on
12
10.3
9.8
LNA bypassed
Rx Current Consumption
mA
mA
Switch cap filter bypassed, LNA on
Both switch cap filter and LNA
bypassed
8
Rx Current Consumption Variation Over temperature
2
-113
-111
-107
-104
-101
-100
-97
2.4kbps, β = 16
4.8kbps, β = 16
19.2kbps, β = 4
Receiver Sensitivity (BER 10-3)
dBm
dBm
38.4kbps, β = 4
76.8kbps, β = 2
125kbps, β = 2
200kbps, β = 2
125kbps, 125kHz deviation, LNA on
+7
125kbps, 125kHz deviation, LNA
bypassed
Receiver Maximum Input Power
Receiver Sensitivity Tolerance
+12
20kbps, 40kHz deviation
Over temperature
+2
2
dB
dB
Over power supply range
1
Receiver Baseband Bandwidth
50
350
kHz
19.2kbps, β = 6, PF_FC[1:0] = 01,
fCUT = 133kHz
Co-Channel Rejection, BER = 10-3
-8
dB
Note:
5. Guaranteed by design.
Revision 2.2
October 2, 2013
8
Micrel, Inc.
MICRF507
Electrical Characteristics(4) (Continued)
fRF = 490MHz, fXTAL = 16MHz, MICRF507 Development Board, Modulation type = closed-loop VCO modulation, Sync_en bit = 1,
DD = 2.5V; TA = 25°C, the term “bit rate” refers to encoded bit rate throughout the EC table (see Figure 24), bold values indicate
V
–40°C< TA < +85°C, unless noted.
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Adjacent Channel Rejection, both
±500kHz spacing
53
dB
interferer and desired signal are
modulated at 19.2 kbps encoded
bit rate, β = 6, PF_FC[1:0] = 01,
fCUT = 133kHz, BER = 10-3
±1MHz spacing
58
dB
±1MHz
±2MHz
±5MHz
±10MHz
59
60
dB
dB
CW Blocking above desired
signal, desired signal is modulated
at 19.2kbps, β = 6, 3dB above
sensitivity, PF_FC[1:0] = 01,
47
dB
f
CUT = 133kHz, BER = 10-3
60
dB
P1dB
1dB Compression
Input IP3
-34
-25
-90
dBm
dBm
dBm
dBm
dBm
2 tones with 1MHz separation
LO Leakage
<1GHz
>1GHz
-57
-47
Spurious Emission(5)
Input Impedance with no matching
components
33+7j
Ω
RSSI Dynamic Range
50
0.9
2
dB
V
PIN = -110dBm
PIN = -60dBm
RSSI Output Range
V
Digital Inputs/Outputs
0.7*VDD
0
VDD
0.3*VDD
10
VIH
VIL
Logic Input High
V
V
Logic Input Low
Clock/Data Frequency(5)
Clock/Data Duty Cycle(5)
MHz
%
45
55
Revision 2.2
October 2, 2013
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Micrel, Inc.
MICRF507
Functional Description
Control (3-wire) Interface
General
The IO is an input for entry of starting addresses, the R/W
bit, and bytes being written to registers, and an output for
bytes read from registers.
The MICRF507 operation is controlled through a set of 8-
bit registers. The chip has a total of 23 readable registers
(addresses 0-22) of which 22 (addresses 0-21) are
writeable. Through this register set, the user can set the
MICRF507 in transmit or receive mode, program the
carrier frequency, and select a bit rate, among other
options.
CS enables transactions at the control interface, active
high. Transitions at the other two pins are ignored when
CS is low. This allows the MICRF507 to share SCLK and
IO with other devices as long as they have separate CS
lines.
Table 1 identifies all register bits. Table 26 gives more
detail and Table 27 shows the register fields grouped by
category, with don’t-care and mandatory bits omitted.
Some bits shown as ‘0’ or ‘1’ are mandatory bits and must
always be written with the values given. Other bits marked
as “-“ are “don’t care” bits.
To start a transaction (with SCLK and CS initially low),
bring CS high. To end a transaction (with SCLK low), bring
CS low.
To write a bit into IO (when IO is an input); first bring SCLK
high and drive IO with the bit level to be input (in either
order, or simultaneously). Then bring SCLK low.
Registers are accessed serially through the control
interface consisting of the CS, IO, and SCLK pins.
To read a bit out of IO (when IO is an output); first bring
SCLK high and read the level on IO. Then bring SCLK low
(in either order, or simultaneously).
Positive-going pulses at SCLK serve to clock bits in and
out of IO at a rate determined by the user. When IO is an
input, falling edges of SCLK strobe each bit in; when IO is
an output, each bit appears at IO after the rising edge of
SCLK.
The first byte to be clocked in during a transaction is made
of seven bits (MSB first) of register address followed by
the R/W bit, 0 for write, 1 for read. Then, one or more
bytes to be written to or read from registers are clocked in
or out respectively, always MSB first.
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MICRF507
Adr
Data Field
D3
A6…A0
D7
D6
D5
D4
D2
D1
D0
0000000 LNA_by
0000001 Modulation1
0000010 CP_HI
0000011 ‘1’
PA2
PA1
‘0’
PA0
Sync_en
RSSI_en
OUTS3
VCO_IB1
Mod_I3
Mod_A3
Mode1
LD_en
OUTS2
VCO_IB0
Mod_I2
Mod_A2
Mode0
PF_FC1
OUTS1
VCO_freq1
Mod_I1
Mod_A1
’1’
Modulation0
SC_by
‘1’
‘0’
PF_FC0
OUTS0
VCO_freq0
Mod_I0
Mod_A0
‘0’
PA_By
VCO_IB2
Mod_I4
‘1’
‘0’
0000100 Mod_F2
Mod_F1
-
Mod_F0
‘0’
0000101
0000110
-
-
Mod_clkS2
Mod_clkS1 Mod_clkS0 BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2
0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4 RefClk_K3
RefClk_K2
ScClk2
XCOtune2
A0_2
RefClk_K1
ScClk1
XCOtune1
A0_1
RefClk_K0
ScClk0
XCOtune0
A0_0
0001000 ‘1’
0001001 ‘0’
‘1’
‘0’
ScClk4
ScClk3
XCOtune3
A0_3
‘0’
‘1’
XCOtune4
0001010
0001011
-
-
-
A0_5
A0_4
-
-
-
N0_11
N0_3
N0_10
N0_2
N0_9
N0_8
0001100 N0_7
0001101
0001110 M0_7
N0_6
N0_5
N0_4
N0_1
N0_0
-
-
-
-
M0_11
M0_3
M0_10
M0_2
M0_9
M0_8
M0_6
M0_5
A1_5
-
M0_4
A1_4
-
M0_1
M0_0
0001111
0010000
-
-
-
A1_3
A1_2
A1_1
A1_0
-
N1_11
N1_3
N1_10
N1_2
N1_9
N1_8
0010001 N1_7
0010010
N1_6
N1_5
-
N1_4
-
N1_1
N1_0
-
-
M1_11
M1_3
M1_10
M1_2
M1_9
M1_8
0010011 M1_7
0010100 ‘1’
M1_6
‘0’
M1_5
‘1’
M1_4
‘0’
M1_1
M1_0
‘0’
‘0’
‘1’
‘1’
0010101
-
-
-
-
FEEC_3
FEE_3
FEEC_2
FEE_2
FEEC_1
FEE_1
FEEC_0
FEE_0
0010110 FEE_7
FEE_6
FEE_5
FEE_4
Names of programming bits. Unused bits (“-“) and mandatory bits (“1” or “0”) are shown. Changes to mandatory bits may cause
malfunction.
Table 1. Control Registers
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MICRF507
Writing
This method is used to write either to one register (see
Figure 1), or any number of registers with consecutive
addresses up to all 22 writeable registers (see Figure 2) in
a single transaction.
•
•
Clock in one or more bytes, MSB of each byte
first.
Bring CS low to end the transaction.
Bits passing through IO are clocked serially into pre-
buffers, then transferred in parallel to the actual registers
upon de-assertion of CS.
Procedure:
•
Bring CS active (high). IO is initially an input (and
remains so for the duration of the transaction).
•
Clock in a byte consisting of the address bits and
the R/W bit. The first seven bits are the address
(starting with MSB) of the register, or the first
register if more than one, to be written. The eighth
bit is the R/W bit, which is 0 as this is a write
operation.
Figure 1. Writing a Byte into a Register
Figure 2. Writing Bytes into n+1 Registers at Consecutive Addresses Starting with Address i
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MICRF507
Reading
•
•
Clock out 8 bits per register (one or more) to be
read through IO, MSB first. Rising edges of SCLK
bring each bit to IO. The user can then
conveniently sample the bit at the next falling edge
of SCLK.
Any number of registers with consecutive addresses, from
one up to all 23, can be read.
Procedure:
•
•
Bring CS active (high). IO is initially an input.
Bring CS low to end the transaction. IO reverts to
being an input.
Clock in a byte consisting of the address bits and
the R/W bit. The first seven bits are the address
(starting with MSB) of the register, or the first
register if more than one, to be read. The eighth
bit is the R/W bit, which is 1 as this is a read
operation. After the R/W bit is clocked in (falling
edge of SCLK), the next rising edge on SCLK will
enable IO as an output for the duration of the
transaction.
Figure 3 shows how to read one register. To read more
registers at consecutive addresses, continue pulsing SCLK
eight times for each register to be read before de-asserting
CS.
Figure 3. Reading a Byte from a Register
Figure 4. Definitions of Control Interface Timing Parameters
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MICRF507
Control Interface Timing
Power-on Reset
Figure 4 and Table 2 give the timing specifications for the
control interface.
The power-on reset time (tPOR), given in Table 2, is defined
as the time from application of supply voltage to
completion of power on reset.
When in Receive or Transmit mode (but not Power-down
or Standby mode), an additional timing constraint applies:
elapsed time between falling edges of CS must be a
minimum of 2/fc, where fc is the synthesizer’s comparison
To determine when the chip has completed its power-on
without waiting for the worst-case time (maximum tPOR), do
the following:
frequency (also called phase detector frequency). fc
fXCO/M,
=
•
Write hex 03 (binary 00000011) to Register 0.
This puts the chip in Standby mode.
fXCO
fc =
•
Read Register 0. If the value read is binary
00000011, then exit; power-on is complete. If not,
go to previous step and repeat.
M
2M
Because registers are initially in an unknown state after
power-on (exception: Mode[1:0] initializes to 00), always
enter a complete set of register values as the first
transaction, and always enter only nonzero values for N
and M.
min time =
fXCO
where M = M0 when receiving or transmitting with VCO
modulation, and M = max{M0, M1} when transmitting with
divider modulation.
Values
Units
Symbol
Parameter
Min.
Typ. Max.
Min. high time of
SCLK
Thigh
20
ns
Min. low time of
SCLK
T
low
20
ns
tfall
Fall time of SCLK
Rise time of SCLK
1
1
µs
µs
trise
Time from rising
edge of CS to
falling edge of
SCLK
Tcsr
50
25
ns
ns
Min. delay from
rising edge of CS
to rising edge of
SCLK
Tcsf
Min. delay from
valid IO to falling
edge of SCLK
during a write
operation
Twrite
20
75
ns
Min. delay from
rising edge of
SCLK to valid IO
during a read
operation
Figure 5. Power-On Programming Flowchart
Tread
ns
(assuming load
capacitance of IO
is 25pF)
9
Power on Reset
time
tPOR
4.6
ms
Table 1. Control Interface Timing
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Clock Generation
The MICRF507’s crystal oscillator:
Figure 6 shows the oscillator with its frequency-shifting
capacitor bank (controlled by the register field XCOtune)
and the frequency dividers that derive the latter three
clocks from its output. This division occurs in two stages.
First, the XCO output is divided by the 6-bit field Refclk_K,
which has allowable values between 1 and 63. Then, for
each of the three clocks, another field (BitSync_clkS,
BitRate_ClkS, and ModClkS, respectively) selects the
number of further divisions by 2. Complete relationships of
field values and resultant frequencies are given below for
each clock.
•
•
•
Serves as the reference for the synthesizer that is
the carrier and local oscillator source.
Is divided down to clock the switched-capacitor IF
filter.
Is divided down to generate three other clocks: bit
rate clock, bit synchronization clock, and
modulator clock
Number Location
Field Name
Description
of bits
of bits
XCOtune
RefClk_K
5
6
Reg9[4:0]
Reg7[5:0]
Crystal oscillator trimming.
Reference clock divider.
Reg6[0],
Reg7[7:6]
Transmitter Bit rate clock setting. See Figure 9 and “Data
Interface and Bit Synchronization” section for more details.
BitRate_clkS
Mod_clkS
3
3
VCO Modulator clock setting, set the modulator clock to
either 8x or 16x the bit rate clock.
Reg6[6:4]
Reg6[3:1]
Receiver Bit Synchronization clock setting, always set bit
synchronization clock to 16x the bit rate clock. See Figure 9
and “Data Interface and Bit Synchronization” section for more
details.
BitSync_clkS
3
Table 3. Register Bit Fields for Clock Generation
Figure 6. MICRF507 Clock Sources
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To achieve 9pF load capacitance required to center
TN4-26011 at 16MHz, set the external capacitors to
1.5pF and XCOtune=16dec. Figure 8 shows the tuning
range for two different capacitor values, 1.5pF and zero
(external capacitors omitted). External capacitor values
will strongly affect the tuning range. Using 1.5pF with the
above crystal gives a tuning range that is approximately
symmetrical about the center frequency.
Crystal Oscillator (XCO)
The crystal oscillator’s role as the synthesizer reference
demands very good phase and frequency stability. As
shown in Figure 7, the external components required for
the oscillator are a crystal, connected between pins 23
and 24, and loading capacitors.
Pin 24
XtalOut
Y1
Pin 23
XtalIn
TN4-26011
C8
1.5pF
C9
1.5pF
Figure 7. Crystal Oscillator Circuit
The load capacitance CL seen between the crystal
terminals is:
1
Figure 8. XCO Tuning with the XCOtune Field
CL =
+ CXCOtune + Cpin
1
1
+
C8 C9
The start-up time of the cystal oscillator, given in Table
4, is about a millisecond and increases with capacitance.
When the MICRF507’s main mode is switched from
Power down mode to Transmit mode via Standby mode,
or to Receive mode via Standby mode, only the XCO is
energized at first. Current consumption during this
prestart period is approximately 280μA (the same as for
Standby mode). After the XCO amplitude is sufficient to
trigger the M-counter and produce two pulses at its
output, the remaining circuits on the chip are powered
on.
Where CXCOtune is the capacitance of the internal
adjustable capacitor bank, and Cpin is defined as the
internal chip capacitance when XCOtune bits are all
zeros, plus PCB stray capacitance across pins 23 and
24. The value of Cpin is about 6pF. The loading capacitor
values required depend on the total CL specified for the
crystal for oscillation at the desired frequency.
It is possible to tune the crystal oscillator internally by
giving the 5-bit register field XCOtune a non-zero value,
which causes internal capacitors to be switched across
the crystal. As this capacitance increases, frequency
decreases. When XCOtune is set to its maximum value
of 31, approximately 4.5pF additional capacitance is
connected across the crystal pins.
XCOtune
Start-up Time (µs)
0
1
590
590
The XCO tuning can be used to cancel crystal resonant
frequency error, both initial and with temperature. It can
be used in combination with the Frequency Error
Estimator (FEE). See “FEE” section.
2
700
4
700
8
810
The crystal used is a TN4-26011 from Toyocom.
Specification:
16
31
1140
2050
•
•
•
•
Package TSX-10A,
Table 4. Typical Crystal Oscillator Start-up Time
with C8 = C9 = 1.5pF
Nominal frequency 16.000000MHz
Frequency tolerance ±10ppm
Frequency stability ±9ppm, load capacitance
9pF
•
Pulling sensitivity 15ppm/pF
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An external reference clock, when used instead of a
crystal, should be applied to pin 24 (XTALOUT) with pin
23 (XTALIN) not connected. To maintain proper DC
biasing within the chip, use AC-coupling between the
external reference and the XTALOUT-pin.
The modulator clock is used if VCO modulation method
is selected. Set the modulator clock frequency to either
8x or 16x the bit rate. See “VCO Modulation and the
Modulator” subsection for more information.
BitRate_clkS[2:0]
BITSYNC_CLK (Receiver Bit Synchronization Clock)
Corresponding Clock
Frequency
BitSync_clkS[2:0]
The frequency of the bit synchronization clock
(fXCO is crystal frequency)
fBITSYNC_CLK
,
is a function of the crystal oscillator
Mod_clkS[2:0]
frequency fXCO and the values of the register fields
Refclk_K and BitSync_clkS:
000
001
010
011
100
101
110
111
fXCO/(128xRefClk_K)
fXCO/(64xRefClk_K)
fXCO/(32xRefClk_K)
fXCO/(16xRefClk_K)
fXCO/(8xRefClk_K)
fXCO/(4xRefClk_K)
fXCO/(2xRefClk_K) (*)
fXCO /RefClk_K (*)
fXCO
fBITSYNC_CLK
=
Refclk_K ×2(7-BitSync_clkS)
The bit synchronizer uses a clock that needs to be
programmed to 16 times the actual bit rate. As an
example, a bit rate of 20kbps needs a bit synchronizer
clock with frequency of 320kHz. Refer to Figure 9 and
“Data Interface and Bit Synchronization” section for more
details.
(*) Can not be used as BitRate_clk.
BITRATE_CLK (Transmitter Bit Rate Clock)
Table 5. Generation of Bitrate_clk, BitSync_clk
and Mod_clk
The frequency fBITRATE_CLK of BITRATE_CLK is a function
of the crystal oscillator frequency fXCO and the values of
the register fields Refclk_K and BitRate_clkS:
Data Interface and Bit Synchronization
fXCO
fBITRATE_CLK
=
Transmitted and received data bits are coupled to the
MICRF507 serially through the Data Interface. This Data
Interface consists of the DATAIXO and DATACLK pins.
This is a separate interface from the Control Interface
(CS, IO, and SCLK), for which see Control (3-wire)
Interface.
Refclk_K × 2(7-BitRate_clkS)
In transmit mode, when Sync_en = 1, BITRATE_CLK
appears on the DATACLK pin. Its frequency is equal to
the bit rate. Example; a bit rate of 20 kbit/sec requires an
fBITRATE_CLK of 20kHz. Refer to Figure 9 and the “Data
Interface and Bit Synchronization” subsection for more
details.
Figure 9 shows the data interface circuitry aboard the
MICRF507. DATAIXO is an input during transmission,
whereas during reception a driver is enabled and it
becomes an output. DATACLK is always an output.
MODULATOR_CLK (VCO Modulator Clock)
A rule that applies when using VCO modulation is: after
commanding the MICRF507 to enter transmit mode, the
microcontroller shall tri-state the driver connected to
DATAIXO to leave that pin floating until the
microcontroller begins sending data. See “Mode
Transitions” section for more details.
The frequency fMOD_CLK of MODULATOR_CLK is a
function of the crystal oscillator frequency fXCO and the
values of the register fields Refclk_K and Mod_clkS:
fXCO
fMOD_CLK
=
Refclk_K ×2(7-Mod_clkS)
The data interface can be programmed for synchronous
and non-synchronous operation according to the setting
of the Sync_en bit; see Table 7.
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Number Location
Reference
Description
Field Name
of bits
of bits
Sync_en
1
Reg0[3]
Synchronizer Mode bit
Table 7
Table 6. Register Bit Fields for Data Interface and Bit Synchronization
Sync_en
State
Comments
RX: Bit
0
0
synchronization off
Transparent reception of data
TX: DataClk pin off
Transparent transmission of data
RX: Bit
1
1
synchronization on
Bit clock is generated by transceiver
Bit clock is generated by transceiver
TX: DataClk pin on
Table 7. Synchronizer Mode Bit
DATAIXO
19
RECEIVE
DATA PATH
TRANSMIT
DATA PATH
RECEIVE
MODE
Sync_en = 0
TO
TRANSMITTER
Sync_en = 1
ENABLE
Sync_en = 0
Sync_en = 1
D
Q
D
Q
TRANSMIT
BITRATE_CLK
18
RECEIVE
Sync_en
DATACLK
Filter &
data slicer
FROM
Bit
Sync
DEMOD
RECOVERED
CLOCK
BITSYNC_CLK
Figure 9. Data Interface and Synchronization
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Mode
Sync_en
DATACLK
Signal
DATAIXO
Direction
Direction
Signal/Function
Input
Modulates carrier directly
(asynchronously)
0
Output
0
Transmit
Receive
Input
Sampled at rising edge of BitRate
clock; latched output modulates
carrier
1
0
1
Output
Output
Output
BitRate clock
0
Output
Output
Raw output from demodulator
Filtered and latched demodulator
output; transitions occur at rising
edge of DATACLK
Clock recovered by bit
synchronizer
Table 8. Synchronizer Mode and Data Interface
In sync mode (Sync_en bit set to 1), the transmitted bit
stream is clocked with the precision of the MICRF507’s
crystal oscillator, which relaxes timing accuracy
requirements on the data source. During reception, the
synchronizer ensures that transitions of DATAIXO occur
only at rising edges of DATACLK, without edge jitter or
internal glitches. Receiver sensitivity values given in the
Electrical Characteristics table are measured with Sync_en
= 1; with Sync_en = 0, as much as 3-6 dB of sensitivity
could be lost.
recovered clock. DATAIXO (an output during reception)
brings out the synchronized data stream, which has its
transitions at rising edges of DATACLK. See Figure 11.
Figure 11. Data Interface in Receive Mode
By being in control of bit timing, the MICRF507 is
effectively the “master.” For maximum timing margin, the
microcontroller, as the “slave,” can present or sample
(during transmit and receive, respectively) each new bit at
the DATAIXO pin at falling edges of DATACLK.
Sync_en = 0
When Sync_en = 0, the input signal at DATAIXO
modulates the transmitter directly during transmission and
the output signal from DATAIXO is the raw demodulator
output. DATACLK remains fixed at a logic low level during
both transmission and reception.
Additional Considerations in the Use of Synchronizer
(Sync_en = 1)
Sync_en = 1
Two clock signals, BITRATE_CLK and BITSYNC_CLK,
must be properly programmed when using the
synchronizer. BITRATE_CLK, used in transmission, must
During transmission when Sync_en = 1 the data bit stream
entering DATAIXO is buffered with a flip-flop strobed at the
rising edge of BITRATE_CLK, and the output of the flip-
flop modulates the transmitter. BITRATE_CLK is brought
out at the DATACLK output. Figure 10 shows the
relationship of DATACLK and DATAIXO transitions.
be set to
a
frequency equal to the bit rate.
BITSYNC_CLK, used in reception, must have a frequency
16 times the bit rate. These frequencies are controlled by
the crystal oscillator frequency and the settings of register
fields, as described in the “Clock Generation” section. Bit
clocking of the incoming signal must agree with the
receiver’s local clocking within ±2.5% (easily met with 100
PPM or better crystals). For example, if fBITSYNC_CLK is
16x19.231kbps, the incoming bit rate can be between
0.975x19.231kbps to 1.025x19.231kbps.
All incoming messages must start with a 0101… preamble
so that the synchronizer can acquire the incoming clock. A
24-bit preamble is typically used; a minimum of 22 bits is
required.
Figure 10. Data Interface in Transmit Mode
During reception, the bit synchronizer recovers the
received signal’s clock. This recovered clock strobes a flip-
flop that samples in mid-bit-period the demodulated and
filtered bit stream. The DATACLK output brings out the
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Frequency Synthesizer
The MICRF507 frequency synthesizer is an integer-N
phase-locked loop consisting of:
after filtering, controls the VCO, closing the loop and forcing
the error between the reference frequency and the divided
VCO frequency to zero.
•
a reference source, made of an M-divider
clocked by the crystal oscillator
The block diagram, Figure 12, shows the basic elements and
arrangement of a PLL-based frequency synthesizer. The
MICRF507 has a dual modulus prescaler for increased
frequency resolution. In a dual modulus prescaler the main
divider is split into two parts, the main part N and an
additional divider A, where A < N. Both dividers are clocked
from the output of the dual-modulus prescaler, but only the
output of the N divider is fed into the phase detector. The
prescaler will first divide by 16. Both N and A count down
until A reaches zero, at which point the prescaler is switched
to a division ratio 16+1. At this point, the divider N has
completed A counts. Counting continues until N reaches
zero, which is an additional N-A counts. At this point, the
cycle repeats.
•
•
a voltage controlled oscillator (VCO)
a programmable frequency divider made of an
N-divider, an A-divider, and a dual modulus
prescaler
•
a phase/frequency detector
The loop filter is external for flexibility and can be a
simple passive circuit.
The phase/frequency detector compares the reference
frequency (from the M-divider) with the VCO output fed
through the programmable frequency divider. The
charge pump output of the phase/frequency detector,
Number
of bits
Description
Field Name
Location of bits
Reg13[3:0],
Reg14[7:0]
M0 counter
A0 counter
N0 counter
M0
A0
12
6
Reg10[5:0]
Reg11[3:0],
Reg12[7:0]
N0
12
Reg18[3:0],
Reg19[7:0]
M1 counter
A1 counter
N1 counter
M1
A1
12
6
Reg15[5:0]
Reg16[3:0],
Reg17[7:0]
N1
12
1
CP_HI
VCO_Freq
VCO_IB
LD_en
Reg2[7]
Reg3[1:0]
Reg3[4:2]
Reg1[2]
High charge pump current (1= 500μA, 0 = 125µA)
Frequency setting of VCO (see Table 11)
VCO bias current setting (see Table 11)
Lock detect function on/off
2
3
1
Table 9. Register Bit Fields for Frequency Synthesizer
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Loop filter
Downconverter
VCO
A-Divider
Prescaler
N-Divider
Charge pump
Div 2
Div 2
Phase
detector
PA
M-Divider
XCO
Figure 12. PLL Block Diagram
A6…A0
D7
D6
D5
A0_5
-
D4
A0_4
-
D3
D2
D1
D0
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
-
-
A0_3
A0_2
A0_1
N0_9
N0_1
M0_9
M0_1
A1_1
N1_9
N1_1
M1_9
M1_1
A0_0
-
-
N0_11
N0_3
M0_11
M0_3
A1_3
N0_10
N0_2
M0_10
M0_2
A1_2
N0_8
N0_0
M0_8
M0_0
A1_0
N1_8
N1_0
M1_8
M1_0
N0_7
N0_6
N0_5
-
N0_4
-
-
-
M0_7
M0_6
M0_5
A1_5
-
M0_4
A1_4
-
-
-
-
-
N1_11
N1_3
M1_11
M1_3
N1_10
N1_2
M1_10
M1_2
N1_7
-
N1_6
-
N1_5
-
N1_4
-
M1_7
M1_6
M1_5
M1_4
Table 10. Register Bit Fields for PLL
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N, M, and A are numbers of length 12, 12 and 6 bits,
respectively The synthesizer’s output frequency can be
calculated from the following equation:
The input capacitance at the varactor pin must be taken
into consideration when designing the PLL loop filter. This
is most critical when designing a loop filter with high
bandwidth, which gives relatively small component values.
The input capacitance is approximately 6pF.
fXCO
M
fVCO
16×N + A
M≠0
fRF × 2
16×N + A
fPD
=
=
=
(
)
× 2
(
)
RF Frequency vs Varactor Input Voltage
1 ≤ A ≤ 16
540
530
520
510
16×N + A
fRF = fXCO
11
2M
500
490
10
01
where
480
470
460
450
fPD: Phase detector comparison frequency
fXCO: Crystal oscillator frequency
0
0.4
0.8
1.2
1.6
2
2.4
fVCO: Voltage controlled oscillator frequency
fRF: RF carrier frequency
VARIN Voltage (V)
Figure 13. RF Frequency vs. Varactor Voltage
and VCO_ Freq bits (VDD = 2.5V)
The MICRF507 has two sets of register fields controlling
the synthesizer’s frequency multiplication ratio; A0/N0/M0
and A1/N1/M1. During transmission using divider
modulation (see “Divider Modulation” section), bit values of
‘0’ and ‘1’ respectively select the 0 and 1 register field set.
During reception and during transmission using VCO
modulation, only the 0 set is used.
Charge Pump
The charge pump current can be set to either 125µA or
500µA by CP_HI (‘1’ → 500µA). This will affect the loop
gain and, consequently, filter component values. For
applications using high phase detector frequency and high
PLL bandwidth, use 500µA charge pump current.
VCO
PLL Filter
The VCO has no external components.
The three-bit field VCO_IB controls VCO bias current to
optimize phase noise. The two bit field VCO_freq controls
a capacitor bank which determines the VCO frequency
range. These five bits are set according to the RF
frequency as follows:
The design of the PLL filter strongly affects the
performance of the frequency synthesizer. Key parameters
in PLL filter design are loop bandwidth, the modulation
method (VCO modulation or divider modulation) and the
bit rate. Filter design also affect the switching time
(important when frequency hopping) and phase noise.
Divider modulation requires the PLL to lock on a new
carrier frequency for every new data bit. As a rule of
thumb, the PLL loop bandwidth should be at least twice as
high as the bit rate. In such cases it is recommended to
use a third order filter to suppress the phase detector
frequency.
RF
VCO_IB2 VCO_IB1 VCO_IB0 VCO_freq1 VCO_freq0
Freq
470-
482MHz
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
482-
497MHz
For VCO modulation, the PLL loop bandwidth should be
less than 1/10 of the bit rate. If the loop bandwidth is high
relative to the bit rate, the PLL will keep the VCO at a fixed
frequency, preventing it from being modulated.
497-
510MHz
Table 11. VCO Bit Setting
The recommended third-order loop filter (made with
external components) is shown in Figure 14. When R2=0
and C3 is omitted, this reduces to a second-order loop
filter.
The tuning range, the RF frequency versus VCO tune
voltage (varactor input, pin 29), depends on the VCO
frequency setting as shown in as shown in Figure 13.
When the tuning voltage is in the range from 0.9V to 1.4V,
the VCO gain (as seen by the PLL) is at its maximum,
approximately 64 to 70MHz/V. Note that the RF frequency
is half of the PLL frequency. It is recommended that the
VCO tune voltage stays in this range.
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Lock Detect
A lock detector can be enabled by setting LD_en = 1.
When pin LD is high, it indicates that the PLL is in lock.
After a control word is loaded LD will (typically) go low,
then high again when the synthesizer has locked. LD also
goes low initially when the PA (power amplifier) is turning
on.
After the transceiver has been put into Receive or
Transmit mode, or after the power amplifier has been
turned on, a low-to-high transition at LD can serve as an
indicator that the synthesizer frequency has stabilized.
Figure 14. Second and Third Order Loop Filter
Table 12 shows three different loop filter designs, the first
two for VCO modulation and the last one for modulation
using the internal dividers. The component values are
calculated with RF frequency = 490MHz, VCO gain =
67MHz/V as seen by the PLL, and desired phase margin =
56º. Other settings are shown in the table. The VARIN pin
capacitance (pin 29) of 6pF can be neglected for the two
filters with lowest bandwidth (which have R2=0 and
relatively large values of C1). For other loop bandwidth
and phase detector values, use the loop filter calculation
tool in RF Testbench software available on Micrel’s
website.
Encoded
Bit Rate
(kbps)
PLL Charge
Phase
Detector
Freq. (kHz)
BW
Pump
C1
C2
R1
R2
C3
(kHz)
(μA)
VCO
>8
0.8
3.2
13
125
125
500
100
100
500
10nF
680pF
390pF
100nF
6.8nF
8.2nF
6.2kΩ
22kΩ
5kΩ
0
0
NC
NC
VCO
>32
<6.5
Divider
68kΩ
18pF
Table 12. Loop Filter Component Values
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Receiver
Number Location
Description
Reference
Field Name
of bits
of bits
Reg0[7]
Reg1[1:0]
Reg2[6]
Reg8[4:0]
Reg1[3]
By_LNA
PF_FC
SC_by
ScClk
1
2
1
5
1
4
8
LNA bypass on/off
Pre-filter corner frequency
Bypass of switched capacitor filter on/off
Switched Cap clock divider
RSSI function on/off
Table 14
Table 15
RSSI_en
FEEC
Reg21[3:0] FEE control bits
FEE
Reg22[7:0] FEE value (read only)
Table 13. Register Bit Fields for Receiver
The receiver is a zero intermediate frequency (ZIF) type
employing low-power, fully integrated low-pass filters.
available at pins IchOut and QchOut. The output
impedance of each mixer is about 8kΩ.
A low noise amplifier (LNA) drives a quadrature mixer pair.
The mixer outputs feed two identical signal channels.
Each channel’s signal path has a pre-amplifier, a third
order Sallen-Key RC low-pass pre-filter, a six-pole
switched-capacitor filter (which determines actual
selectivity), and finally a limiter.
The limiter outputs then enter a demodulator which detects
the relative phase of the baseband I and Q signals. If the I
channel signal lags the Q channel, the FSK tone frequency
lies above the LO frequency (data ‘1’). If the I channel
leads the Q channel, then the FSK tone lies below the LO
frequency (data ‘0’). The output of the demodulator is
available on the DATAIXO pin; in either raw form or
latched with the recovered clock according to the setting of
Sync_en bit. An RSSI (receive signal strength indicator)
circuit indicates the received signal level.
Front End
The MICRF507’s low-noise amplifier boosts the incoming
signal prior to frequency conversion in order to prevent
mixer noise from degrading overall front-end noise
performance. The LNA is a two-stage amplifier and has a
nominal gain of approximately 23dB at 490MHz. The front
end has a gain of about 31dB to34dB. The gain varies by
1-1.5dB over a 2.0V to 2.5V variation in power supply.
MARKER MHz
RESISTANCE REACTANCE
The LNA can be bypassed by setting bit LNA_by to ‘1’.
This can be useful for very strong input signal levels. The
front-end gain with the LNA bypassed is about 12dB. The
mixers have about 10dB of gain at 490MHz. With
appropriate setting of the OUTS field (register 2, bits D3 to
D0), the differential outputs of the mixers can be made
1
2
3
470
490
510
32.4Ω
33.4Ω
34.4Ω
7.9Ω
7.4Ω
6.4Ω
Figure 15. LNA Input Impedance
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MICRF507
The front end’s input impedance, with no matching
network, is close to 50Ω as shown in Figure 15. This gives
an input reflection coefficient of about -13dB. Although the
receiver does not require a matching network to optimize
the gain, a matching network is recommended for
harmonic suppression during transmission and for
improved selectivity in reception.
The pre-filter and switched-capacitor filters in cascade
must pass the full IF bandwidth of the received signal. In a
zero-IF receiver such as the MICRF507 this bandwidth is
as follows:
rb
fBW = fOFFSET + fDEV
+
2
where
Sallen-Key Filters
fBW: Needed receiver bandwidth; fCUT above should
not be smaller than fBW [Hz]
Each IF channel includes a pre-amplifier and a pre-filter.
The preamplifier has a gain of 22dB. The IF amplifier also
removes DC offset. Gain varies by less than 0.5dB over a
2.0V to 2.5V variation in power supply.
fOFFSET: Total frequency offset between receiver and
transmitter [Hz]
fDEV: Single-sided frequency deviation [Hz]
rb: The bit rate in bits/sec
The pre-filter is implemented as a three-pole Sallen-Key
low-pass filter. It protects the switched-capacitor filter that
follows it from strong adjacent channel signals and also
serves as an anti-aliasing filter. It is programmable to four
different cut-off frequencies as shown in Table 14.
RSSI
PF_FC1
PF_FC0
Cutoff (3dB filter corner)
0
0
1
1
0
1
0
1
100kHz
150kHz
230kHz
340kHz
Table 14. Pre-Filter Bit Field
Switched Capacitor Filter
The main IF channel filter is a switched-capacitor
implementation of a six-pole elliptic low pass filter. This
meets selectivity and dynamic range requirements with
minimum total capacitance. The cut-off frequency of the
switched-capacitor filter is adjustable by changing the
clock frequency.
Figure 16. RSSI Voltage
A 6-bit frequency divider, programmed by the ScClk[5:0]
field, is clocked by the crystal oscillator. Its output, which is
20 times the filter’s cutoff frequency, is then divided by 4 to
generate the correct non-overlapping clock phases needed
by the filter. The cut-off frequency of the filter is given by:
fXCO
Figure 17. RSSI Network
fCUT
=
40⋅ScClk
fCUT: Filter cutoff frequency
Figure 16 shows a typical plot of the RSSI voltage as a
function of input power. The RSSI termination network is
shown in Figure 17. The RSSI has a dynamic range of
about 50dB from about -110dBm to -60dBm input power.
fXCO: Crystal oscillator frequency
ScClk: Switched capacitor filter clock, bits ScClk[4:0]
(bit 0 has a mandatory value of ‘0’).
When an RF signal is received, the RSSI output increases
and can serve as a signal presence indicator. It could be
used to wake up external circuitry that conserves battery
life while in a sleep mode. Note that RSSI only functions in
Receive mode.
For instance, for a crystal frequency of 16MHz and if the 6
bit divider divides the input frequency by 4, the cut-off
frequency of the SC filter is 16MHz/(40 x 4) = 100kHz. A
first-order RC low-pass filter removes clock frequency
components from the signal at the switched-capacitor filter
output.
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Another use for RSSI is to determine that transmit power
can be reduced in a system. If the RSSI detects a strong
signal, the transmitter could be alerted to reduce its
transmit power and so reduce current consumption.
The result of the measurement, read from the FEE register
at address 22 (16 hex, 0010110 binary), is actually an
eight-bit two’s complement signed number, which can
have values from -128 to 127. Reading FEE gives the
most recently transferred value. The raw FEE value,
treated as an unsigned number ranging from 0 to 255, can
be converted into a signed integer as follows:
FEE
The Frequency Error Estimator (FEE) counts pulses from
inside the demodulator to measure the frequency offset
between it’s receive frequency and the transmitter’s
frequency. The maximum offset that FEE can correctly
report a frequency difference is about ±20ppm. The output
of the FEE can be used to tune the XCO frequency, both
for production calibration and to compensate for crystal
temperature drift and aging.
If FEE < 128 then {FEESIGNED = FEE}
Else {FEESIGNED = (FEE - 256)},
For a straightforward measurement of frequency offset, the
incoming signal has to have an equal number of ones and
zeros, such as a 1010… preamble. The frequency offset
can then be calculated:
The FEE is enabled when FEEC[1:0] = 11, and is off when
FEEC[1:0] = 00 (do not use other values). It has two
counters. One counter determines the measurement
period by generating a trigger every time it has counted up
the number of bit periods selected by the setting of
FEEC[3:2] as given in Table 15. A second counter
accumulates the net tally of UP and DN pulses from the
demodulator. For each incoming ‘1’ bit, UP carries an
average number of pulses that is twice the modulation
index (β), and likewise for each incoming ‘0’ bit and DN.
The trigger transfers the contents of the second counter to
the FEE register and clears it, after which it begins
accumulating again.
rb
fOFFSET
=
FEESIGNED
4P
where FEE is the value read from the FEE register (treated
as a signed number), P is the number of data bits over
which the count is taken, and rb is the bit rate. When
fOFFSET is zero, the transmitter and receiver are perfectly
aligned. A positive fOFFSET means that the received signal
has a higher frequency than the carrier frequency to which
the receiver is tuned. To compensate for this, the
receiver’s XCO frequency should be increased by reducing
XCO_tune bits as detailed in the “Crystal Oscillator (XCO)”
section.
FEEC_1
FEEC_0 FEE Mode
Counting a larger number of symbols (higher P) improves
the accuracy of the measurement. Beware, however, of
overflow, which can cause the FEE value to jump from
+127 to -128 after only one excessive count.
0
0
1
0
1
0
Off
Do not use
Do not use
If the frequency offset is too large for the chosen P, then P
must be reduced. P = 8 or P = 16 is safest.
Counting UP and DN pulses. UP
increments the counter, DN
decrements it.
1
1
No. of bits used for the
measurement
FEEC_3
FEEC_2
0
0
1
1
0
1
0
1
8
16
Do not use
Do not use
Table 15. FEEC (Frequency Error Estimator Control) Bits
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XCOtune Procedure Example
Registers properly set for reception;
LOOP:
A procedure such as the algorithm given below can be
called during production (storing the calibrated XCO_tune
value), at regular intervals, or implemented in the
communication protocol when the frequency has changed.
The MICRF507 measures the frequency offset between
the demodulated signal and the LO, and a micro-controller
programs the XCO_tune bits to tune the XCO so the LO
frequency is equal to received carrier frequency.
XCO_Step = XCO_Step/2;
If (XCO_Sign == POS) then
// If POS then increase LO frequency:
{XCO_present = XCO_present - XCO_Step}
Else
Procedure description: A transmitter is assumed to be
sending a 1010… pattern at the correct frequency and bit
rate. The FEE is enabled (FEEC[1:0] = 11) and the
number P of bit periods used in the measurement is 8 or
16. Only the sign of FEE is used.
// If NEG then decrease LO frequency:
{XCO_present = XCO_present + XCO_Step}
;
XCO_tune_bits = XCO_Present;
ProgramRFChip;
Objective: The best XCO_tune value (giving the lowest
IFEEI). The desired frequency of the receiver’s PLL is
midway between the “0” and “1” frequencies.
Wait for > P bit periods;
Local variables:
XCO_Present: (5-bit) holds current value in XCO_tune
field
Read FEE;
If (FEE > 0?) then
XCO_Step: (4-bit) holds amount by which XCO_tune will
be incremented or decremented
{XCO_Sign = POS}
else
XCO_Sign: (1 bit) has a value of either POS or NEG,
determining respectively whether XCOtune is to be
incremented or decremented (reducing XCOtune
increases LO frequency)
{XCO_Sign = NEG} // negative or 0
;
If (XCO_Step > 1) then
{Branch to LOOP}
XCO_tune_bits is a buffer, which is written to the XCOtune
field when ProgramRFChip is called.
Else
{If(XCO_Sign == POS) then
XCO TUNE PROCEDURE
Initialization:
{XCO_Present = XCO_Present – 1;
Return (XCO_Present)}; \\ done
XCO_Present = 16;
XCO_Step = 16;
}
;
XCO_Sign = NEG;
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Transmitter
Power Amplifier
The maximum output power of the power amplifier (PA) is
approximately 10dBm with a 50Ω load. For maximum
output power, the load seen by the PA must be resistive.
Higher output power can be obtained by decreasing the
load impedance, but this will conflict with impedance
matching to the LNA.
Setting PA_by=1 causes the PA to be bypassed and
output power to drop by ~22dB. It is still possible to control
the power with PA[2:0] bits.
The LC filter shown in Figure 18 reduces harmonic
emission when placed between the ANT pin and antenna.
The output power is programmable in seven levels by
means of the PA[2:0] field, with approximately 2.5dB
between steps; see Table 17. The power amplifier is
turned off when PA[2:0] = 000. Otherwise the PA is on and
output power increases with the value of the PA[2:0] field
and is maximum when PA[2:0] = 111.
Number Location
Description
Reference
Field Name
Modulation
Mod_I
of bits
of bits
2
5
4
3
3
1
Reg1[7:6]
Reg4[4:0]
Reg5[3:0]
Reg4[7:5]
Reg0[6:4]
Reg2[4]
Modulation selection
Table 18
Modulator current setting
Modulator attenuator setting
Modulator filter setting
Power amplifier level
Mod_A
Mod_F
PA
Table 17
Table 17
PA_by
Bypass of PA stage on/off
Table 16. Register Bit Fields for Transmitter and VCO Modulation
PA2
PA1
0
PA0
0
State (approximate attenuation)
PA off
0
0
0
1
15dB attenuation
12.5dB attenuation
10dB attenuation
7.5dB attenuation
5dB attenuation
2.5dB attenuation
Max output
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PA_By
0
1
Power Amplifier Enabled
Power Amplifier bypassed, approx 20dB reduced output power.
Table 17. Register Bit Fields for Power Amplifier
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Modulation1 Modulation0 State
C5
39pF
L1
12nH
0
0
1
1
0
1
0
1
Closed loop VCO-modulation
ANT (pin 5)
Not in use
C6
C4
12pF
Modulation by A,M and N
Not in use
12pF
Table 18. Modulation Field
Figure 18. LC Filter
Bits from the microcontroller to be transmitted enter at the
DATAIXO pin. See Table 19.
This filter is designed for the 490MHz band with 50Ω
terminations. Component values may have to be tuned to
compensate for layout parasitics.
The modulation index ß must be a minimum of 2. It is
given by
Frequency Modulation
fDEV
β = 2
rb
The MICRF507 supports two methods of FSK modulation,
selected with the Modulation field as shown in Table 18:
VCO modulation (enabled when Modulation1 is bit set to
0) and divider modulation (Modulation1 bit set to 1). The
Modulation0 bit must always remain 0.
in which fDEV is the single-sided deviation and rb is the bit
rate. Another constraint on fDEV is
fDEV ≥ rb + fOFFSET
where fOFFSET is the total frequency offset between the
receiver and the transmitter:
The calculated fDEV should be used to calculate the needed
receiver bandwidth, see “Switched Capacitor Filter”
section.
VCO Modulation
Frequency Divider Modulation
Set Modulation[1:0] to
Means of modulation
00
10
Divider modulation by switching between
A0/M0/NO and A1/M1/N1
VCO modulation using modulator
Refclk_K, Mod_clkS, Mod_I, Mod_A,
Mod_F
Register fields to set
A0, M0, N0, A1, M1, N1
PLL bandwidth required
Bitstream constraints
Lower than 1/10 of bit rate
DC balance required
Higher than 2x bit rate
None
Instantaneous frequency
waveform (spectrum)
determined by
Register fields affecting modulator
PLL transient response
Table 19. Modulation Modes
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Divider Modulation
as to “round” the waveform and reduce the transmission
spectral width.
When Modulation[1:0] = 10, two sets of divider values
need to be programmed. The divider values stored in the
M0, N0, and A0 registers are selected to transmit a ‘0’ and
the M1, N1, and A1 registers are selected to transmit a ‘1’.
The amplitude of the modulating waveform, and therefore
frequency deviation, is determined by the modulation clock
frequency (controlled by the crystal oscillator frequency
and the register fields Refclk_K, and Mod_ClkS), the
charge/discharge current (controlled by the register field
Mod_I), and the setting of an attenuator (controlled by the
register field Mod_A). The effects of these factors are
explained and quantified belo. A filter is provided to
optimize transmit bandwidth, the proper setting of which is
also explained below.
16×N0 + A0
fRF0 = fXCO
2M0
16×N1+ A1
fRF1 = fXCO
The synthesizer is a negative feedback loop that
suppresses perturbations inside the loop (including the
modulating varactor control voltage) below its bandwidth.
The PLL will not allow modulation unless its transient
response is slower than the bitstream pulses. Frequency
deviation is a high-pass response to modulation. This
means that when VCO modulation is used, the loop
bandwidth must be less than the lowest baseband spectral
component of the bitstream. It also means that the
bitstream must be DC-free (have an equal number of ones
and zeros). See “DC Balanced Line Coding” section.
2M1
The carrier frequency that a receiver must be set to in
order to receive the above transmitted signal is:
fRF0 + fRF1
fRF =
2
and the single-sided deviation is:
fRF1 − fRF0
fDEV
=
2
The PLL must lock to a new frequency upon every
transition in the transmitted bitstream and therefore, needs
a high bandwidth, at least twice the bit rate.
VCO Modulation and the Modulator
VCO Modulation is selected when Modulation[1:0] = 00.
The modulator generates a waveform with programmable
amplitude and shape. This waveform is fed into a
modulation varactor in the VCO, which performs the
desired frequency modulation. The synthesizer operates
with A=A0, M=M0, and N=N0.
Figure 19. Modulator Waveform and Clock
To create the modulating waveform the modulator charges
and discharges a capacitor, controlled by a modulator
clock. As shown in Figure 19, each transition of the
waveform takes four periods of the modulator clock.
Charge/discharge current, and therefore slope, varies so
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Frequency Deviation under VCO Modulation
To avoid saturation in the modulator, it is important not to
exceed maximum Mod_I. Maximum Mod_I for a given
fMOD_CLK is given by:
Three factors determine the deviation at which the data
stream is modulated: modulator clock frequency, capacitor
charge/discharge current, and modulator attenuator
setting. After each is presented in turn, the complete
formula for deviation is given.
Mod_IMAX = INT(fMOD_CLK ⋅ 28×10-6 )-1
The modulator clock frequency is determined by the
crystal oscillator frequency and the settings of the
Refclk_K and Mod_clkS fields:
where INT() returns the integer part of the argument.
fXCO
fMOD_CLK
=
Refclk_K ×2(7-Mod_clkS)
Set the modulator clock frequency to either 8x or 16x the
frequency deviation rate.
Figure 21. Two Different Modulator Current Settings
A third factor determining deviation is the modulator
attenuator, controlled by the Mod_A field. The attenuator is
used when the bit rate is small and/or the BT is small,
which gives a relatively slow modulator clock and therefore
long rise- and fall times, leading in turn to large frequency
deviations unless the signal is attenuated. Additionally, the
attenuator will improve the resolution in the modulator.
Figure 20. Two Different Modulator Clock Settings
Having fMOD_CLK set at 8 times the bit rate corresponds to a
baseband data signal filtered in a Gaussian filter with a
bandwidth-period product (BT) of 1. When BT is increased,
the waveform will be less filtered. Figure 20 shows two
waveforms with BT=1 (the minimum, with fMOD_CLK at 8
times the bitrate) and BT=2 (with fMOD_CLK at 16 times the
bit rate). Changing BT changes the charge-and discharge
times and therefore the frequency deviation, as seen in
Figure 20.
The capacitor charge/discharge current, set with the Mod_I
field, affects deviation, as shown in Figure 21, where
Figure 22. Two Different Modulator Attenuator Settings
Mod_Ia>Mod_Ib. Higher current will give
a
higher
frequency deviation and vice versa. The effect of
modulator clock and Mod_I is as follows:
The effect of the attenuator is given by:
1
fDEV
∝
Mod_I
1+ Mod_A
fDEV
∝
fMOD_CLK
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Figure 22 shows two waveforms with different attenuator
setting: Mod_Aa <Mod_Ab . If Mod_A is increased, the
frequency deviation is lowered and vice versa.
The resulting frequency deviation in terms of the
parameters discussed above is given in the following
equations:
fXCO
fMOD_CLK
=
Refclk_K × 2(7−Mod_clkS)
Figure 23. Modulator Waveform with and without Filtering
in which rb is the bit rate in bits/sec. Mod_F=0 disables the
modulator filter and Mod_F=7 provides the most filtering.
Figure 23 shows a waveform with and without the filter.
Mod_I
1
fDEV
=
×
×
(
C1 + C2 ×fRF
)
fMOD_CLK 1+Mod_A
The modulator filter will not influence the frequency
deviation as long as the programmed cut-off frequency is
above the actual bit rate.
where:
fDEV
fXCO
fRF:
:
Single sided frequency deviation [Hz]
Crystal oscillator frequency [Hz]
Center frequency [Hz]
:
Refclk_K:
Mod_clkS:
6 bit divider, values between 1 and 63
Modulator clock setting, values
between 0 and 7
fMOD_CLK
:
Modulator clock frequency, derived
from the crystal frequency, Refclk_K
and Mod_clkS
Mod_I:
Modulator current setting, values
between 0 and 31
Mod_A:
Modulator attenuator setting, values
between 0 and 15
C1:
C2:
-2.72 x 1010
85.2
Note that the constants C1 and C2 are empirically derived.
Actual frequency deviation may differ by a few percent.
Modulator Filter
To reduce the high-frequency components in the
generated waveform, a filter with programmable cut-off
frequency can be enabled. This is done using Mod_F[2:0],
bit 0 being LSB. The Mod_F field should be set according
to the formula:
150x103 bps
Mod_F =
rb
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When using VCO modulation; after MICRF507 has been
put in transmit mode, the microcontroller will tri-state the
driver connected to DATAIXO pin to leave that pin floating
until the microcontroller begins sending data. This is
because in transmit mode, the modulator is disabled while
the DATAIXO pin is floating (a weak voltage divider sets its
level at Vdd/2) in order to prevent a performance-
degrading transient when message transmission begins.
System Modes and Initialization
Start-up and Initialization
After supply voltage is applied to the MICRF507, a power
on reset period elapses during which it should be
considered to be in an unknown state. The microcontroller
should wait until power on reset is completed. See
“Power-On Reset” subsection within the “Control (3-wire)
Interface” section. After power-on is completed, all 22
writeable registers must be correctly initialized before
operation of the MICRF507. Write only non-zero values to
the M0, N0, M1, and N1 fields.
Below, “write to registers” means writing a complete
control word, or writing just to registers that need to
change.
Transition to transmit mode:
•
Write to registers, setting transmit mode, and other
changes as needed; set/keep PA off (to reduce
spurious emissions). This makes DATAIXO an
input.
Modes of Operation
Mode1 Mode0
State
Comments
Power
down
0
0
Keeps register configuration
•
Write to registers setting PA on (this requires
updating Register 0 only).
Only crystal oscillator
running
0
1
1
1
0
1
Standby
Receive
Transmit
•
•
Wait for LD.
Full receive
Enable the microcontroller’s pin as an output
driving DATAIXO and begin sending the transmit
bitstream.
Full transmit except PA
state
•
After the last bit is transmitted return the
microcontroller’s pin to being an input.
Table 20. Main Mode Bits
Transition to receive mode:
Mode Transitions
•
•
•
Have the microcontroller’s DATAIXO driver
disabled.
To go from power down mode to either receive or transmit
mode, the MICRF507 needs to go through the standby
mode first. This is to ensure that the crystal oscillator starts
up correctly. Once the crystal oscillator settles, the
MICRF507 can go to receive or transmit mode.
Write to registers setting receive mode and other
changes as needed.
Wait for LD. Or, if desired, commence checking
the received bitstream for a valid message without
waiting.
When the mode has been changed to Transmit or
Receive, or when the power amplifier has been enabled,
the synthesizer must be allowed to stabilize. See “Lock
Detect” section.
Number
of bits
Location
of bits
Description
Reference
Field Name
Mode
2
4
Reg0[2:1]
Reg2[3:0]
Main mode selection
Test pins output
Table 20
Table 28
OUTS
Table 21. Register Bit Fields for System Functions
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Message Coding and Formatting
DC Balanced Line Coding
Data
000
001
010
011
100
101
110
111
Word A
1011
1100
0011
1010
0101
1001
0110
1101
Word B
0100
Line coding, diagrammed in Figure 24, is used when a
communication channel imposes constraints on bit
sequences. An encoding stage that ensures DC balance
(equal numbers of ‘1’ and ‘0’ bits and no long consecutive
runs of either) in the encoded bit stream allows the use of
VCO modulation without restrictions on the message bit
stream. Of the coding schemes which meet this need,
Manchester encoding and 3B4B are among the most
commonly used. Programming and performance of the
MICRF507 are based on the encoded bit rate.
0010
In Manchester encoding, each message bit maps to a
word made of two encoded bits as shown in Table 22. The
encoded bit rate is twice the message bit rate so the
encoding overhead is 100%. When selecting PLL loop
filter it is important to note that frequency content of the
encoded bit stream extends down to one-fourth of the
encoded bit rate. That is the case of a 0101… message
bit sequence, which results in a 100110011001… encoded
bit sequence.
Table 23. 3B4B Encoding
Data bits
Encoded words
Comments
A Flag indicates
if “Word A” has
been used
000 000 000 000 1011 0100 1011
000 0100 1011
A Flag indicates
if “Word A” has
been used
111 111 010 110 1101 0010 0011
000 0110 1011
Data
“0”
Word
“10”
Table 24. Example of 3B4B Encoding
“1”
“01”
Message Formatting: Preamble
Table 22. Manchester Encoding
Messages are typically preceded by a header consisting of
24 bits in an alternating pattern: 0101… Such a header
can permit the following actions by the receiver prior to the
arrival of information-carrying bits:
Another encoding method, which is much more efficient
than Manchester coding, is 3B4B, where three message
data bits are encoded into a four-line-bit word. The
encoded bit rate is three-quarter times the message bit
rate. For perfect DC balance, a four bit word would have to
have two ‘1’ line bits and two ‘0’ line bits. Only six such
words are possible. Special steps are therefore needed to
deal with the remaining two encodings: whenever 000 and
111 data appear, toggle a flag that remembers whether the
last encoded word was taken from the “Word A” column
and select the respective word from the other column
shown in Table 23.
•
•
•
Reading of RSSI
Bit synchronizer lock-up
Using the FEE to null out frequency offset
Figure 24. Link Architecture with Encoding
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Typical Application
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Bill of Materials
Item
C1
Part Number
Manufacturer
Murata(6)
Description
Qty.
1
GRM188R71C103K
GRM219R71C104K
0.01µF, 16V Capacitor, X7R ±10%, Size 0603
0.1µF, 16V Capacitor, X7R ±10%, Size 0805
No Connect
C2
Murata
1
C3
0
C4
GRM1885C1H120J
GRM1885C1H390J
GRM1885C1H120J
GRM155R61A102K
GRM1555C1H1R5C
GRM155R61A102K
GRM155R71H221K
GRM155R61A102K
CRCW04026200RJK
CRCW04020RJK
CRCW040227KJK
CRCW040282KJK
CRCW040233KJK
CRCW04020RJK
0603CS-12NXJB
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Vishay(7)
Vishay
Vishay
Vishay
Vishay
Vishay
Coilcraft(8)
12pF, 50V Capacitor, COG ±5%, Size 0603
39pF, 50V Capacitor, COG ±5%, Size 0603
12pF, 50V Capacitor, COG ±5%, Size 0603
Optional 1000pF
1
C5
1
C6
1
C7
1
C8, C9
C10
C11
C12, C13
R1
1.5pF, 50V Capacitor, COG ±0.25pF, Szie 0402
1000pF, 10V Capacitor, X5R ±10%, Size 0402
220pF, 50V Capacitor, X7R ±10%, Size 0402
1000pF, 10V Capacitor, X5R ±10%, Size 0402
6.2k Resistor, ±5%, Size 0402
2
1
1
2
1
R2
0Ω Resistor, ±5%, Size 0402
1
R3
27k Resistor, ±5%, Size 0402
1
R5
82k Resistor, ±5%, Size 0402
1
R6
33K Resistor, ±5%, Size 0402
1
R7
0Ω Resister, ±5% Size 0402
1
L1
12nH, ±5%, Size 0603
1
TSX-10A16.0000MHz:
TN4-26011
Y1
Toyocom(9)
16MHz, 9pF, 10/10ppm
1
470MHz to 510MHz Low-Power FSK Transceiver
with +10dBm Power Amplifier
U1
MICRF507
Micrel, Inc.(10)
1
Notes:
6. Murata: www.murata.com
7. Vishay: www.vishay.com
8. Coilcraft: www.coilcraft.com
9. Toyocom: www.epsontoyocom.co.jp/english
10. Micrel, Inc.: www.micrel.com
Revision 2.2
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Micrel, Inc.
MICRF507
Layout Considerations
RF Traces
To ensure the best RF performance, a carefully planned
layout is essential. Grounding, RF path geometry, supply
routing, and layer definition all play a role in an optimal
design. These are discussed below, and a recommended
layout can be found on the Micrel website at:
www.micrel.com.
The ANT pin impedance is approximately 50Ω. To
minimize reflection due to impedance mismatch, RF traces
should be a controlled impedance of 50Ω as well. Refer to
the Micrel Development Board layout, or a transmission
line impedance calculator to verify a specific geometry’s
characteristic impedance.
Layer Definition
Supply Routing
A typical MICRF507 PCB design consists of four layers,
with the following stack-up:
The radio system is sensitive to supply noise and signals
coupled from one section to another. Routing the supply
lines on an internal layer (below the ground layer)
separates them from potential noise sources such as the
reference oscillator, PA, charge pump, etc. Route supplies
separately and place bypass capacitors as close as
possible to the associated pin.
Layer1 – Component and RF routing
Layer2 – Ground
Layer3 – VDD Routing
Layer 4 – Non-RF Routing
While not the only acceptable definition, this example
provides a good foundation for the general techniques
discussed below.
PLL Loop Filter
Place loop filter components close to each other and near
pins 27 and 29. Connection of the loop filter to VDD should
occur very close to VCOVDD, pin 31. Avoid routing
potentially noisy busses or traces near the loop filter.
Grounding
Design the layout to provide the shortest possible return
path for signals and noise sources. Place ground vias
close to all critical items such as ground pins on the RF IC,
decoupling capacitors, and matching components.
Revision 2.2
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Micrel, Inc.
MICRF507
Overview of Programming Bits
Address
Field
Data Field
A6..A0
D7
D6
D5
D4
PA0
D3
D2
D1
D0
0000000
LNA_by
PA2
PA1
Sync_en
Mode1
Mode0
Load_en
OL_opamp_en PA_LDc_en
0000001
0000010
Modulation1
CP_HI
Modulation0
SC_by
RSSI_en
OUTS3
LD_en
PF_FC1
OUTS1
PF_FC0
OUTS0
(“0”)
VCO_by
(“0”)
(”0”)
PA_by
OUTS2
IFBias_s
(“1”)
IFA_HG
(“1”)
VCO_BIAS_s
(“0”)
VCO_freq
1
0000011
0000100
0000101
VCO_IB2
VCO_IB1
Mod_I3
VCO_IB0
Mod_I2
VCO_freq0
Mod_I0
Mod_F2
Mod_F1
Mod_F0
Mod_FHG
(“0”)
Mod_I4
Mod_shape
(“1”)
Mod_I1
-
-
-
Mod_A3
Mod_A2
Mod_A1
Mod_A0
BitSync_cl
kS0
0000110
0000111
Mod_clkS2
Mod_clkS1
Mod_clkS0 BitSync_clkS2 BitSync_clkS1
BitRate_clkS2
BitRate_clkS1 BitRate_clkS0 RefClk_K5
RefClk_K4
ScClk4
RefClk_K3
ScClk3
RefClk_K2 RefClk_K1 RefClk_K0
ScClk2 ScClk1 ScClk0
SC_HI
ScClk_X2
ScSW_en
0001000
0001001
(“1”)
(“1”)
(“0”)
PrescalMode_s
Prescal_s
XCOAR_en
XCOtune4
XCOtune3
XCOtune2 XCOtune1 XCOtune0
(“0”)
(“0”)
(”1”)
A0_5
-
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
-
-
A0_4
-
A0_3
N0_11
N0_3
A0_2
N0_10
N0_2
A0_1
N0_9
A0_0
N0_8
-
-
N0_7
N0_6
N0_5
-
N0_4
-
N0_1
N0_0
-
-
M0_11
M0_3
M0_10
M0_2
M0_9
M0_1
A1_1
M0_8
M0_0
A1_0
M0_7
M0_6
M0_5
A1_5
-
M0_4
A1_4
-
-
-
-
-
A1_3
A1_2
N1_11
N1_3
N1_10
N1_2
N1_9
N1_8
N1_7
-
N1_6
-
N1_5
-
N1_4
-
N1_1
N1_0
M1_11
M1_3
M1_10
M1_2
M1_9
M1_1
PA_IB1
(”0”)
M1_8
M1_0
PA_IB0
(“1”)
M1_7
Div2_HI
(“1”)
-
M1_6
LO_IB1
(“0”)
-
M1_5
LO_IB0
(“1”)
-
M1_4
PA_IB4
(”1”)
-
PA_IB3
(”0”)
PA_IB2
(”1”)
0010100
0010101
0010110
FEEC_3
FEE_3
FEEC_2
FEE_2
FEEC_1
FEE_1
FEEC_0
FEE_0
FEE_7
FEE_6
FEE_5
FEE_4
Table 25. Overview of Register Bits
Revision 2.2
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Micrel, Inc.
MICRF507
Detailed Description of Programming Bits
Comments
ADR #
BIT #
Name
Description
0000000
7
By_LNA
LNA bypass on/off
6
PA2
Power amplifier level, 3.bit
Reference Table 17
5
4
3
2
1
0
7
6
5
PA1
Power amplifier level, 2.bit
Power amplifier level, 1.bit
Synchronizer Mode bit
Main Mode selection 2.bit
Main Mode selection 1.bit
“1” mandatory
Reference Table 17
Reference Table 17
Reference Table 7
Reference Table 20
Reference Table 20
PA0
Sync_en
Mode1
Mode0
Load_en
Modulation1
Modulation0
0000001
Modulation selection 2.bit
Modulation selection 1.bit
Reference Table 18
Reference Table 18
OL_opamp_en “0” mandatory
“0” mandatory. PA on/off controlled by Lock Detect pin
if this bit is 1
4
PA_LDc_en
3
2
1
0
7
6
5
4
3
2
1
0
7
6
RSSI_en
LD_en
RSSI function on/off
Lock detect function on/off
Pre-filter corner frequency 2.bit
Pre-filter corner frequency 1.bit
High charge-pump current (4x=500uA) on/off
Bypass of Switched Capacitor filter on/off
“0” mandatory. Bypass of VCO stage on/off
Bypass of PA stage on/off
Test pins output 4.bit
PF_FC1
PF_FC0
CP_HI
Reference Table 14
Reference Table 14
0000010
SC_by
VCO_by
PA_by
OUTS3
OUTS2
OUTS1
OUTS0
IFBias_s
IFA_HG
Reference Table 28
Reference Table 28
Reference Table 28
Reference Table 28
Test pins output 3.bit
Test pins output 2.bit
Test pins output 1.bit
0000011
“1” mandatory.
“1” mandatory.High gain setting in preamplifier
“0” mandatory.Select separate bias for VCO on
VCOBias pin
5
VCO_Bias_s
4
3
2
VCO_IB2
VCO_IB1
VCO_IB0
VCO bias current setting, 3. bit (111 = highest current)
VCO bias current setting, 2. bit (100 = typical current)
VCO bias current setting, 1. bit
Reference Table 11
Reference Table 11
Reference Table 11
Frequency setting of VCO, 2. bit (11=highest
frequency)
1
VCO_freq1
Reference Table 11
Reference Table 11
0
7
6
5
4
3
2
1
VCO_freq0
Mod_F2
Mod_F1
Mod_F0
Mod_I4
Frequency setting of VCO, 1.bit
Modulator filter setting, MSB
Modulator filter setting
0000100
Modulator filter setting, LSB
Modulator current setting, MSB
Modulator current setting
Modulator current setting
Modulator current setting
Mod_I3
Mod_I2
Mod_I1
Revision 2.2
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Micrel, Inc.
ADR #
MICRF507
Comments
BIT #
Name
Description
0
7
6
5
4
3
2
1
Mod_I0
Modulator current setting, LSB
Reserved/not in use
0000101
---------
---------
Reserved/not in use
Mod_FHG
Mod_shape
Mod_A3
Mod_A2
Mod_A1
“0” mandatory. Modulator Test bit.
“1” mandatory.Modulator shape enable
Modulator attenuator setting, LSB
Modulator attenuator setting
Modulator attenuator setting
Modulator attenuator setting, MSB (=0: Attenuator
active)
0
Mod_A0
0000110
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
---------
Reserved/not in use
Mod_clkS2
Mod_clkS1
Mod_clkS0
BitSync_clkS2
BitSync_clkS1
BitSync_clkS0
BitRate_clkS2
BitRate_clkS1
BitRate_clkS0
RefClk_K5
Modulator clock setting 3.bit
Modulator clock setting 2.bit
Modulator clock setting 1.bit
BitSync clock setting 3.bit
BitSync clock setting 2.bit
BitSync clock setting 1.bit
Bitrate clock setting 3.bit
Bitrate clock setting 2.bit
Bitrate clock setting 1.bit
Reference clock divider 6.bit
Reference clock divider 5.bit
Reference clock divider 4.bit
Reference clock divider 3.bit
Reference clock divider 2.bit
Reference clock divider 1.bit
0000111
RefClk_K4
RefClk_K3
RefClk_K2
RefClk_K1
RefClk_K0
“1” mandatory. Switced Cap filter high current setting
on/off
0001000
7
SC_HI
6
5
4
3
2
1
0
ScClk_X2
ScSw_EN
ScClk4
“1” mandatory. Switced Cap clock mulitplied by two
“0” mandatory. Switch cap switch enable
SwitchCap clock divider 5.bit
ScClk3
SwitchCap clock divider 4.bit
ScClk2
SwitchCap clock divider 3.bit
ScClk1
SwitchCap clock divider 2.bit
ScClk0
SwitchCap clock divider 1.bit
“1” mandatory. Select external control of prescal mode
(div32/33)
0001001
7
6
PrescalMode_s
Prescale_s
“0” mandatory. Select external control of prescale mode
(div 32/33)
5
4
3
2
1
XCOAR_en
XCOtune4
XCOtune3
XCOtune2
XCOtune1
“1” mandatory. XCO amplitude regulation on/off
Crystal oscillator trimming, LSB
Crystal oscillator trimming
Crystal oscillator trimming
Crystal oscillator trimming
Revision 2.2
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Micrel, Inc.
ADR #
MICRF507
Comments
BIT #
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
Name
XCOtune0
---------
---------
A0_5
Description
Crystal oscillator trimming, MSB
Reserved/not in use
Reserved/not in use
A0-counter 6.bit
0001010
A0_4
A0-counter 5.bit
A0_3
A0-counter 4.bit
A0_2
A0-counter 3.bit
A0_1
A0-counter 2.bit
A0_0
A0-counter 1.bit
0001011
0001100
0001101
0001110
0001111
---------
---------
---------
---------
N0_11
N0_10
N0_9
Reserved/not in use
Reserved/not in use
Reserved/not in use
Reserved/not in use
N0-counter 12.bit
N0-counter 11.bit
N0-counter 10.bit
N0-counter 9.bit
N0-counter 8.bit
N0-counter 7.bit
N0-counter 6.bit
N0-counter 5.bit
N0-counter 4.bit
N0-counter 3.bit
N0-counter 2.bit
N0-counter 1.bit
Reserved/not in use
Reserved/not in use
Reserved/not in use
Reserved/not in use
M0-counter 12.bit
M0-counter 11.bit
M0-counter 10.bit
M0-counter 9.bit
M0-counter 8.bit
M0-counter 7.bit
M0-counter 6.bit
M0-counter 5.bit
M0-counter 4.bit
M0-counter 3.bit
M0-counter 2.bit
M0-counter 1.bit
Reserved/not in use
Reserved/not in use
N0_8
N0_7
N0_6
N0_5
N0_4
N0_3
N0_2
N0_1
N0_0
---------
---------
---------
---------
M0_11
M0_10
M0_9
M0_8
M0_7
M0_6
M0_5
M0_4
M0_3
M0_2
M0_1
M0_0
---------
---------
Revision 2.2
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MICRF507
Comments
ADR #
BIT #
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Name
A1_5
Description
A1-counter 6.bit
A1-counter 5.bit
A1-counter 4.bit
A1-counter 3.bit
A1-counter 2.bit
A1-counter 1.bit
Reserved/not in use
Reserved/not in 7use
Reserved/not in use
Reserved/not in use
N1-counter 12.bit
N1-counter 11.bit
N1-counter 10.bit
N1-counter 9.bit
N1-counter 8.bit
N1-counter 7.bit
N1-counter 6.bit
N1-counter 5.bit
N1-counter 4.bit
N1-counter 3.bit
N1-counter 2.bit
N1-counter 1.bit
Reserved/not in use
Reserved/not in use
Reserved/not in use
Reserved/not in use
M1-counter 12.bit
M1-counter 11.bit
M1-counter 10.bit
M1-counter 9.bit
M1-counter 8.bit
M1-counter 7.bit
M1-counter 6.bit
M1-counter 5.bit
M1-counter 4.bit
M1-counter 3.bit
M1-counter 2.bit
M1-counter 1.bit
A1_4
A1_3
A1_2
A1_1
A1_0
0010000
0010001
0010010
0010011
---------
---------
---------
---------
N1_11
N1_10
N1_9
N1_8
N1_7
N1_6
N1_5
N1_4
N1_3
N1_2
N1_1
N1_0
---------
---------
---------
---------
M1_11
M1_10
M1_9
M1_8
M1_7
M1_6
M1_5
M1_4
M1_3
M1_2
M1_1
M1_0
“1” mandatory. High bias current setting in Div2 circuit
on/off
0010100
7
6
Div2_HI
LO_IB1
“0 mandatory. Bias current setting of LObuffer, 2. bit
(11 = highest current)
Revision 2.2
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Micrel, Inc.
MICRF507
Comments
ADR #
BIT #
Name
Description
“1” mandatory. Bias current setting of LObuffer, 1. bit
(01 = typical current)
5
LO_IB0
“0” mandatory. Bias current setting of PA, 2. bit (11 =
highest current)
4
3
PA_IB4
PA_IB3
“0 mandatory. Bias current setting of PA, 1. bit (01 =
typical current)
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
PA_IB2
PA_IB1
PA_IB0
---------
---------
---------
---------
FEEC_3
FEEC_2
FEEC_1
FEEC_0
FEE_7
FEE_6
FEE_5
FEE_4
FEE_3
FEE_2
FEE_1
FEE_0
“0” mandatory. Bias current setting of PAbuffer, 3. bit
“1”mandatory. Bias current setting of PAbuffer, 2. bit
“1” mandatory. Bias current setting of PAbuffer, 1. bit
Reserved/not in use
0010101
Reserved/not in use
Reserved/not in use
Reserved/not in use
FEE control bit
Reference Table 15
Reference Table 15
Reference Table 15
Reference Table 15
FEE control bit
FEE control bit
FEE control bit
0010110
FEE value, bit 7, MSB
FEE value, bit 6
FEE value, bit 5
FEE value, bit 4
FEE value, bit 3
FEE value, bit 2
FEE value, bit 1
FEE value, bit 0, LSB
Table 26. Detailed Description of Programming Bits
Revision 2.2
October 2, 2013
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Micrel, Inc.
MICRF507
Number
of Bits
Location
of Bits
Category Field Name
Description
Reference
XCOtune
RefClk_K
5
6
Reg9[4:0]
Reg7[5:0]
Crystal oscillator trimming
Reference clock divider
Reg6[0],
Reg7[7:6]
BitRate_clkS
3
Bitrate clock setting
Mod_clkS
3
3
Reg6[6:4]
Reg6[3:1]
Modulator clock setting
BitSync clock setting
BitSync_clkS
DataI/F
Sync_en
1
Reg0[3]
Synchronizer Mode bit
Table 7
Reg13[3:0],
Reg14[7:0]
M0
A0
N0
12
6
M0 counter
A0 counter
N0 counter
Reg10[5:0]
Reg11[3:0],
Reg12[7:0]
12
Reg18[3:0],
Reg19[7:0]
M1
A1
N1
12
6
M1 counter
A1 counter
N1 counter
Reg15[5:0]
Reg16[3:0],
Reg17[7:0]
12
CP_HI
1
2
Reg2[7]
High charge pump current (500 μA = 4x) on/off
VCO_Freq
Reg3[1:0]
Frequency setting of VCO (highest frequency at 11)
VCO bias current setting (highest current at 111, 100
typical)
VCO_IB
LD_en
3
1
Reg3[4:2]
Reg1[2]
Lock detect function on/off
By_LNA
PF_FC
SC_by
ScClk
1
2
1
5
1
4
8
Reg0[7]
Reg1[1:0]
Reg2[6]
LNA bypass on/off
Pre-filter corner frequency
Bypass of switched capacitor filter on/off
Switched Cap clock divider
RSSI function on/off
Table 14
Reg8[4:0]
Reg1[3]
RSSI_en
FEEC
Reg21[3:0]
Reg22[7:0]
FEE control bits
Table 15
Table 18
FEE
FEE value (read only)
Modulation
Mod_I
Mod_A
Mod_F
PA
2
5
4
3
3
1
Reg1[7:6]
Reg4[4:0]
Reg5[3:0]
Reg4[7:5]
Reg0[6:4]
Reg2[4]
Modulation selection
Modulator current setting
Modulator attenuator setting
Modulator filter setting
Power amplifier level
Table 17
PA_by
Bypass of PA stage on/off
Mode
2
4
Reg0[2:1]
Reg2[3:0]
Main mode selection
Test pins output
Table 20
Table 28
System
OUTS
Table 27. Register Fields
Revision 2.2
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Micrel, Inc.
MICRF507
OutS3
OutS2
OutS1
OutS0
IchOut
Gnd
QchOut
Gnd
Ichout2 / RSSI
Gnd
QchOut2 / NC
Gnd
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ip mixer
Qp mixer
Ip IFamp
Qp IFamp
Ip SC-filter
Qp SC-filter
Ip mixer
Qp mixer
Ip mixer
Qp mixer
Ip mixer
Ip IFamp
Ip SC-filter
I limiter
In mixer
Ip IFamp
Qp IFamp
Ip SC-filter
Qp SC-filter
Gnd
In IFamp
Qn IFamp
In SC-filter
Qn SC-filter
I limiter
Qn mixer
In IFamp
Qn IFamp
In SC-filter
Qn SC-filter
In mixer
Gnd
Q limiter
In SC-filter
Qn SC-filter
I limiter
Ip SC-filter
Qp SC-filter
Gnd
Qn mixer
In mixer
Qn mixer
Qp mixer
Qp IFamp
Qp SC-filter
Q limiter
M-div
Gnd
Q limiter
PrescalMode
TQ1
ModIn
TI1
DemodUp
Demod
Phi1n
DemodDn
MAout
N-div
Phi2n
Table 28. Test Signals
Revision 2.2
October 2, 2013
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Micrel, Inc.
MICRF507
Package Information(11) and Recommended Landing Pattern
32-Pin QFN (ML)
Note:
11. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
Revision 2.2
October 2, 2013
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Micrel, Inc.
MICRF507
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2010 Micrel, Incorporated
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