MPC3301-CI/MS_技术文档

MCP3301

13-Bit Differential Input, Low Power A/D Converter

with SPI Serial Interface

Features

General Description

• Full Differential Inputs

The MCP3301 13-bit analog-to-digital (A/D) converter

features full differential inputs and low power consump-

tion in a small package that is ideal for battery-powered

systems and remote data acquisition applications.

• ±1 LSB max DNL

• ±1 LSB max INL (MCP3301-B)

• ±2 LSB max INL (MCP3301-C)

• Single supply operation: 4.5V to 5.5V

• 100 ksps sampling rate with 5V supply voltage

• 50 nA typical standby current, 1 µA max

• 450 µA max active current at 5V

• Industrial temp range: -40°C to +85°C

• 8-pin MSOP, PDIP, and SOIC packages

Incorporating a successive approximation architecture

with on-board sample and hold circuitry, the 13-bit A/D

converter is specified to have ±1 LSB Differential Non-

linearity (DNL) and ±1 LSB Integral Nonlinearity (INL)

for B-grade devices and ±2 LSB for C-grade devices.

The industry-standard SPI serial interface enables 13-

bit A/D converter capability to be added to any PIC^®

microcontroller.

• Mixed Signal PICtail™ Demo Board (P/N:

MXSIGDM) compatible

The MCP3301 features a low current design that per-

mits operation with typical standby and active currents

of only 50 nA and 300 µA, respectively. The device is

capable of conversion rates of up to 100 ksps with

tested specifications over a 4.5V to 5.5V supply range.

The reference voltage can be varied from 400 mV to

5V, yielding input-referred resolution between 98 µV

and 1.22 mV.

Applications

• Remote Sensors

• Battery-operated Systems

• Transducer Interface

Functional Block Diagram

The MCP3301 is available in 8-pin PDIP, 150 mil SOIC,

and MSOP packages. The full differential inputs of this

device enable a wide variety of signals to be used in

applications such as remote data acquisition, portable

instrumentation, and battery-operated applications.

V_REF

V_DDV_SS

Package Types

CDAC

Comparator

MSOP, PDIP, SOIC

V_REF

V_DD

-

8

1

IN+

IN-

Sample

& Hold

Circuits

13-Bit SAR

IN(+)

IN(-)

V_SS

CLK

2

3

4

7

6

5

+

D_OUT

CS/SHDN

Shift

Register

Control Logic

CS/SHDN CLK

D_OUT

 2001-2011 Microchip Technology Inc.

DS21700E-page 1

MCP3301

*Notice: Stresses above those listed under “Maximum

ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Maximum Ratings*

V

...................................................................................7.0V

DD

All inputs and outputs w.r.t. V ............... -0.3V to V +0.3V

SS

DD

Storage temperature .....................................-65°C to +150°C

Ambient temperature with power applied......-65°C to +125°C

Maximum Junction Temperature ..................................150°C

ESD protection on all pins (HBM) .................................> 4 kV

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, and V

= 5V. Full differential

DD

REF

SS

input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with

T

= -40°C to +85°C (Note 7). Conversion speed (F

is 100 ksps with F_CLK= 17*F_SAMPLE

AMB

SAMPLE)

Parameter

Symbol

Min

Typ

Max

Units

Conditions

Conversion Rate

Maximum Sampling Frequency

—

100

ksps See F_CLKspecifications (Note 8)

F_SAMPLE

Conversion Time

Acquisition Time

t

13

1.5

CLK

periods

CONV

t

CLK

ACQ

periods

DC Accuracy

Resolution

12 data bits + sign

bits

Integral Nonlinearity

INL

—

±0.5

±1

±2

LSB MCP3301-B

MCP3301-C

Differential Nonlinearity

DNL

—

±0.5

±1

LSB Monotonic with no missing codes over

temperature

Positive Gain Error

-3

-0.75

-0.5

+3

+2

+6

LSB

Negative Gain Error

Offset Error

Dynamic Performance

Total Harmonic Distortion

Signal to Noise and Distortion

Spurious Free Dynamic Range

Common-Mode Rejection

Power Supply Rejection

THD

SINAD

SFDR

CMRR

PSR

—

-91

78

92

79

74

—

dB

Note 3

Note 6

Note 4

Note 1: This specification is established by characterization and not 100% tested.

2: See characterization graphs that relate converter performance to V level.

REF

3:

4:

V

= 0.1V to 4.9V @ 1 kHz.

IN

= 5V DC ±500 mV

@ 1 kHz, see test circuit Figure 1-4.

DD

P-P

5: Maximum clock frequency specification must be met.

6: = 400 mV, V = 0.1V to 4.9V @ 1 kHz

V

REF

IN

7: MSOP devices are only specified at 25°C and +85°C.

8: For slow sample rates, see Section 5.2.1 “Maintaining Minimum Clock Speed” for limitations on clock frequency.

9: 4.5V - 5.5V is the supply voltage range for specified performance

DS21700E-page 2

 2001-2011 Microchip Technology Inc.

MCP3301

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, and V

= 5V. Full differential

DD

REF

SS

input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with

T

= -40°C to +85°C (Note 7). Conversion speed (F

is 100 ksps with F_CLK= 17*F_SAMPLE

SAMPLE)

AMB

Parameter

Symbol

Min

Typ

Max

Units

Conditions

Reference Input

Voltage Range

0.4

—

V

Note 2

DD

Current Drain

100

0.001

150

3

µA

—

CS = V

= 5V

DD

Analog Inputs

Full-Scale Input Span

Absolute Input Voltage

IN(+)-IN(-)

IN(+)

-V

REF

—

V

REF

-0.3

V

+ 0.3

DD

IN(-)

-0.3

—

+ 0.3

V

Leakage Current

0.001

1

±1

µA

k

pF

Switch Resistance

R

—

See Figure 5-3

S

Sample Capacitor

C

—

25

SAMPLE

Digital Input/Output

Data Coding Format

Binary Two’s Complement

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Output Leakage Current

Pin Capacitance

V

0.7 V

—

0.3 V

—

V

IH

DD

V

IL

DD

V

4.1

—

V

I

= -1 mA, V

= 1 mA, V

= 4.5V

OH

DD

= 4.5V

DD

V

0.4

10

V

OL

I

-10

—

µA

pF

V

= V or V

SS DD

LI

IN

I

= V

or V

SS

LO

OUT

DD

C

, C

T

AMB

= 25°C, f = 1 MHz, Note 1

IN OUT

Timing Specifications

Clock Frequency (Note 8)

Clock High Time

0.085

275

100

—

1.7

—

MHz

ns

V

= 5V, F_SAMPLE= 100 ksps

DD

F_CLK

t

Note 5

HI

Clock Low Time

t

ns

LO

CS Fall To First Rising CLK Edge

CLK Fall To Output Data Valid

t

ns

SUCS

t

125

200

ns

V

= 5V, see Figure 1-2

DO

DD

= 2.7V, see Figure 1-2

CLK Fall To Output Enable

t

—

125

200

ns

V

= 5V, see Figure 1-2

= 2.7V, see Figure 1-2

EN

DD

CS Rise To Output Disable

CS Disable Time

t

—

580

—

100

—

ns

See test circuits, Figure 1-2; Note 1

DIS

t

CSH

D

Rise Time

Fall Time

t

100

See test circuits, Figure 1-2; Note 1

OUT

R

t

—

F

Note 1: This specification is established by characterization and not 100% tested.

2: See characterization graphs that relate converter performance to V level.

REF

3:

4:

V

= 0.1V to 4.9V @ 1 kHz.

IN

= 5V DC ±500 mV

@ 1 kHz, see test circuit Figure 1-4.

DD

P-P

5: Maximum clock frequency specification must be met.

6: = 400 mV, V = 0.1V to 4.9V @ 1 kHz

V

REF

IN

7: MSOP devices are only specified at 25°C and +85°C.

8: For slow sample rates, see Section 5.2.1 “Maintaining Minimum Clock Speed” for limitations on clock frequency.

9: 4.5V - 5.5V is the supply voltage range for specified performance

 2001-2011 Microchip Technology Inc.

DS21700E-page 3

MCP3301

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, and V

= 5V. Full differential

DD

REF

SS

input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with

T

= -40°C to +85°C (Note 7). Conversion speed (F

is 100 ksps with F_CLK= 17*F_SAMPLE

SAMPLE)

AMB

Parameter

Symbol

Min

Typ

Max

Units

Conditions

Power Requirements

Operating Voltage

Operating Current

V

4.5

—

5.5

V

Note 9

DD

I

—

300

200

450

—

µA

V

= 5V, D

= 2.7V, D

unloaded

OUT

DD

DD , REF

OUT

, V

DD REF

Standby Current

I

—

0.05

1

µA

CS = V

DD

= 5.0V

DDS

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistance

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-PDIP

Thermal Resistance, 8L-SOIC

T

A

-40

-65

—

+85

°C

T

A

T

A

+150



—

206

85

—

°C/W

JA

163

Note 1: This specification is established by characterization and not 100% tested.

2: See characterization graphs that relate converter performance to V level.

REF

3:

4:

V

= 0.1V to 4.9V @ 1 kHz.

IN

= 5V DC ±500 mV

@ 1 kHz, see test circuit Figure 1-4.

DD

P-P

5: Maximum clock frequency specification must be met.

6: = 400 mV, V = 0.1V to 4.9V @ 1 kHz

V

REF

IN

7: MSOP devices are only specified at 25°C and +85°C.

8: For slow sample rates, see Section 5.2.1 “Maintaining Minimum Clock Speed” for limitations on clock frequency.

9: 4.5V - 5.5V is the supply voltage range for specified performance

.

t

CSH

CS

t

SUCS

t

HI

LO

CLK

t

EN

DO

DIS

t

R

F

HI-Z

D

LSB

Sign Bit

OUT

Null Bit

FIGURE 1-1:

Timing Parameters.

DS21700E-page 4

 2001-2011 Microchip Technology Inc.

MCP3301

1.1

Test Circuits

1 k

1/2 MCP602

+

-

1.4V

5V ±500 mVp-p

To V

DD

on DUT

1 k

20 k

3 k

Test Point

D_OUT

5V

1 k

2.63V

P-P

C_L= 100 pF

FIGURE 1-4:

Power Supply Sensitivity

FIGURE 1-2:

Load Circuit for t_R, t_Ft_DO.

,

Test Circuit (PSRR).

Test Point

V_DD

V

= 5V

V

= 5V

REF

1 µF

0.1 µF

DD

t_DISWaveform 2

V_DD/2

3 k



D_OUT

0.1 µF

t_ENWaveform

_DISWaveform 1

5V

P-P

100 pF

t

IN(+)

IN(-)

V_SS

V

REF DD

MCP3301

V

SS

5V

P-P

Voltage Waveforms for t_DIS

V_IH

V

= 2.5V

CS

CM

D_OUT

Waveform 1

90%

10%

*

FIGURE 1-5:

Full Differential Test

T_DIS

Configuration Example.

D_OUT

Waveform 2

†

V

=2.5V

1 µF

V

=5V

DD

REF

*Waveform 1 is for an output with internal

conditions such that the output is high, unless

disabled by the output control.

0.1 µF

†Waveform 2 is for an output with internal

conditions such that the output is low, unless

disabled by the output control.

IN(+)

V

5V

REF DD

MCP3301

P-P

IN(-)

V

SS

FIGURE 1-3:

T_EN

Load Circuit for T_DISand

V

=2.5V

CM

.

FIGURE 1-6:

Pseudo Differential Test

Configuration Example.

 2001-2011 Microchip Technology Inc.

DS21700E-page 5

MCP3301

2.0

TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V, F_SAMPLE= 100 ksps,

F_CLK= 17*F_SAMPLE, T_A= 25°C.

1.0

0.8

0.6

1.0

0.8

0.6

Positive INL

0.4

0.2

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

Negative INL

-50

-25

0

25

50

75

100

125

150

0

50

100

Sample Rate (ksps)

150

200

Temperature(°C)

FIGURE 2-1:

Integral Nonlinearity (INL)

FIGURE 2-4:

Integral Nonlinearity (INL)

vs. Sample Rate.

vs. Temperature.

1.0

0.8

2.0

1.5

0.6

1.0

0.4

Positive INL

Negative INL

Positive INL

Negative INL

0.5

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.5

-1.0

-1.5

-2.0

0

50

100

150

200

0

1

2

3

4

5

V_REF(V)

Sample Rate(ksps)

FIGURE 2-2:

Integral Nonlinearity (INL)

FIGURE 2-5:

Differential Nonlinearity

vs. V_REF.

(DNL) vs. Sample Rate.

2.0

1.5

1.0

1

0.8

0.6

0.4

0.2

0

Positive INL

0.5

0.0

-0.2

-0.4

-0.6

-0.8

-1

-0.5

-1.0

-1.5

-2.0

Negative INL

-4096 -3072 -2048 -1024

0

1024

2048

3072

4096

0

1

2

3

4

5

6

Code

V_REF(V)

FIGURE 2-3:

vs. Code (Representative Part).

Integral Nonlinearity (INL)

FIGURE 2-6:

(DNL) vs. V_REF

Differential Nonlinearity

.

DS21700E-page 6

 2001-2011 Microchip Technology Inc.

MCP3301

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V, F_SAMPLE= 100 ksps,

F_CLK= 17*F_SAMPLE, T_A= 25°C.

1

20

0.8

18

0.6

16

0.4

14

0.2

12

0

10

-0.2

8

-0.4

6

-0.6

4

-0.8

2

-1

0

-4096 -3072 -2048 -1024

0

1024

2048

3072

4096

150

6

0

1

2

3

4

5

6

V_REF(V)

Code

FIGURE 2-7:

Differential Nonlinearity

FIGURE 2-10:

Offset Error vs. V_REF.

(DNL) vs. Code (Representative Part).

1.0

0.8

0.6

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

0.4

Positive DNL

0.2

0.0

-0.2

Negative DNL

-0.4

-0.6

-0.8

-1.0

-1.8

-50

0

50

100

150

-50

0

50

100

Temperature (°C)

FIGURE 2-8:

Differential Nonlinearity

FIGURE 2-11:

Temperature.

Positive Gain Error vs.

(DNL) vs. Temperature.

5

4

100

90

80

70

60

50

40

30

20

10

3

2

1

0

-1

-2

0

1

0

1

2

3

4

5

10

100

V_REF(V)

Input Frequency (kHz)

FIGURE 2-9:

Positive Gain Error vs. V_REF

.

FIGURE 2-12:

Signal to Noise Ratio (SNR)

vs. Input Frequency.

 2001-2011 Microchip Technology Inc.

DS21700E-page 7

MCP3301

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V, F_SAMPLE= 100 ksps,

F_CLK= 17*F_SAMPLE, T_A= 25°C.

80

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

70

60

50

40

30

20

10

0

-40

-35

-30

-25

-20

-15

-10

-5

0

1

10

100

Input Frequency (kHz)

Input Signal Level (dB)

FIGURE 2-13:

Total Harmonic Distortion

FIGURE 2-16:

Signal to Noise and

(THD) vs. Input Frequency.

Distortion (SINAD) vs. Input Signal Level.

3.5

3

13

12

11

10

9

2.5

2

1.5

1

8

0.5

0

7

-50

0

50

100

150

0

1

2

3

4

5

6

Temperature (°C)

V

_REF(V)

FIGURE 2-14:

Offset Error vs.

FIGURE 2-17:

Effective Number of Bits

Temperature.

(ENOB) vs. V_REF.

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

0

1

0

1

10

100

10

100

Input Frequency (kHz)

FIGURE 2-15:

Signal to Noise and

FIGURE 2-18:

Spurious Free Dynamic

Distortion (SINAD) vs. Input Frequency.

Range (SFDR) vs. Input Frequency.

DS21700E-page 8

 2001-2011 Microchip Technology Inc.

MCP3301

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V, F_SAMPLE= 100 ksps,

F_CLK= 17*F_SAMPLE, T_A= 25°C.

0

-10

450

400

350

300

250

200

150

100

50

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

0

5000

10000

15000

20000

25000

2

2.5

3

3.5

4

4.5

5

5.5

6

V_DD(V)

Frequency (Hz)

FIGURE 2-19:

Frequency Spectrum of

FIGURE 2-22:

I_DDvs. V_DD.

10 kHz Input (Representative Part).

500

450

400

350

300

250

200

150

100

50

13

12.8

12.6

12.4

12.2

12

11.8

11.6

11.4

11.2

0

1

10

100

50

100

150

200

Sample Rate (ksps)

Input Frequency (kHz)

FIGURE 2-20:

Effective Number of Bits

FIGURE 2-23:

I_DDvs. Sample Rate.

(ENOB) vs. Input Frequency.

-30

-35

-40

-45

-50

-55

-60

-65

-70

-75

-80

345

340

335

330

325

320

315

310

305

300

295

-50

1

10

100

1000

10000

0

50

100

150

Ripple Frequency (kHz)

Temperature (°C)

FIGURE 2-21:

Power Supply Rejection

FIGURE 2-24:

I_DDvs. Temperature.

(PSR) vs. Ripple Frequency. A 0.1 µF bypass

capacitor is connected to the V_DDpin.

 2001-2011 Microchip Technology Inc.

DS21700E-page 9

MCP3301

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V, F_SAMPLE= 100 ksps,

F_CLK= 17*F_SAMPLE, T_A= 25°C.

120

100

80

60

40

20

0

80

70

60

50

40

30

20

10

0

2

2.5

3

3.5

4

4.5

5

5.5

6

100

6

2

2.5

3

3.5

4

4.5

5

5.5

6

V_DD(V)

FIGURE 2-25:

I_REFvs. V_DD

.

FIGURE 2-28:

I_DDSvs. V_DD.

100

10

100

90

80

70

60

50

40

30

20

10

1

0.1

0.01

0.001

0

-50

-25

0

25

50

75

50

100

150

200

Sample Rate (ksps)

Temperature (°C)

FIGURE 2-26:

I_REFvs. Sample Rate.

FIGURE 2-29:

I_DDSvs. Temperature.

73.8

73.6

73.4

73.2

73

8

7

6

5

4

72.8

72.6

72.4

72.2

72

3

2

1

0

-1

71.8

-50

0

1

2

3

4

5

0

50

100

150

V_REF(V)

Temperature (°C)

FIGURE 2-27:

I_REFvs. Temperature.

FIGURE 2-30:

Reference Voltage.

Negative Gain Error vs.

DS21700E-page 10

 2001-2011 Microchip Technology Inc.

MCP3301

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V, F_SAMPLE= 100 ksps,

F_CLK= 17*F_SAMPLE, T_A= 25°C.

80

1

79

78

77

76

75

74

73

72

71

70

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

-50

0

50

100

150

1

10

100

1000

Temperature (°C)

Input Frequency (kHz)

FIGURE 2-31:

Negative Gain Error vs.

FIGURE 2-32:

Common Mode Rejection

Temperature.

vs. Frequency.

 2001-2011 Microchip Technology Inc.

DS21700E-page 11

MCP3301

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Name

MSOP, PDIP,

SOIC

Function

1

2

3

4

5

6

7

8

V_REF

IN(+)

Reference Voltage Input

Positive Analog Input

Negative Analog Input

Ground

IN(-)

V_SS

CS/SHDN

D_OUT

CLK

Chip Select / Shutdown Input

Serial Data Out

Serial Clock

V_DD

+4.5V to 5.5V Power Supply

3.1

Voltage Reference (V

)

3.5

Chip Select/Shutdown (CS/SHDN)

REF

This input pin provides the reference voltage for the

device, which determines the maximum range of the

analog input signal and the LSB size.

The CS/SHDN pin is used to initiate communication

with the device when pulled low. This pin will end a con-

version and put the device in low power standby when

pulled high. The CS/SHDN pin must be pulled high

between conversions and cannot be tied low for

multiple conversions. See Figure 6-2 for serial

communication protocol.

The LSB size is determined by the equation shown

below. As the reference input is reduced, the LSB size

is reduced accordingly.

EQUATION

3.6

Serial Data Output (D

)

OUT

2 x V_REF

LSB Size =

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place. See Figure 6-2 for serial communication

protocol.

8192

When using an external voltage reference device, the

system designer should always refer to the manufac-

turer’s recommendations for circuit layout. Any instabil-

ity in the operation of the reference device will have a

direct effect on the accuracy of the ADC conversion

results.

3.7

Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion, as

well as to clock out each bit of the conversion as it takes

place. See Section 5.2 “Driving the Analog Input”

for constraints on clock speed, and Figure 6-2 for serial

communication protocol.

3.2

Positive Analog Input (IN+)

This pin has an absolute voltage range of V_SS-0.3V to

_DD+0.3V. The full scale input range is defined as the

absolute value of (IN+) - (IN-).

V

3.8

Power Supply (V

)

DD

3.3

Negative Analog Input (IN-)

The device can operate from 2.7V to 5.5V, but the per-

formance is applicable from a 4.5V to 5.5V supply

range. To ensure accuracy, a 0.1 µF ceramic bypass

capacitor should be placed as close as possible to the

pin. See Section 5.6 “Layout Considerations” for

more information regarding circuit layout.

This pin has an absolute voltage range of V_SS-0.3V to

V_DD+0.3V. The full scale input range is defined as the

absolute value of (IN+) - (IN-).

3.4

Ground Connection (V

)

SS

If an analog ground plane is available, it is recom-

mended that this device be tied to the analog ground

plane in the circuit. See Section 5.6 “Layout Consid-

erations”, for more information regarding circuit

layout.

DS21700E-page 12

 2001-2011 Microchip Technology Inc.

MCP3301

Signal to Noise Ratio - Signal to Noise Ratio (SNR) is

defined as the ratio of the signal to noise measured at

the output of the converter. The signal is defined as the

rms amplitude of the fundamental frequency of the

input signal. The noise value is dependant on the

device noise as well as the quantization error of the

converter and is directly affected by the number of bits

in the converter. The theoretical signal to noise ratio

limit based on quantization error only for an N-bit

converter is defined as:

4.0

DEFINITION OF TERMS

Bipolar Operation - This applies to either a differential

or single-ended input configuration, where both

positive and negative codes are output from the A/D

converter. Full bipolar range includes all 8192 codes.

For bipolar operation on a single-ended input signal,

the A/D converter must be configured to operate in

pseudo differential mode.

Unipolar Operation - This applies to either a single-

ended or differential input signal where only one side of

the device transfer is being used. This could be either

the positive or negative side, depending on which input

(IN+ or IN-) is being used for the DC bias. Full unipolar

operation is equivalent to a 12-bit converter.

EQUATION

SNR = 6.02N + 1.76dB

For a 13-bit converter, the theoretical SNR limit is

80.02 dB.

Full Differential Operation - Applying a full differential

signal to both the IN(+) and IN(-) inputs is referred to as

full differential operation. This configuration is

described in Figure 1-5.

Total Harmonic Distortion - Total Harmonic Distortion

(THD) is the ratio of the rms sum of the harmonics to

the fundamental, measured at the output of the

converter. For the MCP3301, it is defined using the first

9 harmonics, as shown in the following equation:

Pseudo-Differential Operation - Applying a single-

ended signal to only one of the input channels with a

bipolar output is referred to as pseudo differential

operation. To obtain a bipolar output from a single-

ended input signal the inverting input of the A/D

converter must be biased above V_SS. This operation is

described in Figure 1-6.

EQUATION

V₂²+ V²₃+ V²₄+ ..... + V²₈+ V²₉

THD(-dB) = –20 log-------------------------------------------------------------------------------

V²₁

Integral Nonlinearity - The maximum deviation from a

straight line passing through the endpoints of the

bipolar transfer function is defined as the maximum

integral nonlinearity error. The endpoints of the transfer

function are a point 1/2 LSB above the first code

transition (0x1000) and 1/2 LSB below the last code

transition (0x0FFF).

Here V₁is the rms amplitude of the fundamental and V₂

through V₉are the rms amplitudes of the second

through ninth harmonics.

Signal-to-Noise plus Distortion (SINAD) - Numeri-

cally defined, SINAD is the calculated combination of

SNR and THD. This number represents the dynamic

performance of the converter, including any harmonic

distortion.

Differential Nonlinearity - The difference between two

measured adjacent code transitions and the 1 LSB

ideal is defined as differential nonlinearity.

EQUATION

Positive Gain Error - This is the deviation between the

last positive code transition (0x0FFF) and the ideal

voltage level of V_REF-1/2 LSB, after the bipolar offset

error has been adjusted out.

SINAD(dB) = 20 log 10^{SNR  10}+ 10^{–THD  10}

EffectIve Number of Bits - Effective Number of Bits

(ENOB) states the relative performance of the ADC in

terms of its resolution. This term is directly related to

SINAD by the following equation:

Negative Gain Error - This is the deviation between

the last negative code transition (0X1000) and the ideal

voltage level of -V_REF-1/2 LSB, after the bipolar offset

error has been adjusted out.

Offset Error - This is the deviation between the first

positive code transition (0x0001) and the ideal 1/2 LSB

voltage level.

EQUATION

SINAD – 1.76

ENOBN = -----------------------------------

6.02

Acquisition Time - The acquisition time is defined as

the time during which the internal sample capacitor is

charging. This occurs for 1.5 clock cycles of the

external CLK as defined in Figure 6-2.

For SINAD performance of 78 dB, the effective number

of bits is 12.66.

Spurious Free Dynamic Range - Spurious Free

Dynamic Range (SFDR) is the ratio of the rms value of

the fundamental to the next largest component in the

output spectrum of the ADC. This is, typically, the first

harmonic, but could also be a noise peak.

Conversion Time - The conversion time occurs

immediately after the acquisition time. During this time,

successive approximation of the input signal occurs as

the 13-bit result is being calculated by the internal

circuitry. This occurs for 13 clock cycles of the external

CLK as defined in Figure 6-2.

 2001-2011 Microchip Technology Inc.

DS21700E-page 13

MCP3301

5.2

Driving the Analog Input

5.0

5.1

APPLICATIONS INFORMATION

The analog input of the MCP3301 is easily driven either

differentially or single ended. Any signal that is

common to the two input channels will be rejected by

the common mode rejection of the device. During the

charging time of the sample capacitor, a small charging

current will be required. For low source impedances,

this input can be driven directly. For larger source

impedances, a larger acquisition time will be required,

due to the RC time constant that includes the source

impedance. For the A/D Converter to meet specifica-

tion, the charge holding capacitor (C_SAMPLE) must be

given enough time to acquire a 13-bit accurate voltage

level during the 1.5 clock cycle acquisition period.

Conversion Description

The MCP3301MCP3301 A/D converter employs a con-

ventional SAR architecture. With this architecture, the

potential between the IN+ and IN- inputs are

simultaneously sampled and stored with the internal

sample circuits for 1.5 clock cycles (t_ACQ). Following

this sample time, the input hold switches of the

converter open and the device uses the collected

charge to produce a serial 13-bit binary two’s

complement output code. This conversion process is

driven by the external clock and must include 13 clock

cycles, one for each bit. During this process, the most

significant bit (MSB) is output first. This bit is the sign

bit and indicates whether the IN+ input or the IN- input

is at a higher potential.

An analog input model is shown in Figure 5-3. This

model is accurate for an analog input, regardless of

whether it is configured as a single-ended input or the

IN+ and IN- input in differential mode. In this diagram,

it is shown that the source impedance (R_S) adds to the

internal sampling switch (R_SS) impedance, directly

affecting the time that is required to charge the capaci-

tor (C_SAMPLE). Consequently, a larger source imped-

ance with no additional acquisition time increases the

offset, gain, and integral linearity errors of the conver-

sion. To overcome this, a slower clock speed can be

used to allow for the longer charging time. Figure 5-2

shows the maximum clock speed associated with

source impedances.

CDAC

Hold

IN+

C_SAMP

+

Comp

13-Bit SAR

-

C_SAMP

IN-

Shift

Register

1.8

1.6

1.4

1.2

1

Hold

D_OUT

FIGURE 5-1:

Simplified Block Diagram.

0.8

0.6

0.4

0.2

0

100

1000

10000

100000

Input Resistance (ohms)

FIGURE 5-2:

Maximum Clock Frequency

vs. Source Resistance (R_S) to maintain ±1 LSB

INL.

DS21700E-page 14

 2001-2011 Microchip Technology Inc.

MCP3301

V_DD

Sampling

Switch

V_T= 0.6V

R_SS= 1 k

CHx

SS

R_S

C_SAMPLE

= DAC capacitance

= 25 pF

C_PIN

7 pF

I_LEAKAGE

±1 nA

VA

V_SS

Legend

VA

signal source

=

source impedance

input channel pad

R

S

CHx

input pin capacitance

threshold voltage

C

V

T

leakage current at the pin due to various junctions

sampling switch

I

LEAKAGE

SS

sampling switch resistor

R

SS

SAMPLE

sample/hold capacitance

C

Using the values in Figure 5-4, we have a 100 Hz cor-

ner frequency. See Figure 5-2 for the relationship

between input impedance and acquisition time.

FIGURE 5-3:

5.2.1

Analog Input Model.

MAINTAINING MINIMUM CLOCK

SPEED

When the MCP3301 initiates, charge is stored on the

sample capacitor. When the sample period is complete,

the device converts one bit for each clock that is

received. It is important for the user to note that a slow

clock rate will allow charge to bleed off the sample

capacitor while the conversion is taking place. For

MCP3301 devices, the recommended minimum clock

speed during the conversion cycle (t_CONV) is 85 kHz.

Failure to meet this criteria may introduce linearity

errors into the conversion outside the rated specifica-

tions. It should be noted that, during the entire conver-

sion cycle, the A/D converter does not have

requirements for clock speed or duty cycle, as long as

all timing specifications are met.

V

= 5V

DD

0.1 µF

C

10 µF

IN+

IN-

V

IN

MCP3301

1 k



R

V

REF

V

IN

OUT

5.3

Biasing Solutions

MCP1525

0.1 µF

1 µF

For pseudo-differential bipolar operation, the biasing

circuit shown in Figure 5-4 shows a single-ended input

AC coupled to the converter. This configuration will give

a digital output range of -4096 to +4095. With the 2.5V

reference, the LSB size is equal to 610 µV.

FIGURE 5-4:

Pseudo-differential biasing

circuit for bipolar operation.

Although the ADC is not production tested with a 2.5V

reference as shown, linearity will not change more than

0.1 LSB. See Figure 2-2 and Figure 2-6 for INL and

DNL errors versus V_REFat V_DD= 5V. A trade-off exists

between the high-pass corner and the acquisition time.

The value of C will need to be quite large in order to

bring down the high-pass corner. The value of R needs

to be 1 k or less, since higher input impedances

require additional acquisition time.

 2001-2011 Microchip Technology Inc.

DS21700E-page 15

MCP3301

Using an external operational amplifier on the input

allows for gain and buffers the input signal from the

input to the ADC, allowing for a higher source

impedance. This circuit is shown in Figure 5-5.

5.4

Common Mode Input Range

The common mode input range has no restriction and

is equal to the absolute input voltage range: V_SS-0.3V

to V_DD+ 0.3V. However, for a given V_REF, the common

mode voltage has a limited swing if the entire range of

the A/D converter is to be used. Figure 5-7 and

Figure 5-8 show the relationship between V_REFand the

common mode voltage. A smaller V_REFallows for wider

flexibility in a common mode voltage. V_REFlevels,

down to 400 mV, exhibit less than 0.1 LSB change in

INL and DNL.

V

= 5V

DD

10 k

0.1 µF

MCP6022

1 k

-

IN+

IN-

V

+

MCP3301

IN

For characterization graphs that show this performance

relationship, see Figure 2-2 and Figure 2-6.

1 µF

V

REF

1 M

V

= 5V

DD

V

OUT

IN

5

4

MCP1525

4.05V

0.95V

1 µF

0.1 µF

2.8V

2.3V

3

2

1

0

FIGURE 5-5:

Adding an amplifier allows

for gain and also buffers the input from any high

impedance sources.

This circuit shows that some headroom will be lost due

to the amplifier output not being able to swing all the

way to the rail. An example would be for an output

swing of 0V to 5V. This limitation can be overcome by

supplying a V_REFthat is slightly less than the common

mode voltage. Using a 2.048V reference for the A/D

converter, while biasing the input signal at 2.5V solves

the problem. This circuit is shown in Figure 5-6.

-1

0.25

1.0

5.0

2.5

4.0

V

(V)

REF

FIGURE 5-7:

Common Mode Range of

Full Differential input signal versus V_REF

.

V

= 5V

DD

V

= 5V

DD

5

10 k

0.1 µF

4.05V

4

2.8V

2.3V

MCP606

1 k

3

2

-

IN+

IN-

V

+

MCP3301

IN

1 µF

V

REF

1 M

1

0.95V

10 k

0

2.048V

-1

0.25

0.5

2.5

1.25

(V)

2.0

V

REF

OUT

IN

1 µF

MCP1525

0.1 µF

FIGURE 5-8:

Common Mode Range

versus V_REFfor Pseudo Differential Input.

FIGURE 5-6:

Circuit solution to overcome

amplifier output swing limitation.

DS21700E-page 16

 2001-2011 Microchip Technology Inc.

MCP3301

5.5

Buffering/Filtering the Analog

Inputs

5.6

Layout Considerations

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

noise wherever possible. A bypass capacitor from V_DD

to ground should always be used with this device and

should be placed as close as possible to the device pin.

A bypass capacitor value of 0.1 µF is recommended.

Inaccurate conversion results may occur if the signal

source for the A/D converter is not a low impedance

source. Buffering the input will solve the impedance

issue. It is also recommended that an analog filter be

used to eliminate any signals that may be aliased back

into the conversion results. Using an op amp to drive

the analog input of the MCP3301 is illustrated in

Figure 5-9. This amplifier provides a low impedance

source for the converter input and low pass filter, which

eliminates unwanted high frequency noise. Values

shown are for a 10 Hz Butterworth Low pass filter.

Digital and analog traces should be separated as much

as possible on the board with no traces running

underneath the device or bypass capacitor. Extra

precautions should be taken to keep traces with high

frequency signals (such as clock lines) as far as

possible from analog traces.

Low pass (anti-aliasing) filters can be designed using

Microchip’s interactive FilterLab^®software. FilterLab

will calculate capacitor and resistor values as well as

determine the number of poles that are required for the

application. For more information on filtering signals,

see AN-699 “Anti-Aliasing Analog Filters for Data

Acquisition Systems”.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing V_DDconnections to

devices in a “star” configuration can also reduce noise

by eliminating current return paths and associated

errors (Figure 5-10). For more information on layout

tips when using the MCP3301 or other ADC devices,

refer to AN-688 “Layout Tips for 12-Bit A/D Converter

Applications”.

V

DD

10 µF

4.096V

Reference

V

DD

Connection

1 µF

0.1 µF

MCP1541

C

L

0.1 µF

V

REF

IN+

MCP3301

IN-

2.2 µF

MCP601

7.86 k

IN

Device 4

V

+

-

14.6 k

1 µF

Device 1

FIGURE 5-9:

The MCP601 Operational

Amplifier is used to implement a 2nd order anti-

aliasing filter for the signal being converted by

the MCP3301.

Device 3

Device 2

FIGURE 5-10:

V_DDtraces arranged in a

‘Star’ configuration in order to reduce errors

caused by current return paths.MCP3301

 2001-2011 Microchip Technology Inc.

DS21700E-page 17

MCP3301

6.0

6.1

SERIAL COMMUNICATIONS

Output Code Format

The output code format is a binary two’s complement

scheme with a leading sign bit that indicates the sign of

the output. If the IN+ input is higher than the IN- input,

the sign bit will be a zero. If the IN- input is higher, the

sign bit will be a ‘1’.

The diagram shown in Figure 6-1 shows the output

code transfer function. In this diagram, the horizontal

axis is the analog input voltage and the vertical axis is

the output code of the ADC. It shows that when IN+ is

equal to IN-, both the sign bit and the data word are

zero. As IN+ gets larger, with respect to IN-, the sign bit

is a zero and the data word gets larger. The full scale

output code is reached at +4095 when the input [(IN+)

- (IN-)] reaches V_REF- 1 LSB. When IN- is larger than

IN+, the two’s complement output codes will be seen

with the sign bit being a one. Some examples of analog

input levels and corresponding output codes are shown

in Table 6-1.

TABLE 6-1:

BINARY TWO’S COMPLEMENT OUTPUT CODE EXAMPLES.

Sign

Bit

Decimal

DATA

Analog Input Levels

Binary Data

Full Scale Positive

(IN+)-(IN-) = V_REF-1 LSB

(IN+)-(IN-) = V_REF-2 LSB

IN+ = (IN-) +2 LSB

IN+ = (IN-) +1 LSB

IN+ = IN-

0

1

1111 1111 1111

1111 1111 1110

0000 0000 0010

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

0000 0000 0001

0000 0000 0000

+4095

+4094

+2

+1

0

IN+ = (IN-) - 1 LSB

IN+ = (IN-) - 2 LSB

IN⁺- IN^-= V_REF+1 LSB

IN⁺- IN^-= -V_REF

-1

-2

-4095

-4096

Full Scale Negative

DS21700E-page 18

 2001-2011 Microchip Technology Inc.

MCP3301

Output

Code

Positive Full

Scale Output = V_REF-1 LSB

0 + 1111 1111 1111 (+4095)

0 + 1111 1111 1110 (+4094)

0 + 0000 0000 0011 (+3)

0 + 0000 0000 0010 (+2)

0 + 0000 0000 0001 (+1)

Analog Input

IN+ > IN-

0 + 0000 0000 0000 (0)

Voltage

IN+ - IN-

IN+ < IN-

1 + 1111 1111 1111 (-1)

1 + 1111 1111 1110 (-2)

1 + 1111 1111 1101 (-3)

-V_REF

V_REF

1 + 0000 0000 0001 (-4095)

1 + 0000 0000 0000 (-4096)

Negative Full

Scale Output = -V_REF

FIGURE 6-1:

Output Code Transfer Function.

 2001-2011 Microchip Technology Inc.

DS21700E-page 19

MCP3301

12 remaining data bits, as shown in Figure 6-2. Data is

always output from the device on the falling edge of the

clock. If all 13 data bits have been transmitted and the

device continues to receive clocks while the CS is held

low, the device will output the conversion result LSB

first, as shown in Figure 6-3. If more clocks are

provided to the device while CS is still low (after the

LSB first data has been transmitted), the device will

clock out zeros indefinitely.

6.2

Communicating with the MCP3301

Communication with the device is completed using a

standard SPI compatible serial interface. Initiating com-

munication with the MCP3301 begins with the CS

going low. If the device was powered up with the CS pin

low, it must be brought high and back low to initiate

communication. The device will begin to sample the

analog input on the first rising edge of CLK after CS

goes low. The sample period will end in the falling edge

of the second clock, at which time the device will output

a low null bit. The next 13 clocks will output the result

of the conversion with the sign bit first, followed by the

t

SAMPLE

t

CSH

CS

Power

Down

t

SUCS

CLK

t

**

DATA

t

CONV

ACQ

HI-Z

NULL

BIT

NULL

BIT

SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0^*

D

SB B11 B10 B9

OUT

* After completing the data transfer, if further clocks are applied with CS low, the ADC will output LSB first data,

followed by zeros indefinitely. See Figure 6-2 below.

** t

: during this time, the bias current and the comparator power down and the reference input becomes a

high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.

DATA

FIGURE 6-2:

Communication with MCP3301 (MSB first Format).

t

SAMPLE

t

CSH

CS

t

SUCS

Power Down

CLK

t

ACQ

t

**

t

DATA

CONV

NULL

BIT SB

HI-Z

D

SB*

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

OUT

* After completing the data transfer, if further clocks are applied with CS low, the ADC will output zeros indefi-

nitely.

** t

: during this time, the bias current and the comparator power down and the reference input becomes a

high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.

DATA

FIGURE 6-3:

Communication with MCP3301 (LSB first Format).

DS21700E-page 20

 2001-2011 Microchip Technology Inc.

MCP3301

falling edge of the third clock pulse, followed by the

remaining 12 data bits (MSB first). Once the first eight

clocks have been sent to the device, the microcon-

troller’s receive buffer will contain two unknown bits (for

the first two clocks, the output is high impedance),

followed by the null bit, the sign bit and the highest

order four bits of the conversion. After the second eight

clocks have been sent to the device, the MCU receive

register will contain the lowest order 8 data bits. Notice

that, on the falling edge of clock 16, the ADC has begun

to shift out LSB first data.

6.3

Using the MCP3301 with

Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required to

clock out eight bits at a time. Using a hardware SPI port

with the MCP3301 is very easy because each conver-

sion requires 16 clocks. For example, Figure 6-4 and

Figure 6-5 show how the MCP3301 can be interfaced

to a microcontroller with a standard SPI port. Since the

MCP3301 always clocks data out on the falling edge of

clock, the MCU SPI port must be configured to match

this operation. SPI Mode 0,0 (clock idles low) and SPI

Mode 1,1 (clock idles high) are both compatible with

the MCP3301. Figure 6-4 depicts the operation shown

in SPI Mode 0,0, which requires that the CLK from the

microcontroller idles in the ‘low’ state. As shown in the

diagram, the sign bit is clocked out of the ADC on the

Figure 6-5 shows the same scenario in SPI Mode 1,1,

which requires that the clock idles in the high state. As

with mode 0,0, the ADC outputs data on the falling

edge of the clock and the MCU latches data from the

ADC in on the rising edge of the clock.

CS

MCU latches data from ADC

on rising edges of SCLK

1

2

3

4

5

6

7

8

CLK

9

10 11 12

14 15 16

13

Data is clocked out of

ADC on falling edges

HI-Z

NULL

BIT

B7

B6 B5 B4 B3 B2 B1 B0 B1

SB B11 B10 B9

B8

D

OUT

LSB first data begins

to come out

SB B11 B10 B9 B8

?

0

B0

B7 B6 B5 B4 B3 B2 B1

X = Don’t Care Bits

? = Unknown Bits

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

FIGURE 6-4:

SPI Communication with the MCP3301 using 8-bit segments

(Mode 0,0: SCLK idles low).

CS

MCU latches data from ADC

on rising edges of SCLK

1

2

3

4

5

6

7

8

CLK

9

10 11 12 13 14 15 16

Data is clocked out of

ADC on falling edges

HI-Z

NULL

BIT

B7 B6 B5 B4 B3 B2 B1

B0

SB B11 B10 B9

B8

D

OUT

LSB first data begins

to come out

SB B11 B10 B9 B8

?

0

B7 B6 B5 B4 B3 B2 B1 B0

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

X = Don’t Care Bits

? = Unknown Bits

FIGURE 6-5:

SPI Communication with the MCP3301 using 8-bit segments

(Mode 1,1: SCLK idles high).

 2001-2011 Microchip Technology Inc.

DS21700E-page 21

MCP3301

7.0

7.1

PACKAGING INFORMATION

Package Marking Information

8-Lead MSOP (3x3 mm)

Example

3301CI

130256

8-Lead PDIP (300 mil)

Example

XXXXXXXX

XXXXXNNN

3301-BI

3

I/P 256

1130

YYWW

8-Lead SOIC (3.90 mm)

Example

3301-BI

3

SN 1130

NNN

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available characters

for customer-specific information.

DS21700E-page 22

 2001-2011 Microchip Technology Inc.

MCP3301

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢋꢌꢎꢏꢆꢐꢑꢄꢈꢈꢆꢒꢓꢊꢈꢋꢔꢃꢆꢇꢄꢌꢕꢄꢖꢃꢆꢗꢍꢐꢘꢆꢙꢍꢐꢒꢇꢚ

ꢛꢏꢊꢃꢜ 3ꢌꢊꢅ&ꢎꢉꢅ'ꢌ!&ꢅꢍ"ꢊꢊꢉꢄ&ꢅꢑꢇꢍ4ꢇꢔꢉꢅ#ꢊꢇ*ꢃꢄꢔ!(ꢅꢑꢈꢉꢇ!ꢉꢅ!ꢉꢉꢅ&ꢎꢉꢅꢒꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ4ꢇꢔꢃꢄꢔꢅꢖꢑꢉꢍꢃ%ꢃꢍꢇ&ꢃꢌꢄꢅꢈꢌꢍꢇ&ꢉ#ꢅꢇ&ꢅ

ꢎ&&ꢑ255***ꢁ'ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ'5ꢑꢇꢍ4ꢇꢔꢃꢄꢔ

D

N

E

E1

NOTE 1

2

b

1

e

c

φ

A2

A

L

L1

A1

6ꢄꢃ&!

ꢒꢚ77ꢚꢒ+ꢘ+ꢙꢖ

ꢐꢃ'ꢉꢄ!ꢃꢌꢄꢅ7ꢃ'ꢃ&!

ꢒꢚ8

89ꢒ

ꢒꢕ:

8"')ꢉꢊꢅꢌ%ꢅꢂꢃꢄ!

ꢂꢃ&ꢍꢎ

8

ꢉ

;

ꢓꢁ=,ꢅ0ꢖ1

9ꢆꢉꢊꢇꢈꢈꢅ?ꢉꢃꢔꢎ&

ꢒꢌꢈ#ꢉ#ꢅꢂꢇꢍ4ꢇꢔꢉꢅꢘꢎꢃꢍ4ꢄꢉ!!

ꢖ&ꢇꢄ#ꢌ%%ꢅ

9ꢆꢉꢊꢇꢈꢈꢅBꢃ#&ꢎ

ꢒꢌꢈ#ꢉ#ꢅꢂꢇꢍ4ꢇꢔꢉꢅBꢃ#&ꢎ

9ꢆꢉꢊꢇꢈꢈꢅ7ꢉꢄꢔ&ꢎ

3ꢌꢌ&ꢅ7ꢉꢄꢔ&ꢎ

ꢕ

M

ꢓꢁꢛ,

ꢓꢁꢓꢓ

M

ꢓꢁ;,

ꢀꢁꢀꢓ

ꢓꢁꢜ,

ꢓꢁꢀ,

ꢕꢏ

ꢕꢀ

+

+ꢀ

ꢐ

M

ꢗꢁꢜꢓꢅ0ꢖ1

-ꢁꢓꢓꢅ0ꢖ1

ꢓꢁ=ꢓ

7

ꢓꢁꢗꢓ

ꢓꢁ;ꢓ

3ꢌꢌ&ꢑꢊꢃꢄ&

3ꢌꢌ&ꢅꢕꢄꢔꢈꢉ

7ꢀ

ꢀ

ꢓꢁꢜ,ꢅꢙ+3

M

ꢓꢝ

;ꢝ

7ꢉꢇ#ꢅꢘꢎꢃꢍ4ꢄꢉ!!

7ꢉꢇ#ꢅBꢃ#&ꢎ

ꢍ

)

ꢓꢁꢓ;

ꢓꢁꢏꢏ

M

ꢓꢁꢏ-

ꢓꢁꢗꢓ

ꢛꢏꢊꢃꢉꢜ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ!"ꢇꢈꢅꢃꢄ#ꢉ$ꢅ%ꢉꢇ&"ꢊꢉꢅ'ꢇꢋꢅꢆꢇꢊꢋ(ꢅ)"&ꢅ'"!&ꢅ)ꢉꢅꢈꢌꢍꢇ&ꢉ#ꢅ*ꢃ&ꢎꢃꢄꢅ&ꢎꢉꢅꢎꢇ&ꢍꢎꢉ#ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢐꢃ'ꢉꢄ!ꢃꢌꢄ!ꢅꢐꢅꢇꢄ#ꢅ+ꢀꢅ#ꢌꢅꢄꢌ&ꢅꢃꢄꢍꢈ"#ꢉꢅ'ꢌꢈ#ꢅ%ꢈꢇ!ꢎꢅꢌꢊꢅꢑꢊꢌ&ꢊ"!ꢃꢌꢄ!ꢁꢅꢒꢌꢈ#ꢅ%ꢈꢇ!ꢎꢅꢌꢊꢅꢑꢊꢌ&ꢊ"!ꢃꢌꢄ!ꢅ!ꢎꢇꢈꢈꢅꢄꢌ&ꢅꢉ$ꢍꢉꢉ#ꢅꢓꢁꢀ,ꢅ''ꢅꢑꢉꢊꢅ!ꢃ#ꢉꢁ

-ꢁ ꢐꢃ'ꢉꢄ!ꢃꢌꢄꢃꢄꢔꢅꢇꢄ#ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢔꢅꢑꢉꢊꢅꢕꢖꢒ+ꢅ/ꢀꢗꢁ,ꢒꢁ

0ꢖ12 0ꢇ!ꢃꢍꢅꢐꢃ'ꢉꢄ!ꢃꢌꢄꢁꢅꢘꢎꢉꢌꢊꢉ&ꢃꢍꢇꢈꢈꢋꢅꢉ$ꢇꢍ&ꢅꢆꢇꢈ"ꢉꢅ!ꢎꢌ*ꢄꢅ*ꢃ&ꢎꢌ"&ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢉ!ꢁ

ꢙ+32 ꢙꢉ%ꢉꢊꢉꢄꢍꢉꢅꢐꢃ'ꢉꢄ!ꢃꢌꢄ(ꢅ"!"ꢇꢈꢈꢋꢅ*ꢃ&ꢎꢌ"&ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢉ(ꢅ%ꢌꢊꢅꢃꢄ%ꢌꢊ'ꢇ&ꢃꢌꢄꢅꢑ"ꢊꢑꢌ!ꢉ!ꢅꢌꢄꢈꢋꢁ

ꢒꢃꢍꢊꢌꢍꢎꢃꢑ ꢘꢉꢍꢎꢄꢌꢈꢌꢔꢋ ꢐꢊꢇ*ꢃꢄꢔ 1ꢓꢗꢞꢀꢀꢀ0

 2001-2011 Microchip Technology Inc.

DS21700E-page 23

MCP3301

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS21700E-page 24

 2001-2011 Microchip Technology Inc.

MCP3301

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢝꢓꢄꢈꢆꢞꢔꢁꢂꢋꢔꢃꢆꢗꢇꢘꢆꢟꢆꢠꢡꢡꢆꢑꢋꢈꢆꢢꢏꢅꢣꢆꢙꢇꢝꢞꢇꢚ

ꢛꢏꢊꢃꢜ 3ꢌꢊꢅ&ꢎꢉꢅ'ꢌ!&ꢅꢍ"ꢊꢊꢉꢄ&ꢅꢑꢇꢍ4ꢇꢔꢉꢅ#ꢊꢇ*ꢃꢄꢔ!(ꢅꢑꢈꢉꢇ!ꢉꢅ!ꢉꢉꢅ&ꢎꢉꢅꢒꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ4ꢇꢔꢃꢄꢔꢅꢖꢑꢉꢍꢃ%ꢃꢍꢇ&ꢃꢌꢄꢅꢈꢌꢍꢇ&ꢉ#ꢅꢇ&ꢅ

ꢎ&&ꢑ255***ꢁ'ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ'5ꢑꢇꢍ4ꢇꢔꢃꢄꢔ

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

A1

c

e

eB

b1

b

6ꢄꢃ&!

ꢚ81?+ꢖ

ꢐꢃ'ꢉꢄ!ꢃꢌꢄꢅ7ꢃ'ꢃ&!

ꢒꢚ8

89ꢒ

;

ꢁꢀꢓꢓꢅ0ꢖ1

M

ꢁꢀ-ꢓ

M

ꢁ-ꢀꢓ

ꢁꢏ,ꢓ

ꢁ-=,

ꢁꢀ-ꢓ

ꢁꢓꢀꢓ

ꢁꢓ=ꢓ

ꢁꢓꢀ;

M

ꢒꢕ:

8"')ꢉꢊꢅꢌ%ꢅꢂꢃꢄ!

ꢂꢃ&ꢍꢎ

ꢘꢌꢑꢅ&ꢌꢅꢖꢉꢇ&ꢃꢄꢔꢅꢂꢈꢇꢄꢉ

ꢒꢌꢈ#ꢉ#ꢅꢂꢇꢍ4ꢇꢔꢉꢅꢘꢎꢃꢍ4ꢄꢉ!!

0ꢇ!ꢉꢅ&ꢌꢅꢖꢉꢇ&ꢃꢄꢔꢅꢂꢈꢇꢄꢉ

ꢖꢎꢌ"ꢈ#ꢉꢊꢅ&ꢌꢅꢖꢎꢌ"ꢈ#ꢉꢊꢅBꢃ#&ꢎ

ꢒꢌꢈ#ꢉ#ꢅꢂꢇꢍ4ꢇꢔꢉꢅBꢃ#&ꢎ

9ꢆꢉꢊꢇꢈꢈꢅ7ꢉꢄꢔ&ꢎ

8

ꢉ

ꢕ

ꢕꢏ

ꢕꢀ

+

+ꢀ

ꢐ

7

ꢍ

)ꢀ

)

ꢉ0

M

ꢁꢏꢀꢓ

ꢁꢀꢜ,

M

ꢁꢀꢀ,

ꢁꢓꢀ,

ꢁꢏꢜꢓ

ꢁꢏꢗꢓ

ꢁ-ꢗ;

ꢁꢀꢀ,

ꢁꢓꢓ;

ꢁꢓꢗꢓ

ꢁꢓꢀꢗ

M

ꢁ-ꢏ,

ꢁꢏ;ꢓ

ꢁꢗꢓꢓ

ꢁꢀ,ꢓ

ꢁꢓꢀ,

ꢁꢓꢛꢓ

ꢁꢓꢏꢏ

ꢁꢗ-ꢓ

ꢘꢃꢑꢅ&ꢌꢅꢖꢉꢇ&ꢃꢄꢔꢅꢂꢈꢇꢄꢉ

7ꢉꢇ#ꢅꢘꢎꢃꢍ4ꢄꢉ!!

6ꢑꢑꢉꢊꢅ7ꢉꢇ#ꢅBꢃ#&ꢎ

7ꢌ*ꢉꢊꢅ7ꢉꢇ#ꢅBꢃ#&ꢎ

9ꢆꢉꢊꢇꢈꢈꢅꢙꢌ*ꢅꢖꢑꢇꢍꢃꢄꢔꢅꢅꢟ

ꢛꢏꢊꢃꢉꢜ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ!"ꢇꢈꢅꢃꢄ#ꢉ$ꢅ%ꢉꢇ&"ꢊꢉꢅ'ꢇꢋꢅꢆꢇꢊꢋ(ꢅ)"&ꢅ'"!&ꢅ)ꢉꢅꢈꢌꢍꢇ&ꢉ#ꢅ*ꢃ&ꢎꢅ&ꢎꢉꢅꢎꢇ&ꢍꢎꢉ#ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢟꢅꢖꢃꢔꢄꢃ%ꢃꢍꢇꢄ&ꢅ1ꢎꢇꢊꢇꢍ&ꢉꢊꢃ!&ꢃꢍꢁ

-ꢁ ꢐꢃ'ꢉꢄ!ꢃꢌꢄ!ꢅꢐꢅꢇꢄ#ꢅ+ꢀꢅ#ꢌꢅꢄꢌ&ꢅꢃꢄꢍꢈ"#ꢉꢅ'ꢌꢈ#ꢅ%ꢈꢇ!ꢎꢅꢌꢊꢅꢑꢊꢌ&ꢊ"!ꢃꢌꢄ!ꢁꢅꢒꢌꢈ#ꢅ%ꢈꢇ!ꢎꢅꢌꢊꢅꢑꢊꢌ&ꢊ"!ꢃꢌꢄ!ꢅ!ꢎꢇꢈꢈꢅꢄꢌ&ꢅꢉ$ꢍꢉꢉ#ꢅꢁꢓꢀꢓFꢅꢑꢉꢊꢅ!ꢃ#ꢉꢁ

ꢗꢁ ꢐꢃ'ꢉꢄ!ꢃꢌꢄꢃꢄꢔꢅꢇꢄ#ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢔꢅꢑꢉꢊꢅꢕꢖꢒ+ꢅ/ꢀꢗꢁ,ꢒꢁ

0ꢖ12ꢅ0ꢇ!ꢃꢍꢅꢐꢃ'ꢉꢄ!ꢃꢌꢄꢁꢅꢘꢎꢉꢌꢊꢉ&ꢃꢍꢇꢈꢈꢋꢅꢉ$ꢇꢍ&ꢅꢆꢇꢈ"ꢉꢅ!ꢎꢌ*ꢄꢅ*ꢃ&ꢎꢌ"&ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢉ!ꢁ

ꢒꢃꢍꢊꢌꢍꢎꢃꢑ ꢘꢉꢍꢎꢄꢌꢈꢌꢔꢋ ꢐꢊꢇ*ꢃꢄꢔ 1ꢓꢗꢞꢓꢀ;0

 2001-2011 Microchip Technology Inc.

DS21700E-page 25

MCP3301

Note: ꢠor the most current package drawingsꢡ please see the ꢢicrochip Packaging Specification located at

httpꢣꢤꢤwww.microchip.comꢤpackaging

DS21700E-page 26

 2001-2011 Microchip Technology Inc.

MCP3301

Note: ꢠor the most current package drawingsꢡ please see the ꢢicrochip Packaging Specification located at

httpꢣꢤꢤwww.microchip.comꢤpackaging

 2001-2011 Microchip Technology Inc.

DS21700E-page 27

MCP3301

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢐꢑꢄꢈꢈꢆꢒꢓꢊꢈꢋꢔꢃꢆꢗꢐꢛꢘꢆꢟꢆꢛꢄꢎꢎꢏꢤꢥꢆꢠꢦꢧꢡꢆꢑꢑꢆꢢꢏꢅꢣꢆꢙꢐꢒꢞꢨꢚ

ꢛꢏꢊꢃꢜ 3ꢌꢊꢅ&ꢎꢉꢅ'ꢌ!&ꢅꢍ"ꢊꢊꢉꢄ&ꢅꢑꢇꢍ4ꢇꢔꢉꢅ#ꢊꢇ*ꢃꢄꢔ!(ꢅꢑꢈꢉꢇ!ꢉꢅ!ꢉꢉꢅ&ꢎꢉꢅꢒꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ4ꢇꢔꢃꢄꢔꢅꢖꢑꢉꢍꢃ%ꢃꢍꢇ&ꢃꢌꢄꢅꢈꢌꢍꢇ&ꢉ#ꢅꢇ&ꢅ

ꢎ&&ꢑ255***ꢁ'ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ'5ꢑꢇꢍ4ꢇꢔꢃꢄꢔ

DS21700E-page 28

 2001-2011 Microchip Technology Inc.

MCP3301

APPENDIX A: REVISION HISTORY

Revision E (November 2011)

Updated Product Identification System.

Corrected MSOP marking drawings.

Updated Package Specification Drawings with new

additions.

Revision D (April 2011)

The following is the list of modifications:

1. Updated the content to illustrate that the devices

now have tested specifications in the 4.5V to

5.5V supply range.

2. Removed figures 2-4 to 2-6, 2-10 to 2-12, 2-16

and 2-17.

Revision C (January 2007)

This revision includes updates to the packaging

diagrams.

Revision B (February 2002)

Undocumented changes.

Revision A (December 2001)

Original Release of this Document.

 2001-2011 Microchip Technology Inc.

DS21700E-page 29

MCP3301

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact the local Microchip sales office.

PART NO.

Device

X

/XX

Examples:

Grade Temperature Package

Range

a)

b)

c)

MCP3301-BI/P: ±1 LSB INL, Industrial

Temperature, PDIP package

MCP3301-BI/SN: ±1 LSB INL, Industrial

Temperature, SOIC package

Device:

Grade:

MCP3301: 13-Bit Serial A/D Converter

MCP3301T: 13-Bit Serial A/D Converter (Tape and Reel)

MCP3301-CI/MS: ±2 LSB INL, Industrial

Temperature, MSOP package

B

C

=

±1 LSB INL

±2 LSB INL

Temperature Range:

Package:

I

=

-40°C to +85°C

MS

P

SN

=

Plastic MSOP, 8-lead

Plastic DIP (300 mil Body), 8-lead

Plastic SOIC (150 mil Body), 8-lead

DS21700E-page 30

 2001-2011 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-756-0

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2001-2011 Microchip Technology Inc.

DS21700E-page 31

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Los Angeles

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Toronto

Mississauga, Ontario,

Canada

China - Xiamen

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

08/02/11

DS21700E-page 32

 2001-2011 Microchip Technology Inc.


型号：	MPC3301-CI/MS
厂家：	MICROCHIP
描述：	SUCCESSIVE APPROXIMATION ADC, PDSO8, PLASTIC, MSOP-8 光电二极管转换器
文件：	总32页 (文件大小：989K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC3301-CI/MS [MICROCHIP]

相关型号：

MPC3301-CI/P

MPC3301T-BI/MS

MPC3301T-CI/MS

MPC3301T-CI/SN

MPC332V1600BI

MPC333J1250AMK

MPC333J315BF

MPC333J400AD

MPC333K1600AMK

MPC333K630AD

MPC333V800BMK

MPC334H315AFK