MTA85401-04I/SS_技术文档

MTA85XXX

PICSEE 20-Pin MCU with Serial EEPROM Multi-Chip Module

FEATURES

PACKAGE TYPE

SSOP

• Multi-chip module

SDA

SCL

OSC2

OSC1

RA0

•1

2

3

20

19

18

17

16

15

14

13

12

11

VDD

RB7

RB6

RB5

RB4

RB3

RB2

RB1

• PIC16C54A or PIC16C58A Microcontrollers with

24LC01B or 24LC02B Serial EEPROMs (SEEs)

in a single package

4

5

• Wide operating voltage range: VDD = 3.0V to

6.25V

RA1

RA2

RA3

6

7

8

• Microcontroller control of SEE power for low

standby current: MTA85X1X series

T0CKI

NMCLR

9

10

RB0

VSS

• Industrial grade only

High Performance RISC-like CPU

• Only 33 single-word instructions to learn

SDA

SCL

•1

2

20

19

18

17

16

15

14

13

12

11

PVDD

N/C

OSC2

OSC1

RA0

RA1

RA2

3

4

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VSS

• All instructions are single-cycle except for

program branches, which are two cycle

5

6

7

8

• Operating speed: MTA854XX, DC - 4 MHz

MTA858XX, DC - 4 and 10 MHz

RA3

• 12-bit wide instructions

• 8-bit wide data path

T0CKI

NMCLR

9

10

• 512 or 2048 x 12 on-chip EPROM program

memory

Serial EEPROM Features

• 25 or 73 x 8 general purpose registers (SRAM)

• Seven special function hardware registers

• Two-level deep hardware stack

• 1K or 2K of EEPROM memory, organized as a

single block: 128 x 8 or 256 x 8

2

• Two-wire serial interface bus, I C compatible

• Direct, indirect, and relative addressing modes for

data and instructions

• 100 kHz and 400 kHz compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 2 ms typical cycle times for page-write

• 1,000,000 ERASE/WRITE cycles typical

• Data retention > 40 years

Peripheral Features

• 12 I/O pins with individual direction control (RB7

dedicated for SEE VDD in MTA85X1X devices)

• 8-bit real time clock/counter (T0CKI) with 8-bit

programmable prescaler

CMOS Technology

• Power-On Reset

• Low-power, high-speed CMOS EPROM and

EEPROM technologies, in a single package

• Oscillator Start-Up timer

• Watchdog timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Fully static design

• Low-power consumption (PIC16C54/58A)

- < 2 mA typical @ 5V, 4 MHz

- 15 µA typical @ 3V, 32 kHz

• Security EPROM bit for code-protection

• Power saving SLEEP mode

• EPROM selectable oscillator options:

- Low-cost RC oscillator: RC

- < 0.3 µA typical standby current (with WDT

disabled) @ 3V, 0°C to 70°C

- Standard crystal/resonator: XT

- High-speed crystal/resonator: HS

- Power-saving low frequency crystal: LP

• Low-power consumption (24LC01B/02B)

- 1 mA active current typical

- 10 µA standby current typical @ 5.5V

- 5 µA standby current typical @ 3.0V

1995 Microchip Technology Inc.

DS40115C-page 1

MTA85XXX

PIN DESCRIPTIONS

Name

Function

Description

RA3: RA0

RB7: RB0

SVDD/RB7

I/O PORTA

4 input/output lines.

8 input/output lines.

I/O PORTB

Shared VDD-I/O pin

Input/Output pin dedicated to EEPROM VDD.

No external connection needed. MTA85X1X only.

T0CKI*

Clock input to TMR0 Register Schmitt Trigger Input.

Clock input to T0CKI register. Must be tied to VSS or VDD if not in

use to avoid unintended entering of test modes and to reduce

current consumption.

MCLR

Master Clear

Schmitt Trigger Input.

A low voltage on this input generates a RESET for the

microcontroller.

A rising voltage triggers the on-chip oscillator start-up timer which

keeps the chip in RESET mode for about 18 ms. This input must be

tied directly, or via a pull-up resistor, to VDD.

OSC1

Oscillator (input)

XT, HS and LP devices:

Input terminal for crystal, ceramic resonator, or external clock

generator.

RC devices:

Driver terminal for external RC combination to establish oscillation.

OSC2/CLKOUT Oscillator (output)

For XT, HS and LP devices:

Output terminal for crystal and ceramic resonator.

Do not connect any other load to this output.

Leave open if external clock generator is used.

For RC devices:

A CLKOUT signal with a frequency of 1/4 FOSC1 is put out on this

pin.

SDA

Serial EEPROM Data

Serial EEPROM Clock

Power supply

EEPROM data line.

EEPROM clock line.

SCL

VDD

VSS

Ground

* Formerly RTCC.

DS40115C-page 2

1995 Microchip Technology Inc.

MTA85XXX

Table of Contents

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

General Description ................................................................................................................................................................... 4

Architectural Description............................................................................................................................................................ 5

Factory Programming Options................................................................................................................................................... 7

Program Memory ....................................................................................................................................................................... 8

Data Memory and Operational Register Files.......................................................................................................................... 10

Special Purpose Registers....................................................................................................................................................... 18

Reset Condition ....................................................................................................................................................................... 19

Prescaler.................................................................................................................................................................................. 20

Basic Instruction Set Summary................................................................................................................................................ 21

10.0 Watchdog Timer (WDT)........................................................................................................................................................... 23

11.0 Oscillator Configurations.......................................................................................................................................................... 24

12.0 Reset........................................................................................................................................................................................ 26

13.0 Power-Down Mode (SLEEP) ................................................................................................................................................... 30

14.0 Configuration Fuses................................................................................................................................................................. 31

15.0 Electrical Characteristics.......................................................................................................................................................... 32

16.0 DC and AC Characteristics...................................................................................................................................................... 44

17.0 EEPROM Bus Description ....................................................................................................................................................... 52

18.0 Write Operation........................................................................................................................................................................ 54

19.0 Read Operation........................................................................................................................................................................ 56

20.0 General EEPROM Information................................................................................................................................................. 58

21.0 Development Support .............................................................................................................................................................. 59

22.0 Packaging Diagrams and Dimensions..................................................................................................................................... 63

23.0 Package Marking Information .................................................................................................................................................. 64

1995 Microchip Technology Inc.

DS40115C-page 3

MTA85XXX

The MTA85XXX devices are supported by an in-circuit

emulator, an assembler, and a production quality

programmer. All tools are supported by IBM PC and

compatible machines.

1.0

GENERAL DESCRIPTION

The MTA85XXX devices from Microchip Technology

Inc. are a family of multi-chip products which offer a

unique combination of EPROM-based Microcontrollers

and Serial EEPROM data memory in a single package.

The MTA85XXX line features the PIC16C5XA family of

Microcontrollers combined with Microchip’s 24LC0XB

family of Serial EEPROMs.

1.1

Applications

The MTA85XXX family is ideally suited to a wide variety

of applications including, but not limited to: keyless

entry, remote control, smart cards and automotive

controllers. The EPROM program memory makes

customization of application programs fast and

convenient. The EEPROM data memory is ideal for

storing configuration information, access codes, serial

numbers, and adaptive look-up tables. The small

footprint package makes the MTA85XXX devices

perfect for applications with physical space limitations.

This small size coupled with the low-cost, low-power,

wide voltage range, and high performance of this

flexible family of devices makes the MTA85XXX the

The Microcontroller and Serial EEPROM portions of

these multi-chip devices are equivalent to their

respective individual components chips, except for the

electrical specifications on shared pins. Please refer to

the datasheets of the component die for information on

each device’s architecture, functionality, and other

important user information.

Two unique pinouts are available in this family of

devices, regardless of which combination of

component chips are

used. The first pinout

(MTA85X0X series) features shared power and ground

pins for the Microcontroller and Serial EEPROM. All

other Microcontroller and Serial EEPROM pins are

electrically independent. The second available pinout

(MTA85X1X series) features Microcontroller control of

the Serial EEPROM VDD. This allows the Serial

EEPROM to be powered down when going into a

standby mode. This is often desirable in power con-

scious applications to reduce current when the Serial

EEPROM is not being accessed. In this configuration

the Microcontroller I/O pin RB7 is used to supply power

to the Serial EEPROM. It is the user’s responsibility to

ensure that RB7 is driving a '1' while the Serial

EEPROM is being used.

microcontroller of choice for

applications which utilize EEPROM memory.

a wide variety of

1.2

MTA85XXX Series Overview

A variety of EPROM program memory sizes, EEPROM

data memory sizes and frequency ranges are

available. Depending on the application and production

requirements, the proper device option can be selected

using the information in Table 1-1 and Table 1-2. When

placing orders, please use the “MTA85XXX Product

Identification System” on the back page of this data

sheet to specify the correct part.

TABLE 1-1:

FAMILY OVERVIEW

Part Number Microcontroller

SEE

PGM EPROM

EEPROM

RAM

I/O

MTA85401

MTA85402

MTA85411

MTA85412

MTA85801

MTA85802

MTA85811

MTA85812

PIC16C54A

PIC16C58A

24LC01B

24LC02B

24LC01B

24LC02B

24LC01B

24LC02B

24LC01B

24LC02B

512 x 12

2048 x 12

128 x 8

256 x 8

128 x 8

256 x 8

128 x 8

256 x 8

128 x 8

256 x 8

32 x 8

80 x 8

12

12 note 1

12

12 note 1

Note:

RB7 dedicated to SEE VDD

DS40115C-page 4

1995 Microchip Technology Inc.

MTA85XXX

2.2

Clocking Scheme/Instruction Cycle

2.0

ARCHITECTURAL

DESCRIPTION

The clock input (from pin OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, PC is

incremented every Q1, instruction is fetched from

program memory and latched into instruction register in

Q4. It is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

is shown in Figure 2-2.

2.1

Harvard Architecture

The MTA85XXX microcontrollers are low-power, high-

speed, full static CMOS devices containing EEPROM,

EPROM, RAM, I/O and a central processing unit in a

single package.

The architecture is based on a register file concept with

separate bus and memories for data and instructions

(Harvard architecture). The data bus and memory

(RAM) are 8-bits wide while the program bus and

program memory (EPROM) have a width of 12-bits.

This concept allows a simple yet powerful instruction

set designed to emphasize bit, byte and register

operations under high speed with overlapping

instruction fetch and execution cycles. That means

that, while one instruction is executed, the following

instruction is already being read from the program

memory. A block diagram of the MTA85XXX is given in

Figure 2-1.

FIGURE 2-1: MTA85XXX SERIES BLOCK DIAGRAM

OSC1

MCLR

T0CKI

9-11

Configuration WORD

“OSC

Select”

EPROM

512 X 12 To

2048 X 12

STACK1

STACK2

9-11

Page

Latches

OSC2

“Disable"

PC

Watchdog

EEPROM

Array

“Code

12

2

XDEC

Timer

Protect”

Oscillator/

Timing &

Control

Instruction

Register

WDT/TMR0

Prescaler

WDT

Time Out

9

CLKOUT

12

HV

Generator

6

“SLEEP”

Instruction

Decoder

8

Option

Reg.

“OPTION”

General

Purpose

Register

File

Direct RAM

Address

Direct

From W

5

(SRAM)

24-72

Bytes

5-7

8

Memory

Control

Logic

I/O

Control

Logic

STATUS

ALU

TMR0

FSR

8

Data

W

8

SCL

From W

8

SDA

From W

Sense

AMP R/W

Control

8

4

PORTA

4

8

“TRIS 5”

“TRIS 6”

“TRIS 7”

TRISA

TRISB

TRISC

PORTB

PORTC

8

RC7:RC0

(28-Pin

Devices Only)

YDEC

RA3:RA0

RB7:RB0

1

RB7

EEPROM Portion

Block Diagram

PIC16C5XA Portion

Block Diagram

VDD

VSS

VDD

VSS

MTA85X0X devices have PIC16C5XA VDD tied to EEPROM VDD.

MTA85X1X devices have PIC16C5XA RB7 tied to EEPROM VDD.

1995 Microchip Technology Inc.

DS40115C-page 5

MTA85XXX

2.3

Data Register File

2.4

Arithmetic/Logic Unit (ALU)

The 8-bit data bus connects two basic functional

elements together: the Register File composed of

addressable 8-bit registers including the I/O Ports, and

an 8-bit wide Arithmetic Logic Unit. The 32 bytes of

RAM are directly addressable while a "banking"

scheme, with banks of 16 bytes each, is employed to

address larger data memories (Figure 5-1). Data can

be addressed direct, or indirect using the file select

register (f4). Immediate data addressing is supported

by special "literal" instructions which load data from

program memory into the W register.

The 8-bit wide ALU contains one temporary working

register (W Register). It performs arithmetic and

Boolean functions between data held in the W Register

and any file register. It also does single operand

operations on either the W register or any file register.

2.5

Program Memory

512 or 2048 words of 12-bit wide on-chip program

memory (EPROM) can be directly addressed.

Sequencing of microinstructions is controlled via the

Program Counter (PC) which automatically increments

The register file is divided into two functional groups:

operational registers and general purpose registers.

The operational registers include the Real Time Clock

Counter (T0CKI) register, the Program Counter (PC),

the Status Register, the I/O registers (PORTs), and the

File Select Register. The general purpose registers are

used for data and control information under command

of the instructions.

to execute

in-line programs. Program control

operations, supporting direct, indirect, relative

addressing modes, can be performed by Bit Test and

Skip instructions, Call instructions, Jump instructions or

by loading computed addresses into the PC. In

addition, an on-chip two-level stack is employed to

provide easy to use subroutine nesting.

In addition, special purpose registers are used to

control the I/O port configuration, and the prescaler

options.

FIGURE 2-2: CLOCKS/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

Internal

phase

clock

PC

PC+1

PC+2

(Program counter)

OSC2/CLKOUT

(RC mode)

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

Note: For additional details on the PIC16C5X architecture, please refer to document # DS30236.

DS40115C-page 6

1995 Microchip Technology Inc.

MTA85XXX

3.2

Quick-Turn-Production (QTP) Devices

3.0

FACTORY PROGRAMMING

OPTIONS

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for volume users with stable code, who

choose not to program the devices themselves. A QTP

device is identical to an OTP device, except that the

program memory and special EPROM fuses are

programmed at the factory, with the customer’s code.

Certain code and prototype verification procedures do

apply before production shipments are available.

Please contact your Microchip Technology Inc. sales

office for more details.

A variety of EPROM program memory sizes, EEPROM

data memory sizes and frequency ranges are

available. Depending on the application and production

requirements, the proper device option can be selected

using the information in Table 1-1 and Table 1-2. When

placing orders, please use the “MTA85XXX Product

Identification System” on the back page of this data

sheet to specify the correct part.

3.1

One-Time-Programmable (OTP)

Devices

3.3

Serialized-Quick-Turnaround-

Production (SQTP) Devices

The availability of OTP devices is especially useful for

customers expecting frequent code changes and

updates.

Microchip offers the unique programming service

where few locations in each device are programmed

with different serial numbers. The serial numbers may

be random, pseudo-random or sequential.

With OTP devices the program EPROM is erased,

allowing the user to write the application code into it.

Additionally the watchdog timer can be disabled, and/

or the code protection logic can be activated by

programming special EPROM fuses. 16 non-dedicated

EPROM bits are available for the customer ID or other

customer information and are also user programmable.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

1995 Microchip Technology Inc.

DS40115C-page 7

MTA85XXX

The MTA858XX devices have multiple program

memory pages. It should be noted for the MTA858XX

products that because bit 8 (ninth bit) of PC is cleared

in CALL instruction or any instruction which writes to

the PC (e.g., MOVWF PC), all subroutine calls or com-

puted jumps are limited to the first 256 locations of any

program memory page (512 words long).

4.0

PROGRAM MEMORY

The MTA854XX devices contain 512 12-bit words of

program memory. The MTA858XX devices contain

2048 12-bit words. Refer to Figure 4-1 and Figure 4-2

for a description of the program memory organization.

4.1

Program Memory Organization

Incrementing the program counter when it is pointing to

the last address of a selected memory page is also

possible and will cause the program to continue in the

next page. However, the page pre-select bits in the

STATUS register will not be changed and the next

GOTO, CALL, ADDWF PC, MOVWF PCinstruction will

return to the previous page unless the page pre-select

bits have been updated under program control. For

example, a NOP at location 1FFh (page 0) increments

the PC to 200h (page 1). A “GOTO xxx” at 200h will

return the program to address “xxx” on page 0 (assum-

ing that the page preselect bits in the STATUS register

are '0').

Up to 512 words of 12-bit wide on-chip program mem-

ory (EPROM/ROM) can be directly addressed. Larger

program memories can be addressed by selecting one

of up to four available pages of 512 words each

(Figure 4-2). Sequencing of instructions is controlled

via the Program Counter (PC) which automatically

increments to execute in-line programs. Program con-

trol operations supporting direct, indirect, and relative

addressing modes, can be performed by bit test, skip,

call, and jump type instructions, or by loading com-

puted addresses into the PC. In addition, an on-chip

two-level stack is employed to provide easy to use sub-

routine nesting.

Upon a RESET condition, page 0 is pre-selected while

the program counter addresses the last location in the

last page. Thus, a GOTOinstruction at this location will

automatically cause the program to continue in page 0.

4.2

Program Counter

The program counter generates addresses for on-chip

EEPROM containing the program instruction words.

Note: The MTA854XX devices only have a single

The program counter is set to all '1's upon a RESET

condition. During program execution, it is auto

incremented with each instruction unless the result of

that instruction changes the PC itself:

page, page 0 (Figure 4-1).

a) GOTOinstructions allow the direct loading of the

lower nine program counter bits (PC8:PC0). For

MTA858XX devices, the upper two bits of PC

(PC10:PC9) are loaded with page select bits

PA1:PA0 (STATUS <6:5>). Thus GOTO permits

jumping to any location on any page.

b) CALLinstructions load the lower 8-bits of the PC

directly while the 9-bits are cleared. The PC

value, incremented by one, will be PUSH’ed

onto the stack. For MTA858XX, the upper two

bits of PC (PC10:PC9) are loaded with Page

Select bits PA1:PA0 (STATUS <6:5>).

c) RETLW instructions load the program counter

with the top of stack contents.

d) If the PC is the destination in any instruction

(e.g., MOVWF PC, ADDWF PC, or BSF PC, 5),

then the computed 8-bit result will be loaded into

the low 8-bits of program counter. The ninth bit

of PC will be cleared. In MTA858XX devices

PC10:PC9 will be loaded with the page select

bits.

DS40115C-page 8

1995 Microchip Technology Inc.

MTA85XXX

4.3

Stack

FIGURE 4-2: PROGRAM MEMORY

ORGANIZATION MTA858XX

GOTO, CALL, Inst with PC as destination -

from PA1 (STATUS<6>) (Note1)

The MTA85XXX employs a two-level hardware PUSH/

POP stack (Figure 4-1 and Figure 4-2).

GOTO, CALL, Inst with PC as destination -

The CALL instruction pushes the current program

counter value, incremented by one, into stack level 1.

Stack level 1 is automatically pushed to level 2. If more

than 2 subsequent CALLs are executed, only the most

recent two return addresses are stored.

from PA0 (STATUS<5>) (Note1)

GOTO- Direct from instruction WORD

CALL, Inst with PC as Destination -

Always '0'

GOTO, CALL- Direct from Instruction WORD

Inst with PC as Destination - From ALU

The page preselect bits of the STATUS register will be

loaded into the most significant bits of the program

counter. The ninth bit is always cleared upon a CALL

instruction. This means that subroutine entry

addresses have to be located always within the lower

half of a memory page (addresses 000h-0FFh, 200h-

2FFh, 400h-4FFh, 600h-6FFh). However, as the stack

has the same width as the PC, subroutines can be

called from anywhere in the program.

RETLW,

Stack Level 1

Stack Level 2

CALL

PC

A10 A9 A8 A<7:0>

9-11 bit

1

8

2

Max EPROM

Address for:

000

0FF

00

Page 0

The RETLWinstruction loads the contents of the stack

level 1 into the program counter while stack level 2 gets

copied into level 1. If more than 2 subsequent RETLWs

are executed, the stack will be filled with the address

previously stored in level 2. The return will be always to

the page from where the subroutine was called,

regardless of the current setting of the page pre-select

bits in the STATUS register. Note that the W register will

be loaded with the literal value specified in the RETLW

instruction. This is particularly useful for the

implementation of “data” tables within the program

memory.

100

1FF

PIC16C54A

200

2FF

01

10

11

Page 1

Page 2

Page 3

300

3FF

400

4FF

500

5FF

FIGURE 4-1: PROGRAM MEMORY

ORGANIZATION MTA854XX

GOTO... Direct from instruction word

CALL, Inst with PC as Destination ... Always '0'

600

6FF

GOTO, CALL... Direct from Instruction Word

Inst with PC as Destination ... From ALU

RETLW, CALL

700

7FF

PC

A8 A<7:0>

Stack Level 1

Stack Level 2

9-bit

1

8

PIC16C58A

/CR58A

000

0FF

Page 0

100

1FF

Note 1: PIC16C58A/CR58A only.

1995 Microchip Technology Inc.

DS40115C-page 9

MTA85XXX

For MTA858XX devices, there are seven special

function register (operational register files) and

73 general purpose registers. These registers are

mapped according to Figure 5-1. Note that several

address blocks are mapped to the same physical

registers. To address the banked registers (addresses

above 0Fh) bits (STATUS <6:5>) of the FSR are used.

5.0

DATA MEMORY AND

OPERATIONAL REGISTER

FILES

For MTA854XX devices, there are seven special

function registers (operational register files) and 25

general purpose registers. Data addresses 00h-06h

are reserved for the operational register files,

addresses 07h-1Fh are used for the general purpose

file registers. FSR bits (STATUS <6:5>) are not used.

FIGURE 5-1: DATA MEMORY MAP

File

Address

7 6 5 4 3 2 1 0

INDF (*)

00

CALL

RETLW

10 9 8

7 6 5 4 3 2 1 0

10 9 8

7

5

6 5 4 3 2 1 0

TMR0

01

STACK 1

A10 A9 A8

PCL

STATUS

FSR

PORTA

PORTB

PORTC (**)

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

STACK 2

7 6 5 4 3 2 1 0

TRISA

4

3 2 1 0

TRISB

OPTION

TRISC

General

Purpose

Register

File

To and from

register file

via ALU

W

From Program Memory

Bit 6, 5 of FSR: Bank Select

(C58A, CR58A Only)

11

01

10

00

10

11

50

70

30

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

General

Purpose

Register

File

General Purpose

Register File

(C58A, CR58A Only)

(All Types)

(Bank 0) (***)

(Bank 1) (***)

3F

(Bank 2) (***)

5F

(Bank 3) (***)

7F

(*)

Not a physically implemented register. See Section 4.5 for details.

(**)

File address 7h is a general purpose register on the PIC16C54A, and PIC16C58A/CR58A.

Bank 0 is available on all microcontrollers while Bank 1, Bank 2, and Bank 3 are only available on the

C58A, CR58A. (Section 4.5).

(***)

DS40115C-page 10

1995 Microchip Technology Inc.

MTA85XXX

5.1.1

GENERAL PURPOSE REGISTER FILE

5.1

Data Memory Organization

The register file is accessed either directly or indirectly

through the file select register FSR.

The 8-bit data bus connects two basic functional ele-

ments together: the register file composed of up to 80

addressable 8-bit registers including the I/O ports, and

an 8-bit wide Arithmetic Logic Unit (ALU). 32 bytes of

RAM are directly addressable while a “banking”

scheme, with banks of 16 bytes each, is employed to

address larger data memories (Figure 5-1). Data can

be addressed directly, or indirectly using the File Select

Register (FSR). Immediate data addressing is sup-

ported by special “literal” instructions which load data

from program memory into the W register.

5.1.2

SPECIAL FUNCTION REGISTERS:

The Special Function Registers are registers used by

the CPU and peripheral functions to control the opera-

tion of the device (Table 5-1).

The special registers can be classified into two sets.

The special registers associated with the “core” func-

tions are described in this section. Those related to the

operation of the peripheral features are described in

the section for each peripheral feature.

The register file is divided into two functional groups:

Special Function registers and General Purpose regis-

ters. The special function registers include the Timer0

(TMR0) register, the Program Counter (PC), the Status

Register, the I/O registers (ports), and the File Select

Register (FSR). The general purpose registers are

used for data and control information under command

of the instructions.

In addition, special purpose registers are used to con-

trol the I/O port configuration and prescaler options.

TABLE 5-1:

PIC16C5X REGISTER FILE SUMMARY

Value on

Power-On

Reset

Value on

MCLR and

WDT resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h

01h

02h

03h

04h

05h

06h

07h

INDF

Uses contents of FSR to address data memory (not a physical register)

8-bit real-time clock/counter

---- ----

xxxx xxxx

1111 1111

0001 1xxx

xxxx xxxx

---- xxxx

xxxx xxxx

---- ----

uuuu uuuu

1111 1111

000? ?uuu

uuuu uuuu

---- uuuu

uuuu uuuu

TMR0

PCL

Low order 8 bits of PC

STATUS

FSR

PA2

PA1

PA0

TO

PD

Z

DC

C

Indirect data memory address pointer 0

PORTA

PORTB

PORTC

—

RA3

RB3

RC3

RA2

RB2

RC2

RA1

RB1

RC1

RA0

RB0

RC0

RB7

RC7

RB6

RC6

RB5

RC5

RB4

RC4

2

Legend: x = unknown, u = unchanged. - = unimplemented, read as '0'.

Note 1: The upper byte of the program counter is not directly accessible. The upper bits can be set or cleared by writing to

PA1:PA0 (STATUS<6:5>).

2: File address 7h is a general purpose register on the PIC16C54A and PIC16C58A/CR58A.

3: Shading indicates unimplemented bits.

1995 Microchip Technology Inc.

DS40115C-page 11

MTA85XXX

be delayed by two cycles before the T0CKI register is

incremented. This is true for instructions that either

write to or read-modify-write T0CKI (e.g., MOVF

T0CKI, CLRF T0CKI). For applications where T0CKI

needs to be tested for '0' without affecting its count, use

of the MOVF T0CKI, W instruction is recommended.

Timing diagrams in Figure 5-3 and Figure 5-4 show

T0CKI read, write and increment timing.

5.2

Indirect Data Addressing (INDF) f0

This is not

a physically implemented register.

Addressing INDF calls for the contents of the File

Select Register to be used to select a file register. The

INDF register is useful as an indirect address pointer.

For example, in the instruction ADDWF INDF, W will

add the contents of the register pointed to by the FSR

to the content of the W Register and place the result in

W.

5.3.1

USING T0CKI WITH EXTERNAL CLOCK

If INDF itself is read through indirect addressing

(i.e., FSR = 0h), then 00h is read. If the INDF register

is written to via indirect addressing, the result will be a

no operation (NOP).

When external clock input is used for T0CKI, it is

synchronized with internal phase clocks. Therefore,

external clock input must meet certain requirements.

Also there is some delay from the occurrence of the

external clock edge to the actual incrementing of

T0CKI. Referring to Figure 5-5, the synchronization is

done after the prescaler. Output of the prescaler is

sampled twice in every instruction cycle to detect rising

or falling edges. Therefore, it is necessary for PSOUT

to be high for at least 2 TOST and low for at least 2 TOSC

where:

5.3

Real Time Clock/Counter Register

(T0CKI) f1

This register can be loaded and read by the program as

any other register. In addition, its contents can be

incremented by an external signal edge applied to the

T0CKI pin or by the internal instruction cycle clock

(CLKOUT = FOSC/4). Figure 5-2 is a simplified block

diagram of the T0CKI module.

TOSC = oscillator time period.

When no prescaler is used, PSOUT (Prescaler output,

Figure 5-3) is the same as T0CKI clock input and,

therefore, the requirements are:

An 8-bit prescaler can be assigned to the T0CKI by

writing the proper values to the PSA bit and the PS bits

in the OPTION register. The OPTION register is a

special register (not mapped in data memory)

TRTH

TRTL

=

T0CKI high time ≥ 2 TOSC + 20 ns

T0CKI low time ≥ 2 TOSC + 20 ns

addressable

using

the

OPTION

instruction

When prescaler is used, the T0CKI input is divided by

the asynchronous ripple counter-type prescaler so the

prescaler output is symmetrical.

(Section 6.4). If the prescaler is assigned to the T0CKI,

instructions writing to the T0CKI register (e.g., CLRF

T0CKI, or BSF T0CKI,5,...etc.) clear the prescaler.

Then:

The bit RTS (T0CKI Signal Source) in the OPTION

register determines if the T0CKI register is incremented

internally or externally.

N • TRT

PSOUT high time = PSOUT low time =

2

where TRT = T0CKI input period and N = prescale value

RTS = 1: The clock source for the T0CKI or the

prescaler, if assigned to it, is the signal on the T0CKI

pin. Bit4 of the OPTION register (RTE) determines if an

increment occurs on the falling (RTE = 1) or rising

(RTE = 0) edge of the signal presented to the T0CKI

pin.

(2, 4, ...., 256).

The requirement is, therefore,

N • TRT

2

4 TOSC + 40 ns

TRT ≥

≥ 2 TOSC + 20 ns, or

N

The user will notice that no requirement on T0CKI high

time or low time is specified. However, if the high time

or low time on T0CKI is too small, then the pulse may

not be detected. Hence, a minimum high or low time of

10 ns is required. In summary, the T0CKI input

requirements are:

RTS = 0: The T0CKI register or its prescaler,

respectively, will be incremented with the internal

instruction clock (= FOSC/4). The RTE bit in the

OPTION register and the T0CKI pin are "don't care" in

this case. However, the T0CKI pin must not be left

floating (tie to VDD or VSS). This prevents unintended

operation and to reduce the current consumption in

low-power applications.

TRT

=

T0CKI period ≥ (4 TOSC + 40 ns)/N

T0CKI high time ≥ 10 ns

TRTH

TRTL

As long as clocks are applied to the T0CKI (from

internal or external source, with or without prescaler),

the T0CKI register keeps incrementing and just rolls

over when the value FFh is reached. All increment

pulses for the T0CKI register are delayed by two

instruction cycles. After writing to the T0CKI register,

for example, no increment takes place for the following

two instruction cycles. This is independent if internal or

external clock source is selected. If a prescaler is

assigned to the T0CKI, the output of the prescaler will

T0CKI low time ≥ 10 ns

Delay from external clock edge: Since the prescaler

output is synchronized with the internal clocks, there is

a small delay from the time the external clock edge

occurs to the time the T0CKI is actually incremented.

This delay is between 3 TOSC and 7 TOSC (Figure 5-5).

Thus, for example, measuring the interval between two

edges (e.g., period) will be accurate within ±4 TOSC

(±200 ns @ 20 MHz).

DS40115C-page 12

1995 Microchip Technology Inc.

MTA85XXX

FIGURE 5-2: T0CKI BLOCK DIAGRAM (SIMPLIFIED)

Data bus

8

fOSC/4

0

1

0

Sync with

Internal

clocks

T0CKI (8)

T0CKI

Programmable

Prescaler

PSout

(2 cycle delay)

RTE

PSA

PS2, PS1, PS0

RTS

Note 1: Bits, RTE, RTS, PS2, PS1, PS0 and PSA are located in the OPTION register.

Note 2: The prescaler is shared with Watchdog Timer.

FIGURE 5-3: T0CKI TIMING: INT CLOCK/NO PRESCALE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W

MOVWF T0CKI

Instruction

Fetch

RT

RT+1

RT+2

NRT

NRT+1

NRT+2

NRT+3

T0

T0CKI

Read T0CKI

reads NRT+2

Read T0CKI

reads NRT

Read T0CKI

reads NRT

Read T0CKI

reads NRT+1

Read T0CKI

reads NRT+3

Write T0CKI

executed

FIGURE 5-4: T0CKI TIMING: INT CLOCK/PRESCALE 1:2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W

MOVWF T0CKI

Instruction

Fetch

RT

RT+1

NRT+1

NRT

T0CKI

Read T0CKI

reads NRT

Read T0CKI

reads NRT

Read T0CKI

reads NRT

Read T0CKI

reads NRT

Read T0CKI

reads NRT + 1

Write T0CKI

executed

FIGURE 5-5: T0CKI TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

EXT CLOCK INPUT OR

misses sampling

PRESCALER OUT (NOTE 2)

EXT CLOCK/PRESCALER

OUTPUT AFTER SAMPLING

(note 3)

INCREMENT T0CKI (Q4)

R

R + 1

R + 2

T0CKI

Notes:

1. Delay from clock input change to T0CKI increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC).

Therefore, the error in measuring the interval between two edges on T0CKI input = ± 4 TOSC maximum.

2. External clock if no prescaler selected, Prescaler output otherwise.

3. The arrows indicate the points in time where sampling occurs.

1995 Microchip Technology Inc.

DS40115C-page 13

MTA85XXX

will clear all bits except for TO and PD and then set the

Z bit and leave STATUS register as 000uu100(where

u= unchanged).

5.4

Program Counter (PC) f2

See Section 4.2

It is recommended, therefore, that only BCF, BSFand

MOVWF instructions are used to alter the STATUS

registers because these instructions do not affect any

status bit.

5.5

Stack

See Section 4.3

5.6

Status Word Register (STATUS) f3

For other instructions, affecting any status bits, see

Section "Instruction Set Summary" (Table 9-1).

This register contains the arithmetic status of the ALU,

the RESET status.

The STATUS register can be destination for any

instruction like any other register. However, the status

bits are set after the following write. Furthermore, TO

and PD bits are not writable. Therefore, the result of an

instruction with STATUS register as destination may be

different than intended. For example, CLRF STATUS

FIGURE 5-6: STATUS WORD REGISTER

R/W

PA2

R/W

PA1

R/W

PA0

R

R/W

Z

R/W R/W

DC

Register:

Address:

POR value:

STATUS W:

Writable

Readable

Unimplemented,

read as '0'

R:

U:

TO

PD

C

bit7

bit0

TO, PD are uniquely set or cleared

C: Carry/borrow bit.

For ADDWFand ADDLWinstructions.

1 =

A carry-out from the most significant bit of the result occurred

Note that a subtraction is executed by adding the two's

complement of the second operand. For rotate (RRF, RLF)

instructions, this bit is loaded with either the high or low order bit

of the source register.

No carry-out from the most significant bit of the result

0 =

Note: For borrow the polarity is reversed.

DC: Digit carry/borrow bit

For ADDWFand ADDLWinstructions.

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

Note: For borrow the polarity is reversed.

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

PD: Power down bit

1 = After power-up or by a CLRWDTinstruction

0 = By execution of the SLEEPinstruction

TO: Time-out bit

1 =

After power-up and by the CLRWDTand SLEEPinstruction

0 = A watchdog timer time-out has occurred

PA1:PA0: Two general purpose read/write bits for MTA854XX

In MTA858XX these are page select bits.

PA2: General purpose read/write bit

(reserved for future use)

DS40115C-page 14

1995 Microchip Technology Inc.

MTA85XXX

5.6.1

CARRY/BORROW AND

DIGIT CARRY/BORROW BITS:

TABLE 5-3:

TO/PD STATUS AFTER

RESET

The carry bit (C) is a carry out in addition operation

(ADDWF) and a borrow out in subtract operation

(SUBWF).

TO

PD

Reset was caused by

0

1

u

0

1

0

1

u

WDT wake-up from SLEEP

WDT time-out (not during SLEEP)

MCLR wake-up from SLEEP

Power-up

It is also affected by RRF and RLF instructions. The

following examples explain carry/borrow bit operation:

;SUBWF Example #1

;

Low pulse on MCLR input

clrf

movlw

subwf

0x1f

1

0x1f

;f(1fh)=0

;wreg=1

;f(1fh) =f(1fh)- wreg

;=0-1=FFh

Note 1: The TO and PD bit maintain their status (u)

until an event of Table 5-2 occurs. A low

pulse on the MCLR input does not change

the TO and PD status bits.

;Carry=0: Result is

;negative

;

;SUBWF Example #2

5.6.3

PROGRAM PAGE PRESELECT FOR

MTA858XX

movlw

movwf

clrw

0xFF

0x1F

;

;f(0x1F)=FFh

;wreg=0

Bits (STATUS <6:5>) are defined as page address bits

PA1:PA0 and are used to preselect a program memory

page. When executing a GOTO, CALL, or an instruc-

tion with PC as destination (e.g., MOVWF PC), PA1:PA0

are loaded into bit A10:A9 of the program counter,

selecting one of the available program memory pages.

The direct address specified in the instruction is only

valid within this particular memory page.

subwf

0x1F

;f(0x1F)=f(0x1F)- wreg

;=FFh-0=FFh

;Carry=1:Result is

;positive

;

The digit carry operates in the same way as the carry

bit, (i.e., it is a borrow in a subtract operation).

RETLW instructions do not change the page preselect

bits.

5.6.2

TIME OUT AND POWER DOWN STATUS

BITS (TO, PD)

Upon a RESET condition, PA2:PA0 are cleared to '0's.

The TO and PD bits (STATUS<4:3>) can be tested to

determine if a RESET condition has been caused by a

Watchdog Timer time-out, a power-up condition, or a

wake-up from SLEEP by the Watchdog Timer or MCLR

pin.

5.7

File Select Register (FSR) f4

Bits (STATUS <4:0>) select one of the 32 available file

registers in the indirect addressing mode (that is,

calling for the INDF register in any of the file oriented

instructions).

These status bits are only affected by events listed in

Table 5-2.

Bit7 of the FSR is read-only and is always read as a '1'.

TABLE 5-2:

EVENTS AFFECTING TO/PD

STATUS BITS

If no indirect addressing is used, the FSR can be used

as a 5-bit wide general purpose register.

Bits (STATUS <6:5>) of the FSR will always read as a

'1' for MTA854XX devices. For MTA858XX products,

bits (STATUS <6:5>) of the FSR will select the current

data memory bank (Figure 5-1).

Event

TO PD

Remarks

1

0

1

x

0

1

Power-Up

WDT Time-out

SLEEP instruction

CLRWDT instruction

No effect on PD

The lower 16 bytes of each bank are physically

identical and are always selected when bit4 of the FSR

(in case of indirect addressing) is '0', or bit4 of the direct

file register address of the currently executing

instruction is '0' (e.g., MOVWF DATAMEM).

Note 1: A WDT time-out will occur regardless of the

status of the bit TO. A SLEEP instruction

will be executed, regardless of the status of

Only if bit4 in the above mentioned cases is '1',

(STATUS <6:5>) of the FSR select one of the four

available register banks with 16 bytes each

(MTA858XX only).

the PD bit. Table 5-3 reflects the status of

TO and PD after the corresponding event.

1995 Microchip Technology Inc.

DS40115C-page 15

MTA85XXX

5.8.2

PORTB f6

5.8

I/O Registers (Ports)

8-bit I/O register. Note that RB7 is tied to SEE VDD on

MTA85XIX devices.

The I/O registers can be written and read under

program control like any other register of the register

file. However, "read" instructions (e.g., MOVF

PORTB,W) always read the I/O pins, regardless if a pin

is defined as "input" or "output." Upon a RESET, all I/O

ports are defined as "input" (= hi impedance mode) as

the I/O control registers (TRISA, TRISB) are all set to

'1's.

5.8.3

I/O INTERFACING

The equivalent circuit for an I/O port bit is shown in

Figure 5-7. All ports may be used for both input and

output operations. For input operations these ports are

non-latching. Any input must be present until read by

an input instruction (e.g., MOVF PORTB, W). The out-

puts are latched and remain unchanged until the output

latch is rewritten. To use a port pin as output, the

corresponding direction control bit (in TRISA, TRISB)

must be set to '0'. For use as an input, the

corresponding TRIS bit must be '1'. Any I/O pin can be

programmed individually as an input or output.

The execution

of

a

"TRIS f" instruction with

corresponding ’0’s in the W register is necessary to

define any of the I/O pins as output.

5.8.1

PORTA f5

4-bit I/O register. Low-order 4-bits only are used (RA3:

RA0). Bits (STATUS <7:4>) are unimplemented and

read as '0's.

FIGURE 5-7: EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN

From

D

Q

VDD

Data

Bus

Data

Latch

Q1

Write

CK

P

To Data Bus

I/O Pin

"Read"

From

W-Register

D

Q

I/O

Q2

Control

Latch

N

CK

TRIS f

Q

Set

VSS

Reset

FIGURE 5-8: I/O PORT READ/WRITE TIMING

Q4

Q3

Q1 Q2

Note:

PC + 3

NOP

This example shows a write to PORTB

followed by a read from PORTB.

PC

PC + 1

PC + 2

NOP

Instruction

fetched

MOVWF PORTB MOVF PORTB,W

Note that:

write to

PORTB

Read PORTB

data setup time = (0.25 TCY - TPD)

where TCY = instruction cycle.

TPD = propagation delay

RB7:RB0>

Therefore, at higher clock frequencies,

a write followed by a read may be problematic.

Port pin

sampled here

Instruction

executed

TPD

Execute

MOVWF PORTB

Execute

MOVF PORTB,W

Execute

NOP

DS40115C-page 16

1995 Microchip Technology Inc.

MTA85XXX

5.8.4

BIDIRECTIONAL I/O PORTS

5.8.5

SUCCESSIVE OPERATIONS ON I/O

PORTS

Some instructions operate internally as read followed

by write operations. The BCFand BSFinstructions, for

example, read the entire port into the CPU, execute the

bit operation, and re-output the result. Caution must be

used when these instructions are applied to a port

where one or more pins are used as input/outputs.

The actual write to an I/O port will happen at the end of

an instruction cycle, whereas for reading, the data must

be valid at the beginning of the instruction cycle

(Figure 5-8). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load

dependent) before the next instruction which causes

that file to be read into the CPU is executed. Otherwise,

the previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with a NOP or an other

instruction not accessing this I/O port.

For example, a BSF operation on bit5 of PORTB will

cause all eight bits of PORTB to be read into the CPU.

Then the BSF operation takes place on bit5 and

PORTB is re-output to the output latches. If another bit

of PORTB is used as a bidirectional I/O pin (say bit0)

and it is defined as an input at this time, the input signal

present on the pin itself would be read into the CPU and

re-written to the data latch of this particular pin, over-

writing the previous content. As long as the pin stays in

the input mode, no problem occurs. However, if bit0 is

switched into output mode later on, the content of the

data latch may now be unknown.

A pin actively outputting a '0' or '1' should not be driven

from external devices at the same time in order to

change the level on this pin ("wired-or", "wired-and").

The resulting high output currents may damage the

chip.

1995 Microchip Technology Inc.

DS40115C-page 17

MTA85XXX

6.4

OPTION Prescaler/T0CKI OPTION

Register

6.0

SPECIAL PURPOSE

REGISTERS

Defines prescaler assignment (T0CKI or WDT),

prescaler value, signal source and signal edge for the

T0CKI. The OPTION register is "write-only" and is 6-

bits wide.

6.1

W (Working) Register

Holds second operand in two operand instructions and/

or supports the internal data transfer.

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION

register. Upon a RESET, the OPTION register is set.

6.2

TRISA I/O Control Register For

PORTA

Only bits (STATUS <3:0>) are available. The

corresponding I/O port (f5) is only 4-bit wide.

6.3

TRISB I/O Control Register For

PORTB

The I/O control registers will be loaded with the content

of the W register, by executing of the TRIS f instruction.

A '1' in the I/O control register will put the corresponding

I/O pin into a high impedance mode. A '0' puts the con-

tents of file register PORTA or PORTB, respectively,

out on the selected I/O pins.

These registers are "write-only" and are set to all '1's

upon a RESET.

FIGURE 6-1: OPTION REGISTER

U

R/W R/W R/W R/W R/W R/W

RTS RTE PSA PS2 PS1 PS0

W:

R:

U:

Writable

Readable

Unimplemented.

Read as '0'

Register:

Address:

POR value: 111111b

OPTION

—

bit7

bit0

PRESCALER VALUE

T0CKI RATE WDT RATE

PS2:PS0

PS2

0

PS1 PS0

0

1

0

1

0

1

0

1

0

1

0

1

1 : 2

1 : 1

0

1

1 : 4

1 : 2

1 : 8

1 : 4

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

PSA: Prescaler assignment bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to T0CKI

RTE: T0CKI signal edge

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

RTS: T0CKI signal source

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

Unimplemented: reads as 0

DS40115C-page 18

1995 Microchip Technology Inc.

MTA85XXX

During a RESET the state of the microcontroller is

defined as:

7.0

RESET CONDITION

A RESET can be caused by applying power to the chip

(power-up), pulling the MCLR input "low" or by a

Watchdog Timer time-out. The device will stay in

RESET as long as the Oscillator Start-Up Timer (OST)

is active or the MCLR input is "low."

a) The oscillator is running or will be started

(power-up or wake-up from SLEEP).

b) All I/O port pins (RA3:RA0 and RB7:RB0) are

put into the hi impedance state by setting the

TRIS registers to all '1's (= input mode).

The Oscillator Start-Up Timer is activated as soon as

MCLR input is sensed to be high. This implies that in

case of Power-On Reset (POR) with MCLR tied to VDD

the OST starts from power-up. In case of WDT time-

out, it will start at the end of the time-out (since MCLR

is high). In case of MCLR reset, the OST will start when

MCLR goes high. The nominal OST time-out period is

18 ms. See Section 12.0 for detailed information on

OST and Power-On Reset.

c) The Program Counter is set to all '1's.

d) The OPTION register is set to all '1's.

e) The Watchdog Timer and its prescaler are

cleared.

f) The upper-three bits (page select bits) in the

STATUS Register are cleared.

g) RC mode only: The CLKOUT signal on the

OSC2 pin is held at a"low" level.

TABLE 7-1:

RESET CONDITION FOR REGISTERS

Address

MCLR Reset during:

- normal operation

Wake up from

- SLEEP

Register

Power-on Reset

SLEEP through

WDT time-out

during normal

operation

xxxx xxxx

0011 1111

—

uuuu uuuu

0011 1111

—

uuuu uuuu

0011 1111

—

W

OPTION

INDF

—

00h

01h

02h

xxxx xxxx

uuuu uuuu

T0CKI

PC

1FFh MTA854XX

7FFh MTA858XX

1FFh MTA854XX

7FFh MTA858XX

1FFh MTA854XX

7FFh MTA858XX

0001 1xxx

xxxx xxxx

000? ?uuu

uuuu uuuu

uuu? ?uuu

uuuu uuuu

STATUS

FSR

03h

04h

05h

06h

PORTA

PORTB

Legend: u = unchanged, x = unknown, reads as '0', ? = value depends on condition.

1995 Microchip Technology Inc.

DS40115C-page 19

MTA85XXX

1. MOVLW 'xx0x0xxx'b ; Select internal

; clock and select new

8.0

PRESCALER

An 8-bit counter is available as a prescaler for the

T0CKI, or as a post-scaler for the Watchdog Timer.

(Figure 8-1). For simplicity, this counter is being

referred to as "prescaler" throughout this data sheet.

Note that there is only one prescaler available which is

mutually exclusively shared between the T0CKI and

the Watchdog Timer. Thus, a prescaler assignment for

the T0CKI means that there is no prescaler for the

Watchdog Timer, and vice-versa.

2. OPTION

; prescaler value. If

; new prescale value

; is = '000' or '001',

; then select any

; other prescale

; value temporarily.

; Clear T0CKI and

; prescaler.

3. CLRF 1

4. MOVLW

xxxx1xxx'b ; Select WDT, do not

; change prescale

; value.

The PSA and PS0-PS2 bits in the OPTION register

determine the prescaler assignment and pre-scale

ratio. When assigned to the T0CKI, all instructions

writing to the T0CKI (e.g., CLRF T0CKI, MOVWF

T0CKI, BSF T0CKI,x....etc.) will clear the prescaler.

When assigned to WDT, a CLRWDTinstruction will clear

the prescaler along with the Watchdog Timer.

5. OPTION

6. CLRWDT

;

; Clears WDT and

; prescaler.

7. MOVLW 'xxxx1xxx'b ; Select new prescale

; value.

8. OPTION

;

Steps 1 and 2 are only required if an external T0CKI

source is used. Steps 7 and 8 are necessary only if the

desired prescale value is '000' or '001'.

8.1

Switching Prescaler Assignment

Changing prescaler from T0CKI to WDT

Changing prescaler from WDT to T0CKI

The prescaler assignment is fully under software

control, (i.e., it can be changed "on the fly" during

program execution). To avoid an unintended device

RESET, the following instruction sequence must be

executed when changing the prescaler assignment

from T0CKI to WDT:

To change prescaler from WDT to T0CKI use the fol-

lowing sequence:

1. CLRWDT

; Clear WDT and

; prescaler.

2. MOVLW

'xxxx0xxx'b; Select T0CKI, new

; prescale value

; and clock source

;

3. OPTION

FIGURE 8-1: BLOCK DIAGRAM T0CKI/WDT PRESCALER

Data Bus

8

CLKOUT (= Fosc/4)

M

U

X

1

0

1

M

U

X

T0CKI

SYNC

T0CKI

2

Cycles

RTE

RTS

PSA

0

1

8-bit Counter

8 - to - 1MUX

M

U

X

Watchdog

timer

PS2:PS0

PSA

1

0

WDT Enable

EEPROM Fuse

M U X

PSA

Note: RTS, RTE, PSA, PS2-PS0 are bits

in the OPTION register.

WDT

Time-out

DS40115C-page 20

1995 Microchip Technology Inc.

MTA85XXX

Notes to Table 9-1

9.0

BASIC INSTRUCTION SET

SUMMARY

Note 1: The ninth bit of the program counter will be

forced to a '0' by any instruction that writes

to the PC except for GOTO (e.g., CALL,

MOVWF PC, ...etc.). See Section 5.6.3

for details.

Each instruction is a 12-bit word divided into an

OPCODE which specifies the instruction type and one

or more operands which further specify the operation of

the instruction. The Instruction Set Summary in

Table 9-1 lists byte-oriented, bit-oriented, and literal

and control operations.

Note 2: When an I/O register is modified as a func-

tion of itself (e.g., MOVF PORTB,1), the

value used will be that value present on the

pins themselves. For example, if the data

latch is '1' for a pin configured as output and

is driven low by an external device, the data

will be written back with a '0'.

For byte-oriented instructions, 'f' represents a file

register designator and 'd' represents a destination

designator. The file register designator specifies which

one of the file registers is to be utilized by the

instruction.

Note 3: The instruction "TRIS f", where f = PORTA,

PORTB, or PORTC causes the contents of

the W register to be written to the three-

state latches of the specified file (port). A '1'

forces the pin to a hi impedance state and

disables the output buffers.

The destination designator specifies where the result of

the operation is to be placed. If 'd' is '0', the result is

placed in the W register. If 'd' is '1', the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, 'b' represents a bit field

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

file in which the bit is located.

Note 4: If this instruction is executed on the T0CKI

register (and, where applicable, d = 1), the

prescaler will be cleared if assigned to the

T0CKI.

For literal and control operations, 'k' represents an

eight or nine bit constant or literal value.

All instructions are executed within one single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles. One instruction cycle consists of four

oscillator periods. Thus, for an oscillator frequency of

4 MHz, the normal instruction execution time is 1 µs. If

a conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2 µs.

1995 Microchip Technology Inc.

DS40115C-page 21

MTA85XXX

TABLE 9-1:

INSTRUCTION SET SUMMARY

(5)

d

(4-0)

(11-6)

f(FILE #)

OPCODE

BYTE-ORIENTED FILE REGISTER OPERATIONS

d = 0 for destination W

d = 1 for destination f

Mnemonic,

Operands

Status

Affected

Instruction-Binary (Hex) Name

Operation

Notes

0001 11df ffff 1Cf Add W and f

0001 01df ffff 14f AND W and f

0000 011f ffff 06f Clear f

ADDWF f, d W + f → d

ANDWF f, d W f → d

C,DC,Z

1,2,4

2,4

4

Z

CLRF

CLRW

COMF

DECF

f

-

0 → f

Z

0000 0100 0000 040 Clear W

0010 01df ffff 24f Complement f

0000 11df ffff 0Cf Decrement f

0 → W

Z

f, d f → d

Z

2,4

1,4

f, d f -1 → d

Z

0010 11df ffff 2Cf Decrement f,Skip if Zero DECFSZ f, d f - 1 → d, skip if zero

None

Z

0010 10df ffff 28f Increment f

0011 11df ffff 3Cf Increment f,Skip if zero

0001 00df ffff 10f Inclusive OR W and f

0010 00df ffff 20f Move f

INCF

f, d f + 1 → d

INCFSZ

IORWF

MOVF

MOVWF

NOP

f, d f + 1 → d, skip if zero

f, d W f → d

f, d f → d

None

Z

0000 001f ffff 02f Move W to f

0000 0000 0000 000 No Operation

0011 01df ffff 34f Rotate left f

0011 00df ffff 30f Rotate right f

0000 10df ffff 08f Subtract W from f

0011 10df ffff 38f Swap halves f

0001 10df ffff 18f Exclusive OR W and f

f

-

W → f

None

C

-

RLF

f, d f(n) → d(n+1), C → d(0), f(7) → C

f, d f(n) → d(n-1), C → d(7), f(0) → C

2,4

RRF

C

SUBWF f, d f - W → d [f + W + 1 → d]

SWAPF f, d f(0-3) ↔ f(4-7) → d

C,DC,Z

None

Z

1,2,4

2,4

XORWF f, d W f → d

2,4

(7-5)

(4-0)

(11-8)

BIT-ORIENTED FILE REGISTER OPERATIONS

f(FILE #)

OPCODE

b(bit #)

Mnemonic,

Operation

Operands

Status

Affected

Instruction-Binary (Hex) Name

Notes

0100 bbbf ffff 4bf Bit Clear f

BCF

f, b 0 → f(b)

f, b 1 → f(b)

None

2,4

0101 bbbf ffff 5bf Bit Set f

BSF

0110 bbbf ffff 6bf Bit Test f,Skip if Clear

0111 bbbf ffff 7bf Bit Test f, Skip if Set

BTFSC

BTFSS

f, b Test bit (b) in file (f): Skip if clear

f, b Test bit (b) in file (f): Skip if set

(7-0)

(11-8)

LITERAL AND CONTROL OPERATIONS

k(literal)

OPCODE

Mnemonic,

Operands

Status

Affected

Instruction-Binary (Hex) Name

Operation

Notes

1110 kkkk kkkk Ekk AND Literal and W

1001 kkkk kkkk 9kk Call subroutine

0000 0000 0100 004 Clear Watchdog timer

ANDLW

CALL

k

-

k

W→ W

Z

PC + 1 → Stack, k → PC

None

1

CLRWDT

0 → WDT (and prescaler, if assigned) TO, PD

101k kkkk kkkk Akk Go To address (k is 9 bit) GOTO

k

-

k → PC (9 bits)

W → W

None

Z

1101 kkkk kkkk Dkk Incl. OR Literal and W

1100 kkkk kkkk Ckk Move Literal to W

0000 0000 0010 002 Load OPTION register

IORLW

k

MOVLW

OPTION

k → W

None

TO, PD

None

Z

W → OPTION register

k → W, Stack → PC

0 → WDT, stop oscillator

W→ I/O control register f

1000 kkkk kkkk 8kk Return,place Literal in W RETLW

k

-

0000 0000 0011 003 Go into standby mode

0000 0000 0fff 00f Tri-State port f

1111 kkkk kkkk Fkk Excl. OR Literal and W

Note 1: See previous page.

SLEEP

TRIS

f

3

XORLW

k

W → W

DS40115C-page 22

1995 Microchip Technology Inc.

MTA85XXX

assigned to the WDT (under software control) by

writing to the OPTION register. Thus, time-out periods

up to 2.3 seconds can be realized.

10.0 WATCHDOG TIMER (WDT)

The watchdog timer is realized as a free running on-

chip RC oscillator which does not require any external

components. This RC oscillator is separate from the

RC oscillator of the OSC1/CLKIN pin. That means that

the WDT will run even if the clock on the OSC1/CLKIN

and OSC2/CLKOUT pins of the device have been

stopped (i.e., by executing the SLEEP instruction).

During normal operation a WDT time-out generates a

device RESET. If the device is in SLEEP mode, a WDT

time-out causes the device to wake-up and continue

with normal operation. The WDT can be permanently

disabled by programming the configuration bit WDTE

as a '0'.

The CLRWDT and SLEEP instructions clear the WDT

and the postscaler (if assigned to the WDT) and pre-

vent it from timing out and generating a device RESET.

The TO bit (STATUS<4>) will be cleared upon a WDT

time-out.

10.2

WDT Programming Considerations

At worst case conditions (VDD = Min., Temperature =

Max., max. WDT prescaler) it may take several

seconds before a WDT time-out occurs.

10.1

WDT Period

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). These periods vary with temperature,

VDD and process variations from part to part (see DC

specifications). If longer time-out periods are desired, a

prescaler with a division ratio of up to 1:128 can be

FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source

(Figure 6-6)

0

M

U

X

Postscaler

1

Watchdog

Timer

8 - to - 1 MUX

PS2:PS0

PSA

WDT Enable

EPROM Fuse

To TMR0 (Figure 6-6)

1

0

MUX

PSA

Note: PSA and PS2:PS0 are bits in the OPTION register.

WDT

Time-out

TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

FOSC1 FOSC0

PS1 PS0

Bit 0

Config. Word

OPTION

CP

—

CP

—

CP

WDTE

PS2

T0CS

T0SE

PSA

Note 1: CP7:CP4 are used by the PIC16CCR58A only. Unused in all other devices.

2: Shaded cells are not used by the Watchdog Timer.

1995 Microchip Technology Inc.

DS40115C-page 23

MTA85XXX

TABLE 11-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

11.0 OSCILLATOR

CONFIGURATIONS

Osc

Type

Resonator Cap. Range Cap. Range

11.0.1

OSCILLATOR TYPES

Freq.

C1

C2

The PIC16C5X can be operated in four different

oscillator modes. The user can program two

configuration bits (FOSC1:FOSC0) to select one of

these four modes:

XT

455 kHz

2.0 MHz

4.0 MHz

22-100 pF

15-68 pF

22-100 pF

15-68 pF

HS

8.0 MHz

10-68 pF

• LP:

• XT:

• HS:

• RC:

Low Power Crystal

These values are for design guidance only. Since

each resonator has its own characteristics, the user

should consult the resonator manufacturer for

appropriate values of external components.

Crystal/Resonator

High Speed Crystal/Resonator

Resistor/Capacitor

TABLE 11-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

Note: The MTA854XX operates at 4 MHz and

the MTA858XX operates up to 10 MHz.

Osc

Type

Resonator Cap. Range Cap. Range

11.0.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

Freq.

C1

C2

LP

32 kHz†

200 kHz

33-68 pF

15-47 pF

33-68 pF

15-47 pF

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 11-1). The

PIC16C5X oscillator design requires the use of a

parallel cut crystal. Use of a series cut crystal may give

XT

100 kHz

2 MHz

4 MHz

47-100 pF

15-33 pF

10-33 pF

47-100 pF

15-33 pF

10-33 pF

HS

8 MHz

15-47 pF

a

frequency out of the crystal manufacturers

† For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended.

specifications. When in XT, LP or HS modes, the device

can have an external clock source drive the OSC1/

CLKIN pin (Figure 11-2).

These values are for design guidance only. Rs may

be required in HS mode as well as XT mode to avoid

overdriving crystals with low drive level specification.

Since each crystal has its own characteristics, the

user should consult the crystal manufacturer for

appropriate values of external components.

FIGURE 11-1: CRYSTAL /CERAMIC

RESONATOR OPERATION

(HS, XT OR LP OSC

CONFIGURATION)

OSC1

PIC16C5X

C1

XTAL

OSC2

SLEEP

To internal

logic

RF

RS

C2

Note1

See Table 11-1 and Table 11-2 for recommended

values of C1 and C2.

Note 1: A series resistor may be required for AT

strip cut crystals.

FIGURE 11-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

OSC MODE)

OSC1

OSC2

Clock from

ext. system

PIC16C5X

Open

DS40115C-page 24

1995 Microchip Technology Inc.

MTA85XXX

11.1.1 RC OSCILLATOR

11.1

External Crystal Oscillator circuit

For timing insensitive applications the RC device option

offers additional cost savings. RC oscillator frequency

is a function of the supply voltage, the resistor (Rext)

and capacitor (Cext) values, and the operating temper-

ature. In addition to this, the oscillator frequency will

vary from unit to unit due to normal process parameter

variation. Furthermore, the difference in lead frame

capacitance between package types will also affect the

oscillation frequency, especially for low Cext values.

The user also needs to take into account variation due

to tolerance of external R and C components used.

Figure 11-5 shows how the R/C combination is con-

nected to the PIC16C5X. For Rext values below 2.2

kΩ, the oscillator operation may become unstable, or

stop completely. For very high Rext values (e.g., 1 MΩ)

the oscillator becomes sensitive to noise, humidity and

leakage. Thus, we recommend keeping Rext between

3 kΩ and 100 kΩ.

A prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built. Prepack-

aged oscillators provide a wide operating range and

better stability. A well-designed crystal oscillator will

provide good performance with TTL gates. Two types

of crystal oscillator circuits can be used; one with series

resonance, or one with parallel resonance.

Figure 11-3 shows implementation of

a parallel

resonant oscillator circuit. The circuit is designed to use

the fundamental frequency of the crystal. The 74AS04

inverter performs the 180-degree phase shift that a par-

allel oscillator requires. The 4.7 kΩ resistor provides

the negative feedback for stability. The 10 kΩ potenti-

ometers bias the 74AS04 in the linear region. This cir-

cuit could be used for external oscillator designs.

FIGURE 11-3: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or pack-

age lead frame capacitance.

+5V

To Other

Devices

PIC16C5X

10k

74AS04

4.7k

CLKIN

74AS04

See Section 15.0 for RC frequency variation from part

to part due to normal process variation. The variation is

larger for larger R (since leakage current variation will

affect RC frequency more for large R) and for smaller

C (since variation of input capacitance will affect RC

frequency more).

10k

XTAL

10k

20 pF

See Section 15.0 for variation of oscillator frequency

due to VDD for given Rext/Cext values as well as

frequency variation due to operating temperature for

given R, C, and VDD values.

Figure 11-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a 180°

phase shift in a series resonant oscillator circuit. The

330 Ω resistors provide the negative feedback to bias

the inverters in their linear region.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test

purposes or to synchronize other logic.

FIGURE 11-5: RC OSCILLATOR MODE

FIGURE 11-4: EXTERNAL SERIES

RESONANT CRYSTAL

VDD

OSCILLATOR CIRCUIT

Rext

Internal

To Other

clock

OSC1

N

Devices

330Ω

PIC16C5X

74AS04

PIC16C5X

Cext

VSS

CLKIN

0.1 µF

Fosc/4

XTAL

OSC2/CLKOUT

1995 Microchip Technology Inc.

DS40115C-page 25

MTA85XXX

Device Reset Timer circuit are closely related. On

power-up the reset latch is set and the DRT is reset.

The DRT timer begins counting once it detects MCLR

to be high. After the time-out period, which is typically

18 ms, it will reset the reset-latch and thus end the on-

chip reset signal.

12.0 RESET

The PIC16C5X differentiates between various kinds of

resets:

• Power-On Reset (POR)

• MCLR reset during normal operation

• MCLR reset during SLEEP

• WDT time-out reset

Figure 12-2 and Figure 12-3 are two power-up

situations with relatively fast rise time on VDD. VDD is

allowed to rise and stabilize (Figure 12-2) before

bringing MCLR high. The chip will actually come out of

reset (TDRT msec) after MCLR goes high. The on-chip

Power-On Reset feature (Figure 12-3) is being used

(MCLR and VDD are tied together). VDD is stable before

the start-up timer times out and there is no problem in

getting a proper reset. Figure 12-4 depicts a potentially

problematic situation where VDD rises too slowly. In this

situation, when the start-up timer times out, VDD has

not reached the VDD (min) value and the chip is, there-

fore, not guaranteed to function correctly.

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in all

other resets. Most other registers are reset to a “reset

state” on Power-On Reset (POR), MCLR or a WDT

reset. Note that the PIC16C5X does not differentiate

between a WDT reset during SLEEP or during normal

operation. The TO and PD bits are set or cleared

depending upon the reset situation (Table 12-1). These

bits may be used to determine the nature of the reset.

See Table 12-3 for a full description of reset states of all

registers.

To summarize, the on-chip POR is guaranteed to work

if the rate of rise of VDD is no slower than 0.05V/ms, and

VDD starts from 0V. The on-chip POR time delay is too

short for low frequency crystals which require much

longer than 18 ms to start-up and stabilize. For such sit-

uations, we recommend that external RC circuits be

used to achieve longer POR delay times.

Figure 12-1 shows the simplified block diagram of the

on-chip reset circuit.

12.1

Power-On Reset (POR) and Device-

Reset Timer (DRT)

12.1.1 POWER-ON RESET (POR)

The PIC16C5X family incorporates an on-chip Power-

On Reset (POR) circuitry which provides an internal

chip reset for most power-up situations. To use this fea-

ture the user merely needs to tie the MCLR/VPP pin to

VDD. Figure 12-8 shows the electrical structure of

TMR0 inputs. The Power-On Reset circuit and the

FIGURE 12-1: ON-CHIP RESET CIRCUIT BLOCK DIAGRAM

Power-Up

Detect

POR (Power-On Reset)

VDD

MCLR/VPP pin

WDT Time-out

8-bit Async

RESET

S

R

Q

On-Chip

RC OSC

Ripple Counter

(Start-up Timer)

CHIP RESET

DS40115C-page 26

1995 Microchip Technology Inc.

MTA85XXX

12.1.2 DEVICE RESET TIMER (DRT)

12.1.3 TIME-OUT SEQUENCE

The Device Reset Timer provides a fixed 18 ms

nominal time-out on RESET. The Device Reset Timer

operates with an internal RC oscillator. The processor

is kept in RESET as long as the DRT is active. The DRT

delay allows VDD to rise above VDD min., and allows

the oscillator to stabilize.

Table 12-2 lists the reset conditions for the special

function registers while Table 12-3 lists the reset

conditions for all the registers.

TABLE 12-1: TO/PD STATUS AFTER

RESET

Oscillator circuits based on crystals or ceramic

resonators require a certain time after power-up to

establish a stable oscillation. The on-chip DRT keeps

the device in a RESET condition for approximately

18 ms after the voltage on the MCLR/VPP pin has

reached a logic high (VIHMC) level. Thus, external RC

networks connected to the MCLR input are not required

in most cases, allowing for savings in cost-sensitive

and/or space restricted applications.

TO

PD

RESET was caused by

0

1

u

0

1

0

1

u

WDT wake-up from SLEEP

WDT time-out (not during SLEEP)

MCLR wake-up from SLEEP

Power-up

= Low pulse on MCLR input

The TO and PD bits maintain their status (u) until a

reset occurs. A low-pulse on the MCLR input does

not change the TO and PD status bits.

The Device Reset time delay will vary from chip to chip

and due to VDD, temperature, and process variation.

The DRT will also be triggered upon a WDT time-out.

This is particularly important for applications using the

WDT to waken the PIC16C5X from SLEEP

automatically.

TABLE 12-2: RESET CONDITIONS FOR SPECIAL REGISTERS

STATUS

Addr: 03h

PCL

Addr: 02h

Condition

0001 1xxx

000u uuuu(1)

0001 0uuu

1111 1111

Power-On Reset

MCLR reset during normal operation

MCLR reset during SLEEP

0000 0uuu

WDT reset during SLEEP

0000 1uuu

WDT reset during normal operation

Legend: u = unchanged, x = unknown, -= unimplemented read as '0'.

Note 1: The TO and PD bits retain their last value until one of the other reset conditions occur.

2: The CLRWDTinstruction will set the TO and PD bits

TABLE 12-3: RESET CONDITIONS FOR ALL REGISTERS

Register

Address

N/A

Power-on Reset

xxxx xxxx

MCLR or WDT Reset

uuuu uuuu

1111 1111

--11 1111

W

1111 1111

TRIS

N/A

--11 1111

OPTION

INDF

N/A

00h

—

xxxx xxxx

1111 1111

0001 1xxx

xxxx xxxx

---- xxxx

xxxx xxxx

uuuu uuuu

1111 1111

000? ?uuu (1)

uuuu uuuu

---- uuuu

uuuu uuuu

TMR0

PCL

01h

02h

STATUS

FSR

03h

04h

PORTA

PORTB

PORTC

05h

06h

07h

General Purpose

register files

08-7Fh

Legend:

u

= unchanged,

x = unknown, -= unimplemented read as '0', ? = value depends on condition.

Note 1: See Table 12-2 for reset value for specific conditions.

1995 Microchip Technology Inc.

DS40115C-page 27

MTA85XXX

FIGURE 12-2: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): Case 1

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

FIGURE 12-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): Case 2

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

DS40115C-page 28

1995 Microchip Technology Inc.

MTA85XXX

FIGURE 12-5: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

FIGURE 12-6: BROWN-OUT PROTECTION

CIRCUIT 1

VDD

33k

D

R

R1

10k

MCLR

40k

PIC16C5X

C

PIC16C5X

Note 1: External Power-On Reset circuit is

required only if VDD power-up is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

This circuit will activate reset when VDD goes

below Vz + 0.7V (where Vz = Zener voltage).

FIGURE 12-7: BROWN-OUT PROTECTION

CIRCUIT 2

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not

exceed 0.2V (max leakage current spec on

MCLR pin is 5 µA). A larger voltage drop

will degrade VIH level on the MCLR/VPP

pin.

3: R1 = 100Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor

C in the event of MCLR/VPP pin breakdown

due to ESD or EOS.

VDD

R1

Q1

MCLR

R2

40k

PIC16C5X

This brown-out circuit is less expensive, although

less accurate. Transistor Q1 turns off when VDD

is below a certain level such that:

R1

= 0.7V.

VDD •

R1 + R2

FIGURE 12-8: ELECTRICAL STRUCTURE OF THE MCLR/VPP AND T0CKI PINS

RIN

MCLR/VPP

and

Schmitt Trigger

Input Buffer

N

T0CKI pins

VSS

1995 Microchip Technology Inc.

DS40115C-page 29

MTA85XXX

13.0.1 WAKE-UP FROM SLEEP

13.0 POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing

SLEEPinstruction.

a

The device can wake from SLEEP through one of the

following events:

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared, and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

1. An external reset input on the MCLR/VPP pin.

2. A WDT time-out reset (if WDT was enabled).

Both of these events cause a device reset. The TO and

PD bits can be used to determine the cause of device

reset. The TO bit is cleared if a WDT time-out occurred

(and caused wake-up). The PD bit, which is set on

power-up, is cleared when SLEEPis invoked.

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR/VPP pin low.

The WDT is cleared when the device wakes from

SLEEP, regardless of the wake-up source.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

MCLR/VPP pin must be at a logic high level (VIHMC).

DS40115C-page 30

1995 Microchip Technology Inc.

MTA85XXX

14.2

Code Protection

14.0 CONFIGURATION FUSES

The configuration EPROM consists of four EPROM

fuses.

The code in the program memory can be protected by

clearing the code protect bits.

Two are for the selection of the oscillator type, one is

the watchdog timer enable fuse and one is the code

protection fuse.

In code protected mode, the configuration word will not

be protected, allowing reading of all bits.

14.2.1 PIC16C54A AND PIC16C58A

FIGURE 14-1: CONFIGURATION WORD

Once code protected, all memory locations read out in

a scrambled fashion. For EPROM devices, program

memory locations 40h and above cannot be further

programmed. However, the first 64 locations, 00h -

3Fh, may be programmed. These locations are not

considered secure.

_

Register: FUSES

Address: N/A

OT0

CP WDTE OT1

11

bit0

OT1:OT0: OSC selection fuses

11: RC oscillator

10: HS oscillator

14.2.2 PIC16CR58A

01: XT oscillator

00: LP oscillator

In a protected device, program memory locations 00h-

3Fh read out normally. Locations 40h and higher

cannot be read out.

WDTE: WDT enable fuse

1 = WDT enabled

0 = WDT disabled

CP: Code protection fuse

1 = Code protection off

0 = All memory is code

protected

Unimplemented

14.1

ID Locations

Four memory locations are designated as ID locations

where the user can store checksum or other code-iden-

tification numbers. These locations are not accessible

during normal execution but are readable and writable

during program/verify.

Use only the lower 4-bits of the ID locations and always

program the upper 8-bits as '1's.

* Note: Microchip will assign a unique pattern

number for QTP and SQTP requests and

for ROM devices. This pattern number will

be unique and traceable to the submitted

code.

1995 Microchip Technology Inc.

DS40115C-page 31

MTA85XXX

15.0 ELECTRICAL CHARACTERISTICS

15.1

Absolute Maximum Ratings*

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage Temperature.............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR).................................................... -0.6V to (VDD + 0.6V)

Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V

Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V

Total power Dissipation (Note 1) ..........................................................................................................................800 mW

Maximum Current out of VSS pin...........................................................................................................................150 mA

Maximum Current into VDD pin................................................................................................................................50 mA

Maximum Current into an input pin ..................................................................................................................................±500 µA

Maximum Output Current sunk by any I/O pin ........................................................................................................25 mA

Maximum Output Current sourced by any I/O pin...................................................................................................20 mA

Maximum Output Current sourced by a single I/O port (PortA or B).......................................................................40 mA

Maximum Output Current sunk by a single I/O port (PortA or B) ............................................................................50 mA

Note 1: Total power dissipation should not exceed 800 mW for the package. Power dissipation is calculated as fol-

lows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,

a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling

this pin directly to VSS.

* Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operation listings of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

TABLE 15-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC16C54A-04

RC

VDD: 3.0V to 6.25V

IDD: 2.4 mA max. at 5.5V

IPD: 4 µA max. at 3.0V WDT dis

Freq: 4 MHz max.

XT

HS

LP

VDD: 3.0V to 6.25V

IDD 2.4 mA max. at 5.5V

IPD: 4 µA max. at 3.0V WDT dis

Freq: 4 MHz max.

VDD: 4.5V to 5.5V

IDD: 2.4 mA typ. at 5.5V

IPD: 0.25 µA typ. at 3.0V WDT dis

Freq: 4 MHz max.

VDD: 3.0V to 6.25V

IDD: 14 µA typ. at 32kHz, 3.0V

IPD: 0.25 µA typ. at 3.0V WDT dis

Freq: 200 kHz max.

* Note: The shaded sections indicate oscillator

selections which are tested for functionality,

but not for MIN/MAX specifications. It is

recommended that the user select the

device

type

that

guarantees

the

specifications required.

DS40115C-page 32

1995 Microchip Technology Inc.

MTA85XXX

15.2

DC Characteristics

TABLE 15-2: DC CHARACTERISTICS OF MICROCONTROLLER MTA854XX-04 (INDUSTRIAL)

Standard Operating Conditions

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC CHARACTERISTICS

Power Supply Pins

Characteristic

Sym

Min Typ* Max Units

Conditions

XT, RC and LP options

HS option

Supply Voltage

VDD

3.0

4.5

6.25

5.5

V

RAM Data Retention

Voltage (Note 3)

VDR

1.5

V

Device in SLEEP mode

VDD start voltage to

guarantee Power-On Reset

VPOR

VSS

V

See POR section in microcontroller datasheet

for details on Power-On Reset

VDD rise rate to guarantee

Power-On Reset

SVDD 0.05*

IDD

V/ms See POR section in microcontroller datasheet

for details on Power-On Reset

Supply Current (Note 2)

XT and RC options (C-04)

1.8 2.4

mA FOSC = 4 MHz, VDD = 5.5V

HS option (C-10)

5.8

17

13

70

mA FOSC = 10 MHz, VDD = 5.5V

LP option, Industrial, EEPROM standby

µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled

Power Down Current (Note 4)

WDT enabled

WDT disabled

IPD

5

13

14

5

µA VDD = 3.0V, Industrial

*

These parameters are characterized but not tested.

Note 1: Data in the column labeled "Typ" is based on characterization results at 25°C. These parameters are for

design guidance only and are not tested for, or guaranteed by Microchip Technology.

Note 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1= external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, RT = VDD,

MCLR = VDD; WDT enabled/disabled as specified; EEPROM in write condition (except LP mode).

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP

mode and SDA and SCL are tied to VSS.

Note 3: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

Note 4: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS;

SDA and SCL tied to VSS.

Note 5: Does not include current through Rext. The current through the resistor can be estimated by the formula

Ir = VDD/2Rext (mA) with Rext in kΩ.

1995 Microchip Technology Inc.

DS40115C-page 33

MTA85XXX

TABLE 15-3: DC CHARACTERISTICS OF MICROCONTROLLER MTA858XX-04 (INDUSTRIAL)

MTA858XX-10 (INDUSTRIAL)

Standard Operating Conditions

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC CHARACTERISTICS

Power Supply Pins

Characteristic

Sym

Min Typ* Max Units

Conditions

XT, RC and LP options

Supply Voltage

VDD

3.0

4.5

6.25

5.5

V

HS option

RAM Data Retention

Voltage (Note 3)

VDR

1.5

V

Device in SLEEP mode

VDD start voltage to

guarantee Power-On Reset

VPOR

VSS

V

See POR section in microcontroller datasheet

for details on Power-On Reset

VDD rise rate to guarantee

Power-On Reset

SVDD 0.05*

IDD

V/ms See POR section in microcontroller datasheet

for details on Power-On Reset

Supply Current (Note 2)

XT and RC options (C-04)

1.8 2.4

mA FOSC = 4 MHz, VDD = 5.5V

HS option (C-10)

5.8

17

13

40

mA FOSC = 4 MHz, VDD = 5.5V

LP option, Industrial, EEPROM standby

µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled

Power Down Current (Note 4)

WDT enabled

WDT disabled

IPD

5

0.8

14

12

µA VDD = 3.0V, Industrial

*

These parameters are characterized but not tested.

Note 1: Data in the column labeled "Typ" is based on characterization results at 25°C. These parameters are for

design guidance only and are not tested for, or guaranteed by Microchip Technology.

Note 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1= external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, except RB7 driving '1'

for SEE VDD, RT = VDD, MCLR = VDD; WDT enabled/disabled as specified; EEPROM in write condition

(except LP mode).

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP

mode and SDA and SCL are tied to VSS.

Note 3: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

Note 4: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS;

SDA and SCL tied to VSS.

Note 5: Does not include current through Rext. The current through the resistor can be estimated by the formula

Ir = VDD/2Rext (mA) with Rext in kΩ.

DS40115C-page 34

1995 Microchip Technology Inc.

MTA85XXX

TABLE 15-4: DC CHARACTERISTICS OF INPUTS/OUTPUTS:

MTA854XX-04 (INDUSTRIAL)

MTA858XX-04 (INDUSTRIAL)

MTA858XX-10 (INDUSTRIAL

Standard Operating Conditions

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC CHARACTERISTICS

All Pins Except Power Supply

Characteristic

Sym

Min Typ

Max

Units Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt trigger)

T0CKI (Schmitt trigger)

OSC1 (Schmitt trigger)

OSC1, SCL

VIL

VSS

Vss

0.2 VDD

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

RC option only (Note 5)

XT, HS and LP options

Input High Voltage

I/O ports

VIH

0.45 VDD

VDD

V

For all VDD (Note 6)

4.0V < VDD ≤ 5.5V (Note 6)

VDD > 5.5V

2.0

0.36VDD

0.85 VDD

0.7 VDD

MCLR (Schmitt trigger)

T0CKI (Schmitt trigger)

OSC1 (Schmitt trigger)

OSC1, SCL

RC option only (Note 5)

XT, HS, and LP options

Input Leakage Current (Note 4)

I/O ports

MCLR

T0CKI

IIL

-1

-5

0.5

+1

µA VSS ≤ VPIN ≤ VDD, Pin at hi-impedance

µA VPIN = VSS + 0.25V (Note 3)

µA VPIN = VDD (Note 3)

0.5

+5

+3

10

-3

-10

µA VSS ≤ VPIN ≤ VDD

OSC1

SDA, SCL

µA VSS ≤ VPIN ≤ VDD

µA XT, HS and LP options

Output Low Voltage

I/O ports

OSC2/CLKOUT

(RC option only)

SDA

Output High Voltage

I/O ports (Note 4)

OSC2/CLKOUT

(RC option only)

VOL

VOH

0.6

V

IOL = 8.7 mA, VDD = 4.5V

0.6

0.4

V

IOL = 1.6 mA, VDD = 4.5V

IOL = 3.0 mA, VDD = 3.0V

VDD-0.7

V

IOH = -5.4 mA, VDD = 4.5V

IOH = -1.0 mA, VDD = 4.5V

Note 1: Data in “Typ” column is based on characterization results at 25°C. These parameters are for design guidance

only and are not tested for, or guaranteed by Microchip Technology.

Note 2: Total power dissipation as stated under absolute maximum ratings must not be exceeded.

Note 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

Note 4: Negative current is defined as coming out of the pin.

Note 5: In RC oscillator mode, the OSC1 pin is a Schmitt trigger input. It is not recommended that the microcontroller

be driven with external clock in RC mode.

Note 6: The user may use better of the two specifications.

1995 Microchip Technology Inc.

DS40115C-page 35

MTA85XXX

15.3

AC Characteristics

TABLE 15-5: AC CHARACTERISTICS OF MICROCONTROLLER: MTA854XX-04 (INDUSTRIAL)

MTA858XX-04 (INDUSTRIAL)

MTA858XX-10 (INDUSTRIAL)

Standard Operating Conditions

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

AC CHARACTERISTICS

Characteristic

Sym

Min

Typ

Max

Units

Conditions

External CLOCKIN

Frequency (Note 2)

FOSC

DC

0.1

4

DC

1.0

0.2

100

4

20

40

4

20

40

MHz RC mode

MHz XT mode

MHz HS mode (Com/Ind) (Note 5)

kHz LP mode

MHz RC mode

MHz XT mode

MHz HS mode (Com/Ind) (Note 5)

kHz LP mode

µs RC mode

µs XT mode

µs HS mode (Note 5)

µs LP mode

Oscillator Frequency (Note 2)

Instruction Cycle Time (Note 2)

FOSC

TCY

4/Fosc DC

DC

External Clock in Timing (Note 4)

Clock in (OSC1) High or Low time

XT oscillator type

LP oscillator type

HS oscillator type

TCKHLXT

TCKHLLP

TCKHLHS

50*

2*

20*

ns

µs

ns

Clock in (OSC1) Rise or fall time

XT oscillator type

LP oscillator type

TCKRFXT

TCKRFLP

TCKRFHS

25*

50*

25*

ns

HS oscillator type

RESET Timing

MCLR Pulse Width (low)

T0CKI Input Timing, No prescaler

T0CKI High Pulse Width

T0CKI Low Pulse Width

TMCL

100*

ns

TRTH

TRTL

0.5 TCY+20*

ns Note 3

* Guaranteed by characterization but not tested.

Note 1: Data in the column labeled "Typ" is based on characterization results at 25°C. This data is for design guidance

only and is not tested for, or guaranteed by Microchip Technology.

Note 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at "minimum" values with an

external clock applied to the OSC1 pin. When an external clock input is used, the "maximum" cycle time limit

is "DC" (no clock) for all devices.

Note 3: For a detailed explanation of T0CKI input clock requirements see microcontroller datasheet Section 5.2.1.

Note 4: Clock-in high-time is the duration for which clock input is at VIHOSC or higher.

Clock-in low-time is the duration for which clock input is at VILOSC or lower.

Note 5: This HS specification is only for the -20 device. The -10 device has a maximum of 10 MHz and the -04 device

has a maximum of 4 MHz.

DS40115C-page 36

1995 Microchip Technology Inc.

MTA85XXX

Standard Operating Conditions

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

AC CHARACTERISTICS

Characteristic

Sym

Min

Typ

Max

Units

Conditions

T0CKI Input Timing,

With prescaler

T0CKI High Pulse Width

T0CKI Low Pulse Width

T0CKI period

TRTH

10*

TCY +40*

N

ns Note 3

ns Note 3. Where N = prescale

value (2,4,...,256)

TRTL

TRTP

Watchdog Timer Time-out Period,

No prescaler

Oscillation Start-up Timer Period TOST

I/O Timing

TWDT

9*

18*

30*

ms VDD = 5.0V

I/O pin input valid before

CLKOUT↑ (RC mode)

I/O Pin input hold after CLKOUT↑

(RC mode)

I/O pin output valid after CLKOUT↓

(RC Mode)

I/O pin input valid before OSC↑

(I/O setup time)

OSC1↑ to I/O pin input invalid

(I/O holdup time)

OSC1↑ to I/O pin output valid

I/O pin output rise time

I/O pin output fall time

Capacitive loading specs on

output pins

TDS

0.25 TCY+30*

0*

ns

TDH

TPD

40*

TioV2osH

TBD

TosH2ioL

TosH2ioV

TioR

ns

TBD

TioF

In Xt, HS or LP modes when

external clock is used to drive

pF OSC1

pF Excludes RB7 on MTA85X1X

devices

OSC2 pin

All I/O pins

COSC2

CIO

15

50

* Guaranteed by characterization but not tested.

Note 1: Data in the column labeled "Typ" is based on characterization results at 25°C. This data is for design guidance

only and is not tested for, or guaranteed by Microchip Technology.

Note 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at "minimum" values with an

external clock applied to the OSC1 pin. When an external clock input is used, the "maximum" cycle time limit

is "DC" (no clock) for all devices.

Note 3: For a detailed explanation of T0CKI input clock requirements see microcontroller datasheet Section 5.2.1.

Note 4: Clock-in high-time is the duration for which clock input is at VIHOSC or higher.

Clock-in low-time is the duration for which clock input is at VILOSC or lower.

Note 5: This HS specification is only for the -20 device. The -10 device has a maximum of 10 MHz and the -04 device

has a maximum of 4 MHz.

1995 Microchip Technology Inc.

DS40115C-page 37

MTA85XXX

TABLE 15-6: AC CHARACTERISTICS OF EEPROM

Standard Mode VCC = 4.5-5.5V

Fast Mode

AC CHARACTERISTICS

Parameter

Symbol

Units

Remarks

Min

Max

Min

Max

Clock frequency

Clock high time

Clock low time

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

FCLK

0

100

—

1000

300

—

0

400

—

300

—

kHz

ns

THIGH

TLOW

TR

4000

4700

—

4000

600

1300

UF

600

ns Note 2

ns After this period the first clock

pulse is generated

ns Only relevant for repeated

START condition

TF

THD:STA

START condition setup time

TSU:STA

4700

—

600

—

Data input hold time

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time

THD:DAT

TSU:DAT

TSU:STO

TAA

0

—

3500

—

0

—

900

—

ns Note 1

ns

250

4000

—

100

600

—

ns Note 1

TBUF

4700

1300

ns Time the bus must be free

before a new transmission can

start

Output fall time from VIH minimum to TOF

VIL maximum

—

250 20+0.1

CB

250

ns Note 2, CB ≤ 100 pF

Input filter spike suppression

(SDA and SCL pins)

Write cycle time

Endurance

TSP

TWR

—

N/A

—

100,000

N/A

10

—

0

—

100,000

50

10

—

ns Note 3

ms Byte or Page mode

E/W

cycles

Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

Note 2: Not 100% tested. CB = total capacitance of one bus line in pF.

Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise

spike suppression. This eliminates the need for a TI specification for standard operation.

15.4

Electrical Structure of Pins

FIGURE 15-2: ELECTRICAL STRUCTURE OF

MCLR AND T0CKI PINS

FIGURE 15-1: ELECTRICAL STRUCTURE OF

I/O PINS (RA, RB)

VDD

RIN

P

MCLR,

T0CKI

Schmitt Trigger

Input Buffer

N

I/O pin

N

VSS

RIN

VSS

Input

Buffer

Notes to Figure 15-1 and Figure 15-2: The diodes and the grounded gate (or output driver) NMOS device are carefully

designed to protect against ESD (Electrostatic discharge) and EOS (Electrical overstress). RIN is a small resistance to

further protect the input buffer from ESD.

DS40115C-page 38

1995 Microchip Technology Inc.

MTA85XXX

15.5

Timing Diagrams

FIGURE 15-3: LOAD CONDITIONS

CL

VSS

CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or

LP modes when external clock

is used to drive OSC1.

1995 Microchip Technology Inc.

DS40115C-page 39

MTA85XXX

FIGURE 15-4: EXTERNAL CLOCK TIMING

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

CLKOUT

TABLE 15-7: EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min Typ†

Max

Units Conditions

Fosc

External CLKIN Frequency

(Note 1)

DC

0.1

4

—

4

MHz XT and RC osc mode

MHz HS osc mode (PIC16C5XA-04)

MHz HS osc mode (PIC16C5XA-10)

MHz HS osc mode (PIC16C5XA-20)

kHz LP osc mode

10

20

200

4

Oscillator Frequency

(Note 1)

MHz RC osc mode

4

MHz XT osc mode

4

MHz HS osc mode (PIC16C5XA-04)

MHz HS osc mode (PIC16C5XA-10)

MHz HS osc mode (PIC16C5XA-20)

kHz LP osc mode

4

10

20

200

—

4

5

1

TOSC

External CLKIN Period

(Note 1)

250

100

50

ns

µs

ns

µs

ns

µs

ns

XT and RC osc mode

HS osc mode (PIC16C5XA-04)

HS osc mode (PIC16C5XA-10)

HS osc mode (PIC16C5XA-20)

LP osc mode

5.0

250

100

50

Oscillator Period

(Note 1)

RC osc mode

10,000

250

200

DC

—

XT osc mode

HS osc mode (PIC16C5XA-04)

HS osc mode (PIC16C5XA-10)

HS osc mode (PIC16C5XA-20)

LP osc mode

5

2

3

TCY

Instruction Cycle Time (Note 1)

1.0

50

TosL, TosH Clock in (OSC1) Low or High Time

XT oscillator

LP oscillator

HS oscillator

XT oscillator

LP oscillator

HS oscillator

2.5

10

—

4

TosR, TosF Clock in (OSC1) Rise or Fall Time

25

—

50

—

15

—

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min." values with an external

clock applied to the OSC1/CLKIN pin.

When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

DS40115C-page 40

1995 Microchip Technology Inc.

MTA85XXX

FIGURE 15-5: CLKOUT AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

CLKOUT

13

12

16

19

18

14

I/O Pin

(input)

15

17

I/O Pin

new value

old value

(output)

20, 21

Note: All tests must be done with specified capacitive loads (see datasheet) 50 pF on I/O pins and CLKOUT.

TABLE 15-8: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max

Units Conditions

10

11

TosH2ckL

OSC1↑ to CLKOUT↓

—

15

5

30

ns

Note 1

Note 2

TosH2ckH OSC1↑ to CLKOUT↑

—

30

12

13

14

15

16

17

18

TckR

CLKOUT rise time

—

15

TckF

CLKOUT fall time

—

5

TckL2ioV

TioV2ckH

TckH2ioI

TosH2ioV

TosH2ioI

CLKOUT↓ to Port out valid

Port in valid before CLKOUT↑

Port in hold after CLKOUT↑

OSC1↑ (Q1 cycle) to Port out valid

—

0.5 TCY+20

—

0.25 TCY+25

0

—

80 - 100

OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time)

TBD

—

ns

19

TioV2osH

Port input valid to OSC1↑

(I/O in setup time)

TBD

—

10

—

25

ns

20

21

TioR

TioF

Port output rise time

Port output fall time

Note 2

—

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

2: See Figure 15-3 for loading conditions.

1995 Microchip Technology Inc.

DS40115C-page 41

MTA85XXX

FIGURE 15-6: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING

VDD

MCLR

30

Internal

POR

32

DRT

Timeout

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

TABLE 15-9: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER

Parameter

No.

Sym

Characteristic

Min

Typ†

Max Units

Conditions

30

TmcL

MCLR Pulse Width (low)

100

—

ns VDD = 5V, -40°C to

+125°C

31

Twdt

Watchdog Timer Timeout Period

9*

18

30*

ms VDD = 5V, -40°C to

+125°C

(No Prescaler)

32

34

TDRT

TioZ

Device Reset Timer Period

18*

30*

100

ms VDD = 5V, -40°C to

+125°C

I/O Hi-impedance from MCLR Low

or WDT timeout

ns

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS40115C-page 42

1995 Microchip Technology Inc.

MTA85XXX

FIGURE 15-7: TIMER0 CLOCK TIMINGS

T0CKI

40

41

42

TABLE 15-10: TIMER0 CLOCK REQUIREMENTS

Parameter Sym Characteristic

No.

Min

Typ† Max Units Conditions

40

41

42

Tt0H T0CKI High Pulse Width

Tt0L T0CKI Low Pulse Width

Tt0P T0CKI Period

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20*

10*

—

ns

0.5 TCY + 20*

10*

TCY + 40*

N

ns N = prescale value

(1, 2, 4, ..., 256)

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

1995 Microchip Technology Inc.

DS40115C-page 43

MTA85XXX

The data presented in this section is a statistical

summary of data collected on units from different lots

over a period of time. "Typical" represents the mean of

the distribution while "max" or "min" represents (mean

+ 3σ) and (mean - 3σ) respectively where σ is standard

deviation.

16.0 DC / AC CHARACTERISTICS

The graphs and tables provided in this section are for

design guidance and are not tested or guaranteed. In

some graphs or tables the data presented are outside

specified operating range (e.g., outside specified VDD

range). This is for information only and devices are

guaranteed to operate properly only within the

specified range.

FIGURE 16-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE

FOSC

Frequency normalized to +25°C

FOSC (25°C)

1.10

Rext ≥ 10 kΩ

Cext = 100 pF

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

VDD = 5.5V

VDD = 3.5V

0.92

0.90

0.88

0

10

20

25

30

40

50

60

70

T(°C)

TABLE 16-1: RC OSCILLATOR FREQUENCIES

Average

Fosc @ 5V, 25°C

Cext

Rext

20 pF

3.3k

5k

4.973 MHz

3.82 MHz

2.22 MHz

262.15 kHz

1.63 MHz

1.19 MHz

684.64 kHz

71.56 kHz

660.0 kHz

484.1 kHz

267.63 kHz

29.44 kHz

± 27%

± 21%

± 31%

± 13%

± 18%

± 25%

± 10%

± 14%

± 15%

± 19%

10k

100k

3.3k

5k

100 pF

300 pF

10k

100k

3.3k

5.k

10k

160k

Note 1: The frequencies are measured on DIP packages.

Note 2: The percentage variation indicated here is part to part variation due to normal process distribution.

The variation indicated is ±3 standard deviation from average value for VDD = 5V.

DS40115C-page 44

1995 Microchip Technology Inc.

MTA85XXX

FIGURE 16-2: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD

FIGURE 16-3: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD

1.8

5.5

R = 3.3k

5.0

1.6

1.4

R = 3.3k

4.5

4.0

R = 5k

1.2

R = 5k

1.0

3.5

3.0

0.8

R = 10k

2.5

0.6

R = 10k

Cext = 100 pF, T = 25°C

2.0

1.5

0.4

0.2

R = 100k

Cext = 20 pF, T = 25°C

0.0

3.0

1.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

Measured on DIP Packages

0.5

FIGURE 16-4: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD

R = 100k

5.5

0.0

3.0

3.5

4.0

4.5

5.0

6.0

800

VDD (Volts)

Measured on DIP Packages

700

600

500

400

300

200

100

0

R = 3.3k

R = 5k

R = 10k

Cext = 300 pF, T = 25°C

R = 100k

5.5

3.0

3.5

4.0

4.5

5.0

6.0

VDD (Volts)

Measured on DIP Packages

1995 Microchip Technology Inc.

DS40115C-page 45

MTA85XXX

FIGURE 16-5: TYPICAL IPD vs. VDD

FIGURE 16-7: TYPICAL IPD vs. VDD

WATCHDOG ENABLED 25°C

WATCHDOG DISABLED 25°C

2.5

2.0

1.5

20

18

16

14

12

10

8

1.0

0.5

0.0

6

4

2

0

2.5 3.0

3.5 4.0

4.5 5.0 5.5 6.0

2.5 3.0

3.5 4.0

4.5 5.0 5.5 6.0

VDD (Volts)

FIGURE 16-6: MAXIMUM IPD vs. VDD

WATCHDOG DISABLED

FIGURE 16-8: MAXIMUM IPD vs. VDD

WATCHDOG ENABLED

100

60

Temp. (°C)

Temp. = 125°C

50

-55

85

10

40

0

30

-40

70

125

-40

-55

1

20

10

0

85

0

2.5 3.0

3.5 4.0

4.5 5.0 5.5 6.0

6.5

7.0

2.5 3.0

3.5 4.0

4.5 5.0 5.5 6.0

6.5

7.0

VDD (Volts)

IPD, with WDT enabled, has two components:

The leakage current which increases with higher temperature

and the operating current of the WDT logic which increases

with lower temperature. At -40°C, the latter dominates

explaining the apparently anomalous behavior.

DS40115C-page 46

1995 Microchip Technology Inc.

MTA85XXX

FIGURE 16-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD

2.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

FIGURE 16-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

2.5

3.0

3.5

4.0

4.5

VDD (Volts)

5.0

5.5

6.0

Note: These input pins have Schmitt Trigger input buffers.

FIGURE 16-11: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

2.5

3.0

3.5

4.0

VDD (Volts)

4.5

5.0

5.5

6.0

1995 Microchip Technology Inc.

DS40115C-page 47

MTA85XXX

FIGURE 16-12: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C)

10

1.0

7.0

6.5

0.1

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

0.01

10k

100k

1M

10M

100M

External Clock Frequency (Hz)

FIGURE 16-13: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK -40°C TO +85°C)

10

1.0

7.0

6.5

6.0

0.1

5.5

5.0

4.5

4.0

3.5

3.0

2.5

0.01

10k

100k

1M

10M

100M

External Clock Frequency (Hz)

DS40115C-page 48

1995 Microchip Technology Inc.

MTA85XXX

FIGURE 16-14: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK -55°C TO +125°C)

10

1.0

7.0

6.5

6.0

5.5

0.1 5.0

4.0

4.5

3.5

3.0

2.5

0.01

10k

100k

1M

10M

100M

External Clock Frequency (Hz)

FIGURE 16-15: WDT TIMER TIME-OUT

PERIOD vs. VDD

FIGURE 16-16: TRANSCONDUCTANCE (gm)

OF HS OSCILLATOR vs. VDD

50

9000

45

8000

Max 40°C

40

7000

Max 85°C

35

6000

5000

Max 70°C

30

25

4000

Typ 25°C

20

3000

2000

MIn 0°C

15

Min 85°C

10

100

MIn -40°C

5

0

2

3

4

5

6

7

2

3

4

5

6

7

VDD (Volts)

1995 Microchip Technology Inc.

DS40115C-page 49

MTA85XXX

FIGURE 16-17: TRANSCONDUCTANCE (gm)

OF LP OSCILLATOR vs. VDD

FIGURE 16-19: TRANSCONDUCTANCE (gm)

OF XT OSCILLATOR vs. VDD

45

2500

40

Max -40°C

2000

35

Max -40°C

30

1500

Typ 25°C

25

Typ 25°C

20

1000

15

10

Min 85°C

500

Min 85°C

5

0

2

3

4

5

6

7

0

VDD (Volts)

2

3

4

5

6

7

VDD (Volts)

FIGURE 16-20: IOH vs. VOH, VDD = 5V

FIGURE 16-18: IOH vs. VOH, VDD = 3V

0

Min 85°C

-5

Min +85°C

-10

-20

Typ 25°C

-15

-30

-20

Max -40°C

-40

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

-25

0

0.5 1.0

1.5 2.0

2.5 3.0

VOH (Volts)

DS40115C-page 50

1995 Microchip Technology Inc.

MTA85XXX

FIGURE 16-21: IOL vs. VOL, VDD = 3V

FIGURE 16-22: IOL vs. VOL, VDD = 5V

45

90

80

70

40

Max -40°C

35

30

25

60

50

Typ 25°C

20

40

Min 85°C

15

10

30

20

Min +85°C

5

0

10

0

0.5 1.0 1.5 2.0 2.5 3.0

VOL (Volts)

0

0.5 1.0 1.5 2.0 2.5 3.0

VOL (Volts)

1995 Microchip Technology Inc.

DS40115C-page 51

MTA85XXX

17.1.4 DATA VALID (D)

17.0 EEPROM BUS DESCRIPTION

The MTA85XXX supports a bidirectional two wire bus

and data transmission protocol. A device that sends

data onto the bus is defined as transmitter, and a

device receiving data as receiver. The bus has to be

controlled by a master device (microcontroller) which

generates the serial clock (SCL), controls the bus

access, and generates the START and STOP

conditions, while the EEPROM (24LC01B/02B) works

as slave. Both master and slave can operate as

transmitter or receiver but the master device

determines which mode is activated.

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last

sixteen will be stored when doing a write operation.

When an overwrite does occur it will replace data in a

first in first out fashion.

17.1

Bus Characteristics

The following bus protocol has been defined:

- Data transfer may be initiated only when the

bus is not busy.

17.1.5 ACKNOWLEDGE

- During data transfer, the data line must

remain stable whenever the clock line is

HIGH. Changes in the data line while the

clock line is HIGH will be interpreted as a

START or STOP condition.

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

* Note: The EEPROM does not generate any

acknowledge bits if an internal pro-

gramming cycle is in progress.

Accordingly, the following bus conditions have been

defined (Figure 17-1):

17.1.1 BUS NOT BUSY (A)

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

Both data and clock lines remain HIGH.

17.1.2 START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

17.1.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

FIGURE 17-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START

Condition

Address

or

Acknowledge

Valid

Data Allowed

to Change

STOP

Condition

DS40115C-page 52

1995 Microchip Technology Inc.

MTA85XXX

17.1.6 SLAVE ADDRESS

FIGURE 17-2: EEPROM CONTROL CODES

The 24LC01B/02B (EEPROM) are software-

compatible with older devices such as the 24C01A,

24C02A, 24LC01, and the 24LC02. A single 24LC02B

can be used in place of two 24LC01’s, for example,

without any modifications to software. The "chip select"

portion of the control byte is a don't care.

Control

Code

Chip

Select

Operation

R/W

1010

Read

Write

xxx

1

0

FIGURE 17-3: CONTROL BYTE

ALLOCATION

After generating a START condition, the bus master

transmits the slave address consisting of a 4-bit device

code (1010) for the EEPROM, followed by three don't

care bits.

READ/WRITE

START

SLAVE ADDRESS

A

R/W

X

The eighth bit of slave address determines if the master

device wants to read or write to the EEPROM

(Figure 17-3).

The EEPROM monitors the bus for its corresponding

slave address all the time. It generates an

acknowledge bit if the slave address was true and it is

not in a programming mode.

1

0

1

0

X

X = don’t care

1995 Microchip Technology Inc.

DS40115C-page 53

MTA85XXX

18.2

Page Write

18.0 WRITE OPERATION

The write control byte, word address and the first data

byte are transmitted to the EEPROM in the same way

as in a byte write. But instead of generating a STOP

condition the master transmits up to eight data bytes to

the EEPROM which are temporarily stored in the on-

chip page buffer and will be written into the memory

after the master has transmitted a STOP condition.

After the receipt of each word, the three lower order

address pointer bits are internally incremented by one.

The higher order five bits of the word address remains

constant. If the master should transmit more than eight

words prior to generating the STOP condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the STOP condition is received an

internal write cycle will begin (Figure 18-2).

18.1

Byte Write

Following the START signal from the master, the

device code (4-bits), the don't care bits (3-bits), and the

R/W bit which is a logic low is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow after it has generated an acknowledge bit during

the ninth clock cycle. Therefore the next byte

transmitted by the master is the word address and will

be written into the address pointer of the EEPROM.

After receiving another acknowledge signal from the

EEPROM the master device will transmit the data word

to be written into the addressed memory location. The

EEPROM acknowledges again and the

master

generates a stop condition. This initiates the internal

write cycle, and during this time the EEPROM will not

generate acknowledge signals (Figure 18-1).

FIGURE 18-1: BYTE WRITE

S

T

S

WORD

ADDRESS

CONTROL

BYTE

A

R

T

BUS ACTIVITY:

MASTER

DATA

O

P

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

BUS ACTIVITY:

FIGURE 18-2: PAGE WRITE

S

T

A

R

T

S

T

O

P

WORD

ADDRESS (n)

CONTROL

BYTE

BUS

ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+7

SDA LINE

P

S

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

BUS

ACTIVITY:

DS40115C-page 54

1995 Microchip Technology Inc.

MTA85XXX

18.3

Acknowledge Polling

FIGURE 18-3: ACKNOWLEDGE POLLING

FLOW

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the STOP condition for a write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a START condition followed by the control byte

for a write command (R/W = 0). If the device is still busy

with the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 18-3 for flow diagram.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

No

Did Device

Acknowledge

(ACK = 0)?

Yes

1995 Microchip Technology Inc.

DS40115C-page 55

MTA85XXX

19.2

Random Read

19.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to. There are three basic types of

read operations:

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

EEPROM as part of a write operation. After the word

address is sent, the master generates a START

condition following the acknowledge. This terminates

the write operation, but not before the internal address

pointer is set. Then the master issues the control byte

again but with the R/W bit set to a '1'. The EEPROM will

then issue an acknowledge and transmits the eight-bit

data word. The master will not acknowledge the

transfer but does generate a STOP condition and the

EEPROM discontinues transmission (Figure 19-2).

• Current address read

• Random read

• Sequential read.

19.1

Current Address Read

The EEPROM contains an address counter that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous access (either a read or write operation) was

to address "n", the next current address read operation

would access data from address "n + 1". Upon receipt

of the slave address with R/W bit set, the EEPROM

issues an acknowledge and transmits the eight-bit data

word. The master will not acknowledge the transfer but

does generate a STOP condition and the EEPROM

discontinues transmission (Figure 19-1). If a current

address read is performed after a Power-Up, the last

address will be read.

19.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the EEPROM transmits

the first data byte, the master issues an acknowledge

as opposed to a STOP condition in a random read. This

directs the EEPROM to transmit the next sequentially

addressed 8-bit word (Figure 19-3).

FIGURE 19-1: CURRENT ADDRESS READ

S

T

A

R

T

S

T

CONTROL

BYTE

O

BUS ACTIVITY

MASTER

DATA n

P

SDA LINE

S

P

N

O

A

C

K

BUS ACTIVITY

A

C

K

FIGURE 19-2: RANDOM READ

S

T

A

R

T

S

T

A

R

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS (n)

BUS ACTIVITY:

MASTER

CONTROL

BYTE

SDA LINE

S

P

N

O

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

DATA n

A

C

K

DS40115C-page 56

1995 Microchip Technology Inc.

MTA85XXX

FIGURE 19-3: SEQUENTIAL READ

S

T

O

P

BUS ACTIVITY

A

C

K

A

C

K

MASTER

C

K

CONTROL

BYTE

P

SDA LINE

A

C

K

N

O

BUS ACTIVITY

DATA n

DATA n+1

DATA n+2

DATA n+X

A

C

K

To provide sequential reads the EEPROM contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows the entire memory contents to be serially read

during one operation.

1995 Microchip Technology Inc.

DS40115C-page 57

MTA85XXX

20.2

SDA Serial Address/Data Input/

Output

20.0 GENERAL EEPROM

INFORMATION

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup

resistor to VCC (typical 10 kΩ for 100 kHz and 1 kΩ for

400 kHz).

20.1

Noise Protection

The EEPROM employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.5V at nominal conditions.

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP

conditions.

The SCL and SDA inputs have Schmitt trigger and filter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

20.3

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

DS40115C-page 58

1995 Microchip Technology Inc.

MTA85XXX

The PICMASTER has been designed as a real-time

emulation system with advanced features that are

generally found on more expensive development tools.

The AT platform and Windows 3.x environment was

chosen to best make these features available to you,

the end user.

21.0 DEVELOPMENT SUPPORT

21.1

Development Tools

The PIC16/17 microcontrollers are supported with a full

range of hardware and software development tools:

• PICMASTER Real-Time In-Circuit Emulator

• PRO MATE Universal Programmer

• PICSTART Low-Cost Prototype Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• MPASM Assembler

The PICMASTER Universal Emulator System consists

primarily of four major components:

• Host-Interface Card

• Emulator Control Pod

• Target-Specific Emulator Probe

• PC-Host Emulation Control Software

• MPSIM Software Simulator

The Windows 3.x operating system allows the

developer to take full advantage of the many powerful

features and functions of the PICMASTER system.

• C Compiler (MP-C)

• Fuzzy logic development system

(fuzzyTECH − MP)

PICMASTER emulation can operate in one window,

while a text editor is running in a second window.

21.2

PICMASTER: High Performance

Universal In-Circuit Emulator

PC-Host Emulation Control software takes full

advantage of Dynamic Data Exchange (DDE), a fea-

ture of Windows 3.x. DDE allows data to be dynami-

cally transferred between two or more Windows

programs. With this feature, data collected with

PICMASTER can be automatically transferred to a

spreadsheet or database program for further analysis.

The PICMASTER Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for all

microcontrollers in the PIC16C5X, PIC16CXX and

PIC17CXX families.

A

PICMASTER System

configuration is shown in Figure 21-1.

Under Windows 3.x, two or more PICMASTER

emulators can be run simultaneously from the same

PC making development of multi-microcontroller

Interchangeable target probes allow the system to be

easily reconfigured for emulation of different

processors. The universal architecture of the

PICMASTER allows expansion to support all new

PIC16C5X, PIC16CXX and PIC17CXX microcontrol-

lers.

systems possible (e.g.,

a system containing a

PIC16CXX processor and a PIC17CXX processor).

The PICMASTER probes specifications are shown in

Table 21-1.

The Emulator System is designed to operate on PC

compatible 386 (and better) machines in the Microsoft

Windows

3.x environment. Thus, allowing the

operator access to a wide range of supporting software

and accessories.

1995 Microchip Technology Inc.

DS40115C-page 59

MTA85XXX

FIGURE 21-1: PICMASTER SYSTEM CONFIGURATION

In-Line

5 VDC

Power Supply

90 - 250 VAC

(Optional)

Windows 3.x

Power Switch

Interchangeable

Emulator Probe

Power Connector

PC Bus

PC-Interface

PICMASTER Emulator Pod

Common Interface Card

PC Compatible Computer

Logic Probes

TABLE 21-1: PICMASTER PROBE SPECIFICATION

PROBE

PICMASTER Probe

Devices Supported

Maximum

Frequency

Operating

Voltage

PROBE-16B

PROBE-16C

PROBE-16D

PIC16C71

PIC16C84

10 MHz

20 MHz

4.5V - 5.5V

PIC16C54, PIC16C54A, PIC16CR54, PIC16C55,

PIC16C56, PIC16C57, PIC16C58A, and PIC16CR58A

PROBE-16E

PROBE-16F

PROBE-16G

PROBE-16H

PROBE-17A

PIC16C64

10 MHz

16 MHz

4.5V - 5.5V

PIC16C65*, PIC16C73 and PIC16C74

PIC16C61

PIC16C620, PIC16C621 and PIC16C622

PIC17C42

* PROBE-16F indirectly supports the PIC16C65.

of the features of the software. Essential commands

such as read, verify, program and blank check can be

issued from the screen. Additionally, serial program-

ming support is possible where each part is pro-

grammed with a different serial number, sequential or

random.

21.3

PRO MATE: Universal Programmer

The PRO MATE Universal Programmer is a full-

featured programmer capable of operating in stand-

alone mode as well as PC-hosted mode.

The PRO MATE has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE can read, verify or program

PIC16C5X, PIC16CXX and PIC17CXX devices. It can

also set fuse configuration and code-protect bits in this

mode.

The PRO MATE has a modular “programming socket

module”. Different socket modules are required for

different processor types and/or package types.

PRO MATE supports all PIC16C5X, PIC16CXX and

PIC17CXX processors.

21.4

PICSTART Low-Cost Development

System

The PICSTART programmer is an easy to use, very

low-cost prototype programmer. It connects to the PC

via one of the COM (RS-232) ports. A PC-based user

interface software makes using the programmer simple

and efficient. The user interface is full-screen and

menu-based. PICSTART is not recommended for

production programming.

In PC-hosted mode, the PRO MATE connects to the

PC via one of the COM (RS-232) ports. PC based user-

interface software makes using the programmer simple

and efficient. The user interface is full-screen and

menu-based. Full screen display and editing of data,

easy selection of fuse configuration and part type, easy

selection of VDD min, VDD max and VPP levels, load

and store to and from disk files (hex format) are some

DS40115C-page 60

1995 Microchip Technology Inc.

MTA85XXX

21.5

PICDEM-1 Low-Cost PIC16/17

Demonstration Board

21.7

Assembler (MPASM)

The MPASM Cross Assembler is a PC-hosted symbolic

assembler. It supports all microcontroller series

including the PIC16C5X, PIC16CXX, and PIC17CXX

families.

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s

microcontrollers. The microcontrollers supported are:

PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61,

PIC16C62X, PIC16C71, PIC16C84 and PIC17C42. All

necessary hardware and software is included to run

basic demo programs. The users can program sample

microcontrollers provided with the PICDEM-1 board,

on a PRO MATE or PICSTART-16B programmer,

and easily test firmware. The user can also connect

the PICDEM-1 board to the PICMASTER emulator

and download the firmware to the emulator for testing.

Additional prototype area is available for the user to

build some additional hardware and connect it to the

microcontroller socket(s). Some of the features include

an RS-232 interface, a potentiometer for simulated

analog input, push-button switches and eight LEDs

connected to PORTB.

MPASM offers full featured Macro capabilities,

conditional assembly, and several source and listing

formats. It generates various object code formats to

support Microchip's development tools as well as third

party programmers.

MPASM allows full symbolic debugging from

the

(PICMASTER).

Microchip Universal Emulator System

MPASM has the following features to assist in

developing software for specific use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability

• Produces all the files (Object, Listing, Symbol,

and special) required for symbolic debug with

Microchip’s emulator systems.

21.6

PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

• Supports Hex (default), Decimal and Octal source

and listing formats.

The PICDEM-2 is a simple demonstration board that

supports the PIC16C63, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

MPASM provides a full feature directive language

represented by four basic classes of directives:

• Data Directives are those that control the

allocation of memory and provide a way to refer to

data items symbolically (i.e., by meaningful

names).

with the PICDEM-2 board, on

a PRO MATE

programmer or PICSTART-16C, and easily test firm-

ware. The PICMASTER emulator may also be used

with the PICDEM-2 board to test firmware. Additional

prototype area has been provided to the user for

adding additional hardware and connecting it to the

microcontroller socket(s). Some of the features include

• Listing Directives control the MPASM listing

display. They allow the specification of titles and

sub-titles, page ejects and other listing control.

• Control Directives permit sections of

conditionally assembled code.

a

RS-232 interface, push-button switches,

a

• Macro Directives control the execution and data

allocation within macro body definitions.

potentiometer for simulated analog input, a Serial

2

EEPROM to demonstrate usage of the I C bus and

separate headers for connection to an LCD module

and a keypad.

1995 Microchip Technology Inc.

DS40115C-page 61

MTA85XXX

21.8

Software Simulator (MPSIM)

21.10 Fuzzy Logic Development System

(fuzzyTECH-MP)

The MPSIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PIC16/17 series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The input/

output radix can be set by the user and the execution

can be performed in; single step, execute until break, or

in a trace mode. MPSIM fully supports symbolic debug-

ging using MP-C and MPASM. The Software Simulator

offers the low cost flexibility to develop and debug code

outside of the laboratory environment making it an

excellent multi-project software development tool.

fuzzyTECH-MP fuzzy logic development tool is

available in two versions - a low cost introductory

version, MP Explorer, for designers to gain

comprehensive working knowledge of fuzzy logic

system design; and full-featured version,

a

fuzzyTECH-MP Edition, for implementing more

complex systems.

Both versions include Microchip’s fuzzyLAB

demonstration board for hands-on experience with

fuzzy logic systems implementation.

21.11 Development Systems

21.9

C Compiler (MP-C)

For convenience, the development tools are packaged

into comprehensive systems as listed in Table 21-2.

The MP-C Code Development System is a complete 'C'

compiler and integrated development environment for

Microchip’s PIC16/17 family of microcontrollers. The

compiler provides powerful integration capabilities and

ease of use not found with other compilers.

For easier source level debugging, the compiler

provides symbol information that is compatible with the

PICMASTER Universal Emulator memory display

(emulator software versions 1.13 and later).

The MP-C Code Development System is supplied

directly by Byte Craft Limited of Waterloo, Ontario,

Canada. If you have any questions, please contact

your regional Microchip FAE or Microchip technical

support personnel at (602) 786-7627.

TABLE 21-2: DEVELOPMENT SYSTEM PACKAGES

Item

Name

System Description

1.

PICMASTER System

PICMASTER In-Circuit Emulator, PRO MATE Programmer, Assembler,

Software Simulator, Samples and your choice of Target Probe.

2.

3.

4.

5.

6.

PICSTART System

PRO MATE System

PICSTART Low-Cost Prototype Programmer, Assembler, Software Simulator

and Samples.

PRO MATE Universal Programmer, full featured stand-alone or PC-hosted pro-

grammer, Assembler, Simulator

PICSEE-85A

Introduction Design Kit

Kit contains the programming adaptor (item 3), a PICMASTER interface board

and microcontroller samples of the MTA85XXX component devices

PICSEESTART-85A

Development Kit

Kit contains a PICSTART System (item 2) and PICSEE-85A Introduction

Design Lit (item 4)

PICSEE-85A

PRO MATE Header

SSOP PRO MATE header for the MTA85XXX products. No programming

adaptor needed

DS40115C-page 62

1995 Microchip Technology Inc.

MTA85XXX

22.0 PACKAGING DIAGRAMS AND DIMENSIONS

22.1

20-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30mm)

N

Index

area

E

H

α

C

L

1 2 3

e

B

A

Base plane

CP

Seating plane

D

A1

Package Group: Plastic SSOP

Millimeters

Max

Inches

Symbol

Min

Notes

Min

Max

Notes

α

A

0°

8°

0°

8°

1.730

0.050

0.250

0.130

7.070

5.200

0.650

7.650

0.550

20

1.990

0.210

0.380

0.220

7.330

5.380

0.650

7.900

0.950

20

0.068

0.002

0.010

0.005

0.278

0.205

0.026

0.301

0.022

20

0.078

0.008

0.015

0.009

0.289

0.212

0.026

0.311

0.037

20

A1

B

C

D

E

e

Reference

H

L

N

CP

-

0.102

-

0.004

1995 Microchip Technology Inc.

DS40115C-page 63

MTA85XXX

23.0 PACKAGE MARKING INFORMATION

20-Lead SSOP

Example

XXXXXXXXXX

AABBCDE

MTA85401

10/SS

9512CAP

Legend:

MM...M

XX...X

AA

Microchip part number information

Customer specific information*

Year code (last 2 digits of calender year)

Week code (week of January 1 is week '01’)

BB

C

Facility code of the plant at which wafer is manufactured.

C = Chandler, Arizona, U.S.A.

D

E

Mask revision number for microcontroller

Mask revision number for EEPROM

Assembly code of the plant or country of origin in which

part was assembled.

1

2

In the event the full Microchip part number cannot be marked on one

line, it will be carried over to the next line thus limiting the number of

available characters for customer specific information.

Note:

*

Standard OTP marking consists of Microchip part number, year code, week code,

facility code, mask revision number, and assembly code. For OTP marking beyond

this, certain price adders apply. Please check with your Microchip Sales Office.

For QTP devices, any special marking adders are included in QTP price.

DS40115C-page 64

1995 Microchip Technology Inc.

MTA85XXX

Q

INDEX

QTP Devices ........................................................................ 7

A

R

Absolute Maximum Ratings ............................................... 33

AC Characteristics (04, 10, 20) COM/IND ................... 37–39

Assembler .......................................................................... 63

Real Time Clock/Counter (RTCC) ......................... 13, 14, 19

RESET ............................................................................... 20

S

B

Software Simulator (MPSIM) ............................................. 63

Stack .............................................................................. 9, 15

Status Register .................................................................. 15

Block Diagram

Chip .............................................................................. 5

I/O Pin ........................................................................ 17

On-Chip Reset Circuit ................................................ 27

RTCC (Simplified) ...................................................... 14

RTCC and WDT ......................................................... 21

Brown-Out Protection Circuit ............................................. 30

T

Timing Diagrams

I/O Pin ........................................................................ 17

RTCC Timing ............................................................. 14

TO bit ................................................................................. 16

TRIS Registers .................................................................. 19

C

C Compiler (MP-C) ............................................................ 63

Code Protection ................................................................. 32

Configuration Fuses ........................................................... 32

U

UV Erasable Devices ........................................................... 7

D

W

Data Memory Map ............................................................. 10

DC Characteristics (04, 10, 20) COM/IND ................... 34–36

Development Support ........................................................ 60

Development Systems ....................................................... 63

W Register ......................................................................... 19

WDT .................................................................................. 24

Table of Figures

E

Figure 2-1:

Figure 2-2:

Figure 4-1:

Figure 4-2:

Figure 5-1:

Figure 5-2:

Figure 5-3:

Figure 5-4:

Figure 5-5:

Figure 5-6:

Figure 5-7:

Figure 5-8:

Figure 6-1:

Figure 8-1:

MTA85XXX Series Block Diagram ............... 5

Clocks/Instruction Cycle............................... 6

Program Memory Organization MTA854XX. 9

Program Memory Organization MTA858XX. 9

Data Memory Map...................................... 10

T0CKI Block Diagram (Simplified).............. 13

T0CKI Timing: INT Clock/No Prescale....... 13

T0CKI Timing: INT Clock/Prescale 1:2....... 13

T0CKI Timing With External Clock............. 13

Status WORD Register .............................. 14

Equivalent Circuit For a Single I/O Pin....... 16

I/O Port Read/Write Timing ........................ 16

OPTION Register ....................................... 18

Block Diagram T0CKI/WDT Prescaler ....... 20

External Power-On Reset Circuit ....................................... 30

F

Features Overview ............................................................... 1

File Register Descriptions

FSR ............................................................................ 16

INDF ........................................................................... 13

PC .............................................................................. 15

RTCC ......................................................................... 13

STATUS ..................................................................... 15

Fuzzy Logic Dev. System (fuzzyTECH -MP) ................... 63

I

I/O Ports ............................................................................. 17

Indirect Addressing ............................................................ 13

Instruction Set .................................................................... 22

Figure 10-1: Watchdog Timer Block Diagram................. 23

Figure 11-1: Crystal /Ceramic Resonator Operation

(HS, XT or LP OSC Configuration)............. 24

Figure 11-2: External Clock Input Operation

M

(HS, XT or LP OSC Mode)......................... 24

MPASM Assembler ............................................................ 63

MP-C C Compiler ............................................................... 63

MPSIM Software Simulator ................................................ 63

Figure 11-3: External Parallel Resonant Crystal

Oscillator Circuit ......................................... 25

Figure 11-4: External Series Resonant Crystal

Oscillator Circuit ......................................... 25

Figure 11-5: RC Oscillator Mode .................................... 25

Figure 12-1: On-Chip Reset Circuit Block Diagram ........ 26

Figure 12-2: Time-Out Sequence on Power-Up

(MCLR Not Tied to VDD): Case 1 ............... 28

Figure 12-3: Time-Out Sequence on Power-Up

(MCLR Not Tied to VDD): Case 2 ............... 28

Figure 12-4: Time-Out Sequence on Power-Up

(MCLR Tied to VDD) ................................... 28

Figure 12-5: External Power-On Reset Circuit

(For Slow VDD Power-Up) .......................... 29

Figure 12-6: Brown-Out Protection Circuit 1................... 29

Figure 12-7: Brown-Out Protection Circuit 2................... 29

Figure 12-8: Electrical Structure of the MCLR/VPP and

T0CKI Pins ................................................. 29

Figure 14-1: Configuration Word .................................... 32

Figure 15-1: Electrical Structure of I/O Pins (RA, RB).... 39

O

OPTION Register ............................................................... 19

OTP Devices ........................................................................ 7

P

Package Information .................................................... 64, 65

Page Select (program memory) ........................................... 8

PD bit ................................................................................. 16

PICMASTER Probe ........................................................... 61

PICMASTER System Configuration ................................... 61

Pinout Information .......................................................... 1, 40

POR

Time-Out Sequence on Power-Up ............................. 29

Prescaler (RTCC/WDT) ............................................... 19, 21

Program Counter ................................................................. 8

Program memory map ......................................................... 9

1995 Microchip Technology Inc.

DS40115C-page 65

MTA85XXX

Figure 15-2: Electrical Structure of MCLR and

Table 12-1:

Table 12-2:

Table 12-3:

Table 15-1:

TO/PD Status After Reset .......................... 27

Reset Conditions for Special Registers...... 27

Reset Conditions for All Registers.............. 27

Cross Reference of Device Specs

for Oscillator Configurations

and Frequencies of Operation

T0CKI Pins.................................................. 39

Figure 15-3: Load Conditions.......................................... 39

Figure 15-4: External Clock Timing................................. 40

Figure 15-5: CLKOUT and I/O Timing............................. 41

Figure 15-6: Reset, Watchdog Timer, and

Device Reset Timer Timing ........................ 42

(Commercial Devices) ................................ 32

DC Characteristics of Microcontroller

MTA854XX-04 (Industrial).......................... 33

DC Characteristics of Microcontroller

MTA858XX-04 (Industrial) /

MTA858XX-10 (Industrial).......................... 34

DC Characteristics of Inputs/Outputs:

MTA854XX-04 (Industrial) /

Figure 15-7: TIMER0 Clock Timings............................... 43

Figure 16-1: Typical RC Oscillator Frequency vs.

Temperature ............................................... 44

Figure 16-2: Typical RC Oscillator Frequency vs. VDD ... 45

Figure 16-3: Typical RC Oscillator Frequency vs. VDD ... 45

Figure 16-4: Typical RC Oscillator Frequency vs. VDD ... 45

Figure 16-5: Typical IPD vs. VDD Watchdog

Disabled 25°C............................................. 46

Figure 16-6: Maximum IPD vs. VDD Watchdog

Disabled...................................................... 46

Table 15-2:

Table 15-3:

Table 15-4:

Table 15-5:

MTA858XX-04 (Industrial) /

MTA858XX-10 (Industrial).......................... 35

AC Characteristics of Microcontroller:

MTA854XX-04 (Industrial) /

Figure 16-7: Typical IPD vs. VDD Watchdog

Enabled 25°C.............................................. 46

MTA858XX-04 (Industrial) /

Figure 16-8: Maximum IPD vs. VDD Watchdog Enabled.. 46

Figure 16-9: VTH (Input Threshold Voltage)

of I/O Pins vs. VDD...................................... 47

Figure 16-10: VIH, VIL of MCLR, T0CKI and OSC1

(in RC Mode) vs. VDD ................................. 47

MTA858XX-10 (Industrial).......................... 36

AC Characteristics of EEPROM ................. 38

External Clock Timing Requirements ......... 40

CLKOUT and I/O Timing Requirements..... 41

Reset, Watchdog Timer,

Table 15-6:

Table 15-7:

Table 15-8:

Table 15-9:

Figure 16-11: VTH (Input Threshold Voltage)

and Device Reset Timer............................. 42

of I/O Pins vs. VDD...................................... 47

Table 15-10: TIMER0 Clock Requirements..................... 43

Figure 16-12: Typical IDD vs. Frequency

(External Clock 25°C) ................................. 48

Figure 16-13: Maximum IDD vs. Frequency

Table 16-1:

Table 21-1:

Table 21-2:

RC Oscillator Frequencies.......................... 44

PICMASTER Probe Specification............... 60

Development System Packages................. 62

(External Clock -40°C to +85°C)................. 48

Figure 16-14: Maximum IDD vs. Frequency

(External Clock -55°C to +125°C)............... 49

Figure 16-15: WDT Timer Time-out Period vs. VDD.......... 49

Figure 16-16: Transconductance (gm)

of HS Oscillator vs. VDD.............................. 49

Figure 16-17: Transconductance (gm)

of LP Oscillator vs. VDD .............................. 50

Figure 16-18: IOH vs. VOH, VDD = 3V ................................ 50

Figure 16-19: Transconductance (gm)

of XT Oscillator vs. VDD .............................. 50

Figure 16-20: IOH vs. VOH, VDD = 5V ................................ 50

Figure 16-21: IOL vs. VOL, VDD = 3V ................................. 51

Figure 16-22: IOL vs. VOL, VDD = 5V ................................. 51

Figure 17-1: Data Transfer Sequence on the Serial Bus 52

Figure 17-2: EEPROM Control Codes ............................ 53

Figure 17-3: Control Byte Allocation ............................... 53

Figure 18-1: Byte Write ................................................... 54

Figure 18-2: Page Write .................................................. 54

Figure 18-3: Acknowledge Polling Flow .......................... 55

Figure 19-1: Current Address Read ................................ 56

Figure 19-2: Random Read............................................. 56

Figure 19-3: Sequential Read ......................................... 57

Figure 21-1: PICMASTER System Configuration ........... 60

Table of Tables

Table 1-1:

Table 5-1:

Table 5-2:

Table 5-3:

Table 7-1:

Table 9-1:

Table 10-1:

Family Overview ...........................................4

PIC16C5X Register File Summary ........... 11

Events Affecting TO/PD Status bits............ 15

TO/PD Status After Reset........................... 15

Reset Condition For Registers.................... 19

Instruction Set Summary ............................ 22

Summary of Registers Associated

with the Watchdog Timer............................ 23

Capacitor Selection for

Ceramic Resonators................................... 24

Capacitor Selection For Crystal Oscillator ..24

Table 11-1:

Table 11-2:

DS40115C-page 66

1995 Microchip Technology Inc.

MTA85XXX

CONNECTING TO MICROCHIP BBS

Connect worldwide to the Microchip BBS using the

CompuServe communications network. In most

cases a local call is your only expense. The Microchip

Trademarks:

2

I C is a trademark of Philips Corporation.

BBS connection

membership services, therefore you do not need

CompuServe membership to join Microchip's BBS.

does not use CompuServe

PICSEE, PRO MATE and fuzzyLAB trademarks of

Microchip Technology Incorporated.

The Microchip logo and name are registered

trademarks of Microchip Technology Incorporated.

There is no charge for connecting to the BBS, except

for a toll charge to the CompuServe access number,

where applicable. You do not need to be

CompuServe member to take advantage of this

connection (you never actually log in to CompuServe).

a

IBM, IBM PC-AT are registered trademarks of

International Business Machines Corp.

PICMASTER and PICSTART are trademarks of

Microchip Technology Incorporated. PIC is a

registered trademark of Microchip Technology

Incorporated in the U.S.A.

The procedure to connect will vary slightly from country

to country. Please check with your local CompuServe

agent for details if you have a problem. CompuServe

service allows multiple users at baud rates up to

14400 bps.

Tri-State is a trademark of National

Semiconductor.

The following connect procedure applies in most

locations:

fuzzyTECH is a registered trademark of Inform

Software Corporation.

1. Set your modem to 8 bit, No parity, and One stop

(8N1). This is not the normal CompuServe

setting which is 7E1.

Pentium is a trademark of Intel Corporation.

Intel is a registered trademark of Intel Corporation.

2. Dial your local CompuServe access number.

MS-DOS and Microsoft Windows are registered

trademarks of Microsoft Corporation. Windows is a

trademark of Microsoft Corporation.

3. Depress <ENTER > and a garbage string will

appear because CompuServe is expecting a

7E1 setting.

CompuServe is a registered trademark of

CompuServe Incorporated.

4. Type +, depress <ENTER > and Host Name:

will appear.

All other trademarks mentioned herein are the

property of their respective companies.

5. Type MCHIPBBS, depress < ENTER > and

you will be connected to the Microchip BBS.

In the United States, to find CompuServe's phone

number closest to you, set your modem to 7E1 and dial

(800) 848-4480 for 300-2400 baud or (800) 331-7166

for 9600-14400 baud connection. After the system

responds with Host Name:, type

NETWORK, depress < ENTER

>

and follow CompuServe's directions.

For voice information (or calling from overseas), you

may call (614) 457-1550 for your local CompuServe

number.

1995 Microchip Technology Inc.

DS40115C-page 67

MTA85XXX

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at area code

(602) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

To:

Technical Publications Manager

Reader Response

Total Pages Sent

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

Literature Number:

DS40115C

Device:

MTA85XXX

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

DS40115C-page 68

1995 Microchip Technology Inc.

MTA85XXX

NOTES:

1995 Microchip Technology Inc.

DS40115C-page 69

MTA85XXX

NOTES:

DS40115C-page 70

1995 Microchip Technology Inc.

MTA85XXX

NOTES:

1995 Microchip Technology Inc.

DS40115C-page 71

MTA85XXX

Z

MTA85XXX Product Identification System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed

sales offices.

PART NO. -XX X /XX XXX

Pattern:

3-Digit Pattern Code for QTP (blank otherwise)

Package:

SS

I

=

209 mill SSOP

Temperature

Range:

-40°C to +85°C (S for tape/reel)

Frequency

Range:

04

10

=

4 MHz (MTA854XX and 858XX)

10 MHz (MTA858XX only)

Device:

MTA85401 :Refer to Table 1-1

Examples:

a) MTA85402 - 04/SS 301

b) MTA85811 - 10I/SS

=

Commercial temperature, SSOP package, 4 MHz, QTP pattern #301

Industrial temperature, SSOP package, 10 MHz

EUROPE

AMERICAS (continued)

AMERICAS

United Kingdom

San Jose

Corporate Office

Arizona Microchip Technology Ltd.

Unit 6, The Courtyard

Meadow Bank, Furlong Road

Bourne End, Buckinghamshire

SL8 5AJ

Tel: 44 0 1628 851077 Fax: 44 0 1628 850259

France

Arizona Microchip Technology SARL

2 Rue du Buisson aux Fraises

91300 Massy - France

Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 Muenchen, Germany

Tel: 49 89 627 144 0 Fax: 49 89 627 144 44

Italy

Arizona Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Pegaso Ingresso No. 2

Via Paracelso 23, 20041

Agrate Brianza (MI) Italy

Tel: 39 039 689 9939 Fax: 39 039 689 9883

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 602 786-7200 Fax: 602 786-7277

Atlanta

Microchip Technology Inc.

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

Tel: 404 640-0034 Fax: 404 640-0307

Boston

Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752

Tel: 408 436-7950 Fax: 408 436-7955

ASIA/PACIFIC

Hong Kong

Microchip Technology Inc.

Unit No. 3002-3004, Tower 1

Metroplaza

223 Hing Fong Road

Kwai Fong, N.T. Hong Kong

Tel: 852 2 401 1200 Fax: 852 2 401 3431

Korea

Tel: 508 480-9990

Fax: 508 480-8575

Microchip Technology Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku,

Seoul, Korea

Tel: 82 2 554 7200 Fax: 82 2 558 5934

Singapore

Microchip Technology Taiwan

Singapore Branch

200 Middle Road

#10-03 Prime Centre

Singapore 0718

Tel: 65 334 8870 Fax: 65 334 8850

Taiwan

Microchip Technology Taiwan

10F-1C 207

Tung Hua North Road

Taipei, Taiwan, ROC

Tel: 886 2 717 7175 Fax: 886 2 545 0139

Chicago

Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 708 285-0071 Fax: 708 285-0075

Dallas

Microchip Technology Inc.

14651 Dallas Parkway, Suite 816

Dallas, TX 75240-8809

Tel: 214 991-7177 Fax: 214 991-8588

Dayton

JAPAN

Microchip Technology Intl. Inc.

Benex S-1 6F

3-18-20, Shin Yokohama

Kohoku-Ku, Yokohama

Kanagawa 222 Japan

Microchip Technology Inc.

35 Rockridge Road

Englewood, OH 45322

Tel: 513 832-2543 Fax: 513 832-2841

Tel: 81 45 471 6166 Fax: 81 45 471 6122

Los Angeles

Microchip Technology Inc.

18201 Von Karman, Suite 455

Irvine, CA 92715

Tel: 714 263-1888 Fax: 714 263-1338

New York

Microchip Technology Inc.

150 Motor Parkway, Suite 416

Hauppauge, NY 11788

Tel: 516 273-5305 Fax: 516 273-5335

Printed in the USA, 8/95

1995, Microchip Technology Inc.

"Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed

by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. Use of Microchip's products as critical components in life support

systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights." The Microchip logo and name are registered trademarks

DS40115C-page 72

1995 Microchip Technology Inc.


型号：	MTA85401-04I/SS
厂家：	MICROCHIP
描述：	8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20, 0.209 INCH, PLASTIC, SSOP-20 可编程只读存储器光电二极管
文件：	总72页 (文件大小：754K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MTA85401-04I/SS [MICROCHIP]

相关型号：

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MTA85401S-04I/SS

MTA85402-04/SS

MTA85402-04/SS301

MTA85402-04E/SS

MTA85402-04I/SS

MTA85402-10/SS