PD69208T4ILQ-TR_技术文档

PD69208T4 and PD69200 Datasheet

8-Port PSE PoE Manager and PSE PoE Controller

Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of

its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the

application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have

been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any

performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all

performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not

rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to

independently determine suitability of any products and to test and verify the same. The information provided by Microsemi

hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely

with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP

rights, whether with regard to such information itself or anything described by such information. Information provided in this

document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this

document or to any products and services at any time without notice.

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One Enterprise, Aliso Viejo,

CA 92656 USA

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www.microsemi.com

About Microsemi

Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for

aerospace & defense, communications, data center and industrial markets. Products include high-performance and

radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;

timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing

devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and

scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design

capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees

globally. Learn more at www.microsemi.com.

Microsemi logo are trademarks of

Microsemi Corporation. All other

trademarks and service marks are the

property of their respective owners.

PD-000303603. 5.0 12/18

Contents

1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Revision 0.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Revision 0.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Revision 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1

2.2

2.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Typical PoE Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

Digital Block Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PD Detection Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Classification Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Current Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Main Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.10.1 PD69208T4 SPI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.10.2 Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.10.3 PD69200 I²C Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1

4.2

4.3

PD69200 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PD69200 Features Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PD69208T4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

4.3.8

4.3.9

Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Port Real Time Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Port Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Port Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Main Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.4

PD69208T4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1

Pin Configuration and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

iii

5.2.1

5.2.2

PD69200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PD69208T4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.3

5.4

PD69200 Recommended PCB Layout for 32 Pin QFN 5mm x 5mm . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PD69208T4 Recommended PCB Layout for 56-Pin QFN 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . 25

6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1

6.2

6.3

6.4

6.5

PD69200 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PD69208T4 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PD69208T4 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Recommended Solder Reflow Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Tape and Reel—Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.5.1

6.5.2

PD69200 Tape and Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PD69208T4 Tape and Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.6

Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1

Connection Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

PD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Legacy Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Port Start Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Over-Load Detection and Port Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Disconnect Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

IC Thermal Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

V_MAINOut of Range Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2-Pair and 4-Pair Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Port Power Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

System OK Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Port Matrix Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Power Good Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

LED Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

7.17

7.18

7.19

7.20

8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

iv

Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Typical PoE Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PD69208T4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SPI Detailed Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PD69200 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PD69208T4 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PD69200 Top-Layer Copper PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PD69200 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array . . . . . . . . . . . . . 24

Top-Copper Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Top-Solder Paste Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Top-Layer Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

BOT and Internal Layers Copper Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Top-Layer Pin Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PD69200 Package Outline Drawing (32 Pin QFN 5 mm x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . 29

PD69208T4 Package Drawing (56 Pin QFN 8 mm x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Classification Reflow Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PD69200 Tape Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PD69200 Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PD69208T4 Tape and Reel Pin-1 Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PD69208T4 Tape Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PD69208T4 Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4-Pair PoE System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Typical IEEE802.3at Port PoE Voltage Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

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Tables

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

SPI Communication – Packet Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PD69208T4 SPI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PD69208T4 Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SPI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

I²C Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PD69200 Features Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PD69208T4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PD69208T4 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PD69208T4 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PD69208T4 Port Real Time Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PD69208T4 Port Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Port Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PD69208T4 Main Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PD69208T4 Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PD69208T4 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PD69208T4 Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PD69200 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PD69208T4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PD69200 Package Outline Dimensions and Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PD69208T4 Package Outline Dimensions and Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PD69208T4 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PD69200 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Classification Reflow Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Pb-Free Process – Package Classification Reflow Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 32

PD69200 Tape Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PD69200 Reel Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PD69208T4 Tape Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PD69208T4 Reel Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

PD69208T4 Manufacturing and Ordering Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 9

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

Table 26

Table 27

Table 28

Table 29

Table 30

Table 31

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

vi

Revision History

1

Revision History

The revision history describes the changes that were implemented in the document. The changes are

listed by revision, starting with the most current publication.

1.1

Revision 5.0

Revision 5.0 of this document was published in December 2018. The following was a summary of the

changes made in this revision:

•

Port real time protection details are updated for I_PORT, I_LIM, I_CUT, I_UDL, P_PWR, and T_MPS. For more

information, see Table 10, page 14.

•

Main voltage information is updated for accuracy. For more information, see Table 13, page 15.

The PD69200 pin diagram is updated. For more information, see Figure 4, page 18.

The Top-Layer Pin Geometry measurement is updated. For more information, see Figure 12,

page 28.

•

The PD692000 Thermal Specifications table is added. For more information, see Table 23, page 31.

The company name Freescale is replaced with NXP across the document.

Updated Figures 8 - 12. For more information, see Figure 8, page 25,Figure 9, page 26, Figure 10,

page 27, Figure 11, page 27, and Figure 12, page 28.

•

Added table footnotes for D, VVVV, and SS. For more information, see the Ordering Information,

page 41.

1.2

Revision 4.0

Revision 4.0 of this document was published in February 2018. The following was a summary of the

changes:

•

Preliminary designation was removed.

Thermal specifications were updated. For more information, see PD69208T4 Thermal

Specifications, page 31.

•

The tape specification was updated. For more information, see Figure 19, page 35.

Tape mechanical data was added. For more information, see Table 28, page 35.

Ordering part numbers were updated. For more information, see Ordering Information, page 41.

1.3

1.4

Revision 3.0

Revision 3.0 of this document was published in November 2017. The following was a summary of the

changes:

•

Maximum storage temperature value is no longer preliminary.

The link to stencil and via plug recommendations was updated.

Application information was updated.

Maximum slew rate requirement of 100 mS was added.

Manufacturing and ordering part number information was updated.

Revision 2.0

Revision 2.0 of this document was published in September 2017. The following was a summary of the

changes:

•

Updated the recommended PCB layout for better manufacturability.

Redefined quiescent current in terms of port threshold.

Added the PD69208T4 Manufacturing and Ordering Part Numbers table.

Added a note about I²C communication configuration.

Added table footnotes for ESD (HBM and CDM).

Updated the main voltage monitoring table for accuracy data.

Updated the Peak Classification Temperature (TP).

Updated the description for pin 24 for PD69200.

Updated the description for pin 19 for PD69208T4.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

1

Revision History

•

Updated the thermal specifications table.

Changed the notation from V_{PORT_NEGx}to V_PORT

Added the PD69208T4ILQ-TR-LE part number details in the ordering table.

Updated the maximum value of Storage Temperature and added a table footnote for the same.

.

1.5

Revision 1.0

Revision 1.0 of this document was published in April 2017. The following was a summary of the changes:

•

Updated the Absolute Maximum Ratings section.

Updated Main Voltage measurement accuracy.

Updated PoH description.

Updated power sequencing.

Updated top marking.

1.6

1.7

1.8

Revision 0.21

Revision 0.21 was published in November 2016. The following was a summary of changes made in this

revision:

•

Removed 2^ndordering information data.

Corrected typos.

Revision 0.12

Revision 0.12 was published in October 2016. The following was a summary of changes made in this

revision:

•

Updated I_portand V_mainaccuracy details.

Updated the Absolute Maximum ratings and storage temperature.

Revision 0.1

Revision 0.1 of this document was published in September 2016. This was the preliminary release.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

2

Overview

2

Overview

Microsemi's PD69208T4 Power over Ethernet (PoE) manager IC integrates power, analog, and state-of-

the-art logic into a single 56-pin, plastic QFN package. The device is used in Ethernet switches and

Midspans to allow network devices to share power and data over the same cable. The PD69208T4

device is an 8-port, mixed-signal, and high-voltage PoE driver. Together with the PD69200 external MCU,

it performs as a PSE system. Microsemi's PoE controller, PD69200, is a cost-effective, pre-programmed

MCU designed to implement enhanced mode.

PD69208T4/PD69200 chip-set supports PoE Powered Device (PD) detection, power-up, and protection

according to IEEE standards, as well as legacy/pre-standard PD detection. It provides PD real-time

protection through the following mechanisms: overload, under-load, over-voltage, over-temperature, and

short-circuit, and enables operation in a standalone mode. It also executes all real-time functions as

specified in IEEE802.3at/bt high-power and Power Over HDbaseT (PoH) standards, including PD

detection, and classification; using Multiple Classification Attempts (MCA).

Note: The chip-set support typical power level of 95 W.

PD69208T4 supports supply voltages between 32 V and 57 V without additional power supply sources. A

system that powers over four pairs can be implemented by combining two ports of PD69208T4, enabling

an extra feature for a simple and low-cost, high-power PD device. An on-going monitoring of system

parameters for the host software is available via communication. Internal thermal protection is

implemented in the chip. PD69208T4 is a low-power dissipation device that uses internal MOSFETs and

internal 0.1  sense resistors.

PD69200 features an ESPI bus for all PD69208T4. It is developed based on NXP Kinetis_L family,

MKL15Z128VFM4, that is embedded with the ARM Cortex™-M0+ core. It also uses I²C or UART

interface to the host CPU, and is designed to support software field upgradable through the

communication interface.

PD69208T4 is available in a 56 pin, 8 mm x 8 mm QFN package. PD69200 is available in 32 pin,

5 mm x 5 mm QFN package.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

3

Overview

2.1

Features

•

8 independent channels

Complies with IEEE802.3af-2003, IEEE802.3at-2009 (including two-event classification), and

IEEE802.3bt

•

Supports Three and Six Event Classification based on PoH

Drives 2-pair power ports or 4-pair ports

Supports pre-standard PD detection

Single DC voltage input (32 V to 57 V)

Built in 3.3 V and 5 V regulators

Input voltage out of range protection

Wide ambient temperature range: -40 °C to +85 °C

On-chip Over-temperature thermal protection and monitoring

Low power dissipation (0.1  sense resistor and 0.2  MOSFET Rdson per channel)

Includes Reset command pin

4 x direct address configuration pins

Continuous port monitoring and system data

Configurable load current setting

Configurable PSE PSE Type AT/AF- Configurable PSE IEEE AF/AT/BT and PoH modes

Power soft start mechanism

Voltage monitoring/protection

Internal power on reset

Emergency power management supporting four configurable power bank I/Os

Advance System Power Management algorithm supports up to 96 physical ports

Can be cascaded to up to 12 PoE devices (96 ports)

Easy system implementation of PD69208T4 and PD69204T4 for multiplications of 4 ports systems.

That is, 12 ports system consists of 1×PD69208T4 and 1×PD69204T4.

Supports both UART and I²C interfaces to host CPU

Backwards compatible with Microsemi communication protocol used at prior generations

LED stream support

•

System OK indication

Disable ports input pin

Software download via I²C or UART

Detailed port status

Programmable threshold temperature alarm limit

Interrupt out pin for system and port events

Forced port power ON function

Port power limit setting

Port matrix and priority

Automatic PoE device type detection

MSL3, RoHS compliant

2.2

Applications

•

Power over Ethernet (all IEEE compliant 2-pair modes)

Supports 4-pair, IEEE802.3bt, and POH

PSE Switches/Routers/Midspans

Industrial automation

PoE for LED lighting

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

4

Overview

2.3

Typical PoE Application

The following figure illustrates the typical PoE application of PD69208T4 and PD69200 devices.

Figure 1 • Typical PoE Application

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Note: Fuses per port are not required for use in circuits with total power level of up to 3kW as the PD69208T4

designed to fulfill limited power source (LPS) requirements per the latest editions of IEC60950-1 and

EN60950-1.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

5

Functional Descriptions

3

Functional Descriptions

The following illustration shows the functional blocks of PD69208T4.

Figure 2 • PD69208T4 Block Diagram

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The following sections describe the functional blocks of PD69208T4.

3.1

Digital Block Module

The logic main control block includes digital timing mechanisms and state machines synchronizing and

activating PoE functions according to PD69200 control commands, such as:

•

Real Time Protection (RTP)

Start Up Macro (DVDT)

Load Signature Detection (RES DET)

Classification Macro (CLASS)

Voltage and Current Monitoring (VCM)

ADC Interfacing

Direct Digital Signals with Analog Block

SPI Communication Block

Registers

3.2

3.3

PD Detection Generator

Upon request from PD69200 to the main control module, the PD detection generator generates four

different voltage levels to ensure a robust AF/AT/BT PD detection functionality.

Classification Generator

Upon request from PD69200 to the main control module, state machine applies a regulated class event

and mark event voltage to ports, as required by IEEE standards.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

6

Functional Descriptions

3.4

Current Limiter

This circuit continuously monitors the current of powered ports and limits the current to a pre-defined

value set by AF/AT/BT/PoH. When the current value exceeds this specific value, the system starts

measuring the elapsed timing. If this interval is greater than a preset threshold, the port is disconnected.

3.5

3.6

Main Power MOSFET

The main power switching FET is used to control PoE current into load.

Analog to Digital Converter

A 10-bit analog to digital converter (ADC) is used to convert analog signals into digital registers for the

logic control module.

3.7

3.8

Power on Reset

Power on Reset (PoR) monitors the internal 3.3 V and 5 V DC levels. If this voltage drops below specific

thresholds, a reset signal is generated, and PD69208T4 is reset.

Voltage Regulator

The voltage regulator generates 3.3 V and 5 V for internal circuitry. These voltages are derived from

V_MAINsupply. To use internal voltage regulator connect:

•

V

_AUX5to DRV_VAUX5

V_AUX3P3to V_{AUX3P3_INT}

There are three options to reduce PD69208T4 power dissipation by regulating voltage outside the chip:

•

Use an external NPN transistor to regulate the 5 V. In this setup, the configuration of regulators pins

should be as follows:

•

DRV_VAUX5 is connected to NPN BASE

_AUX5is connected to NPN EMITTER (Connect Collector to V_MAIN

V_AUX3P3is connected to V_{AUX3P3_INT}

V

)

Supply PD69208T4 with an external 5 V voltage regulator. In this setup, regulators pins

configuration should be as follows:

•

V_AUX3P3is connected to V_{AUX3P3_INT}

DRV_VAUX5 is not connected (left open)

V_AUX5is connected to external 5 V

Supply PD69208T4 with an external 3.3 V voltage regulator. In this setup, regulators pins

configuration should be as follows:

•

V_AUX5is connected to DRV_VAUX5

V_{AUX3P3_INT}is not connected (left open)

V_AUX3P3is connected to external 3.3 V

These options can be implemented simultaneously to reduce power dissipation.

3.9

Clock

PD69208T4 clock (CLK) is an internal 8 MHz clock oscillator.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

7

Functional Descriptions

3.10 SPI Communication

PD69208T4 uses SPI communication in SPI slave mode to communicate with PD69200 MCU. Each

PD69208T4 has an address determined by ADDR0-ADDR3 pins. The PD69200 can support up to 12 ICs

at addresses 0-11. The actual frequency between PD69200 and PD69208T4 ICs is 1 MHz.

The following table lists the SPI communication packet structure.

SPI Communication – Packet Structure

Data Written to IC (in

Table 1 •

Control byte

Selects PD69208T4

According to the

address

write access)

Read from IC (in

(only in read access) read access)

Internal Register

Address

Number of words

R/W Bit

8 bits

R(0)/W(1)

8 bits

8 bits 16 bits

3.10.1 PD69208T4 SPI Addressing

PD69208T4 operates in 8-bit address and 16-bit data. It responds to SPI transaction if the first SPI byte

(IC address byte bits[7:1]) complies with the following:

Table 2 •

PD69208T4 SPI Addressing

3 Bits (bit 7:5)

4 Bits (bit 4:1)

1 Bit (bit 0)

000

Address Input Pin

Read/Write

3.10.2 Broadcast

•

A broadcast command is intended to instruct all connected PD69208T4 ICs to perform a specific

operation.

•

The broadcast command is a write command with the standard packet structure. In a broadcast read

operation, the read data is not valid and the read operation has no impact.

Table 3 •

PD69208T4 Broadcast

3 Bits (bit 7:5)

4 Bits (bit 4:1)

1 Bit (bit 0)

001

0000

Write

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

8

Functional Descriptions

Figure 3 • SPI Detailed Timing Diagram

SPI1 frame

8 SCK clock cycles

D2

8 SCK clock cycles

D3

D5

Noise Spike

D14

D7

D1

D2

D6

D8

D4

D13

CS_N

SCK

D9

D10

MOSI

MISO

D12

D15

D11

The following table lists the SPI timing diagram description.

Table 4 •

SPI Timing Description

Name Min Delay

Max Delay

Description

D1

D2

D3

910 nS

45 %

SPI clock period

SPI duty cycle

55%

340 nS

SPI_CS setup to SPI clock positive edge (delay after

SPI_CS active signal)

D4

D5

340 nS

SPI_CS hold to SPI clock positive edge (delay before

SPI_CS inactive signal)

2 SPI clock cycles

Delay between last SCK in SPI1 frame and first SCK at

adjacent SPI1 frame

D6

D7

D8

1 SPI clock cycles

Between byte 0 (IC address) and byte 1 (address)

Between byte 1 (address) and byte 2 (data).

Between byte 2 (MS data byte) and byte 3 (LS data

byte).

D9

340 nS

MOSI setup time

D10

D11

D12

D13

MOSI hold time

700 nS

MISO tri-state to valid data from clock positive edge

MISO valid data to tri-state from SPI_CS positive edge

1 SPI clock cycles

SPI_CS width (Delay SPI1 frame to adjacent SPI1

frame)

D14

D15

60 nS

Filtered glitch width

D3 + D11 + 24 SPI clock MISO tri-state from SPI_CS negative edge to valid data

cycles

D16

D17

200 nS

MISO setup to SCK positive edge

MISO hold to SCK positive edge

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

9

Functional Descriptions

3.10.3 PD69200 I²C Address Selection

The I²C interface between the host CPU and a specific PD69200 requires setting the PD69200 address.

This is done by applying a specific voltage level to pin #22 (I2C_ADDR_MEAS) as listed in the following

table:

Table 5 •

I²C Address Selection

I2C_ADDR Voltage Level

0.00 to 0.21 VDC

0.21 to 0.41 VDC

0.41 to 0.62 VDC

0.62 to 0.83 VDC

0.83 to 1.03 VDC

1.03 to 1.24 VDC

1.24 to 1.44 VDC

1.44 to 1.65 VDC

1.65 to 1.86 VDC

1.86 to 2.06 VDC

2.06 to 2.27 VDC

2.27 to 2.48 VDC

2.48 to 2.68 VDC

2.68 to 2.89 VDC

2.89 to 3.09 VDC

3.09 to 3.30 VDC

I²C Address (Hexadecimal)

UART

0x4

0x8

0xC

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

Note: UART communications configuration:

•

Bits per second: 19,200 bps

Data bits: 8

Parity: None

Stop bits: 1

Flow control: None

Note: I²C communication configuration:

•

Address: 7 bits

Clock stretch: host should support

Transaction: 15 bytes or 1 byte

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

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Electrical Specifications

4

Electrical Specifications

The following sections describes the electrical characteristics of PD69200 and PD69208T4 devices.

4.1

PD69200 Electrical Characteristics

In this application, PD69200 consumption is ~20mA.

•

Manufacturer: NXP

Manufacturer part number: MKL15Z128VFM4

Maximum pull-ups consumption based on PD69200 application is 2mA. See the hardware

application note document: catalog number PD69208_AN_211

4.2

PD69200 Features Description

The following table lists the main features of PD69200.

Table 6 •

PD69200 Features Description

Features

Description

Supports up to 12 PoE devices -

96 physical ports (48 logical)

Up to 12 PoE devices can be cascaded, fitting into a 96-physical-port PoE

system that uses one PoE controller (PD69200). PD69200 can support up to

48 logical ports. A logical port can be built from 2×Physical ports or

1×Physical port.

Power Management

The system supports three power management modes: Class (LLDP), Dynamic

and Static.

Threshold Configuration

Over-voltage and under-voltage thresholds can be configured for disconnection

purposes.

High Power Ports

(2 pairs or 4 pairs)

PoE devices can be configured (both hardware and software) to enable higher

current through ports (up to ~940 mA) or double power at the RJ in case of

4 pairs.

Communication

Supports both I²C and UART interfaces with the host CPU.

Legacy (reduced capacitance)

Detection

Enables detection and powering of pre-standard devices (PDs) up to 30 µF.

LED Stream

Provides a direct SPI interface to an external LED stream circuitry. Enables

designers to implement a simple LED circuit that does not require a software

code. (LED stream clock frequency is 1 MHz).

System OK Indication

Provides a digital output pin to host. System validity indication, when the system

OK pin state is low. The output behavior is controlled by software mask register

settings (Mask 0×28). The mask default settings is 0, meaning that this pin

indicates valid software and V_mainis within the range. This pin is active low.

For more information, see the Serial Communication Protocol User Guide

document - Catalog Number: PD69200_UG_COMM_PROT).

System and Port Measurements

Detailed Port Status

Interrupt Pin

Measurements of the following parameters: Current (mA),

Power Consumption (W), V_main(V), Port Voltage (V), and PD Class (0-4).

Port statuses are received from PoE managers. Statuses such as port on and

port off due to disconnection or overload.

Interrupt out from PoE controller, PD69200, indicating events such as: port on,

port off, port fault, PoE device fault, voltage out of range, and more. For a full list

of interrupt events, see the Serial Communication Protocol User Guide

document - Catalog Number: PD69200_UG_COMM_PROT.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

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Electrical Specifications

Table 6 •

PD69200 Features Description (continued)

Features

Description

Port Power Limit

Configurable port power limit; when a port exceeds the limit, it is automatically

disconnected.

Port Matrix Control

Enables layout designers to connect any physical port to any logical port as

required.

'Power Good' Interrupt from Power For systems comprising more than a single power supply, when one power

Supply directly to PoE Drivers.

supply fails, a fast port disconnection mechanism is executed to maintain

operation and prevent collapse of other power supplies.

4.3

PD69208T4 Electrical Characteristics

Unless otherwise specified under conditions, the Min and Max ratings stated in the following table apply

to the entire specified operating ratings of the device. Typ values stated are either by design or by

production testing at 25 °C ambient.

Table 7 •

PD69208T4 Electrical Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V_MAIN

Main Supply Voltage

Supports Full

IEEE802.3af/at/bt

functionality

32

57

V

V_PORT

V_TH

Port Output

V_MAIN- V_{PORT_NEGx}

0

57

V

POR Threshold

Internal or External 3.3 V

supply

8

I_MAIN

Main Power Supply

Current @ Operating

Mode.V_MAIN= 55 V

14

mA

V_AUX5

5 V Output Voltage

3.3 V Output Voltage

V_AUX5-AGND

4.5

3

5

5.5

3.6

5

V

V_AUX3P3

I_AUX3P3

V_AUX3P3-AGND

Without external NPN

3.3

V

3.3 V Output Current for

application use

mA

With external NPN

transistor on V_AUX5

30

V_{AUX3P3_IN}

3.3 V Input Voltage

V_AUX3P3-AGND

3

3.3

3.6

V

DV_DD

Digital 3.3 V Input Voltage DV_DD-DGND

3

3.3

3.6

V

POR_TP

Power On Reset DV_DD

Trip Point

DV_DD-DGND

2.575

2.775

2.975

POR_HYS

R_{CH_ON}

Power On Reset DV_DD

Hysteresis

POR_TP-DGND

0.2

0.25

0.34

0.3

V

Total Channel Resistance R_{ds_on}+ R_sense+ R_bonding



Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

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Electrical Specifications

4.3.1

Detection

Table 8 •

PD69208T4 Detection

Symbol

Parameter

Conditions

Min

Typ Max

Units

V_OC

Pre-detection Voltage,

Open-circuit Voltage

V_MAIN- V_{PORT_NEGx}, open port

7.8

V

V_VALID

Detection Voltage

V_MAIN- V_{PORT_NEGx}, for IEEE802.3

compliant signature resistance

(RSIG < 33 K)

9.3

V

I_SC

Short Circuit Current

V_MAIN- V_{PORT_NEGx}= 0 V

388 408

19

µA

R_{SIG_LOW}

Minimum Valid Detection

Resistance

15

K

R_{SIG_HIGH}

Maximum Valid Detection

Resistance

26.5

33

K

4.3.2

Classification

PD69208T4 Classification

Parameter

Table 9 •

Symbol

Conditions

Min

Typ Max

Units

V_CLASS

Class Event Output Voltage V_MAIN- V_{PORT_NEGx}

;

15.5

18

8.5

70

20.5

V

0 mA  I_PORT50 mA

V_MARK

Mark Event Output Voltage V_MAIN- V_{PORT_NEGx}

;

7

10

V

0.1mA  I_PORT5 mA

I_{CLASS_LIM}

Class event

V_MAIN- V_{PORT_NEGx}= 0 V

51

100

mA

current limitation

I_{MARK_ LIM}

Mark event

V_MAIN- V_{PORT_NEGx}= 0 V

51

70

100

mA

current limitation

Classification Current

Thresholds

Class 0

Class 1

Class 2

Class 3

Class 4

Class Error

0

5

mA

8

13

21

31

45

100

16

25

35

51

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

13

Electrical Specifications

4.3.3

Port Real Time Protection

Table 10 • PD69208T4 Port Real Time Protection

Symbol

Parameter

Conditions

Min

Typ Max

Units

T_RISE

Turn on rise time

From 10% to 90% of the voltage

difference at the V_{PORT_NEGx}in

POWER_ON state from the

beginning of POWER_UP

15

µS

I_INRUSH

Output current in

POWER_UP state

C_LOAD180 µF¹

400

425 450

mA

T_INRUSH

I_PORT

Inrush Time

65

360

mS

mA

mS

mA

mS

%

Output Operating Current

802.3af

10

802.3at

620

802.3bt class 5

802.3bt class 6

802.3bt class 7

802.3bt class 8

802.3af

560

692

794

948

I_CUT

Overload Current

375

802.3at

645

802.3bt class 5

802.3bt class 6

802.3bt class 7

802.3bt class 8/PoH²

589

709

825

980

T_CUT

I_LIM

Overload Time Limit

Port Current Limit

62

64

66

802.3af

400

670

790

425 450

720 770

802.3bt class 1-3

802.3at, 802.3bt class 4-6

802.3bt class 7-8/PoH

V_MAIN- V_{PORT_NEGx}< 30 V

> 90 W

850

892

1020 1150 1300

T_LIM

P_PWR

I_UDL

Port Current Limit Time

Port power accuracy

1

2

3

2

9

3

DC Disconnect Under-load 2 Pairs

Current

6

7.5

2.5

mA

mS

4 Pairs (for each pairset)

2

T_MPDO

PD Maintain Power

Signature Dropout Time

Limit

322

324 326

T_MPS

PD Maintain Power

Signature Time For Validity

802.3bt PSE Type 1, 2

802.3bt PSE Type 3, 4

From V_MAINto 2.8V

46

3

48

4

50

5

mS

T_OFF

Turn Off Time

500

1. Can be overridden by communication command.

2. Power port is limited to the maximum of 100 W according to UL’s LPS requirements (Port Power = I_PORT× VMAIN)

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

14

Electrical Specifications

4.3.4

Port Current Monitoring

Table 11 • PD69208T4 Port Current Monitoring

Parameter

Resolution

LSB

Conditions

Typ

10

Max

Units

Bits

µA

mS

%

Reported as 14 Bits

122.07

16

Measurement Period

Accuracy

50 mA < I_PORT< 150 mA

150 mA < I_PORT< 350 mA

350 mA < I_PORT< 600 mA

I_PORT> 600 mA

9

4.5

3.5

3.0

%

4.3.5

4.3.6

Port Voltage Monitoring

Table 12 •

Port Voltage Monitoring

Parameter

Resolution

LSB

Typ

10

Max

Units

Bits

mV

mS

%

58.6

3

Measurement Period

Accuracy

3.3

Main Voltage Monitoring

Table 13 • PD69208T4 Main Voltage Monitoring

Parameter

Resolution

LSB

Conditions

Typ

Max

Units

Bits

mV

mS

%

10

58.6

3

Measurement Period

Accuracy

42 V < V_MAIN< 50 V

50 V < V_MAIN< 57 V

50 V < V_MAIN< 57 V¹

2

1.5

0.6

%

1. 0-70 °C

4.3.7

Temperature Monitoring

Table 14 • PD69208T4 Temperature Monitoring

Parameter

Resolution

LSB

Conditions

Min

Typ

Max

Units

Bits

°C

8

Temperature = (DATA x 1.9384) - 277

1.9384

3

Measurement Period

Accuracy

mS

°C

-3

3

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

15

Electrical Specifications

4.3.8

Digital Interface

Table 15 • PD69208T4 Digital Interface

Symbol

Parameter

Conditions

Min

Typ Max

Units

V_IH

Input Logic High Voltage

RESET_N, MOSI, MISO, SCK,

CS_N, PGD[0..3], ADDR[0..3]

2.2

V

V_IL

Hyst

I_IH

Input Logic Low Voltage

RESET_N, MOSI, MISO, SCK,

CS_N, PGD[0..3], ADDR[0..3]

0.8

V

Input Logic Hysteresis

Voltage

RESET_N, MOSI, MISO, SCK,

CS_N, PGD[0..3], ADDR[0..3]

0.4

-10

2.4

0.6

0.8

10

V

Input Logic High Current

RESET_N, MOSI, MISO, SCK,

CS_N, PGD[0..3], ADDR[0..3]

µA

V

I_IL

Input Logic Low Current

RESET_N, MOSI, MISO, SCK,

CS_N, PGD[0..3], ADDR[0..3]

V_OH

Output Logic High Voltage RESET_N, MOSI, MISO, SCK,

CS_N, PGD[0..3], ADDR[0..3]

IOH = -1mA

V_OL

Output Logic Low Voltage

RESET_N, MOSI, MISO, SCK,

CS_N, PGD[0..3], ADDR[0..3]

IOH = 1mA

0.4

V

4.3.9

Immunity

Table 16 • PD69208T4 Immunity

Symbol

Parameter

Conditions

HBM¹

Min

Typ Max

Units

ESD

ESD rating

CDM²

Surge

Lightning surge³

EN61000 4-5

-1

1

KV

1. ESD HBM complies with JESD22 Class 2 standard.

2. ESD CDM complies with JESD22 Class 1 standard.

3. System level common mode 10/700 µS according to IEC61000-4-5.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

16

Electrical Specifications

4.4

PD69208T4 Absolute Maximum Ratings

PoE performance is not guaranteed when exceeding the recommended rating. Exposure to any stress in

the range between the recommended rating, as listed in the following table, and the absolute maximum

rating should be limited to a short time. Exceeding these ratings may impact long-term operating

reliability.

Table 17 • Absolute Maximum Ratings

Parameters

Min

-0.3

Max

Units

1, 2

Supply Input Voltage (V_MAIN

PORT_NEG[0.7] pins

V_AUX5

)

72

V

V_MAIN+0.5

6

V_AUX3P3, DV_DD

4

Digital pins: MISO, MOSI, SCK, CS_N,

ADDR[3:0], PGD[3:0], RESET_N, TRIM

DV_DD+ 0.3 and < 4.0

Junction Temperature

150

260

150

°C

Lead Soldering Temperature (40s, reflow)

Storage Temperature

-65

1. Power Sequence Requirement: V_main> V_AUX5> V_AUX3P3= T_RIM, DV_DD

.

2. PD69208T4 EPAD is connected by copper plane on PCB to AGND. AGND is ground for IC.

Note: DRV_VAUX5 and I_REFare output pins and should not apply voltage or current. DRV_VAUX5 can be left

open when not used.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

17

Pin Descriptions

5

Pin Descriptions

The PD69200 device has 32 pins and PD69208T4 device has 56 pins, which are described in this

section.

5.1

Pin Configuration and Pinout

The following figures represent the top- and bottom-view of PD69200 and PD69208T4 devices.

Figure 4 • PD69200 Pin Diagram

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Note: The marking position of PD69200 may change subject to NXP practice.

Note: For definitions about markings in the PD69200 pinout diagram, see the ordering information table

(Table 30, page 41).

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

18

Pin Descriptions

Figure 5 • PD69208T4 Pin Diagram

1

42

41

40

42

41

40

39

1

2

3

DGND

N.C

TST

VPORT_NEG0

RESERVED

PGD1

2

3

4

5

6

VPORT_NEG7

4

5

6

39

38

37

VPORT_NEG7

RESERVED

38

37

VPORT_NEG1

VPORT_NEG6

36

35

7

8

7

8

VPORT_NEG1

RESERVED

36

35

VPORT_NEG6

RESERVED

EPAD

PD69208T4

e4

F

R

34

33

34

33

VPORT_NEG2

VPORT_NEG5

9

DATE CODE

10

11

12

32

31

32

31

11

12

RESERVED

VPORT_NEG3

VPORT_NEG4

30

29

30

29

13

14

13

14

VPORT_NEG4

RESERVED

VPORT_NEG3

RESERVED

Bottom View

8×8 QFN – 56L

Top View

8×8 QFN – 56L

Note: For definitions about markings in the PD69208T4 pinout diagram, see the ordering information table

(Table 30, page 41).

5.2

Pin Descriptions

The following sections describe the functional pin descriptions of PD69200 and PD69208T4 devices.

5.2.1

PD69200

The following table lists the functional pin descriptions of the PD69200 device.

Table 18 • PD69200 Pin Description

Number Designator

Type

Thermal

OUT

IN

Description

EPAD

Isolated Thermal PAD, recommended to tie to GND.

Reserved UART.

1

2

3

UART1_TX¹

UART1_RX¹

ESPI_xCS

Reserved UART.

OUT

ESPI Bus to PoE Manager. SPI chip select (Active Low). CS is

asserted during all SPI frame.

4

ESPI_SCK

OUT

ESPI Bus to PoE Manager. SPI clock output to PD6920x, and

LED stream clock output, set to 1 MHz.

5

6

ESPI_MOSI

ESPI_MISO

OUT

IN

SPI packets are transmitted on this line.

ESPI Bus to PoE Manager. SPI Master In Slave Out. SPI

packets are received on this line.

7

8

9

VDDA

Supply

GND

Main Supply 3.3 V.

Analog ground.

VSSA

Analog_IN

Analog_IN Analog input. Should be connected to 3.3 V.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

19

Pin Descriptions

Table 18 • PD69200 Pin Description (continued)

Number Designator

Type

DEBUG

IN

Description

10

11

SWD_CLK

Serial Debug Data Bus Clock.

UART0_RX¹

UART receive from host. 15 byte protocol commands are

received on this line. The baud rate is set to 19,200 bps.

For more information, see the Serial Communication Protocol

User Guide document - Catalog Number:

PD69200_UG_COMM_PROT.

12

UART0_TX¹

OUT

UART transmit to host. 15 byte protocol reply/telemetry are

transmitted on this line. The baud rate is set to 19,200 bps.

For more information, see the Serial Communication Protocol

User Guide document - Catalog Number:

PD69200_UG_COMM_PROT.

13

14

15

16

17

18

19

SWD_DIO

DEBUG

Serial Debug Data Bus.

Reserved (NMI_b)

VDD

IRQ_Input Spare, an external pull-up must be connected.

Supply

GND

Main Supply 3.3 V.

Digital ground.

VSS

EXTAL0 (OSC_IN)²

XTAL0 (OSC_OUT)²

xRESET^(3,4)

Oscillator Oscillator input - Reserved.

Oscillator Oscillator output - Reserved.

IN/OUT

Host Reset input (Active Low). The shortest reset pulse from

the host that is required for the PD69200 application is

150 µSec. PD69200 can generate self-reset. In this case, the

xRESET pin is driven low by the PD69200 for about

100 µSec. It is recommended to connect this pin to a host open

drain output with 10 K pull-up. An 47 nF filter capacitor should

be connected between this pin to GND, close to the PD69200

device. If this pin is connected to a push/pull driver, a serial

resistor of 1.5 K must be connected instead of the pull-up.

The required shortest reset pulse in this case is 300 µSec.

For more information about this pin connectivity, see the

Hardware Application Note, Catalog Number:

PD69208_AN_211.

20

21

I2C0_SCL⁴

I2C0_SDA⁴

IN/OUT

I²C clock from the host master. Speed is limited to 400 KHz and

clock stretching functionality must be implemented in the host

master. If PD69200 is busy, it holds the clock line.

I²C bidirectional data. 15 byte protocol messages are

transmitted on this line.

For more information, see the Serial Communication Protocol

User Guide document - Catalog Number:

PD69200_UG_COMM_PROT.

22

I2C_ADDR_MEAS

Analog_IN I²C address of PD69200. Analog input to determine I²C

address or UART operation. See I²C address selection in

Table 5, page 10.

23

24

Analog_IN

Analog_IN Reserved analog input. connect to GND.

xI2C_MESSAGE_READY³

OUT

I²C message ready for read by the host. PD69200 asserts this

line low when it has an answer to the host. Therefore, the host

can poll this line and initiate I²C read cycle only when the

message is ready. This pin is active low.

After the host reads the data from PD69200, this pin is

asserted to high.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

20

Pin Descriptions

Table 18 • PD69200 Pin Description (continued)

Number Designator

Type

Description

25

xINT_OUT^{(3, 4)}

OUT

Interrupt output indication. This line is asserted low when a

pre-configured event is in progress. The host configures the

event that should generate an interrupt through 15 bytes

protocol. When this event occurs, the xINT_OUT pin is

asserted. This pin is active low.

26

27

28

29

xLED_CS³

xLED_LATCH³

xLED_OE³

Reserved

OUT

IN

Chip select signal for LED stream. This pin is active low.

Latch signal for LED stream. This pin is active low.

Output enable signal for LED stream. This pin is active low.

Reserved for MPRPD counter for future support. If not used,

connect to VDD.

30

31

FAN_CONTROL

OUT

IN

Optional. Fan control operates a fan, when the PD69208T4

device temperature is above the temperature alarm threshold.

This pin is active high.

xDISABLE_PORTS³

Disable all PoE ports. When this input is asserted low, the

PD69200 device shuts down all of the PoE ports in the system.

This pin contains software filter of 480 mSec to reject noise and

false disable scenarios.

32

xSys_OK/LED System OK³

OUT

System validity indication. When the system is in OK state, the

pin state is low. The behavior of this output is controlled by

software mask register settings (Mask 0x28). The mask default

settings is 0, meaning that this pin indicates valid software, and

V_mainis in range. This pin is active low.

For more information, see the Serial Communication Protocol

User Guide document - Catalog Number:

PD69200_UG_COMM_PROT.

1. Weak pull-up is recommended. See the PD69208_AN_211 document.

2. The oscillator pins are reserved and unused. The MCU uses internal clock source set to 47.972MHz +/- 1.5% (max).

3. The initial x indicates that the pin is active low.

4. Open drain output requires an external pull-up. See the Hardware Application Note: PD69208_AN_211 document.

Note: All I/Os in this application can sink or source 3 mA maximum.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

21

Pin Descriptions

5.2.2

PD69208T4

The following table lists the functional pin descriptions for the PD69208T4 device.

Table 19 • PD69208T4 Pin Description

Number

Designator

Type

Description

EPAD

Exposed PAD: Connect to analog ground. A decent ground

plane should be deployed around this pin whenever possible.

See the PD69208 Layout Design Guidelines in the hardware

application note, Catalog Number: PD69208_AN_211.

1

N.C

N/A

Not connected. Do not connect externally (leave floating).

Test pin for production use only. Keep connected to DGND.

Negative port 0 output.

2

TST

Digital Input

Analog I/O

N/A

3

VPORT_NEG0

RESERVED

VPORT_NEG1

RESERVED

VPORT_NEG2

RESERVED

VPORT_NEG3

RESERVED

AGND

4

Negative port 0 output.

5

Reserved pin. Do not connect externally.

Negative port 1 output.

6

Analog I/O

N/A

7

Negative port 1 output.

8

Reserved pin. Do not connect externally.

Negative port 2 output.

9

Analog I/O

N/A

10

11

12

13

14

15

16

17

Negative port 2 output.

Reserved pin. Do not connect externally.

Negative port 3 output.

Analog I/O

N/A

Negative port 3 output.

Reserved pin. Do not connect externally.

Analog ground.

Power

RESERVED

VMAIN

N/A

Reserved pin. Do not connect externally.

Power

Main High Voltage Supply voltage. A low ESR 1µF (or higher)

bypass capacitor, connected to AGND, should be placed as

close as possible to this pin through low resistance traces.

18

19

N.C

N/A

Not connected. Do not connect externally.

DRV_VAUX5

Power

Driven outputs for 5 V external regulation; if internal regulation is

used, connect to pin 20. If an external NPN is used to regulate

the voltage, connect this pin to Base.

If an NPN is used, a 4.7 µF capacitor should be connected

between this pin and AGND.

20

VAUX5

Power

Regulated 5 V output voltage source; A 4.7 µF or higher filtering

capacitor should be connected between this pin and AGND. If

an external NPN is used to regulate the voltage, connect this pin

to the emitter. The collector should be connected to V_main

.

21

22

AGND

Power

Analog ground

VAUX3P3

Regulated 3.3 V output voltage source. A 4.7 µF or higher

filtering capacitor should be connected between this pin and

AGND. When an external 3.3 V regulator is used, connect it to

this pin to supply the chip.

23

VAUX3P3_INT

Power

Connected to V_AUX3P3(pin 22) if internal 3.3 V regulator is used.

Leave unconnected (Floating) if external 3.3 V regulator is used.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

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Pin Descriptions

Table 19 • PD69208T4 Pin Description (continued)

Number

Designator

Type

Description

24

IREF

Analog Input

Reference resistor pin. Connect a 28.7 k 1% resistor to AGND.

Use 0.1% resistor in BT/PoH applications.

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

TRIM

Test Input

N/A

Test Input pin; Keep connected to V_AUX3P3

Reserved pin. Do not connect externally.

Analog ground.

.

RESERVED

AGND

N/A

Power

RESERVED

VPORT_NEG4

RESERVED

VPORT_NEG5

RESERVED

VPORT_NEG6

RESERVED

VPORT_NEG7

PGD1

N/A

Reserved pin. Do not connect externally.

Negative port 4 output.

Analog I/O

N/A

Negative port 4 output.

Reserved pin. Do not connect externally.

Negative port 5 output.

Analog I/O

N/A

Negative port 5 output.

Reserved pin. Do not connect externally.

Negative port 6 output.

Analog I/O

N/A

Negative port 6 output.

Reserved pin. Do not connect externally.

Negative port 7 output.

Analog I/O

Digital I/O

Power

Negative port 7 output.

Power good input from system power supply.

Digital ground.

DGND

DVDD

Power In

Regulated 3.3 V for digital circuitry. Connect voltage from pin

V_AUX3P3or from external power supply source if used. A 1 µF or

higher filtering capacitor should be connected between this pin

and DGND.

44

RESET_N

Digital Input

Reset input - active low (0 = reset). An external 10 K pull-up

resistor should be connected between this pin and DVDD.

45

46

47

48

49

50

51

52

53

54

55

56

N.C

N/A

Not connected. do not connect externally.

Power good input from system power supply.

SPI address bit 0 to set chip address.

SPI address bit 1 to set chip address.

SPI address bit 2 to set chip address.

SPI address bit 3 to set chip address.

SPI bus, chip select.

PGD2

PGD3

ADDR0

ADDR1

ADDR2

ADDR3

CS_N

SCK

Digital Input

Digital Output

Digital Input

SPI bus, serial clock Input.

MOSI

MISO

PGD0

SPI bus, Master Data out/slave in.

SPI bus, Master Data in/slave out.

Power good input from system power supply.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

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Pin Descriptions

5.3

PD69200 Recommended PCB Layout for 32 Pin QFN

5mm x 5mm

The following figures illustrate the PCB layout pattern for PD69200. Units are in mm.

Figure 6 • PD69200 Top-Layer Copper PCB Layout

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Figure 7 • PD69200 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array

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Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

24

Pin Descriptions

5.4

PD69208T4 Recommended PCB Layout for 56-Pin QFN

8mm x 8mm

The following figures illustrate the PCB layout pattern for PD69208T4. Units are in mm.

Figure 8 • Top-Copper Layer

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Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

25

Pin Descriptions

Figure 9 • Top-Solder Paste Layer

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Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

26

Pin Descriptions

Figure 10 • Top-Layer Mask

Figure 11 • BOT and Internal Layers Copper Plane

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Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

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Pin Descriptions

Figure 12 • Top-Layer Pin Geometry

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Note: The CM has latitude to modify the solder paste stencil for manufacturability reasons. The solder paste

stencil shall cover 65% to 80% of the thermal pad and must not allow solder to be applied to the thermal

vias under the QFN package using any method they deem appropriate. Any design should be subject to

system validation and qualification prior to commitment to mass production of field deployment.

Use a 5 mil stencil.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

28

Package Information

6

Package Information

This chapter describes package drawings of PD69200 and PD69208T4 devices.

6.1

PD69200 Package Outline Drawing

The following figure illustrates the package drawing of PD69200 device.

Figure 13 • PD69200 Package Outline Drawing (32 Pin QFN 5 mm x 5 mm)

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The following table lists the dimensions and measurements of the PD69200 package.

Table 20 • PD69200 Package Outline Dimensions and Measurements

Dimension

Millimeters

Max

Inches

Max

Min

A

0.80

1.00

0.031

0.039

0.002

A1

A3

K

0.00

0.05

0

0.20 REF

0.20 MIN

0.50 BSC

0.30

0.008 REF

0.008 MIN

0.02 BSC

0.012

e

L

0.50

0.30

3.70

0.02

b

0.18

0.007

0.012

0.147

D2

E2

D

3.50

0.138

3.50

0.138

5.00 BSC

0.197 BSC

E

Note: Dimensions do not include protrusions; they should not exceed 0.155 mm (.006) on any side. Lead

dimension should not include solder coverage. Dimensions are in millimeters and inches for reference.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

29

Package Information

6.2

PD69208T4 Package Outline Drawing

The following figure illustrates the package drawing of the PD69208T4 package.

Figure 14 • PD69208T4 Package Drawing (56 Pin QFN 8 mm x 8 mm)

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The following table lists the dimensions and measurements of the PD69208T4 package.

Table 21 • PD69208T4 Package Outline Dimensions and Measurements

Dimension

Millimeters

Max

Inches

Max

Min

A

0.80

1.00

0.031

0.039

0.002

A1

A3

K

0.00

0.05

0

0.20 REF

0.20 MIN

0.50 BSC

0.30

0.008 REF

0.008 MIN

0.02 BSC

0.012

e

L

0.50

0.30

6.75

0.02

b

0.18

0.007

0.012

0.267

D2

E2

D

6.50

0.256

6.50

0.256

8.00 BSC

0.315 BSC

E

Note: Dimensions do not include protrusions; they should not exceed 0.155mm (.006) on any side. Lead

dimension should not include solder coverage. Dimensions are in millimeters and inches for reference.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

30

Package Information

6.3

PD69208T4 Thermal Specifications

The following tables list the thermal specifications of PD69208T4 and PD69200.

Table 22 • PD69208T4 Thermal Specifications

Thermal Resistance Typ

Units

Notes

_JA

19.0

°C/W

Junction-to-ambient thermal

resistance.

_JT

0.05

°C/W

Junction-to-top thermal

characterization parameter. A thermal

metric derived from the difference in

junction temperature (TJ) and

package top temperature (TT) divided

by total heating power (PH).

_{JC (top)}

_JB

4.9

2.2

°C/W

Junction-to-case thermal resistance

with heat flow through package top.

Junction-to-board thermal resistance.

Note: All parameters are as per JEDEC JESD-51.

Table 23 • PD69200 Thermal Specifications

Thermal Resistance Typ

Units

Notes

_JA

33

°C/W

Junction-to-ambient thermal

resistance.

_JT

8

°C/W

Junction-to-top thermal

characterization parameter. A thermal

metric derived from the difference in

junction temperature (TJ) and

package top temperature (TT) divided

by total heating power (PH).

_{JC (top)}

_JB

1.8

12

°C/W

Junction-to-case thermal resistance

with heat flow through package top.

Junction-to-board thermal resistance.

6.4

Recommended Solder Reflow Information

•

RoHS 6/6

Pb-free 100% Matte Tin Finish

Package Peak Temperature for Solder Reflow(40 seconds maximum exposure)—260 °C

(+0 °C, -5 °C)

Table 24 • Classification Reflow Profiles

Profile Feature

Sn-Pb Eutectic Assembly Pb-Free Assembly

Average Ramp-up Rate (TS_maxto Tp) 3 °C/second max

Preheat

3 °C/second max

Temperature Min (TS_min

Temperature Max (TS_max

Time (ts_minto ts_max

)

100 °C

150 °C

60 - 120 seconds

150 °C

200 °C

60 - 180 seconds

)

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

31

Package Information

Table 24 • Classification Reflow Profiles

Profile Feature

Sn-Pb Eutectic Assembly Pb-Free Assembly

Time Maintained

Temperature (T_L)

Time (t_L)

183 °C

60 - 150 seconds

217 °C

60 - 150 seconds

Peak Classification Temperature (T_P) 210 - 235 °C

240 - 255 °C

Time within 5 °C of actual peak

temperature (tp)

10 - 30 seconds

20 - 40 seconds

Ramp-Down Rate

6 °C/second max

6 minutes max

6 °C/second max

8 minutes max

Time 25 °C to Peak Temperature

Figure 15 • Classification Reflow Profiles

Table 25 • Pb-Free Process – Package Classification Reflow Temperatures

Volume mm³

Package Thickness Volume mm³< 350

350 – 2000

260 +0 °C

250 +0 °C

245 +0 °C

Volume mm³> 2000

260 +0 °C

< 1.6 mm¹

260 +0 °C

250 +0 °C

1.6 mm - 2.5 mm¹

2.5 mm¹

245 +0 °C

1. Tolerance: The device manufacturer or supplier should assure process compatibility up to and

including the stated classification temperature, meaning that the Peak reflow temperature is +0

°C. For example, 260 °C to 0 °C, at the rated MSL value.

Note: Exceeding the ratings that are mentioned in Table 25, page 32 may cause damage to the device.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

32

Package Information

6.5

Tape and Reel—Packaging Information

The following sections provide the tape and reel information.

6.5.1

PD69200 Tape and Reel Specification

Figure 16 • PD69200 Tape Specification

The following table lists the PD69200 tape mechanical data.

Table 26 • PD69200 Tape Mechanical Data

Dimensions Value (mm)

Value (inches)

0.059 + 0.004/0

0.069 ±0.004

0.157 ±0.004

0.0118 ±0.003

0.059

D

1.50 + 0.1/0

1.75 ±0.1

4.00 ±0.1

0.3 ±0.05

1.5

E

P0

T (max)

D1

F

5.5 ±0.1

1.6 ±0.1

2.00 ±0.1

30

0.216 ±0.003

0.0.63 ±0.004

0.079 ±0.004

1.181

K (max)

P2

R

W

12.00 ±0.3

8.00 ±0.1

1.1

0.472 ±0.012

0.31 ±0.004

0.043

P1

K0

A0

5.30

0.208

B0

5.30

0.208

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

33

Package Information

Figure 17 • PD69200 Reel Specification

The following table lists the PD69200 reel mechanical data.

Table 27 • PD69200 Reel Mechanical Data

Dimensions Value (mm) Value (inches)

Tape size

W1

12 +0.3

12.4

0.472 +0.012

0.488

W2

18.4

0.724

W3

15.4

0.606

6.5.2

PD69208T4 Tape and Reel Specification

Figure 18 • PD69208T4 Tape and Reel Pin-1 Orientation

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

34

Package Information

Figure 19 • PD69208T4 Tape Specifications

The following table lists the PD69208T4 tape mechanical data.

Table 28 • PD69208T4 Tape Mechanical Data

Dimension

A0

Value (mm)

8.35 ±0.10

1.40 ±0.10

N/A

B0

K0

K1

Pitch

Width

12.00 ±0.10

16.00 ±0.30

Figure 20 • PD69208T4 Reel Specifications

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

35

Package Information

Table 29 • PD69208T4 Reel Mechanical Data

Dimensions

Tape size

A max.

B max

Value (mm)

16.00 ±0.3

330

Value (inch)

0.630 ±0.012

13"

1.5

0.059

C

13.0 ±0.20

20.2

0.512 ±0.008

0.795

D min.

N min.

50

1.968

G

16.4+2.0/-0.0

29

0.645+ 0.079/-0.0

1.142

T max

BASE QUANTITY

2000 pcs.

6.6

Reference Documents

•

IEEE Std 802.3-2018 Clause 33 Power over Ethernet over 2-Pair and Clause 145 Power over

Ethernet

Microsemi, Serial communication protocol user guide, Catalog Number:

PD69200_UG_COMM_PROT

Microsemi, Designing 48-port Enhanced PoE System (802.3af/802.3at Compliant) application note,

Catalog Number: PD69208_AN_211

•

Microsemi, PoE LED Stream Interface technical note, Catalog Number: PD69200_TN_218

Microsemi, Design for surge immunity within PSE systems, Catalog Number: PD69208/4_TN_205

Microsemi, PD69204T4 and PD69200 datasheet, Catalog Number: DS_PD69204T4_PD69200

NXP, Kinetis_L MKL15Z128VFM4 datasheet

NXP package drawings 98ASA00473D

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

36

Application Information

7

Application Information

PD69208T4/PD69200 PSE Chipset performs IEEE802.3af (Type 1), IEEE802.3at (Type 2), Power over

HDBaseT (POH), and IEEE802.3bt (Type 3 and 4) PSE functionalities in addition to pre-standard and

legacy (capacitor) detection. Moreover, it includes additional protections such as short circuit and dV/dT

protection upon startup.

Note: IEEE802.3bt functionality will be enabled by a firmware upgrade.

7.1

7.2

Connection Check

An additional PD construction detection phase named, connection check, is done to detect which PD

configuration is connected (single-signature or dual-signature) per the IEEE802.3bt standard.

PD Detection

The PD detection feature detects a valid IEEE802.3af, IEEE802.3at or IEEE802.3bt. The PD detection is

done based on four different voltage levels generated over PD (the load) as illustrated in Figure 22,

page 38.

7.3

7.4

Legacy Detection

When legacy detection is enabled, the PD detection mechanism detects and powers up legacy and

pre-standard PDs as well as IEEE802.3af, IEEE802.3at and IEEE802.3bt standard compliant PDs

(Classes 0 - 8)

Classification

The classification process takes place immediately after PD detection is successfully completed. The

goal of the classification process is to detect PD class as specified in IEEE802.3 standards.

In IEEE802.3af mode, the classification mechanism is based on a single voltage level (single event). In

IEEE802.3at and IEEE802.3bt modes, the classification mechanism is based on two voltage levels

(multiple events) as defined in IEEE802.3-2015 Clause 33 and IEEE802.3bt. In PoH mode, the

classification mechanism is based on three events classification as defined in HDBaseT standard.

Figure 21 • 4-Pair PoE System Diagram

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Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

37

Application Information

Figure 22 • Typical IEEE802.3at Port PoE Voltage Diagram

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7.5

7.6

Port Start Up

Upon a successful detection and classification process, power is applied to the load via a controlled start

up mechanism.

During this period, inrush current is limited to 425 mA for a typical duration of 65 mS, which allows PD

load to charge and allows steady state of power condition.

Over-Load Detection and Port Shut Down

After power up, PD69208T4 automatically initializes its internal protection mechanisms. These

mechanisms are used to monitor and disconnect power from the PD when extreme conditions occur, as

specified in the IEEE802.3 standards. These conditions include over-current or short ports terminals

scenarios.

7.7

7.8

Disconnect Detection

PD69208T4 supports the DC disconnect function as per IEEE802.3 standards. This mechanism

continuously monitors load current and disconnects power according to I_UDL, T_MPDO, and T_MPS

parameters as specified in Table 10, page 14.

IC Thermal Monitoring

PD69208T4 contain a thermal sensor that is sampled by the PD69200 for every 20 mS so that the

PD69208T4 die temperature is monitored at all times. To protect the PD69208T4 device from damage,

the system ports are disconnected before damage can occur.

A temperature alarm threshold can be set by PD69200 controller to send interrupt indication by the

xINT_OUT pin before ports are disconnected. The temperature can be read and monitored by the host

as well, if required.

7.9

Over-Temperature Protection

In addition to the die thermal sensor, there are thermal sensors on each MOSFET that continuously

monitors each port main MOSFETs junction temperature, and shuts down the port load power when the

temperature exceeds 200 °C.

7.10 V

Out of Range Protection

MAIN

The system automatically disconnects ports power when V_MAINexceeds the pre-configured over-voltage

and under-voltage thresholds.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

38

Application Information

7.11 2-Pair and 4-Pair Ports

Operation modes include the following:

•

POE Type 1/2 class 0-4 (up to 30 W)

POE Type 3 class 0-4 2-Pair and class 5-6 4-Pair (up to 60 W)

POE Type 4 class 7/8 4-Pair (75 W/90 W)

POH Mode: 4-Pair (up to 95 W)

Note: For more information about 4-Pair operation modes and power configuration, see

Microsemi_PoE_4_Pair_Behavior_PD6920x_PSE_Application_Note_160159.

7.12 Power Management

System supports three power management modes:

•

Class (LLDP and CDP)

Dynamic

Static

7.13 Port Power Limit

Port power limit (PPL) is used to configure port power limit. When a port exceeds the power limit, it gets

disconnected automatically.

7.14 Reset Pin

xRESET pin is PD69200 digital host reset input (Active Low). The shortest pulse that is guaranteed to be

recognized is 150 µSec. PD69200 can generate self-reset. In this case xRESET pin is driven low by

PD69200 for about 100 µSec. It is recommended to connect this pin to a host open drain output with pull-

up in a range of 4.7 K to 10 K. If this pin is connected to a push/pull driver, a serial resistor of 4.7 K

must be connected instead of pull-up. Avoid resetting the PD69208T4 IC directly by the RESET_N pin.

PD69200 controls the PD69204T4 ICs when system reset is needed.

For more information about this pin connectivity, see the hardware application note, Catalog Number:

PD69208_AN_211.

7.15 System OK Indication

Digital output pin to host is used as a system validity indication. When system is OK pin state is low. The

behavior of this output is controlled by software mask register settings (Mask 0×28). The mask default

settings is 0, meaning that this pin indicates valid software and V_mainis in range. This pin is active low.

For more information, see the Serial Communication Protocol User Guide document - Catalog Number:

PD69200_UG_COMM_PROT.

7.16 Interrupt Pin

Interrupt out from PoE controller, indicating events such as: port on, port off, port fault, PoE device fault,

voltage out of range, and more. For a full list of interrupt events, see the Serial Communication Protocol

User Guide document - Catalog Number: PD69200_UG_COMM_PROT. This pin is active low.

7.17 Port Matrix Control

Port matrix control enables layout designers to ascribe each physical port in the system to a logical port if

required.

7.18 Power Good Interrupt

Interrupt from power supply directly to PD69208T4 manager. For systems comprising more than a single

power supply, in case one power supply fails, a port shutdown mechanism is executed to maintain

operation and prevent collapse of other power supplies.

When function is used, PGD0, PGD1, PGD2, and PGD3 should be connected to main power supplies

status indication pin. Any change of at least 1 µS on these lines triggers a pre-defined disconnection

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

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Application Information

matrix. This matrix is defined by PD69200 system power parameters. The port shutdown function reacts

within 2 µS to any power good event.

7.19 LED Stream

The direct SPI interface to an external LED stream circuitry that can drive LEDs directly without the host

intervention. It enables designers to implement a simple LED circuit that does not require a software

code. The LED stream clock frequency is 1 MHz.

For more information, see the TN-218, catalog number PD69200_TN_218.

7.20 Power Sequencing

Figure 23 • Power Sequencing

9

9PDLQꢁꢁ

ꢋꢁ9

ꢄꢂꢄꢁ9

7Gꢆ

7Gꢀ

7Gꢊ

7

7Gꢄ

When using external V_aux5or V_aux3p3

•

Td1: V_mainat 5 V to V_aux5> 0 µS

Td2: V_aux5to V_aux3p3> 0 µS

Td3: V_aux3p3to V_aux5> 0 µS

Td4: Vaux5 to V_mainat 5 V > 0 µS

DV_DD= V_aux3p3

Note: See the Application Note AN211 - Designing a PD69208 48-port PoE System 802.3af/802.3at compliant.

For proper operations, you need to ensure that V_mainis always in the highest voltage connected to the

IC. With an external DC-DC converter, the maximum 3.3 V slew rate is 100 mS.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

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Ordering Information

8

Ordering Information

The following table the part ordering information for PD69200 and PD69208T4 devices.

Table 30 • Ordering Information

Packaging

Type

Part Number

Package

Temperature

Part Marking

Tray Marking

PD69200D¹-VVVV²SS³

Plastic QFN

5 mm × 5 mm

(32 lead)

Tray

–40 °C to 85 °C Microsemi Logo PD69200D-

NXP Logo

69200

VVVVSS

PD-OOOOG3bb⁷

YYWW

M15M7V⁴

XXXXX⁵

YYYYY⁶

PD69200D-VVVVSS-TR

Plastic QFN

Tape and

–40 °C to 85 °C Microsemi Logo PD69200-

5 mm × 5 mm Reel

(32 lead)

NXP Logo

69200

VVVVSS-TR

PD-OOOOT3bb⁷

YYWW

M15M7V⁴

XXXXX⁵

YYYYY⁶

PD69208T4ILQ-TR-LE

PD69208T4ILQ-TR

Plastic QFN

8 mm × 8 mm Reel

(56 lead)

Tape and

–40 °C to 85 °C Microsemi Logo

PD69208T4

F R e4⁸

YYWWAZZ⁹

Plastic QFN

8 mm × 8 mm Reel

(56 lead)

Tape and

–40 °C to 85 °C Microsemi Logo

PD69208T4

F R e4⁸

YYWWAZZ⁹

1. D stands for the detection method set as: C: Detection Method = IEEE802.3 and pre-standard;

R: Detection Method = IEEE802.3.

2. VVVV is firmware revision

3. SS stands for firmware parameters option

4. Short part number

5. Mask set

6. Date code

7. MKTG Product Type (Detection = R: Resistor/D = C: Resistor/Legacy)/Version/SW Parameters/Operation P/N.

8. F = FAB Code, R = Product revision code (D for V2R2 and E for V2R4), and e4 = 2^ndlevel interconnect.

9. YY = Year, WW = Week, A = Assembly location, and ZZ = assembly lot sequence code.

The Firmware Release Notes has all the required information about how to specify the choice of VVVV

and SS. You can find the Firmware Release Notes in the Microchip Software Libraries, and register

yourself to a My Microchip account to have access to the release notes.

Note: The package meets RoHS, Pb-free, and MSL3 of the European Council to minimize the environmental

impact of electrical equipment.

Note: Initial burning of controller's firmware is performed in factory. Firmware upgrades can be performed by

users using communication interface. For more information, see TN-140, Catalog Number: 06-0024-081.

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Ordering Information

The following table lists the manufacturing and ordering part numbers of PD69208T4 devices.

Table 31 • PD69208T4 Manufacturing and Ordering Part Numbers

Ordering Part Number Die Revision Product Revision Code Manufacturing Part Number

PD69208T4ILQ-TR-LE V2R4

PD69208T4ILQ-TR V2R4

E

PD69208T4ILQ-TR-LE

Note: Customers can order the PD69208T4 device using either the ordering part number or the manufacturing

part number. See Table 30, page 41 for package, packing type, temperature, and part marking

information.

Microsemi Proprietary and Confidential PD69208T4 and PD69200 Datasheet Revision 5.0

42


型号：	PD69208T4ILQ-TR
厂家：	MICROCHIP
描述：	Telecom Circuit 电信电信集成电路
文件：	总48页 (文件大小：1335K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PD69208T4ILQ-TR [MICROCHIP]

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