PIC10F204-E/MC_技术文档

PIC10F200/202/204/206

Data Sheet

6-Pin, 8-bit Flash Microcontrollers

DS41239D

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and

SmartShunt are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC^®DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS41239D-page ii

PIC10F200/202/204/206

6-Pin, 8-Bit Flash Microcontrollers

Devices Included In This Data Sheet:

Low-Power Features/CMOS Technology:

• Operating Current:

• PIC10F200

• PIC10F202

• PIC10F204

• PIC10F206

- < 175 μA @ 2V, 4 MHz, typical

• Standby Current:

High-Performance RISC CPU:

- 100 nA @ 2V, typical

• Low-power, high-speed Flash technology:

• Only 33 single-word instructions to learn

- 100,000 Flash endurance

- > 40 year retention

• All single-cycle instructions except for program

branches, which are two-cycle

• Fully static design

• 12-bit wide instructions

• Wide operating voltage range: 2.0V to 5.5V

• Wide temperature range:

• 2-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

for data and instructions

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• 8-bit wide data path

• 8 Special Function Hardware registers

• Operating speed:

Peripheral Features (PIC10F200/202):

• 4 I/O pins:

- 4 MHz internal clock

- 1 μs instruction cycle

- 3 I/O pins with individual direction control

- 1 input-only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pull-ups

Special Microcontroller Features:

• 4 MHz precision internal oscillator:

- Factory calibrated to ±1%

• 8-bit real-time clock/counter (TMR0) with 8-bit

programmable prescaler

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) support

• Power-on Reset (POR)

Peripheral Features (PIC10F204/206):

• 4 I/O pins:

• Device Reset Timer (DRT)

- 3 I/O pins with individual direction control

- 1 input-only pin

• Watchdog Timer (WDT) with dedicated on-chip

RC oscillator for reliable operation

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pull-ups

• Programmable code protection

• Multiplexed MCLR input pin

• Internal weak pull-ups on I/O pins

• Power-Saving Sleep mode

• 8-bit real-time clock/counter (TMR0) with 8-bit

programmable prescaler

• Wake-up from Sleep on pin change

• 1 Comparator:

- Internal absolute voltage reference

- Both comparator inputs visible externally

- Comparator output visible externally

TABLE 1-1:

PIC10F20X MEMORY AND FEATURES

Program Memory

Data Memory

Timers

8-bit

Device

I/O

Comparator

Flash (words)

SRAM (bytes)

PIC10F200

PIC10F202

PIC10F204

PIC10F206

256

512

256

512

16

24

16

24

4

1

0

1

DS41239D-page 1

PIC10F200/202/204/206

SOT-23 Pin Diagrams

GP0/ICSPDAT

VSS

GP3/MCLR/VPP

VDD

1

2

3

6

5

4

GP1/ICSPCLK

GP2/T0CKI/FOSC4

GP0/ICSPDAT/CIN+

VSS

GP3/MCLR/VPP

VDD

1

6

2

3

5

4

GP1/ICSPCLK/CIN-

GP2/T0CKI/COUT/FOSC4

8-Pin PDIP Pin Diagrams

N/C

VDD

1

2

3

4

8

GP3/MCLR/VPP

VSS

7

6

5

GP2/T0CKI/FOSC4

GP1/ICSPCLK

N/C

GP0/ICSPDAT

N/C

VDD

1

8

GP3/MCLR/VPP

VSS

2

3

4

7

6

5

GP2/T0CKI/COUT/FOSC4

GP1/ICSPCLK/CIN-

N/C

GP0/ICSPDAT/CIN+

8-Pin DFN Pin Diagrams

1

2

3

4

8

7

6

5

N/C

VDD

GP3/MCLR/VPP

VSS

N/C

GP2/T0CKI/FOSC4

GP1/ICSPCLK

GP0/ICSPDAT

N/C

VDD

1

2

3

4

8

7

6

5

GP3/MCLR/VPP

VSS

GP2/T0CKI/COUT/FOSC4

GP1/ICSPCLK/CIN-

N/C

GP0/ICSPDAT/CIN+

DS41239D-page 2

PIC10F200/202/204/206

Table of Contents

1.0 General Description...................................................................................................................................................................... 5

2.0 PIC10F200/202/204/206 Device Varieties .................................................................................................................................. 7

3.0 Architectural Overview ................................................................................................................................................................. 9

4.0 Memory Organization................................................................................................................................................................. 15

5.0 I/O Port....................................................................................................................................................................................... 25

6.0 Timer0 Module and TMR0 Register (PIC10F200/202)............................................................................................................... 29

7.0 Timer0 Module and TMR0 Register (PIC10F204/206)............................................................................................................... 33

8.0 Comparator Module.................................................................................................................................................................... 37

9.0 Special Features of the CPU...................................................................................................................................................... 41

10.0 Instruction Set Summary............................................................................................................................................................ 51

11.0 Development Support................................................................................................................................................................. 59

12.0 Electrical Characteristics............................................................................................................................................................ 63

13.0 DC and AC Characteristics Graphs and Tables......................................................................................................................... 73

14.0 Packaging Information................................................................................................................................................................ 81

Index .................................................................................................................................................................................................... 89

The Microchip Web Site....................................................................................................................................................................... 91

Customer Change Notification Service ................................................................................................................................................ 91

Customer Support................................................................................................................................................................................ 91

Reader Response................................................................................................................................................................................ 92

Product Identification System .............................................................................................................................................................. 93

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-

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DS41239D-page 3

PIC10F200/202/204/206

NOTES:

DS41239D-page 4

PIC10F200/202/204/206

1.1

Applications

1.0

GENERAL DESCRIPTION

The PIC10F200/202/204/206 devices fit in applications

ranging from personal care appliances and security

systems to low-power remote transmitters/receivers.

The Flash technology makes customizing application

programs (transmitter codes, appliance settings,

receiver frequencies, etc.) extremely fast and conve-

nient. The small footprint packages, for through hole or

surface mounting, make these microcontrollers well

suited for applications with space limitations. Low cost,

low power, high performance, ease-of-use and I/O

flexibility make the PIC10F200/202/204/206 devices

very versatile even in areas where no microcontroller

use has been considered before (e.g., timer functions,

logic and PLDs in larger systems and coprocessor

applications).

The PIC10F200/202/204/206 devices from Microchip

Technology are low-cost, high-performance, 8-bit, fully-

static, Flash-based CMOS microcontrollers. They

employ a RISC architecture with only 33 single-word/

single-cycle instructions. All instructions are single

cycle (1 μs) except for program branches, which take

two cycles. The PIC10F200/202/204/206 devices

deliver performance in an order of magnitude higher

than their competitors in the same price category. The

12-bit wide instructions are highly symmetrical, result-

ing in a typical 2:1 code compression over other 8-bit

microcontrollers in its class. The easy-to-use and easy

to remember instruction set reduces development time

significantly.

The PIC10F200/202/204/206 products are equipped

with special features that reduce system cost and

power requirements. The Power-on Reset (POR) and

Device Reset Timer (DRT) eliminate the need for exter-

nal Reset circuitry. INTRC Internal Oscillator mode is

provided, thereby preserving the limited number of I/O

available. Power-Saving Sleep mode, Watchdog Timer

and code protection features improve system cost,

power and reliability.

The PIC10F200/202/204/206 devices are available in

cost-effective Flash, which is suitable for production in

any volume. The customer can take full advantage of

Microchip’s price leadership in Flash programmable

microcontrollers, while benefiting from the Flash

programmable flexibility.

The PIC10F200/202/204/206 products are supported

by a full-featured macro assembler, a software simula-

tor, an in-circuit debugger, a ‘C’ compiler, a low-cost

development programmer and a full featured program-

mer. All the tools are supported on IBM^®PC and

compatible machines.

TABLE 1-1:

PIC10F200/202/204/206 DEVICES

PIC10F200

PIC10F202

PIC10F204

PIC10F206

Clock

Maximum Frequency of Operation (MHz)

Flash Program Memory

4

Memory

256

512

256

512

Data Memory (bytes)

16

24

16

24

Peripherals Timer Module(s)

Wake-up from Sleep on Pin Change

TMR0

Yes

Comparators

0

1

Features

I/O Pins

3

Input-Only Pins

Internal Pull-ups

In-Circuit Serial Programming™

Number of Instructions

Packages

1

Yes

33

6-pin SOT-23

8-pin PDIP, DFN 8-pin PDIP, DFN 8-pin PDIP, DFN 8-pin PDIP, DFN

The PIC10F200/202/204/206 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current

capability and precision internal oscillator.

The PIC10F200/202/204/206 device uses serial programming with data pin GP0 and clock pin GP1.

DS41239D-page 5

PIC10F200/202/204/206

NOTES:

DS41239D-page 6

PIC10F200/202/204/206

2.2

Serialized Quick Turn

Programming^SM(SQTP^SM) Devices

2.0

PIC10F200/202/204/206 DEVICE

VARIETIES

Microchip offers a unique programming service, where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

A variety of packaging options are available. Depend-

ing on application and production requirements, the

proper device option can be selected using the

information in this section. When placing orders, please

use the PIC10F200/202/204/206 Product Identification

System at the back of this data sheet to specify the

correct part number.

Serial programming allows each device to have a

unique number, which can serve as an entry code,

password or ID number.

2.1

Quick Turn Programming (QTP)

Devices

Microchip offers a QTP programming service for

factory production orders. This service is made

available for users who choose not to program

medium-to-high quantity units and whose code

patterns have stabilized. The devices are identical to

the Flash devices but with all Flash locations and fuse

options already programmed by the factory. Certain

code and prototype verification procedures do apply

before production shipments are available. Please

contact your local Microchip Technology sales office for

more details.

DS41239D-page 7

PIC10F200/202/204/206

NOTES:

DS41239D-page 8

PIC10F200/202/204/206

The PIC10F200/202/204/206 devices contain an 8-bit

ALU and working register. The ALU is a general

purpose arithmetic unit. It performs arithmetic and

Boolean functions between data in the working register

and any register file.

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC10F200/202/204/206

devices can be attributed to a number of architectural

features commonly found in RISC microprocessors. To

begin with, the PIC10F200/202/204/206 devices use a

Harvard architecture in which program and data are

accessed on separate buses. This improves band-

width over traditional von Neumann architectures

where program and data are fetched on the same bus.

Separating program and data memory further allows

instructions to be sized differently than the 8-bit wide

data word. Instruction opcodes are 12 bits wide,

making it possible to have all single-word instructions.

A 12-bit wide program memory access bus fetches a

12-bit instruction in a single cycle. A two-stage pipeline

overlaps fetch and execution of instructions.

Consequently, all instructions (33) execute in a single

cycle (1 μs @ 4 MHz) except for program branches.

The ALU is 8 bits wide and capable of addition, subtrac-

tion, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two’s comple-

ment in nature. In two-operand instructions, one oper-

and is typically the W (working) register. The other

operand is either a file register or an immediate con-

stant. In single operand instructions, the operand is

either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC) and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

The table below lists program memory (Flash) and data

memory (RAM) for the PIC10F200/202/204/206

devices.

A simplified block diagram is shown in Figure 3-1 and

Figure 3-2, with the corresponding device pins

described in Table 3-2.

TABLE 3-1:

Device

PIC10F2XX MEMORY

Memory

Program

Data

PIC10F200

PIC10F202

PIC10F204

PIC10F206

256 x 12

512 x 12

256 x 12

512 x 12

16 x 8

24 x 8

16 x 8

24 x 8

The PIC10F200/202/204/206 devices can directly or

indirectly address its register files and data memory. All

Special Function Registers (SFR), including the PC,

are mapped in the data memory. The PIC10F200/202/

204/206 devices have

a

highly orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation, on any register, using any

addressing mode. This symmetrical nature and lack of

“special optimal situations” make programming with the

PIC10F200/202/204/206 devices simple, yet efficient.

In addition, the learning curve is reduced significantly.

DS41239D-page 9

PIC10F200/202/204/206

FIGURE 3-1:

PIC10F200/202 BLOCK DIAGRAM

9-10

8

GPIO

Data Bus

Program Counter

Flash

512 x12 or

256 x12

Program

Memory

GP0/ICSPDAT

GP1/ICSPCLK

GP2/T0CKI/FOSC4

RAM

24 or 16

bytes

Stack 1

Stack 2

GP3/MCLR/VPP

File

Registers

Program

Bus

12

RAM Addr

9

Addr MUX

Instruction Reg

Indirect

Addr

5

Direct Addr

5-7

FSR Reg

STATUS Reg

8

3

MUX

Device Reset

Timer

Instruction

Decode &

Control

Power-on

Reset

ALU

8

Watchdog

Timer

Timing

Generation

W Reg

Internal RC

Clock

Timer0

MCLR

VDD, VSS

DS41239D-page 10

PIC10F200/202/204/206

FIGURE 3-2:

PIC10F204/206 BLOCK DIAGRAM

9-10

8

GPIO

Data Bus

Program Counter

Flash

512 x12 or

256 x12

Program

Memory

GP0/ICSPDAT/CIN+

GP1/ICSPCLK/CIN-

GP2/T0CKI/COUT/FOSC4

GP3/MCLR/VPP

RAM

24 or 16

bytes

Stack 1

Stack 2

File

Registers

Program

Bus

12

RAM Addr

9

Addr MUX

Instruction Reg

Indirect

Addr

5

Direct Addr

5-7

FSR Reg

STATUS Reg

8

3

MUX

Device Reset

Timer

Instruction

Decode &

Control

Power-on

Reset

ALU

8

Watchdog

Timer

Timing

Generation

W Reg

Internal RC

Clock

CIN+

CIN-

Timer0

Comparator

MCLR

VDD, VSS

COUT

DS41239D-page 11

PIC10F200/202/204/206

TABLE 3-2:

Name

PIC10F200/202/204/206 PINOUT DESCRIPTION

Input Output

Function

Description

Type

GP0/ICSPDAT/CIN+

GP1/ICSPCLK/CIN-

GP0

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.

CMOS In-Circuit Serial Programming^™data pin.

ICSPDAT

CIN+

ST

AN

—

Comparator input (PIC10F204/206 only).

GP1

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.

ICSPCLK

CIN-

ST

AN

TTL

ST

—

CMOS In-Circuit Serial Programming clock pin.

—

Comparator input (PIC10F204/206 only).

CMOS Bidirectional I/O pin.

Clock input to TMR0.

GP2/T0CKI/COUT/

FOSC4

GP2

T0CKI

COUT

FOSC4

GP3

—

CMOS Comparator output (PIC10F204/206 only).

CMOS Oscillator/4 output.

—

GP3/MCLR/VPP

TTL

—

Input pin. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

MCLR

ST

—

Master Clear (Reset). When configured as MCLR, this pin is

an active-low Reset to the device. Voltage on GP3/MCLR/VPP

must not exceed VDD during normal device operation or the

device will enter Programming mode. Weak pull-up always on

if configured as MCLR.

VPP

VDD

VSS

HV

P

—

Programming voltage input.

VDD

VSS

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

P

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input, AN = Analog input

DS41239D-page 12

PIC10F200/202/204/206

3.1

Clocking Scheme/Instruction

Cycle

3.2

Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the PC to change (e.g., GOTO), then two cycles

are required to complete the instruction (Example 3-1).

The clock is internally divided by four to generate four

non-overlapping quadrature clocks, namely Q1, Q2,

Q3 and Q4. Internally, the PC is incremented every Q1

and the instruction is fetched from program memory

and latched into the instruction register in Q4. It is

decoded and executed during the following Q1 through

Q4. The clocks and instruction execution flow is shown

in Figure 3-3 and Example 3-1.

A fetch cycle begins with the PC incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-3:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

PC

Internal

phase

clock

PC

PC + 1

PC + 2

Fetch INST (PC)

Execute INST (PC – 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF GPIO

3. CALL SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

GPIO, BIT1

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

DS41239D-page 13

PIC10F200/202/204/206

NOTES:

DS41239D-page 14

PIC10F200/202/204/206

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC10F200/204

4.0

MEMORY ORGANIZATION

The PIC10F200/202/204/206 memories are organized

into program memory and data memory. Data memory

banks are accessed using the File Select Register

(FSR).

PC<7:0>

9

CALL, RETLW

Stack Level 1

Stack Level 2

4.1

Program Memory Organization for

the PIC10F200/204

The PIC10F200/204 devices have a 9-bit Program

Counter (PC) capable of addressing a 512 x 12

program memory space.

(1)

Reset Vector

0000h

Only the first 256 x 12 (0000h-00FFh) for the

PIC10F200/204 are physically implemented (see

On-chip Program

Memory

Figure 4-1). Accessing

a location above these

boundaries will cause a wraparound within the first

256 x 12 space (PIC10F200/204). The effective

Reset vector is at 0000h (see Figure 4-1). Location

00FFh (PIC10F200/204) contains the internal clock

oscillator calibration value. This value should never

be overwritten.

256 Word

00FFh

0100h

01FFh

Note 1: Address 0000h becomes the

effective Reset vector. Location

00FFh contains the MOVLW XX

internal oscillator calibration value.

DS41239D-page 15

PIC10F200/202/204/206

4.2

Program Memory Organization for

the PIC10F202/206

4.3

Data Memory Organization

Data memory is composed of registers or bytes of

RAM. Therefore, data memory for a device is specified

by its register file. The register file is divided into two

functional groups: Special Function Registers (SFR)

and General Purpose Registers (GPR).

The PIC10F202/206 devices have a 10-bit Program

Counter (PC) capable of addressing a 1024 x 12

program memory space.

Only the first 512 x 12 (0000h-01FFh) for the

PIC10F202/206 are physically implemented (see

Figure 4-2). Accessing

boundaries will cause a wraparound within the first

512 x 12 space (PIC10F202/206). The effective

Reset vector is at 0000h (see Figure 4-2). Location

01FFh (PIC10F202/206) contains the internal clock

oscillator calibration value. This value should never

be overwritten.

The Special Function Registers include the TMR0 reg-

ister, the Program Counter (PCL), the STATUS register,

the I/O register (GPIO) and the File Select Register

(FSR). In addition, Special Function Registers are used

to control the I/O port configuration and prescaler

options.

a location above these

The General Purpose registers are used for data and

control information under command of the instructions.

For the PIC10F200/204, the register file is composed of

7 Special Function registers and 16 General Purpose

registers (see Figure 4-3 and Figure 4-4).

FIGURE 4-2:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC10F202/206

For the PIC10F202/206, the register file is composed of

8 Special Function registers and 24 General Purpose

registers (see Figure 4-4).

PC<8:0>

10

CALL, RETLW

Stack Level 1

Stack Level 2

4.3.1

GENERAL PURPOSE REGISTER

FILE

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 4.9 “Indirect Data Addressing:

INDF and FSR Registers”.

(1)

Reset Vector

0000h

On-chip Program

Memory

512 Words

01FFh

0200h

02FFh

Note 1: Address 0000h becomes the

effective Reset vector. Location

01FFh contains the MOVLW XX

internal oscillator calibration value.

DS41239D-page 16

PIC10F200/202/204/206

FIGURE 4-3:

PIC10F200/204 REGISTER

FILE MAP

FIGURE 4-4:

PIC10F202/206 REGISTER

FILE MAP

File Address

(1)

INDF

00h

01h

02h

03h

04h

05h

06h

07h

08h

INDF

00h

01h

02h

03h

04h

05h

06h

07h

08h

TMR0

PCL

TMR0

PCL

STATUS

FSR

STATUS

FSR

OSCCAL

GPIO

OSCCAL

GPIO

(2)

CMCON0

(3)

Unimplemented

General

Purpose

Registers

0Fh

10h

General

Purpose

Registers

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and

FSR Registers”.

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and

FSR Registers”.

2: PIC10F206 only. Unimplemented on the

2: PIC10F204 only. Unimplemented on the

PIC10F202 and reads as 00h.

PIC10F200 and reads as 00h.

3: Unimplemented, read as 00h.

DS41239D-page 17

PIC10F200/202/204/206

4.3.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the

operation of the device (Table 4-1).

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

TABLE 4-1:

SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC10F200/202/204/206)

Value on

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Power-On Page #

Reset

(2)

00h

01h

INDF

Uses Contents of FSR to Address Data Memory (not a physical register)

8-bit Real-Time Clock/Counter

xxxx xxxx

23

TMR0

PCL

xxxx xxxx 29, 33

(1)

02h

Low-order 8 bits of PC

1111 1111

22

19

23

21

25

34

37

20

(5)

(3)

03h

04h

05h

06h

STATUS

FSR

GPWUF CWUF

—

TO

PD

Z

DC

C

00-1 1xxx

111x xxxx

Indirect Data Memory Address Pointer

OSCCAL

GPIO

CAL6

—

CAL5

—

CAL4

—

CAL3

—

CAL2

GP3

CAL1

GP2

CAL0 FOSC4 1111 1110

GP1 GP0 ---- xxxx

(4)

07h

CMCON0 CMPOUT COUTEN

POL

—

CMPT0CS CMPON CNREF CPREF CWU 1111 1111

N/A

TRISGPIO

OPTION

—

I/O Control Register

PSA PS2

---- 1111

1111 1111

N/A

GPWU

GPPU

T0CS

T0SE

PS1

PS0

Legend:

– = unimplemented, read as ‘0’, x= unknown, u= unchanged, q= value depends on condition.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter” for an

explanation of how to access these bits.

2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin change

Reset.

3: See Table 9-1 for other Reset specific values.

4: PIC10F204/206 only.

5: PIC10F204/206 only. On all other devices, this bit is reserved and should not be used.

DS41239D-page 18

PIC10F200/202/204/206

For example, CLRF STATUS, will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

4.4

STATUS Register

This register contains the arithmetic status of the ALU,

the Reset status and the page preselect bit.

Therefore, it is recommended that only BCF, BSF and

MOVWFinstructions be used to alter the STATUS regis-

ter. These instructions do not affect the Z, DC or C bits

from the STATUS register. For other instructions which

do affect Status bits, see Section 10.0 “Instruction

Set Summary”.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

REGISTER 4-1:

STATUS REGISTER

R/W-0

GPWUF

bit 7

R/W-0

CWUF⁽¹⁾

R/W-0

—

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

GPWUF: GPIO Reset bit

1= Reset due to wake-up from Sleep on pin change

0= After power-up or other Reset

CWUF: Comparator Wake-up on Change Flag bit⁽¹⁾

1= Reset due to wake-up from Sleep on comparator change

0= After power-up or other Reset conditions.

bit 5

bit 4

Reserved: Do not use. Use of this bit may affect upward compatibility with future products.

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

bit 3

bit 2

bit 1

PD: Power-Down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (for ADDWFand SUBWFinstructions)

ADDWF:

1= A carry from the 4th low-order bit of the result occurred

0= A carry from the 4th low-order bit of the result did not occur

SUBWF:

1= A borrow from the 4th low-order bit of the result did not occur

0= A borrow from the 4th low-order bit of the result occurred

bit 0

C: Carry/Borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)

ADDWF:

SUBWF:

RRFor RLF:

1= A carry occurred

1= A borrow did not occur Load bit with LSb or MSb, respectively

0= A carry did not occur 0= A borrow occurred

Note 1: This bit is used on the PIC10F204/206. For code compatibility do not use this bit on the PIC10F200/202.

DS41239D-page 19

PIC10F200/202/204/206

4.5

OPTION Register

Note:

If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled

for that pin (i.e., note that TRIS overrides

Option control of GPPU and GPWU).

The OPTION register is a 8-bit wide, write-only register,

which contains various control bits to configure the

Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION regis-

ter. A Reset sets the OPTION<7:0> bits.

If the T0CS bit is set to ‘1’, it will override

the TRIS function on the T0CKI pin.

REGISTER 4-2:

OPTION REGISTER

W-1

GPPU

W-1

PSA

W-1

PS2

W-1

PS1

W-1

PS0

GPWU

bit 7

T0CS

T0SE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

GPWU: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)

1= Disabled

0= Enabled

GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)

1= Disabled

0= Enabled

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin (overrides TRIS on the T0CKI pin)

0= Transition on internal instruction cycle clock, FOSC/4

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on the T0CKI pin

0= Increment on low-to-high transition on the T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler assigned to the WDT

0= Prescaler assigned to Timer0

PS<2:0>: Prescaler Rate Select bits

Bit Value Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

.

DS41239D-page 20

PIC10F200/202/204/206

4.6

OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to

calibrate the internal precision 4 MHz oscillator. It

contains seven bits for calibration.

Note:

Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

After you move in the calibration constant, do not

change the value. See Section 9.2.2 “Internal 4 MHz

Oscillator”.

REGISTER 4-3:

OSCCAL REGISTER

R/W-1

CAL6

R/W-1

CAL5

R/W-1

CAL4

R/W-1

CAL3

R/W-1

CAL2

R/W-1

CAL1

R/W-1

CAL0

R/W-0

FOSC4

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

CAL<6:0>: Oscillator Calibration bits

0111111= Maximum frequency

•

0000001

0000000= Center frequency

1111111

•

1000000=Minimum frequency

bit 0

FOSC4: INTOSC/4 Output Enable bit⁽¹⁾

1= INTOSC/4 output onto GP2

0= GP2/T0CKI/COUT applied to GP2

Note 1: Overrides GP2/T0CKI/COUT control registers when enabled.

DS41239D-page 21

PIC10F200/202/204/206

4.7.1

EFFECTS OF RESET

4.7

Program Counter

The PC is set upon a Reset, which means that the PC

addresses the last location in program memory (i.e.,

the oscillator calibration instruction). After executing

MOVLW XX, the PC will roll over to location 0000h and

begin executing user code.

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

For a GOTOinstruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The Program Counter

Low (PCL) is mapped to PC<7:0>.

4.8

Stack

The PIC10F200/204 devices have a 2-deep, 8-bit wide

hardware PUSH/POP stack.

For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are pro-

vided by the instruction word. However, PC<8> does

not come from the instruction word, but is always

cleared (Figure 4-5).

The PIC10F202/206 devices have a 2-deep, 9-bit wide

hardware PUSH/POP stack.

A CALLinstruction will PUSH the current value of Stack 1

into Stack 2 and then PUSH the current PC value,

incremented by one, into Stack Level 1. If more than two

sequential CALLs are executed, only the most recent two

return addresses are stored.

Instructions where the PCL is the destination, or modify

PCL instructions, include MOVWF PC, ADDWF PCand

BSF PC,5.

Note:

Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction,

all subroutine calls or computed jumps are

limited to the first 256 locations of any

program memory page (512 words long).

A RETLW instruction will POP the contents of Stack

Level 1 into the PC and then copy Stack Level 2

contents into level 1. If more than two sequential

RETLWs are executed, the stack will be filled with the

address previously stored in Stack Level 2.

Note 1: The W register will be loaded with the lit-

eral value specified in the instruction. This

is particularly useful for the implementa-

tion of the data look-up tables within the

program memory.

FIGURE 4-5:

LOADING OF PC

BRANCH INSTRUCTIONS

GOTOInstruction

8 7

0

2: There are no Status bits to indicate stack

PC

PCL

overflows or stack underflow conditions.

3: There are no instruction mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL

and RETLWinstructions.

Instruction Word

CALLor Modify PCL Instruction

8 7

0

PC

PCL

Instruction Word

Reset to ‘0’

DS41239D-page 22

PIC10F200/202/204/206

EXAMPLE 4-1:

HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

4.9

Indirect Data Addressing: INDF

and FSR Registers

The INDF register is not a physical register. Addressing

INDF actually addresses the register whose address is

contained in the FSR register (FSR is a pointer). This is

indirect addressing.

MOVLW

MOVWF

0x10

;initialize pointer

;to RAM

FSR

INDF

;clear INDF

;register

INCF

BTFSC

GOTO

FSR,F

FSR,4

;all done?

;NO, clear next

4.10 Indirect Addressing

• Register file 09 contains the value 10h

• Register file 0A contains the value 0Ah

• Load the value 09 into the FSR register

CONTINUE

:

;YES, continue

• A read of the INDF register will return the value

of 10h

The FSR is a 5-bit wide register. It is used in conjunc-

tion with the INDF register to indirectly address the data

memory area.

• Increment the value of the FSR register by one

(FSR = 0A)

• A read of the INDR register now will return the

value of 0Ah.

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no operation (although Status bits may be affected).

Note:

PIC10F200/202/204/206 – Do not use

banking. FSR <7:5> are unimplemented

and read as ‘1’s.

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 4-1.

FIGURE 4-6:

DIRECT/INDIRECT ADDRESSING (PIC10F200/202/204/206)

Direct Addressing

(opcode) 0

Indirect Addressing

(FSR)

4

0

4

Location Select

00h

Data

Memory

0Fh

10h

(1)

1Fh

Bank 0

Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.

DS41239D-page 23

PIC10F200/202/204/206

NOTES:

DS41239D-page 24

PIC10F200/202/204/206

5.3

I/O Interfacing

5.0

I/O PORT

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All port pins, except GP3 which is input-

only, may be used for both input and output operations.

For input operations, these ports are non-latching. Any

input must be present until read by an input instruction

(e.g., MOVF GPIO, W). The outputs are latched and

remain unchanged until the output latch is rewritten. To

use a port pin as output, the corresponding direction

control bit in TRIS must be cleared (= 0). For use as an

input, the corresponding TRIS bit must be set. Any I/O

pin (except GP3) can be programmed individually as

input or output.

As with any other register, the I/O register(s) can be

written and read under program control. However, read

instructions (e.g., MOVF GPIO, W) always read the I/O

pins independent of the pin’s Input/Output modes. On

Reset, all I/O ports are defined as input (inputs are at

high-impedance) since the I/O control registers are all

set.

5.1

GPIO

GPIO is an 8-bit I/O register. Only the low-order 4 bits

are used (GP<3:0>). Bits 7 through 4 are unimple-

mented and read as ‘0’s. Please note that GP3 is an

input-only pin. Pins GP0, GP1 and GP3 can be config-

ured with weak pull-ups and also for wake-up on

change. The wake-up on change and weak pull-up

functions are not pin selectable. If GP3/MCLR is config-

ured as MCLR, weak pull-up is always on and wake-up

on change for this pin is not enabled.

FIGURE 5-1:

PIC10F200/202/204/206

EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Data

Bus

D

Q

Data

Latch

VDD

P

VDD

WR

Port

5.2

TRIS Registers

CK

The Output Driver Control register is loaded with the

contents of the W register by executing the TRIS

f

instruction. A ‘1’ from a TRIS register bit puts the corre-

sponding output driver in a High-Impedance mode. A

‘0’ puts the contents of the output data latch on the

selected pins, enabling the output buffer. The excep-

tions are GP3, which is input-only and the GP2/T0CKI/

COUT/FOSC4 pin, which may be controlled by various

registers. See Table 5-1.

N

I/O

W

Reg

D

Q

TRIS

Latch

VSS VSS

TRIS‘f’

CK

Note:

A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

Reset

(1)

RD Port

The TRIS registers are “write-only” and are set (output

drivers disabled) upon Reset.

Note 1: See Table 3-2 for buffer type.

TABLE 5-1:

ORDER OF PRECEDENCE

FOR PIN FUNCTIONS

Priority

GP0

CIN+

GP1

GP2

GP3

1

2

3

4

CIN-

FOSC4

COUT

I/MCLR

TRIS GPIO TRIS GPIO

—

T0CKI

TRIS GPIO

DS41239D-page 25

PIC10F200/202/204/206

TABLE 5-2:

SUMMARY OF PORT REGISTERS

Value on

Power-On

Reset

Value on

All Other Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

N/A

TRISGPIO

—

I/O Control Register

---- 1111

1111 1111

00-1 1xxx

---- xxxx

1111 1111

N/A

OPTION

STATUS

GPIO

GPWU

GPPU

T0CS

—

T0SE

TO

PSA

PD

PS2

Z

PS1

DC

PS0

C

(1), (2)

qq-q quuu

03h

GPWUF CWUF

06h

—

GP3

GP2

GP1

GP0

---- uuuu

Legend:

Shaded cells are not used by PORT registers, read as ‘0’, – = unimplemented, read as ‘0’, x= unknown, u=

unchanged,

q= depends on condition.

Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

2: If Reset was due to wake-up on comparator change, then bit 6 = 1. All other Resets will cause bit 6 = 0.

EXAMPLE 5-1:

READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

5.4

I/O Programming Considerations

5.4.1

BIDIRECTIONAL I/O PORTS

;Initial GPIO Settings

;GPIO<3:2> Inputs

;GPIO<1:0> Outputs

;

Some instructions operate internally as read followed

by write operations. The BCFand BSFinstructions, for

example, read the entire port into the CPU, execute the

bit operation and rewrite the result. Caution must be

used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

example, a BSFoperation on bit 2 of GPIO will cause

all eight bits of GPIO to be read into the CPU, bit 2 to

be set and the GPIO value to be written to the output

latches. If another bit of GPIO is used as a bidirectional

I/O pin (say bit 0), and it is defined as an input at this

time, the input signal present on the pin itself would be

read into the CPU and rewritten to the data latch of this

particular pin, overwriting the previous content. As long

as the pin stays in the Input mode, no problem occurs.

However, if bit 0 is switched into Output mode later on,

the content of the data latch may now be unknown.

;

GPIO latch

GPIO pins

----------

---- pp11

----------

GPIO, 1 ;---- pp01

GPIO, 0 ;---- pp10

BCF

MOVLW 007h;

TRIS GPIO

;---- pp10

---- pp11

;

Note 1: The user may have expected the pin val-

ues to be ---- pp00. The 2nd BCFcaused

GP1 to be latched as the pin value (High).

5.4.2

SUCCESSIVE OPERATIONS ON

I/O PORTS

Example 5-1 shows the effect of two sequential

Read-Modify-Write instructions (e.g., BCF, BSF, etc.)

on an I/O port.

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle (Figure 5-2).

Therefore, care must be exercised if a write followed by

a read operation is carried out on the same I/O port. The

sequence of instructions should allow the pin voltage to

stabilize (load dependent) before the next instruction

causes that file to be read into the CPU. Otherwise, the

previous state of that pin may be read into the CPU rather

than the new state. When in doubt, it is better to separate

these instructions with a NOP or another instruction not

accessing this I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired OR”, “wired

AND”). The resulting high output currents may damage

the chip.

DS41239D-page 26

PIC10F200/202/204/206

FIGURE 5-2:

SUCCESSIVE I/O OPERATION (PIC10F200/202/204/206)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC + 3

PC

PC + 1

PC + 2

This example shows a write to GPIO followed

by a read from GPIO.

Instruction

Fetched

MOVWF GPIO

MOVF GPIO, W

NOP

Data setup time = (0.25 TCY – TPD)

where: TCY = instruction cycle

TPD = propagation delay

GP<2:0>

Port pin

written here

Port pin

sampled here

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

Instruction

Executed

MOVWF GPIO

(Write to GPIO)

MOVF GPIO,W

(Read GPIO)

NOP

DS41239D-page 27

PIC10F200/202/204/206

NOTES:

DS41239D-page 28

PIC10F200/202/204/206

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

T0SE bit (OPTION<4>) determines the source edge.

Clearing the T0SE bit selects the rising edge. Restric-

tions on the external clock input are discussed in detail

in Section 6.1 “Using Timer0 with an External Clock

(PIC10F200/202)”.

6.0

TIMER0 MODULE AND TMR0

REGISTER (PIC10F200/202)

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit, PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4, 1:256

are selectable. Section 6.2 “Prescaler” details the

operation of the prescaler.

Figure 6-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-2 and Figure 6-3).

The user can work around this by writing an adjusted

value to the TMR0 register.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1:

TIMER0 BLOCK DIAGRAM

Data Bus

GP2/T0CKI

FOSC/4

0

1

PSOUT

8

1

0

Sync with

Internal

Clocks

TMR0 Reg

Programmable

PSOUT

Sync

(2)

Prescaler

(1)

(2 TCY delay)

T0SE

3

(1)

PS2, PS1, PS0

PSA

(1)

T0CS

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

FIGURE 6-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6

Instruction

Fetch

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

NT0 + 1

T0

T0 + 1

T0 + 2

NT0

NT0 + 2

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

DS41239D-page 29

PIC10F200/202/204/206

FIGURE 6-3:

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Instruction

Fetch

T0

T0 + 1

NT0

NT0 + 1

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-On

Reset

Value on

All Other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

N/A

TMR0

Timer0 – 8-bit Real-Time Clock/Counter

GPWU GPPU T0CS T0SE PSA

xxxx xxxx

1111 1111

---- 1111

uuuu uuuu

1111 1111

---- 1111

OPTION

TRISGPIO

PS2

PS1

PS0

(1)

—

I/O Control Register

—

Legend: Shaded cells not used by Timer0. – = unimplemented, x = unknown, u= unchanged.

Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.

6.1.1

EXTERNAL CLOCK

SYNCHRONIZATION

6.1

Using Timer0 with an External

Clock (PIC10F200/202)

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-4).

Therefore, it is necessary for T0CKI to be high for at

least 2 TOSC (and a small RC delay of 2 Tt0H) and low

for at least 2 TOSC (and a small RC delay of 2 Tt0H).

Refer to the electrical specification of the desired

device.

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock require-

ment is due to internal phase clock (TOSC) synchroniza-

tion. Also, there is a delay in the actual incrementing of

Timer0 after synchronization.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler, so that the prescaler output is symmetrical.

For the external clock to meet the sampling require-

ment, the ripple counter must be taken into account.

Therefore, it is necessary for T0CKI to have a period of

at least 4 TOSC (and a small RC delay of 4 Tt0H) divided

by the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the

minimum pulse width requirement of Tt0H. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device.

DS41239D-page 30

PIC10F200/202/204/206

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-4 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 6-4:

TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

misses sampling

External Clock Input or

(2)

Prescaler Output

(1)

External Clock/Prescaler

Output After Sampling

(3)

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

6.2.1

SWITCHING PRESCALER

ASSIGNMENT

6.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Section 9.6 “Watch-

dog Timer (WDT)”). For simplicity, this counter is

being referred to as “prescaler” throughout this data

sheet.

The prescaler assignment is fully under software

control (i.e., it can be changed “on-the-fly” during pro-

gram execution). To avoid an unintended device Reset,

the following instruction sequence (Example 6-1) must

be executed when changing the prescaler assignment

from Timer0 to the WDT.

Note:

The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice versa.

EXAMPLE 6-1:

CHANGING PRESCALER

(TIMER0 → WDT)

CLRWDT

CLRF

;Clear WDT

TMR0

;Clear TMR0 & Prescaler

MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7)

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

OPTION

;are required only if

;desired

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x, etc.) will clear the prescaler. When assigned

to WDT, a CLRWDT instruction will clear the prescaler

along with the WDT. The prescaler is neither readable

nor writable. On a Reset, the prescaler contains all ‘0’s.

CLRWDT

;PS<2:0> are 000 or 001

MOVLW ‘00xx1xxx’b;Set Postscaler to

OPTION ;desired WDT rate

DS41239D-page 31

PIC10F200/202/204/206

To change the prescaler from the WDT to the Timer0

module, use the sequence shown in Example 6-2. This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before

switching the prescaler.

EXAMPLE 6-2:

CHANGING PRESCALER

(WDT→TIMER0)

;Clear WDT and

;prescaler

CLRWDT

MOVLW ‘xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

OPTION

FIGURE 6-5:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY (= FOSC/4)

Data Bus

0

1

8

(2)

GP2/T0CKI

M

U

X

1

0

M

U

X

Sync

2

Cycles

TMR0 Reg

(1)

T0SE

T0CS

(1)

PSA

0

1

8-bit Prescaler

M

U

X

8

Watchdog

Timer

(1)

8-to-1 MUX

PS<2:0>

(1)

PSA

1

0

WDT Enable bit

(1)

MUX

PSA

WDT

Time-out

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

2: T0CKI is shared with pin GP2 on the PIC10F200/202/204/206.

DS41239D-page 32

PIC10F200/202/204/206

The second Counter mode uses the output of the com-

parator to increment Timer0. It can be entered in two

different ways. The first way is selected by setting the

T0CS bit (OPTION<5>) and clearing the CMPT0CS bit

(CMCON<4>); (COUTEN [CMCON<6>]) does not

affect this mode of operation. This enables an internal

connection between the comparator and the Timer0.

7.0

TIMER0 MODULE AND TMR0

REGISTER (PIC10F204/206)

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

The second way is selected by setting the T0CS bit

(OPTION<5>),

setting

the

CMPT0CS

bit

(CMCON0<4>) and clearing the COUTEN bit

(CMCON0<6>). This allows the output of the compara-

tor onto the T0CKI pin, while keeping the T0CKI input

active. Therefore, any comparator change on the

COUT pin is fed back into the T0CKI input. The T0SE

bit (OPTION<4>) determines the source edge. Clear-

ing the T0SE bit selects the rising edge. Restrictions on

the external clock input as discussed in Section 7.1

“Using Timer0 with an External Clock (PIC10F204/

206)”

- External clock from either the T0CKI pin or

from the output of the comparator

Figure 7-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 7-2 and Figure 7-3).

The user can work around this by writing an adjusted

value to the TMR0 register.

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit, PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4,...,

1:256 are selectable. Section 7.2 “Prescaler” details

the operation of the prescaler.

There are two types of Counter mode. The first Counter

mode uses the T0CKI pin to increment Timer0. It is

selected by setting the T0CS bit (OPTION<5>), setting

the CMPT0CS bit (CMCON0<4>) and setting the

COUTEN bit (CMCON0<6>). In this mode, Timer0 will

increment either on every rising or falling edge of pin

T0CKI. The T0SE bit (OPTION<4>) determines the

source edge. Clearing the T0SE bit selects the rising

edge. Restrictions on the external clock input are

discussed in detail in Section 7.1 “Using Timer0 with

an External Clock (PIC10F204/206)”.

A summary of registers associated with the Timer0

module is found in Table 7-1.

FIGURE 7-1:

TIMER0 BLOCK DIAGRAM (PIC10F204/206)

T0CKI

Data Bus

FOSC/4

0

1

PSOUT

8

1

0

1

0

Internal

Comparator

Output

Sync with

Internal

Clocks

TMR0 Reg

Programmable

PSOUT

Sync

(2)

Prescaler

(1)

(2 TCY delay)

T0SE

3

(3)

(1)

CMPT0CS

PS2, PS1, PS0

PSA

(1)

T0CS

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 7-5).

3: Bit CMPT0CS is located in the CMCON0 register, CMCON0<4>.

DS41239D-page 33

PIC10F200/202/204/206

FIGURE 7-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC+5 PC + 6

Instruction

Fetch

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

NT0 + 1

T0

T0 + 1

T0 + 2

NT0

NT0 + 2

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

FIGURE 7-3:

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Instruction

Fetch

T0

T0 + 1

NT0

NT0 + 1

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

TABLE 7-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-On

Reset

Value on

All Other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

TMR0

Timer0 – 8-bit Real-Time Clock/Counter

xxxx xxxx uuuu uuuu

07h

CMCON0

OPTION

CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 uuuu uuuu

N/A

GPWU

—

GPPU

—

T0CS

—

T0SE

—

PSA

PS2

PS1

PS0

1111 1111 1111 1111

---- 1111 ---- 1111

(1)

N/A

TRISGPIO

I/O Control Register

Legend:

Shaded cells not used by Timer0. – = unimplemented, x = unknown, u= unchanged.

Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.

small RC delay of 2 Tt0H) and low for at least 2 TOSC

(and a small RC delay of 2 Tt0H). Refer to the electrical

specification of the desired device.

7.1

Using Timer0 with an External

Clock (PIC10F204/206)

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock require-

ment is due to internal phase clock (TOSC) synchroniza-

tion. Also, there is a delay in the actual incrementing of

Timer0 after synchronization.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter type

prescaler, so that the prescaler output is symmetrical.

For the external clock to meet the sampling require-

ment, the ripple counter must be taken into account.

Therefore, it is necessary for T0CKI or the comparator

output to have a period of at least 4 TOSC (and a small

RC delay of 4 Tt0H) divided by the prescaler value. The

only requirement on T0CKI or the comparator output

high and low time is that they do not violate the

minimum pulse width requirement of Tt0H. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device.

7.1.1

EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of an external clock with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 7-4). Therefore, it is necessary for T0CKI or the

comparator output to be high for at least 2 TOSC (and a

DS41239D-page 34

PIC10F200/202/204/206

7.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 7-4 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 7-4:

TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

misses sampling

External Clock Input or

(2)

Prescaler Output

(1)

External Clock/Prescaler

Output After Sampling

(3)

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

7.2.1

SWITCHING PRESCALER

ASSIGNMENT

7.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Figure 9-6). For

simplicity, this counter is being referred to as

“prescaler” throughout this data sheet.

The prescaler assignment is fully under software

control (i.e., it can be changed “on-the-fly” during pro-

gram execution). To avoid an unintended device Reset,

the following instruction sequence (Example 7-1) must

be executed when changing the prescaler assignment

from Timer0 to the WDT.

Note:

The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice versa.

EXAMPLE 7-1:

CHANGING PRESCALER

(TIMER0 → WDT)

CLRWDT

;Clear WDT

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

CLRF

TMR0

;Clear TMR0 & Prescaler

MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7)

OPTION

;are required only if

;desired

;PS<2:0> are 000 or 001

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x, etc.) will clear the prescaler. When assigned

to WDT, a CLRWDT instruction will clear the prescaler

along with the WDT. The prescaler is neither readable

nor writable. On a Reset, the prescaler contains all ‘0’s.

CLRWDT

MOVLW ‘00xx1xxx’b;Set Postscaler to

OPTION ;desired WDT rate

To change the prescaler from the WDT to the Timer0

module, use the sequence shown in Example 7.2. This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before

switching the prescaler.

DS41239D-page 35

PIC10F200/202/204/206

EXAMPLE 7-2:

CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT

;Clear WDT and

;prescaler

MOVLW ‘xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

OPTION

FIGURE 7-5:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

(2)

GP2/T0CKI

TCY (= FOSC/4)

Data Bus

8

0

1

M

U

X

1

0

1

0

M

U

X

Comparator

Output

Sync

2

Cycles

TMR0 Reg

(1)

T0SE

T0CS

(1)

PSA

(3)

CMPT0CS

0

1

8-bit Prescaler

M

U

X

8

Watchdog

Timer

(1)

8-to-1 MUX

PS<2:0>

(1)

PSA

1

0

WDT Enable bit

(1)

MUX

PSA

WDT

Time-out

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

2: T0CKI is shared with pin GP2.

3: Bit CMPT0CS is located in the CMCON0 register.

DS41239D-page 36

PIC10F200/202/204/206

8.0

COMPARATOR MODULE

The comparator module contains one Analog

comparator. The inputs to the comparator are

multiplexed with GP0 and GP1 pins. The output of the

comparator can be placed on GP2.

The CMCON0 register, shown in Register 8-1, controls

the comparator operation. A block diagram of the

comparator is shown in Figure 8-1.

REGISTER 8-1:

CMCON0 REGISTER

R-1

CMPOUT

bit 7

R/W-1

COUTEN

R/W-1

POL

R/W-1

CWU

CMPT0CS

CMPON

CNREF

CPREF

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

CMPOUT: Comparator Output bit

1= VIN+ > VIN-

0= VIN+ < VIN-

COUTEN: Comparator Output Enable bit^{(1, 2)}

1= Output of comparator is NOT placed on the COUT pin

0= Output of comparator is placed in the COUT pin

POL: Comparator Output Polarity bit⁽²⁾

1= Output of comparator not inverted

0= Output of comparator inverted

CMPT0CS: Comparator TMR0 Clock Source bit⁽²⁾

1= TMR0 clock source selected by T0CS control bit

0= Comparator output used as TMR0 clock source

CMPON: Comparator Enable bit

1= Comparator is on

0= Comparator is off

CNREF: Comparator Negative Reference Select bit⁽²⁾

1= CIN- pin⁽³⁾

0= Internal voltage reference

CPREF: Comparator Positive Reference Select bit⁽²⁾

1= CIN+ pin⁽³⁾

0= CIN- pin⁽³⁾

CWU: Comparator Wake-up on Change Enable bit⁽²⁾

1= Wake-up on comparator change is disabled

0= Wake-up on comparator change is enabled.

Note 1: Overrides T0CS bit for TRIS control of GP2.

2: When the comparator is turned on, these control bits assert themselves. When the comparator is off, these

bits have no effect on the device operation and the other control registers have precedence.

3: PIC10F204/206 only.

DS41239D-page 37

PIC10F200/202/204/206

8.1

Comparator Configuration

Note:

The comparator can have an inverted

output (see Figure 8-1).

The on-board comparator inputs, (GP0/CIN+, GP1/

CIN-), as well as the comparator output (GP2/COUT),

are steerable. The CMCON0, OPTION and TRIS

registers are used to steer these pins (see Figure 8-1).

If the Comparator mode is changed, the comparator

output level may not be valid for the specified mode

change delay shown in Table 12-1.

FIGURE 8-1:

BLOCK DIAGRAM OF THE COMPARATOR

T0CKI/GP2/COUT

COUTEN

CPREF

C+

+

C-

COUT(Register)

OSCCAL

Band Gap Buffer

-

(0.6V)

CNREF

POL

CMPON

T0CKI

T0CKI Pin

T0CKSEL

CWU

Q

D

S

Read

CWUF

CMCON

TABLE 8-1:

TMR0 CLOCK SOURCE

FUNCTION MUXING

T0CS CMPT0CS COUTEN

Source

0

x

Internal Instruction

Cycle

1

0

1

0

1

0

1

CMPOUT

T0CKI

DS41239D-page 38

PIC10F200/202/204/206

8.2

Comparator Operation

8.5

Comparator Output

A single comparator is shown in Figure 8-2 along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input VIN-, the output of the comparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 8-2 represent

the uncertainty due to input offsets and response time.

See Table 12-1 for Common Mode Voltage.

The comparator output is read through CMCON0

register. This bit is read-only. The comparator output

may also be used internally, see Figure 8-1.

Note:

Analog levels on any pin that is defined as

a digital input may cause the input buffer to

consume more current than is specified.

8.6

Comparator Wake-up Flag

The comparator wake-up flag is set whenever all of the

following conditions are met:

FIGURE 8-2:

SINGLE COMPARATOR

• CWU = 0 (CMCON0<0>)

• CMCON0 has been read to latch the last known

state of the CMPOUT bit (MOVF CMCON0, W)

Vin+

Vin-

+

Result

–

• Device is in Sleep

• The output of the comparator has changed state

The wake-up flag may be cleared in software or by

another device Reset.

VIN-

8.7

Comparator Operation During

Sleep

VIN+

When the comparator is active and the device is placed

in Sleep mode, the comparator remains active. While

the comparator is powered-up, higher Sleep currents

than shown in the power-down current specification will

occur. To minimize power consumption while in Sleep

mode, turn off the comparator before entering Sleep.

Result

8.3

Comparator Reference

8.8

Effects of a Reset

An internal reference signal may be used depending on

the comparator operating mode. The analog signal that

is present at VIN- is compared to the signal at VIN+ and

the digital output of the comparator is adjusted

accordingly (Figure 8-2). Please see Table 12-1 for

internal reference specifications.

A Power-on Reset (POR) forces the CMCON0 register

to its Reset state. This forces the Comparator module

to be in the comparator Reset mode. This ensures that

all potential inputs are analog inputs. Device current is

minimized when analog inputs are present at Reset

time. The comparator will be powered-down during the

Reset interval.

8.4

Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is to have a valid level. If the com-

parator inputs are changed, a delay must be used to

allow the comparator to settle to its new state. Please

see Table 12-1 for comparator response time

specifications.

8.9

Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 8-3. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

maximum

source

impedance

of

10 kΩ

is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

DS41239D-page 39

PIC10F200/202/204/206

FIGURE 8-3:

ANALOG INPUT MODE

VDD

VT = 0.6V

RIC

RS < 10 kΩ

AIN

ILEAKAGE

±500 nA

CPIN

5 pF

VA

VT = 0.6V

VSS

Legend: CPIN

VT

= Input Capacitance

= Threshold Voltage

ILEAKAGE = Leakage Current at the Pin

RIC

RS

VA

= Interconnect Resistance

= Source Impedance

= Analog Voltage

TABLE 8-2:

REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Value on

All Other

Resets

Value on

POR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

03h

07h

N/A

STATUS

GPWUF

CWUF

—

TO

PD

Z

DC

C

00-1 1xxx qq0q quuu

CMCON0 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 uuuu uuuu

TRISGPIO I/O Control Register ---- 1111 ---- 1111

—

Legend: x= Unknown, u= Unchanged, – = Unimplemented, read as ‘0’, q= Depends on condition.

DS41239D-page 40

PIC10F200/202/204/206

The PIC10F200/202/204/206 devices have a Watch-

dog Timer, which can be shut off only through Configu-

ration bit WDTE. It runs off of its own RC oscillator for

added reliability. When using INTRC, there is an 18 ms

delay only on VDD power-up. With this timer on-chip,

most applications need no external Reset circuitry.

9.0

SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors are special circuits that deal with the needs of real-

time applications. The PIC10F200/202/204/206

microcontrollers have a host of such features intended

to maximize system reliability, minimize cost through

elimination of external components, provide power-

saving operating modes and offer code protection.

These features are:

The Sleep mode is designed to offer a very low-current

Power-Down mode. The user can wake-up from Sleep

through a change on input pins, wake-up from

comparator change, or through a Watchdog Timer

time-out.

• Reset:

9.1

Configuration Bits

- Power-on Reset (POR)

- Device Reset Timer (DRT)

- Watchdog Timer (WDT)

- Wake-up from Sleep on pin change

- Wake-up from Sleep on comparator change

• Sleep

The PIC10F200/202/204/206 Configuration Words

consist of 12 bits. Configuration bits can be pro-

grammed to select various device configurations. One

bit is the Watchdog Timer enable bit, one bit is the

MCLR enable bit and one bit is for code protection (see

Register 9-1).

• Code Protection

• ID Locations

• In-Circuit Serial Programming™

• Clock Out

REGISTER 9-1:

CONFIGURATION WORD FOR PIC10F200/202/204/206^{(1), (2)}

—

MCLRE

CP

WDTE

—

bit 11

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 11-5 Unimplemented: Read as ‘0’

bit 4

bit 3

bit 2

MCLRE: GP3/MCLR Pin Function Select bit

1= GP3/MCLR pin function is MCLR

0= GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD

CP: Code Protection bit

1= Code protection off

0= Code protection on

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

bit 1-0 Reserved: Read as ‘0’

Note 1: Refer to the “PIC10F200/202/204/206 Memory Programming Specifications” (DS41228) to determine how

to access the Configuration Word. The Configuration Word is not user addressable during device

operation.

2: INTRC is the only oscillator mode offered on the PIC10F200/202/204/206.

DS41239D-page 41

PIC10F200/202/204/206

9.2

Oscillator Configurations

9.3

Reset

The device differentiates between various kinds of

Reset:

9.2.1

OSCILLATOR TYPES

The PIC10F200/202/204/206 devices are offered with

Internal Oscillator mode only.

• Power-on Reset (POR)

• MCLR Reset during normal operation

• MCLR Reset during Sleep

• INTOSC: Internal 4 MHz Oscillator

• WDT time-out Reset during normal operation

• WDT time-out Reset during Sleep

• Wake-up from Sleep on pin change

• Wake-up from Sleep on comparator change

9.2.2

INTERNAL 4 MHz OSCILLATOR

The internal oscillator provides a 4 MHz (nominal) system

clock (see Section 12.0 “Electrical Characteristics” for

information on variation over voltage and temperature).

In addition, a calibration instruction is programmed into

the last address of memory, which contains the calibra-

tion value for the internal oscillator. This location is

always uncode protected, regardless of the code-pro-

tect settings. This value is programmed as a MOVLW xx

instruction where xx is the calibration value and is

placed at the Reset vector. This will load the W register

with the calibration value upon Reset and the PC will

then roll over to the users program at address 0x000.

The user then has the option of writing the value to the

OSCCAL Register (05h) or ignoring it.

Some registers are not reset in any way, they are

unknown on POR and unchanged in any other Reset.

Most other registers are reset to “Reset state” on

Power-on Reset (POR), MCLR, WDT or Wake-up on

pin change Reset during normal operation. They are

not affected by a WDT Reset during Sleep or MCLR

Reset during Sleep, since these Resets are viewed as

resumption of normal operation. The exceptions to this

are TO, PD, GPWUF and CWUF bits. They are set or

cleared differently in different Reset situations. These

bits are used in software to determine the nature of

Reset. See Table 9-1 for a full description of Reset

states of all registers.

OSCCAL, when written to with the calibration value, will

“trim” the internal oscillator to remove process variation

from the oscillator frequency.

Note:

Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

TABLE 9-1:

RESET CONDITIONS FOR REGISTERS – PIC10F200/202/204/206

MCLR Reset, WDT Time-out,

Wake-up On Pin Change, Wake on

Comparator Change

Register

Address

Power-on Reset

(1)

W

—

qqqq qqqu

INDF

TMR0

PCL

00h

01h

02h

xxxx xxxx

1111 1111

uuuu uuuu

1111 1111

(2)

STATUS

03h

00-1 1xxx

q00q quuu

(3)

(2)

STATUS

qq0q quuu

FSR

04h

05h

06h

111x xxxx

1111 1110

---- xxxx

111u uuuu

uuuu uuuu

---- uuuu

OSCCAL

GPIO

(3)

CMCON

07h

—

1111 1111

---- 1111

uuuu uuuu

1111 1111

---- 1111

OPTION

TRISGPIO

—

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.

Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.

2: See Table 9-2 for Reset value for specific conditions.

3: PIC10F204/206 only.

DS41239D-page 42

PIC10F200/202/204/206

TABLE 9-2:

RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h

PCL Addr: 02h

Power-on Reset

00-1 1xxx

000u uuuu

0001 0uuu

0000 0uuu

0000 uuuu

1001 0uuu

0101 0uuu

1111 1111

MCLR Reset during normal operation

MCLR Reset during Sleep

WDT Reset during Sleep

WDT Reset normal operation

Wake-up from Sleep on pin change

Wake-up from Sleep on comparator change

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’.

The Power-on Reset circuit and the Device Reset

Timer (see Section 9.5 “Device Reset Timer (DRT)”)

circuit are closely related. On power-up, the Reset latch

is set and the DRT is reset. The DRT timer begins

counting once it detects MCLR to be high. After the

time-out period, which is typically 18 ms, it will reset the

Reset latch and thus end the on-chip Reset signal.

9.3.1

MCLR ENABLE

This Configuration bit, when unprogrammed (left in the

‘1’ state), enables the external MCLR function. When

programmed, the MCLR function is tied to the internal

VDD and the pin is assigned to be a I/O. See Figure 9-1.

FIGURE 9-1:

MCLR SELECT

A power-up example where MCLR is held low is shown

in Figure 9-3. VDD is allowed to rise and stabilize before

bringing MCLR high. The chip will actually come out of

Reset TDRT msec after MCLR goes high.

GPWU

In Figure 9-4, the on-chip Power-on Reset feature is

being used (MCLR and VDD are tied together or the pin

is programmed to be GP3). The VDD is stable before

the Start-up Timer times out and there is no problem in

getting a proper Reset. However, Figure 9-5 depicts a

problem situation where VDD rises too slowly. The time

between when the DRT senses that MCLR is high and

when MCLR and VDD actually reach their full value, is

too long. In this situation, when the Start-up Timer times

out, VDD has not reached the VDD (min) value and the

chip may not function correctly. For such situations, we

recommend that external RC circuits be used to

achieve longer POR delay times (Figure 9-4).

GP3/MCLR/VPP

Internal MCLR

MCLRE

9.4

Power-on Reset (POR)

The PIC10F200/202/204/206 devices incorporate an

on-chip Power-on Reset (POR) circuitry, which

provides an internal chip Reset for most power-up

situations.

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper oper-

ation. To take advantage of the internal POR, program

the GP3/MCLR/VPP pin as MCLR and tie through a

resistor to VDD, or program the pin as GP3. An internal

weak pull-up resistor is implemented using a transistor

(refer to Table 12-2 for the pull-up resistor ranges).

This will eliminate external RC components usually

needed to create a Power-on Reset. A maximum rise

time for VDD is specified. See Section 12.0 “Electrical

Characteristics” for details.

Note:

When the devices start normal operation

(exit the Reset condition), device operat-

ing parameters (voltage, frequency,

temperature, etc.) must be met to ensure

operation. If these conditions are not met,

the device must be held in Reset until the

operating conditions are met.

For additional information, refer to Application Notes

AN522 “Power-Up Considerations”, (DS00522) and

AN607 “Power-up Trouble Shooting”, (DS00607).

When the devices start normal operation (exit the

Reset condition), device operating parameters (volt-

age, frequency, temperature,...) must be met to ensure

operation. If these conditions are not met, the devices

must be held in Reset until the operating parameters

are met.

A simplified block diagram of the on-chip Power-on

Reset circuit is shown in Figure 9-2.

DS41239D-page 43

PIC10F200/202/204/206

FIGURE 9-2:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

VDD

Power-up

Detect

POR (Power-on Reset)

MCLR Reset

GP3/MCLR/VPP

S

R

Q

MCLRE

WDT Reset

WDT Time-out

Start-up Timer

CHIP Reset

(10 μs or 18 ms)

Pin Change

Sleep

Wake-up on pin change Reset

FIGURE 9-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

FIGURE 9-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE

TIME

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

DS41239D-page 44

PIC10F200/202/204/206

FIGURE 9-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

V1

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

Note:

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final

value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

DS41239D-page 45

PIC10F200/202/204/206

9.6.1

WDT PERIOD

9.5

Device Reset Timer (DRT)

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by

writing to the OPTION register. Thus, a time-out period

of a nominal 2.3 seconds can be realized. These peri-

ods vary with temperature, VDD and part-to-part

process variations (see DC specs).

On the PIC10F200/202/204/206 devices, the DRT runs

any time the device is powered up.

The DRT operates on an internal oscillator. The

processor is kept in Reset as long as the DRT is active.

The DRT delay allows VDD to rise above VDD min. and

for the oscillator to stabilize.

The on-chip DRT keeps the devices in a Reset

condition for approximately 18 ms after MCLR has

reached a logic high (VIH MCLR) level. Programming

GP3/MCLR/VPP as MCLR and using an external RC

network connected to the MCLR input is not required in

most cases. This allows savings in cost-sensitive and/

or space restricted applications, as well as allowing the

use of the GP3/MCLR/VPP pin as a general purpose

input.

Under worst-case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

9.6.2

WDT PROGRAMMING

CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from

timing out and generating a device Reset.

The Device Reset Time delays will vary from chip-to-

chip due to VDD, temperature and process variation.

See AC parameters for details.

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum Sleep time before a WDT wake-up Reset.

Reset sources are POR, MCLR, WDT time-out and

wake-up on pin change. See Section 9.9.2 “Wake-up

from Sleep”, Notes 1, 2 and 3.

TABLE 9-3:

DRT (DEVICE RESET TIMER

PERIOD)

Subsequent

POR Reset

Oscillator

Resets

INTOSC

18 ms (typical) 10 μs (typical)

9.6

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator, which does not require any external

components. This RC oscillator is separate from the

internal 4 MHz oscillator. This means that the WDT will

run even if the main processor clock has been stopped,

for example, by execution of a SLEEP instruction.

During normal operation or Sleep, a WDT Reset or

wake-up Reset, generates a device Reset.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer Reset.

The WDT can be permanently disabled by program-

ming the configuration WDTE as a ‘0’ (see Section 9.1

“Configuration Bits”). Refer to the PIC10F200/202/

204/206 Programming Specifications to determine how

to access the Configuration Word.

DS41239D-page 46

PIC10F200/202/204/206

FIGURE 9-6:

WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source

(Figure 6-5)

0

M

U

X

Postscaler

8-to-1 MUX

1

Watchdog

Time

PS<2:0>

PSA

WDT Enable

Configuration

(Figure 6-4)

To Timer0

Bit

0

1

MUX

PSA

WDT Time-out

TABLE 9-4:

Address

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

All Other

Resets

Name

Bit 7

Bit 6

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On

Reset

N/A

OPTION

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u= unchanged.

DS41239D-page 47

PIC10F200/202/204/206

9.7

Time-out Sequence, Power-down

and Wake-up from Sleep Status

Bits (TO, PD, GPWUF, CWUF)

The TO, PD, GPWUF and CWUF bits in the STATUS

register can be tested to determine if a Reset condition

has been caused by a power-up condition, a MCLR,

Watchdog Timer (WDT) Reset, wake-up on comparator

change or wake-up on pin change.

TABLE 9-5:

CWUF

TO, PD, GPWUF, CWUF STATUS AFTER RESET

GPWUF

TO

PD

Reset Caused By

WDT wake-up from Sleep

0

1

0

1

0

1

u

1

0

u

0

1

u

0

WDT time-out (not from Sleep)

MCLR wake-up from Sleep

Power-up

MCLR not during Sleep

Wake-up from Sleep on pin change

Wake-up from Sleep on comparator change

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.

Note 1: The TO, PD, GPWUF and CWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the

MCLR input does not change the TO, PD, GPWUF or CWUF Status bits.

FIGURE 9-8:

BROWN-OUT

9.8

Reset on Brown-out

PROTECTION CIRCUIT 2

A Brown-out Reset is a condition where device power

(VDD) dips below its minimum value, but not to zero,

and then recovers. The device should be reset in the

event of a brown-out.

VDD

R1

R2

To reset PIC10F200/202/204/206 devices when a

Brown-out Reset occurs, external brown-out protection

circuits may be built, as shown in Figure 9-7 and

Figure 9-8.

PIC10F20X

Q1

(2)

MCLR

(1)

40k

FIGURE 9-7:

BROWN-OUT

PROTECTION CIRCUIT 1

VDD

Note 1: This brown-out circuit is less expensive,

although less accurate. Transistor Q1 turns

off when VDD is below a certain level such

VDD

33k

that:

R1

R1 + R2

= 0.7V

VDD •

PIC10F20X

Q1

(2)

MCLR

10k

(1)

2: Pin must be confirmed as MCLR.

40k

Note 1: This circuit will activate Reset when VDD goes

below Vz + 0.7V (where Vz = Zener voltage).

2: Pin must be confirmed as MCLR.

DS41239D-page 48

PIC10F200/202/204/206

FIGURE 9-9:

BROWN-OUT

9.9.2

WAKE-UP FROM SLEEP

PROTECTION CIRCUIT 3

The device can wake-up from Sleep through one of

the following events:

VDD

1. An external Reset input on GP3/MCLR/VPP pin,

when configured as MCLR.

MCP809

VDD

Bypass

Capacitor

VSS

VDD

2. A Watchdog Timer time-out Reset (if WDT was

enabled).

RST

MCLR

3. A change on input pin GP0, GP1 or GP3 when

wake-up on change is enabled.

PIC10F20X

4. A comparator output change has occurred when

wake-up on comparator change is enabled.

Note:

This brown-out protection circuit employs

Microchip Technology’s MCP809 micro-

controller supervisor. There are 7 different

trip point selections to accommodate 5V to

3V systems.

These events cause a device Reset. The TO, PD

GPWUF and CWUF bits can be used to determine the

cause of device Reset. The TO bit is cleared if a WDT

time-out occurred (and caused wake-up). The PD bit,

which is set on power-up, is cleared when SLEEP is

invoked. The GPWUF bit indicates a change in state

while in Sleep at pins GP0, GP1 or GP3 (since the last

file or bit operation on GP port). The CWUF bit

indicates a change in the state while in Sleep of the

comparator output.

9.9

Power-Down Mode (Sleep)

A device may be powered down (Sleep) and later

powered up (wake-up from Sleep).

9.9.1

SLEEP

Note:

Caution: Right before entering Sleep,

read the input pins. When in Sleep, wake-

up occurs when the values at the pins

change from the state they were in at the

last reading. If a wake-up on change

occurs and the pins are not read before re-

entering Sleep, a wake-up will occur

immediately even if no pins change while

in Sleep mode.

The Power-Down mode is entered by executing a

SLEEPinstruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low or high-impedance).

Note:

A Reset generated by a WDT time-out

does not drive the MCLR pin low.

Note:

The WDT is cleared when the device

wakes from Sleep, regardless of the wake-

up source.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the GP3/

MCLR/VPP pin must be at a logic high level if MCLR is

enabled.

DS41239D-page 49

PIC10F200/202/204/206

FIGURE 9-10:

TYPICAL IN-CIRCUIT

SERIAL

PROGRAMMING™

CONNECTION

9.10 Program Verification/Code

Protection

If the code protection bit has not been programmed, the

on-chip program memory can be read out for

verification purposes.

To Normal

Connections

The first 64 locations and the last location (Reset

vector) can be read, regardless of the code protection

bit setting.

External

Connector

Signals

PIC10F20X

+5V

0V

VDD

9.11 ID Locations

VSS

VPP

MCLR/VPP

Four memory locations are designated as ID locations

where the user can store checksum or other code

identification numbers. These locations are not

accessible during normal execution, but are readable

and writable during Program/Verify.

GP1

GP0

CLK

Data I/O

Use only the lower 4 bits of the ID locations and always

VDD

program the upper 8 bits as ‘0’s.

To Normal

Connections

9.12 In-Circuit Serial Programming™

The PIC10F200/202/204/206 microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock and data,

and three other lines for power, ground and the

programming voltage. This allows customers to manu-

facture boards with unprogrammed devices and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware or a

custom firmware, to be programmed.

The devices are placed into a Program/Verify mode by

holding the GP1 and GP0 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

specification). GP1 becomes the programming clock

and GP0 becomes the programming data. Both GP1

and GP0 are Schmitt Trigger inputs in this mode.

After Reset, a 6-bit command is then supplied to the

device. Depending on the command, 16 bits of program

data are then supplied to or from the device, depending

if the command was a Load or a Read. For complete

details of serial programming, please refer to the

PIC10F200/202/204/206 Programming Specifications.

A typical In-Circuit Serial Programming connection is

shown in Figure 9-10.

DS41239D-page 50

PIC10F200/202/204/206

All instructions are executed within a single instruction

cycle, unless a conditional test is true or the program

counter is changed as a result of an instruction. In this

case, the execution takes two instruction cycles. One

instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 μs. If a conditional test is

true or the program counter is changed as a result of an

instruction, the instruction execution time is 2 μs.

10.0 INSTRUCTION SET SUMMARY

The PIC16 instruction set is highly orthogonal and is

comprised of three basic categories.

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Each PIC16 instruction is a 12-bit word divided into an

opcode, which specifies the instruction type and one or

more operands which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 10-1, while the various opcode

fields are summarized in Table 10-1.

Figure 10-1 shows the three general formats that the

instructions can have. All examples in the figure use

the following format to represent a hexadecimal

number:

0xhhh

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

where ‘h’ signifies a hexadecimal digit.

FIGURE 10-1:

GENERAL FORMAT FOR

INSTRUCTIONS

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’, the result is placed

in the file register specified in the instruction.

Byte-oriented file register operations

11

6

5

d

4

0

OPCODE

f (FILE #)

For bit-oriented instructions, ‘b’ represents a bit field

designator which selects the number of the bit affected

by the operation, while ‘f’ represents the number of the

file in which the bit is located.

d = 0for destination W

d = 1for destination f

f = 5-bit file register address

Bit-oriented file register operations

11 8 7

b (BIT #)

For literal and control operations, ‘k’ represents an

8 or 9-bit constant or literal value.

5

4

0

OPCODE

f (FILE #)

b = 3-bit address

f = 5-bit file register address

TABLE 10-1: OPCODE FIELD

DESCRIPTIONS

Literal and control operations (except GOTO)

11

Field

Description

8

7

0

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

OPCODE

k (literal)

Bit address within an 8-bit file register

Literal field, constant data or label

k = 8-bit immediate value

k

Literal and control operations – GOTOinstruction

11

x

Don’t care location (= 0or 1)

The assembler will generate code with x = 0. It is

the recommended form of use for compatibility with

all Microchip software tools.

9

8

0

OPCODE

k (literal)

d

Destination select;

k = 9-bit immediate value

d= 0(store result in W)

d= 1(store result in file register ‘f’)

Default is d = 1

label

TOS

PC

Label name

Top-of-Stack

Program Counter

Watchdog Timer counter

Time-out bit

WDT

TO

PD

Power-down bit

dest

Destination, either the W register or the specified

register file location

[

(

]

)

Options

Contents

→

Assigned to

Register bit field

In the set of

< >

∈

italics User defined term (font is courier)

DS41239D-page 51

PIC10F200/202/204/206

TABLE 10-2: INSTRUCTION SET SUMMARY

12-Bit Opcode

MSb LSb

Mnemonic,

Description

Operands

Status

Affected

Cycles

Notes

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

1

0001 11df ffff C, DC, Z 1, 2, 4

0001 01df ffff

0000 011f ffff

0000 0100 0000

0010 01df ffff

0000 11df ffff

0010 11df ffff

0010 10df ffff

0011 11df ffff

0001 00df ffff

0010 00df ffff

0000 001f ffff

0000 0000 0000

0011 01df ffff

0011 00df ffff

Z

None

Z

None

Z

2, 4

4

—

f, d

f

1

2, 4

1, 4

DECFSZ

INCF

1⁽²⁾

1

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

1⁽²⁾

1

Z

None

C

—

f, d

2, 4

C

0000 10df ffff C, DC, Z 1, 2, 4

0011 10df ffff

0001 10df ffff

None

Z

2, 4

Exclusive OR W with f

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

0100 bbbf ffff

None

2, 4

0101 bbbf ffff

0110 bbbf ffff

0111 bbbf ffff

1⁽²⁾

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

k

AND literal with W

Call Subroutine

1

2

1

2

1

2

1

1110 kkkk kkkk

1001 kkkk kkkk

0000 0000 0100 TO, PD

101k kkkk kkkk

1101 kkkk kkkk

1100 kkkk kkkk

0000 0000 0010

1000 kkkk kkkk

Z

None

1

3

Clear Watchdog Timer

Unconditional branch

Inclusive OR literal with W

Move literal to W

Load OPTION register

Return, place Literal in W

Go into Standby mode

Load TRIS register

k

—

k

—

f

k

None

Z

None

0000 0000 0011 TO, PD

0000 0000 0fff

1111 kkkk kkkk

None

Z

XORLW

Exclusive OR literal to W

Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for

GOTO. See Section 4.7 “Program Counter”.

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ‘0’.

3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state

latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be

cleared (if assigned to TMR0).

DS41239D-page 52

PIC10F200/202/204/206

ADDWF

Add W and f

BCF

Bit Clear f

Syntax:

[ label ] ADDWF f,d

Syntax:

[ label ] BCF f,b

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation:

(W) + (f) → (dest)

Operation:

0 → (f<b>)

Status Affected: C, DC, Z

Status Affected: None

Description:

Add the contents of the W register

Description:

Bit ‘b’ in register ‘f’ is cleared.

and register ‘f’. If ‘d’ is ‘0’, the result

is stored in the W register. If ‘d’ is

‘1’, the result is stored back in

register ‘f’.

ANDLW

AND literal with W

BSF

Bit Set f

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] BSF f,b

Operands:

Operation:

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

(W).AND. (k) → (W)

Operation:

1 → (f<b>)

Status Affected: Z

Status Affected: None

Description:

The contents of the W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC

Bit Test f, Skip if Clear

ANDWF

AND W with f

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

skip if (f<b>) = 0

Operation:

(W) .AND. (f) → (dest)

Status Affected: None

Status Affected: Z

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the

Description: The contents of the W register are

next instruction is skipped.

AND’ed with register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W register.

If ‘d’ is ‘1’, the result is stored back

in register ‘f’.

If bit ‘b’ is ‘0’, then the next instruc-

tion fetched during the current

instruction execution is discarded,

and a NOPis executed instead,

making this a two-cycle instruction.

DS41239D-page 53

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CLRW

Clear W

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRW

None

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

Operands:

0 ≤ f ≤ 31

0 ≤ b < 7

00h → (W);

1 → Z

Operation:

skip if (f<b>) = 1

Status Affected:

Description:

Z

Status Affected: None

The W register is cleared. Zero bit

(Z) is set.

Description:

If bit ‘b’ in register ‘f’ is ‘1’, then the

next instruction is skipped.

If bit ‘b’ is ‘1’, then the next instruc-

tion fetched during the current

instruction execution, is discarded

and a NOPis executed instead,

making this a two-cycle instruction.

CLRWDT

Syntax:

Clear Watchdog Timer

[ label ] CLRWDT

None

CALL

Subroutine Call

[ label ] CALL k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Operands:

Operation:

00h → WDT;

0 → WDT prescaler (if assigned);

(PC) + 1→ Top-of-Stack;

k → PC<7:0>;

1 → TO;

1 → PD

(STATUS<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected: TO, PD

Status Affected: None

Description:

The CLRWDTinstruction resets the

Description:

Subroutine call. First, return

WDT. It also resets the prescaler, if

the prescaler is assigned to the

WDT and not Timer0. Status bits

TO and PD are set.

address (PC + 1) is PUSHed onto

the stack. The eight-bit immediate

address is loaded into PC

bits <7:0>. The upper bits

PC<10:9> are loaded from

STATUS<6:5>, PC<8> is cleared.

CALLis a two-cycle instruction.

CLRF

Clear f

COMF

Complement f

Syntax:

[ label ] CLRF

0 ≤ f ≤ 31

f

Syntax:

Operands:

[ label ] COMF f,d

Operands:

Operation:

0 ≤ f ≤ 31

d ∈ [0,1]

00h → (f);

1 → Z

Operation:

(f) → (dest)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back in

register ‘f’.

DS41239D-page 54

PIC10F200/202/204/206

DECF

Decrement f

INCF

Increment f

Syntax:

Operands:

[ label ] DECF f,d

Syntax:

Operands:

[ label ] INCF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

(f) – 1 → (dest)

Operation:

(f) + 1 → (dest)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

INCFSZ

Syntax:

Increment f, Skip if 0

DECFSZ

Syntax:

Decrement f, Skip if 0

[ label ] INCFSZ f,d

[ label ] DECFSZ f,d

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

(f) + 1 → (dest), skip if result = 0

Operation:

(f) – 1 → d; skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘0’, then the next

instruction, which is already

fetched, is discarded and a NOPis

executed instead making it a

two-cycle instruction.

If the result is ‘0’, the next instruc-

tion, which is already fetched, is

discarded and a NOPis executed

instead making it a two-cycle

instruction.

IORLW

Inclusive OR literal with W

[ label ] IORLW k

0 ≤ k ≤ 255

GOTO

Unconditional Branch

[ label ] GOTO k

0 ≤ k ≤ 511

Syntax:

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

(W) .OR. (k) → (W)

Z

k → PC<8:0>;

STATUS<6:5> → PC<10:9>

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

Description: GOTOis an unconditional branch.

The 9-bit immediate value is

loaded into PC bits <8:0>. The

upper bits of PC are loaded from

STATUS<6:5>. GOTOis a two-

cycle instruction.

DS41239D-page 55

PIC10F200/202/204/206

IORWF

Inclusive OR W with f

MOVWF

Syntax:

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 31

Syntax:

[ label ] IORWF f,d

f

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

Operation:

(W) → (f)

Operation:

(W).OR. (f) → (dest)

Status Affected: None

Status Affected:

Description:

Z

Description:

Move data from the W register to

register ‘f’.

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’,

the result is placed back in register

‘f’.

MOVF

Move f

NOP

No Operation

[ label ] NOP

None

Syntax:

Operands:

[ label ] MOVF f,d

Syntax:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

Operation:

No operation

Operation:

(f) → (dest)

Status Affected: None

Status Affected:

Description:

Z

Description:

No operation.

The contents of register ‘f’ are

moved to destination ‘d’. If ‘d’ is ‘0’,

destination is the W register. If ‘d’

is ‘1’, the destination is file

register ‘f’. ‘d’ = 1is useful as a

test of a file register, since status

flag Z is affected.

MOVLW

Syntax:

Move literal to W

[ label ] MOVLW k

0 ≤ k ≤ 255

OPTION

Syntax:

Load OPTION Register

[ label ] OPTION

None

Operands:

Operation:

Operands:

Operation:

(W) → Option

k → (W)

Status Affected: None

Description: The content of the W register is

Description:

The eight-bit literal ‘k’ is loaded

into the W register. The “don’t

loaded into the OPTION register.

cares” will assembled as ‘0’s.

DS41239D-page 56

PIC10F200/202/204/206

RETLW

Return with literal in W

[ label ] RETLW k

0 ≤ k ≤ 255

SLEEP

Enter SLEEP Mode

Syntax:

[ label ]

SLEEP

Operands:

Operation:

Operands:

Operation:

None

k → (W);

TOS → PC

00h → WDT;

0 → WDT prescaler;

1 → TO;

Status Affected: None

0 → PD

Description:

The W register is loaded with the

Status Affected: TO, PD, RBWUF

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address). This

is a two-cycle instruction.

Description:

Time-out Status bit (TO) is set. The

Power-down Status bit (PD) is

cleared.

RBWUF is unaffected.

The WDT and its prescaler are

cleared.

The processor is put into Sleep

mode with the oscillator stopped.

See Section 9.9 “Power-Down

Mode (Sleep)” for more details.

RLF

Rotate Left f through Carry

SUBWF

Subtract W from f

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

[ label ] SUBWF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

See description below

C

Operation:

(f) – (W) → (dest)

Status Affected:

Description:

Status Affected: C, DC, Z

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is stored back in

register ‘f’.

Description:

Subtract (2’s complement method)

the W register from register ‘f’. If ‘d’

is ‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

register ‘f’

C

RRF

Rotate Right f through Carry

SWAPF

Syntax:

Swap Nibbles in f

Syntax:

Operands:

[ label ] RRF f,d

[ label ] SWAPF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

See description below

C

Operation:

(f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected:

Description:

Status Affected: None

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

register ‘f’

C

DS41239D-page 57

PIC10F200/202/204/206

TRIS

Load TRIS Register

XORWF

Syntax:

Exclusive OR W with f

Syntax:

[ label ] TRIS

f

[ label ] XORWF f,d

Operands:

Operation:

f = 6

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

(W) → TRIS register f

Status Affected: None

Operation:

(W) .XOR. (f) → (dest)

Description:

TRIS register ‘f’ (f = 6 or 7) is

loaded with the contents of the W

register

Status Affected:

Description:

Z

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

XORLW

Exclusive OR literal with W

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

Operation:

(W) .XOR. k → (W)

Z

Status Affected:

Description:

The contents of the W register are

XOR’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

DS41239D-page 58

PIC10F200/202/204/206

11.1 MPLAB Integrated Development

Environment Software

11.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

DS41239D-page 59

PIC10F200/202/204/206

11.2 MPASM Assembler

11.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

11.6 MPLAB SIM Software Simulator

11.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 family of microcontrollers and the

dsPIC30, dsPIC33 and PIC24 family of digital signal

controllers. These compilers provide powerful integra-

tion capabilities, superior code optimization and ease

of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

11.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS41239D-page 60

PIC10F200/202/204/206

11.7 MPLAB ICE 2000

High-Performance

11.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC micro-

controllers. Software control of the MPLAB ICE 2000

In-Circuit Emulator is advanced by the MPLAB Inte-

grated Development Environment, which allows edit-

ing, building, downloading and source debugging from

a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

11.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

11.8 MPLAB ICE 4000

High-Performance

In-Circuit Emulator

The MPLAB ICE 4000 In-Circuit Emulator is intended to

provide the product development engineer with a

complete microcontroller design tool set for high-end

PIC MCUs and dsPIC DSCs. Software control of the

MPLAB ICE 4000 In-Circuit Emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debugging from a single environment.

The MPLAB ICE 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanced emulator features include complex triggering

and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

DS41239D-page 61

PIC10F200/202/204/206

11.11 PICSTART Plus Development

Programmer

11.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

11.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer with an easy-to-use interface for pro-

gramming many of Microchip’s baseline, mid-range

and PIC18F families of Flash memory microcontrollers.

The PICkit 2 Starter Kit includes a prototyping develop-

ment board, twelve sequential lessons, software and

HI-TECH’s PICC™ Lite C compiler, and is designed to

help get up to speed quickly using PIC^®micro-

controllers. The kit provides everything needed to

program, evaluate and develop applications using

Microchip’s powerful, mid-range Flash memory family

of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS41239D-page 62

PIC10F200/202/204/206

12.0 ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Ambient temperature under bias..........................................................................................................-40°C to +125°C

Storage temperature ............................................................................................................................-65°C to +150°C

Voltage on VDD with respect to VSS ...............................................................................................................0 to +6.5V

Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V

Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾..................................................................................................................................800 mW

Max. current out of VSS pin ..................................................................................................................................80 mA

Max. current into VDD pin.....................................................................................................................................80 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................±20 mA

Max. output current sunk by any I/O pin ..............................................................................................................25 mA

Max. output current sourced by any I/O pin.........................................................................................................25 mA

Max. output current sourced by I/O port ..............................................................................................................75 mA

Max. output current sunk by I/O port ...................................................................................................................75 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

^†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

DS41239D-page 63

PIC10F200/202/204/206

FIGURE 12-1:

6.0

PIC10F200/202/204/206 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

5.5

5.0

4.5

4.0

3.5

VDD

(Volts)

3.0

2.5

2.0

0

4

10

20

25

Frequency (MHz)

DS41239D-page 64

PIC10F200/202/204/206

12.1 DC Characteristics: PIC10F200/202/204/206 (Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40×C ≤ TA ≤ +85°C (industrial)

DC CHARACTERISTICS

Param

Sym

No.

(1)

Characteristic

Min Typ

Max Units

Conditions

D001

D002

D003

VDD Supply Voltage

2.0

5.5

—

V

See Figure 12-1

Device in Sleep mode

(2)

VDR RAM Data Retention Voltage

1.5*

—

VPOR VDD Start Voltage

Vss

—

to ensure Power-on Reset

D004

D010

D020

D022

D023

D024

SVDD VDD Rise Rate

to ensure Power-on Reset)

(3)

0.05*

—

V/ms

IDD

Supply Current

—

175

0.63

275

1.1

μA

VDD = 2.0V

mA VDD = 5.0V

(4)

IPD

Power-down Current

—

0.1

0.35

1.2

2.4

μA

VDD = 2.0V

VDD = 5.0V

(5)

IWDT WDT Current

—

1.0

7

3

16

μA

VDD = 2.0V

VDD = 5.0V

(5)

ICMP Comparator Current

—

12

44

23

80

μA

VDD = 2.0V

VDD = 5.0V

(5), (6)

IVREF Internal Reference Current

—

85

175

115

195

μA

VDD = 2.0V.

VDD = 5.0V

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only

and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus

rate, internal code execution pattern and temperature also have an impact on the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode.

4: Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD

or VSS.

5: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled.

6: Measured with the comparator enabled.

DS41239D-page 65

PIC10F200/202/204/206

12.2 DC Characteristics: PIC10F200/202/204/206 (Extended)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40×C £ TA £ +125×C (extended)

DC CHARACTERISTICS

Param

Sym

No.

(1)

Characteristic

Supply Voltage

Min

Typ

Max

Units

Conditions

D001

D002

D003

VDD

VDR

2.0

1.5*

—

5.5

—

V

See Figure 12-1

(2)

RAM Data Retention Voltage

Device in Sleep mode

VPOR

VDD Start Voltage

Vss

—

to ensure Power-on Reset

D004

D010

D020

D022

D023

D024

SVDD

IDD

VDD Rise Rate

to ensure Power-on Reset

0.05*

—

V/ms

(3)

Supply Current

—

175

0.63

275

1.1

μA

mA

VDD = 2.0V

VDD = 5.0V

(4)

IPD

Power-down Current

—

0.1

0.35

9

15

μA

VDD = 2.0V

VDD = 5.0V

(5)

IWDT

ICMP

VREF

WDT Current

—

1.0

7

18

22

μA

VDD = 2.0V

VDD = 5.0V

(5)

Comparator Current

—

12

42

27

85

μA

VDD = 2.0V

VDD = 5.0

(5), (6)

Internal Reference Current

—

85

175

120

200

μA

VDD = 2.0V

VDD = 5.0V

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only

and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus

rate, internal code execution pattern and temperature also have an impact on the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode.

4: Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD

or VSS.

5: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled.

6: Measured with the Comparator enabled.

DS41239D-page 66

PIC10F200/202/204/206

12.3 DC Characteristics: PIC10F200/202/204/206 (Industrial, Extended)

Standard Operating Conditions (unless otherwise specified)

Operating temperature

-40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

DC CHARACTERISTICS

Operating voltage VDD range as described in DC specification

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

VIL Input Low Voltage

I/O ports:

D030

D030A

D031

with TTL buffer

Vss

—

0.8

V

For all 4.5 ≤ VDD ≤ 5.5V

0.15 VDD

0.2 VDD

Otherwise

with Schmitt Trigger

buffer

D032

MCLR, T0CKI

Vss

—

0.2 VDD

V

VIH Input High Voltage

I/O ports:

—

D040

D040A

D041

with TTL buffer

2.0

VDD

V

4.5 ≤ VDD ≤ 5.5V

Otherwise

0.25 VDD + 0.8

0.8VDD

with Schmitt Trigger

For entire VDD range

buffer

D042

D070

MCLR, T0CKI

0.8VDD

50

—

VDD

400

V

(3)

IPUR GPIO weak pull-up current

250

μA VDD = 5V, VPIN = VSS

(1, 2)

IIL

Input Leakage Current

D060

D061

I/O ports

—

±0.1

±0.7

± 1

± 5

μA Vss ≤ VPIN ≤ VDD, Pin at high-imped-

ance

(4)

GP3/MCLR

μA Vss ≤ VPIN ≤ VDD

Output Low Voltage

D080

I/O ports

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V, -40°C to

+85°C

D080A

IOL = 7.0 mA, VDD = 4.5V, -40°C to

+125°C

Output High Voltage

(2)

D090

I/O ports

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V, -40°C to

+85°C

D090A

IOH = -2.5 mA, VDD = 4.5V, -40°C to

+125°C

Capacitive Loading Specs on Output Pins

All I/O pins

D101

—

50*

pF

†

*

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

These parameters are for design guidance only and are not tested.

Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

2: Negative current is defined as coming out of the pin.

3: This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the

MCLR circuit is higher than the standard I/O logic.

DS41239D-page 67

PIC10F200/202/204/206

TABLE 12-1: COMPARATOR SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristics

Min Typ†

Max

Units

Comments

D300

D301

D302

VOS

Input Offset Voltage

—

0

± 5.0

—

± 10

VDD–1.5*

—

mV (VDD - 1.5)/2

VCM

Input Common Mode Voltage

Common Mode Rejection Ratio

Response Time

V

CMRR

55*

—

dB

D303* TRT

Falling

Rising

150

200

—

600

ns

μs

(Note 1)

1000

10*

D304* TMC2COV Comparator Mode Change to

Output Valid

D305

Vivrf

Internal Reference Voltage

0.55

0.6

0.65

V

2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ ± 125°C (extended)

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.

TABLE 12-2: PULL-UP RESISTOR RANGES

VDD (Volts)

GP0/GP1

Temperature (°C)

Min

Typ

Max

Units

2.0

-40

25

73K

82K

86K

15K

19K

23K

105K

113K

123K

132k

21K

186K

187K

190K

33K

Ω

85

125

-40

25

5.5

22K

34K

85

26k

35K

125

29K

35K

GP3

2.0

-40

25

63K

77K

82K

86K

16K

24K

26K

81K

93K

96k

96K

116K

119K

22K

Ω

85

125

-40

25

100K

20k

5.5

21K

25k

23K

85

28K

125

27K

29K

DS41239D-page 68

PIC10F200/202/204/206

12.4 Timing Parameter Symbology and Load Conditions – PIC10F200/202/204/206

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

T Time

Lowercase subscripts (pp) and their meanings:

pp

2

to

mc

osc

t0

MCLR

ck

cy

drt

io

CLKOUT

Cycle time

Device Reset Timer

I/O port

Oscillator

T0CKI

wdt

Watchdog Timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (high-impedance)

Low

Valid

L

High-impedance

FIGURE 12-2:

LOAD CONDITIONS – PIC10F200/202/204/206

Legend:

CL

CL = 50 pF for all pins

VSS

DS41239D-page 69

PIC10F200/202/204/206

TABLE 12-3: CALIBRATED INTERNAL RC FREQUENCIES – PIC10F200/202/204/206

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

-40°C ≤ TA ≤ +85°C (industrial),

-40°C ≤ TA ≤ +125°C (extended)

AC CHARACTERISTICS

Operating Voltage VDD range is described in

Section 12.1 “DC Characteristics”.

Param

Freq

Tolerance

Sym

Characteristic

Min Typ†

Max Units

Conditions

No.

F10

FOSC

Internal Calibrated

INTOSC

± 1%

± 2%

3.96 4.00

3.92 4.00

4.04 MHz VDD=3.5V @ 25°C

4.08 MHz 2.5V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +85°C (industrial)

4.20 MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

Frequency^(1,2)

± 5%

3.80 4.00

*

These parameters are characterized but not tested.

†

Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.

2: Under stable VDD conditions

FIGURE 12-3:

RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –

PIC10F200/202/204/206

VDD

MCLR

30

Internal

POR

32

DRT

(2)

Timeout

Internal

Reset

Watchdog

Timer

Reset

31

34

(1)

I/O pin

Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.

2: Runs on POR only.

DS41239D-page 70

PIC10F200/202/204/206

TABLE 12-4: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC10F200/202/204/206

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 12.1 “DC

Characteristics”

Param

Sym

No.

Characteristic

MCLR Pulse Width (low)

Min Typ⁽¹⁾Max Units

Conditions

30

31

32

TMC

2*

5*

—

μs

VDD = 5V, -40°C to +85°C

VDD = 5.0V

L

TWDT Watchdog Timer Time-out Period

(no prescaler)

10

16

29

31

ms VDD = 5.0V (Industrial)

ms VDD = 5.0V (Extended)

TDRT

Device Reset Timer Period (stan-

dard)

10

16

29

31

ms VDD = 5.0V (Industrial)

ms VDD = 5.0V (Extended)

34

TIOZ

I/O High-impedance from MCLR

low

—

2*

μs

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

FIGURE 12-4:

TIMER0 CLOCK TIMINGS – PIC10F200/202/204/206

T0CKI

40

41

42

TABLE 12-5: TIMER0 CLOCK REQUIREMENTS – PIC10F200/202/204/206

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in

Section 12.1 “DC Characteristics”.

Param

Sym

No.

Characteristic

Min

Typ⁽¹⁾Max Units

Conditions

40

41

42

Tt0H T0CKI High Pulse

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20*

10*

—

ns

Width

Tt0L T0CKI Low Pulse

Width

0.5 TCY + 20*

10*

Tt0P T0CKI Period

TCY + 40*

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

20 or

N

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

DS41239D-page 71

PIC10F200/202/204/206

NOTES:

DS41239D-page 72

PIC10F200/202/204/206

13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean -

3σ) respectively, where s is a standard deviation, over each temperature range.

FIGURE 13-1:

IDD vs. VDD OVER FOSC

XT Mode

1,400

1,200

1,000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

Maximum

4 MHz

Typical

600

400

200

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41239D-page 73

PIC10F200/202/204/206

FIGURE 13-2:

TYPICAL IPD vs. VDD (SLE_TE_yP_picM_aO_lDE, ALL PERIPHERALS DISABLED)

(Sleep Mode all Peripherals Disabled)

0.45

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-3:

MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

Maximum

(Sleep Mode all Peripherals Disabled)

18.0

Typical: Statistical Mean @25°C

16.0

14.0

12.0

10.0

8.0

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

6.0

4.0

Max. 85°C

2.0

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41239D-page 74

PIC10F200/202/204/206

FIGURE 13-4:

COMPARATOR IPD vs. VDD (COMPARATOR ENABLED)

80

60

40

20

0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

Maximum

Typical

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-5:

TYPICAL WDT IPD vs. VDD

9

8

7

6

5

4

3

2

1

0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41239D-page 75

PIC10F200/202/204/206

FIGURE 13-6:

MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE

Maximum

25.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

20.0

15.0

10.0

5.0

Max. 125°C

Max. 85°C

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-7:

WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER)

50

45

40

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

Max. 85°C

35

30

25

20

15

10

5

Typical. 25°C

Min. -40°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41239D-page 76

PIC10F200/202/204/206

FIGURE 13-8:

VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)

(VDD = 3V, -40×C TO 125×C)

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typical 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

FIGURE 13-9:

VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)

0.45

Typical: Statistical Mean @25°C

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

Typical: Statistical Mean @25×C

Maximum: Mean (Worst Case Temp) + 3σ

Maximum: Meas(-+403×C to 125×C)

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typ. 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

DS41239D-page 77

PIC10F200/202/204/206

FIGURE 13-10:

VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)

3.5

3.0

2.5

2.0

1.5

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

IOH (mA)

FIGURE 13-11:

VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)

5.5

5.0

4.5

4.0

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

3.5

3.0

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

-4.5

-5.0

IOH (mA)

DS41239D-page 78

PIC10F200/202/204/206

FIGURE 13-12:

TTL INPUT THRESHOLD VIN vs. VDD

(TTL Input, -40×C TO 125×C)

1.7

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

1.5

1.3

1.1

0.9

0.7

0.5

Max. -40°C

Typ. 25°C

Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-13:

SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD

(ST Input, -40×C TO 125×C)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VIH Max. 125°C

VIH Min. -40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

VIL Max. -40°C

VIL Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41239D-page 79

PIC10F200/202/204/206

FIGURE 13-14:

INTOSC (INTERNAL OSCILLATOR) POWERUP TIMES vs. VDD

Maximum

(Sleep Mode all Peripherals Disabled)

45

40

35

30

25

20

15

10

5

Max. 125°C

Max. 85°C

Typical 25°C

Max. -40°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41239D-page 80

PIC10F200/202/204/206

14.0 PACKAGING INFORMATION

14.1 Package Marking Information

6-Lead SOT-23A*

Example

XXNN

02JR

8-Lead PDIP

Example

PIC10F202

I/P 07Q

0520

XXXXXXXX

XXXXXNNN

YYWW

e

3

8-Lead 2x3 DFN*

Example

X X X

Y W W

N N

B E 0

6 1 0

1 7

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for product-specific information.

DS41239D-page 81

PIC10F200/202/204/206

TABLE 14-1: 8-LEAD 2x3 DFN (MC) TOP

MARKING

TABLE 14-2: 6-LEAD SOT-23 (OT)

PACKAGE TOP MARKING

Part Number

Marking

Part Number

Marking

PIC10F200-I/MC

PIC10F200-E/MC

PIC10F202-I/MC

PIC10F202-E/MC

PIC10F204-I/MC

PIC10F204-E/MC

PIC10F206-I/MC

PIC10F206-E/MC

BA0

BB0

BC0

BD0

BE0

BF0

BG0

BH0

PIC10F200-I/OT

PIC10F200-E/OT

PIC10F202-I/OT

PIC10F202-E/OT

PIC10F204-I/OT

PIC10F204-E/OT

PIC10F206-I/OT

PIC10F206-E/OT

00NN

02NN

04NN

06NN

Note:

NN

represents

the

alphanumeric

traceability code.

DS41239D-page 82

PIC10F200/202/204/206

6-Lead Plastic Small Outline Transistor (OT) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

b

4

N

E

E1

PIN 1 ID BY

LASER MARK

1

2

3

e

e1

D

c

A

φ

A2

L

A1

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

6

0.95 BSC

Outside Lead Pitch

Overall Height

e1

A

1.90 BSC

0.90

0.89

0.00

2.20

1.30

2.70

0.10

0.35

0°

–

1.45

1.30

0.15

3.20

1.80

3.10

0.60

0.80

30°

Molded Package Thickness

Standoff

A2

A1

E

Overall Width

Molded Package Width

Overall Length

Foot Length

E1

D

L

Footprint

L1

φ

Foot Angle

Lead Thickness

Lead Width

c

0.08

0.20

0.26

0.51

b

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-028B

DS41239D-page 83

PIC10F200/202/204/206

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

A1

c

e

eB

b1

b

Units

INCHES

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.348

.115

.008

.040

.014

–

.130

–

.310

.250

.365

.130

.010

.060

.018

–

.325

.280

.400

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-018B

DS41239D-page 84

PIC10F200/202/204/206

8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

e

D

b

N

L

K

E2

E

EXPOSED PAD

NOTE 1

2

1

2

D2

BOTTOM VIEW

TOP VIEW

A

NOTE 2

A3

A1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

0.50 BSC

0.90

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

D

0.02

Contact Thickness

Overall Length

Overall Width

0.20 REF

2.00 BSC

3.00 BSC

–

E

Exposed Pad Length

Exposed Pad Width

Contact Width

Contact Length

Contact-to-Exposed Pad

D2

E2

b

1.30

1.50

0.18

0.30

0.20

1.75

1.90

0.30

0.50

–

0.25

L

0.40

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Package is saw singulated.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-123B

DS41239D-page 85

PIC10F200/202/204/206

NOTES:

DS41239D-page 86

PIC10F200/202/204/206

APPENDIX A: REVISION HISTORY

Revision C (August 2006)

Added 8-Pin DFN Pin Diagram; Revised Table 1-1;

Reformated all Registers; Revised Section 4.8 and

added note; Section 5.3 (changed Figure reference to

Figure 5-1); Tables 6-1 and 7-1 (removed shading from

TRISGPIO (I/O Control Register); Sections 8.1-8.4

(changed Table reference to Table 12-2); Section 14.1

Revised and replaced Package Marking Information

and drawings, Added Tables 14-1 & 14-2, Added DFN

Package drawing.

Revision D (April 2007)

Revised section 12.1, 12.2, 12.3, Table 1-1, 12-1, 12-3,

12-4. Added Section 13.0. Replaced Package Draw-

ings (Rev. AP); Removed instances of PICmicro^®and

replaced it with PIC^®.

DS41239D-page 87

PIC10F200/202/204/206

NOTES:

DS41239D-page 88

PIC10F200/202/204/206

INDEX

Program Memory (PIC10F200/204) ........................... 15

Program Memory (PIC10F202/206) ........................... 16

Microchip Internet Web Site................................................ 91

MPLAB ASM30 Assembler, Linker, Librarian..................... 60

MPLAB ICD 2 In-Circuit Debugger..................................... 61

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator...................................................... 61

MPLAB ICE 4000 High-Performance Universal

In-Circuit Emulator...................................................... 61

MPLAB Integrated Development Environment Software.... 59

MPLAB PM3 Device Programmer ...................................... 61

MPLINK Object Linker/MPLIB Object Librarian.................. 60

A

Assembler

MPASM Assembler..................................................... 60

B

Block Diagram

On-Chip Reset Circuit................................................. 44

Timer0................................................................... 29, 33

TMR0/WDT Prescaler..................................... 32, 36, 38

Watchdog Timer.......................................................... 47

Brown-Out Protection Circuit .............................................. 48

C

O

C Compilers

Option Register................................................................... 20

OSCCAL Register............................................................... 21

Oscillator Configurations..................................................... 42

Oscillator Types

MPLAB C18 ................................................................ 60

MPLAB C30 ................................................................ 60

Carry ..................................................................................... 9

Clocking Scheme ................................................................ 13

Code Protection ............................................................ 41, 50

Comparator

HS............................................................................... 42

LP ............................................................................... 42

Comparator Module .................................................... 37

Configuration............................................................... 38

Interrupts..................................................................... 39

Operation .................................................................... 39

Reference ................................................................... 39

Configuration Bits................................................................ 41

Customer Change Notification Service ............................... 91

Customer Notification Service............................................. 91

Customer Support............................................................... 91

P

PIC10F200/202/204/206 Device Varieties............................ 7

PICSTART Plus Development Programmer....................... 62

POR

Device Reset Timer (DRT) ................................... 41, 46

PD............................................................................... 48

Power-on Reset (POR)............................................... 41

TO............................................................................... 48

Power-down Mode.............................................................. 49

Prescaler ...................................................................... 31, 35

Program Counter................................................................ 22

D

DC and AC Characteristics

Graphs and Tables ..................................................... 73

Development Support ......................................................... 59

Digit Carry............................................................................. 9

Q

Q cycles.............................................................................. 13

R

E

Reader Response............................................................... 92

Read-Modify-Write.............................................................. 26

Register File Map

PIC10F200/204 .......................................................... 17

PIC10F202/206 .......................................................... 17

Registers

Errata .................................................................................... 3

F

Family of Devices

PIC10F200/202/204/206............................................... 5

G

Special Function......................................................... 18

Reset .................................................................................. 41

Reset on Brown-Out ........................................................... 48

GPIO................................................................................... 25

I

S

I/O Interfacing ..................................................................... 25

I/O Ports.............................................................................. 25

I/O Programming Considerations........................................ 26

ID Locations.................................................................. 41, 50

INDF.................................................................................... 23

Indirect Data Addressing..................................................... 23

Instruction Cycle ................................................................. 13

Instruction Flow/Pipelining .................................................. 13

Instruction Set Summary..................................................... 52

Internet Address.................................................................. 91

Sleep ............................................................................ 41, 49

Software Simulator (MPLAB SIM) ...................................... 60

Special Features of the CPU .............................................. 41

Special Function Registers................................................. 18

Stack................................................................................... 22

Status Register ............................................................... 9, 19

T

Timer0

Timer0 .................................................................. 29, 33

Timer0 (TMR0) Module ........................................ 29, 33

TMR0 with External Clock .................................... 30, 34

Timing Parameter Symbology and Load Conditions .......... 69

TRIS Registers ................................................................... 25

L

Loading of PC ..................................................................... 22

M

Memory Organization.......................................................... 15

Data Memory .............................................................. 16

DS41239D-page 89

PIC10F200/202/204/206

W

Wake-up from Sleep ...........................................................49

Watchdog Timer (WDT) ................................................ 41, 46

Period..........................................................................46

Programming Considerations .....................................46

WWW Address....................................................................91

WWW, On-Line Support........................................................3

Z

Zero bit..................................................................................9

DS41239D-page 90

PIC10F200/202/204/206

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS41239D-page 91

PIC10F200/202/204/206

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC10F200/202/204/206

DS41239D

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41239D-page 92

PIC10F200/202/204/206

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

b)

PIC10F200-I/P = Industrial temp., PDIP

package (Pb-free)

PIC10F202T-E/OT = Extended temp., SOT-23

package (Pb-free), Tape and Reel

c)

PIC10F202-E/MC = Extended temp., DFN-

package (Pb-free)

Device:

PIC10F200

PIC10F202

PIC10F204

PIC10F206

PIC10F200T (Tape & Reel)

PIC10F202T (Tape & Reel)

PIC10F204T (Tape & Reel)

PIC10F206T (Tape & Reel)

Temperature

Range:

I

E

=

-40°C to +85°C (Industrial)

-40°C to +125°C (Extended)

Package:

Pattern:

P

=

300 mil PDIP (Pb-free)

SOT-23, 6-LD (Pb-free)

DFN, 8-LD 2x3 (Pb-free)

OT

MC

Special Requirements

DS41239D-page 93

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS41239D-page 94


型号：	PIC10F204-E/MC
厂家：	MICROCHIP
描述：	6-Pin, 8-Bit Flash Microcontrollers 6引脚8位闪存微控制器闪存微控制器和处理器外围集成电路时钟
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PIC10F204-E/MC [MICROCHIP]

相关型号：

PIC10F204-E/OT

PIC10F204-E/OTG

PIC10F204-E/P

PIC10F204-I/MC

PIC10F204-I/OT

PIC10F204-I/OTG

PIC10F204-I/P

PIC10F204T

PIC10F204T-E/MC

PIC10F204T-E/OT

PIC10F204T-E/OTG

PIC10F204T-E/OTVAO